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ath79: fix eth pll for ar913x
[openwrt/openwrt.git]
/
target
/
linux
/
ath79
/
dts
/
ar9132.dtsi
diff --git
a/target/linux/ath79/dts/ar9132.dtsi
b/target/linux/ath79/dts/ar9132.dtsi
index f1822e8775cedfa3368b4edb21da73738b062263..01572c022e03d2042735f8c87565df4ca13de566 100644
(file)
--- a/
target/linux/ath79/dts/ar9132.dtsi
+++ b/
target/linux/ath79/dts/ar9132.dtsi
@@
-93,7
+93,7
@@
pll: pll-controller@18050000 {
compatible = "qca,ar9132-pll",
pll: pll-controller@18050000 {
compatible = "qca,ar9132-pll",
- "qca,ar9130-pll";
+ "qca,ar9130-pll"
, "syscon"
;
reg = <0x18050000 0x20>;
clock-names = "ref";
reg = <0x18050000 0x20>;
clock-names = "ref";
@@
-162,7
+162,7
@@
#size-cells = <0>;
};
#size-cells = <0>;
};
- wmac:
g
mac@180c0000 {
+ wmac:
w
mac@180c0000 {
compatible = "qca,ar9130-wmac";
reg = <0x180c0000 0x230000>;
compatible = "qca,ar9130-wmac";
reg = <0x180c0000 0x230000>;
@@
-191,6
+191,6
@@
pll-data = <0x1a000000 0x13000a44 0x00441099>;
pll-reg = <0x4 0x10 17>;
pll-handle = <&pll>;
pll-data = <0x1a000000 0x13000a44 0x00441099>;
pll-reg = <0x4 0x10 17>;
pll-handle = <&pll>;
- resets = <&rst
8>, <&rst
9>;
- reset-names = "
phy", "
mac";
+ resets = <&rst 9>;
+ reset-names = "mac";
};
};