brcm43xx: update SSB driver * files/ now contains the wireless-dev tree version ...
authorPeter Denison <openwrt@marshadder.org>
Thu, 21 Jun 2007 20:10:50 +0000 (20:10 +0000)
committerPeter Denison <openwrt@marshadder.org>
Thu, 21 Jun 2007 20:10:50 +0000 (20:10 +0000)
SVN-Revision: 7691

23 files changed:
target/linux/brcm47xx-2.6/files/drivers/ssb/Kconfig
target/linux/brcm47xx-2.6/files/drivers/ssb/Makefile
target/linux/brcm47xx-2.6/files/drivers/ssb/core.c [deleted file]
target/linux/brcm47xx-2.6/files/drivers/ssb/driver_chipcommon.c [new file with mode: 0644]
target/linux/brcm47xx-2.6/files/drivers/ssb/driver_chipcommon/chipcommon.c [deleted file]
target/linux/brcm47xx-2.6/files/drivers/ssb/driver_mips/mips.c [deleted file]
target/linux/brcm47xx-2.6/files/drivers/ssb/driver_mipscore.c [new file with mode: 0644]
target/linux/brcm47xx-2.6/files/drivers/ssb/driver_pci/pcicore.c [deleted file]
target/linux/brcm47xx-2.6/files/drivers/ssb/driver_pcicore.c [new file with mode: 0644]
target/linux/brcm47xx-2.6/files/drivers/ssb/main.c [new file with mode: 0644]
target/linux/brcm47xx-2.6/files/drivers/ssb/pci.c
target/linux/brcm47xx-2.6/files/drivers/ssb/pcihost_wrapper.c [new file with mode: 0644]
target/linux/brcm47xx-2.6/files/drivers/ssb/scan.c
target/linux/brcm47xx-2.6/files/drivers/ssb/ssb_private.h
target/linux/brcm47xx-2.6/files/drivers/usb/host/ohci-ssb.c [new file with mode: 0644]
target/linux/brcm47xx-2.6/files/include/linux/ssb/ssb.h
target/linux/brcm47xx-2.6/files/include/linux/ssb/ssb_driver_chipcommon.h
target/linux/brcm47xx-2.6/files/include/linux/ssb/ssb_driver_extif.h
target/linux/brcm47xx-2.6/files/include/linux/ssb/ssb_driver_mips.h
target/linux/brcm47xx-2.6/files/include/linux/ssb/ssb_regs.h
target/linux/brcm47xx-2.6/patches/200-b44_ssb_fixup.patch [new file with mode: 0644]
target/linux/brcm47xx-2.6/patches/205-ssb_integrate.patch [new file with mode: 0644]
target/linux/brcm47xx-2.6/patches/210-ssb_merge.patch [new file with mode: 0644]

index 09330df..03c4945 100644 (file)
@@ -71,4 +71,23 @@ config SSB_PCICORE_HOSTMODE
        help
          PCIcore hostmode operation (external PCI bus).
 
+config SSB_DRIVER_MIPS
+       bool "SSB Broadcom MIPS core driver"
+       depends on SSB && MIPS
+       select SSB_SERIAL
+       help
+         Driver for the Sonics Silicon Backplane attached
+         Broadcom MIPS core.
+
+         If unsure, say N
+
+config SSB_DRIVER_EXTIF
+       bool "SSB Broadcom EXTIF core driver"
+       depends on SSB_DRIVER_MIPS
+       help
+         Driver for the Sonics Silicon Backplane attached
+         Broadcom EXTIF core.
+
+         If unsure, say N
+
 endmenu
index 9f85d22..9a2b379 100644 (file)
@@ -1,14 +1,11 @@
-ssb-driver-chipcommon-y                                := driver_chipcommon/chipcommon.o
-ssb-driver-mips-$(CONFIG_BCM947XX)     := driver_mips/mips.o
-ssb-driver-pci-$(CONFIG_SSB_DRIVER_PCICORE)    := driver_pci/pcicore.o
+ssb-builtin-drivers-y                                  += driver_chipcommon.o
+ssb-builtin-drivers-$(CONFIG_SSB_DRIVER_MIPS)          += driver_mipscore.o
+ssb-builtin-drivers-$(CONFIG_SSB_DRIVER_PCICORE)       += driver_pcicore.o
 
-ssb-$(CONFIG_SSB_PCIHOST)                      += pci.o
-ssb-$(CONFIG_SSB_PCMCIAHOST)                   += pcmcia.o
+ssb-hostsupport-$(CONFIG_SSB_PCIHOST)                  += pci.o pcihost_wrapper.o
+ssb-hostsupport-$(CONFIG_SSB_PCMCIAHOST)               += pcmcia.o
 
 obj-$(CONFIG_SSB) += ssb.o
 
-ssb-objs       := core.o scan.o \
-                  $(ssb-y) $(ssb-m) \
-                  $(ssb-driver-chipcommon-y) \
-                  $(ssb-driver-mips-y) \
-                  $(ssb-driver-pci-y)
+ssb-objs       := main.o scan.o \
+                  $(ssb-hostsupport-y) $(ssb-builtin-drivers-y)
diff --git a/target/linux/brcm47xx-2.6/files/drivers/ssb/core.c b/target/linux/brcm47xx-2.6/files/drivers/ssb/core.c
deleted file mode 100644 (file)
index 2ee13d2..0000000
+++ /dev/null
@@ -1,805 +0,0 @@
-/*
- * Sonics Silicon Backplane
- * Subsystem core
- *
- * Copyright 2005, Broadcom Corporation
- * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
- *
- * Licensed under the GNU/GPL. See COPYING for details.
- */
-
-#include "ssb_private.h"
-
-#include <linux/delay.h>
-#include <linux/ssb/ssb.h>
-#include <linux/ssb/ssb_regs.h>
-
-#ifdef CONFIG_SSB_PCIHOST
-# include <linux/pci.h>
-#endif
-
-#ifdef CONFIG_SSB_PCMCIAHOST
-# include <pcmcia/cs_types.h>
-# include <pcmcia/cs.h>
-# include <pcmcia/cistpl.h>
-# include <pcmcia/ds.h>
-#endif
-
-
-MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
-MODULE_LICENSE("GPL");
-
-
-static LIST_HEAD(attach_queue);
-static LIST_HEAD(buses);
-static int nr_buses;
-static DEFINE_MUTEX(buses_mutex);
-
-#define ssb_buses_lock() do {                  \
-       if (!is_early_boot())                   \
-               mutex_lock(&buses_mutex);       \
-                       } while (0)
-
-#define ssb_buses_unlock() do {                        \
-       if (!is_early_boot())                   \
-               mutex_unlock(&buses_mutex);     \
-                       } while (0)
-
-
-static struct ssb_device * ssb_device_get(struct ssb_device *dev)
-{
-       if (dev)
-               get_device(&dev->dev);
-       return dev;
-}
-
-static void ssb_device_put(struct ssb_device *dev)
-{
-       if (dev)
-               put_device(&dev->dev);
-}
-
-static void ssb_bus_resume(struct ssb_bus *bus)
-{
-printk("SSB BUS RESUME\n");
-       ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
-       ssb_chipco_resume(&bus->chipco);
-}
-
-static int ssb_device_resume(struct device *dev)
-{
-       struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
-       struct ssb_driver *ssb_drv;
-       struct ssb_bus *bus;
-       int err = 0;
-
-printk("SSB DEV RESUME\n");
-       bus = ssb_dev->bus;
-       if (bus->suspend_cnt == bus->nr_devices)
-               ssb_bus_resume(bus);
-       bus->suspend_cnt--;
-       if (dev->driver) {
-               ssb_drv = drv_to_ssb_drv(dev->driver);
-               if (ssb_drv && ssb_drv->resume)
-                       err = ssb_drv->resume(ssb_dev);
-               if (err)
-                       goto out;
-       }
-out:
-       return err;
-}
-
-static void ssb_bus_suspend(struct ssb_bus *bus, pm_message_t state)
-{
-printk("SSB BUS SUSPEND\n");
-//     ssb_chipco_suspend(&bus->chipco, state);
-//     ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
-}
-
-static int ssb_device_suspend(struct device *dev, pm_message_t state)
-{
-       struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
-       struct ssb_driver *ssb_drv;
-       struct ssb_bus *bus;
-       int err = 0;
-
-printk("SSB DEV SUSPEND\n");
-       if (dev->driver) {
-               ssb_drv = drv_to_ssb_drv(dev->driver);
-               if (ssb_drv && ssb_drv->suspend)
-                       err = ssb_drv->suspend(ssb_dev, state);
-               if (err)
-                       goto out;
-       }
-
-       bus = ssb_dev->bus;
-       bus->suspend_cnt++;
-       if (bus->suspend_cnt == bus->nr_devices) {
-               /* All devices suspended. Shutdown the bus. */
-               ssb_bus_suspend(bus, state);
-       }
-
-out:
-       return err;
-}
-
-static void ssb_device_shutdown(struct device *dev)
-{
-       struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
-       struct ssb_driver *ssb_drv;
-
-       if (!dev->driver)
-               return;
-       ssb_drv = drv_to_ssb_drv(dev->driver);
-       if (ssb_drv && ssb_drv->shutdown)
-               ssb_drv->shutdown(ssb_dev);
-}
-
-static int ssb_device_remove(struct device *dev)
-{
-       struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
-       struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
-
-       if (ssb_drv && ssb_drv->remove)
-               ssb_drv->remove(ssb_dev);
-       ssb_device_put(ssb_dev);
-
-       return 0;
-}
-
-static int ssb_device_probe(struct device *dev)
-{
-       struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
-       struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
-       int err = 0;
-
-       ssb_device_get(ssb_dev);
-       if (ssb_drv && ssb_drv->probe)
-               err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
-       if (err)
-               ssb_device_put(ssb_dev);
-
-       return err;
-}
-
-static int ssb_match_devid(const struct ssb_device_id *tabid,
-                          const struct ssb_device_id *devid)
-{
-       if ((tabid->vendor != devid->vendor) &&
-           tabid->vendor != SSB_ANY_VENDOR)
-               return 0;
-       if ((tabid->coreid != devid->coreid) &&
-           tabid->coreid != SSB_ANY_ID)
-               return 0;
-       if ((tabid->revision != devid->revision) &&
-           tabid->revision != SSB_ANY_REV)
-               return 0;
-       return 1;
-}
-
-static int ssb_bus_match(struct device *dev, struct device_driver *drv)
-{
-       struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
-       struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
-       const struct ssb_device_id *id;
-
-       for (id = ssb_drv->id_table;
-            id->vendor || id->coreid || id->revision;
-            id++) {
-               if (ssb_match_devid(id, &ssb_dev->id))
-                       return 1; /* found */
-       }
-
-       return 0;
-}
-
-struct bus_type ssb_bustype = {
-       .name           = NULL, /* Intentionally NULL to indicate early boot */
-       .match          = ssb_bus_match,
-       .probe          = ssb_device_probe,
-       .remove         = ssb_device_remove,
-       .shutdown       = ssb_device_shutdown,
-       .suspend        = ssb_device_suspend,
-       .resume         = ssb_device_resume,
-};
-
-#define is_early_boot()                (ssb_bustype.name == NULL)
-
-void ssb_bus_unregister(struct ssb_bus *bus)
-{
-       struct ssb_device *dev;
-       int i;
-
-       ssb_buses_lock();
-       for (i = bus->nr_devices - 1; i >= 0; i--) {
-               dev = &(bus->devices[i]);
-               device_unregister(&dev->dev);
-       }
-       list_del(&bus->list);
-       ssb_buses_unlock();
-
-       ssb_iounmap(bus);
-}
-EXPORT_SYMBOL(ssb_bus_unregister);
-
-static void ssb_release_dev(struct device *dev)
-{
-       /* Nothing, devices are allocated together with struct ssb_bus. */
-}
-
-/* Needs ssb_buses_lock() */
-static int ssb_attach_queued_buses(void)
-{
-       struct ssb_bus *bus, *n;
-       struct ssb_device *dev;
-       int i, err;
-
-       list_for_each_entry_safe(bus, n, &attach_queue, list) {
-               ssb_pcicore_init(&bus->pcicore);
-               for (i = 0; i < bus->nr_devices; i++) {
-                       dev = &(bus->devices[i]);
-
-                       dev->dev.release = ssb_release_dev;
-                       err = device_register(&dev->dev);
-                       if (err) {
-                               ssb_printk(KERN_ERR PFX
-                                          "Could not register %s\n",
-                                          dev->dev.bus_id);
-                       }
-               }
-               list_move_tail(&bus->list, &buses);
-       }
-       return 0;
-}
-
-static void ssb_get_boardtype(struct ssb_bus *bus)
-{//FIXME for pcmcia?
-       if (bus->bustype != SSB_BUSTYPE_PCI) {
-               /* Must set board_vendor, board_type and board_rev
-                * before calling ssb_bus_*_register() */
-               assert(bus->board_vendor && bus->board_type);
-               return;
-       }
-       ssb_pci_get_boardtype(bus);
-}
-
-static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
-{
-       struct ssb_bus *bus = dev->bus;
-
-       offset += dev->core_index * SSB_CORE_SIZE;
-       return readw(bus->mmio + offset);
-}
-
-static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset)
-{
-       struct ssb_bus *bus = dev->bus;
-
-       offset += dev->core_index * SSB_CORE_SIZE;
-       return readl(bus->mmio + offset);
-}
-
-static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
-{
-       struct ssb_bus *bus = dev->bus;
-
-       offset += dev->core_index * SSB_CORE_SIZE;
-       writew(value, bus->mmio + offset);
-}
-
-static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
-{
-       struct ssb_bus *bus = dev->bus;
-
-       offset += dev->core_index * SSB_CORE_SIZE;
-       writel(value, bus->mmio + offset);
-}
-
-static const struct ssb_bus_ops ssb_ssb_ops = {
-       .read16         = ssb_ssb_read16,
-       .read32         = ssb_ssb_read32,
-       .write16        = ssb_ssb_write16,
-       .write32        = ssb_ssb_write32,
-};
-
-static int ssb_bus_register(struct ssb_bus *bus,
-                           unsigned long baseaddr)
-{
-       int err;
-
-       ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on ");
-       switch (bus->bustype) {
-       case SSB_BUSTYPE_SSB:
-               ssb_printk("address 0x%08lX\n", baseaddr);
-               break;
-       case SSB_BUSTYPE_PCI:
-#ifdef CONFIG_SSB_PCIHOST
-               ssb_printk("PCI device %s\n", bus->host_pci->dev.bus_id);
-#endif
-               break;
-       case SSB_BUSTYPE_PCMCIA:
-#ifdef CONFIG_SSB_PCMCIAHOST
-               ssb_printk("PCMCIA device %s\n", bus->host_pcmcia->devname);
-#endif
-               break;
-       }
-
-       spin_lock_init(&bus->bar_lock);
-       INIT_LIST_HEAD(&bus->list);
-
-       ssb_get_boardtype(bus);
-       /* Powerup the bus */
-       err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
-       if (err)
-               goto out;
-       ssb_buses_lock();
-       bus->busnumber = nr_buses;
-       /* Scan for devices (cores) */
-       err = ssb_bus_scan(bus, baseaddr);
-       if (err)
-               goto err_disable_xtal;
-
-       /* Init PCI-host device (if any) */
-       err = ssb_pci_init(bus);
-       if (err)
-               goto err_unmap;
-       /* Init PCMCIA-host device (if any) */
-       err = ssb_pcmcia_init(bus);
-       if (err)
-               goto err_unmap;
-
-       /* Initialize basic system devices (if available) */
-       ssb_chipcommon_init(&bus->chipco);
-       ssb_mipscore_init(&bus->mipscore);
-
-       /* Queue it for attach */
-       list_add_tail(&bus->list, &attach_queue);
-       if (!is_early_boot()) {
-               /* This is not early boot, so we must attach the bus now */
-               err = ssb_attach_queued_buses();
-               if (err)
-                       goto err_dequeue;
-       }
-       nr_buses++;
-       ssb_buses_unlock();
-
-out:
-       return err;
-
-err_dequeue:
-       list_del(&bus->list);
-err_unmap:
-       ssb_iounmap(bus);
-err_disable_xtal:
-       ssb_buses_unlock();
-       ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
-       goto out;
-}
-
-#ifdef CONFIG_SSB_PCIHOST
-int ssb_bus_pcibus_register(struct ssb_bus *bus,
-                           struct pci_dev *host_pci)
-{
-       int err;
-
-       bus->bustype = SSB_BUSTYPE_PCI;
-       bus->host_pci = host_pci;
-       bus->ops = &ssb_pci_ops;
-
-       err = ssb_bus_register(bus, 0);
-
-       return err;
-}
-EXPORT_SYMBOL(ssb_bus_pcibus_register);
-#endif /* CONFIG_SSB_PCIHOST */
-
-#ifdef CONFIG_SSB_PCMCIAHOST
-int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
-                              struct pcmcia_device *pcmcia_dev,
-                              unsigned long baseaddr,
-                              void (*fill_sprom)(struct ssb_sprom *sprom))
-{
-       int err;
-
-       bus->bustype = SSB_BUSTYPE_PCMCIA;
-       bus->host_pcmcia = pcmcia_dev;
-       bus->ops = &ssb_pcmcia_ops;
-       fill_sprom(&bus->sprom);
-
-       err = ssb_bus_register(bus, baseaddr);
-
-       return err;
-}
-EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
-#endif /* CONFIG_SSB_PCMCIAHOST */
-
-int ssb_bus_ssbbus_register(struct ssb_bus *bus,
-                           unsigned long baseaddr,
-                           void (*fill_sprom)(struct ssb_sprom *sprom))
-{
-       int err;
-
-       bus->bustype = SSB_BUSTYPE_SSB;
-       bus->ops = &ssb_ssb_ops;
-       fill_sprom(&bus->sprom);
-       err = ssb_bus_register(bus, baseaddr);
-
-       return err;
-}
-
-int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
-{
-       drv->drv.name = drv->name;
-       drv->drv.bus = &ssb_bustype;
-       drv->drv.owner = owner;
-
-       return driver_register(&drv->drv);
-}
-EXPORT_SYMBOL(__ssb_driver_register);
-
-void ssb_driver_unregister(struct ssb_driver *drv)
-{
-       driver_unregister(&drv->drv);
-}
-EXPORT_SYMBOL(ssb_driver_unregister);
-
-void ssb_set_devtypedata(struct ssb_device *dev, void *data)
-{
-       struct ssb_bus *bus = dev->bus;
-       struct ssb_device *ent;
-       int i;
-
-       for (i = 0; i < bus->nr_devices; i++) {
-               ent = &(bus->devices[i]);
-               if (ent->id.vendor != dev->id.vendor)
-                       continue;
-               if (ent->id.coreid != dev->id.coreid)
-                       continue;
-
-               ent->devtypedata = data;
-       }
-}
-EXPORT_SYMBOL(ssb_set_devtypedata);
-
-static u32 clkfactor_f6_resolve(u32 v)
-{
-       /* map the magic values */
-       switch (v) {
-       case SSB_CHIPCO_CLK_F6_2:
-               return 2;
-       case SSB_CHIPCO_CLK_F6_3:
-               return 3;
-       case SSB_CHIPCO_CLK_F6_4:
-               return 4;
-       case SSB_CHIPCO_CLK_F6_5:
-               return 5;
-       case SSB_CHIPCO_CLK_F6_6:
-               return 6;
-       case SSB_CHIPCO_CLK_F6_7:
-               return 7;
-       }
-       return 0;
-}
-
-/* Calculate the speed the backplane would run at a given set of clockcontrol values */
-u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
-{
-       u32 n1, n2, clock, m1, m2, m3, mc;
-
-       n1 = (n & SSB_CHIPCO_CLK_N1);
-       n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
-
-       switch (plltype) {
-       case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
-               if (m & SSB_CHIPCO_CLK_T6_MMASK)
-                       return SSB_CHIPCO_CLK_T6_M0;
-               return SSB_CHIPCO_CLK_T6_M1;
-       case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
-       case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
-       case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
-       case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
-               n1 = clkfactor_f6_resolve(n1);
-               n2 += SSB_CHIPCO_CLK_F5_BIAS;
-               break;
-       case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
-               n1 += SSB_CHIPCO_CLK_T2_BIAS;
-               n2 += SSB_CHIPCO_CLK_T2_BIAS;
-               assert((n1 >= 2) && (n1 <= 7));
-               assert((n2 >= 5) && (n2 <= 23));
-               break;
-       case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
-               return 100000000;
-       default:
-               assert(0);
-       }
-
-       switch (plltype) {
-       case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
-       case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
-               clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
-               break;
-       default:
-               clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
-       }
-       if (!clock)
-               return 0;
-
-       m1 = (m & SSB_CHIPCO_CLK_M1);
-       m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
-       m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
-       mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
-
-       switch (plltype) {
-       case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
-       case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
-       case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
-       case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
-               m1 = clkfactor_f6_resolve(m1);
-               if ((plltype == SSB_PLLTYPE_1) ||
-                   (plltype == SSB_PLLTYPE_3))
-                       m2 += SSB_CHIPCO_CLK_F5_BIAS;
-               else
-                       m2 = clkfactor_f6_resolve(m2);
-               m3 = clkfactor_f6_resolve(m3);
-
-               switch (mc) {
-               case SSB_CHIPCO_CLK_MC_BYPASS:
-                       return clock;
-               case SSB_CHIPCO_CLK_MC_M1:
-                       return (clock / m1);
-               case SSB_CHIPCO_CLK_MC_M1M2:
-                       return (clock / (m1 * m2));
-               case SSB_CHIPCO_CLK_MC_M1M2M3:
-                       return (clock / (m1 * m2 * m3));
-               case SSB_CHIPCO_CLK_MC_M1M3:
-                       return (clock / (m1 * m3));
-               }
-               return 0;
-       case SSB_PLLTYPE_2:
-               m1 += SSB_CHIPCO_CLK_T2_BIAS;
-               m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
-               m3 += SSB_CHIPCO_CLK_T2_BIAS;
-               assert((m1 >= 2) && (m1 <= 7));
-               assert((m2 >= 3) && (m2 <= 10));
-               assert((m3 >= 2) && (m3 <= 7));
-
-               if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
-                       clock /= m1;
-               if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
-                       clock /= m2;
-               if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
-                       clock /= m3;
-               return clock;
-       default:
-               assert(0);
-       }
-       return 0;
-}
-
-/* Get the current speed the backplane is running at */
-u32 ssb_clockspeed(struct ssb_bus *bus)
-{
-       u32 rate;
-       u32 plltype;
-       u32 clkctl_n, clkctl_m;
-
-       //TODO if EXTIF: PLLTYPE == 1, read n from clockcontrol_n, m from clockcontrol_sb
-
-       if (bus->chipco.dev) {
-               ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
-                                           &clkctl_n, &clkctl_m);
-       } else
-               return 0;
-
-       if (bus->chip_id == 0x5365) {
-               rate = 100000000;
-       } else {
-               rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
-               if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
-                       rate /= 2;
-       }
-
-       return rate;
-}
-EXPORT_SYMBOL(ssb_clockspeed);
-
-int ssb_device_is_enabled(struct ssb_device *dev)
-{
-       u32 val;
-
-       val = ssb_read32(dev, SSB_TMSLOW);
-       val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT;
-
-       return (val == SSB_TMSLOW_CLOCK);
-}
-EXPORT_SYMBOL(ssb_device_is_enabled);
-
-void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
-{
-       u32 val;
-
-       ssb_device_disable(dev, core_specific_flags);
-       ssb_write32(dev, SSB_TMSLOW,
-                   SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
-                   SSB_TMSLOW_FGC | core_specific_flags);
-       /* flush */
-       ssb_read32(dev, SSB_TMSLOW);
-       udelay(1);
-
-       /* Clear SERR if set. This is a hw bug workaround. */
-       if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
-               ssb_write32(dev, SSB_TMSHIGH, 0);
-
-       val = ssb_read32(dev, SSB_IMSTATE);
-       if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
-               val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
-               ssb_write32(dev, SSB_IMSTATE, val);
-       }
-
-       ssb_write32(dev, SSB_TMSLOW,
-                   SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
-                   core_specific_flags);
-       /* flush */
-       ssb_read32(dev, SSB_TMSLOW);
-       udelay(1);
-
-       ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
-                   core_specific_flags);
-       /* flush */
-       ssb_read32(dev, SSB_TMSLOW);
-       udelay(1);
-}
-EXPORT_SYMBOL(ssb_device_enable);
-
-static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
-                       int timeout, int set)
-{
-       int i;
-       u32 val;
-
-       for (i = 0; i < timeout; i++) {
-               val = ssb_read32(dev, reg);
-               if (set) {
-                       if (val & bitmask)
-                               return 0;
-               } else {
-                       if (!(val & bitmask))
-                               return 0;
-               }
-               udelay(10);
-       }
-       printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
-                           "register %04X to %s.\n",
-              bitmask, reg, (set ? "set" : "clear"));
-
-       return -ETIMEDOUT;
-}
-
-void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
-{
-       if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
-               return;
-
-       ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_REJECT | SSB_TMSLOW_CLOCK);
-       ssb_wait_bit(dev, SSB_TMSLOW, SSB_TMSLOW_REJECT, 1000, 1);
-       ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
-       ssb_write32(dev, SSB_TMSLOW,
-                   SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
-                   SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET |
-                   core_specific_flags);
-       /* flush */
-       ssb_read32(dev, SSB_TMSLOW);
-       udelay(1);
-
-       ssb_write32(dev, SSB_TMSLOW,
-                   SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET |
-                   core_specific_flags);
-       /* flush */
-       ssb_read32(dev, SSB_TMSLOW);
-       udelay(1);
-}
-EXPORT_SYMBOL(ssb_device_disable);
-
-u32 ssb_dma_translation(struct ssb_device *dev)
-{
-       switch(dev->bus->bustype) {
-       case SSB_BUSTYPE_SSB:
-               return 0;
-       case SSB_BUSTYPE_PCI:
-       case SSB_BUSTYPE_PCMCIA:
-               return SSB_PCI_DMA;
-       }
-       return 0;
-}
-EXPORT_SYMBOL(ssb_dma_translation);
-
-int ssb_dma_set_mask(struct ssb_device *ssb_dev, u64 mask)
-{
-       struct device *dev = &ssb_dev->dev;
-
-#ifdef CONFIG_SSB_PCIHOST
-       if (ssb_dev->bus->bustype == SSB_BUSTYPE_PCI &&
-           !dma_supported(dev, mask))
-               return -EIO;
-#endif
-       dev->coherent_dma_mask = mask;
-       dev->dma_mask = &dev->coherent_dma_mask;
-
-       return 0;
-}
-EXPORT_SYMBOL(ssb_dma_set_mask);
-
-u32 ssb_admatch_base(u32 adm)
-{
-       u32 base = 0;
-
-       switch (adm & SSB_ADM_TYPE) {
-       case SSB_ADM_TYPE0:
-               base = (adm & SSB_ADM_BASE0);
-               break;
-       case SSB_ADM_TYPE1:
-               assert(!(adm & SSB_ADM_NEG)); /* unsupported */
-               base = (adm & SSB_ADM_BASE1);
-               break;
-       case SSB_ADM_TYPE2:
-               assert(!(adm & SSB_ADM_NEG)); /* unsupported */
-               base = (adm & SSB_ADM_BASE2);
-               break;
-       default:
-               assert(0);
-       }
-
-       return base;
-}
-EXPORT_SYMBOL(ssb_admatch_base);
-
-u32 ssb_admatch_size(u32 adm)
-{
-       u32 size = 0;
-
-       switch (adm & SSB_ADM_TYPE) {
-       case SSB_ADM_TYPE0:
-               size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
-               break;
-       case SSB_ADM_TYPE1:
-               assert(!(adm & SSB_ADM_NEG)); /* unsupported */
-               size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
-               break;
-       case SSB_ADM_TYPE2:
-               assert(!(adm & SSB_ADM_NEG)); /* unsupported */
-               size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
-               break;
-       default:
-               assert(0);
-       }
-       size = (1 << (size + 1));
-
-       return size;
-}
-EXPORT_SYMBOL(ssb_admatch_size);
-
-static int __init ssb_modinit(void)
-{
-       int err;
-
-       ssb_bustype.name = "ssb";
-       err = bus_register(&ssb_bustype);
-       if (err)
-               return err;
-
-       /* Maybe we already registered some buses at early boot.
-        * Check for this and attach them
-        */
-       ssb_buses_lock();
-       err = ssb_attach_queued_buses();
-       ssb_buses_unlock();
-
-       return err;
-}
-subsys_initcall(ssb_modinit);
-
-static void __exit ssb_modexit(void)
-{
-       bus_unregister(&ssb_bustype);
-}
-module_exit(ssb_modexit)
diff --git a/target/linux/brcm47xx-2.6/files/drivers/ssb/driver_chipcommon.c b/target/linux/brcm47xx-2.6/files/drivers/ssb/driver_chipcommon.c
new file mode 100644 (file)
index 0000000..8e511c7
--- /dev/null
@@ -0,0 +1,402 @@
+/*
+ * Sonics Silicon Backplane
+ * Broadcom ChipCommon core driver
+ *
+ * Copyright 2005, Broadcom Corporation
+ * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+#include <linux/ssb/ssb.h>
+#include <linux/ssb/ssb_regs.h>
+#include <linux/pci.h>
+
+#include "ssb_private.h"
+
+
+/* Clock sources */
+enum {
+       /* PCI clock */
+       SSB_CHIPCO_CLKSRC_PCI,
+       /* Crystal slow clock oscillator */
+       SSB_CHIPCO_CLKSRC_XTALOS,
+       /* Low power oscillator */
+       SSB_CHIPCO_CLKSRC_LOPWROS,
+};
+
+
+static inline u32 chipco_read32(struct ssb_chipcommon *cc,
+                               u16 offset)
+{
+       return ssb_read32(cc->dev, offset);
+}
+
+static inline void chipco_write32(struct ssb_chipcommon *cc,
+                                 u16 offset,
+                                 u32 value)
+{
+       ssb_write32(cc->dev, offset, value);
+}
+
+void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
+                             enum ssb_clkmode mode)
+{
+       struct ssb_device *ccdev = cc->dev;
+       struct ssb_bus *bus;
+       u32 tmp;
+
+       if (!ccdev)
+               return;
+       bus = ccdev->bus;
+       /* chipcommon cores prior to rev6 don't support dynamic clock control */
+       if (ccdev->id.revision < 6)
+               return;
+       /* chipcommon cores rev10 are a whole new ball game */
+       if (ccdev->id.revision >= 10)
+               return;
+       if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
+               return;
+
+       switch (mode) {
+       case SSB_CLKMODE_SLOW:
+               tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
+               tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
+               chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
+               break;
+       case SSB_CLKMODE_FAST:
+               ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
+               tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
+               tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
+               tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
+               chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
+               break;
+       case SSB_CLKMODE_DYNAMIC:
+               tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
+               tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
+               tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
+               tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
+               if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
+                       tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
+               chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
+
+               /* for dynamic control, we have to release our xtal_pu "force on" */
+               if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
+                       ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
+               break;
+       default:
+               assert(0);
+       }
+}
+
+/* Get the Slow Clock Source */
+static int chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc)
+{
+       struct ssb_bus *bus = cc->dev->bus;
+       u32 tmp = 0;
+
+       if (cc->dev->id.revision < 6) {
+               if (bus->bustype == SSB_BUSTYPE_SSB ||
+                   bus->bustype == SSB_BUSTYPE_PCMCIA)
+                       return SSB_CHIPCO_CLKSRC_XTALOS;
+               if (bus->bustype == SSB_BUSTYPE_PCI) {
+                       pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp);
+                       if (tmp & 0x10)
+                               return SSB_CHIPCO_CLKSRC_PCI;
+                       return SSB_CHIPCO_CLKSRC_XTALOS;
+               }
+       }
+       if (cc->dev->id.revision < 10) {
+               tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
+               tmp &= 0x7;
+               if (tmp == 0)
+                       return SSB_CHIPCO_CLKSRC_LOPWROS;
+               if (tmp == 1)
+                       return SSB_CHIPCO_CLKSRC_XTALOS;
+               if (tmp == 2)
+                       return SSB_CHIPCO_CLKSRC_PCI;
+       }
+
+       return SSB_CHIPCO_CLKSRC_XTALOS;
+}
+
+/* Get maximum or minimum (depending on get_max flag) slowclock frequency. */
+static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max)
+{
+       int limit;
+       int clocksrc;
+       int divisor;
+       u32 tmp;
+
+       clocksrc = chipco_pctl_get_slowclksrc(cc);
+       if (cc->dev->id.revision < 6) {
+               switch (clocksrc) {
+               case SSB_CHIPCO_CLKSRC_PCI:
+                       divisor = 64;
+                       break;
+               case SSB_CHIPCO_CLKSRC_XTALOS:
+                       divisor = 32;
+                       break;
+               default:
+                       assert(0);
+                       divisor = 1;
+               }
+       } else if (cc->dev->id.revision < 10) {
+               switch (clocksrc) {
+               case SSB_CHIPCO_CLKSRC_LOPWROS:
+                       divisor = 1;
+                       break;
+               case SSB_CHIPCO_CLKSRC_XTALOS:
+               case SSB_CHIPCO_CLKSRC_PCI:
+                       tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
+                       divisor = (tmp >> 16) + 1;
+                       divisor *= 4;
+                       break;
+               default:
+                       assert(0);
+                       divisor = 1;
+               }
+       } else {
+               tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL);
+               divisor = (tmp >> 16) + 1;
+               divisor *= 4;
+       }
+
+       switch (clocksrc) {
+       case SSB_CHIPCO_CLKSRC_LOPWROS:
+               if (get_max)
+                       limit = 43000;
+               else
+                       limit = 25000;
+               break;
+       case SSB_CHIPCO_CLKSRC_XTALOS:
+               if (get_max)
+                       limit = 20200000;
+               else
+                       limit = 19800000;
+               break;
+       case SSB_CHIPCO_CLKSRC_PCI:
+               if (get_max)
+                       limit = 34000000;
+               else
+                       limit = 25000000;
+               break;
+       default:
+               assert(0);
+               limit = 0;
+       }
+       limit /= divisor;
+
+       return limit;
+}
+
+static void chipco_powercontrol_init(struct ssb_chipcommon *cc)
+{
+       struct ssb_bus *bus = cc->dev->bus;
+
+       if (bus->chip_id == 0x4321) {
+               if (bus->chip_rev == 0)
+                       chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4);
+               else if (bus->chip_rev == 1)
+                       chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4);
+       }
+
+       if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
+               return;
+
+       if (cc->dev->id.revision >= 10) {
+               /* Set Idle Power clock rate to 1Mhz */
+               chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
+                              (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
+                               0x0000FFFF) | 0x00040000);
+       } else {
+               int maxfreq;
+
+               maxfreq = chipco_pctl_clockfreqlimit(cc, 1);
+               chipco_write32(cc, SSB_CHIPCO_PLLONDELAY,
+                              (maxfreq * 150 + 999999) / 1000000);
+               chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY,
+                              (maxfreq * 15 + 999999) / 1000000);
+       }
+}
+
+static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
+{
+       struct ssb_bus *bus = cc->dev->bus;
+       int minfreq;
+       unsigned int tmp;
+       u32 pll_on_delay;
+
+       if (bus->bustype != SSB_BUSTYPE_PCI)
+               return;
+       if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
+               return;
+
+       minfreq = chipco_pctl_clockfreqlimit(cc, 0);
+       pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY);
+       tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq;
+       assert((tmp & ~0xFFFF) == 0);
+
+       cc->fast_pwrup_delay = tmp;
+}
+
+void ssb_chipcommon_init(struct ssb_chipcommon *cc)
+{
+       if (!cc->dev)
+               return; /* We don't have a ChipCommon */
+       chipco_powercontrol_init(cc);
+       ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
+       calc_fast_powerup_delay(cc);
+}
+
+void ssb_chipco_suspend(struct ssb_chipcommon *cc, pm_message_t state)
+{
+       if (!cc->dev)
+               return;
+       ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
+}
+
+void ssb_chipco_resume(struct ssb_chipcommon *cc)
+{
+       if (!cc->dev)
+               return;
+       chipco_powercontrol_init(cc);
+       ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
+}
+
+void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
+                                u32 *plltype, u32 *n, u32 *m)
+{
+       *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
+       *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
+       switch (*plltype) {
+       case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
+               *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
+               break;
+       case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
+               if (cc->dev->bus->chip_id != 0x5365) {
+                       *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
+                       break;
+               }
+               /* Fallthough */
+       default:
+               *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
+       }
+}
+
+void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
+                           unsigned long ns)
+{
+       struct ssb_device *dev = cc->dev;
+       struct ssb_bus *bus = dev->bus;
+       u32 tmp;
+
+       /* set register for external IO to control LED. */
+       chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11);
+       tmp = ceildiv(10, ns) << SSB_PROG_WCNT_3_SHIFT;         /* Waitcount-3 = 10ns */
+       tmp |= ceildiv(40, ns) << SSB_PROG_WCNT_1_SHIFT;        /* Waitcount-1 = 40ns */
+       tmp |= ceildiv(240, ns);                                /* Waitcount-0 = 240ns */
+       chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp);       /* 0x01020a0c for a 100Mhz clock */
+
+       /* Set timing for the flash */
+       tmp = ceildiv(10, ns) << SSB_FLASH_WCNT_3_SHIFT;        /* Waitcount-3 = 10nS */
+       tmp |= ceildiv(10, ns) << SSB_FLASH_WCNT_1_SHIFT;       /* Waitcount-1 = 10nS */
+       tmp |= ceildiv(120, ns);                                /* Waitcount-0 = 120nS */
+       if ((bus->chip_id == 0x5365) ||
+           (dev->id.revision < 9))
+               chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp);
+       if ((bus->chip_id == 0x5365) ||
+           (dev->id.revision < 9) ||
+           ((bus->chip_id == 0x5350) && (bus->chip_rev == 0)))
+               chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp);
+
+       if (bus->chip_id == 0x5350) {
+               /* Enable EXTIF */
+               tmp = ceildiv(10, ns) << SSB_PROG_WCNT_3_SHIFT;   /* Waitcount-3 = 10ns */
+               tmp |= ceildiv(20, ns) << SSB_PROG_WCNT_2_SHIFT;  /* Waitcount-2 = 20ns */
+               tmp |= ceildiv(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */
+               tmp |= ceildiv(120, ns);                          /* Waitcount-0 = 120ns */
+               chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
+       }
+}
+
+
+#ifdef CONFIG_SSB_SERIAL
+int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
+                          struct ssb_serial_port *ports)
+{
+       struct ssb_bus *bus = cc->dev->bus;
+       int nr_ports = 0;
+       u32 plltype;
+       unsigned int irq;
+       u32 baud_base, div;
+       u32 i, n;
+
+       plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
+       irq = ssb_mips_irq(cc->dev);
+
+       if (plltype == SSB_PLLTYPE_1) {
+               /* PLL clock */
+               baud_base = ssb_calc_clock_rate(plltype,
+                                               chipco_read32(cc, SSB_CHIPCO_CLOCK_N),
+                                               chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
+               div = 1;
+       } else {
+               if (cc->dev->id.revision >= 11) {
+                       /* Fixed ALP clock */
+                       baud_base = 20000000;
+                       div = 1;
+                       /* Set the override bit so we don't divide it */
+                       chipco_write32(cc, SSB_CHIPCO_CORECTL,
+                                      SSB_CHIPCO_CORECTL_UARTCLK0);
+               } else if (cc->dev->id.revision >= 3) {
+                       /* Internal backplane clock */
+                       baud_base = ssb_clockspeed(bus);
+                       div = 2; /* Minimum divisor */
+                       chipco_write32(cc, SSB_CHIPCO_CLKDIV,
+                                      (chipco_read32(cc, SSB_CHIPCO_CLKDIV)
+                                       & ~SSB_CHIPCO_CLKDIV_UART) | div);
+               } else {
+                       /* Fixed internal backplane clock */
+                       baud_base = 88000000;
+                       div = 48;
+               }
+
+               /* Clock source depends on strapping if UartClkOverride is unset */
+               if ((cc->dev->id.revision > 0) &&
+                   !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
+                       if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
+                           SSB_CHIPCO_CAP_UARTCLK_INT) {
+                               /* Internal divided backplane clock */
+                               baud_base /= div;
+                       } else {
+                               /* Assume external clock of 1.8432 MHz */
+                               baud_base = 1843200;
+                       }
+               }
+       }
+
+       /* Determine the registers of the UARTs */
+       n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART);
+       for (i = 0; i < n; i++) {
+               void __iomem *cc_mmio;
+               void __iomem *uart_regs;
+
+               cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
+               uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
+               /* Offset changed at after rev 0 */
+               if (cc->dev->id.revision == 0)
+                       uart_regs += (i * 8);
+               else
+                       uart_regs += (i * 256);
+
+               nr_ports++;
+               ports[i].regs = uart_regs;
+               ports[i].irq = irq;
+               ports[i].baud_base = baud_base;
+               ports[i].reg_shift = 0;
+       }
+
+       return nr_ports;
+}
+#endif /* CONFIG_SSB_SERIAL */
diff --git a/target/linux/brcm47xx-2.6/files/drivers/ssb/driver_chipcommon/chipcommon.c b/target/linux/brcm47xx-2.6/files/drivers/ssb/driver_chipcommon/chipcommon.c
deleted file mode 100644 (file)
index a179109..0000000
+++ /dev/null
@@ -1,442 +0,0 @@
-/*
- * Sonics Silicon Backplane
- * Broadcom ChipCommon core driver
- *
- * Copyright 2005, Broadcom Corporation
- * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
- *
- * Licensed under the GNU/GPL. See COPYING for details.
- */
-
-#include <linux/ssb/ssb.h>
-#include <linux/ssb/ssb_regs.h>
-#include <linux/pci.h>
-
-#include "../ssb_private.h"
-
-
-/* Clock sources */
-enum {
-       /* PCI clock */
-       SSB_CHIPCO_CLKSRC_PCI,
-       /* Crystal slow clock oscillator */
-       SSB_CHIPCO_CLKSRC_XTALOS,
-       /* Low power oscillator */
-       SSB_CHIPCO_CLKSRC_LOPWROS,
-};
-
-
-static inline u32 chipco_read32(struct ssb_chipcommon *cc,
-                               u16 offset)
-{
-       return ssb_read32(cc->dev, offset);
-}
-
-static inline void chipco_write32(struct ssb_chipcommon *cc,
-                                 u16 offset,
-                                 u32 value)
-{
-       ssb_write32(cc->dev, offset, value);
-}
-
-
-void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
-                             enum ssb_clkmode mode)
-{
-       struct ssb_device *ccdev = cc->dev;
-       struct ssb_bus *bus;
-       u32 tmp;
-
-       if (!ccdev)
-               return;
-       bus = ccdev->bus;
-       /* chipcommon cores prior to rev6 don't support dynamic clock control */
-       if (ccdev->id.revision < 6)
-               return;
-       /* chipcommon cores rev10 are a whole new ball game */
-       if (ccdev->id.revision >= 10)
-               return;
-       if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
-               return;
-
-       switch (mode) {
-       case SSB_CLKMODE_SLOW:
-               tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
-               tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
-               chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
-               break;
-       case SSB_CLKMODE_FAST:
-               ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
-               tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
-               tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
-               tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
-               chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
-               break;
-       case SSB_CLKMODE_DYNAMIC:
-               tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
-               tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
-               tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
-               tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
-               if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
-                       tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
-               chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
-
-               /* for dynamic control, we have to release our xtal_pu "force on" */
-               if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
-                       ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
-               break;
-       default:
-               assert(0);
-       }
-}
-EXPORT_SYMBOL(ssb_chipco_set_clockmode);
-
-/* Get the Slow Clock Source */
-static int chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc)
-{
-       struct ssb_bus *bus = cc->dev->bus;
-       u32 tmp = 0;
-
-       if (cc->dev->id.revision < 6) {
-               if (bus->bustype == SSB_BUSTYPE_SSB /*TODO ||
-                   bus->bustype == SSB_BUSTYPE_PCMCIA*/)
-                       return SSB_CHIPCO_CLKSRC_XTALOS;
-               if (bus->bustype == SSB_BUSTYPE_PCI) {
-                       pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp);
-                       if (tmp & 0x10)
-                               return SSB_CHIPCO_CLKSRC_PCI;
-                       return SSB_CHIPCO_CLKSRC_XTALOS;
-               }
-       }
-       if (cc->dev->id.revision < 10) {
-               tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
-               tmp &= 0x7;
-               if (tmp == 0)
-                       return SSB_CHIPCO_CLKSRC_LOPWROS;
-               if (tmp == 1)
-                       return SSB_CHIPCO_CLKSRC_XTALOS;
-               if (tmp == 2)
-                       return SSB_CHIPCO_CLKSRC_PCI;
-       }
-
-       return SSB_CHIPCO_CLKSRC_XTALOS;
-}
-
-/* Get maximum or minimum (depending on get_max flag) slowclock frequency. */
-static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max)
-{
-       int limit;
-       int clocksrc;
-       int divisor;
-       u32 tmp;
-
-       clocksrc = chipco_pctl_get_slowclksrc(cc);
-       if (cc->dev->id.revision < 6) {
-               switch (clocksrc) {
-               case SSB_CHIPCO_CLKSRC_PCI:
-                       divisor = 64;
-                       break;
-               case SSB_CHIPCO_CLKSRC_XTALOS:
-                       divisor = 32;
-                       break;
-               default:
-                       assert(0);
-                       divisor = 1;
-               }
-       } else if (cc->dev->id.revision < 10) {
-               switch (clocksrc) {
-               case SSB_CHIPCO_CLKSRC_LOPWROS:
-                       divisor = 1;
-                       break;
-               case SSB_CHIPCO_CLKSRC_XTALOS:
-               case SSB_CHIPCO_CLKSRC_PCI:
-                       tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
-                       divisor = (tmp >> 16) + 1;
-                       divisor *= 4;
-                       break;
-               default:
-                       assert(0);
-                       divisor = 1;
-               }
-       } else {
-               tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL);
-               divisor = (tmp >> 16) + 1;
-               divisor *= 4;
-       }
-
-       switch (clocksrc) {
-       case SSB_CHIPCO_CLKSRC_LOPWROS:
-               if (get_max)
-                       limit = 43000;
-               else
-                       limit = 25000;
-               break;
-       case SSB_CHIPCO_CLKSRC_XTALOS:
-               if (get_max)
-                       limit = 20200000;
-               else
-                       limit = 19800000;
-               break;
-       case SSB_CHIPCO_CLKSRC_PCI:
-               if (get_max)
-                       limit = 34000000;
-               else
-                       limit = 25000000;
-               break;
-       default:
-               assert(0);
-               limit = 0;
-       }
-       limit /= divisor;
-
-       return limit;
-}
-
-static void chipco_powercontrol_init(struct ssb_chipcommon *cc)
-{
-       struct ssb_bus *bus = cc->dev->bus;
-
-       if (bus->chip_id == 0x4321) {
-               if (bus->chip_rev == 0)
-                       chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4);
-               else if (bus->chip_rev == 1)
-                       chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4);
-       }
-
-       if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
-               return;
-
-       if (cc->dev->id.revision >= 10) {
-               /* Set Idle Power clock rate to 1Mhz */
-               chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
-                              (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
-                               0x0000FFFF) | 0x00040000);
-       } else {
-               int maxfreq;
-
-               maxfreq = chipco_pctl_clockfreqlimit(cc, 1);
-               chipco_write32(cc, SSB_CHIPCO_PLLONDELAY,
-                              (maxfreq * 150 + 999999) / 1000000);
-               chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY,
-                              (maxfreq * 15 + 999999) / 1000000);
-       }
-}
-
-static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
-{
-       struct ssb_bus *bus = cc->dev->bus;
-       int minfreq;
-       unsigned int tmp;
-       u32 pll_on_delay;
-
-       if (bus->bustype != SSB_BUSTYPE_PCI)
-               return;
-       if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
-               return;
-
-       minfreq = chipco_pctl_clockfreqlimit(cc, 0);
-       pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY);
-       tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq;
-       assert((tmp & ~0xFFFF) == 0);
-
-       cc->fast_pwrup_delay = tmp;
-}
-
-void ssb_chipcommon_init(struct ssb_chipcommon *cc)
-{
-       if (!cc->dev)
-               return; /* We don't have a ChipCommon */
-       ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
-       chipco_powercontrol_init(cc);
-       calc_fast_powerup_delay(cc);
-}
-
-void ssb_chipco_suspend(struct ssb_chipcommon *cc, pm_message_t state)
-{
-       if (!cc->dev)
-               return;
-       ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
-}
-
-void ssb_chipco_resume(struct ssb_chipcommon *cc)
-{
-       if (!cc->dev)
-               return;
-       ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
-       chipco_powercontrol_init(cc);
-}
-
-void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc, u32 chip_id, u32 *rate,
-                            u32 *plltype, u32 *n, u32 *m)
-{
-       *rate = 0;
-       *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
-       *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
-       switch (*plltype) {
-               case SSB_PLLTYPE_2:
-               case SSB_PLLTYPE_4:
-               case SSB_PLLTYPE_6:
-               case SSB_PLLTYPE_7:
-                       *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
-                       break;
-               case SSB_PLLTYPE_5:
-                       *rate = 200000000;
-                       break;
-               case SSB_PLLTYPE_3:
-                       /* 5350 uses m2 to control mips */
-                       *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
-                       break;
-               default:
-                       *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
-                       break;
-       }
-
-       if (*rate == 0 && chip_id == 0x5365)
-               *rate = 200000000;
-}
-
-void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
-                                u32 *plltype, u32 *n, u32 *m)
-{
-       *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
-       *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
-       switch (*plltype) {
-       case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
-               *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
-               break;
-       case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
-               if (cc->dev->bus->chip_id != 0x5365) {
-                       *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
-                       break;
-               }
-               /* Fallthough */
-       default:
-               *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
-       }
-}
-
-void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
-                           unsigned long ns)
-{
-       struct ssb_device *dev = cc->dev;
-       struct ssb_bus *bus = dev->bus;
-       u32 tmp;
-
-       /* set register for external IO to control LED. */
-       chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11);
-       tmp = ceildiv(10, ns) << SSB_PROG_WCNT_3_SHIFT;         /* Waitcount-3 = 10ns */
-       tmp |= ceildiv(40, ns) << SSB_PROG_WCNT_1_SHIFT;        /* Waitcount-1 = 40ns */
-       tmp |= ceildiv(240, ns);                                /* Waitcount-0 = 240ns */
-       chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp);       /* 0x01020a0c for a 100Mhz clock */
-
-       /* Set timing for the flash */
-       tmp = ceildiv(10, ns) << SSB_FLASH_WCNT_3_SHIFT;        /* Waitcount-3 = 10nS */
-       tmp |= ceildiv(10, ns) << SSB_FLASH_WCNT_1_SHIFT;       /* Waitcount-1 = 10nS */
-       tmp |= ceildiv(120, ns);                                /* Waitcount-0 = 120nS */
-       if ((bus->chip_id == 0x5365) ||
-           (dev->id.revision < 9))
-               chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp);
-       if ((bus->chip_id == 0x5365) ||
-           (dev->id.revision < 9) ||
-           ((bus->chip_id == 0x5350) && (bus->chip_rev == 0)))
-               chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp);
-
-       if (bus->chip_id == 0x5350) {
-               /* Enable EXTIF */
-               tmp = ceildiv(10, ns) << SSB_PROG_WCNT_3_SHIFT;   /* Waitcount-3 = 10ns */
-               tmp |= ceildiv(20, ns) << SSB_PROG_WCNT_2_SHIFT;  /* Waitcount-2 = 20ns */
-               tmp |= ceildiv(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */
-               tmp |= ceildiv(120, ns);                          /* Waitcount-0 = 120ns */
-               chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
-       }
-}
-
-#ifdef CONFIG_SSB_SERIAL
-int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
-                          struct ssb_serial_port *ports)
-{
-       struct ssb_bus *bus = cc->dev->bus;
-       int nr_ports = 0;
-       u32 plltype;
-       unsigned int irq;
-       u32 baud_base, div;
-       u32 i, n;
-
-       plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
-       irq = ssb_mips_irq(cc->dev);
-
-       if (plltype == SSB_PLLTYPE_1) {
-               /* PLL clock */
-               baud_base = ssb_calc_clock_rate(plltype,
-                                               chipco_read32(cc, SSB_CHIPCO_CLOCK_N),
-                                               chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
-               div = 1;
-       } else {
-               if (cc->dev->id.revision >= 11) {
-                       /* Fixed ALP clock */
-                       baud_base = 20000000;
-                       div = 1;
-                       /* Set the override bit so we don't divide it */
-                       chipco_write32(cc, SSB_CHIPCO_CORECTL,
-                                      SSB_CHIPCO_CORECTL_UARTCLK0);
-               } else if (cc->dev->id.revision >= 3) {
-                       /* Internal backplane clock */
-                       baud_base = ssb_clockspeed(bus);
-                       div = 2; /* Minimum divisor */
-                       chipco_write32(cc, SSB_CHIPCO_CLKDIV,
-                                      (chipco_read32(cc, SSB_CHIPCO_CLKDIV)
-                                       & ~SSB_CHIPCO_CLKDIV_UART) | div);
-               } else {
-                       /* Fixed internal backplane clock */
-                       baud_base = 88000000;
-                       div = 48;
-               }
-
-               /* Clock source depends on strapping if UartClkOverride is unset */
-               if ((cc->dev->id.revision > 0) &&
-                   !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
-                       if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
-                           SSB_CHIPCO_CAP_UARTCLK_INT) {
-                               /* Internal divided backplane clock */
-                               baud_base /= div;
-                       } else {
-                               /* Assume external clock of 1.8432 MHz */
-                               baud_base = 1843200;
-                       }
-               }
-       }
-
-       /* Determine the registers of the UARTs */
-       n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART);
-       for (i = 0; i < n; i++) {
-               void __iomem *cc_mmio;
-               void __iomem *uart_regs;
-
-               cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
-               uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
-               /* Offset changed at after rev 0 */
-               if (cc->dev->id.revision == 0)
-                       uart_regs += (i * 8);
-               else
-                       uart_regs += (i * 256);
-
-               nr_ports++;
-               ports[i].regs = uart_regs;
-               ports[i].irq = irq;
-               ports[i].baud_base = baud_base;
-               ports[i].reg_shift = 0;
-       }
-
-       return nr_ports;
-}
-#endif /* CONFIG_SSB_SERIAL */
-
-/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
-int
-ssb_chipco_watchdog(struct ssb_chipcommon *cc, uint ticks)
-{
-       /* instant NMI */
-       chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
-       return 0;
-}
-EXPORT_SYMBOL(ssb_chipco_watchdog);
diff --git a/target/linux/brcm47xx-2.6/files/drivers/ssb/driver_mips/mips.c b/target/linux/brcm47xx-2.6/files/drivers/ssb/driver_mips/mips.c
deleted file mode 100644 (file)
index 7b3880a..0000000
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- * Sonics Silicon Backplane
- * Broadcom MIPS core driver
- *
- * Copyright 2005, Broadcom Corporation
- * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
- * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org>
- *
- * Licensed under the GNU/GPL. See COPYING for details.
- */
-
-#include <linux/ssb/ssb.h>
-
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_reg.h>
-#include <asm/time.h>
-
-#include "../ssb_private.h"
-
-#define mips_read32(mcore, offset) ssb_read32((mcore)->dev, offset)
-#define mips_write32(mcore, offset, value) ssb_write32((mcore)->dev, offset, value)
-#define extif_read32(extif, offset) ssb_read32((extif)->dev, offset)
-#define extif_write32(extif, offset, value) ssb_write32((extif)->dev, offset, value)
-
-static const u32 ipsflag_irq_mask[] = {
-       0,
-       SSB_IPSFLAG_IRQ1,
-       SSB_IPSFLAG_IRQ2,
-       SSB_IPSFLAG_IRQ3,
-       SSB_IPSFLAG_IRQ4,
-};
-
-static const u32 ipsflag_irq_shift[] = {
-       0,
-       SSB_IPSFLAG_IRQ1_SHIFT,
-       SSB_IPSFLAG_IRQ2_SHIFT,
-       SSB_IPSFLAG_IRQ3_SHIFT,
-       SSB_IPSFLAG_IRQ4_SHIFT,
-};
-
-static inline u32 ssb_irqflag(struct ssb_device *dev)
-{
-       return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
-}
-
-/* Get the MIPS IRQ assignment for a specified device.
- * If unassigned, 0 is returned.
- */
-unsigned int ssb_mips_irq(struct ssb_device *dev)
-{
-       struct ssb_bus *bus = dev->bus;
-       u32 irqflag;
-       u32 ipsflag;
-       u32 tmp;
-       unsigned int irq;
-
-       irqflag = ssb_irqflag(dev);
-       ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
-       for (irq = 1; irq <= 4; irq++) {
-               tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
-               if (tmp == irqflag)
-                       break;
-       }
-       if (irq == 5)
-               irq = 0;
-
-       return irq;
-}
-
-static void clear_irq(struct ssb_bus *bus, unsigned int irq)
-{
-       struct ssb_device *dev = bus->mipscore.dev;
-
-       /* Clear the IRQ in the MIPScore backplane registers */
-       if (irq == 0) {
-               ssb_write32(dev, SSB_INTVEC, 0);
-       } else {
-               ssb_write32(dev, SSB_IPSFLAG,
-                           ssb_read32(dev, SSB_IPSFLAG) |
-                           ipsflag_irq_mask[irq]);
-       }
-}
-
-static void set_irq(struct ssb_device *dev, unsigned int irq)
-{
-       unsigned int oldirq = ssb_mips_irq(dev);
-       struct ssb_bus *bus = dev->bus;
-       struct ssb_device *mdev = bus->mipscore.dev;
-       u32 irqflag = ssb_irqflag(dev);
-
-       dev->irq = irq + 2;
-
-       ssb_dprintk(KERN_INFO PFX
-                   "set_irq: core 0x%04x, irq %d => %d\n",
-                   dev->id.coreid, oldirq, irq);
-       /* clear the old irq */
-       if (oldirq == 0)
-               ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
-       else
-               clear_irq(bus, oldirq);
-
-       /* assign the new one */
-       if (irq == 0)
-               ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
-
-       irqflag <<= ipsflag_irq_shift[irq];
-       irqflag |= (ssb_read32(mdev, SSB_IPSFLAG) & ~ipsflag_irq_mask[irq]);
-       ssb_write32(mdev, SSB_IPSFLAG, irqflag);
-}
-
-static int ssb_extif_serial_init(struct ssb_extif *dev, struct ssb_serial_port *ports)
-{
-       //TODO if (EXTIF available
-#if 0
-               extifregs_t *eir = (extifregs_t *) regs;
-               sbconfig_t *sb;
-
-               /* Determine external UART register base */
-               sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
-               base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
-
-               /* Determine IRQ */
-               irq = sb_irq(sbh);
-
-               /* Disable GPIO interrupt initially */
-               W_REG(&eir->gpiointpolarity, 0);
-               W_REG(&eir->gpiointmask, 0);
-
-               /* Search for external UARTs */
-               n = 2;
-               for (i = 0; i < 2; i++) {
-                       regs = (void *) REG_MAP(base + (i * 8), 8);
-                       if (BCMINIT(serial_exists)(regs)) {
-                               /* Set GPIO 1 to be the external UART IRQ */
-                               W_REG(&eir->gpiointmask, 2);
-                               if (add)
-                                       add(regs, irq, 13500000, 0);
-                       }
-               }
-
-               /* Add internal UART if enabled */
-               if (R_REG(&eir->corecontrol) & CC_UE)
-                       if (add)
-                               add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
-
-#endif
-
-}
-
-
-static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
-{
-       struct ssb_bus *bus = mcore->dev->bus;
-
-       if (bus->extif.dev)
-               mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
-       else if (bus->chipco.dev)
-               mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
-       else
-               mcore->nr_serial_ports = 0;
-}
-
-static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
-{
-       struct ssb_bus *bus = mcore->dev->bus;
-
-       mcore->flash_buswidth = 2;
-       if (bus->chipco.dev) {
-               mcore->flash_window = 0x1c000000;
-               mcore->flash_window_size = 0x02000000;
-               if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
-                               & SSB_CHIPCO_CFG_DS16) == 0)
-                       mcore->flash_buswidth = 1;
-       } else {
-               mcore->flash_window = 0x1fc00000;
-               mcore->flash_window_size = 0x00400000;
-       }
-}
-
-static void ssb_extif_timing_init(struct ssb_extif *extif, u32 ns)
-{
-       u32 tmp;
-
-       /* Initialize extif so we can get to the LEDs and external UART */
-       extif_write32(extif, SSB_EXTIF_PROG_CFG, SSB_EXTCFG_EN);
-       
-       /* Set timing for the flash */
-       tmp  = ceildiv(10, ns) << SSB_PROG_WCNT_3_SHIFT;
-       tmp |= ceildiv(40, ns) << SSB_PROG_WCNT_1_SHIFT;
-       tmp |= ceildiv(120, ns);
-       extif_write32(extif, SSB_EXTIF_PROG_WAITCNT, tmp);
-
-       /* Set programmable interface timing for external uart */
-       tmp  = ceildiv(10, ns) << SSB_PROG_WCNT_3_SHIFT;
-       tmp |= ceildiv(20, ns) << SSB_PROG_WCNT_2_SHIFT;
-       tmp |= ceildiv(100, ns) << SSB_PROG_WCNT_1_SHIFT;
-       tmp |= ceildiv(120, ns);
-       extif_write32(extif, SSB_EXTIF_PROG_WAITCNT, tmp);
-}
-
-static inline void ssb_extif_get_clockcontrol(struct ssb_extif *extif,
-                                u32 *pll_type, u32 *n, u32 *m)
-{
-       *pll_type = SSB_PLLTYPE_1;
-       *n = extif_read32(extif, SSB_EXTIF_CLOCK_N);
-       *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
-}
-
-u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
-{
-       struct ssb_bus *bus = mcore->dev->bus;
-       u32 pll_type, n, m, rate = 0;
-
-       if (bus->extif.dev) {
-               ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
-       } else if (bus->chipco.dev) {
-               ssb_chipco_get_clockcpu(&bus->chipco, bus->chip_id, &rate,
-                       &pll_type, &n, &m);
-       } else
-               return 0;
-
-       if (rate == 0)
-               rate = ssb_calc_clock_rate(pll_type, n, m);
-
-       if (pll_type == SSB_PLLTYPE_6)
-               rate *= 2;
-
-       return rate;
-}
-
-void ssb_mipscore_init(struct ssb_mipscore *mcore)
-{
-       struct ssb_bus *bus = mcore->dev->bus;
-       struct ssb_device *dev;
-       unsigned long hz, ns;
-       unsigned int irq, i;
-
-       if (!mcore->dev)
-               return; /* We don't have a MIPS core */
-
-       ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n");
-
-       hz = ssb_clockspeed(bus);
-       if (!hz)
-               hz = 100000000;
-       ns = 1000000000 / hz;
-
-       if (bus->extif.dev)
-               ssb_extif_timing_init(&bus->extif, ns);
-       else if (bus->chipco.dev)
-               ssb_chipco_timing_init(&bus->chipco, ns);
-
-       /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
-       for (irq = 2, i = 0; i < bus->nr_devices; i++) {
-               dev = &(bus->devices[i]);
-               dev->irq = ssb_mips_irq(dev) + 2;
-               switch(dev->id.coreid) {
-                       case SSB_DEV_USB11_HOST:
-                               /* shouldn't need a separate irq line for non-4710, most of them have a proper
-                                * external usb controller on the pci */
-                               if ((bus->chip_id == 0x4710) && (irq <= 4)) {
-                                       set_irq(dev, irq++);
-                                       break;
-                               }
-                       case SSB_DEV_PCI:
-                       case SSB_DEV_ETHERNET:
-                       case SSB_DEV_80211:
-                       case SSB_DEV_USB20_HOST:
-                               /* These devices get their own IRQ line if available, the rest goes on IRQ0 */
-                               if (irq <= 4) {
-                                       set_irq(dev, irq++);
-                                       break;
-                               }
-               }
-       }
-
-       ssb_mips_serial_init(mcore);
-       ssb_mips_flash_detect(mcore);
-}
-
-EXPORT_SYMBOL(ssb_mips_irq);
diff --git a/target/linux/brcm47xx-2.6/files/drivers/ssb/driver_mipscore.c b/target/linux/brcm47xx-2.6/files/drivers/ssb/driver_mipscore.c
new file mode 100644 (file)
index 0000000..67d1017
--- /dev/null
@@ -0,0 +1,258 @@
+/*
+ * Sonics Silicon Backplane
+ * Broadcom MIPS core driver
+ *
+ * Copyright 2005, Broadcom Corporation
+ * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+#include <linux/ssb/ssb.h>
+
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/serial_reg.h>
+#include <asm/time.h>
+
+#include "ssb_private.h"
+
+
+static inline u32 mips_read32(struct ssb_mipscore *mcore,
+                             u16 offset)
+{
+       return ssb_read32(mcore->dev, offset);
+}
+
+static inline void mips_write32(struct ssb_mipscore *mcore,
+                               u16 offset,
+                               u32 value)
+{
+       ssb_write32(mcore->dev, offset, value);
+}
+
+static const u32 ipsflag_irq_mask[] = {
+       0,
+       SSB_IPSFLAG_IRQ1,
+       SSB_IPSFLAG_IRQ2,
+       SSB_IPSFLAG_IRQ3,
+       SSB_IPSFLAG_IRQ4,
+};
+
+static const u32 ipsflag_irq_shift[] = {
+       0,
+       SSB_IPSFLAG_IRQ1_SHIFT,
+       SSB_IPSFLAG_IRQ2_SHIFT,
+       SSB_IPSFLAG_IRQ3_SHIFT,
+       SSB_IPSFLAG_IRQ4_SHIFT,
+};
+
+static inline u32 ssb_irqflag(struct ssb_device *dev)
+{
+       return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
+}
+
+/* Get the MIPS IRQ assignment for a specified device.
+ * If unassigned, 0 is returned.
+ */
+unsigned int ssb_mips_irq(struct ssb_device *dev)
+{
+       struct ssb_bus *bus = dev->bus;
+       u32 irqflag;
+       u32 ipsflag;
+       u32 tmp;
+       unsigned int irq;
+
+       irqflag = ssb_irqflag(dev);
+       ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
+       for (irq = 1; irq <= 4; irq++) {
+               tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
+               if (tmp == irqflag)
+                       break;
+       }
+       if (irq == 5)
+               irq = 0;
+
+       return irq;
+}
+
+static void clear_irq(struct ssb_bus *bus, unsigned int irq)
+{
+       struct ssb_device *dev = bus->mipscore.dev;
+
+       /* Clear the IRQ in the MIPScore backplane registers */
+       if (irq == 0) {
+               ssb_write32(dev, SSB_INTVEC, 0);
+       } else {
+               ssb_write32(dev, SSB_IPSFLAG,
+                           ssb_read32(dev, SSB_IPSFLAG) |
+                           ipsflag_irq_mask[irq]);
+       }
+}
+
+static void set_irq(struct ssb_device *dev, unsigned int irq)
+{
+       unsigned int oldirq = ssb_mips_irq(dev);
+       struct ssb_bus *bus = dev->bus;
+       struct ssb_device *mdev = bus->mipscore.dev;
+       u32 irqflag = ssb_irqflag(dev);
+
+       dev->irq = irq + 2;
+
+       ssb_dprintk(KERN_INFO PFX
+                   "set_irq: core 0x%04x, irq %d => %d\n",
+                   dev->id.coreid, oldirq, irq);
+       /* clear the old irq */
+       if (oldirq == 0)
+               ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
+       else
+               clear_irq(bus, oldirq);
+
+       /* assign the new one */
+       if (irq == 0)
+               ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
+
+       irqflag <<= ipsflag_irq_shift[irq];
+       irqflag |= (ssb_read32(mdev, SSB_IPSFLAG) & ~ipsflag_irq_mask[irq]);
+       ssb_write32(mdev, SSB_IPSFLAG, irqflag);
+}
+
+/* XXX: leave here or move into separate extif driver? */
+static int ssb_extif_serial_init(struct ssb_device *dev, struct ssb_serial_ports *ports)
+{
+
+}
+
+
+static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
+{
+       struct ssb_bus *bus = mcore->dev->bus;
+
+       //TODO if (EXTIF available
+#if 0
+               extifregs_t *eir = (extifregs_t *) regs;
+               sbconfig_t *sb;
+
+               /* Determine external UART register base */
+               sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
+               base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
+
+               /* Determine IRQ */
+               irq = sb_irq(sbh);
+
+               /* Disable GPIO interrupt initially */
+               W_REG(&eir->gpiointpolarity, 0);
+               W_REG(&eir->gpiointmask, 0);
+
+               /* Search for external UARTs */
+               n = 2;
+               for (i = 0; i < 2; i++) {
+                       regs = (void *) REG_MAP(base + (i * 8), 8);
+                       if (BCMINIT(serial_exists)(regs)) {
+                               /* Set GPIO 1 to be the external UART IRQ */
+                               W_REG(&eir->gpiointmask, 2);
+                               if (add)
+                                       add(regs, irq, 13500000, 0);
+                       }
+               }
+
+               /* Add internal UART if enabled */
+               if (R_REG(&eir->corecontrol) & CC_UE)
+                       if (add)
+                               add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
+
+#endif
+       if (bus->extif.dev)
+               mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
+       else if (bus->chipco.dev)
+               mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
+       else
+               mcore->nr_serial_ports = 0;
+}
+
+static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
+{
+       struct ssb_bus *bus = mcore->dev->bus;
+
+       if (bus->chipco.dev) {
+               mcore->flash_window = 0x1c000000;
+               mcore->flash_window_size = 0x800000;
+       } else {
+               mcore->flash_window = 0x1fc00000;
+               mcore->flash_window_size = 0x400000;
+       }
+}
+
+
+static void ssb_cpu_clock(struct ssb_mipscore *mcore)
+{
+}
+
+void ssb_mipscore_init(struct ssb_mipscore *mcore)
+{
+       struct ssb_bus *bus = mcore->dev->bus;
+       struct ssb_device *dev;
+       unsigned long hz, ns;
+       unsigned int irq, i;
+
+       if (!mcore->dev)
+               return; /* We don't have a MIPS core */
+
+       ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n");
+
+       hz = ssb_clockspeed(bus);
+       if (!hz)
+               hz = 100000000;
+       ns = 1000000000 / hz;
+
+//TODO
+#if 0
+       if (have EXTIF) {
+               /* Initialize extif so we can get to the LEDs and external UART */
+               W_REG(&eir->prog_config, CF_EN);
+
+               /* Set timing for the flash */
+               tmp = CEIL(10, ns) << FW_W3_SHIFT;      /* W3 = 10nS */
+               tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
+               tmp = tmp | CEIL(120, ns);              /* W0 = 120nS */
+               W_REG(&eir->prog_waitcount, tmp);       /* 0x01020a0c for a 100Mhz clock */
+
+               /* Set programmable interface timing for external uart */
+               tmp = CEIL(10, ns) << FW_W3_SHIFT;      /* W3 = 10nS */
+               tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
+               tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
+               tmp = tmp | CEIL(120, ns);              /* W0 = 120nS */
+               W_REG(&eir->prog_waitcount, tmp);
+       }
+       else... chipcommon
+#endif
+       if (bus->chipco.dev)
+               ssb_chipco_timing_init(&bus->chipco, ns);
+
+       /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
+       for (irq = 2, i = 0; i < bus->nr_devices; i++) {
+               dev = &(bus->devices[i]);
+               dev->irq = ssb_mips_irq(dev) + 2;
+               switch(dev->id.coreid) {
+                       case SSB_DEV_USB11_HOST:
+                               /* shouldn't need a separate irq line for non-4710, most of them have a proper
+                                * external usb controller on the pci */
+                               if ((bus->chip_id == 0x4710) && (irq <= 4)) {
+                                       set_irq(dev, irq++);
+                                       break;
+                               }
+                       case SSB_DEV_PCI:
+                       case SSB_DEV_ETHERNET:
+                       case SSB_DEV_80211:
+                       case SSB_DEV_USB20_HOST:
+                               /* These devices get their own IRQ line if available, the rest goes on IRQ0 */
+                               if (irq <= 4) {
+                                       set_irq(dev, irq++);
+                                       break;
+                               }
+               }
+       }
+
+       ssb_mips_serial_init(mcore);
+       ssb_mips_flash_detect(mcore);
+}
diff --git a/target/linux/brcm47xx-2.6/files/drivers/ssb/driver_pci/pcicore.c b/target/linux/brcm47xx-2.6/files/drivers/ssb/driver_pci/pcicore.c
deleted file mode 100644 (file)
index 3ad9703..0000000
+++ /dev/null
@@ -1,551 +0,0 @@
-/*
- * Sonics Silicon Backplane
- * Broadcom PCI-core driver
- *
- * Copyright 2005, Broadcom Corporation
- * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
- *
- * Licensed under the GNU/GPL. See COPYING for details.
- */
-
-#include <linux/ssb/ssb.h>
-#include <linux/pci.h>
-#include <linux/delay.h>
-
-#include "../ssb_private.h"
-
-static inline
-u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
-{
-       return ssb_read32(pc->dev, offset);
-}
-
-static inline
-void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
-{
-       ssb_write32(pc->dev, offset, value);
-}
-
-/**************************************************
- * Code for hostmode operation.
- **************************************************/
-
-#ifdef CONFIG_SSB_PCICORE_HOSTMODE
-
-#include <asm/paccess.h>
-/* Read the bus and catch bus exceptions. This is MIPS specific. */
-#define mips_busprobe(val, addr)       get_dbe((val), (addr))
-
-/* Assume one-hot slot wiring */
-#define SSB_PCI_SLOT_MAX       16
-
-/* Global lock is OK, as we won't have more than one extpci anyway. */
-static DEFINE_SPINLOCK(cfgspace_lock);
-/* Core to access the external PCI config space. Can only have one. */
-static struct ssb_pcicore *extpci_core;
-
-u32 pci_iobase = 0x100;
-u32 pci_membase = SSB_PCI_DMA;
-
-int pcibios_plat_dev_init(struct pci_dev *d)
-{
-       struct resource *res;
-       int pos, size;
-       u32 *base;
-
-       printk("PCI: Fixing up device %s\n", pci_name(d));
-
-       /* Fix up resource bases */
-       for (pos = 0; pos < 6; pos++) {
-               res = &d->resource[pos];
-               base = ((res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase);
-               if (res->end) {
-                       size = res->end - res->start + 1;
-                       if (*base & (size - 1))
-                               *base = (*base + size) & ~(size - 1);
-                       res->start = *base;
-                       res->end = res->start + size - 1;
-                       *base += size;
-                       pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
-               }
-               /* Fix up PCI bridge BAR0 only */
-               if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
-                       break;
-       }
-       /* Fix up interrupt lines */
-       d->irq = ssb_mips_irq(extpci_core->dev) + 2;
-       pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
-
-       return 0;
-}
-
-static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
-{
-       if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
-               return;
-
-       printk("PCI: fixing up bridge\n");
-
-       /* Enable PCI bridge bus mastering and memory space */
-       pci_set_master(dev);
-       pcibios_enable_device(dev, ~0);
-
-       /* Enable PCI bridge BAR1 prefetch and burst */
-       pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
-
-       /* Make sure our latency is high enough to handle the devices behind us */
-       pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xa8);
-}
-DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
-
-int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
-{
-       return ssb_mips_irq(extpci_core->dev) + 2;
-}
-
-static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
-                            unsigned int bus, unsigned int dev,
-                            unsigned int func, unsigned int off)
-{
-       u32 addr = 0;
-       u32 tmp;
-
-       if (unlikely(pc->cardbusmode && dev > 1))
-               goto out;
-       if (bus == 0) {//FIXME busnumber ok?
-               /* Type 0 transaction */
-               if (unlikely(dev >= SSB_PCI_SLOT_MAX))
-                       goto out;
-               /* Slide the window */
-               tmp = SSB_PCICORE_SBTOPCI_CFG0;
-               tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK);
-               pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp);
-               /* Calculate the address */
-               addr = SSB_PCI_CFG;
-               addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK);
-               addr |= (func << 8);
-               addr |= (off & ~3);
-       } else {
-               /* Type 1 transaction */
-               pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
-                               SSB_PCICORE_SBTOPCI_CFG1);
-               /* Calculate the address */
-               addr = SSB_PCI_CFG;
-               addr |= (bus << 16);
-               addr |= (dev << 11);
-               addr |= (func << 8);
-               addr |= (off & ~3);
-       }
-out:
-       return addr;
-}
-
-static int ssb_extpci_read_config(struct ssb_pcicore *pc,
-                                 unsigned int bus, unsigned int dev,
-                                 unsigned int func, unsigned int off,
-                                 void *buf, int len)
-{
-       int err = -EINVAL;
-       u32 addr, val;
-       void __iomem *mmio;
-
-       assert(pc->hostmode);
-       if (unlikely(len != 1 && len != 2 && len != 4))
-               goto out;
-       addr = get_cfgspace_addr(pc, bus, dev, func, off);
-       if (unlikely(!addr))
-               goto out;
-       err = -ENOMEM;
-       mmio = ioremap_nocache(addr, len);
-       if (!mmio)
-               goto out;
-
-       if (mips_busprobe(val, (u32 *) mmio)) {
-               val = 0xffffffff;
-               goto unmap;
-       }
-       
-       val >>= (8 * (off & 3));
-
-       switch (len) {
-       case 1:
-               *((u8 *)buf) = (u8)val;
-               break;
-       case 2:
-               *((u16 *)buf) = (u16)val;
-               break;
-       case 4:
-               *((u32 *)buf) = (u32)val;
-               break;
-       }
-       err = 0;
-unmap:
-       iounmap(mmio);
-out:
-       return err;
-}
-
-static int ssb_extpci_write_config(struct ssb_pcicore *pc,
-                                  unsigned int bus, unsigned int dev,
-                                  unsigned int func, unsigned int off,
-                                  const void *buf, int len)
-{
-       int err = -EINVAL;
-       u32 addr, val = 0;
-       void __iomem *mmio;
-
-       assert(pc->hostmode);
-       if (unlikely(len != 1 && len != 2 && len != 4))
-               goto out;
-       addr = get_cfgspace_addr(pc, bus, dev, func, off);
-       if (unlikely(!addr))
-               goto out;
-       err = -ENOMEM;
-       mmio = ioremap_nocache(addr, len);
-       if (!mmio)
-               goto out;
-
-       if (mips_busprobe(val, (u32 *) mmio)) {
-               val = 0xffffffff;
-               goto unmap;
-       }
-
-       switch (len) {
-       case 1:
-               val &= ~(0xFF << (8 * (off & 3)));
-               val |= *((const u8 *)buf) << (8 * (off & 3));
-               break;
-       case 2:
-               val &= ~(0xFFFF << (8 * (off & 3)));
-               val |= *((const u16 *)buf) << (8 * (off & 3));
-               break;
-       case 4:
-               val = *((const u32 *)buf);
-               break;
-       }
-       writel(val, mmio);
-
-       err = 0;
-unmap:
-       iounmap(mmio);
-out:
-       return err;
-}
-
-static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn,
-                                  int reg, int size, u32 *val)
-{
-       unsigned long flags;
-       int err;
-
-       spin_lock_irqsave(&cfgspace_lock, flags);
-       err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn),
-                                    PCI_FUNC(devfn), reg, val, size);
-       spin_unlock_irqrestore(&cfgspace_lock, flags);
-
-       return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
-}
-
-static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn,
-                                   int reg, int size, u32 val)
-{
-       unsigned long flags;
-       int err;
-
-       spin_lock_irqsave(&cfgspace_lock, flags);
-       err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn),
-                                     PCI_FUNC(devfn), reg, &val, size);
-       spin_unlock_irqrestore(&cfgspace_lock, flags);
-
-       return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
-}
-
-static struct pci_ops ssb_pcicore_pciops = {
-       .read   = ssb_pcicore_read_config,
-       .write  = ssb_pcicore_write_config,
-};
-
-static struct resource ssb_pcicore_mem_resource = {
-       .name   = "SSB PCIcore external memory",
-       .start  = SSB_PCI_DMA,
-       .end    = (u32)SSB_PCI_DMA + (u32)SSB_PCI_DMA_SZ - 1,
-       .flags  = IORESOURCE_MEM,
-};
-
-static struct resource ssb_pcicore_io_resource = {
-       .name   = "SSB PCIcore external I/O",
-       .start  = 0x100,
-       .end    = 0x7FF,
-       .flags  = IORESOURCE_IO,
-};
-
-static struct pci_controller ssb_pcicore_controller = {
-       .pci_ops        = &ssb_pcicore_pciops,
-       .io_resource    = &ssb_pcicore_io_resource,
-       .mem_resource   = &ssb_pcicore_mem_resource,
-       .mem_offset     = 0x24000000,
-};
-
-static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
-{
-       u32 val;
-
-       assert(!extpci_core);
-       extpci_core = pc;
-
-       ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
-       /* Reset devices on the external PCI bus */
-       val = SSB_PCICORE_CTL_RST_OE;
-       val |= SSB_PCICORE_CTL_CLK_OE;
-       pcicore_write32(pc, SSB_PCICORE_CTL, val);
-       val |= SSB_PCICORE_CTL_CLK; /* Clock on */
-       pcicore_write32(pc, SSB_PCICORE_CTL, val);
-       udelay(150);
-       val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
-       pcicore_write32(pc, SSB_PCICORE_CTL, val);
-       val = SSB_PCICORE_ARBCTL_INTERN;
-       pcicore_write32(pc, SSB_PCICORE_ARBCTL, val); 
-       udelay(1);
-
-       //TODO cardbus mode
-
-       /* 64MB I/O window */
-       pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
-                       SSB_PCICORE_SBTOPCI_IO);
-       /* 64MB config space */
-       pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
-                       SSB_PCICORE_SBTOPCI_CFG0);
-       /* 1GB memory window */
-       pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
-                       SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
-
-       /* Enable PCI bridge BAR0 prefetch and burst */
-       val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-       ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 4);
-
-       /* Enable PCI interrupts */
-       pcicore_write32(pc, SSB_PCICORE_IMASK,
-                       SSB_PCICORE_IMASK_INTA);
-
-       /* Ok, ready to run, register it to the system.
-        * The following needs change, if we want to port hostmode
-        * to non-MIPS platform. */
-       set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
-       mdelay(300);
-       register_pci_controller(&ssb_pcicore_controller);
-}
-
-static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
-{
-       struct ssb_bus *bus = pc->dev->bus;
-       u16 chipid_top;
-       u32 tmp;
-
-       chipid_top = (bus->chip_id & 0xFF00);
-       if (chipid_top != 0x4700 &&
-           chipid_top != 0x5300)
-               return 0;
-
-       if (bus->sprom.r1.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
-               return 0;
-
-       /* The 200-pin BCM4712 package does not bond out PCI. Even when
-        * PCI is bonded out, some boards may leave the pins floating. */
-       if (bus->chip_id == 0x4712) {
-               if (bus->chip_package == SSB_CHIPPACK_BCM4712S)
-                       return 0;
-               if (bus->chip_package == SSB_CHIPPACK_BCM4712M)
-                       return 0;
-       }
-       if (bus->chip_id == 0x5350)
-               return 0;
-
-       return !mips_busprobe(tmp, (u32 *) (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE)));
-}
-#endif /* CONFIG_SSB_PCICORE_HOSTMODE */
-
-
-/**************************************************
- * Generic and Clientmode operation code.
- **************************************************/
-
-static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
-{
-       /* Disable PCI interrupts. */
-       ssb_write32(pc->dev, SSB_INTVEC, 0);
-}
-
-void ssb_pcicore_init(struct ssb_pcicore *pc)
-{
-       struct ssb_device *dev = pc->dev;
-       struct ssb_bus *bus;
-
-       if (!dev)
-               return;
-       bus = dev->bus;
-       ssb_device_enable(dev, 0);
-
-#ifdef CONFIG_SSB_PCICORE_HOSTMODE
-       pc->hostmode = pcicore_is_in_hostmode(pc);
-       if (pc->hostmode)
-               ssb_pcicore_init_hostmode(pc);
-#endif /* CONFIG_SSB_PCICORE_HOSTMODE */
-       if (!pc->hostmode)
-               ssb_pcicore_init_clientmode(pc);
-}
-
-static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)
-{
-       pcicore_write32(pc, 0x130, address);
-       return pcicore_read32(pc, 0x134);
-}
-
-static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
-{
-       pcicore_write32(pc, 0x130, address);
-       pcicore_write32(pc, 0x134, data);
-}
-
-static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
-                               u8 address, u16 data)
-{
-       const u16 mdio_control = 0x128;
-       const u16 mdio_data = 0x12C;
-       u32 v;
-       int i;
-
-       v = 0x80; /* Enable Preamble Sequence */
-       v |= 0x2; /* MDIO Clock Divisor */
-       pcicore_write32(pc, mdio_control, v);
-
-       v = (1 << 30); /* Start of Transaction */
-       v |= (1 << 28); /* Write Transaction */
-       v |= (1 << 17); /* Turnaround */
-       v |= (u32)device << 22;
-       v |= (u32)address << 18;
-       v |= data;
-       pcicore_write32(pc, mdio_data, v);
-       udelay(10);
-       for (i = 0; i < 10; i++) {
-               v = pcicore_read32(pc, mdio_control);
-               if (v & 0x100 /* Trans complete */)
-                       break;
-               msleep(1);
-       }
-       pcicore_write32(pc, mdio_control, 0);
-}
-
-static void ssb_broadcast_value(struct ssb_device *dev,
-                               u32 address, u32 data)
-{
-       /* This is used for both, PCI and ChipCommon core, so be careful. */
-       BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
-       BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
-
-       ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
-       ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
-       ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
-       ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
-}
-
-static void ssb_commit_settings(struct ssb_bus *bus)
-{
-       struct ssb_device *dev;
-
-       dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
-       assert(dev);
-       /* This forces an update of the cached registers. */
-       ssb_broadcast_value(dev, 0xFD8, 0);
-}
-
-int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
-                                  struct ssb_device *dev)
-{
-       struct ssb_device *pdev = pc->dev;
-       struct ssb_bus *bus;
-       int err = 0;
-       u32 tmp;
-
-       might_sleep();
-
-       if (!pdev)
-               goto out;
-       bus = pdev->bus;
-
-       /* Enable interrupts for this device. */
-       if (bus->host_pci &&
-           ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
-               u32 coremask;
-
-               /* Calculate the "coremask" for the device. */
-               coremask = (1 << dev->core_index);
-
-               err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
-               if (err)
-                       goto out;
-               tmp |= coremask << 8;
-               err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp);
-               if (err)
-                       goto out;
-       } else {
-               u32 intvec;
-
-               intvec = ssb_read32(pdev, SSB_INTVEC);
-               tmp = ssb_read32(dev, SSB_TPSFLAG);
-               tmp &= SSB_TPSFLAG_BPFLAG;
-               intvec |= tmp;
-               ssb_write32(pdev, SSB_INTVEC, intvec);
-       }
-
-       /* Setup PCIcore operation. */
-       if (pc->setup_done)
-               goto out;
-       if (pdev->id.coreid == SSB_DEV_PCI) {
-               tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
-               tmp |= SSB_PCICORE_SBTOPCI_PREF;
-               tmp |= SSB_PCICORE_SBTOPCI_BURST;
-               pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
-
-               if (pdev->id.revision < 5) {
-                       tmp = ssb_read32(pdev, SSB_IMCFGLO);
-                       tmp &= ~SSB_IMCFGLO_SERTO;
-                       tmp |= 2;
-                       tmp &= ~SSB_IMCFGLO_REQTO;
-                       tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
-                       ssb_write32(pdev, SSB_IMCFGLO, tmp);
-                       ssb_commit_settings(bus);
-               } else if (pdev->id.revision >= 11) {
-                       tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
-                       tmp |= SSB_PCICORE_SBTOPCI_MRM;
-                       pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
-               }
-       } else {
-               assert(pdev->id.coreid == SSB_DEV_PCIE);
-               //TODO: Better make defines for all these magic PCIE values.
-               if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
-                       /* TLP Workaround register. */
-                       tmp = ssb_pcie_read(pc, 0x4);
-                       tmp |= 0x8;
-                       ssb_pcie_write(pc, 0x4, tmp);
-               }
-               if (pdev->id.revision == 0) {
-                       const u8 serdes_rx_device = 0x1F;
-
-                       ssb_pcie_mdio_write(pc, serdes_rx_device,
-                                           2 /* Timer */, 0x8128);
-                       ssb_pcie_mdio_write(pc, serdes_rx_device,
-                                           6 /* CDR */, 0x0100);
-                       ssb_pcie_mdio_write(pc, serdes_rx_device,
-                                           7 /* CDR BW */, 0x1466);
-               } else if (pdev->id.revision == 1) {
-                       /* DLLP Link Control register. */
-                       tmp = ssb_pcie_read(pc, 0x100);
-                       tmp |= 0x40;
-                       ssb_pcie_write(pc, 0x100, tmp);
-               }
-       }
-       pc->setup_done = 1;
-out:
-       return err;
-}
-EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable);
diff --git a/target/linux/brcm47xx-2.6/files/drivers/ssb/driver_pcicore.c b/target/linux/brcm47xx-2.6/files/drivers/ssb/driver_pcicore.c
new file mode 100644 (file)
index 0000000..a59dff0
--- /dev/null
@@ -0,0 +1,556 @@
+/*
+ * Sonics Silicon Backplane
+ * Broadcom PCI-core driver
+ *
+ * Copyright 2005, Broadcom Corporation
+ * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+#include <linux/ssb/ssb.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+
+#include "ssb_private.h"
+
+
+static inline
+u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
+{
+       return ssb_read32(pc->dev, offset);
+}
+
+static inline
+void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
+{
+       ssb_write32(pc->dev, offset, value);
+}
+
+/**************************************************
+ * Code for hostmode operation.
+ **************************************************/
+
+#ifdef CONFIG_SSB_PCICORE_HOSTMODE
+
+#include <asm/paccess.h>
+/* Read the bus and catch bus exceptions. This is MIPS specific. */
+#define mips_busprobe(val, addr)       get_dbe((val), (addr))
+
+/* Assume one-hot slot wiring */
+#define SSB_PCI_SLOT_MAX       16
+
+/* Global lock is OK, as we won't have more than one extpci anyway. */
+static DEFINE_SPINLOCK(cfgspace_lock);
+/* Core to access the external PCI config space. Can only have one. */
+static struct ssb_pcicore *extpci_core;
+
+u32 pci_iobase = 0x100;
+u32 pci_membase = SSB_PCI_DMA;
+
+int pcibios_plat_dev_init(struct pci_dev *d)
+{
+       struct resource *res;
+       int pos, size;
+       u32 *base;
+
+       printk("PCI: Fixing up device %s\n", pci_name(d));
+
+       /* Fix up resource bases */
+       for (pos = 0; pos < 6; pos++) {
+               res = &d->resource[pos];
+               base = ((res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase);
+               if (res->end) {
+                       size = res->end - res->start + 1;
+                       if (*base & (size - 1))
+                               *base = (*base + size) & ~(size - 1);
+                       res->start = *base;
+                       res->end = res->start + size - 1;
+                       *base += size;
+                       pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
+               }
+               /* Fix up PCI bridge BAR0 only */
+               if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
+                       break;
+       }
+       /* Fix up interrupt lines */
+       d->irq = ssb_mips_irq(extpci_core->dev) + 2;
+       pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
+
+       return 0;
+}
+
+static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
+{
+       if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
+               return;
+
+       printk("PCI: fixing up bridge\n");
+
+       /* Enable PCI bridge bus mastering and memory space */
+       pci_set_master(dev);
+       pcibios_enable_device(dev, ~0);
+
+       /* Enable PCI bridge BAR1 prefetch and burst */
+       pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
+
+int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+       return ssb_mips_irq(extpci_core->dev) + 2;
+}
+
+static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
+                            unsigned int bus, unsigned int dev,
+                            unsigned int func, unsigned int off)
+{
+       u32 addr = 0;
+       u32 tmp;
+
+       if (unlikely(pc->cardbusmode && dev > 1))
+               goto out;
+       if (bus == 0) {
+               /* Type 0 transaction */
+               if (unlikely(dev >= SSB_PCI_SLOT_MAX))
+                       goto out;
+               /* Slide the window */
+               tmp = SSB_PCICORE_SBTOPCI_CFG0;
+               tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK);
+               pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp);
+               /* Calculate the address */
+               addr = SSB_PCI_CFG;
+               addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK);
+               addr |= (func << 8);
+               addr |= (off & ~3);
+       } else {
+               /* Type 1 transaction */
+               pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
+                               SSB_PCICORE_SBTOPCI_CFG1);
+               /* Calculate the address */
+               addr = SSB_PCI_CFG;
+               addr |= (bus << 16);
+               addr |= (dev << 11);
+               addr |= (func << 8);
+               addr |= (off & ~3);
+       }
+out:
+       return addr;
+}
+
+static int ssb_extpci_read_config(struct ssb_pcicore *pc,
+                                 unsigned int bus, unsigned int dev,
+                                 unsigned int func, unsigned int off,
+                                 void *buf, int len)
+{
+       int err = -EINVAL;
+       u32 addr, val;
+       void __iomem *mmio;
+
+       assert(pc->hostmode);
+       if (unlikely(len != 1 && len != 2 && len != 4))
+               goto out;
+       addr = get_cfgspace_addr(pc, bus, dev, func, off);
+       if (unlikely(!addr))
+               goto out;
+       err = -ENOMEM;
+       mmio = ioremap_nocache(addr, len);
+       if (!mmio)
+               goto out;
+
+       if (mips_busprobe(val, (u32 *) mmio)) {
+               val = 0xffffffff;
+               goto unmap;
+       }
+
+       val = readl(mmio);
+       val >>= (8 * (off & 3));
+
+       switch (len) {
+       case 1:
+               *((u8 *)buf) = (u8)val;
+               break;
+       case 2:
+               *((u16 *)buf) = (u16)val;
+               break;
+       case 4:
+               *((u32 *)buf) = (u32)val;
+               break;
+       }
+       err = 0;
+unmap:
+       iounmap(mmio);
+out:
+       return err;
+}
+
+static int ssb_extpci_write_config(struct ssb_pcicore *pc,
+                                  unsigned int bus, unsigned int dev,
+                                  unsigned int func, unsigned int off,
+                                  const void *buf, int len)
+{
+       int err = -EINVAL;
+       u32 addr, val = 0;
+       void __iomem *mmio;
+
+       assert(pc->hostmode);
+       if (unlikely(len != 1 && len != 2 && len != 4))
+               goto out;
+       addr = get_cfgspace_addr(pc, bus, dev, func, off);
+       if (unlikely(!addr))
+               goto out;
+       err = -ENOMEM;
+       mmio = ioremap_nocache(addr, len);
+       if (!mmio)
+               goto out;
+
+       if (mips_busprobe(val, (u32 *) mmio)) {
+               val = 0xffffffff;
+               goto unmap;
+       }
+
+       switch (len) {
+       case 1:
+               val = readl(mmio);
+               val &= ~(0xFF << (8 * (off & 3)));
+               val |= *((const u8 *)buf) << (8 * (off & 3));
+               break;
+       case 2:
+               val = readl(mmio);
+               val &= ~(0xFFFF << (8 * (off & 3)));
+               val |= *((const u16 *)buf) << (8 * (off & 3));
+               break;
+       case 4:
+               val = *((const u32 *)buf);
+               break;
+       }
+       writel(*((const u32 *)buf), mmio);
+
+       err = 0;
+unmap:
+       iounmap(mmio);
+out:
+       return err;
+}
+
+static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn,
+                                  int reg, int size, u32 *val)
+{
+       unsigned long flags;
+       int err;
+
+       spin_lock_irqsave(&cfgspace_lock, flags);
+       err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn),
+                                    PCI_FUNC(devfn), reg, val, size);
+       spin_unlock_irqrestore(&cfgspace_lock, flags);
+
+       return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
+}
+
+static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn,
+                                   int reg, int size, u32 val)
+{
+       unsigned long flags;
+       int err;
+
+       spin_lock_irqsave(&cfgspace_lock, flags);
+       err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn),
+                                     PCI_FUNC(devfn), reg, &val, size);
+       spin_unlock_irqrestore(&cfgspace_lock, flags);
+
+       return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops ssb_pcicore_pciops = {
+       .read   = ssb_pcicore_read_config,
+       .write  = ssb_pcicore_write_config,
+};
+
+static struct resource ssb_pcicore_mem_resource = {
+       .name   = "SSB PCIcore external memory",
+       .start  = SSB_PCI_DMA,
+       .end    = (u32)SSB_PCI_DMA + (u32)SSB_PCI_DMA_SZ - 1,
+       .flags  = IORESOURCE_MEM,
+};
+
+static struct resource ssb_pcicore_io_resource = {
+       .name   = "SSB PCIcore external I/O",
+       .start  = 0x100,
+       .end    = 0x7FF,
+       .flags  = IORESOURCE_IO,
+};
+
+static struct pci_controller ssb_pcicore_controller = {
+       .pci_ops        = &ssb_pcicore_pciops,
+       .io_resource    = &ssb_pcicore_io_resource,
+       .mem_resource   = &ssb_pcicore_mem_resource,
+       .mem_offset     = 0x24000000,
+};
+
+static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
+{
+       u32 val;
+
+       if (extpci_core) {
+               WARN_ON(1);
+               return;
+       }
+       extpci_core = pc;
+
+       ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
+       /* Reset devices on the external PCI bus */
+       val = SSB_PCICORE_CTL_RST_OE;
+       val |= SSB_PCICORE_CTL_CLK_OE;
+       pcicore_write32(pc, SSB_PCICORE_CTL, val);
+       val |= SSB_PCICORE_CTL_CLK; /* Clock on */
+       pcicore_write32(pc, SSB_PCICORE_CTL, val);
+       udelay(150);
+       val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
+       pcicore_write32(pc, SSB_PCICORE_CTL, val);
+       udelay(1);
+
+       //TODO cardbus mode
+
+       /* 64MB I/O window */
+       pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
+                       SSB_PCICORE_SBTOPCI_IO);
+       /* 64MB config space */
+       pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
+                       SSB_PCICORE_SBTOPCI_CFG0);
+       /* 1GB memory window */
+       pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
+                       SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
+
+       /* Enable PCI bridge BAR0 prefetch and burst */
+       val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+       ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2);
+       /* Clear error conditions */
+       val = 0;
+       ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2);
+
+       /* Enable PCI interrupts */
+       pcicore_write32(pc, SSB_PCICORE_IMASK,
+                       SSB_PCICORE_IMASK_INTA);
+
+       /* Ok, ready to run, register it to the system.
+        * The following needs change, if we want to port hostmode
+        * to non-MIPS platform. */
+       set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
+       register_pci_controller(&ssb_pcicore_controller);
+}
+
+static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
+{
+       struct ssb_bus *bus = pc->dev->bus;
+       u16 chipid_top;
+       u32 tmp;
+
+       chipid_top = (bus->chip_id & 0xFF00);
+       if (chipid_top != 0x4700 &&
+           chipid_top != 0x5300)
+               return 0;
+
+       if (bus->sprom.r1.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
+               return 0;
+
+       /* The 200-pin BCM4712 package does not bond out PCI. Even when
+        * PCI is bonded out, some boards may leave the pins floating. */
+       if (bus->chip_id == 0x4712) {
+               if (bus->chip_package == SSB_CHIPPACK_BCM4712S)
+                       return 0;
+               if (bus->chip_package == SSB_CHIPPACK_BCM4712M)
+                       return 0;
+       }
+       if (bus->chip_id == 0x5350)
+               return 0;
+
+       return !mips_busprobe(tmp, (u32 *) (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE)));
+}
+#endif /* CONFIG_SSB_PCICORE_HOSTMODE */
+
+
+/**************************************************
+ * Generic and Clientmode operation code.
+ **************************************************/
+
+static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
+{
+       /* Disable PCI interrupts. */
+       ssb_write32(pc->dev, SSB_INTVEC, 0);
+}
+
+void ssb_pcicore_init(struct ssb_pcicore *pc)
+{
+       struct ssb_device *dev = pc->dev;
+       struct ssb_bus *bus;
+
+       if (!dev)
+               return;
+       bus = dev->bus;
+       if (!ssb_device_is_enabled(dev))
+               ssb_device_enable(dev, 0);
+
+#ifdef CONFIG_SSB_PCICORE_HOSTMODE
+       pc->hostmode = pcicore_is_in_hostmode(pc);
+       if (pc->hostmode)
+               ssb_pcicore_init_hostmode(pc);
+#endif /* CONFIG_SSB_PCICORE_HOSTMODE */
+       if (!pc->hostmode)
+               ssb_pcicore_init_clientmode(pc);
+}
+
+static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)
+{
+       pcicore_write32(pc, 0x130, address);
+       return pcicore_read32(pc, 0x134);
+}
+
+static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
+{
+       pcicore_write32(pc, 0x130, address);
+       pcicore_write32(pc, 0x134, data);
+}
+
+static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
+                               u8 address, u16 data)
+{
+       const u16 mdio_control = 0x128;
+       const u16 mdio_data = 0x12C;
+       u32 v;
+       int i;
+
+       v = 0x80; /* Enable Preamble Sequence */
+       v |= 0x2; /* MDIO Clock Divisor */
+       pcicore_write32(pc, mdio_control, v);
+
+       v = (1 << 30); /* Start of Transaction */
+       v |= (1 << 28); /* Write Transaction */
+       v |= (1 << 17); /* Turnaround */
+       v |= (u32)device << 22;
+       v |= (u32)address << 18;
+       v |= data;
+       pcicore_write32(pc, mdio_data, v);
+       udelay(10);
+       for (i = 0; i < 10; i++) {
+               v = pcicore_read32(pc, mdio_control);
+               if (v & 0x100 /* Trans complete */)
+                       break;
+               msleep(1);
+       }
+       pcicore_write32(pc, mdio_control, 0);
+}
+
+static void ssb_broadcast_value(struct ssb_device *dev,
+                               u32 address, u32 data)
+{
+       /* This is used for both, PCI and ChipCommon core, so be careful. */
+       BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
+       BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
+
+       ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
+       ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
+       ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
+       ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
+}
+
+static void ssb_commit_settings(struct ssb_bus *bus)
+{
+       struct ssb_device *dev;
+
+       dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
+       assert(dev);
+       /* This forces an update of the cached registers. */
+       ssb_broadcast_value(dev, 0xFD8, 0);
+}
+
+int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
+                                  struct ssb_device *dev)
+{
+       struct ssb_device *pdev = pc->dev;
+       struct ssb_bus *bus;
+       int err = 0;
+       u32 tmp;
+
+       might_sleep();
+
+       if (!pdev)
+               goto out;
+       bus = pdev->bus;
+
+       /* Enable interrupts for this device. */
+       if (bus->host_pci &&
+           ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
+               u32 coremask;
+
+               /* Calculate the "coremask" for the device. */
+               coremask = (1 << dev->core_index);
+
+               err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
+               if (err)
+                       goto out;
+               tmp |= coremask << 8;
+               err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp);
+               if (err)
+                       goto out;
+       } else {
+               u32 intvec;
+
+               intvec = ssb_read32(pdev, SSB_INTVEC);
+               tmp = ssb_read32(dev, SSB_TPSFLAG);
+               tmp &= SSB_TPSFLAG_BPFLAG;
+               intvec |= tmp;
+               ssb_write32(pdev, SSB_INTVEC, intvec);
+       }
+
+       /* Setup PCIcore operation. */
+       if (pc->setup_done)
+               goto out;
+       if (pdev->id.coreid == SSB_DEV_PCI) {
+               tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
+               tmp |= SSB_PCICORE_SBTOPCI_PREF;
+               tmp |= SSB_PCICORE_SBTOPCI_BURST;
+               pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
+
+               if (pdev->id.revision < 5) {
+                       tmp = ssb_read32(pdev, SSB_IMCFGLO);
+                       tmp &= ~SSB_IMCFGLO_SERTO;
+                       tmp |= 2;
+                       tmp &= ~SSB_IMCFGLO_REQTO;
+                       tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
+                       ssb_write32(pdev, SSB_IMCFGLO, tmp);
+                       ssb_commit_settings(bus);
+               } else if (pdev->id.revision >= 11) {
+                       tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
+                       tmp |= SSB_PCICORE_SBTOPCI_MRM;
+                       pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
+               }
+       } else {
+               assert(pdev->id.coreid == SSB_DEV_PCIE);
+               //TODO: Better make defines for all these magic PCIE values.
+               if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
+                       /* TLP Workaround register. */
+                       tmp = ssb_pcie_read(pc, 0x4);
+                       tmp |= 0x8;
+                       ssb_pcie_write(pc, 0x4, tmp);
+               }
+               if (pdev->id.revision == 0) {
+                       const u8 serdes_rx_device = 0x1F;
+
+                       ssb_pcie_mdio_write(pc, serdes_rx_device,
+                                           2 /* Timer */, 0x8128);
+                       ssb_pcie_mdio_write(pc, serdes_rx_device,
+                                           6 /* CDR */, 0x0100);
+                       ssb_pcie_mdio_write(pc, serdes_rx_device,
+                                           7 /* CDR BW */, 0x1466);
+               } else if (pdev->id.revision == 1) {
+                       /* DLLP Link Control register. */
+                       tmp = ssb_pcie_read(pc, 0x100);
+                       tmp |= 0x40;
+                       ssb_pcie_write(pc, 0x100, tmp);
+               }
+       }
+       pc->setup_done = 1;
+out:
+       return err;
+}
+EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable);
diff --git a/target/linux/brcm47xx-2.6/files/drivers/ssb/main.c b/target/linux/brcm47xx-2.6/files/drivers/ssb/main.c
new file mode 100644 (file)
index 0000000..a2d2231
--- /dev/null
@@ -0,0 +1,1054 @@
+/*
+ * Sonics Silicon Backplane
+ * Subsystem core
+ *
+ * Copyright 2005, Broadcom Corporation
+ * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+#include "ssb_private.h"
+
+#include <linux/delay.h>
+#include <linux/ssb/ssb.h>
+#include <linux/ssb/ssb_regs.h>
+
+#ifdef CONFIG_SSB_PCIHOST
+# include <linux/pci.h>
+#endif
+
+#ifdef CONFIG_SSB_PCMCIAHOST
+# include <pcmcia/cs_types.h>
+# include <pcmcia/cs.h>
+# include <pcmcia/cistpl.h>
+# include <pcmcia/ds.h>
+#endif
+
+
+MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
+MODULE_LICENSE("GPL");
+
+
+static LIST_HEAD(attach_queue);
+static LIST_HEAD(buses);
+static int nr_buses;
+static DEFINE_MUTEX(buses_mutex);
+
+static void ssb_buses_lock(void);
+static void ssb_buses_unlock(void);
+
+
+#ifdef CONFIG_SSB_PCIHOST
+struct ssb_bus * ssb_pci_dev_to_bus(struct pci_dev *pdev)
+{
+       struct ssb_bus *bus;
+
+       ssb_buses_lock();
+       list_for_each_entry(bus, &buses, list) {
+               if (bus->bustype == SSB_BUSTYPE_PCI &&
+                   bus->host_pci == pdev)
+                       goto found;
+       }
+       bus = NULL;
+found:
+       ssb_buses_unlock();
+
+       return bus;
+}
+#endif /* CONFIG_SSB_PCIHOST */
+
+static struct ssb_device * ssb_device_get(struct ssb_device *dev)
+{
+       if (dev)
+               get_device(dev->dev);
+       return dev;
+}
+
+static void ssb_device_put(struct ssb_device *dev)
+{
+       if (dev)
+               put_device(dev->dev);
+}
+
+static int ssb_bus_resume(struct ssb_bus *bus)
+{
+       int err;
+
+       ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
+       err = ssb_pcmcia_init(bus);
+       if (err) {
+               /* No need to disable XTAL, as we don't have one on PCMCIA. */
+               return err;
+       }
+       ssb_chipco_resume(&bus->chipco);
+
+       return 0;
+}
+
+static int ssb_device_resume(struct device *dev)
+{
+       struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
+       struct ssb_driver *ssb_drv;
+       struct ssb_bus *bus;
+       int err = 0;
+
+       bus = ssb_dev->bus;
+       if (bus->suspend_cnt == bus->nr_devices) {
+               err = ssb_bus_resume(bus);
+               if (err)
+                       return err;
+       }
+       bus->suspend_cnt--;
+       if (dev->driver) {
+               ssb_drv = drv_to_ssb_drv(dev->driver);
+               if (ssb_drv && ssb_drv->resume)
+                       err = ssb_drv->resume(ssb_dev);
+               if (err)
+                       goto out;
+       }
+out:
+       return err;
+}
+
+static void ssb_bus_suspend(struct ssb_bus *bus, pm_message_t state)
+{
+       ssb_chipco_suspend(&bus->chipco, state);
+       ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
+
+       /* Reset HW state information in memory, so that HW is
+        * completely reinitialized on resume. */
+       bus->mapped_device = NULL;
+#ifdef CONFIG_SSB_DRIVER_PCICORE
+       bus->pcicore.setup_done = 0;
+#endif
+}
+
+static int ssb_device_suspend(struct device *dev, pm_message_t state)
+{
+       struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
+       struct ssb_driver *ssb_drv;
+       struct ssb_bus *bus;
+       int err = 0;
+
+       if (dev->driver) {
+               ssb_drv = drv_to_ssb_drv(dev->driver);
+               if (ssb_drv && ssb_drv->suspend)
+                       err = ssb_drv->suspend(ssb_dev, state);
+               if (err)
+                       goto out;
+       }
+
+       bus = ssb_dev->bus;
+       bus->suspend_cnt++;
+       if (bus->suspend_cnt == bus->nr_devices) {
+               /* All devices suspended. Shutdown the bus. */
+               ssb_bus_suspend(bus, state);
+       }
+
+out:
+       return err;
+}
+
+#ifdef CONFIG_SSB_PCIHOST
+int ssb_devices_freeze(struct ssb_bus *bus)
+{
+       struct ssb_device *dev;
+       struct ssb_driver *drv;
+       int err = 0;
+       int i;
+       pm_message_t state = PMSG_FREEZE;
+
+       for (i = 0; i < bus->nr_devices; i++) {
+               dev = &(bus->devices[i]);
+               if (!dev->dev->driver)
+                       continue;
+               if (!device_is_registered(dev->dev))
+                       continue;
+               drv = drv_to_ssb_drv(dev->dev->driver);
+               if (drv && drv->suspend) {
+                       err = drv->suspend(dev, state);
+                       if (err)
+                               goto out;
+               }
+       }
+out:
+       return err;
+}
+
+int ssb_devices_thaw(struct ssb_bus *bus)
+{
+       struct ssb_device *dev;
+       struct ssb_driver *drv;
+       int err = 0;
+       int i;
+
+       for (i = 0; i < bus->nr_devices; i++) {
+               dev = &(bus->devices[i]);
+               if (!dev->dev->driver)
+                       continue;
+               if (!device_is_registered(dev->dev))
+                       continue;
+               drv = drv_to_ssb_drv(dev->dev->driver);
+               if (drv && drv->resume) {
+                       err = drv->resume(dev);
+                       if (err)
+                               goto out;
+               }
+       }
+out:
+       return err;
+}
+#endif /* CONFIG_SSB_PCIHOST */
+
+static void ssb_device_shutdown(struct device *dev)
+{
+       struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
+       struct ssb_driver *ssb_drv;
+
+       if (!dev->driver)
+               return;
+       ssb_drv = drv_to_ssb_drv(dev->driver);
+       if (ssb_drv && ssb_drv->shutdown)
+               ssb_drv->shutdown(ssb_dev);
+}
+
+static int ssb_device_remove(struct device *dev)
+{
+       struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
+       struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
+
+       if (ssb_drv && ssb_drv->remove)
+               ssb_drv->remove(ssb_dev);
+       ssb_device_put(ssb_dev);
+
+       return 0;
+}
+
+static int ssb_device_probe(struct device *dev)
+{
+       struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
+       struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
+       int err = 0;
+
+       ssb_device_get(ssb_dev);
+       if (ssb_drv && ssb_drv->probe)
+               err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
+       if (err)
+               ssb_device_put(ssb_dev);
+
+       return err;
+}
+
+static int ssb_match_devid(const struct ssb_device_id *tabid,
+                          const struct ssb_device_id *devid)
+{
+       if ((tabid->vendor != devid->vendor) &&
+           tabid->vendor != SSB_ANY_VENDOR)
+               return 0;
+       if ((tabid->coreid != devid->coreid) &&
+           tabid->coreid != SSB_ANY_ID)
+               return 0;
+       if ((tabid->revision != devid->revision) &&
+           tabid->revision != SSB_ANY_REV)
+               return 0;
+       return 1;
+}
+
+static int ssb_bus_match(struct device *dev, struct device_driver *drv)
+{
+       struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
+       struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
+       const struct ssb_device_id *id;
+
+       for (id = ssb_drv->id_table;
+            id->vendor || id->coreid || id->revision;
+            id++) {
+               if (ssb_match_devid(id, &ssb_dev->id))
+                       return 1; /* found */
+       }
+
+       return 0;
+}
+
+static struct bus_type ssb_bustype = {
+       .name           = NULL, /* Intentionally NULL to indicate early boot */
+       .match          = ssb_bus_match,
+       .probe          = ssb_device_probe,
+       .remove         = ssb_device_remove,
+       .shutdown       = ssb_device_shutdown,
+       .suspend        = ssb_device_suspend,
+       .resume         = ssb_device_resume,
+};
+
+#define is_early_boot()                (ssb_bustype.name == NULL)
+
+static void ssb_buses_lock(void)
+{
+       if (!is_early_boot())
+               mutex_lock(&buses_mutex);
+}
+
+static void ssb_buses_unlock(void)
+{
+       if (!is_early_boot())
+               mutex_unlock(&buses_mutex);
+}
+
+static void ssb_devices_unregister(struct ssb_bus *bus)
+{
+       struct ssb_device *sdev;
+       int i;
+
+       for (i = bus->nr_devices - 1; i >= 0; i--) {
+               sdev = &(bus->devices[i]);
+               if (sdev->dev)
+                       device_unregister(sdev->dev);
+       }
+}
+
+void ssb_bus_unregister(struct ssb_bus *bus)
+{
+       ssb_buses_lock();
+       ssb_devices_unregister(bus);
+       list_del(&bus->list);
+       ssb_buses_unlock();
+
+       /* ssb_pcmcia_exit(bus); */
+       ssb_pci_exit(bus);
+       ssb_iounmap(bus);
+}
+EXPORT_SYMBOL(ssb_bus_unregister);
+
+static void ssb_release_dev(struct device *dev)
+{
+       struct __ssb_dev_wrapper *devwrap;
+
+       devwrap = container_of(dev, struct __ssb_dev_wrapper, dev);
+       kfree(devwrap);
+}
+
+static int ssb_devices_register(struct ssb_bus *bus)
+{
+       struct ssb_device *sdev;
+       struct device *dev;
+       struct __ssb_dev_wrapper *devwrap;
+       int i, err = 0;
+       int dev_idx = 0;
+
+       for (i = 0; i < bus->nr_devices; i++) {
+               sdev = &(bus->devices[i]);
+
+               /* We don't register SSB-system devices to the kernel,
+                * as the drivers for them are built into SSB. */
+               switch (sdev->id.coreid) {
+               case SSB_DEV_CHIPCOMMON:
+               case SSB_DEV_PCI:
+               case SSB_DEV_PCIE:
+               case SSB_DEV_PCMCIA:
+               case SSB_DEV_MIPS:
+               case SSB_DEV_MIPS_3302:
+               case SSB_DEV_EXTIF:
+                       continue;
+               }
+
+               devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
+               if (!devwrap) {
+                       ssb_printk(KERN_ERR PFX
+                                  "Could not allocate device\n");
+                       err = -ENOMEM;
+                       goto error;
+               }
+               dev = &devwrap->dev;
+               devwrap->sdev = sdev;
+
+               dev->release = ssb_release_dev;
+               dev->bus = &ssb_bustype;
+               snprintf(dev->bus_id, sizeof(dev->bus_id),
+                        "ssb%d:%d", bus->busnumber, dev_idx);
+
+               switch (bus->bustype) {
+               case SSB_BUSTYPE_PCI:
+#ifdef CONFIG_SSB_PCIHOST
+                       sdev->irq = bus->host_pci->irq;
+                       dev->parent = &bus->host_pci->dev;
+#endif
+                       break;
+               case SSB_BUSTYPE_PCMCIA:
+#ifdef CONFIG_SSB_PCMCIAHOST
+                       dev->parent = &bus->host_pcmcia->dev;
+#endif
+                       break;
+               case SSB_BUSTYPE_SSB:
+                       break;
+               }
+
+               sdev->dev = dev;
+               err = device_register(dev);
+               if (err) {
+                       ssb_printk(KERN_ERR PFX
+                                  "Could not register %s\n",
+                                  dev->bus_id);
+                       /* Set dev to NULL to not unregister
+                        * dev on error unwinding. */
+                       sdev->dev = NULL;
+                       kfree(devwrap);
+                       goto error;
+               }
+               dev_idx++;
+       }
+
+       return 0;
+error:
+       /* Unwind the already registered devices. */
+       ssb_devices_unregister(bus);
+       return err;
+}
+
+/* Needs ssb_buses_lock() */
+static int ssb_attach_queued_buses(void)
+{
+       struct ssb_bus *bus, *n;
+       int err = 0;
+       int drop_them_all = 0;
+
+       list_for_each_entry_safe(bus, n, &attach_queue, list) {
+               if (drop_them_all) {
+                       list_del(&bus->list);
+                       continue;
+               }
+               /* Can't init the PCIcore in ssb_bus_register(), as that
+                * is too early in boot for embedded systems
+                * (no udelay() available). So do it here in attach stage.
+                */
+               ssb_pcicore_init(&bus->pcicore);
+
+               err = ssb_devices_register(bus);
+               if (err) {
+                       drop_them_all = 1;
+                       list_del(&bus->list);
+                       continue;
+               }
+               list_move_tail(&bus->list, &buses);
+       }
+
+       return err;
+}
+
+static void ssb_get_boardtype(struct ssb_bus *bus)
+{//FIXME for pcmcia?
+       if (bus->bustype != SSB_BUSTYPE_PCI) {
+               /* Must set board_vendor, board_type and board_rev
+                * before calling ssb_bus_*_register() */
+               assert(bus->board_vendor && bus->board_type);
+               return;
+       }
+       ssb_pci_get_boardtype(bus);
+}
+
+static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
+{
+       struct ssb_bus *bus = dev->bus;
+
+       offset += dev->core_index * SSB_CORE_SIZE;
+       return readw(bus->mmio + offset);
+}
+
+static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset)
+{
+       struct ssb_bus *bus = dev->bus;
+
+       offset += dev->core_index * SSB_CORE_SIZE;
+       return readl(bus->mmio + offset);
+}
+
+static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
+{
+       struct ssb_bus *bus = dev->bus;
+
+       offset += dev->core_index * SSB_CORE_SIZE;
+       writew(value, bus->mmio + offset);
+}
+
+static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
+{
+       struct ssb_bus *bus = dev->bus;
+
+       offset += dev->core_index * SSB_CORE_SIZE;
+       writel(value, bus->mmio + offset);
+}
+
+static const struct ssb_bus_ops ssb_ssb_ops = {
+       .read16         = ssb_ssb_read16,
+       .read32         = ssb_ssb_read32,
+       .write16        = ssb_ssb_write16,
+       .write32        = ssb_ssb_write32,
+};
+
+static int ssb_bus_register(struct ssb_bus *bus,
+                           unsigned long baseaddr)
+{
+       int err;
+
+       spin_lock_init(&bus->bar_lock);
+       INIT_LIST_HEAD(&bus->list);
+
+       ssb_get_boardtype(bus);
+       /* Powerup the bus */
+       err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
+       if (err)
+               goto out;
+       ssb_buses_lock();
+       bus->busnumber = nr_buses;
+       /* Scan for devices (cores) */
+       err = ssb_bus_scan(bus, baseaddr);
+       if (err)
+               goto err_disable_xtal;
+
+       /* Init PCI-host device (if any) */
+       err = ssb_pci_init(bus);
+       if (err)
+               goto err_unmap;
+       /* Init PCMCIA-host device (if any) */
+       err = ssb_pcmcia_init(bus);
+       if (err)
+               goto err_pci_exit;
+
+       /* Initialize basic system devices (if available) */
+       ssb_chipcommon_init(&bus->chipco);
+       ssb_mipscore_init(&bus->mipscore);
+
+       /* Queue it for attach */
+       list_add_tail(&bus->list, &attach_queue);
+       if (!is_early_boot()) {
+               /* This is not early boot, so we must attach the bus now */
+               err = ssb_attach_queued_buses();
+               if (err)
+                       goto err_dequeue;
+       }
+       nr_buses++;
+       ssb_buses_unlock();
+
+out:
+       return err;
+
+err_dequeue:
+       list_del(&bus->list);
+/* err_pcmcia_exit: */
+/*     ssb_pcmcia_exit(bus); */
+err_pci_exit:
+       ssb_pci_exit(bus);
+err_unmap:
+       ssb_iounmap(bus);
+err_disable_xtal:
+       ssb_buses_unlock();
+       ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
+       return err;
+}
+
+#ifdef CONFIG_SSB_PCIHOST
+int ssb_bus_pcibus_register(struct ssb_bus *bus,
+                           struct pci_dev *host_pci)
+{
+       int err;
+
+       bus->bustype = SSB_BUSTYPE_PCI;
+       bus->host_pci = host_pci;
+       bus->ops = &ssb_pci_ops;
+
+       err = ssb_bus_register(bus, 0);
+       if (!err) {
+               ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
+                          "PCI device %s\n", host_pci->dev.bus_id);
+       }
+
+       return err;
+}
+EXPORT_SYMBOL(ssb_bus_pcibus_register);
+#endif /* CONFIG_SSB_PCIHOST */
+
+#ifdef CONFIG_SSB_PCMCIAHOST
+int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
+                              struct pcmcia_device *pcmcia_dev,
+                              unsigned long baseaddr,
+                              void (*fill_sprom)(struct ssb_sprom *sprom))
+{
+       int err;
+
+       bus->bustype = SSB_BUSTYPE_PCMCIA;
+       bus->host_pcmcia = pcmcia_dev;
+       bus->ops = &ssb_pcmcia_ops;
+       fill_sprom(&bus->sprom);
+
+       err = ssb_bus_register(bus, baseaddr);
+       if (!err) {
+               ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
+                          "PCMCIA device %s\n", pcmcia_dev->devname);
+       }
+
+       return err;
+}
+EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
+#endif /* CONFIG_SSB_PCMCIAHOST */
+
+int ssb_bus_ssbbus_register(struct ssb_bus *bus,
+                           unsigned long baseaddr,
+                           void (*fill_sprom)(struct ssb_sprom *sprom))
+{
+       int err;
+
+       bus->bustype = SSB_BUSTYPE_SSB;
+       bus->ops = &ssb_ssb_ops;
+       fill_sprom(&bus->sprom);
+
+       err = ssb_bus_register(bus, baseaddr);
+       if (!err) {
+               ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at "
+                          "address 0x%08lX\n", baseaddr);
+       }
+
+       return err;
+}
+
+int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
+{
+       drv->drv.name = drv->name;
+       drv->drv.bus = &ssb_bustype;
+       drv->drv.owner = owner;
+
+       return driver_register(&drv->drv);
+}
+EXPORT_SYMBOL(__ssb_driver_register);
+
+void ssb_driver_unregister(struct ssb_driver *drv)
+{
+       driver_unregister(&drv->drv);
+}
+EXPORT_SYMBOL(ssb_driver_unregister);
+
+void ssb_set_devtypedata(struct ssb_device *dev, void *data)
+{
+       struct ssb_bus *bus = dev->bus;
+       struct ssb_device *ent;
+       int i;
+
+       for (i = 0; i < bus->nr_devices; i++) {
+               ent = &(bus->devices[i]);
+               if (ent->id.vendor != dev->id.vendor)
+                       continue;
+               if (ent->id.coreid != dev->id.coreid)
+                       continue;
+
+               ent->devtypedata = data;
+       }
+}
+EXPORT_SYMBOL(ssb_set_devtypedata);
+
+static u32 clkfactor_f6_resolve(u32 v)
+{
+       /* map the magic values */
+       switch (v) {
+       case SSB_CHIPCO_CLK_F6_2:
+               return 2;
+       case SSB_CHIPCO_CLK_F6_3:
+               return 3;
+       case SSB_CHIPCO_CLK_F6_4:
+               return 4;
+       case SSB_CHIPCO_CLK_F6_5:
+               return 5;
+       case SSB_CHIPCO_CLK_F6_6:
+               return 6;
+       case SSB_CHIPCO_CLK_F6_7:
+               return 7;
+       }
+       return 0;
+}
+
+/* Calculate the speed the backplane would run at a given set of clockcontrol values */
+u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
+{
+       u32 n1, n2, clock, m1, m2, m3, mc;
+
+       n1 = (n & SSB_CHIPCO_CLK_N1);
+       n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
+
+       switch (plltype) {
+       case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
+               if (m & SSB_CHIPCO_CLK_T6_MMASK)
+                       return SSB_CHIPCO_CLK_T6_M0;
+               return SSB_CHIPCO_CLK_T6_M1;
+       case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
+       case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
+       case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
+       case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
+               n1 = clkfactor_f6_resolve(n1);
+               n2 += SSB_CHIPCO_CLK_F5_BIAS;
+               break;
+       case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
+               n1 += SSB_CHIPCO_CLK_T2_BIAS;
+               n2 += SSB_CHIPCO_CLK_T2_BIAS;
+               assert((n1 >= 2) && (n1 <= 7));
+               assert((n2 >= 5) && (n2 <= 23));
+               break;
+       case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
+               return 100000000;
+       default:
+               assert(0);
+       }
+
+       switch (plltype) {
+       case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
+       case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
+               clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
+               break;
+       default:
+               clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
+       }
+       if (!clock)
+               return 0;
+
+       m1 = (m & SSB_CHIPCO_CLK_M1);
+       m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
+       m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
+       mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
+
+       switch (plltype) {
+       case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
+       case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
+       case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
+       case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
+               m1 = clkfactor_f6_resolve(m1);
+               if ((plltype == SSB_PLLTYPE_1) ||
+                   (plltype == SSB_PLLTYPE_3))
+                       m2 += SSB_CHIPCO_CLK_F5_BIAS;
+               else
+                       m2 = clkfactor_f6_resolve(m2);
+               m3 = clkfactor_f6_resolve(m3);
+
+               switch (mc) {
+               case SSB_CHIPCO_CLK_MC_BYPASS:
+                       return clock;
+               case SSB_CHIPCO_CLK_MC_M1:
+                       return (clock / m1);
+               case SSB_CHIPCO_CLK_MC_M1M2:
+                       return (clock / (m1 * m2));
+               case SSB_CHIPCO_CLK_MC_M1M2M3:
+                       return (clock / (m1 * m2 * m3));
+               case SSB_CHIPCO_CLK_MC_M1M3:
+                       return (clock / (m1 * m3));
+               }
+               return 0;
+       case SSB_PLLTYPE_2:
+               m1 += SSB_CHIPCO_CLK_T2_BIAS;
+               m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
+               m3 += SSB_CHIPCO_CLK_T2_BIAS;
+               assert((m1 >= 2) && (m1 <= 7));
+               assert((m2 >= 3) && (m2 <= 10));
+               assert((m3 >= 2) && (m3 <= 7));
+
+               if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
+                       clock /= m1;
+               if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
+                       clock /= m2;
+               if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
+                       clock /= m3;
+               return clock;
+       default:
+               assert(0);
+       }
+       return 0;
+}
+
+/* Get the current speed the backplane is running at */
+u32 ssb_clockspeed(struct ssb_bus *bus)
+{
+       u32 rate;
+       u32 plltype;
+       u32 clkctl_n, clkctl_m;
+
+       //TODO if EXTIF: PLLTYPE == 1, read n from clockcontrol_n, m from clockcontrol_sb
+
+       if (bus->chipco.dev) {
+               ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
+                                           &clkctl_n, &clkctl_m);
+       } else
+               return 0;
+
+       if (bus->chip_id == 0x5365) {
+               rate = 100000000;
+       } else {
+               rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
+               if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
+                       rate /= 2;
+       }
+
+       return rate;
+}
+EXPORT_SYMBOL(ssb_clockspeed);
+
+static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
+{
+       /* The REJECT bit changed position in TMSLOW between
+        * Backplane revisions. */
+       switch (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV) {
+       case SSB_IDLOW_SSBREV_22:
+               return SSB_TMSLOW_REJECT_22;
+       case SSB_IDLOW_SSBREV_23:
+               return SSB_TMSLOW_REJECT_23;
+       default:
+               assert(0);
+       }
+       return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
+}
+
+int ssb_device_is_enabled(struct ssb_device *dev)
+{
+       u32 val;
+       u32 reject;
+
+       reject = ssb_tmslow_reject_bitmask(dev);
+       val = ssb_read32(dev, SSB_TMSLOW);
+       val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject;
+
+       return (val == SSB_TMSLOW_CLOCK);
+}
+EXPORT_SYMBOL(ssb_device_is_enabled);
+
+void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
+{
+       u32 val;
+
+       ssb_device_disable(dev, core_specific_flags);
+       ssb_write32(dev, SSB_TMSLOW,
+                   SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
+                   SSB_TMSLOW_FGC | core_specific_flags);
+       /* flush */
+       ssb_read32(dev, SSB_TMSLOW);
+       udelay(1);
+
+       /* Clear SERR if set. This is a hw bug workaround. */
+       if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
+               ssb_write32(dev, SSB_TMSHIGH, 0);
+
+       val = ssb_read32(dev, SSB_IMSTATE);
+       if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
+               val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
+               ssb_write32(dev, SSB_IMSTATE, val);
+       }
+
+       ssb_write32(dev, SSB_TMSLOW,
+                   SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
+                   core_specific_flags);
+       /* flush */
+       ssb_read32(dev, SSB_TMSLOW);
+       udelay(1);
+
+       ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
+                   core_specific_flags);
+       /* flush */
+       ssb_read32(dev, SSB_TMSLOW);
+       udelay(1);
+}
+EXPORT_SYMBOL(ssb_device_enable);
+
+static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
+                       int timeout, int set)
+{
+       int i;
+       u32 val;
+
+       for (i = 0; i < timeout; i++) {
+               val = ssb_read32(dev, reg);
+               if (set) {
+                       if (val & bitmask)
+                               return 0;
+               } else {
+                       if (!(val & bitmask))
+                               return 0;
+               }
+               udelay(10);
+       }
+       printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
+                           "register %04X to %s.\n",
+              bitmask, reg, (set ? "set" : "clear"));
+
+       return -ETIMEDOUT;
+}
+
+void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
+{
+       u32 reject;
+
+       if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
+               return;
+
+       reject = ssb_tmslow_reject_bitmask(dev);
+       ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
+       ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
+       ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
+       ssb_write32(dev, SSB_TMSLOW,
+                   SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
+                   reject | SSB_TMSLOW_RESET |
+                   core_specific_flags);
+       /* flush */
+       ssb_read32(dev, SSB_TMSLOW);
+       udelay(1);
+
+       ssb_write32(dev, SSB_TMSLOW,
+                   reject | SSB_TMSLOW_RESET |
+                   core_specific_flags);
+       /* flush */
+       ssb_read32(dev, SSB_TMSLOW);
+       udelay(1);
+}
+EXPORT_SYMBOL(ssb_device_disable);
+
+u32 ssb_dma_translation(struct ssb_device *dev)
+{
+       switch(dev->bus->bustype) {
+       case SSB_BUSTYPE_SSB:
+               return 0;
+       case SSB_BUSTYPE_PCI:
+       case SSB_BUSTYPE_PCMCIA:
+               return SSB_PCI_DMA;
+       }
+       return 0;
+}
+EXPORT_SYMBOL(ssb_dma_translation);
+
+int ssb_dma_set_mask(struct ssb_device *ssb_dev, u64 mask)
+{
+       struct device *dev = ssb_dev->dev;
+
+#ifdef CONFIG_SSB_PCIHOST
+       if (ssb_dev->bus->bustype == SSB_BUSTYPE_PCI &&
+           !dma_supported(dev, mask))
+               return -EIO;
+#endif
+       dev->coherent_dma_mask = mask;
+       dev->dma_mask = &dev->coherent_dma_mask;
+
+       return 0;
+}
+EXPORT_SYMBOL(ssb_dma_set_mask);
+
+int ssb_bus_may_powerdown(struct ssb_bus *bus)
+{
+       struct ssb_chipcommon *cc;
+       int err;
+
+       /* On buses where more than one core may be working
+        * at a time, we must not powerdown stuff if there are
+        * still cores that may want to run. */
+       if (bus->bustype == SSB_BUSTYPE_SSB)
+               return 0;
+
+       cc = &bus->chipco;
+       ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
+       err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
+       if (err)
+               goto error;
+
+       return 0;
+error:
+       ssb_printk(KERN_ERR PFX "Bus powerdown failed\n");
+       return err;
+}
+EXPORT_SYMBOL(ssb_bus_may_powerdown);
+
+int ssb_bus_powerup(struct ssb_bus *bus, int dynamic_pctl)
+{
+       struct ssb_chipcommon *cc;
+       int err;
+       enum ssb_clkmode mode;
+
+       err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
+       if (err)
+               goto error;
+       cc = &bus->chipco;
+       mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
+       ssb_chipco_set_clockmode(cc, mode);
+
+       return 0;
+error:
+       ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
+       return err;
+}
+EXPORT_SYMBOL(ssb_bus_powerup);
+
+u32 ssb_admatch_base(u32 adm)
+{
+       u32 base = 0;
+
+       switch (adm & SSB_ADM_TYPE) {
+       case SSB_ADM_TYPE0:
+               base = (adm & SSB_ADM_BASE0);
+               break;
+       case SSB_ADM_TYPE1:
+               assert(!(adm & SSB_ADM_NEG)); /* unsupported */
+               base = (adm & SSB_ADM_BASE1);
+               break;
+       case SSB_ADM_TYPE2:
+               assert(!(adm & SSB_ADM_NEG)); /* unsupported */
+               base = (adm & SSB_ADM_BASE2);
+               break;
+       default:
+               assert(0);
+       }
+
+       return base;
+}
+EXPORT_SYMBOL(ssb_admatch_base);
+
+u32 ssb_admatch_size(u32 adm)
+{
+       u32 size = 0;
+
+       switch (adm & SSB_ADM_TYPE) {
+       case SSB_ADM_TYPE0:
+               size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
+               break;
+       case SSB_ADM_TYPE1:
+               assert(!(adm & SSB_ADM_NEG)); /* unsupported */
+               size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
+               break;
+       case SSB_ADM_TYPE2:
+               assert(!(adm & SSB_ADM_NEG)); /* unsupported */
+               size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
+               break;
+       default:
+               assert(0);
+       }
+       size = (1 << (size + 1));
+
+       return size;
+}
+EXPORT_SYMBOL(ssb_admatch_size);
+
+static int __init ssb_modinit(void)
+{
+       int err;
+
+       ssb_bustype.name = "ssb";
+       err = bus_register(&ssb_bustype);
+       if (err)
+               return err;
+
+       /* Maybe we already registered some buses at early boot.
+        * Check for this and attach them
+        */
+       ssb_buses_lock();
+       err = ssb_attach_queued_buses();
+       ssb_buses_unlock();
+       if (err)
+               bus_unregister(&ssb_bustype);
+
+       return err;
+}
+subsys_initcall(ssb_modinit);
+
+static void __exit ssb_modexit(void)
+{
+       bus_unregister(&ssb_bustype);
+}
+module_exit(ssb_modexit)
index 811af78..fcd8e87 100644 (file)
@@ -121,7 +121,7 @@ int ssb_pci_xtal(struct ssb_bus *bus, u32 what, int turn_on)
                                err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
                                if (err)
                                        goto err_pci;
-                               msleep(2);
+                               msleep(5);
                        }
                }
 
@@ -240,6 +240,52 @@ static void sprom_do_read(struct ssb_bus *bus, u16 *sprom)
                sprom[i] = readw(bus->mmio + SSB_SPROM_BASE + (i * 2));
 }
 
+static int sprom_do_write(struct ssb_bus *bus, const u16 *sprom)
+{
+       struct pci_dev *pdev = bus->host_pci;
+       int i, err;
+       u32 spromctl;
+
+       ssb_printk(KERN_NOTICE PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
+       err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl);
+       if (err)
+               goto err_ctlreg;
+       spromctl |= SSB_SPROMCTL_WE;
+       err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl);
+       if (err)
+               goto err_ctlreg;
+       ssb_printk(KERN_NOTICE PFX "[ 0%%");
+       msleep(500);
+       for (i = 0; i < SSB_SPROMSIZE_WORDS; i++) {
+               if (i == SSB_SPROMSIZE_WORDS / 4)
+                       ssb_printk("25%%");
+               else if (i == SSB_SPROMSIZE_WORDS / 2)
+                       ssb_printk("50%%");
+               else if (i == (SSB_SPROMSIZE_WORDS / 4) * 3)
+                       ssb_printk("75%%");
+               else if (i % 2)
+                       ssb_printk(".");
+               writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2));
+               mmiowb();
+               msleep(20);
+       }
+       err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl);
+       if (err)
+               goto err_ctlreg;
+       spromctl &= ~SSB_SPROMCTL_WE;
+       err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl);
+       if (err)
+               goto err_ctlreg;
+       msleep(500);
+       ssb_printk("100%% ]\n");
+       ssb_printk(KERN_NOTICE PFX "SPROM written.\n");
+
+       return 0;
+err_ctlreg:
+       ssb_printk(KERN_ERR PFX "Could not access SPROM control register.\n");
+       return err;
+}
+
 static void sprom_extract_r1(struct ssb_sprom_r1 *out, const u16 *in)
 {
        int i;
@@ -472,9 +518,155 @@ const struct ssb_bus_ops ssb_pci_ops = {
        .write32        = ssb_pci_write32,
 };
 
+static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len)
+{
+       int i, pos = 0;
+
+       for (i = 0; i < SSB_SPROMSIZE_WORDS; i++) {
+               pos += snprintf(buf + pos, buf_len - pos - 1,
+                               "%04X", swab16(sprom[i]) & 0xFFFF);
+       }
+       pos += snprintf(buf + pos, buf_len - pos - 1, "\n");
+
+       return pos + 1;
+}
+
+static int hex2sprom(u16 *sprom, const char *dump, size_t len)
+{
+       char tmp[5] = { 0 };
+       int cnt = 0;
+       unsigned long parsed;
+
+       if (len < SSB_SPROMSIZE_BYTES * 2)
+               return -EINVAL;
+
+       while (cnt < SSB_SPROMSIZE_WORDS) {
+               memcpy(tmp, dump, 4);
+               dump += 4;
+               parsed = simple_strtoul(tmp, NULL, 16);
+               sprom[cnt++] = swab16((u16)parsed);
+       }
+
+       return 0;
+}
+
+static ssize_t ssb_pci_attr_sprom_show(struct device *pcidev,
+                                      struct device_attribute *attr,
+                                      char *buf)
+{
+       struct pci_dev *pdev = container_of(pcidev, struct pci_dev, dev);
+       struct ssb_bus *bus;
+       u16 *sprom;
+       int err = -ENODEV;
+       ssize_t count = 0;
+
+       bus = ssb_pci_dev_to_bus(pdev);
+       if (!bus)
+               goto out;
+       err = -ENOMEM;
+       sprom = kcalloc(SSB_SPROMSIZE_WORDS, sizeof(u16), GFP_KERNEL);
+       if (!sprom)
+               goto out;
+
+       err = -ERESTARTSYS;
+       if (mutex_lock_interruptible(&bus->pci_sprom_mutex))
+               goto out_kfree;
+       sprom_do_read(bus, sprom);
+       mutex_unlock(&bus->pci_sprom_mutex);
+
+       count = sprom2hex(sprom, buf, PAGE_SIZE);
+       err = 0;
+
+out_kfree:
+       kfree(sprom);
+out:
+       return err ? err : count;
+}
+
+static ssize_t ssb_pci_attr_sprom_store(struct device *pcidev,
+                                       struct device_attribute *attr,
+                                       const char *buf, size_t count)
+{
+       struct pci_dev *pdev = container_of(pcidev, struct pci_dev, dev);
+       struct ssb_bus *bus;
+       u16 *sprom;
+       int res = 0, err = -ENODEV;
+
+       bus = ssb_pci_dev_to_bus(pdev);
+       if (!bus)
+               goto out;
+       err = -ENOMEM;
+       sprom = kcalloc(SSB_SPROMSIZE_WORDS, sizeof(u16), GFP_KERNEL);
+       if (!sprom)
+               goto out;
+       err = hex2sprom(sprom, buf, count);
+       if (err) {
+               err = -EINVAL;
+               goto out_kfree;
+       }
+       err = sprom_check_crc(sprom);
+       if (err) {
+               err = -EINVAL;
+               goto out_kfree;
+       }
+
+       err = -ERESTARTSYS;
+       if (mutex_lock_interruptible(&bus->pci_sprom_mutex))
+               goto out_kfree;
+       err = ssb_devices_freeze(bus);
+       if (err) {
+               ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
+               goto out_unlock;
+       }
+       res = sprom_do_write(bus, sprom);
+       err = ssb_devices_thaw(bus);
+       if (err)
+               ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
+out_unlock:
+       mutex_unlock(&bus->pci_sprom_mutex);
+out_kfree:
+       kfree(sprom);
+out:
+       if (res)
+               return res;
+       return err ? err : count;
+}
+
+static DEVICE_ATTR(ssb_sprom, 0600,
+                  ssb_pci_attr_sprom_show,
+                  ssb_pci_attr_sprom_store);
+
+void ssb_pci_exit(struct ssb_bus *bus)
+{
+       struct pci_dev *pdev;
+
+       if (bus->bustype != SSB_BUSTYPE_PCI)
+               return;
+
+       pdev = bus->host_pci;
+       device_remove_file(&pdev->dev, &dev_attr_ssb_sprom);
+}
+
 int ssb_pci_init(struct ssb_bus *bus)
 {
+       struct pci_dev *pdev;
+       int err;
+
        if (bus->bustype != SSB_BUSTYPE_PCI)
                return 0;
-       return ssb_pci_sprom_get(bus);
+
+       pdev = bus->host_pci;
+       mutex_init(&bus->pci_sprom_mutex);
+       err = device_create_file(&pdev->dev, &dev_attr_ssb_sprom);
+       if (err)
+               goto out;
+       err = ssb_pci_sprom_get(bus);
+       if (err)
+               goto err_remove_sprom_file;
+
+out:
+       return err;
+err_remove_sprom_file:
+       device_remove_file(&pdev->dev, &dev_attr_ssb_sprom);
+       return err;
 }
diff --git a/target/linux/brcm47xx-2.6/files/drivers/ssb/pcihost_wrapper.c b/target/linux/brcm47xx-2.6/files/drivers/ssb/pcihost_wrapper.c
new file mode 100644 (file)
index 0000000..82a10ab
--- /dev/null
@@ -0,0 +1,104 @@
+/*
+ * Sonics Silicon Backplane
+ * PCI Hostdevice wrapper
+ *
+ * Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
+ * Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
+ * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
+ * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
+ * Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+#include <linux/pci.h>
+#include <linux/ssb/ssb.h>
+
+
+#ifdef CONFIG_PM
+static int ssb_pcihost_suspend(struct pci_dev *dev, pm_message_t state)
+{
+       pci_save_state(dev);
+       pci_disable_device(dev);
+       pci_set_power_state(dev, pci_choose_state(dev, state));
+
+       return 0;
+}
+
+static int ssb_pcihost_resume(struct pci_dev *dev)
+{
+       int err;
+
+       pci_set_power_state(dev, 0);
+       err = pci_enable_device(dev);
+       if (err)
+               return err;
+       pci_restore_state(dev);
+
+       return 0;
+}
+#else /* CONFIG_PM */
+# define ssb_pcihost_suspend   NULL
+# define ssb_pcihost_resume    NULL
+#endif /* CONFIG_PM */
+
+static int ssb_pcihost_probe(struct pci_dev *dev,
+                            const struct pci_device_id *id)
+{
+       struct ssb_bus *ssb;
+       int err = -ENOMEM;
+       const char *name;
+
+       ssb = kzalloc(sizeof(*ssb), GFP_KERNEL);
+       if (!ssb)
+               goto out;
+       err = pci_enable_device(dev);
+       if (err)
+               goto err_kfree_ssb;
+       name = dev->dev.bus_id;
+       if (dev->driver && dev->driver->name)
+               name = dev->driver->name;
+       err = pci_request_regions(dev, name);
+       if (err)
+               goto err_pci_disable;
+       pci_set_master(dev);
+
+       err = ssb_bus_pcibus_register(ssb, dev);
+       if (err)
+               goto err_pci_release_regions;
+
+       pci_set_drvdata(dev, ssb);
+
+out:
+       return err;
+
+err_pci_release_regions:
+       pci_release_regions(dev);
+err_pci_disable:
+       pci_disable_device(dev);
+err_kfree_ssb:
+       kfree(ssb);
+       return err;
+}
+
+static void ssb_pcihost_remove(struct pci_dev *dev)
+{
+       struct ssb_bus *ssb = pci_get_drvdata(dev);
+
+       ssb_bus_unregister(ssb);
+       pci_release_regions(dev);
+       pci_disable_device(dev);
+       kfree(ssb);
+       pci_set_drvdata(dev, NULL);
+}
+
+int ssb_pcihost_register(struct pci_driver *driver)
+{
+       driver->probe = ssb_pcihost_probe;
+       driver->remove = ssb_pcihost_remove;
+       driver->suspend = ssb_pcihost_suspend;
+       driver->resume = ssb_pcihost_resume;
+
+       return pci_register_driver(driver);
+}
+EXPORT_SYMBOL(ssb_pcihost_register);
index 9e4a121..feaf1e5 100644 (file)
 #include <linux/pci.h>
 #include <asm/io.h>
 
+#ifdef CONFIG_SSB_PCMCIAHOST
+# include <pcmcia/cs_types.h>
+# include <pcmcia/cs.h>
+# include <pcmcia/cistpl.h>
+# include <pcmcia/ds.h>
+#endif
+
 #include "ssb_private.h"
 
 
@@ -222,14 +229,32 @@ static void __iomem * ssb_ioremap(struct ssb_bus *bus,
        return mmio;
 }
 
+static int we_support_multiple_80211_cores(struct ssb_bus *bus)
+{
+       /* More than one 802.11 core is only supported by special chips.
+        * There are chips with two 802.11 cores, but with dangling
+        * pins on the second core. Be careful and reject them here.
+        */
+
+#ifdef CONFIG_SSB_PCIHOST
+       if (bus->bustype == SSB_BUSTYPE_PCI) {
+               if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
+                   bus->host_pci->device == 0x4324)
+                       return 1;
+       }
+#endif /* CONFIG_SSB_PCIHOST */
+       return 0;
+}
+
 int ssb_bus_scan(struct ssb_bus *bus,
                 unsigned long baseaddr)
 {
        int err = -ENOMEM;
        void __iomem *mmio;
        u32 idhi, cc, rev, tmp;
-       int i;
+       int dev_i, i;
        struct ssb_device *dev;
+       int nr_80211_cores = 0;
 
        mmio = ssb_ioremap(bus, baseaddr);
        if (!mmio)
@@ -293,11 +318,11 @@ int ssb_bus_scan(struct ssb_bus *bus,
        }
 
        /* Fetch basic information about each core/device */
-       for (i = 0; i < bus->nr_devices; i++) {
+       for (i = 0, dev_i = 0; i < bus->nr_devices; i++) {
                err = scan_switchcore(bus, i);
                if (err)
                        goto err_unmap;
-               dev = &(bus->devices[i]);
+               dev = &(bus->devices[dev_i]);
 
                idhi = scan_read32(bus, i, SSB_IDHIGH);
                dev->id.coreid = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT;
@@ -306,8 +331,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
                dev->id.vendor = (idhi & SSB_IDHIGH_VC) >> SSB_IDHIGH_VC_SHIFT;
                dev->core_index = i;
                dev->bus = bus;
-               if ((dev->bus->bustype == SSB_BUSTYPE_PCI) && (bus->host_pci))
-                       dev->irq = bus->host_pci->irq;
+               dev->ops = bus->ops;
 
                ssb_dprintk(KERN_INFO PFX
                            "Core %d found: %s "
@@ -315,13 +339,19 @@ int ssb_bus_scan(struct ssb_bus *bus,
                            i, ssb_core_name(dev->id.coreid),
                            dev->id.coreid, dev->id.revision, dev->id.vendor);
 
-               dev->dev.bus = &ssb_bustype;
-               snprintf(dev->dev.bus_id, sizeof(dev->dev.bus_id),
-                        "ssb%02x:%02x", bus->busnumber, i);
-
                switch (dev->id.coreid) {
+               case SSB_DEV_80211:
+                       nr_80211_cores++;
+                       if (nr_80211_cores > 1) {
+                               if (!we_support_multiple_80211_cores(bus)) {
+                                       ssb_dprintk(KERN_INFO PFX "Ignoring additional "
+                                                   "802.11 core\n");
+                                       continue;
+                               }
+                       }
+                       break;
                case SSB_DEV_EXTIF:
-#ifdef CONFIG_BCM947XX
+#ifdef CONFIG_SSB_DRIVER_EXTIF
                        if (bus->extif.dev) {
                                ssb_printk(KERN_WARNING PFX
                                           "WARNING: Multiple EXTIFs found\n");
@@ -340,14 +370,14 @@ int ssb_bus_scan(struct ssb_bus *bus,
                        break;
                case SSB_DEV_MIPS:
                case SSB_DEV_MIPS_3302:
-#ifdef CONFIG_BCM947XX
+#ifdef CONFIG_SSB_DRIVER_MIPS
                        if (bus->mipscore.dev) {
                                ssb_printk(KERN_WARNING PFX
                                           "WARNING: Multiple MIPS cores found\n");
                                break;
                        }
                        bus->mipscore.dev = dev;
-#endif /* CONFIG_BCM947XX */
+#endif /* CONFIG_SSB_DRIVER_MIPS */
                        break;
                case SSB_DEV_PCI:
                case SSB_DEV_PCIE:
@@ -363,7 +393,11 @@ int ssb_bus_scan(struct ssb_bus *bus,
                default:
                        break;
                }
+
+               dev_i++;
        }
+       bus->nr_devices = dev_i;
+
        err = 0;
 out:
        return err;
index 59645f5..ae1fc06 100644 (file)
@@ -53,6 +53,7 @@ extern int ssb_pci_xtal(struct ssb_bus *bus, u32 what,
                        int turn_on);
 extern int ssb_pci_sprom_get(struct ssb_bus *bus);
 extern void ssb_pci_get_boardtype(struct ssb_bus *bus);
+extern void ssb_pci_exit(struct ssb_bus *bus);
 extern int ssb_pci_init(struct ssb_bus *bus);
 extern const struct ssb_bus_ops ssb_pci_ops;
 
@@ -80,6 +81,9 @@ static inline int ssb_pci_sprom_get(struct ssb_bus *bus)
 static inline void ssb_pci_get_boardtype(struct ssb_bus *bus)
 {
 }
+static inline void ssb_pci_exit(struct ssb_bus *bus)
+{
+}
 static inline int ssb_pci_init(struct ssb_bus *bus)
 {
        return 0;
@@ -128,8 +132,12 @@ extern void ssb_iounmap(struct ssb_bus *ssb);
 
 
 /* core.c */
-extern struct bus_type ssb_bustype;
 extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m);
+#ifdef CONFIG_SSB_PCIHOST
+extern int ssb_devices_freeze(struct ssb_bus *bus);
+extern int ssb_devices_thaw(struct ssb_bus *bus);
+extern struct ssb_bus * ssb_pci_dev_to_bus(struct pci_dev *pdev);
+#endif /* CONFIG_SSB_PCIHOST */
 
 
 /* Ceiling division helper. Divides x by y. */
diff --git a/target/linux/brcm47xx-2.6/files/drivers/usb/host/ohci-ssb.c b/target/linux/brcm47xx-2.6/files/drivers/usb/host/ohci-ssb.c
new file mode 100644 (file)
index 0000000..2b3ef36
--- /dev/null
@@ -0,0 +1,254 @@
+/*
+ * Sonics Silicon Backplane
+ * Broadcom USB-core OHCI driver
+ *
+ * Copyright 2007 Michael Buesch <mb@bu3sch.de>
+ *
+ * Derived from the OHCI-PCI driver
+ * Copyright 1999 Roman Weissgaerber
+ * Copyright 2000-2002 David Brownell
+ * Copyright 1999 Linus Torvalds
+ * Copyright 1999 Gregory P. Smith
+ *
+ * Derived from the USBcore related parts of Broadcom-SB
+ * Copyright 2005 Broadcom Corporation
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+#include <linux/ssb/ssb.h>
+
+
+#define SSB_OHCI_TMSLOW_HOSTMODE       (1 << 29)
+
+struct ssb_ohci_device {
+       struct ohci_hcd ohci; /* _must_ be at the beginning. */
+
+       u32 enable_flags;
+};
+
+
+static inline
+struct ssb_ohci_device * hcd_to_ssb_ohci(struct usb_hcd *hcd)
+{
+       return (struct ssb_ohci_device *)(hcd->hcd_priv);
+}
+
+
+static const struct ssb_device_id ssb_ohci_table[] = {
+       SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOSTDEV, SSB_ANY_REV),
+       SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_USB11_HOST, SSB_ANY_REV),
+       SSB_DEVTABLE_END
+};
+MODULE_DEVICE_TABLE(ssb, ssb_ohci_table);
+
+
+static int ssb_ohci_reset(struct usb_hcd *hcd)
+{
+       struct ssb_ohci_device *ohcidev = hcd_to_ssb_ohci(hcd);
+       struct ohci_hcd *ohci = &ohcidev->ohci;
+       int err;
+
+       ohci_hcd_init(ohci);
+       err = ohci_init(ohci);
+
+       return err;
+}
+
+static int ssb_ohci_start(struct usb_hcd *hcd)
+{
+       struct ssb_ohci_device *ohcidev = hcd_to_ssb_ohci(hcd);
+       struct ohci_hcd *ohci = &ohcidev->ohci;
+       int err;
+
+       err = ohci_run(ohci);
+       if (err < 0) {
+               ohci_err(ohci, "can't start\n");
+               ohci_stop(hcd);
+       }
+
+       return err;
+}
+
+#ifdef CONFIG_PM
+static int ssb_ohci_hcd_suspend(struct usb_hcd *hcd, pm_message_t message)
+{
+       struct ssb_ohci_device *ohcidev = hcd_to_ssb_ohci(hcd);
+       struct ohci_hcd *ohci = &ohcidev->ohci;
+       unsigned long flags;
+
+       spin_lock_irqsave(&ohci->lock, flags);
+
+       ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
+       ohci_readl(ohci, &ohci->regs->intrdisable); /* commit write */
+
+       /* make sure snapshot being resumed re-enumerates everything */
+       if (message.event == PM_EVENT_PRETHAW)
+               ohci_usb_reset(ohci);
+
+       clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+
+       spin_unlock_irqrestore(&ohci->lock, flags);
+
+       return 0;
+}
+
+static int ssb_ohci_hcd_resume(struct usb_hcd *hcd)
+{
+       set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+       usb_hcd_resume_root_hub(hcd);
+       return 0;
+}
+#endif /* CONFIG_PM */
+
+static const struct hc_driver ssb_ohci_hc_driver = {
+       .description            = "ssb-usb-ohci",
+       .product_desc           = "SSB OHCI Controller",
+       .hcd_priv_size          = sizeof(struct ssb_ohci_device),
+
+       .irq                    = ohci_irq,
+       .flags                  = HCD_MEMORY | HCD_USB11,
+
+       .reset                  = ssb_ohci_reset,
+       .start                  = ssb_ohci_start,
+       .stop                   = ohci_stop,
+       .shutdown               = ohci_shutdown,
+
+#ifdef CONFIG_PM
+       .suspend                = ssb_ohci_hcd_suspend,
+       .resume                 = ssb_ohci_hcd_resume,
+#endif
+
+       .urb_enqueue            = ohci_urb_enqueue,
+       .urb_dequeue            = ohci_urb_dequeue,
+       .endpoint_disable       = ohci_endpoint_disable,
+
+       .get_frame_number       = ohci_get_frame,
+
+       .hub_status_data        = ohci_hub_status_data,
+       .hub_control            = ohci_hub_control,
+       .hub_irq_enable         = ohci_rhsc_enable,
+
+#ifdef CONFIG_PM
+       .bus_suspend            = ohci_bus_suspend,
+       .bus_resume             = ohci_bus_resume,
+#endif
+
+       .start_port_reset       = ohci_start_port_reset,
+};
+
+
+static void ssb_ohci_detach(struct ssb_device *dev)
+{
+       struct usb_hcd *hcd = ssb_get_drvdata(dev);
+
+       usb_remove_hcd(hcd);
+       iounmap(hcd->regs);
+       usb_put_hcd(hcd);
+       ssb_device_disable(dev, 0);
+}
+
+static int ssb_ohci_attach(struct ssb_device *dev)
+{
+       struct ssb_ohci_device *ohcidev;
+       struct usb_hcd *hcd;
+       int err = -ENOMEM;
+       u32 tmp, flags = 0;
+
+       if (dev->id.coreid == SSB_DEV_USB11_HOSTDEV)
+               flags |= SSB_OHCI_TMSLOW_HOSTMODE;
+
+       ssb_device_enable(dev, flags);
+
+       hcd = usb_create_hcd(&ssb_ohci_hc_driver, dev->dev,
+                            dev->dev->bus_id);
+       if (!hcd)
+               goto err_dev_disable;
+       ohcidev = hcd_to_ssb_ohci(hcd);
+       ohcidev->enable_flags = flags;
+
+       tmp = ssb_read32(dev, SSB_ADMATCH0);
+       hcd->rsrc_start = ssb_admatch_base(tmp);
+       hcd->rsrc_len = ssb_admatch_size(tmp);
+       hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len);
+       if (!hcd->regs)
+               goto err_put_hcd;
+       err = usb_add_hcd(hcd, dev->irq, IRQF_SHARED);
+       if (err)
+               goto err_iounmap;
+
+       ssb_set_drvdata(dev, hcd);
+
+       return err;
+
+err_iounmap:
+       iounmap(hcd->regs);
+err_put_hcd:
+       usb_put_hcd(hcd);
+err_dev_disable:
+       ssb_device_disable(dev, flags);
+       return err;
+}
+
+static int ssb_ohci_probe(struct ssb_device *dev,
+                         const struct ssb_device_id *id)
+{
+       int err;
+       u16 chipid_top;
+
+       chipid_top = (dev->bus->chip_id & 0xFF00);
+       if (chipid_top != 0x4700 &&
+           chipid_top != 0x5300) {
+               /* USBcores are only connected on embedded devices. */
+               return -ENODEV;
+       }
+       /* TODO: Probably need more checks here whether the core is connected. */
+
+       if (usb_disabled())
+               return -ENODEV;
+
+       /* We currently always attach SSB_DEV_USB11_HOSTDEV
+        * as HOST OHCI. If we want to attach it as Client device,
+        * we must branch here and call into the (yet to
+        * be written) Client mode driver. Same for remove(). */
+
+       err = ssb_ohci_attach(dev);
+
+       return err;
+}
+
+static void ssb_ohci_remove(struct ssb_device *dev)
+{
+       ssb_ohci_detach(dev);
+}
+
+#ifdef CONFIG_PM
+static int ssb_ohci_suspend(struct ssb_device *dev, pm_message_t state)
+{
+       ssb_device_disable(dev, 0);
+
+       return 0;
+}
+
+static int ssb_ohci_resume(struct ssb_device *dev)
+{
+       struct usb_hcd *hcd = ssb_get_drvdata(dev);
+       struct ssb_ohci_device *ohcidev = hcd_to_ssb_ohci(hcd);
+
+       ssb_device_enable(dev, ohcidev->enable_flags);
+
+       return 0;
+}
+#else /* CONFIG_PM */
+# define ssb_ohci_suspend      NULL
+# define ssb_ohci_resume       NULL
+#endif /* CONFIG_PM */
+
+static struct ssb_driver ssb_ohci_driver = {
+       .name           = KBUILD_MODNAME,
+       .id_table       = ssb_ohci_table,
+       .probe          = ssb_ohci_probe,
+       .remove         = ssb_ohci_remove,
+       .suspend        = ssb_ohci_suspend,
+       .resume         = ssb_ohci_resume,
+};
index 7fdeae7..1ed3cbc 100644 (file)
@@ -6,6 +6,9 @@
 #include <linux/list.h>
 #include <linux/types.h>
 #include <linux/spinlock.h>
+#ifdef CONFIG_SSB_PCIHOST
+# include <linux/pci.h>
+#endif
 
 #include <linux/ssb/ssb_regs.h>
 
@@ -98,6 +101,17 @@ struct ssb_sprom {
 };
 
 
+struct ssb_device;
+/* Lowlevel read/write operations on the device MMIO.
+ * Internal, don't use that outside of ssb. */
+struct ssb_bus_ops {
+       u16 (*read16)(struct ssb_device *dev, u16 offset);
+       u32 (*read32)(struct ssb_device *dev, u16 offset);
+       void (*write16)(struct ssb_device *dev, u16 offset, u16 value);
+       void (*write32)(struct ssb_device *dev, u16 offset, u32 value);
+};
+
+
 /* Core-ID values. */
 #define SSB_DEV_CHIPCOMMON     0x800
 #define SSB_DEV_ILINE20                0x801
@@ -149,18 +163,37 @@ struct ssb_device_id {
 #define SSB_ANY_ID             0xFFFF
 #define SSB_ANY_REV            0xFF
 
+/* Some kernel subsystems poke with dev->drvdata, so we must use the
+ * following ugly workaround to get from struct device to struct ssb_device */
+struct __ssb_dev_wrapper {
+       struct device dev;
+       struct ssb_device *sdev;
+};
 
 struct ssb_device {
-       struct device dev;
+       /* Having a copy of the ops pointer in each dev struct
+        * is an optimization. */
+       const struct ssb_bus_ops *ops;
+
+       struct device *dev;
        struct ssb_bus *bus;
        struct ssb_device_id id;
 
        u8 core_index;
        unsigned int irq;
+
+       /* Internal-only stuff follows. */
        void *drvdata;          /* Per-device data */
        void *devtypedata;      /* Per-devicetype (eg 802.11) data */
 };
-#define dev_to_ssb_dev(_dev) container_of(_dev, struct ssb_device, dev)
+
+/* Go from struct device to struct ssb_device. */
+static inline
+struct ssb_device * dev_to_ssb_dev(struct device *dev)
+{
+       struct __ssb_dev_wrapper *wrap = container_of(dev, struct __ssb_dev_wrapper, dev);
+       return wrap->sdev;
+}
 
 /* Device specific user data */
 static inline
@@ -182,13 +215,6 @@ void * ssb_get_devtypedata(struct ssb_device *dev)
        return dev->devtypedata;
 }
 
-struct ssb_bus_ops {
-       u16 (*read16)(struct ssb_device *dev, u16 offset);
-       u32 (*read32)(struct ssb_device *dev, u16 offset);
-       void (*write16)(struct ssb_device *dev, u16 offset, u16 value);
-       void (*write32)(struct ssb_device *dev, u16 offset, u32 value);
-};
-
 
 struct ssb_driver {
        const char *name;
@@ -218,7 +244,6 @@ enum ssb_bustype {
        SSB_BUSTYPE_SSB,        /* This SSB bus is the system bus */
        SSB_BUSTYPE_PCI,        /* SSB is connected to PCI bus */
        SSB_BUSTYPE_PCMCIA,     /* SSB is connected to PCMCIA bus */
-       //TODO SSB_BUSTYPE_JTAG,
 };
 
 /* board_vendor */
@@ -238,12 +263,6 @@ enum ssb_bustype {
 #define SSB_CHIPPACK_BCM4712M  2       /* Medium 225pin 4712 */
 #define SSB_CHIPPACK_BCM4712L  0       /* Large 340pin 4712 */
 
-static inline u16 ssb_read16(struct ssb_device *dev, u16 offset);
-static inline u32 ssb_read32(struct ssb_device *dev, u16 offset);
-static inline void ssb_write16(struct ssb_device *dev, u16 offset, u16 value);
-static inline void ssb_write32(struct ssb_device *dev, u16 offset, u32 value);
-static inline u32 ssb_write32_masked(struct ssb_device *dev, u16 offset, u32 mask, u32 value);
-
 #include <linux/ssb/ssb_driver_chipcommon.h>
 #include <linux/ssb/ssb_driver_mips.h>
 #include <linux/ssb/ssb_driver_extif.h>
@@ -269,6 +288,10 @@ struct ssb_bus {
        /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
        struct pcmcia_device *host_pcmcia;
 
+#ifdef CONFIG_SSB_PCIHOST
+       struct mutex pci_sprom_mutex;
+#endif
+
        /* ID information about the PCB. */
        u16 board_vendor;
        u16 board_type;
@@ -328,32 +351,22 @@ void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags);
 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags);
 
 
+/* Device MMIO register read/write functions. */
 static inline u16 ssb_read16(struct ssb_device *dev, u16 offset)
 {
-       return dev->bus->ops->read16(dev, offset);
+       return dev->ops->read16(dev, offset);
 }
 static inline u32 ssb_read32(struct ssb_device *dev, u16 offset)
 {
-       return dev->bus->ops->read32(dev, offset);
+       return dev->ops->read32(dev, offset);
 }
 static inline void ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
 {
-       dev->bus->ops->write16(dev, offset, value);
+       dev->ops->write16(dev, offset, value);
 }
 static inline void ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
 {
-       dev->bus->ops->write32(dev, offset, value);
-}
-
-static inline u32 ssb_write32_masked(struct ssb_device *dev,
-                                 u16 offset,
-                                 u32 mask,
-                                 u32 value)
-{
-       value &= mask;
-       value |= ssb_read32(dev, offset) & ~mask;
-       ssb_write32(dev, offset, value);
-       return value;
+       dev->ops->write32(dev, offset, value);
 }
 
 
@@ -366,6 +379,21 @@ extern u32 ssb_dma_translation(struct ssb_device *dev);
 extern int ssb_dma_set_mask(struct ssb_device *ssb_dev, u64 mask);
 
 
+#ifdef CONFIG_SSB_PCIHOST
+/* PCI-host wrapper driver */
+extern int ssb_pcihost_register(struct pci_driver *driver);
+static inline void ssb_pcihost_unregister(struct pci_driver *driver)
+{
+       pci_unregister_driver(driver);
+}
+#endif /* CONFIG_SSB_PCIHOST */
+
+
+/* Bus-Power handling functions. */
+extern int ssb_bus_may_powerdown(struct ssb_bus *bus);
+extern int ssb_bus_powerup(struct ssb_bus *bus, int dynamic_pctl);
+
+
 /* Various helper functions */
 extern u32 ssb_admatch_base(u32 adm);
 extern u32 ssb_admatch_size(u32 adm);
index e0c0e61..8856590 100644 (file)
 #define SSB_CHIPCO_GPIOOUT             0x0064
 #define SSB_CHIPCO_GPIOOUTEN           0x0068
 #define SSB_CHIPCO_GPIOCTL             0x006C
-#define SSB_CHIPCO_GPIOINTPOL          0x0070
-#define SSB_CHIPCO_GPIOINTMASK         0x0074
+#define SSB_CHIPCO_GPIOPOL             0x0070
+#define SSB_CHIPCO_GPIOIRQ             0x0074
 #define SSB_CHIPCO_WATCHDOG            0x0080
 #define SSB_CHIPCO_GPIOTIMER           0x0088          /* LED powersave (corerev >= 16) */
 #define  SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT     16
@@ -364,8 +364,6 @@ extern void ssb_chipcommon_init(struct ssb_chipcommon *cc);
 extern void ssb_chipco_suspend(struct ssb_chipcommon *cc, pm_message_t state);
 extern void ssb_chipco_resume(struct ssb_chipcommon *cc);
 
-extern void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc, u32 chip_id,
-       u32 *rate, u32 *plltype, u32 *n, u32 *m);
 extern void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
                                        u32 *plltype, u32 *n, u32 *m);
 extern void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
@@ -380,47 +378,6 @@ enum ssb_clkmode {
 extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
                                     enum ssb_clkmode mode);
 
-
-/* GPIO functions */
-static inline u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc,
-                                    u32 mask)
-{
-       return ssb_read32(cc->dev, SSB_CHIPCO_GPIOIN) & mask;
-}
-
-static inline u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc,
-                                    u32 mask, u32 value)
-{
-       return ssb_write32_masked(cc->dev, SSB_CHIPCO_GPIOOUT, mask, value);
-}
-
-static inline u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc,
-                                    u32 mask, u32 value)
-{
-       return ssb_write32_masked(cc->dev, SSB_CHIPCO_GPIOOUTEN, mask, value);
-}
-
-static inline u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc,
-                                    u32 mask, u32 value)
-{
-       return ssb_write32_masked(cc->dev, SSB_CHIPCO_GPIOCTL, mask, value);
-}
-
-static inline u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc,
-                                    u32 mask, u32 value)
-{
-       return ssb_write32_masked(cc->dev, SSB_CHIPCO_GPIOINTMASK, mask, value);
-}
-
-static inline u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc,
-                                    u32 mask, u32 value)
-{
-       return ssb_write32_masked(cc->dev, SSB_CHIPCO_GPIOINTPOL, mask, value);
-}
-/* TODO: GPIO reservation */
-
-extern int ssb_chipco_watchdog(struct ssb_chipcommon *cc, uint ticks);
-
 #ifdef CONFIG_SSB_SERIAL
 extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
                                  struct ssb_serial_port *ports);
index 63add56..278a637 100644 (file)
@@ -159,37 +159,5 @@ struct ssb_extif {
 #define SSB_EXTIF_WATCHDOG_CLK         48000000        /* Hz */
 
 
-/* GPIO functions */
-static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif,
-                                    u32 mask)
-{
-       return ssb_read32(extif->dev, SSB_EXTIF_GPIO_IN) & mask;
-}
-
-static inline u32 ssb_extif_gpio_out(struct ssb_extif *extif,
-                                    u32 mask, u32 value)
-{
-       return ssb_write32_masked(extif->dev, SSB_EXTIF_GPIO_OUT(0), mask, value);
-}
-
-static inline u32 ssb_extif_gpio_outen(struct ssb_extif *extif,
-                                    u32 mask, u32 value)
-{
-       return ssb_write32_masked(extif->dev, SSB_EXTIF_GPIO_OUTEN(0), mask, value);
-}
-
-static inline u32 ssb_extif_gpio_polarity(struct ssb_extif *extif,
-                                    u32 mask, u32 value)
-{
-       return ssb_write32_masked(extif->dev, SSB_EXTIF_GPIO_INTPOL, mask, value);
-}
-
-static inline u32 ssb_extif_gpio_intmask(struct ssb_extif *extif,
-                                    u32 mask, u32 value)
-{
-       return ssb_write32_masked(extif->dev, SSB_EXTIF_GPIO_INTMASK, mask, value);
-}
-
-
 #endif /* __KERNEL__ */
 #endif /* LINUX_SSB_EXTIFCORE_H_ */
index 61c7665..91f2373 100644 (file)
@@ -3,7 +3,7 @@
 
 #ifdef __KERNEL__
 
-#ifdef CONFIG_BCM947XX
+#ifdef CONFIG_SSB_DRIVER_MIPS
 
 struct ssb_device;
 
@@ -22,17 +22,16 @@ struct ssb_mipscore {
        int nr_serial_ports;
        struct ssb_serial_port serial_ports[4];
 
-       int flash_buswidth;
        u32 flash_window;
        u32 flash_window_size;
 };
 
 extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
-extern u32 ssb_cpu_clock(struct ssb_mipscore *mcore);
+
 extern unsigned int ssb_mips_irq(struct ssb_device *dev);
 
 
-#else /* CONFIG_BCM947XX */
+#else /* CONFIG_SSB_DRIVER_MIPS */
 
 struct ssb_mipscore {
 };
@@ -42,7 +41,7 @@ void ssb_mipscore_init(struct ssb_mipscore *mcore)
 {
 }
 
-#endif /* CONFIG_BCM947XX */
+#endif /* CONFIG_SSB_DRIVER_MIPS */
 
 #endif /* __KERNEL__ */
 #endif /* LINUX_SSB_MIPSCORE_H_ */
index 6bb4046..e1c7ff7 100644 (file)
@@ -96,7 +96,8 @@
 #define  SSB_INTVEC_ENET1      0x00000040 /* Enable interrupts for enet 1 */
 #define SSB_TMSLOW             0x0F98     /* SB Target State Low */
 #define  SSB_TMSLOW_RESET      0x00000001 /* Reset */
-#define  SSB_TMSLOW_REJECT     0x00000002 /* Reject */
+#define  SSB_TMSLOW_REJECT_22  0x00000002 /* Reject (Backplane rev 2.2) */
+#define  SSB_TMSLOW_REJECT_23  0x00000004 /* Reject (Backplane rev 2.3) */
 #define  SSB_TMSLOW_CLOCK      0x00010000 /* Clock Enable */
 #define  SSB_TMSLOW_FGC                0x00020000 /* Force Gated Clocks On */
 #define  SSB_TMSLOW_PE         0x40000000 /* Power Management Enable */
diff --git a/target/linux/brcm47xx-2.6/patches/200-b44_ssb_fixup.patch b/target/linux/brcm47xx-2.6/patches/200-b44_ssb_fixup.patch
new file mode 100644 (file)
index 0000000..816d7e1
--- /dev/null
@@ -0,0 +1,256 @@
+Index: linux-2.6.22-rc4/drivers/net/b44.c
+===================================================================
+--- linux-2.6.22-rc4.orig/drivers/net/b44.c    2007-06-10 21:33:15.000000000 +0100
++++ linux-2.6.22-rc4/drivers/net/b44.c 2007-06-10 21:33:23.000000000 +0100
+@@ -128,7 +128,7 @@
+                                              unsigned long offset,
+                                              enum dma_data_direction dir)
+ {
+-      dma_sync_single_range_for_device(&sdev->dev, dma_base,
++      dma_sync_single_range_for_device(sdev->dev, dma_base,
+                                       offset & dma_desc_align_mask,
+                                       dma_desc_sync_size, dir);
+ }
+@@ -138,7 +138,7 @@
+                                           unsigned long offset,
+                                           enum dma_data_direction dir)
+ {
+-      dma_sync_single_range_for_cpu(&sdev->dev, dma_base,
++      dma_sync_single_range_for_cpu(sdev->dev, dma_base,
+                                    offset & dma_desc_align_mask,
+                                    dma_desc_sync_size, dir);
+ }
+@@ -563,7 +563,7 @@
+               BUG_ON(skb == NULL);
+-              dma_unmap_single(&bp->sdev->dev,
++              dma_unmap_single(bp->sdev->dev,
+                                pci_unmap_addr(rp, mapping),
+                                skb->len,
+                                DMA_TO_DEVICE);
+@@ -603,7 +603,7 @@
+       if (skb == NULL)
+               return -ENOMEM;
+       
+-      mapping = dma_map_single(&bp->sdev->dev, skb->data,
++      mapping = dma_map_single(bp->sdev->dev, skb->data,
+                                RX_PKT_BUF_SZ,
+                                DMA_FROM_DEVICE);
+@@ -613,18 +613,18 @@
+               mapping + RX_PKT_BUF_SZ > DMA_30BIT_MASK) {
+               /* Sigh... */
+               if (!dma_mapping_error(mapping))
+-                      dma_unmap_single(&bp->sdev->dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
++                      dma_unmap_single(bp->sdev->dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
+               dev_kfree_skb_any(skb);
+               skb = __dev_alloc_skb(RX_PKT_BUF_SZ,GFP_DMA);
+               if (skb == NULL)
+                       return -ENOMEM;
+-              mapping = dma_map_single(&bp->sdev->dev, skb->data,
++              mapping = dma_map_single(bp->sdev->dev, skb->data,
+                                        RX_PKT_BUF_SZ,
+                                        DMA_FROM_DEVICE);
+               if (dma_mapping_error(mapping) ||
+                       mapping + RX_PKT_BUF_SZ > DMA_30BIT_MASK) {
+                       if (!dma_mapping_error(mapping))
+-                              dma_unmap_single(&bp->sdev->dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
++                              dma_unmap_single(bp->sdev->dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
+                       dev_kfree_skb_any(skb);
+                       return -ENOMEM;
+               }
+@@ -702,7 +702,7 @@
+                                           dest_idx * sizeof(dest_desc),
+                                           DMA_BIDIRECTIONAL);
+-      dma_sync_single_for_device(&bp->sdev->dev, le32_to_cpu(src_desc->addr),
++      dma_sync_single_for_device(bp->sdev->dev, le32_to_cpu(src_desc->addr),
+                                      RX_PKT_BUF_SZ,
+                                      DMA_FROM_DEVICE);
+ }
+@@ -724,7 +724,7 @@
+               struct rx_header *rh;
+               u16 len;
+-              dma_sync_single_for_cpu(&bp->sdev->dev, map,
++              dma_sync_single_for_cpu(bp->sdev->dev, map,
+                                           RX_PKT_BUF_SZ,
+                                           DMA_FROM_DEVICE);
+               rh = (struct rx_header *) skb->data;
+@@ -758,7 +758,7 @@
+                       skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
+                       if (skb_size < 0)
+                               goto drop_it;
+-                      dma_unmap_single(&bp->sdev->dev, map,
++                      dma_unmap_single(bp->sdev->dev, map,
+                                        skb_size, DMA_FROM_DEVICE);
+                       /* Leave out rx_header */
+               skb_put(skb, len+bp->rx_offset);
+@@ -931,22 +931,22 @@
+               goto err_out;
+       }
+-      mapping = dma_map_single(&bp->sdev->dev, skb->data, len, DMA_TO_DEVICE);
++      mapping = dma_map_single(bp->sdev->dev, skb->data, len, DMA_TO_DEVICE);
+       if (dma_mapping_error(mapping) || mapping + len > DMA_30BIT_MASK) {
+               /* Chip can't handle DMA to/from >1GB, use bounce buffer */
+               if (!dma_mapping_error(mapping))
+-                      dma_unmap_single(&bp->sdev->dev, mapping, len, DMA_TO_DEVICE);
++                      dma_unmap_single(bp->sdev->dev, mapping, len, DMA_TO_DEVICE);
+               bounce_skb = __dev_alloc_skb(TX_PKT_BUF_SZ,
+                                            GFP_ATOMIC|GFP_DMA);
+               if (!bounce_skb)
+                       goto err_out;
+-              mapping = dma_map_single(&bp->sdev->dev, bounce_skb->data,
++              mapping = dma_map_single(bp->sdev->dev, bounce_skb->data,
+                                        len, DMA_TO_DEVICE);
+               if (dma_mapping_error(mapping) || mapping + len > DMA_30BIT_MASK) {
+                       if (!dma_mapping_error(mapping))
+-                              dma_unmap_single(&bp->sdev->dev, mapping,
++                              dma_unmap_single(bp->sdev->dev, mapping,
+                                        len, DMA_TO_DEVICE);
+                       dev_kfree_skb_any(bounce_skb);
+                       goto err_out;
+@@ -1046,7 +1046,7 @@
+               if (rp->skb == NULL)
+                       continue;
+-              dma_unmap_single(&bp->sdev->dev,
++              dma_unmap_single(bp->sdev->dev,
+                                pci_unmap_addr(rp, mapping),
+                                RX_PKT_BUF_SZ,
+                                DMA_FROM_DEVICE);
+@@ -1060,7 +1060,7 @@
+               if (rp->skb == NULL)
+                       continue;
+-              dma_unmap_single(&bp->sdev->dev,
++              dma_unmap_single(bp->sdev->dev,
+                                pci_unmap_addr(rp, mapping),
+                                rp->skb->len,
+                                DMA_TO_DEVICE);
+@@ -1085,12 +1085,12 @@
+       memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
+       if (bp->flags & B44_FLAG_RX_RING_HACK)
+-              dma_sync_single_for_device(&bp->sdev->dev, bp->rx_ring_dma,
++              dma_sync_single_for_device(bp->sdev->dev, bp->rx_ring_dma,
+                                         DMA_TABLE_BYTES,
+                                         DMA_BIDIRECTIONAL);
+       if (bp->flags & B44_FLAG_TX_RING_HACK)
+-              dma_sync_single_for_device(&bp->sdev->dev, bp->tx_ring_dma,
++              dma_sync_single_for_device(bp->sdev->dev, bp->tx_ring_dma,
+                                         DMA_TABLE_BYTES,
+                                         DMA_TO_DEVICE);
+@@ -1112,24 +1112,24 @@
+       bp->tx_buffers = NULL;
+       if (bp->rx_ring) {
+               if (bp->flags & B44_FLAG_RX_RING_HACK) {
+-                      dma_unmap_single(&bp->sdev->dev, bp->rx_ring_dma,
++                      dma_unmap_single(bp->sdev->dev, bp->rx_ring_dma,
+                                       DMA_TABLE_BYTES,
+                                       DMA_BIDIRECTIONAL);
+                       kfree(bp->rx_ring);
+               } else
+-                      dma_free_coherent(&bp->sdev->dev, DMA_TABLE_BYTES,
++                      dma_free_coherent(bp->sdev->dev, DMA_TABLE_BYTES,
+                                           bp->rx_ring, bp->rx_ring_dma);
+               bp->rx_ring = NULL;
+               bp->flags &= ~B44_FLAG_RX_RING_HACK;
+       }
+       if (bp->tx_ring) {
+               if (bp->flags & B44_FLAG_TX_RING_HACK) {
+-                      dma_unmap_single(&bp->sdev->dev, bp->tx_ring_dma,
++                      dma_unmap_single(bp->sdev->dev, bp->tx_ring_dma,
+                                       DMA_TABLE_BYTES,
+                                       DMA_TO_DEVICE);
+                       kfree(bp->tx_ring);
+               } else
+-                      dma_free_coherent(&bp->sdev->dev, DMA_TABLE_BYTES,
++                      dma_free_coherent(bp->sdev->dev, DMA_TABLE_BYTES,
+                                           bp->tx_ring, bp->tx_ring_dma);
+               bp->tx_ring = NULL;
+               bp->flags &= ~B44_FLAG_TX_RING_HACK;
+@@ -1155,7 +1155,7 @@
+               goto out_err;
+       size = DMA_TABLE_BYTES;
+-      bp->rx_ring = dma_alloc_coherent(&bp->sdev->dev, size, &bp->rx_ring_dma, GFP_ATOMIC);
++      bp->rx_ring = dma_alloc_coherent(bp->sdev->dev, size, &bp->rx_ring_dma, GFP_ATOMIC);
+       if (!bp->rx_ring) {
+               /* Allocation may have failed due to pci_alloc_consistent
+                  insisting on use of GFP_DMA, which is more restrictive
+@@ -1167,7 +1167,7 @@
+               if (!rx_ring)
+                       goto out_err;
+-              rx_ring_dma = dma_map_single(&bp->sdev->dev, rx_ring,
++              rx_ring_dma = dma_map_single(bp->sdev->dev, rx_ring,
+                                           DMA_TABLE_BYTES,
+                                           DMA_BIDIRECTIONAL);
+@@ -1182,7 +1182,7 @@
+               bp->flags |= B44_FLAG_RX_RING_HACK;
+       }
+-      bp->tx_ring = dma_alloc_coherent(&bp->sdev->dev, size, &bp->tx_ring_dma, GFP_ATOMIC);
++      bp->tx_ring = dma_alloc_coherent(bp->sdev->dev, size, &bp->tx_ring_dma, GFP_ATOMIC);
+       if (!bp->tx_ring) {
+               /* Allocation may have failed due to dma_alloc_coherent
+                  insisting on use of GFP_DMA, which is more restrictive
+@@ -1194,7 +1194,7 @@
+               if (!tx_ring)
+                       goto out_err;
+-              tx_ring_dma = dma_map_single(&bp->sdev->dev, tx_ring,
++              tx_ring_dma = dma_map_single(bp->sdev->dev, tx_ring,
+                                           DMA_TABLE_BYTES,
+                                           DMA_TO_DEVICE);
+@@ -2314,13 +2314,13 @@
+       dev = alloc_etherdev(sizeof(*bp));
+       if (!dev) {
+-              dev_err(&sdev->dev, "Etherdev alloc failed, aborting.\n");
++              dev_err(sdev->dev, "Etherdev alloc failed, aborting.\n");
+               err = -ENOMEM;
+               goto out;
+       }
+       SET_MODULE_OWNER(dev);
+-      SET_NETDEV_DEV(dev,&sdev->dev);
++      SET_NETDEV_DEV(dev,sdev->dev);
+       /* No interesting netdevice features in this card... */
+       dev->features |= 0;
+@@ -2358,7 +2358,7 @@
+       err = b44_get_invariants(bp);
+       if (err) {
+-              dev_err(&sdev->dev,
++              dev_err(sdev->dev,
+                       "Problem fetching invariants of chip, aborting.\n");
+               goto err_out_free_dev;
+       }
+@@ -2379,7 +2379,7 @@
+       err = register_netdev(dev);
+       if (err) {
+-              dev_err(&sdev->dev, "Cannot register net device, aborting.\n");
++              dev_err(sdev->dev, "Cannot register net device, aborting.\n");
+               goto out;
+       }
+@@ -2458,7 +2458,6 @@
+       rc = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
+       if (rc) {
+               printk(KERN_ERR PFX "%s: request_irq failed\n", dev->name);
+-              pci_disable_device(pdev);
+               return rc;
+       }
diff --git a/target/linux/brcm47xx-2.6/patches/205-ssb_integrate.patch b/target/linux/brcm47xx-2.6/patches/205-ssb_integrate.patch
new file mode 100644 (file)
index 0000000..6788245
--- /dev/null
@@ -0,0 +1,78 @@
+Index: linux-2.6.22-rc4/drivers/usb/host/Kconfig
+===================================================================
+--- linux-2.6.22-rc4.orig/drivers/usb/host/Kconfig     2007-06-10 21:32:11.000000000 +0100
++++ linux-2.6.22-rc4/drivers/usb/host/Kconfig  2007-06-10 21:33:24.000000000 +0100
+@@ -142,6 +142,19 @@
+         Enables support for PCI-bus plug-in USB controller cards.
+         If unsure, say Y.
++config USB_OHCI_HCD_SSB
++      bool "OHCI support for the Broadcom SSB OHCI core (embedded systems only)"
++      depends on USB_OHCI_HCD && ((USB_OHCI_HCD=m && SSB) || (USB_OHCI_HCD=y && SSB=y)) && EXPERIMENTAL
++      default n
++      ---help---
++        Support for the Sonics Silicon Backplane (SSB) attached
++        Broadcom USB OHCI core.
++
++        This device is only present in some embedded devices with
++        Broadcom based SSB bus.
++
++        If unsure, say N.
++
+ config USB_OHCI_BIG_ENDIAN_DESC
+       bool
+       depends on USB_OHCI_HCD
+Index: linux-2.6.22-rc4/drivers/usb/host/ohci-hcd.c
+===================================================================
+--- linux-2.6.22-rc4.orig/drivers/usb/host/ohci-hcd.c  2007-06-10 21:32:11.000000000 +0100
++++ linux-2.6.22-rc4/drivers/usb/host/ohci-hcd.c       2007-06-10 21:33:24.000000000 +0100
+@@ -920,11 +920,17 @@
+ #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_sb_driver
+ #endif
++#ifdef CONFIG_USB_OHCI_HCD_SSB
++#include "ohci-ssb.c"
++#define SSB_OHCI_DRIVER               ssb_ohci_driver
++#endif
++
+ #if   !defined(PCI_DRIVER) &&         \
+       !defined(PLATFORM_DRIVER) &&    \
+       !defined(OF_PLATFORM_DRIVER) && \
+       !defined(SA1111_DRIVER) &&      \
+-      !defined(PS3_SYSTEM_BUS_DRIVER)
++      !defined(PS3_SYSTEM_BUS_DRIVER) && \
++      !defined(SSB_OHCI_DRIVER)
+ #error "missing bus glue for ohci-hcd"
+ #endif
+@@ -972,10 +978,20 @@
+               goto error_pci;
+ #endif
++#ifdef SSB_OHCI_DRIVER
++      retval = ssb_driver_register(&SSB_OHCI_DRIVER);
++      if (retval)
++              goto error_ssb;
++#endif
++
+       return retval;
+       /* Error path */
++#ifdef SSB_OHCI_DRIVER
++ error_ssb:
++#endif
+ #ifdef PCI_DRIVER
++      pci_unregister_driver(&PCI_DRIVER);
+  error_pci:
+ #endif
+ #ifdef SA1111_DRIVER
+@@ -1001,6 +1017,9 @@
+ static void __exit ohci_hcd_mod_exit(void)
+ {
++#ifdef SSB_OHCI_DRIVER
++      ssb_driver_unregister(&SSB_OHCI_DRIVER);
++#endif
+ #ifdef PCI_DRIVER
+       pci_unregister_driver(&PCI_DRIVER);
+ #endif
diff --git a/target/linux/brcm47xx-2.6/patches/210-ssb_merge.patch b/target/linux/brcm47xx-2.6/patches/210-ssb_merge.patch
new file mode 100644 (file)
index 0000000..21986b3
--- /dev/null
@@ -0,0 +1,421 @@
+Index: linux-2.6.22-rc4/drivers/ssb/driver_chipcommon.c
+===================================================================
+--- linux-2.6.22-rc4.orig/drivers/ssb/driver_chipcommon.c      2007-06-10 21:32:11.000000000 +0100
++++ linux-2.6.22-rc4/drivers/ssb/driver_chipcommon.c   2007-06-10 21:33:25.000000000 +0100
+@@ -264,6 +264,31 @@
+       ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
+ }
++/* TODO: These two functions are a clear candidate for merging, but one gets
++ * the processor clock, and the other gets the bus clock.
++ */
++void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
++                             u32 *plltype, u32 *n, u32 *m)
++{
++      *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
++      *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
++      switch (*plltype) {
++              case SSB_PLLTYPE_2:
++              case SSB_PLLTYPE_4:
++              case SSB_PLLTYPE_6:
++              case SSB_PLLTYPE_7:
++                      *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
++                      break;
++              case SSB_PLLTYPE_3:
++                      /* 5350 uses m2 to control mips */
++                      *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
++                      break;
++              default:
++                      *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
++                      break;
++      }
++}
++
+ void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
+                                u32 *plltype, u32 *n, u32 *m)
+ {
+@@ -400,3 +425,13 @@
+       return nr_ports;
+ }
+ #endif /* CONFIG_SSB_SERIAL */
++
++/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
++int
++ssb_chipco_watchdog(struct ssb_chipcommon *cc, uint ticks)
++{
++      /* instant NMI */
++      chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
++      return 0;
++}
++EXPORT_SYMBOL(ssb_chipco_watchdog);
+Index: linux-2.6.22-rc4/drivers/ssb/driver_mipscore.c
+===================================================================
+--- linux-2.6.22-rc4.orig/drivers/ssb/driver_mipscore.c        2007-06-10 21:32:11.000000000 +0100
++++ linux-2.6.22-rc4/drivers/ssb/driver_mipscore.c     2007-06-10 21:33:25.000000000 +0100
+@@ -4,6 +4,7 @@
+  *
+  * Copyright 2005, Broadcom Corporation
+  * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
++ * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org>
+  *
+  * Licensed under the GNU/GPL. See COPYING for details.
+  */
+@@ -31,6 +32,16 @@
+       ssb_write32(mcore->dev, offset, value);
+ }
++static inline u32 extif_read32(struct ssb_extif *extif, u16 offset)
++{
++      return ssb_read32(extif->dev, offset);
++}
++
++static inline void extif_write32(struct ssb_extif *extif, u16 offset, u32 value)
++{
++      ssb_write32(extif->dev, offset, value);
++}
++
+ static const u32 ipsflag_irq_mask[] = {
+       0,
+       SSB_IPSFLAG_IRQ1,
+@@ -118,9 +129,9 @@
+ }
+ /* XXX: leave here or move into separate extif driver? */
+-static int ssb_extif_serial_init(struct ssb_device *dev, struct ssb_serial_ports *ports)
++static int ssb_extif_serial_init(struct ssb_extif *dev, struct ssb_serial_port *ports)
+ {
+-
++      return 0;
+ }
+@@ -174,23 +185,76 @@
+ {
+       struct ssb_bus *bus = mcore->dev->bus;
++      mcore->flash_buswidth = 2;
+       if (bus->chipco.dev) {
+               mcore->flash_window = 0x1c000000;
+-              mcore->flash_window_size = 0x800000;
++              mcore->flash_window_size = 0x02000000;
++              if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
++                             & SSB_CHIPCO_CFG_DS16) == 0)
++                      mcore->flash_buswidth = 1;
+       } else {
+               mcore->flash_window = 0x1fc00000;
+-              mcore->flash_window_size = 0x400000;
++              mcore->flash_window_size = 0x00400000;
+       }
+ }
++static void ssb_extif_timing_init(struct ssb_extif *extif, u32 ns)
++{
++      u32 tmp;
++
++      /* Initialize extif so we can get to the LEDs and external UART */
++      extif_write32(extif, SSB_EXTIF_PROG_CFG, SSB_EXTCFG_EN);
++
++      /* Set timing for the flash */
++      tmp  = ceildiv(10, ns) << SSB_PROG_WCNT_3_SHIFT;
++      tmp |= ceildiv(40, ns) << SSB_PROG_WCNT_1_SHIFT;
++      tmp |= ceildiv(120, ns);
++      extif_write32(extif, SSB_EXTIF_PROG_WAITCNT, tmp);
++
++      /* Set programmable interface timing for external uart */
++      tmp  = ceildiv(10, ns) << SSB_PROG_WCNT_3_SHIFT;
++      tmp |= ceildiv(20, ns) << SSB_PROG_WCNT_2_SHIFT;
++      tmp |= ceildiv(100, ns) << SSB_PROG_WCNT_1_SHIFT;
++      tmp |= ceildiv(120, ns);
++      extif_write32(extif, SSB_EXTIF_PROG_WAITCNT, tmp);
++}
+-static void ssb_cpu_clock(struct ssb_mipscore *mcore)
++static inline void ssb_extif_get_clockcontrol(struct ssb_extif *extif,
++                                              u32 *pll_type, u32 *n, u32 *m)
+ {
++      *pll_type = SSB_PLLTYPE_1;
++      *n = extif_read32(extif, SSB_EXTIF_CLOCK_N);
++      *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
+ }
+-void ssb_mipscore_init(struct ssb_mipscore *mcore)
++u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
+ {
+       struct ssb_bus *bus = mcore->dev->bus;
++      u32 pll_type, n, m, rate = 0;
++
++      if (bus->extif.dev) {
++              ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
++      } else if (bus->chipco.dev) {
++              ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
++      } else
++              return 0;
++
++      if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
++              rate = 200000000;
++      } else {
++              rate = ssb_calc_clock_rate(pll_type, n, m);
++      }
++
++      if (pll_type == SSB_PLLTYPE_6) {
++              rate *= 2;
++      }
++
++      return rate;
++}
++
++void ssb_mipscore_init(struct ssb_mipscore *mcore)
++{
++      struct ssb_bus *bus;
+       struct ssb_device *dev;
+       unsigned long hz, ns;
+       unsigned int irq, i;
+@@ -198,6 +262,8 @@
+       if (!mcore->dev)
+               return; /* We don't have a MIPS core */
++      bus = mcore->dev->bus;
++
+       ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n");
+       hz = ssb_clockspeed(bus);
+@@ -205,28 +271,9 @@
+               hz = 100000000;
+       ns = 1000000000 / hz;
+-//TODO
+-#if 0
+-      if (have EXTIF) {
+-              /* Initialize extif so we can get to the LEDs and external UART */
+-              W_REG(&eir->prog_config, CF_EN);
+-
+-              /* Set timing for the flash */
+-              tmp = CEIL(10, ns) << FW_W3_SHIFT;      /* W3 = 10nS */
+-              tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
+-              tmp = tmp | CEIL(120, ns);              /* W0 = 120nS */
+-              W_REG(&eir->prog_waitcount, tmp);       /* 0x01020a0c for a 100Mhz clock */
+-
+-              /* Set programmable interface timing for external uart */
+-              tmp = CEIL(10, ns) << FW_W3_SHIFT;      /* W3 = 10nS */
+-              tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
+-              tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
+-              tmp = tmp | CEIL(120, ns);              /* W0 = 120nS */
+-              W_REG(&eir->prog_waitcount, tmp);
+-      }
+-      else... chipcommon
+-#endif
+-      if (bus->chipco.dev)
++      if (bus->extif.dev)
++              ssb_extif_timing_init(&bus->extif, ns);
++      else if (bus->chipco.dev)
+               ssb_chipco_timing_init(&bus->chipco, ns);
+       /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
+@@ -256,3 +303,5 @@
+       ssb_mips_serial_init(mcore);
+       ssb_mips_flash_detect(mcore);
+ }
++
++EXPORT_SYMBOL(ssb_mips_irq);
+Index: linux-2.6.22-rc4/drivers/ssb/driver_pcicore.c
+===================================================================
+--- linux-2.6.22-rc4.orig/drivers/ssb/driver_pcicore.c 2007-06-10 21:32:11.000000000 +0100
++++ linux-2.6.22-rc4/drivers/ssb/driver_pcicore.c      2007-06-10 21:33:25.000000000 +0100
+@@ -93,6 +93,9 @@
+       /* Enable PCI bridge BAR1 prefetch and burst */
+       pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
++
++      /* Make sure our latency is high enough to handle the devices behind us */
++      pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xa8);
+ }
+ DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
+@@ -110,7 +113,7 @@
+       if (unlikely(pc->cardbusmode && dev > 1))
+               goto out;
+-      if (bus == 0) {
++      if (bus == 0) {//FIXME busnumber ok?
+               /* Type 0 transaction */
+               if (unlikely(dev >= SSB_PCI_SLOT_MAX))
+                       goto out;
+@@ -224,7 +227,7 @@
+               val = *((const u32 *)buf);
+               break;
+       }
+-      writel(*((const u32 *)buf), mmio);
++      writel(val, mmio);
+       err = 0;
+ unmap:
+@@ -307,6 +310,8 @@
+       udelay(150);
+       val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
+       pcicore_write32(pc, SSB_PCICORE_CTL, val);
++      val = SSB_PCICORE_ARBCTL_INTERN;
++      pcicore_write32(pc, SSB_PCICORE_ARBCTL, val); 
+       udelay(1);
+       //TODO cardbus mode
+@@ -336,6 +341,7 @@
+        * The following needs change, if we want to port hostmode
+        * to non-MIPS platform. */
+       set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
++      mdelay(300);
+       register_pci_controller(&ssb_pcicore_controller);
+ }
+Index: linux-2.6.22-rc4/include/linux/ssb/ssb_driver_chipcommon.h
+===================================================================
+--- linux-2.6.22-rc4.orig/include/linux/ssb/ssb_driver_chipcommon.h    2007-06-10 21:32:11.000000000 +0100
++++ linux-2.6.22-rc4/include/linux/ssb/ssb_driver_chipcommon.h 2007-06-10 21:33:25.000000000 +0100
+@@ -364,6 +364,8 @@
+ extern void ssb_chipco_suspend(struct ssb_chipcommon *cc, pm_message_t state);
+ extern void ssb_chipco_resume(struct ssb_chipcommon *cc);
++extern void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
++                                    u32 *plltype, u32 *n, u32 *m);
+ extern void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
+                                       u32 *plltype, u32 *n, u32 *m);
+ extern void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
+@@ -378,6 +380,46 @@
+ extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
+                                    enum ssb_clkmode mode);
++/* GPIO functions */
++static inline u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc,
++                                     u32 mask)
++{
++      return ssb_read32(cc->dev, SSB_CHIPCO_GPIOIN) & mask;
++}
++
++static inline u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc,
++                                      u32 mask, u32 value)
++{
++      return ssb_write32_masked(cc->dev, SSB_CHIPCO_GPIOOUT, mask, value);
++}
++
++static inline u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc,
++                                        u32 mask, u32 value)
++{
++      return ssb_write32_masked(cc->dev, SSB_CHIPCO_GPIOOUTEN, mask, value);
++}
++
++static inline u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc,
++                                          u32 mask, u32 value)
++{
++      return ssb_write32_masked(cc->dev, SSB_CHIPCO_GPIOCTL, mask, value);
++}
++
++static inline u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc,
++                                          u32 mask, u32 value)
++{
++      return ssb_write32_masked(cc->dev, SSB_CHIPCO_GPIOIRQ, mask, value);
++}
++
++static inline u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc,
++                                           u32 mask, u32 value)
++{
++      return ssb_write32_masked(cc->dev, SSB_CHIPCO_GPIOPOL, mask, value);
++}
++/* TODO: GPIO reservation */
++
++extern int ssb_chipco_watchdog(struct ssb_chipcommon *cc, uint ticks);
++
+ #ifdef CONFIG_SSB_SERIAL
+ extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
+                                 struct ssb_serial_port *ports);
+Index: linux-2.6.22-rc4/include/linux/ssb/ssb_driver_extif.h
+===================================================================
+--- linux-2.6.22-rc4.orig/include/linux/ssb/ssb_driver_extif.h 2007-06-10 21:32:11.000000000 +0100
++++ linux-2.6.22-rc4/include/linux/ssb/ssb_driver_extif.h      2007-06-10 21:33:25.000000000 +0100
+@@ -158,6 +158,36 @@
+ /* watchdog */
+ #define SSB_EXTIF_WATCHDOG_CLK                48000000        /* Hz */
++/* GPIO functions */
++static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif,
++                                    u32 mask)
++{
++      return ssb_read32(extif->dev, SSB_EXTIF_GPIO_IN) & mask;
++}
++
++static inline u32 ssb_extif_gpio_out(struct ssb_extif *extif,
++                                     u32 mask, u32 value)
++{
++      return ssb_write32_masked(extif->dev, SSB_EXTIF_GPIO_OUT(0), mask, value);
++}
++
++static inline u32 ssb_extif_gpio_outen(struct ssb_extif *extif,
++                                       u32 mask, u32 value)
++{
++      return ssb_write32_masked(extif->dev, SSB_EXTIF_GPIO_OUTEN(0), mask, value);
++}
++
++static inline u32 ssb_extif_gpio_polarity(struct ssb_extif *extif,
++                                          u32 mask, u32 value)
++{
++      return ssb_write32_masked(extif->dev, SSB_EXTIF_GPIO_INTPOL, mask, value);
++}
++
++static inline u32 ssb_extif_gpio_intmask(struct ssb_extif *extif,
++                                         u32 mask, u32 value)
++{
++      return ssb_write32_masked(extif->dev, SSB_EXTIF_GPIO_INTMASK, mask, value);
++}
+ #endif /* __KERNEL__ */
+ #endif /* LINUX_SSB_EXTIFCORE_H_ */
+Index: linux-2.6.22-rc4/include/linux/ssb/ssb_driver_mips.h
+===================================================================
+--- linux-2.6.22-rc4.orig/include/linux/ssb/ssb_driver_mips.h  2007-06-10 21:32:11.000000000 +0100
++++ linux-2.6.22-rc4/include/linux/ssb/ssb_driver_mips.h       2007-06-10 21:33:25.000000000 +0100
+@@ -22,11 +22,13 @@
+       int nr_serial_ports;
+       struct ssb_serial_port serial_ports[4];
++      int flash_buswidth;
+       u32 flash_window;
+       u32 flash_window_size;
+ };
+ extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
++extern u32 ssb_cpu_clock(struct ssb_mipscore *mcore);
+ extern unsigned int ssb_mips_irq(struct ssb_device *dev);
+Index: linux-2.6.22-rc4/include/linux/ssb/ssb.h
+===================================================================
+--- linux-2.6.22-rc4.orig/include/linux/ssb/ssb.h      2007-06-10 21:32:11.000000000 +0100
++++ linux-2.6.22-rc4/include/linux/ssb/ssb.h   2007-06-10 21:33:25.000000000 +0100
+@@ -263,6 +263,12 @@
+ #define SSB_CHIPPACK_BCM4712M 2       /* Medium 225pin 4712 */
+ #define SSB_CHIPPACK_BCM4712L 0       /* Large 340pin 4712 */
++static inline u16 ssb_read16(struct ssb_device *dev, u16 offset);
++static inline u32 ssb_read32(struct ssb_device *dev, u16 offset);
++static inline void ssb_write16(struct ssb_device *dev, u16 offset, u16 value);
++static inline void ssb_write32(struct ssb_device *dev, u16 offset, u32 value);
++static inline u32 ssb_write32_masked(struct ssb_device *dev, u16 offset, u32 mask, u32 value);
++
+ #include <linux/ssb/ssb_driver_chipcommon.h>
+ #include <linux/ssb/ssb_driver_mips.h>
+ #include <linux/ssb/ssb_driver_extif.h>
+@@ -369,6 +375,16 @@
+       dev->ops->write32(dev, offset, value);
+ }
++static inline u32 ssb_write32_masked(struct ssb_device *dev,
++                                     u16 offset,
++                                     u32 mask,
++                                     u32 value)
++{
++      value &= mask;
++      value |= ssb_read32(dev, offset) & ~mask;
++      ssb_write32(dev, offset, value);
++      return value;
++}
+ /* Translation (routing) bits that need to be ORed to DMA
+  * addresses before they are given to a device. */