+@@ -1171,6 +1171,7 @@ u32 ath9k_regd_get_ctl(struct ath_regula
+ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
+ {
+ struct ath_common *common = ath9k_hw_common(ah);
++ int txbuf_size;
+
+ ENABLE_REGWRITE_BUFFER(ah);
+
+@@ -1224,13 +1225,17 @@ static inline void ath9k_hw_set_dma(stru
+ * So set the usable tx buf size also to half to
+ * avoid data/delimiter underruns
+ */
+- REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
+- AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
+- } else if (!AR_SREV_9271(ah)) {
+- REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
+- AR_PCU_TXBUF_CTRL_USABLE_SIZE);
++ txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
++ } else if (AR_SREV_9340_13_OR_LATER(ah)) {
++ /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
++ txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
++ } else {
++ txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
+ }
+
++ if (!AR_SREV_9271(ah))
++ REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
++
+ REGWRITE_BUFFER_FLUSH(ah);
+
+ if (AR_SREV_9300_20_OR_LATER(ah))
+@@ -1305,9 +1310,13 @@ static bool ath9k_hw_set_reset(struct at
+ AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
+ } else {
+ tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
+- if (tmpReg &
+- (AR_INTR_SYNC_LOCAL_TIMEOUT |
+- AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
++ if (AR_SREV_9340(ah))
++ tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
++ else
++ tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
++ AR_INTR_SYNC_RADM_CPL_TIMEOUT;
++
++ if (tmpReg) {
+ u32 val;
+ REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
+
+@@ -1366,7 +1375,10 @@ static bool ath9k_hw_set_reset(struct at