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ath79: ar913x: fix eth pll register
authorChuanhong Guo <gch981213@gmail.com>
Sun, 12 Aug 2018 13:13:31 +0000 (21:13 +0800)
committerMathias Kresin <dev@kresin.me>
Mon, 13 Aug 2018 06:37:19 +0000 (08:37 +0200)
PLL for eth0 internal clock on ar913x is at 0x18050014
and AR913X_ETH0_PLL_SHIFT is 20 instead of 17

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>

No differences found
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