ramips: preliminary support for 4.14
authorRoman Yeryomin <roman@advem.lv>
Tue, 16 Jan 2018 22:07:58 +0000 (00:07 +0200)
committerJohn Crispin <john@phrozen.org>
Thu, 15 Feb 2018 09:46:39 +0000 (10:46 +0100)
- removed upstreamed patches
- 0901-spansion_nand_id_fix.patch is disabled, not clear if it's needed

Signed-off-by: Roman Yeryomin <roman@advem.lv>
Signed-off-by: John Crispin <john@phrozen.org>
77 files changed:
target/linux/generic/backport-4.14/080-v4.15-0001-arch-define-weak-abort.patch
target/linux/generic/backport-4.14/081-v4.15-0002-kernel-exit.c-export-abort-to-modules.patch
target/linux/generic/hack-4.14/204-module_strip.patch
target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/Kconfig [new file with mode: 0644]
target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/Makefile [new file with mode: 0644]
target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/esw_rt3050.c [new file with mode: 0644]
target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/esw_rt3050.h [new file with mode: 0644]
target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/ethtool.c [new file with mode: 0644]
target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/ethtool.h [new file with mode: 0644]
target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/gsw_mt7620.c [new file with mode: 0644]
target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/gsw_mt7620.h [new file with mode: 0644]
target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/gsw_mt7621.c [new file with mode: 0644]
target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mdio.c [new file with mode: 0644]
target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mdio.h [new file with mode: 0644]
target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mdio_mt7620.c [new file with mode: 0644]
target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mdio_rt2880.c [new file with mode: 0644]
target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mdio_rt2880.h [new file with mode: 0644]
target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mt7530.c [new file with mode: 0644]
target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mt7530.h [new file with mode: 0644]
target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mtk_eth_soc.c [new file with mode: 0644]
target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mtk_eth_soc.h [new file with mode: 0644]
target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/soc_mt7620.c [new file with mode: 0644]
target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/soc_mt7621.c [new file with mode: 0644]
target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/soc_rt2880.c [new file with mode: 0644]
target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/soc_rt3050.c [new file with mode: 0644]
target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/soc_rt3883.c [new file with mode: 0644]
target/linux/ramips/mt7620/config-4.14 [new file with mode: 0644]
target/linux/ramips/mt7621/config-4.14 [new file with mode: 0644]
target/linux/ramips/mt76x8/config-4.14 [new file with mode: 0644]
target/linux/ramips/patches-4.14/0004-MIPS-ralink-add-MT7621-pcie-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0005-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0006-MIPS-ralink-add-cpu-frequency-scaling.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0007-MIPS-ralink-copy-the-commandline-from-the-devicetree.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0009-PCI-MIPS-enable-PCIe-on-MT7688.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0013-owrt-hack-fix-mt7688-cache-issue.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0015-arch-mips-do-not-select-illegal-access-driver-by-def.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0024-GPIO-add-named-gpio-exports.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0025-pinctrl-ralink-add-pinctrl-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0026-DT-Add-documentation-for-gpio-ralink.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0027-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0028-GPIO-ralink-add-mt7621-gpio-controller.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0031-uvc-add-iPassion-iP2970-support.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0032-USB-dwc2-add-device_reset.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0034-NET-multi-phy-support.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0036-mtd-fix-cfi-cmdset-0002-erase-status-check.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0037-mtd-cfi-cmdset-0002-force-word-write.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0039-mtd-add-mt7621-nand-support.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0040-nand-hack-restore-write_page.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0040-nand-hack.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0041-DT-Add-documentation-for-spi-rt2880.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0042-SPI-ralink-add-Ralink-SoC-spi-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0043-spi-add-mt7621-support.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0044-i2c-MIPS-adds-ralink-I2C-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0045-i2c-add-mt7621-driver.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0046-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0047-DMA-ralink-add-rt2880-dma-engine.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0048-asoc-add-mt7620-support.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0051-serial-add-ugly-custom-baud-rate-hack.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0052-pwm-add-mediatek-support.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0053-mtd-spi-nor-add-w25q256-3b-mode-switch.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0054-mtd-add-chunked-read-io-to-m25p80.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0069-awake-rt305x-dwc2-controller.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0070-weak_reordering.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0090-ethernet.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0098-disable_cm.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0099-pci-mt7620.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0100-prom_fixes.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/0200-linkit_bootstrap.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/100-mt7621-core-detect-hack.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/101-mt7621-timer.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/302-spi-nor-add-gd25q512.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/303-spi-nor-enable-4B-opcodes-for-mx66l51235l.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/998-mt7621-needs-jiffies.patch [new file with mode: 0644]
target/linux/ramips/patches-4.14/999-fix-pci-init-mt7620.patch [new file with mode: 0644]
target/linux/ramips/rt288x/config-4.14 [new file with mode: 0644]
target/linux/ramips/rt305x/config-4.14 [new file with mode: 0644]
target/linux/ramips/rt3883/config-4.14 [new file with mode: 0644]

index 2d247a3..1867234 100644 (file)
@@ -30,11 +30,9 @@ Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
  kernel/exit.c | 8 ++++++++
  1 file changed, 8 insertions(+)
 
-diff --git a/kernel/exit.c b/kernel/exit.c
-index 6b4298a41167..df0c91d5606c 100644
 --- a/kernel/exit.c
 +++ b/kernel/exit.c
-@@ -1755,3 +1755,11 @@ COMPAT_SYSCALL_DEFINE5(waitid,
+@@ -1755,3 +1755,11 @@ Efault:
        return -EFAULT;
  }
  #endif
@@ -46,6 +44,3 @@ index 6b4298a41167..df0c91d5606c 100644
 +      /* if that doesn't kill us, halt */
 +      panic("Oops failed to kill thread");
 +}
--- 
-2.11.0
-
index 5b95b67..4c1402f 100644 (file)
@@ -24,11 +24,9 @@ Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
  kernel/exit.c                 | 1 +
  4 files changed, 1 insertion(+), 3 deletions(-)
 
-diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
-index 5cf04888c581..3e26c6f7a191 100644
 --- a/arch/arm/kernel/traps.c
 +++ b/arch/arm/kernel/traps.c
-@@ -793,7 +793,6 @@ void abort(void)
+@@ -790,7 +790,6 @@ void abort(void)
        /* if that doesn't kill us, halt */
        panic("Oops failed to kill thread");
  }
@@ -36,8 +34,6 @@ index 5cf04888c581..3e26c6f7a191 100644
  
  void __init trap_init(void)
  {
-diff --git a/arch/m32r/kernel/traps.c b/arch/m32r/kernel/traps.c
-index cb79fba79d43..b88a8dd14933 100644
 --- a/arch/m32r/kernel/traps.c
 +++ b/arch/m32r/kernel/traps.c
 @@ -122,7 +122,6 @@ void abort(void)
@@ -48,8 +44,6 @@ index cb79fba79d43..b88a8dd14933 100644
  
  void __init trap_init(void)
  {
-diff --git a/arch/unicore32/kernel/traps.c b/arch/unicore32/kernel/traps.c
-index 5f25b39f04d4..c4ac6043ebb0 100644
 --- a/arch/unicore32/kernel/traps.c
 +++ b/arch/unicore32/kernel/traps.c
 @@ -298,7 +298,6 @@ void abort(void)
@@ -60,8 +54,6 @@ index 5f25b39f04d4..c4ac6043ebb0 100644
  
  void __init trap_init(void)
  {
-diff --git a/kernel/exit.c b/kernel/exit.c
-index df0c91d5606c..995453d9fb55 100644
 --- a/kernel/exit.c
 +++ b/kernel/exit.c
 @@ -1763,3 +1763,4 @@ __weak void abort(void)
@@ -69,6 +61,3 @@ index df0c91d5606c..995453d9fb55 100644
        panic("Oops failed to kill thread");
  }
 +EXPORT_SYMBOL(abort);
--- 
-2.11.0
-
index 2cbcf0f..f450d6c 100644 (file)
@@ -133,8 +133,8 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
        }
 +#endif
  
-       check_modinfo_retpoline(mod, info);
-
+       check_modinfo_retpoline(mod, info);
 --- a/scripts/mod/modpost.c
 +++ b/scripts/mod/modpost.c
 @@ -1982,7 +1982,9 @@ static void read_symbols(char *modname)
@@ -172,12 +172,12 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  static void add_retpoline(struct buffer *b)
  {
 +#ifndef CONFIG_MODULE_STRIPPED
-       buf_printf(b, "\n#ifdef RETPOLINE\n");
-       buf_printf(b, "MODULE_INFO(retpoline, \"Y\");\n");
-       buf_printf(b, "#endif\n");
+       buf_printf(b, "\n#ifdef RETPOLINE\n");
+       buf_printf(b, "MODULE_INFO(retpoline, \"Y\");\n");
+       buf_printf(b, "#endif\n");
 +#endif
  }
-
  static void add_staging_flag(struct buffer *b, const char *name)
  {
 +#ifndef CONFIG_MODULE_STRIPPED
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/Kconfig b/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/Kconfig
new file mode 100644 (file)
index 0000000..cf883c4
--- /dev/null
@@ -0,0 +1,62 @@
+config NET_VENDOR_MEDIATEK
+       tristate "Mediatek/Ralink ethernet driver"
+       depends on RALINK
+       help
+         This driver supports the ethernet mac inside the Mediatek and Ralink WiSoCs
+
+config NET_MEDIATEK_SOC
+       def_tristate NET_VENDOR_MEDIATEK
+
+if NET_MEDIATEK_SOC
+choice
+       prompt "MAC type"
+
+config NET_MEDIATEK_RT2880
+       bool "RT2882"
+       depends on MIPS && SOC_RT288X
+
+config NET_MEDIATEK_RT3050
+       bool "RT3050/MT7628"
+       depends on MIPS && (SOC_RT305X || SOC_MT7620)
+
+config NET_MEDIATEK_RT3883
+       bool "RT3883"
+       depends on MIPS && SOC_RT3883
+
+config NET_MEDIATEK_MT7620
+       bool "MT7620"
+       depends on MIPS && SOC_MT7620
+
+config NET_MEDIATEK_MT7621
+       bool "MT7621"
+       depends on MIPS && SOC_MT7621
+
+endchoice
+
+config NET_MEDIATEK_MDIO
+       def_bool NET_MEDIATEK_SOC
+       depends on (NET_MEDIATEK_RT2880 || NET_MEDIATEK_RT3883 || NET_MEDIATEK_MT7620 || NET_MEDIATEK_MT7621)
+       select PHYLIB
+
+config NET_MEDIATEK_MDIO_RT2880
+       def_bool NET_MEDIATEK_SOC
+       depends on (NET_MEDIATEK_RT2880 || NET_MEDIATEK_RT3883)
+       select NET_MEDIATEK_MDIO
+
+config NET_MEDIATEK_MDIO_MT7620
+       def_bool NET_MEDIATEK_SOC
+       depends on (NET_MEDIATEK_MT7620 || NET_MEDIATEK_MT7621)
+       select NET_MEDIATEK_MDIO
+
+config NET_MEDIATEK_ESW_RT3050
+       def_tristate NET_MEDIATEK_SOC
+       depends on NET_MEDIATEK_RT3050
+
+config NET_MEDIATEK_GSW_MT7620
+       def_tristate NET_MEDIATEK_SOC
+       depends on NET_MEDIATEK_MT7620
+
+config NET_MEDIATEK_GSW_MT7621
+       def_tristate NET_MEDIATEK_SOC
+       depends on NET_MEDIATEK_MT7621
+endif
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/Makefile b/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/Makefile
new file mode 100644 (file)
index 0000000..07ba4c2
--- /dev/null
@@ -0,0 +1,20 @@
+#
+# Makefile for the Ralink SoCs built-in ethernet macs
+#
+
+mtk-eth-soc-y                                  += mtk_eth_soc.o ethtool.o
+
+mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MDIO)                += mdio.o
+mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MDIO_RT2880) += mdio_rt2880.o
+mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MDIO_MT7620) += mdio_mt7620.o
+
+mtk-eth-soc-$(CONFIG_NET_MEDIATEK_RT2880)      += soc_rt2880.o
+mtk-eth-soc-$(CONFIG_NET_MEDIATEK_RT3050)      += soc_rt3050.o
+mtk-eth-soc-$(CONFIG_NET_MEDIATEK_RT3883)      += soc_rt3883.o
+mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MT7620)      += soc_mt7620.o
+mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MT7621)      += soc_mt7621.o
+
+obj-$(CONFIG_NET_MEDIATEK_ESW_RT3050)          += esw_rt3050.o
+obj-$(CONFIG_NET_MEDIATEK_GSW_MT7620)          += gsw_mt7620.o mt7530.o
+obj-$(CONFIG_NET_MEDIATEK_GSW_MT7621)          += gsw_mt7621.o mt7530.o
+obj-$(CONFIG_NET_MEDIATEK_SOC)                 += mtk-eth-soc.o
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/esw_rt3050.c b/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/esw_rt3050.c
new file mode 100644 (file)
index 0000000..6cad585
--- /dev/null
@@ -0,0 +1,1461 @@
+/*   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; version 2 of the License
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
+ *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
+ *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
+ *   Copyright (C) 2016 Vittorio Gambaletta <openwrt@vittgam.net>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <asm/mach-ralink/ralink_regs.h>
+#include <linux/of_irq.h>
+
+#include <linux/switch.h>
+
+#include "mtk_eth_soc.h"
+
+/* HW limitations for this switch:
+ * - No large frame support (PKT_MAX_LEN at most 1536)
+ * - Can't have untagged vlan and tagged vlan on one port at the same time,
+ *   though this might be possible using the undocumented PPE.
+ */
+
+#define RT305X_ESW_REG_ISR             0x00
+#define RT305X_ESW_REG_IMR             0x04
+#define RT305X_ESW_REG_FCT0            0x08
+#define RT305X_ESW_REG_PFC1            0x14
+#define RT305X_ESW_REG_ATS             0x24
+#define RT305X_ESW_REG_ATS0            0x28
+#define RT305X_ESW_REG_ATS1            0x2c
+#define RT305X_ESW_REG_ATS2            0x30
+#define RT305X_ESW_REG_PVIDC(_n)       (0x40 + 4 * (_n))
+#define RT305X_ESW_REG_VLANI(_n)       (0x50 + 4 * (_n))
+#define RT305X_ESW_REG_VMSC(_n)                (0x70 + 4 * (_n))
+#define RT305X_ESW_REG_POA             0x80
+#define RT305X_ESW_REG_FPA             0x84
+#define RT305X_ESW_REG_SOCPC           0x8c
+#define RT305X_ESW_REG_POC0            0x90
+#define RT305X_ESW_REG_POC1            0x94
+#define RT305X_ESW_REG_POC2            0x98
+#define RT305X_ESW_REG_SGC             0x9c
+#define RT305X_ESW_REG_STRT            0xa0
+#define RT305X_ESW_REG_PCR0            0xc0
+#define RT305X_ESW_REG_PCR1            0xc4
+#define RT305X_ESW_REG_FPA2            0xc8
+#define RT305X_ESW_REG_FCT2            0xcc
+#define RT305X_ESW_REG_SGC2            0xe4
+#define RT305X_ESW_REG_P0LED           0xa4
+#define RT305X_ESW_REG_P1LED           0xa8
+#define RT305X_ESW_REG_P2LED           0xac
+#define RT305X_ESW_REG_P3LED           0xb0
+#define RT305X_ESW_REG_P4LED           0xb4
+#define RT305X_ESW_REG_PXPC(_x)                (0xe8 + (4 * _x))
+#define RT305X_ESW_REG_P1PC            0xec
+#define RT305X_ESW_REG_P2PC            0xf0
+#define RT305X_ESW_REG_P3PC            0xf4
+#define RT305X_ESW_REG_P4PC            0xf8
+#define RT305X_ESW_REG_P5PC            0xfc
+
+#define RT305X_ESW_LED_LINK            0
+#define RT305X_ESW_LED_100M            1
+#define RT305X_ESW_LED_DUPLEX          2
+#define RT305X_ESW_LED_ACTIVITY                3
+#define RT305X_ESW_LED_COLLISION       4
+#define RT305X_ESW_LED_LINKACT         5
+#define RT305X_ESW_LED_DUPLCOLL                6
+#define RT305X_ESW_LED_10MACT          7
+#define RT305X_ESW_LED_100MACT         8
+/* Additional led states not in datasheet: */
+#define RT305X_ESW_LED_BLINK           10
+#define RT305X_ESW_LED_ON              12
+
+#define RT305X_ESW_LINK_S              25
+#define RT305X_ESW_DUPLEX_S            9
+#define RT305X_ESW_SPD_S               0
+
+#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
+#define RT305X_ESW_PCR0_WT_PHY_CMD     BIT(13)
+#define RT305X_ESW_PCR0_CPU_PHY_REG_S  8
+
+#define RT305X_ESW_PCR1_WT_DONE                BIT(0)
+
+#define RT305X_ESW_ATS_TIMEOUT         (5 * HZ)
+#define RT305X_ESW_PHY_TIMEOUT         (5 * HZ)
+
+#define RT305X_ESW_PVIDC_PVID_M                0xfff
+#define RT305X_ESW_PVIDC_PVID_S                12
+
+#define RT305X_ESW_VLANI_VID_M         0xfff
+#define RT305X_ESW_VLANI_VID_S         12
+
+#define RT305X_ESW_VMSC_MSC_M          0xff
+#define RT305X_ESW_VMSC_MSC_S          8
+
+#define RT305X_ESW_SOCPC_DISUN2CPU_S   0
+#define RT305X_ESW_SOCPC_DISMC2CPU_S   8
+#define RT305X_ESW_SOCPC_DISBC2CPU_S   16
+#define RT305X_ESW_SOCPC_CRC_PADDING   BIT(25)
+
+#define RT305X_ESW_POC0_EN_BP_S                0
+#define RT305X_ESW_POC0_EN_FC_S                8
+#define RT305X_ESW_POC0_DIS_RMC2CPU_S  16
+#define RT305X_ESW_POC0_DIS_PORT_M     0x7f
+#define RT305X_ESW_POC0_DIS_PORT_S     23
+
+#define RT305X_ESW_POC2_UNTAG_EN_M     0xff
+#define RT305X_ESW_POC2_UNTAG_EN_S     0
+#define RT305X_ESW_POC2_ENAGING_S      8
+#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
+
+#define RT305X_ESW_SGC2_DOUBLE_TAG_M   0x7f
+#define RT305X_ESW_SGC2_DOUBLE_TAG_S   0
+#define RT305X_ESW_SGC2_LAN_PMAP_M     0x3f
+#define RT305X_ESW_SGC2_LAN_PMAP_S     24
+
+#define RT305X_ESW_PFC1_EN_VLAN_M      0xff
+#define RT305X_ESW_PFC1_EN_VLAN_S      16
+#define RT305X_ESW_PFC1_EN_TOS_S       24
+
+#define RT305X_ESW_VLAN_NONE           0xfff
+
+#define RT305X_ESW_GSC_BC_STROM_MASK   0x3
+#define RT305X_ESW_GSC_BC_STROM_SHIFT  4
+
+#define RT305X_ESW_GSC_LED_FREQ_MASK   0x3
+#define RT305X_ESW_GSC_LED_FREQ_SHIFT  23
+
+#define RT305X_ESW_POA_LINK_MASK       0x1f
+#define RT305X_ESW_POA_LINK_SHIFT      25
+
+#define RT305X_ESW_PORT_ST_CHG         BIT(26)
+#define RT305X_ESW_PORT0               0
+#define RT305X_ESW_PORT1               1
+#define RT305X_ESW_PORT2               2
+#define RT305X_ESW_PORT3               3
+#define RT305X_ESW_PORT4               4
+#define RT305X_ESW_PORT5               5
+#define RT305X_ESW_PORT6               6
+
+#define RT305X_ESW_PORTS_NONE          0
+
+#define RT305X_ESW_PMAP_LLLLLL         0x3f
+#define RT305X_ESW_PMAP_LLLLWL         0x2f
+#define RT305X_ESW_PMAP_WLLLLL         0x3e
+
+#define RT305X_ESW_PORTS_INTERNAL                                      \
+               (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |        \
+                BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |        \
+                BIT(RT305X_ESW_PORT4))
+
+#define RT305X_ESW_PORTS_NOCPU                                         \
+               (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
+
+#define RT305X_ESW_PORTS_CPU   BIT(RT305X_ESW_PORT6)
+
+#define RT305X_ESW_PORTS_ALL                                           \
+               (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
+
+#define RT305X_ESW_NUM_VLANS           16
+#define RT305X_ESW_NUM_VIDS            4096
+#define RT305X_ESW_NUM_PORTS           7
+#define RT305X_ESW_NUM_LANWAN          6
+#define RT305X_ESW_NUM_LEDS            5
+
+#define RT5350_ESW_REG_PXTPC(_x)       (0x150 + (4 * _x))
+#define RT5350_EWS_REG_LED_POLARITY    0x168
+#define RT5350_RESET_EPHY              BIT(24)
+
+enum {
+       /* Global attributes. */
+       RT305X_ESW_ATTR_ENABLE_VLAN,
+       RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
+       RT305X_ESW_ATTR_BC_STATUS,
+       RT305X_ESW_ATTR_LED_FREQ,
+       /* Port attributes. */
+       RT305X_ESW_ATTR_PORT_DISABLE,
+       RT305X_ESW_ATTR_PORT_DOUBLETAG,
+       RT305X_ESW_ATTR_PORT_UNTAG,
+       RT305X_ESW_ATTR_PORT_LED,
+       RT305X_ESW_ATTR_PORT_LAN,
+       RT305X_ESW_ATTR_PORT_RECV_BAD,
+       RT305X_ESW_ATTR_PORT_RECV_GOOD,
+       RT5350_ESW_ATTR_PORT_TR_BAD,
+       RT5350_ESW_ATTR_PORT_TR_GOOD,
+};
+
+struct esw_port {
+       bool    disable;
+       bool    doubletag;
+       bool    untag;
+       u8      led;
+       u16     pvid;
+};
+
+struct esw_vlan {
+       u8      ports;
+       u16     vid;
+};
+
+enum {
+       RT305X_ESW_VLAN_CONFIG_NONE = 0,
+       RT305X_ESW_VLAN_CONFIG_LLLLW,
+       RT305X_ESW_VLAN_CONFIG_WLLLL,
+};
+
+struct rt305x_esw {
+       struct device           *dev;
+       void __iomem            *base;
+       int                     irq;
+
+       /* Protects against concurrent register r/w operations. */
+       spinlock_t              reg_rw_lock;
+
+       unsigned char           port_map;
+       unsigned char           port_disable;
+       unsigned int            reg_initval_fct2;
+       unsigned int            reg_initval_fpa2;
+       unsigned int            reg_led_polarity;
+
+       struct switch_dev       swdev;
+       bool                    global_vlan_enable;
+       bool                    alt_vlan_disable;
+       int                     bc_storm_protect;
+       int                     led_frequency;
+       struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
+       struct esw_port ports[RT305X_ESW_NUM_PORTS];
+
+};
+
+static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
+{
+       __raw_writel(val, esw->base + reg);
+}
+
+static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
+{
+       return __raw_readl(esw->base + reg);
+}
+
+static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg,
+                              unsigned long mask, unsigned long val)
+{
+       unsigned long t;
+
+       t = __raw_readl(esw->base + reg) & ~mask;
+       __raw_writel(t | val, esw->base + reg);
+}
+
+static void esw_rmw(struct rt305x_esw *esw, unsigned reg,
+                   unsigned long mask, unsigned long val)
+{
+       unsigned long flags;
+
+       spin_lock_irqsave(&esw->reg_rw_lock, flags);
+       esw_rmw_raw(esw, reg, mask, val);
+       spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
+}
+
+static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr,
+                           u32 phy_register, u32 write_data)
+{
+       unsigned long t_start = jiffies;
+       int ret = 0;
+
+       while (1) {
+               if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
+                     RT305X_ESW_PCR1_WT_DONE))
+                       break;
+               if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
+                       ret = 1;
+                       goto out;
+               }
+       }
+
+       write_data &= 0xffff;
+       esw_w32(esw, (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
+                     (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
+                     (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
+               RT305X_ESW_REG_PCR0);
+
+       t_start = jiffies;
+       while (1) {
+               if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
+                           RT305X_ESW_PCR1_WT_DONE)
+                       break;
+
+               if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
+                       ret = 1;
+                       break;
+               }
+       }
+out:
+       if (ret)
+               dev_err(esw->dev, "ramips_eth: MDIO timeout\n");
+       return ret;
+}
+
+static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
+{
+       unsigned s;
+       unsigned val;
+
+       s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
+       val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
+       val = (val >> s) & RT305X_ESW_VLANI_VID_M;
+
+       return val;
+}
+
+static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
+{
+       unsigned s;
+
+       s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
+       esw_rmw(esw,
+                      RT305X_ESW_REG_VLANI(vlan / 2),
+                      RT305X_ESW_VLANI_VID_M << s,
+                      (vid & RT305X_ESW_VLANI_VID_M) << s);
+}
+
+static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
+{
+       unsigned s, val;
+
+       s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
+       val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
+       return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
+}
+
+static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
+{
+       unsigned s;
+
+       s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
+       esw_rmw(esw,
+                      RT305X_ESW_REG_PVIDC(port / 2),
+                      RT305X_ESW_PVIDC_PVID_M << s,
+                      (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
+}
+
+static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
+{
+       unsigned s, val;
+
+       s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
+       val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
+       val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
+
+       return val;
+}
+
+static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
+{
+       unsigned s;
+
+       s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
+       esw_rmw(esw,
+                      RT305X_ESW_REG_VMSC(vlan / 4),
+                      RT305X_ESW_VMSC_MSC_M << s,
+                      (msc & RT305X_ESW_VMSC_MSC_M) << s);
+}
+
+static unsigned esw_get_port_disable(struct rt305x_esw *esw)
+{
+       unsigned reg;
+
+       reg = esw_r32(esw, RT305X_ESW_REG_POC0);
+       return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
+              RT305X_ESW_POC0_DIS_PORT_M;
+}
+
+static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
+{
+       unsigned old_mask;
+       unsigned enable_mask;
+       unsigned changed;
+       int i;
+
+       old_mask = esw_get_port_disable(esw);
+       changed = old_mask ^ disable_mask;
+       enable_mask = old_mask & disable_mask;
+
+       /* enable before writing to MII */
+       esw_rmw(esw, RT305X_ESW_REG_POC0,
+                      (RT305X_ESW_POC0_DIS_PORT_M <<
+                       RT305X_ESW_POC0_DIS_PORT_S),
+                      enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
+
+       for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
+               if (!(changed & (1 << i)))
+                       continue;
+               if (disable_mask & (1 << i)) {
+                       /* disable */
+                       rt305x_mii_write(esw, i, MII_BMCR,
+                                        BMCR_PDOWN);
+               } else {
+                       /* enable */
+                       rt305x_mii_write(esw, i, MII_BMCR,
+                                        BMCR_FULLDPLX |
+                                        BMCR_ANENABLE |
+                                        BMCR_ANRESTART |
+                                        BMCR_SPEED100);
+               }
+       }
+
+       /* disable after writing to MII */
+       esw_rmw(esw, RT305X_ESW_REG_POC0,
+                      (RT305X_ESW_POC0_DIS_PORT_M <<
+                       RT305X_ESW_POC0_DIS_PORT_S),
+                      disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
+}
+
+static void esw_set_gsc(struct rt305x_esw *esw)
+{
+       esw_rmw(esw, RT305X_ESW_REG_SGC,
+               RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
+               esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
+       esw_rmw(esw, RT305X_ESW_REG_SGC,
+               RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
+               esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
+}
+
+static int esw_apply_config(struct switch_dev *dev);
+
+static void esw_hw_init(struct rt305x_esw *esw)
+{
+       int i;
+       u8 port_disable = 0;
+       u8 port_map = RT305X_ESW_PMAP_LLLLLL;
+
+       /* vodoo from original driver */
+       esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
+       esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
+       /* Port priority 1 for all ports, vlan enabled. */
+       esw_w32(esw, 0x00005555 |
+                    (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
+               RT305X_ESW_REG_PFC1);
+
+       /* Enable all ports, Back Pressure and Flow Control */
+       esw_w32(esw, ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
+                     (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
+               RT305X_ESW_REG_POC0);
+
+       /* Enable Aging, and VLAN TAG removal */
+       esw_w32(esw, ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
+                     (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
+               RT305X_ESW_REG_POC2);
+
+       if (esw->reg_initval_fct2)
+               esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
+       else
+               esw_w32(esw, 0x0002500c, RT305X_ESW_REG_FCT2);
+
+       /* 300s aging timer, max packet len 1536, broadcast storm prevention
+        * disabled, disable collision abort, mac xor48 hash, 10 packet back
+        * pressure jam, GMII disable was_transmit, back pressure disabled,
+        * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
+        * ports.
+        */
+       esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
+
+       /* Setup SoC Port control register */
+       esw_w32(esw,
+               (RT305X_ESW_SOCPC_CRC_PADDING |
+               (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
+               (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
+               (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
+               RT305X_ESW_REG_SOCPC);
+
+       /* ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
+        * turbo mii off, rgmi 3.3v off
+        * port5: disabled
+        * port6: enabled, gige, full-duplex, rx/tx-flow-control
+        */
+       if (esw->reg_initval_fpa2)
+               esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
+       else
+               esw_w32(esw, 0x3f502b28, RT305X_ESW_REG_FPA2);
+       esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
+
+       /* Force Link/Activity on ports */
+       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
+       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
+       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
+       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
+       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
+
+       /* Copy disabled port configuration from device tree setup */
+       port_disable = esw->port_disable;
+
+       /* Disable nonexistent ports by reading the switch config
+        * after having enabled all possible ports above
+        */
+       port_disable |= esw_get_port_disable(esw);
+
+       for (i = 0; i < 6; i++)
+               esw->ports[i].disable = (port_disable & (1 << i)) != 0;
+
+       if (ralink_soc == RT305X_SOC_RT3352) {
+               /* reset EPHY */
+               fe_reset(RT5350_RESET_EPHY);
+
+               rt305x_mii_write(esw, 0, 31, 0x8000);
+               for (i = 0; i < 5; i++) {
+                       if (esw->ports[i].disable) {
+                               rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
+                       } else {
+                               rt305x_mii_write(esw, i, MII_BMCR,
+                                                BMCR_FULLDPLX |
+                                                BMCR_ANENABLE |
+                                                BMCR_SPEED100);
+                       }
+                       /* TX10 waveform coefficient LSB=0 disable PHY */
+                       rt305x_mii_write(esw, i, 26, 0x1601);
+                       /* TX100/TX10 AD/DA current bias */
+                       rt305x_mii_write(esw, i, 29, 0x7016);
+                       /* TX100 slew rate control */
+                       rt305x_mii_write(esw, i, 30, 0x0038);
+               }
+
+               /* select global register */
+               rt305x_mii_write(esw, 0, 31, 0x0);
+               /* enlarge agcsel threshold 3 and threshold 2 */
+               rt305x_mii_write(esw, 0, 1, 0x4a40);
+               /* enlarge agcsel threshold 5 and threshold 4 */
+               rt305x_mii_write(esw, 0, 2, 0x6254);
+               /* enlarge agcsel threshold  */
+               rt305x_mii_write(esw, 0, 3, 0xa17f);
+               rt305x_mii_write(esw, 0, 12, 0x7eaa);
+               /* longer TP_IDL tail length */
+               rt305x_mii_write(esw, 0, 14, 0x65);
+               /* increased squelch pulse count threshold. */
+               rt305x_mii_write(esw, 0, 16, 0x0684);
+               /* set TX10 signal amplitude threshold to minimum */
+               rt305x_mii_write(esw, 0, 17, 0x0fe0);
+               /* set squelch amplitude to higher threshold */
+               rt305x_mii_write(esw, 0, 18, 0x40ba);
+               /* tune TP_IDL tail and head waveform, enable power
+                * down slew rate control
+                */
+               rt305x_mii_write(esw, 0, 22, 0x253f);
+               /* set PLL/Receive bias current are calibrated */
+               rt305x_mii_write(esw, 0, 27, 0x2fda);
+               /* change PLL/Receive bias current to internal(RT3350) */
+               rt305x_mii_write(esw, 0, 28, 0xc410);
+               /* change PLL bias current to internal(RT3052_MP3) */
+               rt305x_mii_write(esw, 0, 29, 0x598b);
+               /* select local register */
+               rt305x_mii_write(esw, 0, 31, 0x8000);
+       } else if (ralink_soc == RT305X_SOC_RT5350) {
+               /* reset EPHY */
+               fe_reset(RT5350_RESET_EPHY);
+
+               /* set the led polarity */
+               esw_w32(esw, esw->reg_led_polarity & 0x1F,
+                       RT5350_EWS_REG_LED_POLARITY);
+
+               /* local registers */
+               rt305x_mii_write(esw, 0, 31, 0x8000);
+               for (i = 0; i < 5; i++) {
+                       if (esw->ports[i].disable) {
+                               rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
+                       } else {
+                               rt305x_mii_write(esw, i, MII_BMCR,
+                                                BMCR_FULLDPLX |
+                                                BMCR_ANENABLE |
+                                                BMCR_SPEED100);
+                       }
+                       /* TX10 waveform coefficient LSB=0 disable PHY */
+                       rt305x_mii_write(esw, i, 26, 0x1601);
+                       /* TX100/TX10 AD/DA current bias */
+                       rt305x_mii_write(esw, i, 29, 0x7015);
+                       /* TX100 slew rate control */
+                       rt305x_mii_write(esw, i, 30, 0x0038);
+               }
+
+               /* global registers */
+               rt305x_mii_write(esw, 0, 31, 0x0);
+               /* enlarge agcsel threshold 3 and threshold 2 */
+               rt305x_mii_write(esw, 0, 1, 0x4a40);
+               /* enlarge agcsel threshold 5 and threshold 4 */
+               rt305x_mii_write(esw, 0, 2, 0x6254);
+               /* enlarge agcsel threshold 6 */
+               rt305x_mii_write(esw, 0, 3, 0xa17f);
+               rt305x_mii_write(esw, 0, 12, 0x7eaa);
+               /* longer TP_IDL tail length */
+               rt305x_mii_write(esw, 0, 14, 0x65);
+               /* increased squelch pulse count threshold. */
+               rt305x_mii_write(esw, 0, 16, 0x0684);
+               /* set TX10 signal amplitude threshold to minimum */
+               rt305x_mii_write(esw, 0, 17, 0x0fe0);
+               /* set squelch amplitude to higher threshold */
+               rt305x_mii_write(esw, 0, 18, 0x40ba);
+               /* tune TP_IDL tail and head waveform, enable power
+                * down slew rate control
+                */
+               rt305x_mii_write(esw, 0, 22, 0x253f);
+               /* set PLL/Receive bias current are calibrated */
+               rt305x_mii_write(esw, 0, 27, 0x2fda);
+               /* change PLL/Receive bias current to internal(RT3350) */
+               rt305x_mii_write(esw, 0, 28, 0xc410);
+               /* change PLL bias current to internal(RT3052_MP3) */
+               rt305x_mii_write(esw, 0, 29, 0x598b);
+               /* select local register */
+               rt305x_mii_write(esw, 0, 31, 0x8000);
+       } else if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) {
+               int i;
+
+               /* reset EPHY */
+               fe_reset(RT5350_RESET_EPHY);
+
+               rt305x_mii_write(esw, 0, 31, 0x2000); /* change G2 page */
+               rt305x_mii_write(esw, 0, 26, 0x0020);
+
+               for (i = 0; i < 5; i++) {
+                       rt305x_mii_write(esw, i, 31, 0x8000);
+                       rt305x_mii_write(esw, i,  0, 0x3100);
+                       rt305x_mii_write(esw, i, 30, 0xa000);
+                       rt305x_mii_write(esw, i, 31, 0xa000);
+                       rt305x_mii_write(esw, i, 16, 0x0606);
+                       rt305x_mii_write(esw, i, 23, 0x0f0e);
+                       rt305x_mii_write(esw, i, 24, 0x1610);
+                       rt305x_mii_write(esw, i, 30, 0x1f15);
+                       rt305x_mii_write(esw, i, 28, 0x6111);
+                       rt305x_mii_write(esw, i, 31, 0x2000);
+                       rt305x_mii_write(esw, i, 26, 0x0000);
+               }
+
+               /* 100Base AOI setting */
+               rt305x_mii_write(esw, 0, 31, 0x5000);
+               rt305x_mii_write(esw, 0, 19, 0x004a);
+               rt305x_mii_write(esw, 0, 20, 0x015a);
+               rt305x_mii_write(esw, 0, 21, 0x00ee);
+               rt305x_mii_write(esw, 0, 22, 0x0033);
+               rt305x_mii_write(esw, 0, 23, 0x020a);
+               rt305x_mii_write(esw, 0, 24, 0x0000);
+               rt305x_mii_write(esw, 0, 25, 0x024a);
+               rt305x_mii_write(esw, 0, 26, 0x035a);
+               rt305x_mii_write(esw, 0, 27, 0x02ee);
+               rt305x_mii_write(esw, 0, 28, 0x0233);
+               rt305x_mii_write(esw, 0, 29, 0x000a);
+               rt305x_mii_write(esw, 0, 30, 0x0000);
+       } else {
+               rt305x_mii_write(esw, 0, 31, 0x8000);
+               for (i = 0; i < 5; i++) {
+                       if (esw->ports[i].disable) {
+                               rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
+                       } else {
+                               rt305x_mii_write(esw, i, MII_BMCR,
+                                                BMCR_FULLDPLX |
+                                                BMCR_ANENABLE |
+                                                BMCR_SPEED100);
+                       }
+                       /* TX10 waveform coefficient */
+                       rt305x_mii_write(esw, i, 26, 0x1601);
+                       /* TX100/TX10 AD/DA current bias */
+                       rt305x_mii_write(esw, i, 29, 0x7058);
+                       /* TX100 slew rate control */
+                       rt305x_mii_write(esw, i, 30, 0x0018);
+               }
+
+               /* PHY IOT */
+               /* select global register */
+               rt305x_mii_write(esw, 0, 31, 0x0);
+               /* tune TP_IDL tail and head waveform */
+               rt305x_mii_write(esw, 0, 22, 0x052f);
+               /* set TX10 signal amplitude threshold to minimum */
+               rt305x_mii_write(esw, 0, 17, 0x0fe0);
+               /* set squelch amplitude to higher threshold */
+               rt305x_mii_write(esw, 0, 18, 0x40ba);
+               /* longer TP_IDL tail length */
+               rt305x_mii_write(esw, 0, 14, 0x65);
+               /* select local register */
+               rt305x_mii_write(esw, 0, 31, 0x8000);
+       }
+
+       if (esw->port_map)
+               port_map = esw->port_map;
+       else
+               port_map = RT305X_ESW_PMAP_LLLLLL;
+
+       /* Unused HW feature, but still nice to be consistent here...
+        * This is also exported to userspace ('lan' attribute) so it's
+        * conveniently usable to decide which ports go into the wan vlan by
+        * default.
+        */
+       esw_rmw(esw, RT305X_ESW_REG_SGC2,
+               RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
+               port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
+
+       /* make the switch leds blink */
+       for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
+               esw->ports[i].led = 0x05;
+
+       /* Apply the empty config. */
+       esw_apply_config(&esw->swdev);
+
+       /* Only unmask the port change interrupt */
+       esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
+}
+
+static irqreturn_t esw_interrupt(int irq, void *_esw)
+{
+       struct rt305x_esw *esw = (struct rt305x_esw *)_esw;
+       u32 status;
+
+       status = esw_r32(esw, RT305X_ESW_REG_ISR);
+       if (status & RT305X_ESW_PORT_ST_CHG) {
+               u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
+
+               link >>= RT305X_ESW_POA_LINK_SHIFT;
+               link &= RT305X_ESW_POA_LINK_MASK;
+               dev_info(esw->dev, "link changed 0x%02X\n", link);
+       }
+       esw_w32(esw, status, RT305X_ESW_REG_ISR);
+
+       return IRQ_HANDLED;
+}
+
+static int esw_apply_config(struct switch_dev *dev)
+{
+       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
+       int i;
+       u8 disable = 0;
+       u8 doubletag = 0;
+       u8 en_vlan = 0;
+       u8 untag = 0;
+
+       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
+               u32 vid, vmsc;
+               if (esw->global_vlan_enable) {
+                       vid = esw->vlans[i].vid;
+                       vmsc = esw->vlans[i].ports;
+               } else {
+                       vid = RT305X_ESW_VLAN_NONE;
+                       vmsc = RT305X_ESW_PORTS_NONE;
+               }
+               esw_set_vlan_id(esw, i, vid);
+               esw_set_vmsc(esw, i, vmsc);
+       }
+
+       for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
+               u32 pvid;
+               disable |= esw->ports[i].disable << i;
+               if (esw->global_vlan_enable) {
+                       doubletag |= esw->ports[i].doubletag << i;
+                       en_vlan   |= 1                       << i;
+                       untag     |= esw->ports[i].untag     << i;
+                       pvid       = esw->ports[i].pvid;
+               } else {
+                       int x = esw->alt_vlan_disable ? 0 : 1;
+                       doubletag |= x << i;
+                       en_vlan   |= x << i;
+                       untag     |= x << i;
+                       pvid       = 0;
+               }
+               esw_set_pvid(esw, i, pvid);
+               if (i < RT305X_ESW_NUM_LEDS)
+                       esw_w32(esw, esw->ports[i].led,
+                                     RT305X_ESW_REG_P0LED + 4*i);
+       }
+
+       esw_set_gsc(esw);
+       esw_set_port_disable(esw, disable);
+       esw_rmw(esw, RT305X_ESW_REG_SGC2,
+                      (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
+                       RT305X_ESW_SGC2_DOUBLE_TAG_S),
+                      doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
+       esw_rmw(esw, RT305X_ESW_REG_PFC1,
+                      RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
+                      en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
+       esw_rmw(esw, RT305X_ESW_REG_POC2,
+                      RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
+                      untag << RT305X_ESW_POC2_UNTAG_EN_S);
+
+       if (!esw->global_vlan_enable) {
+               /*
+                * Still need to put all ports into vlan 0 or they'll be
+                * isolated.
+                * NOTE: vlan 0 is special, no vlan tag is prepended
+                */
+               esw_set_vlan_id(esw, 0, 0);
+               esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
+       }
+
+       return 0;
+}
+
+static int esw_reset_switch(struct switch_dev *dev)
+{
+       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
+
+       esw->global_vlan_enable = 0;
+       memset(esw->ports, 0, sizeof(esw->ports));
+       memset(esw->vlans, 0, sizeof(esw->vlans));
+       esw_hw_init(esw);
+
+       return 0;
+}
+
+static int esw_get_vlan_enable(struct switch_dev *dev,
+                          const struct switch_attr *attr,
+                          struct switch_val *val)
+{
+       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
+
+       val->value.i = esw->global_vlan_enable;
+
+       return 0;
+}
+
+static int esw_set_vlan_enable(struct switch_dev *dev,
+                          const struct switch_attr *attr,
+                          struct switch_val *val)
+{
+       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
+
+       esw->global_vlan_enable = val->value.i != 0;
+
+       return 0;
+}
+
+static int esw_get_alt_vlan_disable(struct switch_dev *dev,
+                               const struct switch_attr *attr,
+                               struct switch_val *val)
+{
+       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
+
+       val->value.i = esw->alt_vlan_disable;
+
+       return 0;
+}
+
+static int esw_set_alt_vlan_disable(struct switch_dev *dev,
+                               const struct switch_attr *attr,
+                               struct switch_val *val)
+{
+       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
+
+       esw->alt_vlan_disable = val->value.i != 0;
+
+       return 0;
+}
+
+static int
+rt305x_esw_set_bc_status(struct switch_dev *dev,
+                       const struct switch_attr *attr,
+                       struct switch_val *val)
+{
+       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
+
+       esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
+
+       return 0;
+}
+
+static int
+rt305x_esw_get_bc_status(struct switch_dev *dev,
+                       const struct switch_attr *attr,
+                       struct switch_val *val)
+{
+       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
+
+       val->value.i = esw->bc_storm_protect;
+
+       return 0;
+}
+
+static int
+rt305x_esw_set_led_freq(struct switch_dev *dev,
+                       const struct switch_attr *attr,
+                       struct switch_val *val)
+{
+       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
+
+       esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
+
+       return 0;
+}
+
+static int
+rt305x_esw_get_led_freq(struct switch_dev *dev,
+                       const struct switch_attr *attr,
+                       struct switch_val *val)
+{
+       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
+
+       val->value.i = esw->led_frequency;
+
+       return 0;
+}
+
+static int esw_get_port_link(struct switch_dev *dev,
+                        int port,
+                        struct switch_port_link *link)
+{
+       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
+       u32 speed, poa;
+
+       if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
+               return -EINVAL;
+
+       poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
+
+       link->link = (poa >> RT305X_ESW_LINK_S) & 1;
+       link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
+       if (port < RT305X_ESW_NUM_LEDS) {
+               speed = (poa >> RT305X_ESW_SPD_S) & 1;
+       } else {
+               if (port == RT305X_ESW_NUM_PORTS - 1)
+                       poa >>= 1;
+               speed = (poa >> RT305X_ESW_SPD_S) & 3;
+       }
+       switch (speed) {
+       case 0:
+               link->speed = SWITCH_PORT_SPEED_10;
+               break;
+       case 1:
+               link->speed = SWITCH_PORT_SPEED_100;
+               break;
+       case 2:
+       case 3: /* forced gige speed can be 2 or 3 */
+               link->speed = SWITCH_PORT_SPEED_1000;
+               break;
+       default:
+               link->speed = SWITCH_PORT_SPEED_UNKNOWN;
+               break;
+       }
+
+       return 0;
+}
+
+static int esw_get_port_bool(struct switch_dev *dev,
+                        const struct switch_attr *attr,
+                        struct switch_val *val)
+{
+       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
+       int idx = val->port_vlan;
+       u32 x, reg, shift;
+
+       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
+               return -EINVAL;
+
+       switch (attr->id) {
+       case RT305X_ESW_ATTR_PORT_DISABLE:
+               reg = RT305X_ESW_REG_POC0;
+               shift = RT305X_ESW_POC0_DIS_PORT_S;
+               break;
+       case RT305X_ESW_ATTR_PORT_DOUBLETAG:
+               reg = RT305X_ESW_REG_SGC2;
+               shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
+               break;
+       case RT305X_ESW_ATTR_PORT_UNTAG:
+               reg = RT305X_ESW_REG_POC2;
+               shift = RT305X_ESW_POC2_UNTAG_EN_S;
+               break;
+       case RT305X_ESW_ATTR_PORT_LAN:
+               reg = RT305X_ESW_REG_SGC2;
+               shift = RT305X_ESW_SGC2_LAN_PMAP_S;
+               if (idx >= RT305X_ESW_NUM_LANWAN)
+                       return -EINVAL;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       x = esw_r32(esw, reg);
+       val->value.i = (x >> (idx + shift)) & 1;
+
+       return 0;
+}
+
+static int esw_set_port_bool(struct switch_dev *dev,
+                        const struct switch_attr *attr,
+                        struct switch_val *val)
+{
+       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
+       int idx = val->port_vlan;
+
+       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
+           val->value.i < 0 || val->value.i > 1)
+               return -EINVAL;
+
+       switch (attr->id) {
+       case RT305X_ESW_ATTR_PORT_DISABLE:
+               esw->ports[idx].disable = val->value.i;
+               break;
+       case RT305X_ESW_ATTR_PORT_DOUBLETAG:
+               esw->ports[idx].doubletag = val->value.i;
+               break;
+       case RT305X_ESW_ATTR_PORT_UNTAG:
+               esw->ports[idx].untag = val->value.i;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static int esw_get_port_recv_badgood(struct switch_dev *dev,
+                                const struct switch_attr *attr,
+                                struct switch_val *val)
+{
+       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
+       int idx = val->port_vlan;
+       int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
+       u32 reg;
+
+       if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
+               return -EINVAL;
+       reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
+       val->value.i = (reg >> shift) & 0xffff;
+
+       return 0;
+}
+
+static int
+esw_get_port_tr_badgood(struct switch_dev *dev,
+                                const struct switch_attr *attr,
+                                struct switch_val *val)
+{
+       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
+
+       int idx = val->port_vlan;
+       int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
+       u32 reg;
+
+       if ((ralink_soc != RT305X_SOC_RT5350) && (ralink_soc != MT762X_SOC_MT7628AN) && (ralink_soc != MT762X_SOC_MT7688))
+               return -EINVAL;
+
+       if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
+               return -EINVAL;
+
+       reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
+       val->value.i = (reg >> shift) & 0xffff;
+
+       return 0;
+}
+
+static int esw_get_port_led(struct switch_dev *dev,
+                       const struct switch_attr *attr,
+                       struct switch_val *val)
+{
+       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
+       int idx = val->port_vlan;
+
+       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
+           idx >= RT305X_ESW_NUM_LEDS)
+               return -EINVAL;
+
+       val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
+
+       return 0;
+}
+
+static int esw_set_port_led(struct switch_dev *dev,
+                       const struct switch_attr *attr,
+                       struct switch_val *val)
+{
+       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
+       int idx = val->port_vlan;
+
+       if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
+               return -EINVAL;
+
+       esw->ports[idx].led = val->value.i;
+
+       return 0;
+}
+
+static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
+{
+       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
+
+       if (port >= RT305X_ESW_NUM_PORTS)
+               return -EINVAL;
+
+       *val = esw_get_pvid(esw, port);
+
+       return 0;
+}
+
+static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
+{
+       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
+
+       if (port >= RT305X_ESW_NUM_PORTS)
+               return -EINVAL;
+
+       esw->ports[port].pvid = val;
+
+       return 0;
+}
+
+static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
+{
+       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
+       u32 vmsc, poc2;
+       int vlan_idx = -1;
+       int i;
+
+       val->len = 0;
+
+       if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
+               return -EINVAL;
+
+       /* valid vlan? */
+       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
+               if (esw_get_vlan_id(esw, i) == val->port_vlan &&
+                   esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
+                       vlan_idx = i;
+                       break;
+               }
+       }
+
+       if (vlan_idx == -1)
+               return -EINVAL;
+
+       vmsc = esw_get_vmsc(esw, vlan_idx);
+       poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
+
+       for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
+               struct switch_port *p;
+               int port_mask = 1 << i;
+
+               if (!(vmsc & port_mask))
+                       continue;
+
+               p = &val->value.ports[val->len++];
+               p->id = i;
+               if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
+                       p->flags = 0;
+               else
+                       p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
+       }
+
+       return 0;
+}
+
+static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
+{
+       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
+       int ports;
+       int vlan_idx = -1;
+       int i;
+
+       if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
+           val->len > RT305X_ESW_NUM_PORTS)
+               return -EINVAL;
+
+       /* one of the already defined vlans? */
+       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
+               if (esw->vlans[i].vid == val->port_vlan &&
+                   esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
+                       vlan_idx = i;
+                       break;
+               }
+       }
+
+       /* select a free slot */
+       for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
+               if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
+                       vlan_idx = i;
+       }
+
+       /* bail if all slots are in use */
+       if (vlan_idx == -1)
+               return -EINVAL;
+
+       ports = RT305X_ESW_PORTS_NONE;
+       for (i = 0; i < val->len; i++) {
+               struct switch_port *p = &val->value.ports[i];
+               int port_mask = 1 << p->id;
+               bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
+
+               if (p->id >= RT305X_ESW_NUM_PORTS)
+                       return -EINVAL;
+
+               ports |= port_mask;
+               esw->ports[p->id].untag = untagged;
+       }
+       esw->vlans[vlan_idx].ports = ports;
+       if (ports == RT305X_ESW_PORTS_NONE)
+               esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
+       else
+               esw->vlans[vlan_idx].vid = val->port_vlan;
+
+       return 0;
+}
+
+static const struct switch_attr esw_global[] = {
+       {
+               .type = SWITCH_TYPE_INT,
+               .name = "enable_vlan",
+               .description = "VLAN mode (1:enabled)",
+               .max = 1,
+               .id = RT305X_ESW_ATTR_ENABLE_VLAN,
+               .get = esw_get_vlan_enable,
+               .set = esw_set_vlan_enable,
+       },
+       {
+               .type = SWITCH_TYPE_INT,
+               .name = "alternate_vlan_disable",
+               .description = "Use en_vlan instead of doubletag to disable"
+                               " VLAN mode",
+               .max = 1,
+               .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
+               .get = esw_get_alt_vlan_disable,
+               .set = esw_set_alt_vlan_disable,
+       },
+       {
+               .type = SWITCH_TYPE_INT,
+               .name = "bc_storm_protect",
+               .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
+               .max = 3,
+               .id = RT305X_ESW_ATTR_BC_STATUS,
+               .get = rt305x_esw_get_bc_status,
+               .set = rt305x_esw_set_bc_status,
+       },
+       {
+               .type = SWITCH_TYPE_INT,
+               .name = "led_frequency",
+               .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
+               .max = 3,
+               .id = RT305X_ESW_ATTR_LED_FREQ,
+               .get = rt305x_esw_get_led_freq,
+               .set = rt305x_esw_set_led_freq,
+       }
+};
+
+static const struct switch_attr esw_port[] = {
+       {
+               .type = SWITCH_TYPE_INT,
+               .name = "disable",
+               .description = "Port state (1:disabled)",
+               .max = 1,
+               .id = RT305X_ESW_ATTR_PORT_DISABLE,
+               .get = esw_get_port_bool,
+               .set = esw_set_port_bool,
+       },
+       {
+               .type = SWITCH_TYPE_INT,
+               .name = "doubletag",
+               .description = "Double tagging for incoming vlan packets "
+                               "(1:enabled)",
+               .max = 1,
+               .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
+               .get = esw_get_port_bool,
+               .set = esw_set_port_bool,
+       },
+       {
+               .type = SWITCH_TYPE_INT,
+               .name = "untag",
+               .description = "Untag (1:strip outgoing vlan tag)",
+               .max = 1,
+               .id = RT305X_ESW_ATTR_PORT_UNTAG,
+               .get = esw_get_port_bool,
+               .set = esw_set_port_bool,
+       },
+       {
+               .type = SWITCH_TYPE_INT,
+               .name = "led",
+               .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
+                               " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
+                               " 8:100mact, 10:blink, 11:off, 12:on)",
+               .max = 15,
+               .id = RT305X_ESW_ATTR_PORT_LED,
+               .get = esw_get_port_led,
+               .set = esw_set_port_led,
+       },
+       {
+               .type = SWITCH_TYPE_INT,
+               .name = "lan",
+               .description = "HW port group (0:wan, 1:lan)",
+               .max = 1,
+               .id = RT305X_ESW_ATTR_PORT_LAN,
+               .get = esw_get_port_bool,
+       },
+       {
+               .type = SWITCH_TYPE_INT,
+               .name = "recv_bad",
+               .description = "Receive bad packet counter",
+               .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
+               .get = esw_get_port_recv_badgood,
+       },
+       {
+               .type = SWITCH_TYPE_INT,
+               .name = "recv_good",
+               .description = "Receive good packet counter",
+               .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
+               .get = esw_get_port_recv_badgood,
+       },
+       {
+               .type = SWITCH_TYPE_INT,
+               .name = "tr_bad",
+
+               .description = "Transmit bad packet counter. rt5350 only",
+               .id = RT5350_ESW_ATTR_PORT_TR_BAD,
+               .get = esw_get_port_tr_badgood,
+       },
+       {
+               .type = SWITCH_TYPE_INT,
+               .name = "tr_good",
+
+               .description = "Transmit good packet counter. rt5350 only",
+               .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
+               .get = esw_get_port_tr_badgood,
+       },
+};
+
+static const struct switch_attr esw_vlan[] = {
+};
+
+static const struct switch_dev_ops esw_ops = {
+       .attr_global = {
+               .attr = esw_global,
+               .n_attr = ARRAY_SIZE(esw_global),
+       },
+       .attr_port = {
+               .attr = esw_port,
+               .n_attr = ARRAY_SIZE(esw_port),
+       },
+       .attr_vlan = {
+               .attr = esw_vlan,
+               .n_attr = ARRAY_SIZE(esw_vlan),
+       },
+       .get_vlan_ports = esw_get_vlan_ports,
+       .set_vlan_ports = esw_set_vlan_ports,
+       .get_port_pvid = esw_get_port_pvid,
+       .set_port_pvid = esw_set_port_pvid,
+       .get_port_link = esw_get_port_link,
+       .apply_config = esw_apply_config,
+       .reset_switch = esw_reset_switch,
+};
+
+static int esw_probe(struct platform_device *pdev)
+{
+       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       struct device_node *np = pdev->dev.of_node;
+       const __be32 *port_map, *port_disable, *reg_init;
+       struct switch_dev *swdev;
+       struct rt305x_esw *esw;
+       int ret;
+
+       esw = devm_kzalloc(&pdev->dev, sizeof(*esw), GFP_KERNEL);
+       if (!esw)
+               return -ENOMEM;
+
+       esw->dev = &pdev->dev;
+       esw->irq = irq_of_parse_and_map(np, 0);
+       esw->base = devm_ioremap_resource(&pdev->dev, res);
+       if (!esw->base)
+               return -EADDRNOTAVAIL;
+
+       port_map = of_get_property(np, "mediatek,portmap", NULL);
+       if (port_map)
+               esw->port_map = be32_to_cpu(*port_map);
+
+       port_disable = of_get_property(np, "mediatek,portdisable", NULL);
+       if (port_disable)
+               esw->port_disable = be32_to_cpu(*port_disable);
+
+       reg_init = of_get_property(np, "ralink,fct2", NULL);
+       if (reg_init)
+               esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
+
+       reg_init = of_get_property(np, "ralink,fpa2", NULL);
+       if (reg_init)
+               esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
+
+       reg_init = of_get_property(np, "mediatek,led_polarity", NULL);
+       if (reg_init)
+               esw->reg_led_polarity = be32_to_cpu(*reg_init);
+
+       swdev = &esw->swdev;
+       swdev->of_node = pdev->dev.of_node;
+       swdev->name = "rt305x-esw";
+       swdev->alias = "rt305x";
+       swdev->cpu_port = RT305X_ESW_PORT6;
+       swdev->ports = RT305X_ESW_NUM_PORTS;
+       swdev->vlans = RT305X_ESW_NUM_VIDS;
+       swdev->ops = &esw_ops;
+
+       ret = register_switch(swdev, NULL);
+       if (ret < 0) {
+               dev_err(&pdev->dev, "register_switch failed\n");
+               return ret;
+       }
+
+       platform_set_drvdata(pdev, esw);
+
+       spin_lock_init(&esw->reg_rw_lock);
+
+       esw_hw_init(esw);
+
+       reg_init = of_get_property(np, "ralink,rgmii", NULL);
+       if (reg_init && be32_to_cpu(*reg_init) == 1) {
+               /* 
+                * External switch connected to RGMII interface. 
+                * Unregister the switch device after initialization. 
+                */
+               dev_err(&pdev->dev, "RGMII mode, not exporting switch device.\n");
+               unregister_switch(&esw->swdev);
+               platform_set_drvdata(pdev, NULL);
+               return -ENODEV;
+       }
+
+       ret = devm_request_irq(&pdev->dev, esw->irq, esw_interrupt, 0, "esw",
+                              esw);
+
+       if (!ret) {
+               esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
+               esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
+       }
+
+       return ret;
+}
+
+static int esw_remove(struct platform_device *pdev)
+{
+       struct rt305x_esw *esw = platform_get_drvdata(pdev);
+
+       if (esw) {
+               esw_w32(esw, ~0, RT305X_ESW_REG_IMR);
+               platform_set_drvdata(pdev, NULL);
+       }
+
+       return 0;
+}
+
+static const struct of_device_id ralink_esw_match[] = {
+       { .compatible = "ralink,rt3050-esw" },
+       {},
+};
+MODULE_DEVICE_TABLE(of, ralink_esw_match);
+
+static struct platform_driver esw_driver = {
+       .probe = esw_probe,
+       .remove = esw_remove,
+       .driver = {
+               .name = "rt3050-esw",
+               .owner = THIS_MODULE,
+               .of_match_table = ralink_esw_match,
+       },
+};
+
+module_platform_driver(esw_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
+MODULE_DESCRIPTION("Switch driver for RT305X SoC");
+MODULE_VERSION(MTK_FE_DRV_VERSION);
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/esw_rt3050.h b/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/esw_rt3050.h
new file mode 100644 (file)
index 0000000..b757e5d
--- /dev/null
@@ -0,0 +1,29 @@
+/*   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; version 2 of the License
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
+ *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
+ *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
+ */
+
+#ifndef _RALINK_ESW_RT3052_H__
+#define _RALINK_ESW_RT3052_H__
+
+#ifdef CONFIG_NET_MEDIATEK_ESW_RT3052
+
+int __init mtk_switch_init(void);
+void mtk_switch_exit(void);
+
+#else
+
+static inline int __init mtk_switch_init(void) { return 0; }
+static inline void mtk_switch_exit(void) { }
+
+#endif
+#endif
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/ethtool.c b/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/ethtool.c
new file mode 100644 (file)
index 0000000..803346a
--- /dev/null
@@ -0,0 +1,230 @@
+/*   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; version 2 of the License
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
+ *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
+ *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
+ */
+
+#include "mtk_eth_soc.h"
+
+static const char fe_gdma_str[][ETH_GSTRING_LEN] = {
+#define _FE(x...)      # x,
+FE_STAT_REG_DECLARE
+#undef _FE
+};
+
+static int fe_get_link_ksettings(struct net_device *ndev,
+                          struct ethtool_link_ksettings *cmd)
+{
+       struct fe_priv *priv = netdev_priv(ndev);
+
+       if (!priv->phy_dev)
+               return -ENODEV;
+
+       if (priv->phy_flags == FE_PHY_FLAG_ATTACH) {
+               if (phy_read_status(priv->phy_dev))
+                       return -ENODEV;
+       }
+
+       phy_ethtool_ksettings_get(ndev->phydev, cmd);
+
+       return 0;
+}
+
+static int fe_set_link_ksettings(struct net_device *ndev,
+                          const struct ethtool_link_ksettings *cmd)
+{
+       struct fe_priv *priv = netdev_priv(ndev);
+
+       if (!priv->phy_dev)
+               goto out_sset;
+
+       if (cmd->base.phy_address != priv->phy_dev->mdio.addr) {
+               if (priv->phy->phy_node[cmd->base.phy_address]) {
+                       priv->phy_dev = priv->phy->phy[cmd->base.phy_address];
+                       priv->phy_flags = FE_PHY_FLAG_PORT;
+               } else if (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, cmd->base.phy_address)) {
+                       priv->phy_dev = mdiobus_get_phy(priv->mii_bus, cmd->base.phy_address);
+                       priv->phy_flags = FE_PHY_FLAG_ATTACH;
+               } else {
+                       goto out_sset;
+               }
+       }
+
+       return phy_ethtool_ksettings_set(ndev->phydev, cmd);
+
+out_sset:
+       return -ENODEV;
+}
+
+static void fe_get_drvinfo(struct net_device *dev,
+                          struct ethtool_drvinfo *info)
+{
+       struct fe_priv *priv = netdev_priv(dev);
+       struct fe_soc_data *soc = priv->soc;
+
+       strlcpy(info->driver, priv->device->driver->name, sizeof(info->driver));
+       strlcpy(info->version, MTK_FE_DRV_VERSION, sizeof(info->version));
+       strlcpy(info->bus_info, dev_name(priv->device), sizeof(info->bus_info));
+
+       if (soc->reg_table[FE_REG_FE_COUNTER_BASE])
+               info->n_stats = ARRAY_SIZE(fe_gdma_str);
+}
+
+static u32 fe_get_msglevel(struct net_device *dev)
+{
+       struct fe_priv *priv = netdev_priv(dev);
+
+       return priv->msg_enable;
+}
+
+static void fe_set_msglevel(struct net_device *dev, u32 value)
+{
+       struct fe_priv *priv = netdev_priv(dev);
+
+       priv->msg_enable = value;
+}
+
+static int fe_nway_reset(struct net_device *dev)
+{
+       struct fe_priv *priv = netdev_priv(dev);
+
+       if (!priv->phy_dev)
+               goto out_nway_reset;
+
+       return genphy_restart_aneg(priv->phy_dev);
+
+out_nway_reset:
+       return -EOPNOTSUPP;
+}
+
+static u32 fe_get_link(struct net_device *dev)
+{
+       struct fe_priv *priv = netdev_priv(dev);
+       int err;
+
+       if (!priv->phy_dev)
+               goto out_get_link;
+
+       if (priv->phy_flags == FE_PHY_FLAG_ATTACH) {
+               err = genphy_update_link(priv->phy_dev);
+               if (err)
+                       goto out_get_link;
+       }
+
+       return priv->phy_dev->link;
+
+out_get_link:
+       return ethtool_op_get_link(dev);
+}
+
+static int fe_set_ringparam(struct net_device *dev,
+                           struct ethtool_ringparam *ring)
+{
+       struct fe_priv *priv = netdev_priv(dev);
+
+       if ((ring->tx_pending < 2) ||
+           (ring->rx_pending < 2) ||
+           (ring->rx_pending > MAX_DMA_DESC) ||
+           (ring->tx_pending > MAX_DMA_DESC))
+               return -EINVAL;
+
+       dev->netdev_ops->ndo_stop(dev);
+
+       priv->tx_ring.tx_ring_size = BIT(fls(ring->tx_pending) - 1);
+       priv->rx_ring.rx_ring_size = BIT(fls(ring->rx_pending) - 1);
+
+       dev->netdev_ops->ndo_open(dev);
+
+       return 0;
+}
+
+static void fe_get_ringparam(struct net_device *dev,
+                            struct ethtool_ringparam *ring)
+{
+       struct fe_priv *priv = netdev_priv(dev);
+
+       ring->rx_max_pending = MAX_DMA_DESC;
+       ring->tx_max_pending = MAX_DMA_DESC;
+       ring->rx_pending = priv->rx_ring.rx_ring_size;
+       ring->tx_pending = priv->tx_ring.tx_ring_size;
+}
+
+static void fe_get_strings(struct net_device *dev, u32 stringset, u8 *data)
+{
+       switch (stringset) {
+       case ETH_SS_STATS:
+               memcpy(data, *fe_gdma_str, sizeof(fe_gdma_str));
+               break;
+       }
+}
+
+static int fe_get_sset_count(struct net_device *dev, int sset)
+{
+       switch (sset) {
+       case ETH_SS_STATS:
+               return ARRAY_SIZE(fe_gdma_str);
+       default:
+               return -EOPNOTSUPP;
+       }
+}
+
+static void fe_get_ethtool_stats(struct net_device *dev,
+                                struct ethtool_stats *stats, u64 *data)
+{
+       struct fe_priv *priv = netdev_priv(dev);
+       struct fe_hw_stats *hwstats = priv->hw_stats;
+       u64 *data_src, *data_dst;
+       unsigned int start;
+       int i;
+
+       if (netif_running(dev) && netif_device_present(dev)) {
+               if (spin_trylock(&hwstats->stats_lock)) {
+                       fe_stats_update(priv);
+                       spin_unlock(&hwstats->stats_lock);
+               }
+       }
+
+       do {
+               data_src = &hwstats->tx_bytes;
+               data_dst = data;
+               start = u64_stats_fetch_begin_irq(&hwstats->syncp);
+
+               for (i = 0; i < ARRAY_SIZE(fe_gdma_str); i++)
+                       *data_dst++ = *data_src++;
+
+       } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
+}
+
+static struct ethtool_ops fe_ethtool_ops = {
+       .get_link_ksettings     = fe_get_link_ksettings,
+       .set_link_ksettings     = fe_set_link_ksettings,
+       .get_drvinfo            = fe_get_drvinfo,
+       .get_msglevel           = fe_get_msglevel,
+       .set_msglevel           = fe_set_msglevel,
+       .nway_reset             = fe_nway_reset,
+       .get_link               = fe_get_link,
+       .set_ringparam          = fe_set_ringparam,
+       .get_ringparam          = fe_get_ringparam,
+};
+
+void fe_set_ethtool_ops(struct net_device *netdev)
+{
+       struct fe_priv *priv = netdev_priv(netdev);
+       struct fe_soc_data *soc = priv->soc;
+
+       if (soc->reg_table[FE_REG_FE_COUNTER_BASE]) {
+               fe_ethtool_ops.get_strings = fe_get_strings;
+               fe_ethtool_ops.get_sset_count = fe_get_sset_count;
+               fe_ethtool_ops.get_ethtool_stats = fe_get_ethtool_stats;
+       }
+
+       netdev->ethtool_ops = &fe_ethtool_ops;
+}
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/ethtool.h b/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/ethtool.h
new file mode 100644 (file)
index 0000000..6fd16f0
--- /dev/null
@@ -0,0 +1,22 @@
+/*   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; version 2 of the License
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
+ *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
+ *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
+ */
+
+#ifndef FE_ETHTOOL_H
+#define FE_ETHTOOL_H
+
+#include <linux/ethtool.h>
+
+void fe_set_ethtool_ops(struct net_device *netdev);
+
+#endif /* FE_ETHTOOL_H */
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/gsw_mt7620.c b/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/gsw_mt7620.c
new file mode 100644 (file)
index 0000000..b675ad0
--- /dev/null
@@ -0,0 +1,259 @@
+/*   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; version 2 of the License
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
+ *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
+ *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+
+#include <ralink_regs.h>
+
+#include "mtk_eth_soc.h"
+#include "gsw_mt7620.h"
+
+void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
+{
+       iowrite32(val, gsw->base + reg);
+}
+
+u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg)
+{
+       return ioread32(gsw->base + reg);
+}
+
+static irqreturn_t gsw_interrupt_mt7620(int irq, void *_priv)
+{
+       struct fe_priv *priv = (struct fe_priv *)_priv;
+       struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
+       u32 status;
+       int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
+
+       status = mtk_switch_r32(gsw, GSW_REG_ISR);
+       if (status & PORT_IRQ_ST_CHG)
+               for (i = 0; i <= max; i++) {
+                       u32 status = mtk_switch_r32(gsw, GSW_REG_PORT_STATUS(i));
+                       int link = status & 0x1;
+
+                       if (link != priv->link[i])
+                               mt7620_print_link_state(priv, i, link,
+                                                       (status >> 2) & 3,
+                                                       (status & 0x2));
+
+                       priv->link[i] = link;
+               }
+       mt7620_handle_carrier(priv);
+       mtk_switch_w32(gsw, status, GSW_REG_ISR);
+
+       return IRQ_HANDLED;
+}
+
+static void mt7620_hw_init(struct mt7620_gsw *gsw, struct device_node *np)
+{
+       u32 is_BGA = (rt_sysc_r32(0x0c) >> 16) & 1;
+
+       rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
+       mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
+
+       /* Enable MIB stats */
+       mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
+
+       if (of_property_read_bool(np, "mediatek,mt7530")) {
+               u32 val;
+
+               /* turn off ephy and set phy base addr to 12 */
+               mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
+                       (0x1f << 24) | (0xc << 16),
+                       GSW_REG_GPC1);
+
+               /* set MT7530 central align */
+               val = mt7530_mdio_r32(gsw, 0x7830);
+               val &= ~BIT(0);
+               val |= BIT(1);
+               mt7530_mdio_w32(gsw, 0x7830, val);
+
+               val = mt7530_mdio_r32(gsw, 0x7a40);
+               val &= ~BIT(30);
+               mt7530_mdio_w32(gsw, 0x7a40, val);
+
+               mt7530_mdio_w32(gsw, 0x7a78, 0x855);
+       } else {
+               /* global page 4 */
+               _mt7620_mii_write(gsw, 1, 31, 0x4000);
+
+               _mt7620_mii_write(gsw, 1, 17, 0x7444);
+               if (is_BGA)
+                       _mt7620_mii_write(gsw, 1, 19, 0x0114);
+               else
+                       _mt7620_mii_write(gsw, 1, 19, 0x0117);
+
+               _mt7620_mii_write(gsw, 1, 22, 0x10cf);
+               _mt7620_mii_write(gsw, 1, 25, 0x6212);
+               _mt7620_mii_write(gsw, 1, 26, 0x0777);
+               _mt7620_mii_write(gsw, 1, 29, 0x4000);
+               _mt7620_mii_write(gsw, 1, 28, 0xc077);
+               _mt7620_mii_write(gsw, 1, 24, 0x0000);
+
+               /* global page 3 */
+               _mt7620_mii_write(gsw, 1, 31, 0x3000);
+               _mt7620_mii_write(gsw, 1, 17, 0x4838);
+
+               /* global page 2 */
+               _mt7620_mii_write(gsw, 1, 31, 0x2000);
+               if (is_BGA) {
+                       _mt7620_mii_write(gsw, 1, 21, 0x0515);
+                       _mt7620_mii_write(gsw, 1, 22, 0x0053);
+                       _mt7620_mii_write(gsw, 1, 23, 0x00bf);
+                       _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
+                       _mt7620_mii_write(gsw, 1, 25, 0x0fad);
+                       _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
+               } else {
+                       _mt7620_mii_write(gsw, 1, 21, 0x0517);
+                       _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
+                       _mt7620_mii_write(gsw, 1, 23, 0x00bf);
+                       _mt7620_mii_write(gsw, 1, 24, 0x0aab);
+                       _mt7620_mii_write(gsw, 1, 25, 0x00ae);
+                       _mt7620_mii_write(gsw, 1, 26, 0x0fff);
+               }
+               /* global page 1 */
+               _mt7620_mii_write(gsw, 1, 31, 0x1000);
+               _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
+       }
+
+       /* global page 0 */
+       _mt7620_mii_write(gsw, 1, 31, 0x8000);
+       _mt7620_mii_write(gsw, 0, 30, 0xa000);
+       _mt7620_mii_write(gsw, 1, 30, 0xa000);
+       _mt7620_mii_write(gsw, 2, 30, 0xa000);
+       _mt7620_mii_write(gsw, 3, 30, 0xa000);
+
+       _mt7620_mii_write(gsw, 0, 4, 0x05e1);
+       _mt7620_mii_write(gsw, 1, 4, 0x05e1);
+       _mt7620_mii_write(gsw, 2, 4, 0x05e1);
+       _mt7620_mii_write(gsw, 3, 4, 0x05e1);
+
+       /* global page 2 */
+       _mt7620_mii_write(gsw, 1, 31, 0xa000);
+       _mt7620_mii_write(gsw, 0, 16, 0x1111);
+       _mt7620_mii_write(gsw, 1, 16, 0x1010);
+       _mt7620_mii_write(gsw, 2, 16, 0x1515);
+       _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
+
+       /* CPU Port6 Force Link 1G, FC ON */
+       mtk_switch_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
+
+       /* Set Port 6 as CPU Port */
+       mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);
+
+       /* setup port 4 */
+       if (gsw->port4 == PORT4_EPHY) {
+               u32 val = rt_sysc_r32(SYSC_REG_CFG1);
+
+               val |= 3 << 14;
+               rt_sysc_w32(val, SYSC_REG_CFG1);
+               _mt7620_mii_write(gsw, 4, 30, 0xa000);
+               _mt7620_mii_write(gsw, 4, 4, 0x05e1);
+               _mt7620_mii_write(gsw, 4, 16, 0x1313);
+               pr_info("gsw: setting port4 to ephy mode\n");
+       }
+}
+
+static const struct of_device_id mediatek_gsw_match[] = {
+       { .compatible = "mediatek,mt7620-gsw" },
+       {},
+};
+MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
+
+int mtk_gsw_init(struct fe_priv *priv)
+{
+       struct device_node *np = priv->switch_np;
+       struct platform_device *pdev = of_find_device_by_node(np);
+       struct mt7620_gsw *gsw;
+
+       if (!pdev)
+               return -ENODEV;
+
+       if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
+               return -EINVAL;
+
+       gsw = platform_get_drvdata(pdev);
+       priv->soc->swpriv = gsw;
+
+       mt7620_hw_init(gsw, np);
+
+       if (gsw->irq) {
+               request_irq(gsw->irq, gsw_interrupt_mt7620, 0,
+                           "gsw", priv);
+               mtk_switch_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
+       }
+
+       return 0;
+}
+
+static int mt7620_gsw_probe(struct platform_device *pdev)
+{
+       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       const char *port4 = NULL;
+       struct mt7620_gsw *gsw;
+       struct device_node *np = pdev->dev.of_node;
+
+       gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
+       if (!gsw)
+               return -ENOMEM;
+
+       gsw->base = devm_ioremap_resource(&pdev->dev, res);
+       if (!gsw->base)
+               return -EADDRNOTAVAIL;
+
+       gsw->dev = &pdev->dev;
+
+       of_property_read_string(np, "mediatek,port4", &port4);
+       if (port4 && !strcmp(port4, "ephy"))
+               gsw->port4 = PORT4_EPHY;
+       else if (port4 && !strcmp(port4, "gmac"))
+               gsw->port4 = PORT4_EXT;
+       else
+               gsw->port4 = PORT4_EPHY;
+
+       gsw->irq = platform_get_irq(pdev, 0);
+
+       platform_set_drvdata(pdev, gsw);
+
+       return 0;
+}
+
+static int mt7620_gsw_remove(struct platform_device *pdev)
+{
+       platform_set_drvdata(pdev, NULL);
+
+       return 0;
+}
+
+static struct platform_driver gsw_driver = {
+       .probe = mt7620_gsw_probe,
+       .remove = mt7620_gsw_remove,
+       .driver = {
+               .name = "mt7620-gsw",
+               .owner = THIS_MODULE,
+               .of_match_table = mediatek_gsw_match,
+       },
+};
+
+module_platform_driver(gsw_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
+MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7620 SoC");
+MODULE_VERSION(MTK_FE_DRV_VERSION);
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/gsw_mt7620.h b/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/gsw_mt7620.h
new file mode 100644 (file)
index 0000000..ae0b6de
--- /dev/null
@@ -0,0 +1,127 @@
+/*   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; version 2 of the License
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
+ *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
+ *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
+ */
+
+#ifndef _RALINK_GSW_MT7620_H__
+#define _RALINK_GSW_MT7620_H__
+
+#define GSW_REG_PHY_TIMEOUT    (5 * HZ)
+
+#ifdef CONFIG_SOC_MT7621
+#define MT7620A_GSW_REG_PIAC   0x0004
+#else
+#define MT7620A_GSW_REG_PIAC   0x7004
+#endif
+
+#define GSW_NUM_VLANS          16
+#define GSW_NUM_VIDS           4096
+#define GSW_NUM_PORTS          7
+#define GSW_PORT6              6
+
+#define GSW_MDIO_ACCESS                BIT(31)
+#define GSW_MDIO_READ          BIT(19)
+#define GSW_MDIO_WRITE         BIT(18)
+#define GSW_MDIO_START         BIT(16)
+#define GSW_MDIO_ADDR_SHIFT    20
+#define GSW_MDIO_REG_SHIFT     25
+
+#define GSW_REG_MIB_CNT_EN     0x4000
+
+#define GSW_REG_PORT_PMCR(x)   (0x3000 + (x * 0x100))
+#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
+#define GSW_REG_SMACCR0                0x3fE4
+#define GSW_REG_SMACCR1                0x3fE8
+#define GSW_REG_CKGCR          0x3ff0
+
+#define GSW_REG_IMR            0x7008
+#define GSW_REG_ISR            0x700c
+#define GSW_REG_GPC1           0x7014
+
+#define GSW_REG_MAC_P0_MCR     0x100
+#define GSW_REG_MAC_P1_MCR     0x200
+
+// Global MAC control register
+#define GSW_REG_GMACCR         0x30E0
+
+#define SYSC_REG_CHIP_REV_ID   0x0c
+#define SYSC_REG_CFG1          0x14
+#define RST_CTRL_MCM           BIT(2)
+#define SYSC_PAD_RGMII2_MDIO   0x58
+#define SYSC_GPIO_MODE         0x60
+
+#define PORT_IRQ_ST_CHG                0x7f
+
+#ifdef CONFIG_SOC_MT7621
+#define ESW_PHY_POLLING                0x0000
+#else
+#define ESW_PHY_POLLING                0x7000
+#endif
+
+#define        PMCR_IPG                BIT(18)
+#define        PMCR_MAC_MODE           BIT(16)
+#define        PMCR_FORCE              BIT(15)
+#define        PMCR_TX_EN              BIT(14)
+#define        PMCR_RX_EN              BIT(13)
+#define        PMCR_BACKOFF            BIT(9)
+#define        PMCR_BACKPRES           BIT(8)
+#define        PMCR_RX_FC              BIT(5)
+#define        PMCR_TX_FC              BIT(4)
+#define        PMCR_SPEED(_x)          (_x << 2)
+#define        PMCR_DUPLEX             BIT(1)
+#define        PMCR_LINK               BIT(0)
+
+#define PHY_AN_EN              BIT(31)
+#define PHY_PRE_EN             BIT(30)
+#define PMY_MDC_CONF(_x)       ((_x & 0x3f) << 24)
+
+
+enum {
+       /* Global attributes. */
+       GSW_ATTR_ENABLE_VLAN,
+       /* Port attributes. */
+       GSW_ATTR_PORT_UNTAG,
+};
+
+enum {
+       PORT4_EPHY = 0,
+       PORT4_EXT,
+};
+
+struct mt7620_gsw {
+       struct device           *dev;
+       void __iomem            *base;
+       int                     irq;
+       int                     port4;
+       unsigned long int       autopoll;
+};
+
+void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg);
+u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg);
+int mtk_gsw_init(struct fe_priv *priv);
+
+int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
+int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
+void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
+int mt7620_has_carrier(struct fe_priv *priv);
+void mt7620_print_link_state(struct fe_priv *priv, int port, int link,
+                            int speed, int duplex);
+
+void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val);
+u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg);
+
+u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr,
+                            u32 phy_register, u32 write_data);
+u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg);
+void mt7620_handle_carrier(struct fe_priv *priv);
+
+#endif
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/gsw_mt7621.c b/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/gsw_mt7621.c
new file mode 100644 (file)
index 0000000..ef0b79e
--- /dev/null
@@ -0,0 +1,289 @@
+/*   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; version 2 of the License
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
+ *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
+ *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+
+#include <ralink_regs.h>
+
+#include "mtk_eth_soc.h"
+#include "gsw_mt7620.h"
+
+void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
+{
+       iowrite32(val, gsw->base + reg);
+}
+
+u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg)
+{
+       return ioread32(gsw->base + reg);
+}
+
+static irqreturn_t gsw_interrupt_mt7621(int irq, void *_priv)
+{
+       struct fe_priv *priv = (struct fe_priv *)_priv;
+       struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
+       u32 reg, i;
+
+       reg = mt7530_mdio_r32(gsw, 0x700c);
+
+       for (i = 0; i < 5; i++)
+               if (reg & BIT(i)) {
+                       unsigned int link;
+
+                       link = mt7530_mdio_r32(gsw,
+                                              0x3008 + (i * 0x100)) & 0x1;
+
+                       if (link != priv->link[i]) {
+                               priv->link[i] = link;
+                               if (link)
+                                       netdev_info(priv->netdev,
+                                                   "port %d link up\n", i);
+                               else
+                                       netdev_info(priv->netdev,
+                                                   "port %d link down\n", i);
+                       }
+               }
+
+       mt7620_handle_carrier(priv);
+       mt7530_mdio_w32(gsw, 0x700c, 0x1f);
+
+       return IRQ_HANDLED;
+}
+
+static void mt7621_hw_init(struct mt7620_gsw *gsw, struct device_node *np)
+{
+       u32 i;
+       u32 val;
+
+       /* wardware reset the switch */
+       fe_reset(RST_CTRL_MCM);
+       mdelay(10);
+
+       /* reduce RGMII2 PAD driving strength */
+       rt_sysc_m32(3 << 4, 0, SYSC_PAD_RGMII2_MDIO);
+
+       /* gpio mux - RGMII1=Normal mode */
+       rt_sysc_m32(BIT(14), 0, SYSC_GPIO_MODE);
+
+       /* set GMAC1 RGMII mode */
+       rt_sysc_m32(3 << 12, 0, SYSC_REG_CFG1);
+
+       /* enable MDIO to control MT7530 */
+       rt_sysc_m32(3 << 12, 0, SYSC_GPIO_MODE);
+
+       /* turn off all PHYs */
+       for (i = 0; i <= 4; i++) {
+               val = _mt7620_mii_read(gsw, i, 0x0);
+               val |= BIT(11);
+               _mt7620_mii_write(gsw, i, 0x0, val);
+       }
+
+       /* reset the switch */
+       mt7530_mdio_w32(gsw, 0x7000, 0x3);
+       usleep_range(10, 20);
+
+       if ((rt_sysc_r32(SYSC_REG_CHIP_REV_ID) & 0xFFFF) == 0x0101) {
+               /* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536) */
+               mtk_switch_w32(gsw, 0x2305e30b, GSW_REG_MAC_P0_MCR);
+               mt7530_mdio_w32(gsw, 0x3600, 0x5e30b);
+       } else {
+               /* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536) */
+               mtk_switch_w32(gsw, 0x2305e33b, GSW_REG_MAC_P0_MCR);
+               mt7530_mdio_w32(gsw, 0x3600, 0x5e33b);
+       }
+
+       /* (GE2, Link down) */
+       mtk_switch_w32(gsw, 0x8000, GSW_REG_MAC_P1_MCR);
+
+       /* Set switch max RX frame length to 2k */
+       mt7530_mdio_w32(gsw, GSW_REG_GMACCR, 0x3F0B);
+
+       /* Enable Port 6, P5 as GMAC5, P5 disable */
+       val = mt7530_mdio_r32(gsw, 0x7804);
+       val &= ~BIT(8);
+       val |= BIT(6) | BIT(13) | BIT(16);
+       mt7530_mdio_w32(gsw, 0x7804, val);
+
+       val = rt_sysc_r32(0x10);
+       val = (val >> 6) & 0x7;
+       if (val >= 6) {
+               /* 25Mhz Xtal - do nothing */
+       } else if (val >= 3) {
+               /* 40Mhz */
+
+               /* disable MT7530 core clock */
+               _mt7620_mii_write(gsw, 0, 13, 0x1f);
+               _mt7620_mii_write(gsw, 0, 14, 0x410);
+               _mt7620_mii_write(gsw, 0, 13, 0x401f);
+               _mt7620_mii_write(gsw, 0, 14, 0x0);
+
+               /* disable MT7530 PLL */
+               _mt7620_mii_write(gsw, 0, 13, 0x1f);
+               _mt7620_mii_write(gsw, 0, 14, 0x40d);
+               _mt7620_mii_write(gsw, 0, 13, 0x401f);
+               _mt7620_mii_write(gsw, 0, 14, 0x2020);
+
+               /* for MT7530 core clock = 500Mhz */
+               _mt7620_mii_write(gsw, 0, 13, 0x1f);
+               _mt7620_mii_write(gsw, 0, 14, 0x40e);
+               _mt7620_mii_write(gsw, 0, 13, 0x401f);
+               _mt7620_mii_write(gsw, 0, 14, 0x119);
+
+               /* enable MT7530 PLL */
+               _mt7620_mii_write(gsw, 0, 13, 0x1f);
+               _mt7620_mii_write(gsw, 0, 14, 0x40d);
+               _mt7620_mii_write(gsw, 0, 13, 0x401f);
+               _mt7620_mii_write(gsw, 0, 14, 0x2820);
+
+               usleep_range(20, 40);
+
+               /* enable MT7530 core clock */
+               _mt7620_mii_write(gsw, 0, 13, 0x1f);
+               _mt7620_mii_write(gsw, 0, 14, 0x410);
+               _mt7620_mii_write(gsw, 0, 13, 0x401f);
+       } else {
+               /* 20Mhz Xtal - TODO */
+       }
+
+       /* RGMII */
+       _mt7620_mii_write(gsw, 0, 14, 0x1);
+
+       /* set MT7530 central align */
+       val = mt7530_mdio_r32(gsw, 0x7830);
+       val &= ~BIT(0);
+       val |= BIT(1);
+       mt7530_mdio_w32(gsw, 0x7830, val);
+       val = mt7530_mdio_r32(gsw, 0x7a40);
+       val &= ~BIT(30);
+       mt7530_mdio_w32(gsw, 0x7a40, val);
+       mt7530_mdio_w32(gsw, 0x7a78, 0x855);
+
+       /* delay setting for 10/1000M */
+       mt7530_mdio_w32(gsw, 0x7b00, 0x102);
+       mt7530_mdio_w32(gsw, 0x7b04, 0x14);
+
+       /* lower Tx Driving*/
+       mt7530_mdio_w32(gsw, 0x7a54, 0x44);
+       mt7530_mdio_w32(gsw, 0x7a5c, 0x44);
+       mt7530_mdio_w32(gsw, 0x7a64, 0x44);
+       mt7530_mdio_w32(gsw, 0x7a6c, 0x44);
+       mt7530_mdio_w32(gsw, 0x7a74, 0x44);
+       mt7530_mdio_w32(gsw, 0x7a7c, 0x44);
+
+       /* turn on all PHYs */
+       for (i = 0; i <= 4; i++) {
+               val = _mt7620_mii_read(gsw, i, 0);
+               val &= ~BIT(11);
+               _mt7620_mii_write(gsw, i, 0, val);
+       }
+
+       /* mask irq */
+       mt7530_mdio_w32(gsw, 0x7008, 0x1f);
+       /* enable irq */
+       val = mt7530_mdio_r32(gsw, 0x7808);
+       val |= 3 << 16;
+       mt7530_mdio_w32(gsw, 0x7808, val);
+}
+
+static const struct of_device_id mediatek_gsw_match[] = {
+       { .compatible = "mediatek,mt7621-gsw" },
+       {},
+};
+MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
+
+int mtk_gsw_init(struct fe_priv *priv)
+{
+       struct device_node *np = priv->switch_np;
+       struct platform_device *pdev = of_find_device_by_node(np);
+       struct mt7620_gsw *gsw;
+
+       if (!pdev)
+               return -ENODEV;
+
+       if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
+               return -EINVAL;
+
+       gsw = platform_get_drvdata(pdev);
+       priv->soc->swpriv = gsw;
+
+       if (gsw->irq) {
+               request_irq(gsw->irq, gsw_interrupt_mt7621, 0,
+                           "gsw", priv);
+               mt7530_mdio_w32(gsw, 0x7008, ~0x1f);
+       }
+       mt7621_hw_init(gsw, np);
+
+       return 0;
+}
+
+static int mt7621_gsw_probe(struct platform_device *pdev)
+{
+       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       const char *port4 = NULL;
+       struct mt7620_gsw *gsw;
+       struct device_node *np;
+
+       gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
+       if (!gsw)
+               return -ENOMEM;
+
+       gsw->base = devm_ioremap_resource(&pdev->dev, res);
+       if (!gsw->base)
+               return -EADDRNOTAVAIL;
+
+       gsw->dev = &pdev->dev;
+
+       of_property_read_string(np, "mediatek,port4", &port4);
+       if (port4 && !strcmp(port4, "ephy"))
+               gsw->port4 = PORT4_EPHY;
+       else if (port4 && !strcmp(port4, "gmac"))
+               gsw->port4 = PORT4_EXT;
+       else
+               gsw->port4 = PORT4_EPHY;
+
+       gsw->irq = platform_get_irq(pdev, 0);
+
+       platform_set_drvdata(pdev, gsw);
+
+       return 0;
+}
+
+static int mt7621_gsw_remove(struct platform_device *pdev)
+{
+       platform_set_drvdata(pdev, NULL);
+
+       return 0;
+}
+
+static struct platform_driver gsw_driver = {
+       .probe = mt7621_gsw_probe,
+       .remove = mt7621_gsw_remove,
+       .driver = {
+               .name = "mt7621-gsw",
+               .owner = THIS_MODULE,
+               .of_match_table = mediatek_gsw_match,
+       },
+};
+
+module_platform_driver(gsw_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
+MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7621 SoC");
+MODULE_VERSION(MTK_FE_DRV_VERSION);
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mdio.c b/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mdio.c
new file mode 100644 (file)
index 0000000..d3798bb
--- /dev/null
@@ -0,0 +1,259 @@
+/*   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; version 2 of the License
+ *
+ *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
+ *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
+ *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/phy.h>
+#include <linux/of_net.h>
+#include <linux/of_mdio.h>
+
+#include "mtk_eth_soc.h"
+#include "mdio.h"
+
+static int fe_mdio_reset(struct mii_bus *bus)
+{
+       /* TODO */
+       return 0;
+}
+
+static void fe_phy_link_adjust(struct net_device *dev)
+{
+       struct fe_priv *priv = netdev_priv(dev);
+       unsigned long flags;
+       int i;
+
+       spin_lock_irqsave(&priv->phy->lock, flags);
+       for (i = 0; i < 8; i++) {
+               if (priv->phy->phy_node[i]) {
+                       struct phy_device *phydev = priv->phy->phy[i];
+                       int status_change = 0;
+
+                       if (phydev->link)
+                               if (priv->phy->duplex[i] != phydev->duplex ||
+                                   priv->phy->speed[i] != phydev->speed)
+                                       status_change = 1;
+
+                       if (phydev->link != priv->link[i])
+                               status_change = 1;
+
+                       switch (phydev->speed) {
+                       case SPEED_1000:
+                       case SPEED_100:
+                       case SPEED_10:
+                               priv->link[i] = phydev->link;
+                               priv->phy->duplex[i] = phydev->duplex;
+                               priv->phy->speed[i] = phydev->speed;
+
+                               if (status_change &&
+                                   priv->soc->mdio_adjust_link)
+                                       priv->soc->mdio_adjust_link(priv, i);
+                               break;
+                       }
+               }
+       }
+}
+
+int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node)
+{
+       const __be32 *_port = NULL;
+       struct phy_device *phydev;
+       int phy_mode, port;
+
+       _port = of_get_property(phy_node, "reg", NULL);
+
+       if (!_port || (be32_to_cpu(*_port) >= 0x20)) {
+               pr_err("%s: invalid port id\n", phy_node->name);
+               return -EINVAL;
+       }
+       port = be32_to_cpu(*_port);
+       phy_mode = of_get_phy_mode(phy_node);
+       if (phy_mode < 0) {
+               dev_err(priv->device, "incorrect phy-mode %d\n", phy_mode);
+               priv->phy->phy_node[port] = NULL;
+               return -EINVAL;
+       }
+
+       phydev = of_phy_connect(priv->netdev, phy_node, fe_phy_link_adjust,
+                               0, phy_mode);
+       if (IS_ERR(phydev)) {
+               dev_err(priv->device, "could not connect to PHY\n");
+               priv->phy->phy_node[port] = NULL;
+               return PTR_ERR(phydev);
+       }
+
+       phydev->supported &= PHY_GBIT_FEATURES;
+       phydev->advertising = phydev->supported;
+       phydev->no_auto_carrier_off = 1;
+
+       dev_info(priv->device,
+                "connected port %d to PHY at %s [uid=%08x, driver=%s]\n",
+                port, dev_name(&phydev->mdio.dev), phydev->phy_id,
+                phydev->drv->name);
+
+       priv->phy->phy[port] = phydev;
+       priv->link[port] = 0;
+
+       return 0;
+}
+
+static void phy_init(struct fe_priv *priv, struct phy_device *phy)
+{
+       phy_attach(priv->netdev, dev_name(&phy->mdio.dev), PHY_INTERFACE_MODE_MII);
+
+       phy->autoneg = AUTONEG_ENABLE;
+       phy->speed = 0;
+       phy->duplex = 0;
+       phy->supported &= PHY_BASIC_FEATURES;
+       phy->advertising = phy->supported | ADVERTISED_Autoneg;
+
+       phy_start_aneg(phy);
+}
+
+static int fe_phy_connect(struct fe_priv *priv)
+{
+       int i;
+
+       for (i = 0; i < 8; i++) {
+               if (priv->phy->phy_node[i]) {
+                       if (!priv->phy_dev) {
+                               priv->phy_dev = priv->phy->phy[i];
+                               priv->phy_flags = FE_PHY_FLAG_PORT;
+                       }
+               } else if (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, i)) {
+                       phy_init(priv, mdiobus_get_phy(priv->mii_bus, i));
+                       if (!priv->phy_dev) {
+                               priv->phy_dev = mdiobus_get_phy(priv->mii_bus, i);
+                               priv->phy_flags = FE_PHY_FLAG_ATTACH;
+                       }
+               }
+       }
+
+       return 0;
+}
+
+static void fe_phy_disconnect(struct fe_priv *priv)
+{
+       unsigned long flags;
+       int i;
+
+       for (i = 0; i < 8; i++)
+               if (priv->phy->phy_fixed[i]) {
+                       spin_lock_irqsave(&priv->phy->lock, flags);
+                       priv->link[i] = 0;
+                       if (priv->soc->mdio_adjust_link)
+                               priv->soc->mdio_adjust_link(priv, i);
+                       spin_unlock_irqrestore(&priv->phy->lock, flags);
+               } else if (priv->phy->phy[i]) {
+                       phy_disconnect(priv->phy->phy[i]);
+               } else if (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, i)) {
+                       phy_detach(mdiobus_get_phy(priv->mii_bus, i));
+               }
+}
+
+static void fe_phy_start(struct fe_priv *priv)
+{
+       unsigned long flags;
+       int i;
+
+       for (i = 0; i < 8; i++) {
+               if (priv->phy->phy_fixed[i]) {
+                       spin_lock_irqsave(&priv->phy->lock, flags);
+                       priv->link[i] = 1;
+                       if (priv->soc->mdio_adjust_link)
+                               priv->soc->mdio_adjust_link(priv, i);
+                       spin_unlock_irqrestore(&priv->phy->lock, flags);
+               } else if (priv->phy->phy[i]) {
+                       phy_start(priv->phy->phy[i]);
+               }
+       }
+}
+
+static void fe_phy_stop(struct fe_priv *priv)
+{
+       unsigned long flags;
+       int i;
+
+       for (i = 0; i < 8; i++)
+               if (priv->phy->phy_fixed[i]) {
+                       spin_lock_irqsave(&priv->phy->lock, flags);
+                       priv->link[i] = 0;
+                       if (priv->soc->mdio_adjust_link)
+                               priv->soc->mdio_adjust_link(priv, i);
+                       spin_unlock_irqrestore(&priv->phy->lock, flags);
+               } else if (priv->phy->phy[i]) {
+                       phy_stop(priv->phy->phy[i]);
+               }
+}
+
+static struct fe_phy phy_ralink = {
+       .connect = fe_phy_connect,
+       .disconnect = fe_phy_disconnect,
+       .start = fe_phy_start,
+       .stop = fe_phy_stop,
+};
+
+int fe_mdio_init(struct fe_priv *priv)
+{
+       struct device_node *mii_np;
+       int err;
+
+       if (!priv->soc->mdio_read || !priv->soc->mdio_write)
+               return 0;
+
+       spin_lock_init(&phy_ralink.lock);
+       priv->phy = &phy_ralink;
+
+       mii_np = of_get_child_by_name(priv->device->of_node, "mdio-bus");
+       if (!mii_np) {
+               dev_err(priv->device, "no %s child node found", "mdio-bus");
+               return -ENODEV;
+       }
+
+       if (!of_device_is_available(mii_np)) {
+               err = 0;
+               goto err_put_node;
+       }
+
+       priv->mii_bus = mdiobus_alloc();
+       if (!priv->mii_bus) {
+               err = -ENOMEM;
+               goto err_put_node;
+       }
+
+       priv->mii_bus->name = "mdio";
+       priv->mii_bus->read = priv->soc->mdio_read;
+       priv->mii_bus->write = priv->soc->mdio_write;
+       priv->mii_bus->reset = fe_mdio_reset;
+       priv->mii_bus->priv = priv;
+       priv->mii_bus->parent = priv->device;
+
+       snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
+       err = of_mdiobus_register(priv->mii_bus, mii_np);
+       if (err)
+               goto err_free_bus;
+
+       return 0;
+
+err_free_bus:
+       kfree(priv->mii_bus);
+err_put_node:
+       of_node_put(mii_np);
+       priv->mii_bus = NULL;
+       return err;
+}
+
+void fe_mdio_cleanup(struct fe_priv *priv)
+{
+       if (!priv->mii_bus)
+               return;
+
+       mdiobus_unregister(priv->mii_bus);
+       of_node_put(priv->mii_bus->dev.of_node);
+       kfree(priv->mii_bus);
+}
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mdio.h b/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mdio.h
new file mode 100644 (file)
index 0000000..498cf14
--- /dev/null
@@ -0,0 +1,27 @@
+/*   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; version 2 of the License
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
+ *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
+ *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
+ */
+
+#ifndef _RALINK_MDIO_H__
+#define _RALINK_MDIO_H__
+
+#ifdef CONFIG_NET_MEDIATEK_MDIO
+int fe_mdio_init(struct fe_priv *priv);
+void fe_mdio_cleanup(struct fe_priv *priv);
+int fe_connect_phy_node(struct fe_priv *priv,
+                       struct device_node *phy_node);
+#else
+static inline int fe_mdio_init(struct fe_priv *priv) { return 0; }
+static inline void fe_mdio_cleanup(struct fe_priv *priv) {}
+#endif
+#endif
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mdio_mt7620.c b/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mdio_mt7620.c
new file mode 100644 (file)
index 0000000..9efe789
--- /dev/null
@@ -0,0 +1,168 @@
+/*   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; version 2 of the License
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
+ *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
+ *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+#include "mtk_eth_soc.h"
+#include "gsw_mt7620.h"
+#include "mdio.h"
+
+static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
+{
+       unsigned long t_start = jiffies;
+
+       while (1) {
+               if (!(mtk_switch_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
+                       return 0;
+               if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT))
+                       break;
+       }
+
+       dev_err(gsw->dev, "mdio: MDIO timeout\n");
+       return -1;
+}
+
+u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr,
+                            u32 phy_register, u32 write_data)
+{
+       if (mt7620_mii_busy_wait(gsw))
+               return -1;
+
+       write_data &= 0xffff;
+
+       mtk_switch_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
+               (phy_register << GSW_MDIO_REG_SHIFT) |
+               (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
+               MT7620A_GSW_REG_PIAC);
+
+       if (mt7620_mii_busy_wait(gsw))
+               return -1;
+
+       return 0;
+}
+
+u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
+{
+       u32 d;
+
+       if (mt7620_mii_busy_wait(gsw))
+               return 0xffff;
+
+       mtk_switch_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
+               (phy_reg << GSW_MDIO_REG_SHIFT) |
+               (phy_addr << GSW_MDIO_ADDR_SHIFT),
+               MT7620A_GSW_REG_PIAC);
+
+       if (mt7620_mii_busy_wait(gsw))
+               return 0xffff;
+
+       d = mtk_switch_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
+
+       return d;
+}
+
+int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
+{
+       struct fe_priv *priv = bus->priv;
+       struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
+
+       return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
+}
+
+int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
+{
+       struct fe_priv *priv = bus->priv;
+       struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
+
+       return _mt7620_mii_read(gsw, phy_addr, phy_reg);
+}
+
+void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val)
+{
+       _mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
+       _mt7620_mii_write(gsw, 0x1f, (reg >> 2) & 0xf,  val & 0xffff);
+       _mt7620_mii_write(gsw, 0x1f, 0x10, val >> 16);
+}
+
+u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg)
+{
+       u16 high, low;
+
+       _mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
+       low = _mt7620_mii_read(gsw, 0x1f, (reg >> 2) & 0xf);
+       high = _mt7620_mii_read(gsw, 0x1f, 0x10);
+
+       return (high << 16) | (low & 0xffff);
+}
+
+static unsigned char *fe_speed_str(int speed)
+{
+       switch (speed) {
+       case 2:
+       case SPEED_1000:
+               return "1000";
+       case 1:
+       case SPEED_100:
+               return "100";
+       case 0:
+       case SPEED_10:
+               return "10";
+       }
+
+       return "? ";
+}
+
+int mt7620_has_carrier(struct fe_priv *priv)
+{
+       struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
+       int i;
+
+       for (i = 0; i < GSW_PORT6; i++)
+               if (mtk_switch_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
+                       return 1;
+       return 0;
+}
+
+
+void mt7620_handle_carrier(struct fe_priv *priv)
+{
+       if (!priv->phy)
+               return;
+
+       if (mt7620_has_carrier(priv))
+               netif_carrier_on(priv->netdev);
+       else
+               netif_carrier_off(priv->netdev);
+}
+
+void mt7620_print_link_state(struct fe_priv *priv, int port, int link,
+                            int speed, int duplex)
+{
+       if (link)
+               netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
+                           port, fe_speed_str(speed),
+                           (duplex) ? "Full" : "Half");
+       else
+               netdev_info(priv->netdev, "port %d link down\n", port);
+}
+
+void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
+{
+       mt7620_print_link_state(priv, port, priv->link[port],
+                               priv->phy->speed[port],
+                               (priv->phy->duplex[port] == DUPLEX_FULL));
+       mt7620_handle_carrier(priv);
+}
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mdio_rt2880.c b/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mdio_rt2880.c
new file mode 100644 (file)
index 0000000..e72f8c7
--- /dev/null
@@ -0,0 +1,222 @@
+/*   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; version 2 of the License
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
+ *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
+ *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/of_net.h>
+#include <linux/of_mdio.h>
+
+#include "mtk_eth_soc.h"
+#include "mdio_rt2880.h"
+#include "mdio.h"
+
+#define FE_MDIO_RETRY  1000
+
+static unsigned char *rt2880_speed_str(struct fe_priv *priv)
+{
+       switch (priv->phy->speed[0]) {
+       case SPEED_1000:
+               return "1000";
+       case SPEED_100:
+               return "100";
+       case SPEED_10:
+               return "10";
+       }
+
+       return "?";
+}
+
+void rt2880_mdio_link_adjust(struct fe_priv *priv, int port)
+{
+       u32 mdio_cfg;
+
+       if (!priv->link[0]) {
+               netif_carrier_off(priv->netdev);
+               netdev_info(priv->netdev, "link down\n");
+               return;
+       }
+
+       mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |
+                  FE_MDIO_CFG_RX_CLK_SKEW_200 |
+                  FE_MDIO_CFG_GP1_FRC_EN;
+
+       if (priv->phy->duplex[0] == DUPLEX_FULL)
+               mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;
+
+       if (priv->phy->tx_fc[0])
+               mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;
+
+       if (priv->phy->rx_fc[0])
+               mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;
+
+       switch (priv->phy->speed[0]) {
+       case SPEED_10:
+               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;
+               break;
+       case SPEED_100:
+               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;
+               break;
+       case SPEED_1000:
+               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;
+               break;
+       default:
+               BUG();
+       }
+
+       fe_w32(mdio_cfg, FE_MDIO_CFG);
+
+       netif_carrier_on(priv->netdev);
+       netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n",
+                   rt2880_speed_str(priv),
+                   (priv->phy->duplex[0] == DUPLEX_FULL) ? "Full" : "Half");
+}
+
+static int rt2880_mdio_wait_ready(struct fe_priv *priv)
+{
+       int retries;
+
+       retries = FE_MDIO_RETRY;
+       while (1) {
+               u32 t;
+
+               t = fe_r32(FE_MDIO_ACCESS);
+               if ((t & BIT(31)) == 0)
+                       return 0;
+
+               if (retries-- == 0)
+                       break;
+
+               udelay(1);
+       }
+
+       dev_err(priv->device, "MDIO operation timed out\n");
+       return -ETIMEDOUT;
+}
+
+int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
+{
+       struct fe_priv *priv = bus->priv;
+       int err;
+       u32 t;
+
+       err = rt2880_mdio_wait_ready(priv);
+       if (err)
+               return 0xffff;
+
+       t = (phy_addr << 24) | (phy_reg << 16);
+       fe_w32(t, FE_MDIO_ACCESS);
+       t |= BIT(31);
+       fe_w32(t, FE_MDIO_ACCESS);
+
+       err = rt2880_mdio_wait_ready(priv);
+       if (err)
+               return 0xffff;
+
+       pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
+                phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
+
+       return fe_r32(FE_MDIO_ACCESS) & 0xffff;
+}
+
+int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
+{
+       struct fe_priv *priv = bus->priv;
+       int err;
+       u32 t;
+
+       pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
+                phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
+
+       err = rt2880_mdio_wait_ready(priv);
+       if (err)
+               return err;
+
+       t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
+       fe_w32(t, FE_MDIO_ACCESS);
+       t |= BIT(31);
+       fe_w32(t, FE_MDIO_ACCESS);
+
+       return rt2880_mdio_wait_ready(priv);
+}
+
+void rt2880_port_init(struct fe_priv *priv, struct device_node *np)
+{
+       const __be32 *id = of_get_property(np, "reg", NULL);
+       const __be32 *link;
+       int size;
+       int phy_mode;
+
+       if (!id || (be32_to_cpu(*id) != 0)) {
+               pr_err("%s: invalid port id\n", np->name);
+               return;
+       }
+
+       priv->phy->phy_fixed[0] = of_get_property(np,
+                                                 "mediatek,fixed-link", &size);
+       if (priv->phy->phy_fixed[0] &&
+           (size != (4 * sizeof(*priv->phy->phy_fixed[0])))) {
+               pr_err("%s: invalid fixed link property\n", np->name);
+               priv->phy->phy_fixed[0] = NULL;
+               return;
+       }
+
+       phy_mode = of_get_phy_mode(np);
+       switch (phy_mode) {
+       case PHY_INTERFACE_MODE_RGMII:
+               break;
+       case PHY_INTERFACE_MODE_MII:
+               break;
+       case PHY_INTERFACE_MODE_RMII:
+               break;
+       default:
+               if (!priv->phy->phy_fixed[0])
+                       dev_err(priv->device, "port %d - invalid phy mode\n",
+                               priv->phy->speed[0]);
+               break;
+       }
+
+       priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
+       if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
+               return;
+
+       if (priv->phy->phy_fixed[0]) {
+               link = priv->phy->phy_fixed[0];
+               priv->phy->speed[0] = be32_to_cpup(link++);
+               priv->phy->duplex[0] = be32_to_cpup(link++);
+               priv->phy->tx_fc[0] = be32_to_cpup(link++);
+               priv->phy->rx_fc[0] = be32_to_cpup(link++);
+
+               priv->link[0] = 1;
+               switch (priv->phy->speed[0]) {
+               case SPEED_10:
+                       break;
+               case SPEED_100:
+                       break;
+               case SPEED_1000:
+                       break;
+               default:
+                       dev_err(priv->device, "invalid link speed: %d\n",
+                               priv->phy->speed[0]);
+                       priv->phy->phy_fixed[0] = 0;
+                       return;
+               }
+               dev_info(priv->device, "using fixed link parameters\n");
+               rt2880_mdio_link_adjust(priv, 0);
+               return;
+       }
+
+       if (priv->phy->phy_node[0] && mdiobus_get_phy(priv->mii_bus, 0))
+               fe_connect_phy_node(priv, priv->phy->phy_node[0]);
+}
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mdio_rt2880.h b/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mdio_rt2880.h
new file mode 100644 (file)
index 0000000..70e3442
--- /dev/null
@@ -0,0 +1,23 @@
+/*   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; version 2 of the License
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
+ *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
+ *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
+ */
+
+#ifndef _RALINK_MDIO_RT2880_H__
+#define _RALINK_MDIO_RT2880_H__
+
+void rt2880_mdio_link_adjust(struct fe_priv *priv, int port);
+int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
+int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
+void rt2880_port_init(struct fe_priv *priv, struct device_node *np);
+
+#endif
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mt7530.c b/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mt7530.c
new file mode 100644 (file)
index 0000000..5216cb5
--- /dev/null
@@ -0,0 +1,979 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2016 Vitaly Chekryzhev <13hakta@gmail.com>
+ */
+
+#include <linux/if.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/if_ether.h>
+#include <linux/skbuff.h>
+#include <linux/netdevice.h>
+#include <linux/netlink.h>
+#include <linux/bitops.h>
+#include <net/genetlink.h>
+#include <linux/switch.h>
+#include <linux/delay.h>
+#include <linux/phy.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/lockdep.h>
+#include <linux/workqueue.h>
+#include <linux/of_device.h>
+
+#include "mt7530.h"
+
+#define MT7530_CPU_PORT                6
+#define MT7530_NUM_PORTS       8
+#ifdef CONFIG_SOC_MT7621
+#define MT7530_NUM_VLANS       4095
+#else
+#define MT7530_NUM_VLANS       16
+#endif
+#define MT7530_MAX_VID         4095
+#define MT7530_MIN_VID         0
+
+#define MT7530_PORT_MIB_TXB_ID 2       /* TxGOC */
+#define MT7530_PORT_MIB_RXB_ID 6       /* RxGOC */
+
+#define MT7621_PORT_MIB_TXB_ID 18      /* TxByte */
+#define MT7621_PORT_MIB_RXB_ID 37      /* RxByte */
+
+/* registers */
+#define REG_ESW_VLAN_VTCR              0x90
+#define REG_ESW_VLAN_VAWD1             0x94
+#define REG_ESW_VLAN_VAWD2             0x98
+#define REG_ESW_VLAN_VTIM(x)   (0x100 + 4 * ((x) / 2))
+
+#define REG_ESW_VLAN_VAWD1_IVL_MAC     BIT(30)
+#define REG_ESW_VLAN_VAWD1_VTAG_EN     BIT(28)
+#define REG_ESW_VLAN_VAWD1_VALID       BIT(0)
+
+/* vlan egress mode */
+enum {
+       ETAG_CTRL_UNTAG = 0,
+       ETAG_CTRL_TAG   = 2,
+       ETAG_CTRL_SWAP  = 1,
+       ETAG_CTRL_STACK = 3,
+};
+
+#define REG_ESW_PORT_PCR(x)    (0x2004 | ((x) << 8))
+#define REG_ESW_PORT_PVC(x)    (0x2010 | ((x) << 8))
+#define REG_ESW_PORT_PPBV1(x)  (0x2014 | ((x) << 8))
+
+#define REG_HWTRAP             0x7804
+
+#define MIB_DESC(_s , _o, _n)   \
+       {                       \
+               .size = (_s),   \
+               .offset = (_o), \
+               .name = (_n),   \
+       }
+
+struct mt7xxx_mib_desc {
+       unsigned int size;
+       unsigned int offset;
+       const char *name;
+};
+
+static const struct mt7xxx_mib_desc mt7620_mibs[] = {
+       MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT0, "PPE_AC_BCNT0"),
+       MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT0, "PPE_AC_PCNT0"),
+       MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT63, "PPE_AC_BCNT63"),
+       MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT63, "PPE_AC_PCNT63"),
+       MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT0, "PPE_MTR_CNT0"),
+       MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT63, "PPE_MTR_CNT63"),
+       MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GBCNT, "GDM1_TX_GBCNT"),
+       MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GPCNT, "GDM1_TX_GPCNT"),
+       MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_SKIPCNT, "GDM1_TX_SKIPCNT"),
+       MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_COLCNT, "GDM1_TX_COLCNT"),
+       MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GBCNT1, "GDM1_RX_GBCNT1"),
+       MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GPCNT1, "GDM1_RX_GPCNT1"),
+       MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_OERCNT, "GDM1_RX_OERCNT"),
+       MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FERCNT, "GDM1_RX_FERCNT"),
+       MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_SERCNT, "GDM1_RX_SERCNT"),
+       MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_LERCNT, "GDM1_RX_LERCNT"),
+       MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_CERCNT, "GDM1_RX_CERCNT"),
+       MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FCCNT, "GDM1_RX_FCCNT"),
+       MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GBCNT, "GDM2_TX_GBCNT"),
+       MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GPCNT, "GDM2_TX_GPCNT"),
+       MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_SKIPCNT, "GDM2_TX_SKIPCNT"),
+       MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_COLCNT, "GDM2_TX_COLCNT"),
+       MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GBCNT, "GDM2_RX_GBCNT"),
+       MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GPCNT, "GDM2_RX_GPCNT"),
+       MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_OERCNT, "GDM2_RX_OERCNT"),
+       MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FERCNT, "GDM2_RX_FERCNT"),
+       MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_SERCNT, "GDM2_RX_SERCNT"),
+       MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_LERCNT, "GDM2_RX_LERCNT"),
+       MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_CERCNT, "GDM2_RX_CERCNT"),
+       MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FCCNT, "GDM2_RX_FCCNT")
+};
+
+static const struct mt7xxx_mib_desc mt7620_port_mibs[] = {
+       MIB_DESC(1, MT7620_MIB_STATS_PORT_TGPCN,  "TxGPC"),
+       MIB_DESC(1, MT7620_MIB_STATS_PORT_TBOCN,  "TxBOC"),
+       MIB_DESC(1, MT7620_MIB_STATS_PORT_TGOCN,  "TxGOC"),
+       MIB_DESC(1, MT7620_MIB_STATS_PORT_TEPCN,  "TxEPC"),
+       MIB_DESC(1, MT7620_MIB_STATS_PORT_RGPCN,  "RxGPC"),
+       MIB_DESC(1, MT7620_MIB_STATS_PORT_RBOCN,  "RxBOC"),
+       MIB_DESC(1, MT7620_MIB_STATS_PORT_RGOCN,  "RxGOC"),
+       MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC1N, "RxEPC1"),
+       MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC2N, "RxEPC2")
+};
+
+static const struct mt7xxx_mib_desc mt7621_mibs[] = {
+       MIB_DESC(1, MT7621_STATS_TDPC, "TxDrop"),
+       MIB_DESC(1, MT7621_STATS_TCRC, "TxCRC"),
+       MIB_DESC(1, MT7621_STATS_TUPC, "TxUni"),
+       MIB_DESC(1, MT7621_STATS_TMPC, "TxMulti"),
+       MIB_DESC(1, MT7621_STATS_TBPC, "TxBroad"),
+       MIB_DESC(1, MT7621_STATS_TCEC, "TxCollision"),
+       MIB_DESC(1, MT7621_STATS_TSCEC, "TxSingleCol"),
+       MIB_DESC(1, MT7621_STATS_TMCEC, "TxMultiCol"),
+       MIB_DESC(1, MT7621_STATS_TDEC, "TxDefer"),
+       MIB_DESC(1, MT7621_STATS_TLCEC, "TxLateCol"),
+       MIB_DESC(1, MT7621_STATS_TXCEC, "TxExcCol"),
+       MIB_DESC(1, MT7621_STATS_TPPC, "TxPause"),
+       MIB_DESC(1, MT7621_STATS_TL64PC, "Tx64Byte"),
+       MIB_DESC(1, MT7621_STATS_TL65PC, "Tx65Byte"),
+       MIB_DESC(1, MT7621_STATS_TL128PC, "Tx128Byte"),
+       MIB_DESC(1, MT7621_STATS_TL256PC, "Tx256Byte"),
+       MIB_DESC(1, MT7621_STATS_TL512PC, "Tx512Byte"),
+       MIB_DESC(1, MT7621_STATS_TL1024PC, "Tx1024Byte"),
+       MIB_DESC(2, MT7621_STATS_TOC, "TxByte"),
+       MIB_DESC(1, MT7621_STATS_RDPC, "RxDrop"),
+       MIB_DESC(1, MT7621_STATS_RFPC, "RxFiltered"),
+       MIB_DESC(1, MT7621_STATS_RUPC, "RxUni"),
+       MIB_DESC(1, MT7621_STATS_RMPC, "RxMulti"),
+       MIB_DESC(1, MT7621_STATS_RBPC, "RxBroad"),
+       MIB_DESC(1, MT7621_STATS_RAEPC, "RxAlignErr"),
+       MIB_DESC(1, MT7621_STATS_RCEPC, "RxCRC"),
+       MIB_DESC(1, MT7621_STATS_RUSPC, "RxUnderSize"),
+       MIB_DESC(1, MT7621_STATS_RFEPC, "RxFragment"),
+       MIB_DESC(1, MT7621_STATS_ROSPC, "RxOverSize"),
+       MIB_DESC(1, MT7621_STATS_RJEPC, "RxJabber"),
+       MIB_DESC(1, MT7621_STATS_RPPC, "RxPause"),
+       MIB_DESC(1, MT7621_STATS_RL64PC, "Rx64Byte"),
+       MIB_DESC(1, MT7621_STATS_RL65PC, "Rx65Byte"),
+       MIB_DESC(1, MT7621_STATS_RL128PC, "Rx128Byte"),
+       MIB_DESC(1, MT7621_STATS_RL256PC, "Rx256Byte"),
+       MIB_DESC(1, MT7621_STATS_RL512PC, "Rx512Byte"),
+       MIB_DESC(1, MT7621_STATS_RL1024PC, "Rx1024Byte"),
+       MIB_DESC(2, MT7621_STATS_ROC, "RxByte"),
+       MIB_DESC(1, MT7621_STATS_RDPC_CTRL, "RxCtrlDrop"),
+       MIB_DESC(1, MT7621_STATS_RDPC_ING, "RxIngDrop"),
+       MIB_DESC(1, MT7621_STATS_RDPC_ARL, "RxARLDrop")
+};
+
+enum {
+       /* Global attributes. */
+       MT7530_ATTR_ENABLE_VLAN,
+};
+
+struct mt7530_port_entry {
+       u16     pvid;
+};
+
+struct mt7530_vlan_entry {
+       u16     vid;
+       u8      member;
+       u8      etags;
+};
+
+struct mt7530_priv {
+       void __iomem            *base;
+       struct mii_bus          *bus;
+       struct switch_dev       swdev;
+
+       bool                    global_vlan_enable;
+       struct mt7530_vlan_entry        vlan_entries[MT7530_NUM_VLANS];
+       struct mt7530_port_entry        port_entries[MT7530_NUM_PORTS];
+};
+
+struct mt7530_mapping {
+       char    *name;
+       u16     pvids[MT7530_NUM_PORTS];
+       u8      members[MT7530_NUM_VLANS];
+       u8      etags[MT7530_NUM_VLANS];
+       u16     vids[MT7530_NUM_VLANS];
+} mt7530_defaults[] = {
+       {
+               .name = "llllw",
+               .pvids = { 1, 1, 1, 1, 2, 1, 1 },
+               .members = { 0, 0x6f, 0x50 },
+               .etags = { 0, 0x40, 0x40 },
+               .vids = { 0, 1, 2 },
+       }, {
+               .name = "wllll",
+               .pvids = { 2, 1, 1, 1, 1, 1, 1 },
+               .members = { 0, 0x7e, 0x41 },
+               .etags = { 0, 0x40, 0x40 },
+               .vids = { 0, 1, 2 },
+       }, {
+               .name = "lwlll",
+               .pvids = { 1, 2, 1, 1, 1, 1, 1 },
+               .members = { 0, 0x7d, 0x42 },
+               .etags = { 0, 0x40, 0x40 },
+               .vids = { 0, 1, 2 },
+       },
+};
+
+struct mt7530_mapping*
+mt7530_find_mapping(struct device_node *np)
+{
+       const char *map;
+       int i;
+
+       if (of_property_read_string(np, "mediatek,portmap", &map))
+               return NULL;
+
+       for (i = 0; i < ARRAY_SIZE(mt7530_defaults); i++)
+               if (!strcmp(map, mt7530_defaults[i].name))
+                       return &mt7530_defaults[i];
+
+       return NULL;
+}
+
+static void
+mt7530_apply_mapping(struct mt7530_priv *mt7530, struct mt7530_mapping *map)
+{
+       int i = 0;
+
+       for (i = 0; i < MT7530_NUM_PORTS; i++)
+               mt7530->port_entries[i].pvid = map->pvids[i];
+
+       for (i = 0; i < MT7530_NUM_VLANS; i++) {
+               mt7530->vlan_entries[i].member = map->members[i];
+               mt7530->vlan_entries[i].etags = map->etags[i];
+               mt7530->vlan_entries[i].vid = map->vids[i];
+       }
+}
+
+static int
+mt7530_reset_switch(struct switch_dev *dev)
+{
+       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
+       int i;
+
+       memset(priv->port_entries, 0, sizeof(priv->port_entries));
+       memset(priv->vlan_entries, 0, sizeof(priv->vlan_entries));
+
+       /* set default vid of each vlan to the same number of vlan, so the vid
+        * won't need be set explicitly.
+        */
+       for (i = 0; i < MT7530_NUM_VLANS; i++) {
+               priv->vlan_entries[i].vid = i;
+       }
+
+       return 0;
+}
+
+static int
+mt7530_get_vlan_enable(struct switch_dev *dev,
+                          const struct switch_attr *attr,
+                          struct switch_val *val)
+{
+       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
+
+       val->value.i = priv->global_vlan_enable;
+
+       return 0;
+}
+
+static int
+mt7530_set_vlan_enable(struct switch_dev *dev,
+                          const struct switch_attr *attr,
+                          struct switch_val *val)
+{
+       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
+
+       priv->global_vlan_enable = val->value.i != 0;
+
+       return 0;
+}
+
+static u32
+mt7530_r32(struct mt7530_priv *priv, u32 reg)
+{
+       u32 val;
+       if (priv->bus) {
+               u16 high, low;
+
+               mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
+               low = mdiobus_read(priv->bus, 0x1f, (reg >> 2) & 0xf);
+               high = mdiobus_read(priv->bus, 0x1f, 0x10);
+
+               return (high << 16) | (low & 0xffff);
+       }
+
+       val = ioread32(priv->base + reg);
+       pr_debug("MT7530 MDIO Read [%04x]=%08x\n", reg, val);
+
+       return val;
+}
+
+static void
+mt7530_w32(struct mt7530_priv *priv, u32 reg, u32 val)
+{
+       if (priv->bus) {
+               mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
+               mdiobus_write(priv->bus, 0x1f, (reg >> 2) & 0xf,  val & 0xffff);
+               mdiobus_write(priv->bus, 0x1f, 0x10, val >> 16);
+               return;
+       }
+
+       pr_debug("MT7530 MDIO Write[%04x]=%08x\n", reg, val);
+       iowrite32(val, priv->base + reg);
+}
+
+static void
+mt7530_vtcr(struct mt7530_priv *priv, u32 cmd, u32 val)
+{
+       int i;
+
+       mt7530_w32(priv, REG_ESW_VLAN_VTCR, BIT(31) | (cmd << 12) | val);
+
+       for (i = 0; i < 20; i++) {
+               u32 val = mt7530_r32(priv, REG_ESW_VLAN_VTCR);
+
+               if ((val & BIT(31)) == 0)
+                       break;
+
+               udelay(1000);
+       }
+       if (i == 20)
+               printk("mt7530: vtcr timeout\n");
+}
+
+static int
+mt7530_get_port_pvid(struct switch_dev *dev, int port, int *val)
+{
+       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
+
+       if (port >= MT7530_NUM_PORTS)
+               return -EINVAL;
+
+       *val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(port));
+       *val &= 0xfff;
+
+       return 0;
+}
+
+static int
+mt7530_set_port_pvid(struct switch_dev *dev, int port, int pvid)
+{
+       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
+
+       if (port >= MT7530_NUM_PORTS)
+               return -EINVAL;
+
+       if (pvid < MT7530_MIN_VID || pvid > MT7530_MAX_VID)
+               return -EINVAL;
+
+       priv->port_entries[port].pvid = pvid;
+
+       return 0;
+}
+
+static int
+mt7530_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
+{
+       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
+       u32 member;
+       u32 etags;
+       int i;
+
+       val->len = 0;
+
+       if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS)
+               return -EINVAL;
+
+       mt7530_vtcr(priv, 0, val->port_vlan);
+
+       member = mt7530_r32(priv, REG_ESW_VLAN_VAWD1);
+       member >>= 16;
+       member &= 0xff;
+
+       etags = mt7530_r32(priv, REG_ESW_VLAN_VAWD2);
+
+       for (i = 0; i < MT7530_NUM_PORTS; i++) {
+               struct switch_port *p;
+               int etag;
+
+               if (!(member & BIT(i)))
+                       continue;
+
+               p = &val->value.ports[val->len++];
+               p->id = i;
+
+               etag = (etags >> (i * 2)) & 0x3;
+
+               if (etag == ETAG_CTRL_TAG)
+                       p->flags |= BIT(SWITCH_PORT_FLAG_TAGGED);
+               else if (etag != ETAG_CTRL_UNTAG)
+                       printk("vlan egress tag control neither untag nor tag.\n");
+       }
+
+       return 0;
+}
+
+static int
+mt7530_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
+{
+       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
+       u8 member = 0;
+       u8 etags = 0;
+       int i;
+
+       if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS ||
+                       val->len > MT7530_NUM_PORTS)
+               return -EINVAL;
+
+       for (i = 0; i < val->len; i++) {
+               struct switch_port *p = &val->value.ports[i];
+
+               if (p->id >= MT7530_NUM_PORTS)
+                       return -EINVAL;
+
+               member |= BIT(p->id);
+
+               if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED))
+                       etags |= BIT(p->id);
+       }
+       priv->vlan_entries[val->port_vlan].member = member;
+       priv->vlan_entries[val->port_vlan].etags = etags;
+
+       return 0;
+}
+
+static int
+mt7530_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
+               struct switch_val *val)
+{
+       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
+       int vlan;
+       u16 vid;
+
+       vlan = val->port_vlan;
+       vid = (u16)val->value.i;
+
+       if (vlan < 0 || vlan >= MT7530_NUM_VLANS)
+               return -EINVAL;
+
+       if (vid < MT7530_MIN_VID || vid > MT7530_MAX_VID)
+               return -EINVAL;
+
+       priv->vlan_entries[vlan].vid = vid;
+       return 0;
+}
+
+static int
+mt7621_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
+               struct switch_val *val)
+{
+       val->value.i = val->port_vlan;
+       return 0;
+}
+
+static int
+mt7530_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
+               struct switch_val *val)
+{
+       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
+       u32 vid;
+       int vlan;
+
+       vlan = val->port_vlan;
+
+       vid = mt7530_r32(priv, REG_ESW_VLAN_VTIM(vlan));
+       if (vlan & 1)
+               vid = vid >> 12;
+       vid &= 0xfff;
+
+       val->value.i = vid;
+       return 0;
+}
+
+static void
+mt7530_write_vlan_entry(struct mt7530_priv *priv, int vlan, u16 vid,
+                           u8 ports, u8 etags)
+{
+       int port;
+       u32 val;
+
+#ifndef CONFIG_SOC_MT7621
+       /* vid of vlan */
+       val = mt7530_r32(priv, REG_ESW_VLAN_VTIM(vlan));
+       if (vlan % 2 == 0) {
+               val &= 0xfff000;
+               val |= vid;
+       } else {
+               val &= 0xfff;
+               val |= (vid << 12);
+       }
+       mt7530_w32(priv, REG_ESW_VLAN_VTIM(vlan), val);
+#endif
+
+       /* vlan port membership */
+       if (ports)
+               mt7530_w32(priv, REG_ESW_VLAN_VAWD1, REG_ESW_VLAN_VAWD1_IVL_MAC |
+                       REG_ESW_VLAN_VAWD1_VTAG_EN | (ports << 16) |
+                       REG_ESW_VLAN_VAWD1_VALID);
+       else
+               mt7530_w32(priv, REG_ESW_VLAN_VAWD1, 0);
+
+       /* egress mode */
+       val = 0;
+       for (port = 0; port < MT7530_NUM_PORTS; port++) {
+               if (etags & BIT(port))
+                       val |= ETAG_CTRL_TAG << (port * 2);
+               else
+                       val |= ETAG_CTRL_UNTAG << (port * 2);
+       }
+       mt7530_w32(priv, REG_ESW_VLAN_VAWD2, val);
+
+       /* write to vlan table */
+#ifdef CONFIG_SOC_MT7621
+       mt7530_vtcr(priv, 1, vid);
+#else
+       mt7530_vtcr(priv, 1, vlan);
+#endif
+}
+
+static int
+mt7530_apply_config(struct switch_dev *dev)
+{
+       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
+       int i, j;
+       u8 tag_ports;
+       u8 untag_ports;
+
+       if (!priv->global_vlan_enable) {
+               for (i = 0; i < MT7530_NUM_PORTS; i++)
+                       mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00400000);
+
+               mt7530_w32(priv, REG_ESW_PORT_PCR(MT7530_CPU_PORT), 0x00ff0000);
+
+               for (i = 0; i < MT7530_NUM_PORTS; i++)
+                       mt7530_w32(priv, REG_ESW_PORT_PVC(i), 0x810000c0);
+
+               return 0;
+       }
+
+       /* set all ports as security mode */
+       for (i = 0; i < MT7530_NUM_PORTS; i++)
+               mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00ff0003);
+
+       /* check if a port is used in tag/untag vlan egress mode */
+       tag_ports = 0;
+       untag_ports = 0;
+
+       for (i = 0; i < MT7530_NUM_VLANS; i++) {
+               u8 member = priv->vlan_entries[i].member;
+               u8 etags = priv->vlan_entries[i].etags;
+
+               if (!member)
+                       continue;
+
+               for (j = 0; j < MT7530_NUM_PORTS; j++) {
+                       if (!(member & BIT(j)))
+                               continue;
+
+                       if (etags & BIT(j))
+                               tag_ports |= 1u << j;
+                       else
+                               untag_ports |= 1u << j;
+               }
+       }
+
+       /* set all untag-only ports as transparent and the rest as user port */
+       for (i = 0; i < MT7530_NUM_PORTS; i++) {
+               u32 pvc_mode = 0x81000000;
+
+               if (untag_ports & BIT(i) && !(tag_ports & BIT(i)))
+                       pvc_mode = 0x810000c0;
+
+               mt7530_w32(priv, REG_ESW_PORT_PVC(i), pvc_mode);
+       }
+
+       /* first clear the swtich vlan table */
+       for (i = 0; i < MT7530_NUM_VLANS; i++)
+               mt7530_write_vlan_entry(priv, i, i, 0, 0);
+
+       /* now program only vlans with members to avoid
+          clobbering remapped entries in later iterations */
+       for (i = 0; i < MT7530_NUM_VLANS; i++) {
+               u16 vid = priv->vlan_entries[i].vid;
+               u8 member = priv->vlan_entries[i].member;
+               u8 etags = priv->vlan_entries[i].etags;
+
+               if (member)
+                       mt7530_write_vlan_entry(priv, i, vid, member, etags);
+       }
+
+       /* Port Default PVID */
+       for (i = 0; i < MT7530_NUM_PORTS; i++) {
+               int vlan = priv->port_entries[i].pvid;
+               u16 pvid = 0;
+               u32 val;
+
+               if (vlan < MT7530_NUM_VLANS && priv->vlan_entries[vlan].member)
+                       pvid = priv->vlan_entries[vlan].vid;
+
+               val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(i));
+               val &= ~0xfff;
+               val |= pvid;
+               mt7530_w32(priv, REG_ESW_PORT_PPBV1(i), val);
+       }
+
+       return 0;
+}
+
+static int
+mt7530_get_port_link(struct switch_dev *dev,  int port,
+                       struct switch_port_link *link)
+{
+       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
+       u32 speed, pmsr;
+
+       if (port < 0 || port >= MT7530_NUM_PORTS)
+               return -EINVAL;
+
+       pmsr = mt7530_r32(priv, 0x3008 + (0x100 * port));
+
+       link->link = pmsr & 1;
+       link->duplex = (pmsr >> 1) & 1;
+       speed = (pmsr >> 2) & 3;
+
+       switch (speed) {
+       case 0:
+               link->speed = SWITCH_PORT_SPEED_10;
+               break;
+       case 1:
+               link->speed = SWITCH_PORT_SPEED_100;
+               break;
+       case 2:
+       case 3: /* forced gige speed can be 2 or 3 */
+               link->speed = SWITCH_PORT_SPEED_1000;
+               break;
+       default:
+               link->speed = SWITCH_PORT_SPEED_UNKNOWN;
+               break;
+       }
+
+       return 0;
+}
+
+static u64 get_mib_counter(struct mt7530_priv *priv, int i, int port)
+{
+       unsigned int port_base;
+       u64 lo;
+
+       port_base = MT7621_MIB_COUNTER_BASE +
+                   MT7621_MIB_COUNTER_PORT_OFFSET * port;
+
+       lo = mt7530_r32(priv, port_base + mt7621_mibs[i].offset);
+       if (mt7621_mibs[i].size == 2) {
+               u64 hi;
+
+               hi = mt7530_r32(priv, port_base + mt7621_mibs[i].offset + 4);
+               lo |= hi << 32;
+       }
+
+       return lo;
+}
+
+static int mt7621_sw_get_port_mib(struct switch_dev *dev,
+                                 const struct switch_attr *attr,
+                                 struct switch_val *val)
+{
+       static char buf[4096];
+       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
+       int i, len = 0;
+
+       if (val->port_vlan >= MT7530_NUM_PORTS)
+               return -EINVAL;
+
+       len += snprintf(buf + len, sizeof(buf) - len,
+                       "Port %d MIB counters\n", val->port_vlan);
+
+       for (i = 0; i < ARRAY_SIZE(mt7621_mibs); ++i) {
+               u64 counter;
+               len += snprintf(buf + len, sizeof(buf) - len,
+                               "%-11s: ", mt7621_mibs[i].name);
+               counter = get_mib_counter(priv, i, val->port_vlan);
+               len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
+                               counter);
+       }
+
+       val->value.s = buf;
+       val->len = len;
+       return 0;
+}
+
+static u64 get_mib_counter_7620(struct mt7530_priv *priv, int i)
+{
+       return mt7530_r32(priv, MT7620_MIB_COUNTER_BASE + mt7620_mibs[i].offset);
+}
+
+static u64 get_mib_counter_port_7620(struct mt7530_priv *priv, int i, int port)
+{
+       return mt7530_r32(priv,
+                       MT7620_MIB_COUNTER_BASE_PORT +
+                       (MT7620_MIB_COUNTER_PORT_OFFSET * port) +
+                       mt7620_port_mibs[i].offset);
+}
+
+static int mt7530_sw_get_mib(struct switch_dev *dev,
+                                 const struct switch_attr *attr,
+                                 struct switch_val *val)
+{
+       static char buf[4096];
+       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
+       int i, len = 0;
+
+       len += snprintf(buf + len, sizeof(buf) - len, "Switch MIB counters\n");
+
+       for (i = 0; i < ARRAY_SIZE(mt7620_mibs); ++i) {
+               u64 counter;
+               len += snprintf(buf + len, sizeof(buf) - len,
+                               "%-11s: ", mt7620_mibs[i].name);
+               counter = get_mib_counter_7620(priv, i);
+               len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
+                               counter);
+       }
+
+       val->value.s = buf;
+       val->len = len;
+       return 0;
+}
+
+static int mt7530_sw_get_port_mib(struct switch_dev *dev,
+                                 const struct switch_attr *attr,
+                                 struct switch_val *val)
+{
+       static char buf[4096];
+       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
+       int i, len = 0;
+
+       if (val->port_vlan >= MT7530_NUM_PORTS)
+               return -EINVAL;
+
+       len += snprintf(buf + len, sizeof(buf) - len,
+                       "Port %d MIB counters\n", val->port_vlan);
+
+       for (i = 0; i < ARRAY_SIZE(mt7620_port_mibs); ++i) {
+               u64 counter;
+               len += snprintf(buf + len, sizeof(buf) - len,
+                               "%-11s: ", mt7620_port_mibs[i].name);
+               counter = get_mib_counter_port_7620(priv, i, val->port_vlan);
+               len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
+                               counter);
+       }
+
+       val->value.s = buf;
+       val->len = len;
+       return 0;
+}
+
+static int mt7530_get_port_stats(struct switch_dev *dev, int port,
+                                       struct switch_port_stats *stats)
+{
+       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
+
+       if (port < 0 || port >= MT7530_NUM_PORTS)
+               return -EINVAL;
+
+       stats->tx_bytes = get_mib_counter_port_7620(priv, MT7530_PORT_MIB_TXB_ID, port);
+       stats->rx_bytes = get_mib_counter_port_7620(priv, MT7530_PORT_MIB_RXB_ID, port);
+
+       return 0;
+}
+
+static int mt7621_get_port_stats(struct switch_dev *dev, int port,
+                                       struct switch_port_stats *stats)
+{
+       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
+
+       if (port < 0 || port >= MT7530_NUM_PORTS)
+               return -EINVAL;
+
+       stats->tx_bytes = get_mib_counter(priv, MT7621_PORT_MIB_TXB_ID, port);
+       stats->rx_bytes = get_mib_counter(priv, MT7621_PORT_MIB_RXB_ID, port);
+
+       return 0;
+}
+
+static const struct switch_attr mt7530_global[] = {
+       {
+               .type = SWITCH_TYPE_INT,
+               .name = "enable_vlan",
+               .description = "VLAN mode (1:enabled)",
+               .max = 1,
+               .id = MT7530_ATTR_ENABLE_VLAN,
+               .get = mt7530_get_vlan_enable,
+               .set = mt7530_set_vlan_enable,
+       }, {
+               .type = SWITCH_TYPE_STRING,
+               .name = "mib",
+               .description = "Get MIB counters for switch",
+               .get = mt7530_sw_get_mib,
+               .set = NULL,
+       },
+};
+
+static const struct switch_attr mt7621_port[] = {
+       {
+               .type = SWITCH_TYPE_STRING,
+               .name = "mib",
+               .description = "Get MIB counters for port",
+               .get = mt7621_sw_get_port_mib,
+               .set = NULL,
+       },
+};
+
+static const struct switch_attr mt7621_vlan[] = {
+       {
+               .type = SWITCH_TYPE_INT,
+               .name = "vid",
+               .description = "VLAN ID (0-4094)",
+               .set = mt7530_set_vid,
+               .get = mt7621_get_vid,
+               .max = 4094,
+       },
+};
+
+static const struct switch_attr mt7530_port[] = {
+       {
+               .type = SWITCH_TYPE_STRING,
+               .name = "mib",
+               .description = "Get MIB counters for port",
+               .get = mt7530_sw_get_port_mib,
+               .set = NULL,
+       },
+};
+
+static const struct switch_attr mt7530_vlan[] = {
+       {
+               .type = SWITCH_TYPE_INT,
+               .name = "vid",
+               .description = "VLAN ID (0-4094)",
+               .set = mt7530_set_vid,
+               .get = mt7530_get_vid,
+               .max = 4094,
+       },
+};
+
+static const struct switch_dev_ops mt7621_ops = {
+       .attr_global = {
+               .attr = mt7530_global,
+               .n_attr = ARRAY_SIZE(mt7530_global),
+       },
+       .attr_port = {
+               .attr = mt7621_port,
+               .n_attr = ARRAY_SIZE(mt7621_port),
+       },
+       .attr_vlan = {
+               .attr = mt7621_vlan,
+               .n_attr = ARRAY_SIZE(mt7621_vlan),
+       },
+       .get_vlan_ports = mt7530_get_vlan_ports,
+       .set_vlan_ports = mt7530_set_vlan_ports,
+       .get_port_pvid = mt7530_get_port_pvid,
+       .set_port_pvid = mt7530_set_port_pvid,
+       .get_port_link = mt7530_get_port_link,
+       .get_port_stats = mt7621_get_port_stats,
+       .apply_config = mt7530_apply_config,
+       .reset_switch = mt7530_reset_switch,
+};
+
+static const struct switch_dev_ops mt7530_ops = {
+       .attr_global = {
+               .attr = mt7530_global,
+               .n_attr = ARRAY_SIZE(mt7530_global),
+       },
+       .attr_port = {
+               .attr = mt7530_port,
+               .n_attr = ARRAY_SIZE(mt7530_port),
+       },
+       .attr_vlan = {
+               .attr = mt7530_vlan,
+               .n_attr = ARRAY_SIZE(mt7530_vlan),
+       },
+       .get_vlan_ports = mt7530_get_vlan_ports,
+       .set_vlan_ports = mt7530_set_vlan_ports,
+       .get_port_pvid = mt7530_get_port_pvid,
+       .set_port_pvid = mt7530_set_port_pvid,
+       .get_port_link = mt7530_get_port_link,
+       .get_port_stats = mt7530_get_port_stats,
+       .apply_config = mt7530_apply_config,
+       .reset_switch = mt7530_reset_switch,
+};
+
+int
+mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan)
+{
+       struct switch_dev *swdev;
+       struct mt7530_priv *mt7530;
+       struct mt7530_mapping *map;
+       int ret;
+
+       mt7530 = devm_kzalloc(dev, sizeof(struct mt7530_priv), GFP_KERNEL);
+       if (!mt7530)
+               return -ENOMEM;
+
+       mt7530->base = base;
+       mt7530->bus = bus;
+       mt7530->global_vlan_enable = vlan;
+
+       swdev = &mt7530->swdev;
+       if (bus) {
+               swdev->alias = "mt7530";
+               swdev->name = "mt7530";
+       } else if (IS_ENABLED(CONFIG_SOC_MT7621)) {
+               swdev->alias = "mt7621";
+               swdev->name = "mt7621";
+       } else {
+               swdev->alias = "mt7620";
+               swdev->name = "mt7620";
+       }
+       swdev->cpu_port = MT7530_CPU_PORT;
+       swdev->ports = MT7530_NUM_PORTS;
+       swdev->vlans = MT7530_NUM_VLANS;
+       if (IS_ENABLED(CONFIG_SOC_MT7621))
+               swdev->ops = &mt7621_ops;
+       else
+               swdev->ops = &mt7530_ops;
+
+       ret = register_switch(swdev, NULL);
+       if (ret) {
+               dev_err(dev, "failed to register mt7530\n");
+               return ret;
+       }
+
+
+       map = mt7530_find_mapping(dev->of_node);
+       if (map)
+               mt7530_apply_mapping(mt7530, map);
+       mt7530_apply_config(swdev);
+
+       /* magic vodoo */
+       if (!IS_ENABLED(CONFIG_SOC_MT7621) && bus && mt7530_r32(mt7530, REG_HWTRAP) !=  0x1117edf) {
+               dev_info(dev, "fixing up MHWTRAP register - bootloader probably played with it\n");
+               mt7530_w32(mt7530, REG_HWTRAP, 0x1117edf);
+       }
+       dev_info(dev, "loaded %s driver\n", swdev->name);
+
+       return 0;
+}
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mt7530.h b/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mt7530.h
new file mode 100644 (file)
index 0000000..cf725c2
--- /dev/null
@@ -0,0 +1,186 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2016 Vitaly Chekryzhev <13hakta@gmail.com>
+ */
+
+#ifndef _MT7530_H__
+#define _MT7530_H__
+
+#define MT7620_MIB_COUNTER_BASE_PORT   0x4000
+#define MT7620_MIB_COUNTER_PORT_OFFSET 0x100
+#define MT7620_MIB_COUNTER_BASE        0x1010
+
+/* PPE Accounting Group #0 Byte Counter */
+#define MT7620_MIB_STATS_PPE_AC_BCNT0  0x000
+
+/* PPE Accounting Group #0 Packet Counter */
+#define MT7620_MIB_STATS_PPE_AC_PCNT0  0x004
+
+/* PPE Accounting Group #63 Byte Counter */
+#define MT7620_MIB_STATS_PPE_AC_BCNT63 0x1F8
+
+/* PPE Accounting Group #63 Packet Counter */
+#define MT7620_MIB_STATS_PPE_AC_PCNT63 0x1FC
+
+/* PPE Meter Group #0 */
+#define MT7620_MIB_STATS_PPE_MTR_CNT0  0x200
+
+/* PPE Meter Group #63 */
+#define MT7620_MIB_STATS_PPE_MTR_CNT63 0x2FC
+
+/* Transmit good byte count for CPU GDM */
+#define MT7620_MIB_STATS_GDM1_TX_GBCNT 0x300
+
+/* Transmit good packet count for CPU GDM (exclude flow control frames) */
+#define MT7620_MIB_STATS_GDM1_TX_GPCNT 0x304
+
+/* Transmit abort count for CPU GDM */
+#define MT7620_MIB_STATS_GDM1_TX_SKIPCNT       0x308
+
+/* Transmit collision count for CPU GDM */
+#define MT7620_MIB_STATS_GDM1_TX_COLCNT        0x30C
+
+/* Received good byte count for CPU GDM */
+#define MT7620_MIB_STATS_GDM1_RX_GBCNT1        0x320
+
+/* Received good packet count for CPU GDM (exclude flow control frame) */
+#define MT7620_MIB_STATS_GDM1_RX_GPCNT1        0x324
+
+/* Received overflow error packet count for CPU GDM */
+#define MT7620_MIB_STATS_GDM1_RX_OERCNT        0x328
+
+/* Received FCS error packet count for CPU GDM */
+#define MT7620_MIB_STATS_GDM1_RX_FERCNT        0x32C
+
+/* Received too short error packet count for CPU GDM */
+#define MT7620_MIB_STATS_GDM1_RX_SERCNT        0x330
+
+/* Received too long error packet count for CPU GDM */
+#define MT7620_MIB_STATS_GDM1_RX_LERCNT        0x334
+
+/* Received IP/TCP/UDP checksum error packet count for CPU GDM */
+#define MT7620_MIB_STATS_GDM1_RX_CERCNT        0x338
+
+/* Received flow control pkt count for CPU GDM */
+#define MT7620_MIB_STATS_GDM1_RX_FCCNT 0x33C
+
+/* Transmit good byte count for PPE GDM */
+#define MT7620_MIB_STATS_GDM2_TX_GBCNT 0x340
+
+/* Transmit good packet count for PPE GDM (exclude flow control frames) */
+#define MT7620_MIB_STATS_GDM2_TX_GPCNT 0x344
+
+/* Transmit abort count for PPE GDM */
+#define MT7620_MIB_STATS_GDM2_TX_SKIPCNT       0x348
+
+/* Transmit collision count for PPE GDM */
+#define MT7620_MIB_STATS_GDM2_TX_COLCNT        0x34C
+
+/* Received good byte count for PPE GDM */
+#define MT7620_MIB_STATS_GDM2_RX_GBCNT 0x360
+
+/* Received good packet count for PPE GDM (exclude flow control frame) */
+#define MT7620_MIB_STATS_GDM2_RX_GPCNT 0x364
+
+/* Received overflow error packet count for PPE GDM */
+#define MT7620_MIB_STATS_GDM2_RX_OERCNT        0x368
+
+/* Received FCS error packet count for PPE GDM */
+#define MT7620_MIB_STATS_GDM2_RX_FERCNT        0x36C
+
+/* Received too short error packet count for PPE GDM */
+#define MT7620_MIB_STATS_GDM2_RX_SERCNT        0x370
+
+/* Received too long error packet count for PPE GDM */
+#define MT7620_MIB_STATS_GDM2_RX_LERCNT        0x374
+
+/* Received IP/TCP/UDP checksum error packet count for PPE GDM */
+#define MT7620_MIB_STATS_GDM2_RX_CERCNT        0x378
+
+/* Received flow control pkt count for PPE GDM */
+#define MT7620_MIB_STATS_GDM2_RX_FCCNT 0x37C
+
+/* Tx Packet Counter of Port n */
+#define MT7620_MIB_STATS_PORT_TGPCN    0x10
+
+/* Tx Bad Octet Counter of Port n */
+#define MT7620_MIB_STATS_PORT_TBOCN    0x14
+
+/* Tx Good Octet Counter of Port n */
+#define MT7620_MIB_STATS_PORT_TGOCN    0x18
+
+/* Tx Event Packet Counter of Port n */
+#define MT7620_MIB_STATS_PORT_TEPCN    0x1C
+
+/* Rx Packet Counter of Port n */
+#define MT7620_MIB_STATS_PORT_RGPCN    0x20
+
+/* Rx Bad Octet Counter of Port n */
+#define MT7620_MIB_STATS_PORT_RBOCN    0x24
+
+/* Rx Good Octet Counter of Port n */
+#define MT7620_MIB_STATS_PORT_RGOCN    0x28
+
+/* Rx Event Packet Counter of Port n */
+#define MT7620_MIB_STATS_PORT_REPC1N   0x2C
+
+/* Rx Event Packet Counter of Port n */
+#define MT7620_MIB_STATS_PORT_REPC2N   0x30
+
+#define MT7621_MIB_COUNTER_BASE        0x4000
+#define MT7621_MIB_COUNTER_PORT_OFFSET 0x100
+#define MT7621_STATS_TDPC      0x00
+#define MT7621_STATS_TCRC      0x04
+#define MT7621_STATS_TUPC      0x08
+#define MT7621_STATS_TMPC      0x0C
+#define MT7621_STATS_TBPC      0x10
+#define MT7621_STATS_TCEC      0x14
+#define MT7621_STATS_TSCEC     0x18
+#define MT7621_STATS_TMCEC     0x1C
+#define MT7621_STATS_TDEC      0x20
+#define MT7621_STATS_TLCEC     0x24
+#define MT7621_STATS_TXCEC     0x28
+#define MT7621_STATS_TPPC      0x2C
+#define MT7621_STATS_TL64PC    0x30
+#define MT7621_STATS_TL65PC    0x34
+#define MT7621_STATS_TL128PC   0x38
+#define MT7621_STATS_TL256PC   0x3C
+#define MT7621_STATS_TL512PC   0x40
+#define MT7621_STATS_TL1024PC  0x44
+#define MT7621_STATS_TOC       0x48
+#define MT7621_STATS_RDPC      0x60
+#define MT7621_STATS_RFPC      0x64
+#define MT7621_STATS_RUPC      0x68
+#define MT7621_STATS_RMPC      0x6C
+#define MT7621_STATS_RBPC      0x70
+#define MT7621_STATS_RAEPC     0x74
+#define MT7621_STATS_RCEPC     0x78
+#define MT7621_STATS_RUSPC     0x7C
+#define MT7621_STATS_RFEPC     0x80
+#define MT7621_STATS_ROSPC     0x84
+#define MT7621_STATS_RJEPC     0x88
+#define MT7621_STATS_RPPC      0x8C
+#define MT7621_STATS_RL64PC    0x90
+#define MT7621_STATS_RL65PC    0x94
+#define MT7621_STATS_RL128PC   0x98
+#define MT7621_STATS_RL256PC   0x9C
+#define MT7621_STATS_RL512PC   0xA0
+#define MT7621_STATS_RL1024PC  0xA4
+#define MT7621_STATS_ROC       0xA8
+#define MT7621_STATS_RDPC_CTRL 0xB0
+#define MT7621_STATS_RDPC_ING  0xB4
+#define MT7621_STATS_RDPC_ARL  0xB8
+
+int mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan);
+
+#endif
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mtk_eth_soc.c b/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mtk_eth_soc.c
new file mode 100644 (file)
index 0000000..db7b5b2
--- /dev/null
@@ -0,0 +1,1599 @@
+/*   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; version 2 of the License
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
+ *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
+ *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/skbuff.h>
+#include <linux/etherdevice.h>
+#include <linux/ethtool.h>
+#include <linux/platform_device.h>
+#include <linux/of_device.h>
+#include <linux/clk.h>
+#include <linux/of_net.h>
+#include <linux/of_mdio.h>
+#include <linux/if_vlan.h>
+#include <linux/reset.h>
+#include <linux/tcp.h>
+#include <linux/io.h>
+#include <linux/bug.h>
+
+#include <asm/mach-ralink/ralink_regs.h>
+
+#include "mtk_eth_soc.h"
+#include "mdio.h"
+#include "ethtool.h"
+
+#define        MAX_RX_LENGTH           1536
+#define FE_RX_ETH_HLEN         (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
+#define FE_RX_HLEN             (NET_SKB_PAD + FE_RX_ETH_HLEN + NET_IP_ALIGN)
+#define DMA_DUMMY_DESC         0xffffffff
+#define FE_DEFAULT_MSG_ENABLE \
+               (NETIF_MSG_DRV | \
+               NETIF_MSG_PROBE | \
+               NETIF_MSG_LINK | \
+               NETIF_MSG_TIMER | \
+               NETIF_MSG_IFDOWN | \
+               NETIF_MSG_IFUP | \
+               NETIF_MSG_RX_ERR | \
+               NETIF_MSG_TX_ERR)
+
+#define TX_DMA_DESP2_DEF       (TX_DMA_LS0 | TX_DMA_DONE)
+#define TX_DMA_DESP4_DEF       (TX_DMA_QN(3) | TX_DMA_PN(1))
+#define NEXT_TX_DESP_IDX(X)    (((X) + 1) & (ring->tx_ring_size - 1))
+#define NEXT_RX_DESP_IDX(X)    (((X) + 1) & (ring->rx_ring_size - 1))
+
+#define SYSC_REG_RSTCTRL       0x34
+
+static int fe_msg_level = -1;
+module_param_named(msg_level, fe_msg_level, int, 0);
+MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
+
+static const u16 fe_reg_table_default[FE_REG_COUNT] = {
+       [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
+       [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
+       [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
+       [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
+       [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
+       [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
+       [FE_REG_TX_DTX_IDX0] = FE_TX_DTX_IDX0,
+       [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
+       [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
+       [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
+       [FE_REG_RX_DRX_IDX0] = FE_RX_DRX_IDX0,
+       [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
+       [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
+       [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
+       [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
+       [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
+};
+
+static const u16 *fe_reg_table = fe_reg_table_default;
+
+struct fe_work_t {
+       int bitnr;
+       void (*action)(struct fe_priv *);
+};
+
+static void __iomem *fe_base;
+
+void fe_w32(u32 val, unsigned reg)
+{
+       __raw_writel(val, fe_base + reg);
+}
+
+u32 fe_r32(unsigned reg)
+{
+       return __raw_readl(fe_base + reg);
+}
+
+void fe_reg_w32(u32 val, enum fe_reg reg)
+{
+       fe_w32(val, fe_reg_table[reg]);
+}
+
+u32 fe_reg_r32(enum fe_reg reg)
+{
+       return fe_r32(fe_reg_table[reg]);
+}
+
+void fe_reset(u32 reset_bits)
+{
+       u32 t;
+
+       t = rt_sysc_r32(SYSC_REG_RSTCTRL);
+       t |= reset_bits;
+       rt_sysc_w32(t, SYSC_REG_RSTCTRL);
+       usleep_range(10, 20);
+
+       t &= ~reset_bits;
+       rt_sysc_w32(t, SYSC_REG_RSTCTRL);
+       usleep_range(10, 20);
+}
+
+static inline void fe_int_disable(u32 mask)
+{
+       fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
+                  FE_REG_FE_INT_ENABLE);
+       /* flush write */
+       fe_reg_r32(FE_REG_FE_INT_ENABLE);
+}
+
+static inline void fe_int_enable(u32 mask)
+{
+       fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
+                  FE_REG_FE_INT_ENABLE);
+       /* flush write */
+       fe_reg_r32(FE_REG_FE_INT_ENABLE);
+}
+
+static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
+{
+       unsigned long flags;
+
+       spin_lock_irqsave(&priv->page_lock, flags);
+       fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
+       fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
+              FE_GDMA1_MAC_ADRL);
+       spin_unlock_irqrestore(&priv->page_lock, flags);
+}
+
+static int fe_set_mac_address(struct net_device *dev, void *p)
+{
+       int ret = eth_mac_addr(dev, p);
+
+       if (!ret) {
+               struct fe_priv *priv = netdev_priv(dev);
+
+               if (priv->soc->set_mac)
+                       priv->soc->set_mac(priv, dev->dev_addr);
+               else
+                       fe_hw_set_macaddr(priv, p);
+       }
+
+       return ret;
+}
+
+static inline int fe_max_frag_size(int mtu)
+{
+       /* make sure buf_size will be at least MAX_RX_LENGTH */
+       if (mtu + FE_RX_ETH_HLEN < MAX_RX_LENGTH)
+               mtu = MAX_RX_LENGTH - FE_RX_ETH_HLEN;
+
+       return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
+               SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
+}
+
+static inline int fe_max_buf_size(int frag_size)
+{
+       int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
+                      SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
+
+       BUG_ON(buf_size < MAX_RX_LENGTH);
+       return buf_size;
+}
+
+static inline void fe_get_rxd(struct fe_rx_dma *rxd, struct fe_rx_dma *dma_rxd)
+{
+       rxd->rxd1 = dma_rxd->rxd1;
+       rxd->rxd2 = dma_rxd->rxd2;
+       rxd->rxd3 = dma_rxd->rxd3;
+       rxd->rxd4 = dma_rxd->rxd4;
+}
+
+static inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
+{
+       dma_txd->txd1 = txd->txd1;
+       dma_txd->txd3 = txd->txd3;
+       dma_txd->txd4 = txd->txd4;
+       /* clean dma done flag last */
+       dma_txd->txd2 = txd->txd2;
+}
+
+static void fe_clean_rx(struct fe_priv *priv)
+{
+       int i;
+       struct fe_rx_ring *ring = &priv->rx_ring;
+
+       if (ring->rx_data) {
+               for (i = 0; i < ring->rx_ring_size; i++)
+                       if (ring->rx_data[i]) {
+                               if (ring->rx_dma && ring->rx_dma[i].rxd1)
+                                       dma_unmap_single(&priv->netdev->dev,
+                                                        ring->rx_dma[i].rxd1,
+                                                        ring->rx_buf_size,
+                                                        DMA_FROM_DEVICE);
+                               put_page(virt_to_head_page(ring->rx_data[i]));
+                       }
+
+               kfree(ring->rx_data);
+               ring->rx_data = NULL;
+       }
+
+       if (ring->rx_dma) {
+               dma_free_coherent(&priv->netdev->dev,
+                                 ring->rx_ring_size * sizeof(*ring->rx_dma),
+                                 ring->rx_dma,
+                                 ring->rx_phys);
+               ring->rx_dma = NULL;
+       }
+}
+
+static int fe_alloc_rx(struct fe_priv *priv)
+{
+       struct net_device *netdev = priv->netdev;
+       struct fe_rx_ring *ring = &priv->rx_ring;
+       int i, pad;
+
+       ring->rx_data = kcalloc(ring->rx_ring_size, sizeof(*ring->rx_data),
+                       GFP_KERNEL);
+       if (!ring->rx_data)
+               goto no_rx_mem;
+
+       for (i = 0; i < ring->rx_ring_size; i++) {
+               ring->rx_data[i] = netdev_alloc_frag(ring->frag_size);
+               if (!ring->rx_data[i])
+                       goto no_rx_mem;
+       }
+
+       ring->rx_dma = dma_alloc_coherent(&netdev->dev,
+                       ring->rx_ring_size * sizeof(*ring->rx_dma),
+                       &ring->rx_phys,
+                       GFP_ATOMIC | __GFP_ZERO);
+       if (!ring->rx_dma)
+               goto no_rx_mem;
+
+       if (priv->flags & FE_FLAG_RX_2B_OFFSET)
+               pad = 0;
+       else
+               pad = NET_IP_ALIGN;
+       for (i = 0; i < ring->rx_ring_size; i++) {
+               dma_addr_t dma_addr = dma_map_single(&netdev->dev,
+                               ring->rx_data[i] + NET_SKB_PAD + pad,
+                               ring->rx_buf_size,
+                               DMA_FROM_DEVICE);
+               if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
+                       goto no_rx_mem;
+               ring->rx_dma[i].rxd1 = (unsigned int)dma_addr;
+
+               if (priv->flags & FE_FLAG_RX_SG_DMA)
+                       ring->rx_dma[i].rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
+               else
+                       ring->rx_dma[i].rxd2 = RX_DMA_LSO;
+       }
+       ring->rx_calc_idx = ring->rx_ring_size - 1;
+       /* make sure that all changes to the dma ring are flushed before we
+        * continue
+        */
+       wmb();
+
+       fe_reg_w32(ring->rx_phys, FE_REG_RX_BASE_PTR0);
+       fe_reg_w32(ring->rx_ring_size, FE_REG_RX_MAX_CNT0);
+       fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
+       fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
+
+       return 0;
+
+no_rx_mem:
+       return -ENOMEM;
+}
+
+static void fe_txd_unmap(struct device *dev, struct fe_tx_buf *tx_buf)
+{
+       if (tx_buf->flags & FE_TX_FLAGS_SINGLE0) {
+               dma_unmap_single(dev,
+                                dma_unmap_addr(tx_buf, dma_addr0),
+                                dma_unmap_len(tx_buf, dma_len0),
+                                DMA_TO_DEVICE);
+       } else if (tx_buf->flags & FE_TX_FLAGS_PAGE0) {
+               dma_unmap_page(dev,
+                              dma_unmap_addr(tx_buf, dma_addr0),
+                              dma_unmap_len(tx_buf, dma_len0),
+                              DMA_TO_DEVICE);
+       }
+       if (tx_buf->flags & FE_TX_FLAGS_PAGE1)
+               dma_unmap_page(dev,
+                              dma_unmap_addr(tx_buf, dma_addr1),
+                              dma_unmap_len(tx_buf, dma_len1),
+                              DMA_TO_DEVICE);
+
+       tx_buf->flags = 0;
+       if (tx_buf->skb && (tx_buf->skb != (struct sk_buff *)DMA_DUMMY_DESC))
+               dev_kfree_skb_any(tx_buf->skb);
+       tx_buf->skb = NULL;
+}
+
+static void fe_clean_tx(struct fe_priv *priv)
+{
+       int i;
+       struct device *dev = &priv->netdev->dev;
+       struct fe_tx_ring *ring = &priv->tx_ring;
+
+       if (ring->tx_buf) {
+               for (i = 0; i < ring->tx_ring_size; i++)
+                       fe_txd_unmap(dev, &ring->tx_buf[i]);
+               kfree(ring->tx_buf);
+               ring->tx_buf = NULL;
+       }
+
+       if (ring->tx_dma) {
+               dma_free_coherent(dev,
+                                 ring->tx_ring_size * sizeof(*ring->tx_dma),
+                                 ring->tx_dma,
+                                 ring->tx_phys);
+               ring->tx_dma = NULL;
+       }
+
+       netdev_reset_queue(priv->netdev);
+}
+
+static int fe_alloc_tx(struct fe_priv *priv)
+{
+       int i;
+       struct fe_tx_ring *ring = &priv->tx_ring;
+
+       ring->tx_free_idx = 0;
+       ring->tx_next_idx = 0;
+       ring->tx_thresh = max((unsigned long)ring->tx_ring_size >> 2,
+                             MAX_SKB_FRAGS);
+
+       ring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf),
+                       GFP_KERNEL);
+       if (!ring->tx_buf)
+               goto no_tx_mem;
+
+       ring->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
+                       ring->tx_ring_size * sizeof(*ring->tx_dma),
+                       &ring->tx_phys,
+                       GFP_ATOMIC | __GFP_ZERO);
+       if (!ring->tx_dma)
+               goto no_tx_mem;
+
+       for (i = 0; i < ring->tx_ring_size; i++) {
+               if (priv->soc->tx_dma)
+                       priv->soc->tx_dma(&ring->tx_dma[i]);
+               ring->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
+       }
+       /* make sure that all changes to the dma ring are flushed before we
+        * continue
+        */
+       wmb();
+
+       fe_reg_w32(ring->tx_phys, FE_REG_TX_BASE_PTR0);
+       fe_reg_w32(ring->tx_ring_size, FE_REG_TX_MAX_CNT0);
+       fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
+       fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
+
+       return 0;
+
+no_tx_mem:
+       return -ENOMEM;
+}
+
+static int fe_init_dma(struct fe_priv *priv)
+{
+       int err;
+
+       err = fe_alloc_tx(priv);
+       if (err)
+               return err;
+
+       err = fe_alloc_rx(priv);
+       if (err)
+               return err;
+
+       return 0;
+}
+
+static void fe_free_dma(struct fe_priv *priv)
+{
+       fe_clean_tx(priv);
+       fe_clean_rx(priv);
+}
+
+void fe_stats_update(struct fe_priv *priv)
+{
+       struct fe_hw_stats *hwstats = priv->hw_stats;
+       unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
+       u64 stats;
+
+       u64_stats_update_begin(&hwstats->syncp);
+
+       if (IS_ENABLED(CONFIG_SOC_MT7621)) {
+               hwstats->rx_bytes                       += fe_r32(base);
+               stats                                   =  fe_r32(base + 0x04);
+               if (stats)
+                       hwstats->rx_bytes               += (stats << 32);
+               hwstats->rx_packets                     += fe_r32(base + 0x08);
+               hwstats->rx_overflow                    += fe_r32(base + 0x10);
+               hwstats->rx_fcs_errors                  += fe_r32(base + 0x14);
+               hwstats->rx_short_errors                += fe_r32(base + 0x18);
+               hwstats->rx_long_errors                 += fe_r32(base + 0x1c);
+               hwstats->rx_checksum_errors             += fe_r32(base + 0x20);
+               hwstats->rx_flow_control_packets        += fe_r32(base + 0x24);
+               hwstats->tx_skip                        += fe_r32(base + 0x28);
+               hwstats->tx_collisions                  += fe_r32(base + 0x2c);
+               hwstats->tx_bytes                       += fe_r32(base + 0x30);
+               stats                                   =  fe_r32(base + 0x34);
+               if (stats)
+                       hwstats->tx_bytes               += (stats << 32);
+               hwstats->tx_packets                     += fe_r32(base + 0x38);
+       } else {
+               hwstats->tx_bytes                       += fe_r32(base);
+               hwstats->tx_packets                     += fe_r32(base + 0x04);
+               hwstats->tx_skip                        += fe_r32(base + 0x08);
+               hwstats->tx_collisions                  += fe_r32(base + 0x0c);
+               hwstats->rx_bytes                       += fe_r32(base + 0x20);
+               hwstats->rx_packets                     += fe_r32(base + 0x24);
+               hwstats->rx_overflow                    += fe_r32(base + 0x28);
+               hwstats->rx_fcs_errors                  += fe_r32(base + 0x2c);
+               hwstats->rx_short_errors                += fe_r32(base + 0x30);
+               hwstats->rx_long_errors                 += fe_r32(base + 0x34);
+               hwstats->rx_checksum_errors             += fe_r32(base + 0x38);
+               hwstats->rx_flow_control_packets        += fe_r32(base + 0x3c);
+       }
+
+       u64_stats_update_end(&hwstats->syncp);
+}
+
+static void fe_get_stats64(struct net_device *dev,
+                               struct rtnl_link_stats64 *storage)
+{
+       struct fe_priv *priv = netdev_priv(dev);
+       struct fe_hw_stats *hwstats = priv->hw_stats;
+       unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
+       unsigned int start;
+
+       if (!base) {
+               netdev_stats_to_stats64(storage, &dev->stats);
+               return;
+       }
+
+       if (netif_running(dev) && netif_device_present(dev)) {
+               if (spin_trylock(&hwstats->stats_lock)) {
+                       fe_stats_update(priv);
+                       spin_unlock(&hwstats->stats_lock);
+               }
+       }
+
+       do {
+               start = u64_stats_fetch_begin_irq(&hwstats->syncp);
+               storage->rx_packets = hwstats->rx_packets;
+               storage->tx_packets = hwstats->tx_packets;
+               storage->rx_bytes = hwstats->rx_bytes;
+               storage->tx_bytes = hwstats->tx_bytes;
+               storage->collisions = hwstats->tx_collisions;
+               storage->rx_length_errors = hwstats->rx_short_errors +
+                       hwstats->rx_long_errors;
+               storage->rx_over_errors = hwstats->rx_overflow;
+               storage->rx_crc_errors = hwstats->rx_fcs_errors;
+               storage->rx_errors = hwstats->rx_checksum_errors;
+               storage->tx_aborted_errors = hwstats->tx_skip;
+       } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
+
+       storage->tx_errors = priv->netdev->stats.tx_errors;
+       storage->rx_dropped = priv->netdev->stats.rx_dropped;
+       storage->tx_dropped = priv->netdev->stats.tx_dropped;
+}
+
+static int fe_vlan_rx_add_vid(struct net_device *dev,
+                             __be16 proto, u16 vid)
+{
+       struct fe_priv *priv = netdev_priv(dev);
+       u32 idx = (vid & 0xf);
+       u32 vlan_cfg;
+
+       if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
+             (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
+               return 0;
+
+       if (test_bit(idx, &priv->vlan_map)) {
+               netdev_warn(dev, "disable tx vlan offload\n");
+               dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
+               netdev_update_features(dev);
+       } else {
+               vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
+                               ((idx >> 1) << 2));
+               if (idx & 0x1) {
+                       vlan_cfg &= 0xffff;
+                       vlan_cfg |= (vid << 16);
+               } else {
+                       vlan_cfg &= 0xffff0000;
+                       vlan_cfg |= vid;
+               }
+               fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
+                               ((idx >> 1) << 2));
+               set_bit(idx, &priv->vlan_map);
+       }
+
+       return 0;
+}
+
+static int fe_vlan_rx_kill_vid(struct net_device *dev,
+                              __be16 proto, u16 vid)
+{
+       struct fe_priv *priv = netdev_priv(dev);
+       u32 idx = (vid & 0xf);
+
+       if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
+             (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
+               return 0;
+
+       clear_bit(idx, &priv->vlan_map);
+
+       return 0;
+}
+
+static inline u32 fe_empty_txd(struct fe_tx_ring *ring)
+{
+       barrier();
+       return (u32)(ring->tx_ring_size -
+                       ((ring->tx_next_idx - ring->tx_free_idx) &
+                        (ring->tx_ring_size - 1)));
+}
+
+static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
+                        int tx_num, struct fe_tx_ring *ring)
+{
+       struct fe_priv *priv = netdev_priv(dev);
+       struct skb_frag_struct *frag;
+       struct fe_tx_dma txd, *ptxd;
+       struct fe_tx_buf *tx_buf;
+       dma_addr_t mapped_addr;
+       unsigned int nr_frags;
+       u32 def_txd4;
+       int i, j, k, frag_size, frag_map_size, offset;
+
+       tx_buf = &ring->tx_buf[ring->tx_next_idx];
+       memset(tx_buf, 0, sizeof(*tx_buf));
+       memset(&txd, 0, sizeof(txd));
+       nr_frags = skb_shinfo(skb)->nr_frags;
+
+       /* init tx descriptor */
+       if (priv->soc->tx_dma)
+               priv->soc->tx_dma(&txd);
+       else
+               txd.txd4 = TX_DMA_DESP4_DEF;
+       def_txd4 = txd.txd4;
+
+       /* TX Checksum offload */
+       if (skb->ip_summed == CHECKSUM_PARTIAL)
+               txd.txd4 |= TX_DMA_CHKSUM;
+
+       /* VLAN header offload */
+       if (skb_vlan_tag_present(skb)) {
+               u16 tag = skb_vlan_tag_get(skb);
+
+               if (IS_ENABLED(CONFIG_SOC_MT7621))
+                       txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | tag;
+               else
+                       txd.txd4 |= TX_DMA_INS_VLAN |
+                               ((tag >> VLAN_PRIO_SHIFT) << 4) |
+                               (tag & 0xF);
+       }
+
+       /* TSO: fill MSS info in tcp checksum field */
+       if (skb_is_gso(skb)) {
+               if (skb_cow_head(skb, 0)) {
+                       netif_warn(priv, tx_err, dev,
+                                  "GSO expand head fail.\n");
+                       goto err_out;
+               }
+               if (skb_shinfo(skb)->gso_type &
+                               (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
+                       txd.txd4 |= TX_DMA_TSO;
+                       tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
+               }
+       }
+
+       mapped_addr = dma_map_single(&dev->dev, skb->data,
+                                    skb_headlen(skb), DMA_TO_DEVICE);
+       if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
+               goto err_out;
+       txd.txd1 = mapped_addr;
+       txd.txd2 = TX_DMA_PLEN0(skb_headlen(skb));
+
+       tx_buf->flags |= FE_TX_FLAGS_SINGLE0;
+       dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
+       dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
+
+       /* TX SG offload */
+       j = ring->tx_next_idx;
+       k = 0;
+       for (i = 0; i < nr_frags; i++) {
+               offset = 0;
+               frag = &skb_shinfo(skb)->frags[i];
+               frag_size = skb_frag_size(frag);
+
+               while (frag_size > 0) {
+                       frag_map_size = min(frag_size, TX_DMA_BUF_LEN);
+                       mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
+                                                      frag_map_size,
+                                                      DMA_TO_DEVICE);
+                       if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
+                               goto err_dma;
+
+                       if (k & 0x1) {
+                               j = NEXT_TX_DESP_IDX(j);
+                               txd.txd1 = mapped_addr;
+                               txd.txd2 = TX_DMA_PLEN0(frag_map_size);
+                               txd.txd4 = def_txd4;
+
+                               tx_buf = &ring->tx_buf[j];
+                               memset(tx_buf, 0, sizeof(*tx_buf));
+
+                               tx_buf->flags |= FE_TX_FLAGS_PAGE0;
+                               dma_unmap_addr_set(tx_buf, dma_addr0,
+                                                  mapped_addr);
+                               dma_unmap_len_set(tx_buf, dma_len0,
+                                                 frag_map_size);
+                       } else {
+                               txd.txd3 = mapped_addr;
+                               txd.txd2 |= TX_DMA_PLEN1(frag_map_size);
+
+                               tx_buf->skb = (struct sk_buff *)DMA_DUMMY_DESC;
+                               tx_buf->flags |= FE_TX_FLAGS_PAGE1;
+                               dma_unmap_addr_set(tx_buf, dma_addr1,
+                                                  mapped_addr);
+                               dma_unmap_len_set(tx_buf, dma_len1,
+                                                 frag_map_size);
+
+                               if (!((i == (nr_frags - 1)) &&
+                                     (frag_map_size == frag_size))) {
+                                       fe_set_txd(&txd, &ring->tx_dma[j]);
+                                       memset(&txd, 0, sizeof(txd));
+                               }
+                       }
+                       frag_size -= frag_map_size;
+                       offset += frag_map_size;
+                       k++;
+               }
+       }
+
+       /* set last segment */
+       if (k & 0x1)
+               txd.txd2 |= TX_DMA_LS1;
+       else
+               txd.txd2 |= TX_DMA_LS0;
+       fe_set_txd(&txd, &ring->tx_dma[j]);
+
+       /* store skb to cleanup */
+       tx_buf->skb = skb;
+
+       netdev_sent_queue(dev, skb->len);
+       skb_tx_timestamp(skb);
+
+       ring->tx_next_idx = NEXT_TX_DESP_IDX(j);
+       /* make sure that all changes to the dma ring are flushed before we
+        * continue
+        */
+       wmb();
+       if (unlikely(fe_empty_txd(ring) <= ring->tx_thresh)) {
+               netif_stop_queue(dev);
+               smp_mb();
+               if (unlikely(fe_empty_txd(ring) > ring->tx_thresh))
+                       netif_wake_queue(dev);
+       }
+
+       if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
+               fe_reg_w32(ring->tx_next_idx, FE_REG_TX_CTX_IDX0);
+
+       return 0;
+
+err_dma:
+       j = ring->tx_next_idx;
+       for (i = 0; i < tx_num; i++) {
+               ptxd = &ring->tx_dma[j];
+               tx_buf = &ring->tx_buf[j];
+
+               /* unmap dma */
+               fe_txd_unmap(&dev->dev, tx_buf);
+
+               ptxd->txd2 = TX_DMA_DESP2_DEF;
+               j = NEXT_TX_DESP_IDX(j);
+       }
+       /* make sure that all changes to the dma ring are flushed before we
+        * continue
+        */
+       wmb();
+
+err_out:
+       return -1;
+}
+
+static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv)
+{
+       unsigned int len;
+       int ret;
+
+       ret = 0;
+       if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
+               if ((priv->flags & FE_FLAG_PADDING_64B) &&
+                   !(priv->flags & FE_FLAG_PADDING_BUG))
+                       return ret;
+
+               if (skb_vlan_tag_present(skb))
+                       len = ETH_ZLEN;
+               else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
+                       len = VLAN_ETH_ZLEN;
+               else if (!(priv->flags & FE_FLAG_PADDING_64B))
+                       len = ETH_ZLEN;
+               else
+                       return ret;
+
+               if (skb->len < len) {
+                       ret = skb_pad(skb, len - skb->len);
+                       if (ret < 0)
+                               return ret;
+                       skb->len = len;
+                       skb_set_tail_pointer(skb, len);
+               }
+       }
+
+       return ret;
+}
+
+static inline int fe_cal_txd_req(struct sk_buff *skb)
+{
+       int i, nfrags;
+       struct skb_frag_struct *frag;
+
+       nfrags = 1;
+       if (skb_is_gso(skb)) {
+               for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
+                       frag = &skb_shinfo(skb)->frags[i];
+                       nfrags += DIV_ROUND_UP(frag->size, TX_DMA_BUF_LEN);
+               }
+       } else {
+               nfrags += skb_shinfo(skb)->nr_frags;
+       }
+
+       return DIV_ROUND_UP(nfrags, 2);
+}
+
+static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+       struct fe_priv *priv = netdev_priv(dev);
+       struct fe_tx_ring *ring = &priv->tx_ring;
+       struct net_device_stats *stats = &dev->stats;
+       int tx_num;
+       int len = skb->len;
+
+       if (fe_skb_padto(skb, priv)) {
+               netif_warn(priv, tx_err, dev, "tx padding failed!\n");
+               return NETDEV_TX_OK;
+       }
+
+       tx_num = fe_cal_txd_req(skb);
+       if (unlikely(fe_empty_txd(ring) <= tx_num)) {
+               netif_stop_queue(dev);
+               netif_err(priv, tx_queued, dev,
+                         "Tx Ring full when queue awake!\n");
+               return NETDEV_TX_BUSY;
+       }
+
+       if (fe_tx_map_dma(skb, dev, tx_num, ring) < 0) {
+               stats->tx_dropped++;
+       } else {
+               stats->tx_packets++;
+               stats->tx_bytes += len;
+       }
+
+       return NETDEV_TX_OK;
+}
+
+static int fe_poll_rx(struct napi_struct *napi, int budget,
+                     struct fe_priv *priv, u32 rx_intr)
+{
+       struct net_device *netdev = priv->netdev;
+       struct net_device_stats *stats = &netdev->stats;
+       struct fe_soc_data *soc = priv->soc;
+       struct fe_rx_ring *ring = &priv->rx_ring;
+       int idx = ring->rx_calc_idx;
+       u32 checksum_bit;
+       struct sk_buff *skb;
+       u8 *data, *new_data;
+       struct fe_rx_dma *rxd, trxd;
+       int done = 0, pad;
+
+       if (netdev->features & NETIF_F_RXCSUM)
+               checksum_bit = soc->checksum_bit;
+       else
+               checksum_bit = 0;
+
+       if (priv->flags & FE_FLAG_RX_2B_OFFSET)
+               pad = 0;
+       else
+               pad = NET_IP_ALIGN;
+
+       while (done < budget) {
+               unsigned int pktlen;
+               dma_addr_t dma_addr;
+
+               idx = NEXT_RX_DESP_IDX(idx);
+               rxd = &ring->rx_dma[idx];
+               data = ring->rx_data[idx];
+
+               fe_get_rxd(&trxd, rxd);
+               if (!(trxd.rxd2 & RX_DMA_DONE))
+                       break;
+
+               /* alloc new buffer */
+               new_data = netdev_alloc_frag(ring->frag_size);
+               if (unlikely(!new_data)) {
+                       stats->rx_dropped++;
+                       goto release_desc;
+               }
+               dma_addr = dma_map_single(&netdev->dev,
+                                         new_data + NET_SKB_PAD + pad,
+                                         ring->rx_buf_size,
+                                         DMA_FROM_DEVICE);
+               if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
+                       put_page(virt_to_head_page(new_data));
+                       goto release_desc;
+               }
+
+               /* receive data */
+               skb = build_skb(data, ring->frag_size);
+               if (unlikely(!skb)) {
+                       put_page(virt_to_head_page(new_data));
+                       goto release_desc;
+               }
+               skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
+
+               dma_unmap_single(&netdev->dev, trxd.rxd1,
+                                ring->rx_buf_size, DMA_FROM_DEVICE);
+               pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
+               skb->dev = netdev;
+               skb_put(skb, pktlen);
+               if (trxd.rxd4 & checksum_bit)
+                       skb->ip_summed = CHECKSUM_UNNECESSARY;
+               else
+                       skb_checksum_none_assert(skb);
+               skb->protocol = eth_type_trans(skb, netdev);
+
+               stats->rx_packets++;
+               stats->rx_bytes += pktlen;
+
+               napi_gro_receive(napi, skb);
+
+               ring->rx_data[idx] = new_data;
+               rxd->rxd1 = (unsigned int)dma_addr;
+
+release_desc:
+               if (priv->flags & FE_FLAG_RX_SG_DMA)
+                       rxd->rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
+               else
+                       rxd->rxd2 = RX_DMA_LSO;
+
+               ring->rx_calc_idx = idx;
+               /* make sure that all changes to the dma ring are flushed before
+                * we continue
+                */
+               wmb();
+               fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
+               done++;
+       }
+
+       if (done < budget)
+               fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
+
+       return done;
+}
+
+static int fe_poll_tx(struct fe_priv *priv, int budget, u32 tx_intr,
+                     int *tx_again)
+{
+       struct net_device *netdev = priv->netdev;
+       struct device *dev = &netdev->dev;
+       unsigned int bytes_compl = 0;
+       struct sk_buff *skb;
+       struct fe_tx_buf *tx_buf;
+       int done = 0;
+       u32 idx, hwidx;
+       struct fe_tx_ring *ring = &priv->tx_ring;
+
+       idx = ring->tx_free_idx;
+       hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
+
+       while ((idx != hwidx) && budget) {
+               tx_buf = &ring->tx_buf[idx];
+               skb = tx_buf->skb;
+
+               if (!skb)
+                       break;
+
+               if (skb != (struct sk_buff *)DMA_DUMMY_DESC) {
+                       bytes_compl += skb->len;
+                       done++;
+                       budget--;
+               }
+               fe_txd_unmap(dev, tx_buf);
+               idx = NEXT_TX_DESP_IDX(idx);
+       }
+       ring->tx_free_idx = idx;
+
+       if (idx == hwidx) {
+               /* read hw index again make sure no new tx packet */
+               hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
+               if (idx == hwidx)
+                       fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
+               else
+                       *tx_again = 1;
+       } else {
+               *tx_again = 1;
+       }
+
+       if (done) {
+               netdev_completed_queue(netdev, done, bytes_compl);
+               smp_mb();
+               if (unlikely(netif_queue_stopped(netdev) &&
+                            (fe_empty_txd(ring) > ring->tx_thresh)))
+                       netif_wake_queue(netdev);
+       }
+
+       return done;
+}
+
+static int fe_poll(struct napi_struct *napi, int budget)
+{
+       struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
+       struct fe_hw_stats *hwstat = priv->hw_stats;
+       int tx_done, rx_done, tx_again;
+       u32 status, fe_status, status_reg, mask;
+       u32 tx_intr, rx_intr, status_intr;
+
+       status = fe_reg_r32(FE_REG_FE_INT_STATUS);
+       fe_status = status;
+       tx_intr = priv->soc->tx_int;
+       rx_intr = priv->soc->rx_int;
+       status_intr = priv->soc->status_int;
+       tx_done = 0;
+       rx_done = 0;
+       tx_again = 0;
+
+       if (fe_reg_table[FE_REG_FE_INT_STATUS2]) {
+               fe_status = fe_reg_r32(FE_REG_FE_INT_STATUS2);
+               status_reg = FE_REG_FE_INT_STATUS2;
+       } else {
+               status_reg = FE_REG_FE_INT_STATUS;
+       }
+
+       if (status & tx_intr)
+               tx_done = fe_poll_tx(priv, budget, tx_intr, &tx_again);
+
+       if (status & rx_intr)
+               rx_done = fe_poll_rx(napi, budget, priv, rx_intr);
+
+       if (unlikely(fe_status & status_intr)) {
+               if (hwstat && spin_trylock(&hwstat->stats_lock)) {
+                       fe_stats_update(priv);
+                       spin_unlock(&hwstat->stats_lock);
+               }
+               fe_reg_w32(status_intr, status_reg);
+       }
+
+       if (unlikely(netif_msg_intr(priv))) {
+               mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
+               netdev_info(priv->netdev,
+                           "done tx %d, rx %d, intr 0x%08x/0x%x\n",
+                           tx_done, rx_done, status, mask);
+       }
+
+       if (!tx_again && (rx_done < budget)) {
+               status = fe_reg_r32(FE_REG_FE_INT_STATUS);
+               if (status & (tx_intr | rx_intr)) {
+                       /* let napi poll again */
+                       rx_done = budget;
+                       goto poll_again;
+               }
+
+               napi_complete_done(napi, rx_done);
+               fe_int_enable(tx_intr | rx_intr);
+       } else {
+               rx_done = budget;
+       }
+
+poll_again:
+       return rx_done;
+}
+
+static void fe_tx_timeout(struct net_device *dev)
+{
+       struct fe_priv *priv = netdev_priv(dev);
+       struct fe_tx_ring *ring = &priv->tx_ring;
+
+       priv->netdev->stats.tx_errors++;
+       netif_err(priv, tx_err, dev,
+                 "transmit timed out\n");
+       netif_info(priv, drv, dev, "dma_cfg:%08x\n",
+                  fe_reg_r32(FE_REG_PDMA_GLO_CFG));
+       netif_info(priv, drv, dev, "tx_ring=%d, "
+                  "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n",
+                  0, fe_reg_r32(FE_REG_TX_BASE_PTR0),
+                  fe_reg_r32(FE_REG_TX_MAX_CNT0),
+                  fe_reg_r32(FE_REG_TX_CTX_IDX0),
+                  fe_reg_r32(FE_REG_TX_DTX_IDX0),
+                  ring->tx_free_idx,
+                  ring->tx_next_idx);
+       netif_info(priv, drv, dev,
+                  "rx_ring=%d, base=%08x, max=%u, calc=%u, drx=%u\n",
+                  0, fe_reg_r32(FE_REG_RX_BASE_PTR0),
+                  fe_reg_r32(FE_REG_RX_MAX_CNT0),
+                  fe_reg_r32(FE_REG_RX_CALC_IDX0),
+                  fe_reg_r32(FE_REG_RX_DRX_IDX0));
+
+       if (!test_and_set_bit(FE_FLAG_RESET_PENDING, priv->pending_flags))
+               schedule_work(&priv->pending_work);
+}
+
+static irqreturn_t fe_handle_irq(int irq, void *dev)
+{
+       struct fe_priv *priv = netdev_priv(dev);
+       u32 status, int_mask;
+
+       status = fe_reg_r32(FE_REG_FE_INT_STATUS);
+
+       if (unlikely(!status))
+               return IRQ_NONE;
+
+       int_mask = (priv->soc->rx_int | priv->soc->tx_int);
+       if (likely(status & int_mask)) {
+               if (likely(napi_schedule_prep(&priv->rx_napi))) {
+                       fe_int_disable(int_mask);
+                       __napi_schedule(&priv->rx_napi);
+               }
+       } else {
+               fe_reg_w32(status, FE_REG_FE_INT_STATUS);
+       }
+
+       return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+static void fe_poll_controller(struct net_device *dev)
+{
+       struct fe_priv *priv = netdev_priv(dev);
+       u32 int_mask = priv->soc->tx_int | priv->soc->rx_int;
+
+       fe_int_disable(int_mask);
+       fe_handle_irq(dev->irq, dev);
+       fe_int_enable(int_mask);
+}
+#endif
+
+int fe_set_clock_cycle(struct fe_priv *priv)
+{
+       unsigned long sysclk = priv->sysclk;
+
+       sysclk /= FE_US_CYC_CNT_DIVISOR;
+       sysclk <<= FE_US_CYC_CNT_SHIFT;
+
+       fe_w32((fe_r32(FE_FE_GLO_CFG) &
+                       ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
+                       sysclk,
+                       FE_FE_GLO_CFG);
+       return 0;
+}
+
+void fe_fwd_config(struct fe_priv *priv)
+{
+       u32 fwd_cfg;
+
+       fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
+
+       /* disable jumbo frame */
+       if (priv->flags & FE_FLAG_JUMBO_FRAME)
+               fwd_cfg &= ~FE_GDM1_JMB_EN;
+
+       /* set unicast/multicast/broadcast frame to cpu */
+       fwd_cfg &= ~0xffff;
+
+       fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
+}
+
+static void fe_rxcsum_config(bool enable)
+{
+       if (enable)
+               fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
+                                       FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
+                               FE_GDMA1_FWD_CFG);
+       else
+               fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
+                                       FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
+                               FE_GDMA1_FWD_CFG);
+}
+
+static void fe_txcsum_config(bool enable)
+{
+       if (enable)
+               fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
+                                       FE_TCS_GEN_EN | FE_UCS_GEN_EN),
+                               FE_CDMA_CSG_CFG);
+       else
+               fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
+                                       FE_TCS_GEN_EN | FE_UCS_GEN_EN),
+                               FE_CDMA_CSG_CFG);
+}
+
+void fe_csum_config(struct fe_priv *priv)
+{
+       struct net_device *dev = priv_netdev(priv);
+
+       fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
+       fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
+}
+
+static int fe_hw_init(struct net_device *dev)
+{
+       struct fe_priv *priv = netdev_priv(dev);
+       int i, err;
+
+       err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
+                              dev_name(priv->device), dev);
+       if (err)
+               return err;
+
+       if (priv->soc->set_mac)
+               priv->soc->set_mac(priv, dev->dev_addr);
+       else
+               fe_hw_set_macaddr(priv, dev->dev_addr);
+
+       /* disable delay interrupt */
+       fe_reg_w32(0, FE_REG_DLY_INT_CFG);
+
+       fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
+
+       /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc */
+       if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
+               for (i = 0; i < 16; i += 2)
+                       fe_w32(((i + 1) << 16) + i,
+                              fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
+                              (i * 2));
+
+       if (priv->soc->fwd_config(priv))
+               netdev_err(dev, "unable to get clock\n");
+
+       if (fe_reg_table[FE_REG_FE_RST_GL]) {
+               fe_reg_w32(1, FE_REG_FE_RST_GL);
+               fe_reg_w32(0, FE_REG_FE_RST_GL);
+       }
+
+       return 0;
+}
+
+static int fe_open(struct net_device *dev)
+{
+       struct fe_priv *priv = netdev_priv(dev);
+       unsigned long flags;
+       u32 val;
+       int err;
+
+       err = fe_init_dma(priv);
+       if (err) {
+               fe_free_dma(priv);
+               return err;
+       }
+
+       spin_lock_irqsave(&priv->page_lock, flags);
+
+       val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
+       if (priv->flags & FE_FLAG_RX_2B_OFFSET)
+               val |= FE_RX_2B_OFFSET;
+       val |= priv->soc->pdma_glo_cfg;
+       fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
+
+       spin_unlock_irqrestore(&priv->page_lock, flags);
+
+       if (priv->phy)
+               priv->phy->start(priv);
+
+       if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
+               netif_carrier_on(dev);
+
+       napi_enable(&priv->rx_napi);
+       fe_int_enable(priv->soc->tx_int | priv->soc->rx_int);
+       netif_start_queue(dev);
+
+       return 0;
+}
+
+static int fe_stop(struct net_device *dev)
+{
+       struct fe_priv *priv = netdev_priv(dev);
+       unsigned long flags;
+       int i;
+
+       netif_tx_disable(dev);
+       fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
+       napi_disable(&priv->rx_napi);
+
+       if (priv->phy)
+               priv->phy->stop(priv);
+
+       spin_lock_irqsave(&priv->page_lock, flags);
+
+       fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
+                    ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
+                    FE_REG_PDMA_GLO_CFG);
+       spin_unlock_irqrestore(&priv->page_lock, flags);
+
+       /* wait dma stop */
+       for (i = 0; i < 10; i++) {
+               if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
+                               (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
+                       msleep(20);
+                       continue;
+               }
+               break;
+       }
+
+       fe_free_dma(priv);
+
+       return 0;
+}
+
+static int __init fe_init(struct net_device *dev)
+{
+       struct fe_priv *priv = netdev_priv(dev);
+       struct device_node *port;
+       const char *mac_addr;
+       int err;
+
+       priv->soc->reset_fe();
+
+       if (priv->soc->switch_init)
+               if (priv->soc->switch_init(priv)) {
+                       netdev_err(dev, "failed to initialize switch core\n");
+                       return -ENODEV;
+               }
+
+       mac_addr = of_get_mac_address(priv->device->of_node);
+       if (mac_addr)
+               ether_addr_copy(dev->dev_addr, mac_addr);
+
+       /* If the mac address is invalid, use random mac address  */
+       if (!is_valid_ether_addr(dev->dev_addr)) {
+               random_ether_addr(dev->dev_addr);
+               dev_err(priv->device, "generated random MAC address %pM\n",
+                       dev->dev_addr);
+       }
+
+       err = fe_mdio_init(priv);
+       if (err)
+               return err;
+
+       if (priv->soc->port_init)
+               for_each_child_of_node(priv->device->of_node, port)
+                       if (of_device_is_compatible(port, "mediatek,eth-port") &&
+                           of_device_is_available(port))
+                               priv->soc->port_init(priv, port);
+
+       if (priv->phy) {
+               err = priv->phy->connect(priv);
+               if (err)
+                       goto err_phy_disconnect;
+       }
+
+       err = fe_hw_init(dev);
+       if (err)
+               goto err_phy_disconnect;
+
+       if ((priv->flags & FE_FLAG_HAS_SWITCH) && priv->soc->switch_config)
+               priv->soc->switch_config(priv);
+
+       return 0;
+
+err_phy_disconnect:
+       if (priv->phy)
+               priv->phy->disconnect(priv);
+       fe_mdio_cleanup(priv);
+
+       return err;
+}
+
+static void fe_uninit(struct net_device *dev)
+{
+       struct fe_priv *priv = netdev_priv(dev);
+
+       if (priv->phy)
+               priv->phy->disconnect(priv);
+       fe_mdio_cleanup(priv);
+
+       fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
+       free_irq(dev->irq, dev);
+}
+
+static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+{
+       struct fe_priv *priv = netdev_priv(dev);
+
+       if (!priv->phy_dev)
+               return -ENODEV;
+
+       switch (cmd) {
+       case SIOCETHTOOL:
+               return phy_ethtool_ioctl(priv->phy_dev,
+                               (void *) ifr->ifr_data);
+       case SIOCGMIIPHY:
+       case SIOCGMIIREG:
+       case SIOCSMIIREG:
+               return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
+       default:
+               break;
+       }
+
+       return -EOPNOTSUPP;
+}
+
+static int fe_change_mtu(struct net_device *dev, int new_mtu)
+{
+       struct fe_priv *priv = netdev_priv(dev);
+       int frag_size, old_mtu;
+       u32 fwd_cfg;
+
+       if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
+               return eth_change_mtu(dev, new_mtu);
+
+       if (IS_ENABLED(CONFIG_SOC_MT7621))
+               if (new_mtu > 2048)
+                       return -EINVAL;
+
+       frag_size = fe_max_frag_size(new_mtu);
+       if (new_mtu < 68 || frag_size > PAGE_SIZE)
+               return -EINVAL;
+
+       old_mtu = dev->mtu;
+       dev->mtu = new_mtu;
+
+       /* return early if the buffer sizes will not change */
+       if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
+               return 0;
+       if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
+               return 0;
+
+       if (new_mtu <= ETH_DATA_LEN)
+               priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
+       else
+               priv->rx_ring.frag_size = PAGE_SIZE;
+       priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
+
+       if (!netif_running(dev))
+               return 0;
+
+       fe_stop(dev);
+       if (!IS_ENABLED(CONFIG_SOC_MT7621)) {
+               fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
+               if (new_mtu <= ETH_DATA_LEN) {
+                       fwd_cfg &= ~FE_GDM1_JMB_EN;
+               } else {
+                       fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
+                       fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
+                       FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
+               }
+               fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
+       }
+
+       return fe_open(dev);
+}
+
+static const struct net_device_ops fe_netdev_ops = {
+       .ndo_init               = fe_init,
+       .ndo_uninit             = fe_uninit,
+       .ndo_open               = fe_open,
+       .ndo_stop               = fe_stop,
+       .ndo_start_xmit         = fe_start_xmit,
+       .ndo_set_mac_address    = fe_set_mac_address,
+       .ndo_validate_addr      = eth_validate_addr,
+       .ndo_do_ioctl           = fe_do_ioctl,
+       .ndo_change_mtu         = fe_change_mtu,
+       .ndo_tx_timeout         = fe_tx_timeout,
+       .ndo_get_stats64        = fe_get_stats64,
+       .ndo_vlan_rx_add_vid    = fe_vlan_rx_add_vid,
+       .ndo_vlan_rx_kill_vid   = fe_vlan_rx_kill_vid,
+#ifdef CONFIG_NET_POLL_CONTROLLER
+       .ndo_poll_controller    = fe_poll_controller,
+#endif
+};
+
+static void fe_reset_pending(struct fe_priv *priv)
+{
+       struct net_device *dev = priv->netdev;
+       int err;
+
+       rtnl_lock();
+       fe_stop(dev);
+
+       err = fe_open(dev);
+       if (err) {
+               netif_alert(priv, ifup, dev,
+                           "Driver up/down cycle failed, closing device.\n");
+               dev_close(dev);
+       }
+       rtnl_unlock();
+}
+
+static const struct fe_work_t fe_work[] = {
+       {FE_FLAG_RESET_PENDING, fe_reset_pending},
+};
+
+static void fe_pending_work(struct work_struct *work)
+{
+       struct fe_priv *priv = container_of(work, struct fe_priv, pending_work);
+       int i;
+       bool pending;
+
+       for (i = 0; i < ARRAY_SIZE(fe_work); i++) {
+               pending = test_and_clear_bit(fe_work[i].bitnr,
+                                            priv->pending_flags);
+               if (pending)
+                       fe_work[i].action(priv);
+       }
+}
+
+static int fe_probe(struct platform_device *pdev)
+{
+       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       const struct of_device_id *match;
+       struct fe_soc_data *soc;
+       struct net_device *netdev;
+       struct fe_priv *priv;
+       struct clk *sysclk;
+       int err, napi_weight;
+
+       device_reset(&pdev->dev);
+
+       match = of_match_device(of_fe_match, &pdev->dev);
+       soc = (struct fe_soc_data *)match->data;
+
+       if (soc->reg_table)
+               fe_reg_table = soc->reg_table;
+       else
+               soc->reg_table = fe_reg_table;
+
+       fe_base = devm_ioremap_resource(&pdev->dev, res);
+       if (!fe_base) {
+               err = -EADDRNOTAVAIL;
+               goto err_out;
+       }
+
+       netdev = alloc_etherdev(sizeof(*priv));
+       if (!netdev) {
+               dev_err(&pdev->dev, "alloc_etherdev failed\n");
+               err = -ENOMEM;
+               goto err_iounmap;
+       }
+
+       SET_NETDEV_DEV(netdev, &pdev->dev);
+       netdev->netdev_ops = &fe_netdev_ops;
+       netdev->base_addr = (unsigned long)fe_base;
+
+       netdev->irq = platform_get_irq(pdev, 0);
+       if (netdev->irq < 0) {
+               dev_err(&pdev->dev, "no IRQ resource found\n");
+               err = -ENXIO;
+               goto err_free_dev;
+       }
+
+       if (soc->init_data)
+               soc->init_data(soc, netdev);
+       netdev->vlan_features = netdev->hw_features & ~NETIF_F_HW_VLAN_CTAG_TX;
+       netdev->features |= netdev->hw_features;
+
+       /* fake rx vlan filter func. to support tx vlan offload func */
+       if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
+               netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
+
+       priv = netdev_priv(netdev);
+       spin_lock_init(&priv->page_lock);
+       if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
+               priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
+               if (!priv->hw_stats) {
+                       err = -ENOMEM;
+                       goto err_free_dev;
+               }
+               spin_lock_init(&priv->hw_stats->stats_lock);
+       }
+
+       sysclk = devm_clk_get(&pdev->dev, NULL);
+       if (!IS_ERR(sysclk)) {
+               priv->sysclk = clk_get_rate(sysclk);
+       } else if ((priv->flags & FE_FLAG_CALIBRATE_CLK)) {
+               dev_err(&pdev->dev, "this soc needs a clk for calibration\n");
+               err = -ENXIO;
+               goto err_free_dev;
+       }
+
+       priv->switch_np = of_parse_phandle(pdev->dev.of_node, "mediatek,switch", 0);
+       if ((priv->flags & FE_FLAG_HAS_SWITCH) && !priv->switch_np) {
+               dev_err(&pdev->dev, "failed to read switch phandle\n");
+               err = -ENODEV;
+               goto err_free_dev;
+       }
+
+       priv->netdev = netdev;
+       priv->device = &pdev->dev;
+       priv->soc = soc;
+       priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
+       priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
+       priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
+       priv->tx_ring.tx_ring_size = NUM_DMA_DESC;
+       priv->rx_ring.rx_ring_size = NUM_DMA_DESC;
+       INIT_WORK(&priv->pending_work, fe_pending_work);
+
+       napi_weight = 16;
+       if (priv->flags & FE_FLAG_NAPI_WEIGHT) {
+               napi_weight *= 4;
+               priv->tx_ring.tx_ring_size *= 4;
+               priv->rx_ring.rx_ring_size *= 4;
+       }
+       netif_napi_add(netdev, &priv->rx_napi, fe_poll, napi_weight);
+       fe_set_ethtool_ops(netdev);
+
+       err = register_netdev(netdev);
+       if (err) {
+               dev_err(&pdev->dev, "error bringing up device\n");
+               goto err_free_dev;
+       }
+
+       platform_set_drvdata(pdev, netdev);
+
+       netif_info(priv, probe, netdev, "mediatek frame engine at 0x%08lx, irq %d\n",
+                  netdev->base_addr, netdev->irq);
+
+       return 0;
+
+err_free_dev:
+       free_netdev(netdev);
+err_iounmap:
+       devm_iounmap(&pdev->dev, fe_base);
+err_out:
+       return err;
+}
+
+static int fe_remove(struct platform_device *pdev)
+{
+       struct net_device *dev = platform_get_drvdata(pdev);
+       struct fe_priv *priv = netdev_priv(dev);
+
+       netif_napi_del(&priv->rx_napi);
+       kfree(priv->hw_stats);
+
+       cancel_work_sync(&priv->pending_work);
+
+       unregister_netdev(dev);
+       free_netdev(dev);
+       platform_set_drvdata(pdev, NULL);
+
+       return 0;
+}
+
+static struct platform_driver fe_driver = {
+       .probe = fe_probe,
+       .remove = fe_remove,
+       .driver = {
+               .name = "mtk_soc_eth",
+               .owner = THIS_MODULE,
+               .of_match_table = of_fe_match,
+       },
+};
+
+module_platform_driver(fe_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
+MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
+MODULE_VERSION(MTK_FE_DRV_VERSION);
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mtk_eth_soc.h b/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mtk_eth_soc.h
new file mode 100644 (file)
index 0000000..6a946c7
--- /dev/null
@@ -0,0 +1,523 @@
+/*   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; version 2 of the License
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
+ *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
+ *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
+ */
+
+#ifndef FE_ETH_H
+#define FE_ETH_H
+
+#include <linux/mii.h>
+#include <linux/interrupt.h>
+#include <linux/netdevice.h>
+#include <linux/dma-mapping.h>
+#include <linux/phy.h>
+#include <linux/ethtool.h>
+#include <linux/version.h>
+
+enum fe_reg {
+       FE_REG_PDMA_GLO_CFG = 0,
+       FE_REG_PDMA_RST_CFG,
+       FE_REG_DLY_INT_CFG,
+       FE_REG_TX_BASE_PTR0,
+       FE_REG_TX_MAX_CNT0,
+       FE_REG_TX_CTX_IDX0,
+       FE_REG_TX_DTX_IDX0,
+       FE_REG_RX_BASE_PTR0,
+       FE_REG_RX_MAX_CNT0,
+       FE_REG_RX_CALC_IDX0,
+       FE_REG_RX_DRX_IDX0,
+       FE_REG_FE_INT_ENABLE,
+       FE_REG_FE_INT_STATUS,
+       FE_REG_FE_DMA_VID_BASE,
+       FE_REG_FE_COUNTER_BASE,
+       FE_REG_FE_RST_GL,
+       FE_REG_FE_INT_STATUS2,
+       FE_REG_COUNT
+};
+
+enum fe_work_flag {
+       FE_FLAG_RESET_PENDING,
+       FE_FLAG_MAX
+};
+
+#define MTK_FE_DRV_VERSION             "0.1.2"
+
+/* power of 2 to let NEXT_TX_DESP_IDX work */
+#define NUM_DMA_DESC           BIT(10)
+#define MAX_DMA_DESC           0xfff
+
+#define FE_DELAY_EN_INT                0x80
+#define FE_DELAY_MAX_INT       0x04
+#define FE_DELAY_MAX_TOUT      0x04
+#define FE_DELAY_TIME          20
+#define FE_DELAY_CHAN          (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | \
+                                FE_DELAY_MAX_TOUT)
+#define FE_DELAY_INIT          ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
+#define FE_PSE_FQFC_CFG_INIT   0x80504000
+#define FE_PSE_FQFC_CFG_256Q   0xff908000
+
+/* interrupt bits */
+#define FE_CNT_PPE_AF          BIT(31)
+#define FE_CNT_GDM_AF          BIT(29)
+#define FE_PSE_P2_FC           BIT(26)
+#define FE_PSE_BUF_DROP                BIT(24)
+#define FE_GDM_OTHER_DROP      BIT(23)
+#define FE_PSE_P1_FC           BIT(22)
+#define FE_PSE_P0_FC           BIT(21)
+#define FE_PSE_FQ_EMPTY                BIT(20)
+#define FE_GE1_STA_CHG         BIT(18)
+#define FE_TX_COHERENT         BIT(17)
+#define FE_RX_COHERENT         BIT(16)
+#define FE_TX_DONE_INT3                BIT(11)
+#define FE_TX_DONE_INT2                BIT(10)
+#define FE_TX_DONE_INT1                BIT(9)
+#define FE_TX_DONE_INT0                BIT(8)
+#define FE_RX_DONE_INT0                BIT(2)
+#define FE_TX_DLY_INT          BIT(1)
+#define FE_RX_DLY_INT          BIT(0)
+
+#define FE_RX_DONE_INT         FE_RX_DONE_INT0
+#define FE_TX_DONE_INT         (FE_TX_DONE_INT0 | FE_TX_DONE_INT1 | \
+                                FE_TX_DONE_INT2 | FE_TX_DONE_INT3)
+
+#define RT5350_RX_DLY_INT      BIT(30)
+#define RT5350_TX_DLY_INT      BIT(28)
+#define RT5350_RX_DONE_INT1    BIT(17)
+#define RT5350_RX_DONE_INT0    BIT(16)
+#define RT5350_TX_DONE_INT3    BIT(3)
+#define RT5350_TX_DONE_INT2    BIT(2)
+#define RT5350_TX_DONE_INT1    BIT(1)
+#define RT5350_TX_DONE_INT0    BIT(0)
+
+#define RT5350_RX_DONE_INT     (RT5350_RX_DONE_INT0 | RT5350_RX_DONE_INT1)
+#define RT5350_TX_DONE_INT     (RT5350_TX_DONE_INT0 | RT5350_TX_DONE_INT1 | \
+                                RT5350_TX_DONE_INT2 | RT5350_TX_DONE_INT3)
+
+/* registers */
+#define FE_FE_OFFSET           0x0000
+#define FE_GDMA_OFFSET         0x0020
+#define FE_PSE_OFFSET          0x0040
+#define FE_GDMA2_OFFSET                0x0060
+#define FE_CDMA_OFFSET         0x0080
+#define FE_DMA_VID0            0x00a8
+#define FE_PDMA_OFFSET         0x0100
+#define FE_PPE_OFFSET          0x0200
+#define FE_CMTABLE_OFFSET      0x0400
+#define FE_POLICYTABLE_OFFSET  0x1000
+
+#define RT5350_PDMA_OFFSET     0x0800
+#define RT5350_SDM_OFFSET      0x0c00
+
+#define FE_MDIO_ACCESS         (FE_FE_OFFSET + 0x00)
+#define FE_MDIO_CFG            (FE_FE_OFFSET + 0x04)
+#define FE_FE_GLO_CFG          (FE_FE_OFFSET + 0x08)
+#define FE_FE_RST_GL           (FE_FE_OFFSET + 0x0C)
+#define FE_FE_INT_STATUS       (FE_FE_OFFSET + 0x10)
+#define FE_FE_INT_ENABLE       (FE_FE_OFFSET + 0x14)
+#define FE_MDIO_CFG2           (FE_FE_OFFSET + 0x18)
+#define FE_FOC_TS_T            (FE_FE_OFFSET + 0x1C)
+
+#define        FE_GDMA1_FWD_CFG        (FE_GDMA_OFFSET + 0x00)
+#define FE_GDMA1_SCH_CFG       (FE_GDMA_OFFSET + 0x04)
+#define FE_GDMA1_SHPR_CFG      (FE_GDMA_OFFSET + 0x08)
+#define FE_GDMA1_MAC_ADRL      (FE_GDMA_OFFSET + 0x0C)
+#define FE_GDMA1_MAC_ADRH      (FE_GDMA_OFFSET + 0x10)
+
+#define        FE_GDMA2_FWD_CFG        (FE_GDMA2_OFFSET + 0x00)
+#define FE_GDMA2_SCH_CFG       (FE_GDMA2_OFFSET + 0x04)
+#define FE_GDMA2_SHPR_CFG      (FE_GDMA2_OFFSET + 0x08)
+#define FE_GDMA2_MAC_ADRL      (FE_GDMA2_OFFSET + 0x0C)
+#define FE_GDMA2_MAC_ADRH      (FE_GDMA2_OFFSET + 0x10)
+
+#define FE_PSE_FQ_CFG          (FE_PSE_OFFSET + 0x00)
+#define FE_CDMA_FC_CFG         (FE_PSE_OFFSET + 0x04)
+#define FE_GDMA1_FC_CFG                (FE_PSE_OFFSET + 0x08)
+#define FE_GDMA2_FC_CFG                (FE_PSE_OFFSET + 0x0C)
+
+#define FE_CDMA_CSG_CFG                (FE_CDMA_OFFSET + 0x00)
+#define FE_CDMA_SCH_CFG                (FE_CDMA_OFFSET + 0x04)
+
+#ifdef CONFIG_SOC_MT7621
+#define MT7620A_GDMA_OFFSET            0x0500
+#else
+#define MT7620A_GDMA_OFFSET            0x0600
+#endif
+#define        MT7620A_GDMA1_FWD_CFG           (MT7620A_GDMA_OFFSET + 0x00)
+#define MT7620A_FE_GDMA1_SCH_CFG       (MT7620A_GDMA_OFFSET + 0x04)
+#define MT7620A_FE_GDMA1_SHPR_CFG      (MT7620A_GDMA_OFFSET + 0x08)
+#define MT7620A_FE_GDMA1_MAC_ADRL      (MT7620A_GDMA_OFFSET + 0x0C)
+#define MT7620A_FE_GDMA1_MAC_ADRH      (MT7620A_GDMA_OFFSET + 0x10)
+
+#define RT5350_TX_BASE_PTR0    (RT5350_PDMA_OFFSET + 0x00)
+#define RT5350_TX_MAX_CNT0     (RT5350_PDMA_OFFSET + 0x04)
+#define RT5350_TX_CTX_IDX0     (RT5350_PDMA_OFFSET + 0x08)
+#define RT5350_TX_DTX_IDX0     (RT5350_PDMA_OFFSET + 0x0C)
+#define RT5350_TX_BASE_PTR1    (RT5350_PDMA_OFFSET + 0x10)
+#define RT5350_TX_MAX_CNT1     (RT5350_PDMA_OFFSET + 0x14)
+#define RT5350_TX_CTX_IDX1     (RT5350_PDMA_OFFSET + 0x18)
+#define RT5350_TX_DTX_IDX1     (RT5350_PDMA_OFFSET + 0x1C)
+#define RT5350_TX_BASE_PTR2    (RT5350_PDMA_OFFSET + 0x20)
+#define RT5350_TX_MAX_CNT2     (RT5350_PDMA_OFFSET + 0x24)
+#define RT5350_TX_CTX_IDX2     (RT5350_PDMA_OFFSET + 0x28)
+#define RT5350_TX_DTX_IDX2     (RT5350_PDMA_OFFSET + 0x2C)
+#define RT5350_TX_BASE_PTR3    (RT5350_PDMA_OFFSET + 0x30)
+#define RT5350_TX_MAX_CNT3     (RT5350_PDMA_OFFSET + 0x34)
+#define RT5350_TX_CTX_IDX3     (RT5350_PDMA_OFFSET + 0x38)
+#define RT5350_TX_DTX_IDX3     (RT5350_PDMA_OFFSET + 0x3C)
+#define RT5350_RX_BASE_PTR0    (RT5350_PDMA_OFFSET + 0x100)
+#define RT5350_RX_MAX_CNT0     (RT5350_PDMA_OFFSET + 0x104)
+#define RT5350_RX_CALC_IDX0    (RT5350_PDMA_OFFSET + 0x108)
+#define RT5350_RX_DRX_IDX0     (RT5350_PDMA_OFFSET + 0x10C)
+#define RT5350_RX_BASE_PTR1    (RT5350_PDMA_OFFSET + 0x110)
+#define RT5350_RX_MAX_CNT1     (RT5350_PDMA_OFFSET + 0x114)
+#define RT5350_RX_CALC_IDX1    (RT5350_PDMA_OFFSET + 0x118)
+#define RT5350_RX_DRX_IDX1     (RT5350_PDMA_OFFSET + 0x11C)
+#define RT5350_PDMA_GLO_CFG    (RT5350_PDMA_OFFSET + 0x204)
+#define RT5350_PDMA_RST_CFG    (RT5350_PDMA_OFFSET + 0x208)
+#define RT5350_DLY_INT_CFG     (RT5350_PDMA_OFFSET + 0x20c)
+#define RT5350_FE_INT_STATUS   (RT5350_PDMA_OFFSET + 0x220)
+#define RT5350_FE_INT_ENABLE   (RT5350_PDMA_OFFSET + 0x228)
+#define RT5350_PDMA_SCH_CFG    (RT5350_PDMA_OFFSET + 0x280)
+
+#define FE_PDMA_GLO_CFG                (FE_PDMA_OFFSET + 0x00)
+#define FE_PDMA_RST_CFG                (FE_PDMA_OFFSET + 0x04)
+#define FE_PDMA_SCH_CFG                (FE_PDMA_OFFSET + 0x08)
+#define FE_DLY_INT_CFG         (FE_PDMA_OFFSET + 0x0C)
+#define FE_TX_BASE_PTR0                (FE_PDMA_OFFSET + 0x10)
+#define FE_TX_MAX_CNT0         (FE_PDMA_OFFSET + 0x14)
+#define FE_TX_CTX_IDX0         (FE_PDMA_OFFSET + 0x18)
+#define FE_TX_DTX_IDX0         (FE_PDMA_OFFSET + 0x1C)
+#define FE_TX_BASE_PTR1                (FE_PDMA_OFFSET + 0x20)
+#define FE_TX_MAX_CNT1         (FE_PDMA_OFFSET + 0x24)
+#define FE_TX_CTX_IDX1         (FE_PDMA_OFFSET + 0x28)
+#define FE_TX_DTX_IDX1         (FE_PDMA_OFFSET + 0x2C)
+#define FE_RX_BASE_PTR0                (FE_PDMA_OFFSET + 0x30)
+#define FE_RX_MAX_CNT0         (FE_PDMA_OFFSET + 0x34)
+#define FE_RX_CALC_IDX0                (FE_PDMA_OFFSET + 0x38)
+#define FE_RX_DRX_IDX0         (FE_PDMA_OFFSET + 0x3C)
+#define FE_TX_BASE_PTR2                (FE_PDMA_OFFSET + 0x40)
+#define FE_TX_MAX_CNT2         (FE_PDMA_OFFSET + 0x44)
+#define FE_TX_CTX_IDX2         (FE_PDMA_OFFSET + 0x48)
+#define FE_TX_DTX_IDX2         (FE_PDMA_OFFSET + 0x4C)
+#define FE_TX_BASE_PTR3                (FE_PDMA_OFFSET + 0x50)
+#define FE_TX_MAX_CNT3         (FE_PDMA_OFFSET + 0x54)
+#define FE_TX_CTX_IDX3         (FE_PDMA_OFFSET + 0x58)
+#define FE_TX_DTX_IDX3         (FE_PDMA_OFFSET + 0x5C)
+#define FE_RX_BASE_PTR1                (FE_PDMA_OFFSET + 0x60)
+#define FE_RX_MAX_CNT1         (FE_PDMA_OFFSET + 0x64)
+#define FE_RX_CALC_IDX1                (FE_PDMA_OFFSET + 0x68)
+#define FE_RX_DRX_IDX1         (FE_PDMA_OFFSET + 0x6C)
+
+/* Switch DMA configuration */
+#define RT5350_SDM_CFG         (RT5350_SDM_OFFSET + 0x00)
+#define RT5350_SDM_RRING       (RT5350_SDM_OFFSET + 0x04)
+#define RT5350_SDM_TRING       (RT5350_SDM_OFFSET + 0x08)
+#define RT5350_SDM_MAC_ADRL    (RT5350_SDM_OFFSET + 0x0C)
+#define RT5350_SDM_MAC_ADRH    (RT5350_SDM_OFFSET + 0x10)
+#define RT5350_SDM_TPCNT       (RT5350_SDM_OFFSET + 0x100)
+#define RT5350_SDM_TBCNT       (RT5350_SDM_OFFSET + 0x104)
+#define RT5350_SDM_RPCNT       (RT5350_SDM_OFFSET + 0x108)
+#define RT5350_SDM_RBCNT       (RT5350_SDM_OFFSET + 0x10C)
+#define RT5350_SDM_CS_ERR      (RT5350_SDM_OFFSET + 0x110)
+
+#define RT5350_SDM_ICS_EN      BIT(16)
+#define RT5350_SDM_TCS_EN      BIT(17)
+#define RT5350_SDM_UCS_EN      BIT(18)
+
+/* MDIO_CFG register bits */
+#define FE_MDIO_CFG_AUTO_POLL_EN       BIT(29)
+#define FE_MDIO_CFG_GP1_BP_EN          BIT(16)
+#define FE_MDIO_CFG_GP1_FRC_EN         BIT(15)
+#define FE_MDIO_CFG_GP1_SPEED_10       (0 << 13)
+#define FE_MDIO_CFG_GP1_SPEED_100      (1 << 13)
+#define FE_MDIO_CFG_GP1_SPEED_1000     (2 << 13)
+#define FE_MDIO_CFG_GP1_DUPLEX         BIT(12)
+#define FE_MDIO_CFG_GP1_FC_TX          BIT(11)
+#define FE_MDIO_CFG_GP1_FC_RX          BIT(10)
+#define FE_MDIO_CFG_GP1_LNK_DWN                BIT(9)
+#define FE_MDIO_CFG_GP1_AN_FAIL                BIT(8)
+#define FE_MDIO_CFG_MDC_CLK_DIV_1      (0 << 6)
+#define FE_MDIO_CFG_MDC_CLK_DIV_2      (1 << 6)
+#define FE_MDIO_CFG_MDC_CLK_DIV_4      (2 << 6)
+#define FE_MDIO_CFG_MDC_CLK_DIV_8      (3 << 6)
+#define FE_MDIO_CFG_TURBO_MII_FREQ     BIT(5)
+#define FE_MDIO_CFG_TURBO_MII_MODE     BIT(4)
+#define FE_MDIO_CFG_RX_CLK_SKEW_0      (0 << 2)
+#define FE_MDIO_CFG_RX_CLK_SKEW_200    (1 << 2)
+#define FE_MDIO_CFG_RX_CLK_SKEW_400    (2 << 2)
+#define FE_MDIO_CFG_RX_CLK_SKEW_INV    (3 << 2)
+#define FE_MDIO_CFG_TX_CLK_SKEW_0      0
+#define FE_MDIO_CFG_TX_CLK_SKEW_200    1
+#define FE_MDIO_CFG_TX_CLK_SKEW_400    2
+#define FE_MDIO_CFG_TX_CLK_SKEW_INV    3
+
+/* uni-cast port */
+#define FE_GDM1_JMB_LEN_MASK   0xf
+#define FE_GDM1_JMB_LEN_SHIFT  28
+#define FE_GDM1_ICS_EN         BIT(22)
+#define FE_GDM1_TCS_EN         BIT(21)
+#define FE_GDM1_UCS_EN         BIT(20)
+#define FE_GDM1_JMB_EN         BIT(19)
+#define FE_GDM1_STRPCRC                BIT(16)
+#define FE_GDM1_UFRC_P_CPU     (0 << 12)
+#define FE_GDM1_UFRC_P_GDMA1   (1 << 12)
+#define FE_GDM1_UFRC_P_PPE     (6 << 12)
+
+/* checksums */
+#define FE_ICS_GEN_EN          BIT(2)
+#define FE_UCS_GEN_EN          BIT(1)
+#define FE_TCS_GEN_EN          BIT(0)
+
+/* dma ring */
+#define FE_PST_DRX_IDX0                BIT(16)
+#define FE_PST_DTX_IDX3                BIT(3)
+#define FE_PST_DTX_IDX2                BIT(2)
+#define FE_PST_DTX_IDX1                BIT(1)
+#define FE_PST_DTX_IDX0                BIT(0)
+
+#define FE_RX_2B_OFFSET                BIT(31)
+#define FE_TX_WB_DDONE         BIT(6)
+#define FE_RX_DMA_BUSY         BIT(3)
+#define FE_TX_DMA_BUSY         BIT(1)
+#define FE_RX_DMA_EN           BIT(2)
+#define FE_TX_DMA_EN           BIT(0)
+
+#define FE_PDMA_SIZE_4DWORDS   (0 << 4)
+#define FE_PDMA_SIZE_8DWORDS   (1 << 4)
+#define FE_PDMA_SIZE_16DWORDS  (2 << 4)
+
+#define FE_US_CYC_CNT_MASK     0xff
+#define FE_US_CYC_CNT_SHIFT    0x8
+#define FE_US_CYC_CNT_DIVISOR  1000000
+
+/* rxd2 */
+#define RX_DMA_DONE            BIT(31)
+#define RX_DMA_LSO             BIT(30)
+#define RX_DMA_PLEN0(_x)       (((_x) & 0x3fff) << 16)
+#define RX_DMA_GET_PLEN0(_x)   (((_x) >> 16) & 0x3fff)
+#define RX_DMA_TAG             BIT(15)
+/* rxd3 */
+#define RX_DMA_TPID(_x)                (((_x) >> 16) & 0xffff)
+#define RX_DMA_VID(_x)         ((_x) & 0xffff)
+/* rxd4 */
+#define RX_DMA_L4VALID         BIT(30)
+
+struct fe_rx_dma {
+       unsigned int rxd1;
+       unsigned int rxd2;
+       unsigned int rxd3;
+       unsigned int rxd4;
+} __packed __aligned(4);
+
+#define TX_DMA_BUF_LEN         0x3fff
+#define TX_DMA_PLEN0_MASK      (TX_DMA_BUF_LEN << 16)
+#define TX_DMA_PLEN0(_x)       (((_x) & TX_DMA_BUF_LEN) << 16)
+#define TX_DMA_PLEN1(_x)       ((_x) & TX_DMA_BUF_LEN)
+#define TX_DMA_GET_PLEN0(_x)    (((_x) >> 16) & TX_DMA_BUF_LEN)
+#define TX_DMA_GET_PLEN1(_x)    ((_x) & TX_DMA_BUF_LEN)
+#define TX_DMA_LS1             BIT(14)
+#define TX_DMA_LS0             BIT(30)
+#define TX_DMA_DONE            BIT(31)
+
+#define TX_DMA_INS_VLAN_MT7621 BIT(16)
+#define TX_DMA_INS_VLAN                BIT(7)
+#define TX_DMA_INS_PPPOE       BIT(12)
+#define TX_DMA_QN(_x)          ((_x) << 16)
+#define TX_DMA_PN(_x)          ((_x) << 24)
+#define TX_DMA_QN_MASK         TX_DMA_QN(0x7)
+#define TX_DMA_PN_MASK         TX_DMA_PN(0x7)
+#define TX_DMA_UDF             BIT(20)
+#define TX_DMA_CHKSUM          (0x7 << 29)
+#define TX_DMA_TSO             BIT(28)
+
+/* frame engine counters */
+#define FE_PPE_AC_BCNT0                (FE_CMTABLE_OFFSET + 0x00)
+#define FE_GDMA1_TX_GBCNT      (FE_CMTABLE_OFFSET + 0x300)
+#define FE_GDMA2_TX_GBCNT      (FE_GDMA1_TX_GBCNT + 0x40)
+
+/* phy device flags */
+#define FE_PHY_FLAG_PORT       BIT(0)
+#define FE_PHY_FLAG_ATTACH     BIT(1)
+
+struct fe_tx_dma {
+       unsigned int txd1;
+       unsigned int txd2;
+       unsigned int txd3;
+       unsigned int txd4;
+} __packed __aligned(4);
+
+struct fe_priv;
+
+struct fe_phy {
+       /* make sure that phy operations are atomic */
+       spinlock_t              lock;
+
+       struct phy_device       *phy[8];
+       struct device_node      *phy_node[8];
+       const __be32            *phy_fixed[8];
+       int                     duplex[8];
+       int                     speed[8];
+       int                     tx_fc[8];
+       int                     rx_fc[8];
+       int (*connect)(struct fe_priv *priv);
+       void (*disconnect)(struct fe_priv *priv);
+       void (*start)(struct fe_priv *priv);
+       void (*stop)(struct fe_priv *priv);
+};
+
+struct fe_soc_data {
+       const u16 *reg_table;
+
+       void (*init_data)(struct fe_soc_data *data, struct net_device *netdev);
+       void (*reset_fe)(void);
+       void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
+       int (*fwd_config)(struct fe_priv *priv);
+       void (*tx_dma)(struct fe_tx_dma *txd);
+       int (*switch_init)(struct fe_priv *priv);
+       int (*switch_config)(struct fe_priv *priv);
+       void (*port_init)(struct fe_priv *priv, struct device_node *port);
+       int (*has_carrier)(struct fe_priv *priv);
+       int (*mdio_init)(struct fe_priv *priv);
+       void (*mdio_cleanup)(struct fe_priv *priv);
+       int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg,
+                         u16 val);
+       int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
+       void (*mdio_adjust_link)(struct fe_priv *priv, int port);
+
+       void *swpriv;
+       u32 pdma_glo_cfg;
+       u32 rx_int;
+       u32 tx_int;
+       u32 status_int;
+       u32 checksum_bit;
+};
+
+#define FE_FLAG_PADDING_64B            BIT(0)
+#define FE_FLAG_PADDING_BUG            BIT(1)
+#define FE_FLAG_JUMBO_FRAME            BIT(2)
+#define FE_FLAG_RX_2B_OFFSET           BIT(3)
+#define FE_FLAG_RX_SG_DMA              BIT(4)
+#define FE_FLAG_RX_VLAN_CTAG           BIT(5)
+#define FE_FLAG_NAPI_WEIGHT            BIT(6)
+#define FE_FLAG_CALIBRATE_CLK          BIT(7)
+#define FE_FLAG_HAS_SWITCH             BIT(8)
+
+#define FE_STAT_REG_DECLARE            \
+       _FE(tx_bytes)                   \
+       _FE(tx_packets)                 \
+       _FE(tx_skip)                    \
+       _FE(tx_collisions)              \
+       _FE(rx_bytes)                   \
+       _FE(rx_packets)                 \
+       _FE(rx_overflow)                \
+       _FE(rx_fcs_errors)              \
+       _FE(rx_short_errors)            \
+       _FE(rx_long_errors)             \
+       _FE(rx_checksum_errors)         \
+       _FE(rx_flow_control_packets)
+
+struct fe_hw_stats {
+       /* make sure that stats operations are atomic */
+       spinlock_t stats_lock;
+
+       struct u64_stats_sync syncp;
+#define _FE(x) u64 x;
+       FE_STAT_REG_DECLARE
+#undef _FE
+};
+
+enum fe_tx_flags {
+       FE_TX_FLAGS_SINGLE0     = 0x01,
+       FE_TX_FLAGS_PAGE0       = 0x02,
+       FE_TX_FLAGS_PAGE1       = 0x04,
+};
+
+struct fe_tx_buf {
+       struct sk_buff *skb;
+       u32 flags;
+       DEFINE_DMA_UNMAP_ADDR(dma_addr0);
+       DEFINE_DMA_UNMAP_LEN(dma_len0);
+       DEFINE_DMA_UNMAP_ADDR(dma_addr1);
+       DEFINE_DMA_UNMAP_LEN(dma_len1);
+};
+
+struct fe_tx_ring {
+       struct fe_tx_dma *tx_dma;
+       struct fe_tx_buf *tx_buf;
+       dma_addr_t tx_phys;
+       u16 tx_ring_size;
+       u16 tx_free_idx;
+       u16 tx_next_idx;
+       u16 tx_thresh;
+};
+
+struct fe_rx_ring {
+       struct fe_rx_dma *rx_dma;
+       u8 **rx_data;
+       dma_addr_t rx_phys;
+       u16 rx_ring_size;
+       u16 frag_size;
+       u16 rx_buf_size;
+       u16 rx_calc_idx;
+};
+
+struct fe_priv {
+       /* make sure that register operations are atomic */
+       spinlock_t                      page_lock;
+
+       struct fe_soc_data              *soc;
+       struct net_device               *netdev;
+       struct device_node              *switch_np;
+       u32                             msg_enable;
+       u32                             flags;
+
+       struct device                   *device;
+       unsigned long                   sysclk;
+
+       struct fe_rx_ring               rx_ring;
+       struct napi_struct              rx_napi;
+
+       struct fe_tx_ring               tx_ring;
+
+       struct fe_phy                   *phy;
+       struct mii_bus                  *mii_bus;
+       struct phy_device               *phy_dev;
+       u32                             phy_flags;
+
+       int                             link[8];
+
+       struct fe_hw_stats              *hw_stats;
+       unsigned long                   vlan_map;
+       struct work_struct              pending_work;
+       DECLARE_BITMAP(pending_flags, FE_FLAG_MAX);
+};
+
+extern const struct of_device_id of_fe_match[];
+
+void fe_w32(u32 val, unsigned reg);
+u32 fe_r32(unsigned reg);
+
+int fe_set_clock_cycle(struct fe_priv *priv);
+void fe_csum_config(struct fe_priv *priv);
+void fe_stats_update(struct fe_priv *priv);
+void fe_fwd_config(struct fe_priv *priv);
+void fe_reg_w32(u32 val, enum fe_reg reg);
+u32 fe_reg_r32(enum fe_reg reg);
+
+void fe_reset(u32 reset_bits);
+
+static inline void *priv_netdev(struct fe_priv *priv)
+{
+       return (char *)priv - ALIGN(sizeof(struct net_device), NETDEV_ALIGN);
+}
+
+#endif /* FE_ETH_H */
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/soc_mt7620.c b/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/soc_mt7620.c
new file mode 100644 (file)
index 0000000..40bbec4
--- /dev/null
@@ -0,0 +1,335 @@
+/*   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; version 2 of the License
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
+ *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
+ *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/if_vlan.h>
+#include <linux/of_net.h>
+
+#include <asm/mach-ralink/ralink_regs.h>
+
+#include <mt7620.h>
+#include "mtk_eth_soc.h"
+#include "gsw_mt7620.h"
+#include "mt7530.h"
+#include "mdio.h"
+
+#define MT7620A_CDMA_CSG_CFG   0x400
+#define MT7620_DMA_VID         (MT7620A_CDMA_CSG_CFG | 0x30)
+#define MT7621_CDMP_IG_CTRL    (MT7620A_CDMA_CSG_CFG + 0x00)
+#define MT7621_CDMP_EG_CTRL    (MT7620A_CDMA_CSG_CFG + 0x04)
+#define MT7620A_RESET_FE       BIT(21)
+#define MT7621_RESET_FE                BIT(6)
+#define MT7620A_RESET_ESW      BIT(23)
+#define MT7620_L4_VALID                BIT(23)
+#define MT7621_L4_VALID                BIT(24)
+
+#define MT7620_TX_DMA_UDF      BIT(15)
+#define MT7621_TX_DMA_UDF      BIT(19)
+#define TX_DMA_FP_BMAP         ((0xff) << 19)
+
+#define CDMA_ICS_EN            BIT(2)
+#define CDMA_UCS_EN            BIT(1)
+#define CDMA_TCS_EN            BIT(0)
+
+#define GDMA_ICS_EN            BIT(22)
+#define GDMA_TCS_EN            BIT(21)
+#define GDMA_UCS_EN            BIT(20)
+
+/* frame engine counters */
+#define MT7620_REG_MIB_OFFSET  0x1000
+#define MT7620_PPE_AC_BCNT0    (MT7620_REG_MIB_OFFSET + 0x00)
+#define MT7620_GDM1_TX_GBCNT   (MT7620_REG_MIB_OFFSET + 0x300)
+#define MT7620_GDM2_TX_GBCNT   (MT7620_GDM1_TX_GBCNT + 0x40)
+
+#define MT7621_REG_MIB_OFFSET  0x2000
+#define MT7621_PPE_AC_BCNT0    (MT7621_REG_MIB_OFFSET + 0x00)
+#define MT7621_GDM1_TX_GBCNT   (MT7621_REG_MIB_OFFSET + 0x400)
+#define MT7621_GDM2_TX_GBCNT   (MT7621_GDM1_TX_GBCNT + 0x40)
+
+#define GSW_REG_GDMA1_MAC_ADRL 0x508
+#define GSW_REG_GDMA1_MAC_ADRH 0x50C
+
+#define MT7621_FE_RST_GL       (FE_FE_OFFSET + 0x04)
+#define MT7620_FE_INT_STATUS2  (FE_FE_OFFSET + 0x08)
+
+/* FE_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29)
+ * but after test it should be BIT(13).
+ */
+#define MT7620_FE_GDM1_AF      BIT(13)
+#define MT7621_FE_GDM1_AF      BIT(28)
+#define MT7621_FE_GDM2_AF      BIT(29)
+
+static const u16 mt7620_reg_table[FE_REG_COUNT] = {
+       [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
+       [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
+       [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
+       [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
+       [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
+       [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
+       [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
+       [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
+       [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
+       [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
+       [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
+       [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
+       [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
+       [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
+       [FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,
+       [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
+       [FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2,
+};
+
+static int mt7620_gsw_config(struct fe_priv *priv)
+{
+       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
+
+       /* is the mt7530 internal or external */
+       if (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, 0x1f)) {
+               mt7530_probe(priv->device, gsw->base, NULL, 0);
+               mt7530_probe(priv->device, NULL, priv->mii_bus, 1);
+       } else {
+               mt7530_probe(priv->device, gsw->base, NULL, 1);
+       }
+
+       return 0;
+}
+
+static void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
+{
+       struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
+       unsigned long flags;
+
+       spin_lock_irqsave(&priv->page_lock, flags);
+       mtk_switch_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
+       mtk_switch_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
+               GSW_REG_SMACCR0);
+       spin_unlock_irqrestore(&priv->page_lock, flags);
+}
+
+static void mt7620_auto_poll(struct mt7620_gsw *gsw)
+{
+       int phy;
+       int lsb = -1, msb = 0;
+
+       for_each_set_bit(phy, &gsw->autopoll, 32) {
+               if (lsb < 0)
+                       lsb = phy;
+               msb = phy;
+       }
+
+       if (lsb == msb)
+               lsb--;
+
+       mtk_switch_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) |
+               (msb << 8) | lsb, ESW_PHY_POLLING);
+}
+
+static void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
+{
+       struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
+       const __be32 *_id = of_get_property(np, "reg", NULL);
+       int phy_mode, size, id;
+       int shift = 12;
+       u32 val, mask = 0;
+       int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
+
+       if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
+               if (_id)
+                       pr_err("%s: invalid port id %d\n", np->name,
+                              be32_to_cpu(*_id));
+               else
+                       pr_err("%s: invalid port id\n", np->name);
+               return;
+       }
+
+       id = be32_to_cpu(*_id);
+
+       if (id == 4)
+               shift = 14;
+
+       priv->phy->phy_fixed[id] = of_get_property(np, "mediatek,fixed-link",
+                                                  &size);
+       if (priv->phy->phy_fixed[id] &&
+           (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
+               pr_err("%s: invalid fixed link property\n", np->name);
+               priv->phy->phy_fixed[id] = NULL;
+               return;
+       }
+
+       phy_mode = of_get_phy_mode(np);
+       switch (phy_mode) {
+       case PHY_INTERFACE_MODE_RGMII:
+               mask = 0;
+               break;
+       case PHY_INTERFACE_MODE_MII:
+               mask = 1;
+               break;
+       case PHY_INTERFACE_MODE_RMII:
+               mask = 2;
+               break;
+       default:
+               dev_err(priv->device, "port %d - invalid phy mode\n", id);
+               return;
+       }
+
+       priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
+       if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
+               return;
+
+       val = rt_sysc_r32(SYSC_REG_CFG1);
+       val &= ~(3 << shift);
+       val |= mask << shift;
+       rt_sysc_w32(val, SYSC_REG_CFG1);
+
+       if (priv->phy->phy_fixed[id]) {
+               const __be32 *link = priv->phy->phy_fixed[id];
+               int tx_fc, rx_fc;
+               u32 val = 0;
+
+               priv->phy->speed[id] = be32_to_cpup(link++);
+               tx_fc = be32_to_cpup(link++);
+               rx_fc = be32_to_cpup(link++);
+               priv->phy->duplex[id] = be32_to_cpup(link++);
+               priv->link[id] = 1;
+
+               switch (priv->phy->speed[id]) {
+               case SPEED_10:
+                       val = 0;
+                       break;
+               case SPEED_100:
+                       val = 1;
+                       break;
+               case SPEED_1000:
+                       val = 2;
+                       break;
+               default:
+                       dev_err(priv->device, "invalid link speed: %d\n",
+                               priv->phy->speed[id]);
+                       priv->phy->phy_fixed[id] = 0;
+                       return;
+               }
+               val = PMCR_SPEED(val);
+               val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
+                       PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
+               if (tx_fc)
+                       val |= PMCR_TX_FC;
+               if (rx_fc)
+                       val |= PMCR_RX_FC;
+               if (priv->phy->duplex[id])
+                       val |= PMCR_DUPLEX;
+               mtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));
+               dev_info(priv->device, "using fixed link parameters\n");
+               return;
+       }
+
+       if (priv->phy->phy_node[id] && mdiobus_get_phy(priv->mii_bus, id)) {
+               u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
+                       PMCR_TX_EN |  PMCR_MAC_MODE | PMCR_IPG;
+
+               mtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));
+               fe_connect_phy_node(priv, priv->phy->phy_node[id]);
+               gsw->autopoll |= BIT(id);
+               mt7620_auto_poll(gsw);
+               return;
+       }
+}
+
+static void mt7620_fe_reset(void)
+{
+       fe_reset(MT7620A_RESET_FE | MT7620A_RESET_ESW);
+}
+
+static void mt7620_rxcsum_config(bool enable)
+{
+       if (enable)
+               fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
+                                       GDMA_TCS_EN | GDMA_UCS_EN),
+                               MT7620A_GDMA1_FWD_CFG);
+       else
+               fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
+                                       GDMA_TCS_EN | GDMA_UCS_EN),
+                               MT7620A_GDMA1_FWD_CFG);
+}
+
+static void mt7620_txcsum_config(bool enable)
+{
+       if (enable)
+               fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN |
+                                       CDMA_UCS_EN | CDMA_TCS_EN),
+                               MT7620A_CDMA_CSG_CFG);
+       else
+               fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) & ~(CDMA_ICS_EN |
+                                       CDMA_UCS_EN | CDMA_TCS_EN),
+                               MT7620A_CDMA_CSG_CFG);
+}
+
+static int mt7620_fwd_config(struct fe_priv *priv)
+{
+       struct net_device *dev = priv_netdev(priv);
+
+       fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
+
+       mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
+       mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
+
+       return 0;
+}
+
+static void mt7620_tx_dma(struct fe_tx_dma *txd)
+{
+}
+
+static void mt7620_init_data(struct fe_soc_data *data,
+                            struct net_device *netdev)
+{
+       struct fe_priv *priv = netdev_priv(netdev);
+
+       priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
+               FE_FLAG_RX_SG_DMA | FE_FLAG_HAS_SWITCH;
+
+       netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
+               NETIF_F_HW_VLAN_CTAG_TX;
+       if (mt7620_get_eco() >= 5)
+               netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
+                       NETIF_F_IPV6_CSUM;
+}
+
+static struct fe_soc_data mt7620_data = {
+       .init_data = mt7620_init_data,
+       .reset_fe = mt7620_fe_reset,
+       .set_mac = mt7620_set_mac,
+       .fwd_config = mt7620_fwd_config,
+       .tx_dma = mt7620_tx_dma,
+       .switch_init = mtk_gsw_init,
+       .switch_config = mt7620_gsw_config,
+       .port_init = mt7620_port_init,
+       .reg_table = mt7620_reg_table,
+       .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
+       .rx_int = RT5350_RX_DONE_INT,
+       .tx_int = RT5350_TX_DONE_INT,
+       .status_int = MT7620_FE_GDM1_AF,
+       .checksum_bit = MT7620_L4_VALID,
+       .has_carrier = mt7620_has_carrier,
+       .mdio_read = mt7620_mdio_read,
+       .mdio_write = mt7620_mdio_write,
+       .mdio_adjust_link = mt7620_mdio_link_adjust,
+};
+
+const struct of_device_id of_fe_match[] = {
+       { .compatible = "mediatek,mt7620-eth", .data = &mt7620_data },
+       {},
+};
+
+MODULE_DEVICE_TABLE(of, of_fe_match);
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/soc_mt7621.c b/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/soc_mt7621.c
new file mode 100644 (file)
index 0000000..ce41b34
--- /dev/null
@@ -0,0 +1,185 @@
+/*   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; version 2 of the License
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
+ *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
+ *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/if_vlan.h>
+#include <linux/of_net.h>
+
+#include <asm/mach-ralink/ralink_regs.h>
+
+#include "mtk_eth_soc.h"
+#include "gsw_mt7620.h"
+#include "mt7530.h"
+#include "mdio.h"
+
+#define MT7620A_CDMA_CSG_CFG   0x400
+#define MT7621_CDMP_IG_CTRL    (MT7620A_CDMA_CSG_CFG + 0x00)
+#define MT7621_CDMP_EG_CTRL    (MT7620A_CDMA_CSG_CFG + 0x04)
+#define MT7621_RESET_FE                BIT(6)
+#define MT7621_L4_VALID                BIT(24)
+
+#define MT7621_TX_DMA_UDF      BIT(19)
+#define MT7621_TX_DMA_FPORT    BIT(25)
+
+#define CDMA_ICS_EN            BIT(2)
+#define CDMA_UCS_EN            BIT(1)
+#define CDMA_TCS_EN            BIT(0)
+
+#define GDMA_ICS_EN            BIT(22)
+#define GDMA_TCS_EN            BIT(21)
+#define GDMA_UCS_EN            BIT(20)
+
+/* frame engine counters */
+#define MT7621_REG_MIB_OFFSET  0x2000
+#define MT7621_PPE_AC_BCNT0    (MT7621_REG_MIB_OFFSET + 0x00)
+#define MT7621_GDM1_TX_GBCNT   (MT7621_REG_MIB_OFFSET + 0x400)
+#define MT7621_GDM2_TX_GBCNT   (MT7621_GDM1_TX_GBCNT + 0x40)
+
+#define GSW_REG_GDMA1_MAC_ADRL 0x508
+#define GSW_REG_GDMA1_MAC_ADRH 0x50C
+
+#define MT7621_FE_RST_GL       (FE_FE_OFFSET + 0x04)
+#define MT7620_FE_INT_STATUS2  (FE_FE_OFFSET + 0x08)
+
+/* FE_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29)
+ * but after test it should be BIT(13).
+ */
+#define MT7620_FE_GDM1_AF      BIT(13)
+#define MT7621_FE_GDM1_AF      BIT(28)
+#define MT7621_FE_GDM2_AF      BIT(29)
+
+static const u16 mt7621_reg_table[FE_REG_COUNT] = {
+       [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
+       [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
+       [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
+       [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
+       [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
+       [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
+       [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
+       [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
+       [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
+       [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
+       [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
+       [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
+       [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
+       [FE_REG_FE_DMA_VID_BASE] = 0,
+       [FE_REG_FE_COUNTER_BASE] = MT7621_GDM1_TX_GBCNT,
+       [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
+       [FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2,
+};
+
+static int mt7621_gsw_config(struct fe_priv *priv)
+{
+       if (priv->mii_bus &&  mdiobus_get_phy(priv->mii_bus, 0x1f))
+               mt7530_probe(priv->device, NULL, priv->mii_bus, 1);
+
+       return 0;
+}
+
+static void mt7621_fe_reset(void)
+{
+       fe_reset(MT7621_RESET_FE);
+}
+
+static void mt7621_rxcsum_config(bool enable)
+{
+       if (enable)
+               fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
+                                       GDMA_TCS_EN | GDMA_UCS_EN),
+                               MT7620A_GDMA1_FWD_CFG);
+       else
+               fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
+                                       GDMA_TCS_EN | GDMA_UCS_EN),
+                               MT7620A_GDMA1_FWD_CFG);
+}
+
+static void mt7621_rxvlan_config(bool enable)
+{
+       if (enable)
+               fe_w32(1, MT7621_CDMP_EG_CTRL);
+       else
+               fe_w32(0, MT7621_CDMP_EG_CTRL);
+}
+
+static int mt7621_fwd_config(struct fe_priv *priv)
+{
+       struct net_device *dev = priv_netdev(priv);
+
+       fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~0xffff,
+              MT7620A_GDMA1_FWD_CFG);
+
+       /* mt7621 doesn't have txcsum config */
+       mt7621_rxcsum_config((dev->features & NETIF_F_RXCSUM));
+       mt7621_rxvlan_config(priv->flags & FE_FLAG_RX_VLAN_CTAG);
+
+       return 0;
+}
+
+static void mt7621_tx_dma(struct fe_tx_dma *txd)
+{
+       txd->txd4 = MT7621_TX_DMA_FPORT;
+}
+
+static void mt7621_init_data(struct fe_soc_data *data,
+                            struct net_device *netdev)
+{
+       struct fe_priv *priv = netdev_priv(netdev);
+
+       priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
+               FE_FLAG_RX_SG_DMA | FE_FLAG_NAPI_WEIGHT |
+               FE_FLAG_HAS_SWITCH | FE_FLAG_JUMBO_FRAME;
+
+       netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
+               NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_SG | NETIF_F_TSO |
+               NETIF_F_TSO6 | NETIF_F_IPV6_CSUM;
+}
+
+static void mt7621_set_mac(struct fe_priv *priv, unsigned char *mac)
+{
+       unsigned long flags;
+
+       spin_lock_irqsave(&priv->page_lock, flags);
+       fe_w32((mac[0] << 8) | mac[1], GSW_REG_GDMA1_MAC_ADRH);
+       fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
+              GSW_REG_GDMA1_MAC_ADRL);
+       spin_unlock_irqrestore(&priv->page_lock, flags);
+}
+
+static struct fe_soc_data mt7621_data = {
+       .init_data = mt7621_init_data,
+       .reset_fe = mt7621_fe_reset,
+       .set_mac = mt7621_set_mac,
+       .fwd_config = mt7621_fwd_config,
+       .tx_dma = mt7621_tx_dma,
+       .switch_init = mtk_gsw_init,
+       .switch_config = mt7621_gsw_config,
+       .reg_table = mt7621_reg_table,
+       .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
+       .rx_int = RT5350_RX_DONE_INT,
+       .tx_int = RT5350_TX_DONE_INT,
+       .status_int = (MT7621_FE_GDM1_AF | MT7621_FE_GDM2_AF),
+       .checksum_bit = MT7621_L4_VALID,
+       .has_carrier = mt7620_has_carrier,
+       .mdio_read = mt7620_mdio_read,
+       .mdio_write = mt7620_mdio_write,
+       .mdio_adjust_link = mt7620_mdio_link_adjust,
+};
+
+const struct of_device_id of_fe_match[] = {
+       { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data },
+       {},
+};
+
+MODULE_DEVICE_TABLE(of, of_fe_match);
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/soc_rt2880.c b/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/soc_rt2880.c
new file mode 100644 (file)
index 0000000..6c89c99
--- /dev/null
@@ -0,0 +1,76 @@
+/*   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; version 2 of the License
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
+ *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
+ *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+
+#include <asm/mach-ralink/ralink_regs.h>
+
+#include "mtk_eth_soc.h"
+#include "mdio_rt2880.h"
+
+#define RT2880_RESET_FE                        BIT(18)
+
+static void rt2880_init_data(struct fe_soc_data *data,
+                            struct net_device *netdev)
+{
+       struct fe_priv *priv = netdev_priv(netdev);
+
+       priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
+               FE_FLAG_JUMBO_FRAME | FE_FLAG_CALIBRATE_CLK;
+       netdev->hw_features = NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_TX;
+       /* this should work according to the datasheet but actually does not*/
+       /* netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM; */
+}
+
+void rt2880_fe_reset(void)
+{
+       fe_reset(RT2880_RESET_FE);
+}
+
+static int rt2880_fwd_config(struct fe_priv *priv)
+{
+       int ret;
+
+       ret = fe_set_clock_cycle(priv);
+       if (ret)
+               return ret;
+
+       fe_fwd_config(priv);
+       fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
+       fe_csum_config(priv);
+
+       return ret;
+}
+
+struct fe_soc_data rt2880_data = {
+       .init_data = rt2880_init_data,
+       .reset_fe = rt2880_fe_reset,
+       .fwd_config = rt2880_fwd_config,
+       .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
+       .checksum_bit = RX_DMA_L4VALID,
+       .rx_int = FE_RX_DONE_INT,
+       .tx_int = FE_TX_DONE_INT,
+       .status_int = FE_CNT_GDM_AF,
+       .mdio_read = rt2880_mdio_read,
+       .mdio_write = rt2880_mdio_write,
+       .mdio_adjust_link = rt2880_mdio_link_adjust,
+       .port_init = rt2880_port_init,
+};
+
+const struct of_device_id of_fe_match[] = {
+       { .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
+       {},
+};
+
+MODULE_DEVICE_TABLE(of, of_fe_match);
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/soc_rt3050.c b/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/soc_rt3050.c
new file mode 100644 (file)
index 0000000..914b814
--- /dev/null
@@ -0,0 +1,158 @@
+/*   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; version 2 of the License
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
+ *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
+ *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+
+#include <asm/mach-ralink/ralink_regs.h>
+
+#include "mtk_eth_soc.h"
+#include "mdio_rt2880.h"
+
+#define RT305X_RESET_FE         BIT(21)
+#define RT305X_RESET_ESW        BIT(23)
+
+static const u16 rt5350_reg_table[FE_REG_COUNT] = {
+       [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
+       [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
+       [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
+       [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
+       [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
+       [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
+       [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
+       [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
+       [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
+       [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
+       [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
+       [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
+       [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
+       [FE_REG_FE_RST_GL] = 0,
+       [FE_REG_FE_DMA_VID_BASE] = 0,
+};
+
+static void rt305x_init_data(struct fe_soc_data *data,
+                            struct net_device *netdev)
+{
+       struct fe_priv *priv = netdev_priv(netdev);
+
+       priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
+               FE_FLAG_CALIBRATE_CLK | FE_FLAG_HAS_SWITCH;
+       netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
+               NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX;
+}
+
+static int rt3050_fwd_config(struct fe_priv *priv)
+{
+       int ret;
+
+       if (ralink_soc != RT305X_SOC_RT3052) {
+               ret = fe_set_clock_cycle(priv);
+               if (ret)
+                       return ret;
+       }
+
+       fe_fwd_config(priv);
+       if (ralink_soc != RT305X_SOC_RT3352)
+               fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
+       fe_csum_config(priv);
+
+       return 0;
+}
+
+static void rt305x_fe_reset(void)
+{
+       fe_reset(RT305X_RESET_FE);
+}
+
+static void rt5350_init_data(struct fe_soc_data *data,
+                            struct net_device *netdev)
+{
+       struct fe_priv *priv = netdev_priv(netdev);
+
+       priv->flags = FE_FLAG_HAS_SWITCH;
+       netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM;
+}
+
+static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac)
+{
+       unsigned long flags;
+
+       spin_lock_irqsave(&priv->page_lock, flags);
+       fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
+       fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
+              RT5350_SDM_MAC_ADRL);
+       spin_unlock_irqrestore(&priv->page_lock, flags);
+}
+
+static void rt5350_rxcsum_config(bool enable)
+{
+       if (enable)
+               fe_w32(fe_r32(RT5350_SDM_CFG) | (RT5350_SDM_ICS_EN |
+                               RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN),
+                               RT5350_SDM_CFG);
+       else
+               fe_w32(fe_r32(RT5350_SDM_CFG) & ~(RT5350_SDM_ICS_EN |
+                               RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN),
+                               RT5350_SDM_CFG);
+}
+
+static int rt5350_fwd_config(struct fe_priv *priv)
+{
+       struct net_device *dev = priv_netdev(priv);
+
+       rt5350_rxcsum_config((dev->features & NETIF_F_RXCSUM));
+
+       return 0;
+}
+
+static void rt5350_tx_dma(struct fe_tx_dma *txd)
+{
+       txd->txd4 = 0;
+}
+
+static void rt5350_fe_reset(void)
+{
+       fe_reset(RT305X_RESET_FE | RT305X_RESET_ESW);
+}
+
+static struct fe_soc_data rt3050_data = {
+       .init_data = rt305x_init_data,
+       .reset_fe = rt305x_fe_reset,
+       .fwd_config = rt3050_fwd_config,
+       .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
+       .checksum_bit = RX_DMA_L4VALID,
+       .rx_int = FE_RX_DONE_INT,
+       .tx_int = FE_TX_DONE_INT,
+       .status_int = FE_CNT_GDM_AF,
+};
+
+static struct fe_soc_data rt5350_data = {
+       .init_data = rt5350_init_data,
+       .reg_table = rt5350_reg_table,
+       .reset_fe = rt5350_fe_reset,
+       .set_mac = rt5350_set_mac,
+       .fwd_config = rt5350_fwd_config,
+       .tx_dma = rt5350_tx_dma,
+       .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
+       .checksum_bit = RX_DMA_L4VALID,
+       .rx_int = RT5350_RX_DONE_INT,
+       .tx_int = RT5350_TX_DONE_INT,
+};
+
+const struct of_device_id of_fe_match[] = {
+       { .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
+       { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
+       {},
+};
+
+MODULE_DEVICE_TABLE(of, of_fe_match);
diff --git a/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/soc_rt3883.c b/target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/soc_rt3883.c
new file mode 100644 (file)
index 0000000..4935b7f
--- /dev/null
@@ -0,0 +1,75 @@
+/*   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; version 2 of the License
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
+ *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
+ *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+
+#include <asm/mach-ralink/ralink_regs.h>
+
+#include "mtk_eth_soc.h"
+#include "mdio_rt2880.h"
+
+#define RT3883_RSTCTRL_FE              BIT(21)
+
+static void rt3883_fe_reset(void)
+{
+       fe_reset(RT3883_RSTCTRL_FE);
+}
+
+static int rt3883_fwd_config(struct fe_priv *priv)
+{
+       int ret;
+
+       ret = fe_set_clock_cycle(priv);
+       if (ret)
+               return ret;
+
+       fe_fwd_config(priv);
+       fe_w32(FE_PSE_FQFC_CFG_256Q, FE_PSE_FQ_CFG);
+       fe_csum_config(priv);
+
+       return ret;
+}
+
+static void rt3883_init_data(struct fe_soc_data *data,
+                            struct net_device *netdev)
+{
+       struct fe_priv *priv = netdev_priv(netdev);
+
+       priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
+               FE_FLAG_JUMBO_FRAME | FE_FLAG_CALIBRATE_CLK;
+       netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
+               NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX;
+}
+
+static struct fe_soc_data rt3883_data = {
+       .init_data = rt3883_init_data,
+       .reset_fe = rt3883_fe_reset,
+       .fwd_config = rt3883_fwd_config,
+       .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
+       .rx_int = FE_RX_DONE_INT,
+       .tx_int = FE_TX_DONE_INT,
+       .status_int = FE_CNT_GDM_AF,
+       .checksum_bit = RX_DMA_L4VALID,
+       .mdio_read = rt2880_mdio_read,
+       .mdio_write = rt2880_mdio_write,
+       .mdio_adjust_link = rt2880_mdio_link_adjust,
+       .port_init = rt2880_port_init,
+};
+
+const struct of_device_id of_fe_match[] = {
+       { .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
+       {},
+};
+
+MODULE_DEVICE_TABLE(of, of_fe_match);
diff --git a/target/linux/ramips/mt7620/config-4.14 b/target/linux/ramips/mt7620/config-4.14
new file mode 100644 (file)
index 0000000..4926324
--- /dev/null
@@ -0,0 +1,240 @@
+CONFIG_ARCH_BINFMT_ELF_STATE=y
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+# CONFIG_ARCH_HAS_SG_CHAIN is not set
+# CONFIG_ARCH_HAS_STRICT_KERNEL_RWX is not set
+# CONFIG_ARCH_HAS_STRICT_MODULE_RWX is not set
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set
+# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
+CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
+# CONFIG_ARCH_WANTS_THP_SWAP is not set
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_AT803X_PHY=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CEVT_R4K=y
+CONFIG_CEVT_SYSTICK_QUIRK=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKEVT_RT3352=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_R4K_FPU=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_PINCTRL=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_DMA_NOOP_OPS is not set
+# CONFIG_DMA_VIRT_OPS is not set
+# CONFIG_DRM_LIB_RANDOM is not set
+# CONFIG_DTB_MT7620A_EVAL is not set
+# CONFIG_DTB_OMEGA2P is not set
+CONFIG_DTB_RT_NONE=y
+# CONFIG_DTB_VOCORE2 is not set
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_EXPORTFS=y
+CONFIG_FIXED_PHY=y
+CONFIG_FUTEX_PI=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB=y
+# CONFIG_GPIO_MT7621 is not set
+CONFIG_GPIO_RALINK=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_GRO_CELLS is not set
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+# CONFIG_HAVE_ARCH_BITREVERSE is not set
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_CBPF_JIT=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_COPY_THREAD_TLS=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_KVM=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_INTC=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LIBFDT=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+# CONFIG_MIPS_ELF_APPENDED_DTB is not set
+# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MACHINE is not set
+CONFIG_MIPS_NO_APPENDED_DTB=y
+# CONFIG_MIPS_RAW_APPENDED_DTB is not set
+CONFIG_MIPS_SPRAM=y
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MT7621_WDT is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT=16384
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_SEAMA_FW=y
+CONFIG_MTD_SPLIT_TPLINK_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_MEDIATEK_GSW_MT7620=y
+CONFIG_NET_MEDIATEK_MDIO=y
+CONFIG_NET_MEDIATEK_MDIO_MT7620=y
+CONFIG_NET_MEDIATEK_MT7620=y
+# CONFIG_NET_MEDIATEK_RT3050 is not set
+CONFIG_NET_MEDIATEK_SOC=y
+CONFIG_NET_VENDOR_MEDIATEK=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+# CONFIG_NO_IOPORT_MAP is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHY_RALINK_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_RT2880=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_RALINK=y
+CONFIG_RALINK_WDT=y
+# CONFIG_RCU_NEED_SEGCBLIST is not set
+# CONFIG_RCU_STALL_COMMON is not set
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RESET_CONTROLLER=y
+# CONFIG_SCHED_INFO is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SERIAL_8250_FSL is not set
+CONFIG_SERIAL_8250_RT288X=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SOC_MT7620=y
+# CONFIG_SOC_MT7621 is not set
+# CONFIG_SOC_RT288X is not set
+# CONFIG_SOC_RT305X is not set
+# CONFIG_SOC_RT3883 is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+# CONFIG_SPI_MT7621 is not set
+CONFIG_SPI_RT2880=y
+CONFIG_SRCU=y
+CONFIG_SWCONFIG=y
+CONFIG_SWCONFIG_LEDS=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_THIN_ARCHIVES=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TINY_SRCU=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
diff --git a/target/linux/ramips/mt7621/config-4.14 b/target/linux/ramips/mt7621/config-4.14
new file mode 100644 (file)
index 0000000..3a5cd42
--- /dev/null
@@ -0,0 +1,286 @@
+CONFIG_ARCH_BINFMT_ELF_STATE=y
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+# CONFIG_ARCH_HAS_SG_CHAIN is not set
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BOARD_SCACHE=y
+CONFIG_BOUNCE=y
+CONFIG_CEVT_R4K=y
+# CONFIG_CEVT_SYSTICK_QUIRK is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_MIPS_GIC=y
+CONFIG_CLKSRC_OF=y
+CONFIG_CLKSRC_PROBE=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_COMMON_CLK=y
+# CONFIG_COMMON_CLK_BOSTON is not set
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_MIPSR2_IRQ_EI=y
+CONFIG_CPU_MIPSR2_IRQ_VI=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_R4K_FPU=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_NULL2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_PINCTRL=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DTB_RT_NONE=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_FIXED_PHY=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_IPI=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_MT7621=y
+# CONFIG_GPIO_RALINK is not set
+CONFIG_GPIO_SYSFS=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+# CONFIG_HAVE_ARCH_BITREVERSE is not set
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_CBPF_JIT=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_KVM=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HIGHMEM=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_MT7621=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LIBFDT=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+CONFIG_MIPS_CM=y
+# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+CONFIG_MIPS_CPC=y
+CONFIG_MIPS_CPS=y
+# CONFIG_MIPS_CPS_NS16550 is not set
+CONFIG_MIPS_CPU_SCACHE=y
+# CONFIG_MIPS_ELF_APPENDED_DTB is not set
+CONFIG_MIPS_GIC=y
+# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MACHINE is not set
+CONFIG_MIPS_MT=y
+CONFIG_MIPS_MT_FPAFF=y
+CONFIG_MIPS_MT_SMP=y
+CONFIG_MIPS_NO_APPENDED_DTB=y
+CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
+# CONFIG_MIPS_RAW_APPENDED_DTB is not set
+CONFIG_MIPS_SPRAM=y
+# CONFIG_MIPS_VPE_LOADER is not set
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MT7621_WDT=y
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_SEAMA_FW=y
+CONFIG_MTD_SPLIT_TPLINK_FW=y
+CONFIG_MTD_SPLIT_TRX_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+# CONFIG_MTD_UBI_FASTMAP is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTK_MTD_NAND=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_MEDIATEK_GSW_MT7621=y
+CONFIG_NET_MEDIATEK_MDIO=y
+CONFIG_NET_MEDIATEK_MDIO_MT7620=y
+CONFIG_NET_MEDIATEK_MT7621=y
+CONFIG_NET_MEDIATEK_SOC=y
+CONFIG_NET_VENDOR_MEDIATEK=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+# CONFIG_NO_IOPORT_MAP is not set
+CONFIG_NR_CPUS=4
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_PADATA=y
+CONFIG_PCI=y
+CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+# CONFIG_PHY_RALINK_USB is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_RT2880=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_RALINK=y
+# CONFIG_RALINK_WDT is not set
+CONFIG_RATIONAL=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_SPI=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PCF8563=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+# CONFIG_SCHED_INFO is not set
+CONFIG_SCHED_SMT=y
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SERIAL_8250_FSL is not set
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SMP=y
+CONFIG_SMP_UP=y
+# CONFIG_SOC_MT7620 is not set
+CONFIG_SOC_MT7621=y
+# CONFIG_SOC_RT288X is not set
+# CONFIG_SOC_RT305X is not set
+# CONFIG_SOC_RT3883 is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MT7621=y
+# CONFIG_SPI_RT2880 is not set
+CONFIG_SRCU=y
+CONFIG_SWCONFIG_LEDS=y
+CONFIG_SWCONFIG=y
+CONFIG_SWPHY=y
+CONFIG_SYNC_R4K=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_MIPS_CPS=y
+CONFIG_SYS_SUPPORTS_MULTITHREADING=y
+CONFIG_SYS_SUPPORTS_SCHED_SMT=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TREE_RCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WEAK_ORDERING=y
+CONFIG_XPS=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
diff --git a/target/linux/ramips/mt76x8/config-4.14 b/target/linux/ramips/mt76x8/config-4.14
new file mode 100644 (file)
index 0000000..56e734d
--- /dev/null
@@ -0,0 +1,237 @@
+CONFIG_ARCH_BINFMT_ELF_STATE=y
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+# CONFIG_ARCH_HAS_SG_CHAIN is not set
+# CONFIG_ARCH_HAS_STRICT_KERNEL_RWX is not set
+# CONFIG_ARCH_HAS_STRICT_MODULE_RWX is not set
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set
+# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
+CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
+# CONFIG_ARCH_WANTS_THP_SWAP is not set
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_AT803X_PHY=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CEVT_R4K=y
+CONFIG_CEVT_SYSTICK_QUIRK=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKEVT_RT3352=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_R4K_FPU=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_PINCTRL=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_DMA_NOOP_OPS is not set
+# CONFIG_DMA_VIRT_OPS is not set
+# CONFIG_DRM_LIB_RANDOM is not set
+# CONFIG_DTB_MT7620A_EVAL is not set
+# CONFIG_DTB_OMEGA2P is not set
+CONFIG_DTB_RT_NONE=y
+# CONFIG_DTB_VOCORE2 is not set
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_EXPORTFS=y
+CONFIG_FIXED_PHY=y
+CONFIG_FUTEX_PI=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_MT7621=y
+# CONFIG_GPIO_RALINK is not set
+CONFIG_GPIO_SYSFS=y
+# CONFIG_GRO_CELLS is not set
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+# CONFIG_HAVE_ARCH_BITREVERSE is not set
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_CBPF_JIT=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_COPY_THREAD_TLS=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_KVM=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_INTC=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LIBFDT=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+# CONFIG_MIPS_ELF_APPENDED_DTB is not set
+# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MACHINE is not set
+CONFIG_MIPS_NO_APPENDED_DTB=y
+# CONFIG_MIPS_RAW_APPENDED_DTB is not set
+CONFIG_MIPS_SPRAM=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MT7621_WDT=y
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_TPLINK_FW=y
+CONFIG_MTD_SPLIT_TRX_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_MEDIATEK_ESW_RT3050=y
+# CONFIG_NET_MEDIATEK_MT7620 is not set
+CONFIG_NET_MEDIATEK_RT3050=y
+CONFIG_NET_MEDIATEK_SOC=y
+CONFIG_NET_VENDOR_MEDIATEK=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+# CONFIG_NO_IOPORT_MAP is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHY_RALINK_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_RT2880=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_RALINK=y
+# CONFIG_RALINK_WDT is not set
+# CONFIG_RCU_NEED_SEGCBLIST is not set
+# CONFIG_RCU_STALL_COMMON is not set
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RESET_CONTROLLER=y
+# CONFIG_SCHED_INFO is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SERIAL_8250_FSL is not set
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SOC_MT7620=y
+# CONFIG_SOC_MT7621 is not set
+# CONFIG_SOC_RT288X is not set
+# CONFIG_SOC_RT305X is not set
+# CONFIG_SOC_RT3883 is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MT7621=y
+# CONFIG_SPI_RT2880 is not set
+CONFIG_SRCU=y
+CONFIG_SWCONFIG=y
+CONFIG_SWCONFIG_LEDS=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_THIN_ARCHIVES=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TINY_SRCU=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
diff --git a/target/linux/ramips/patches-4.14/0004-MIPS-ralink-add-MT7621-pcie-driver.patch b/target/linux/ramips/patches-4.14/0004-MIPS-ralink-add-MT7621-pcie-driver.patch
new file mode 100644 (file)
index 0000000..0c96d6b
--- /dev/null
@@ -0,0 +1,861 @@
+From fec11d4e8dc5cc79bcd7c8fd55038ac21ac39965 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 16 Mar 2014 05:22:39 +0000
+Subject: [PATCH 04/53] MIPS: ralink: add MT7621 pcie driver
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/Makefile     |    1 +
+ arch/mips/pci/pci-mt7621.c |  813 ++++++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 814 insertions(+)
+ create mode 100644 arch/mips/pci/pci-mt7621.c
+
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -47,6 +47,7 @@ obj-$(CONFIG_SNI_RM)         += fixup-sni.o ops
+ obj-$(CONFIG_LANTIQ)          += fixup-lantiq.o
+ obj-$(CONFIG_PCI_LANTIQ)      += pci-lantiq.o ops-lantiq.o
+ obj-$(CONFIG_SOC_MT7620)      += pci-mt7620.o
++obj-$(CONFIG_SOC_MT7621)      += pci-mt7621.o
+ obj-$(CONFIG_SOC_RT288X)      += pci-rt2880.o
+ obj-$(CONFIG_SOC_RT3883)      += pci-rt3883.o
+ obj-$(CONFIG_TANBAC_TB0219)   += fixup-tb0219.o
+--- /dev/null
++++ b/arch/mips/pci/pci-mt7621.c
+@@ -0,0 +1,836 @@
++/**************************************************************************
++ *
++ *  BRIEF MODULE DESCRIPTION
++ *     PCI init for Ralink RT2880 solution
++ *
++ *  Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
++ *
++ *  This program is free software; you can redistribute  it and/or modify it
++ *  under  the terms of  the GNU General  Public License as published by the
++ *  Free Software Foundation;  either version 2 of the  License, or (at your
++ *  option) any later version.
++ *
++ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
++ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
++ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
++ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
++ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
++ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
++ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ *  You should have received a copy of the  GNU General Public License along
++ *  with this program; if not, write  to the Free Software Foundation, Inc.,
++ *  675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ *
++ **************************************************************************
++ * May 2007 Bruce Chang
++ * Initial Release
++ *
++ * May 2009 Bruce Chang
++ * support RT2880/RT3883 PCIe
++ *
++ * May 2011 Bruce Chang
++ * support RT6855/MT7620 PCIe
++ *
++ **************************************************************************
++ */
++
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/version.h>
++#include <asm/pci.h>
++#include <asm/io.h>
++#include <asm/mips-cm.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/of.h>
++#include <linux/of_pci.h>
++#include <linux/of_irq.h>
++#include <linux/platform_device.h>
++
++#include <ralink_regs.h>
++
++extern void pcie_phy_init(void);
++extern void chk_phy_pll(void);
++
++/*
++ * These functions and structures provide the BIOS scan and mapping of the PCI
++ * devices.
++ */
++
++#define CONFIG_PCIE_PORT0
++#define CONFIG_PCIE_PORT1
++#define CONFIG_PCIE_PORT2
++#define RALINK_PCIE0_CLK_EN             (1<<24)
++#define RALINK_PCIE1_CLK_EN             (1<<25)
++#define RALINK_PCIE2_CLK_EN             (1<<26)
++
++#define RALINK_PCI_CONFIG_ADDR                         0x20
++#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG     0x24
++#define RALINK_INT_PCIE0         pcie_irq[0]
++#define RALINK_INT_PCIE1         pcie_irq[1]
++#define RALINK_INT_PCIE2         pcie_irq[2]
++#define RALINK_PCI_MEMBASE              *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
++#define RALINK_PCI_IOBASE               *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
++#define RALINK_PCIE0_RST                (1<<24)
++#define RALINK_PCIE1_RST                (1<<25)
++#define RALINK_PCIE2_RST                (1<<26)
++#define RALINK_SYSCTL_BASE              0xBE000000
++
++#define RALINK_PCI_PCICFG_ADDR          *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
++#define RALINK_PCI_PCIMSK_ADDR          *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
++#define RALINK_PCI_BASE                 0xBE140000
++
++#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
++#define RT6855_PCIE0_OFFSET     0x2000
++#define RT6855_PCIE1_OFFSET     0x3000
++#define RT6855_PCIE2_OFFSET     0x4000
++
++#define RALINK_PCI0_BAR0SETUP_ADDR      *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
++#define RALINK_PCI0_IMBASEBAR0_ADDR     *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
++#define RALINK_PCI0_ID                  *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
++#define RALINK_PCI0_CLASS               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
++#define RALINK_PCI0_SUBID               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
++#define RALINK_PCI0_STATUS              *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
++#define RALINK_PCI0_DERR                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
++#define RALINK_PCI0_ECRC                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
++
++#define RALINK_PCI1_BAR0SETUP_ADDR      *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
++#define RALINK_PCI1_IMBASEBAR0_ADDR     *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
++#define RALINK_PCI1_ID                  *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
++#define RALINK_PCI1_CLASS               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
++#define RALINK_PCI1_SUBID               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
++#define RALINK_PCI1_STATUS              *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
++#define RALINK_PCI1_DERR                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
++#define RALINK_PCI1_ECRC                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
++
++#define RALINK_PCI2_BAR0SETUP_ADDR      *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
++#define RALINK_PCI2_IMBASEBAR0_ADDR     *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
++#define RALINK_PCI2_ID                  *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
++#define RALINK_PCI2_CLASS               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
++#define RALINK_PCI2_SUBID               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
++#define RALINK_PCI2_STATUS              *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
++#define RALINK_PCI2_DERR                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
++#define RALINK_PCI2_ECRC                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
++
++#define RALINK_PCIEPHY_P0P1_CTL_OFFSET  (RALINK_PCI_BASE + 0x9000)
++#define RALINK_PCIEPHY_P2_CTL_OFFSET    (RALINK_PCI_BASE + 0xA000)
++
++
++#define MV_WRITE(ofs, data)  \
++        *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
++#define MV_READ(ofs, data)   \
++              *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
++#define MV_READ_DATA(ofs)    \
++                      le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
++
++#define MV_WRITE_16(ofs, data)  \
++        *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
++#define MV_READ_16(ofs, data)   \
++              *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
++
++#define MV_WRITE_8(ofs, data)  \
++        *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
++#define MV_READ_8(ofs, data)   \
++              *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
++
++
++
++#define RALINK_PCI_MM_MAP_BASE        0x60000000
++#define RALINK_PCI_IO_MAP_BASE        0x1e160000
++
++#define RALINK_SYSTEM_CONTROL_BASE    0xbe000000
++#define GPIO_PERST
++#define ASSERT_SYSRST_PCIE(val)               do {    \
++                                              if (*(unsigned int *)(0xbe00000c) == 0x00030101)        \
++                                                      RALINK_RSTCTRL |= val;  \
++                                              else    \
++                                                      RALINK_RSTCTRL &= ~val; \
++                                      } while(0)
++#define DEASSERT_SYSRST_PCIE(val)     do {    \
++                                              if (*(unsigned int *)(0xbe00000c) == 0x00030101)        \
++                                                      RALINK_RSTCTRL &= ~val; \
++                                              else    \
++                                                      RALINK_RSTCTRL |= val;  \
++                                      } while(0)
++#define RALINK_SYSCFG1                        *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x14)
++#define RALINK_CLKCFG1                        *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x30)
++#define RALINK_RSTCTRL                        *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x34)
++#define RALINK_GPIOMODE                       *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x60)
++#define RALINK_PCIE_CLK_GEN           *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x7c)
++#define RALINK_PCIE_CLK_GEN1          *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x80)
++#define PPLL_CFG1                     *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x9c)
++#define PPLL_DRV                      *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0xa0)
++//RALINK_SYSCFG1 bit
++#define RALINK_PCI_HOST_MODE_EN               (1<<7)
++#define RALINK_PCIE_RC_MODE_EN                (1<<8)
++//RALINK_RSTCTRL bit
++#define RALINK_PCIE_RST                       (1<<23)
++#define RALINK_PCI_RST                        (1<<24)
++//RALINK_CLKCFG1 bit
++#define RALINK_PCI_CLK_EN             (1<<19)
++#define RALINK_PCIE_CLK_EN            (1<<21)
++//RALINK_GPIOMODE bit
++#define PCI_SLOTx2                    (1<<11)
++#define PCI_SLOTx1                    (2<<11)
++//MTK PCIE PLL bit
++#define PDRV_SW_SET                   (1<<31)
++#define LC_CKDRVPD_                   (1<<19)
++
++#define MEMORY_BASE 0x0
++static int pcie_link_status = 0;
++
++#define PCI_ACCESS_READ_1  0
++#define PCI_ACCESS_READ_2  1
++#define PCI_ACCESS_READ_4  2
++#define PCI_ACCESS_WRITE_1 3
++#define PCI_ACCESS_WRITE_2 4
++#define PCI_ACCESS_WRITE_4 5
++
++static int pcie_irq[3];
++
++static int config_access(unsigned char access_type, struct pci_bus *bus,
++                      unsigned int devfn, unsigned int where, u32 * data)
++{
++      unsigned int slot = PCI_SLOT(devfn);
++      u8 func = PCI_FUNC(devfn);
++      uint32_t address_reg, data_reg;
++      unsigned int address;
++
++      address_reg = RALINK_PCI_CONFIG_ADDR;
++      data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
++
++      address = (((where&0xF00)>>8)<<24) |(bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
++      MV_WRITE(address_reg, address);
++
++      switch(access_type) {
++      case PCI_ACCESS_WRITE_1:
++              MV_WRITE_8(data_reg+(where&0x3), *data);
++              break;
++      case PCI_ACCESS_WRITE_2:
++              MV_WRITE_16(data_reg+(where&0x3), *data);
++              break;
++      case PCI_ACCESS_WRITE_4:
++              MV_WRITE(data_reg, *data);
++              break;
++      case PCI_ACCESS_READ_1:
++              MV_READ_8( data_reg+(where&0x3), data);
++              break;
++      case PCI_ACCESS_READ_2:
++              MV_READ_16(data_reg+(where&0x3), data);
++              break;
++      case PCI_ACCESS_READ_4:
++              MV_READ(data_reg, data);
++              break;
++      default:
++              printk("no specify access type\n");
++              break;
++      }
++      return 0;
++}
++
++static int
++read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
++{
++      return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned int)where, (u32 *)val);
++}
++
++static int
++read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
++{
++      return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned int)where, (u32 *)val);
++}
++
++static int
++read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
++{
++      return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned int)where, (u32 *)val);
++}
++
++static int
++write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
++{
++      if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where, (u32 *)&val))
++              return -1;
++
++      return PCIBIOS_SUCCESSFUL;
++}
++
++static int
++write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
++{
++      if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
++              return -1;
++
++      return PCIBIOS_SUCCESSFUL;
++}
++
++static int
++write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
++{
++      if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
++              return -1;
++
++      return PCIBIOS_SUCCESSFUL;
++}
++
++
++static int
++pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
++{
++      switch (size) {
++      case 1:
++              return read_config_byte(bus, devfn, where, (u8 *) val);
++      case 2:
++              return read_config_word(bus, devfn, where, (u16 *) val);
++      default:
++              return read_config_dword(bus, devfn, where, val);
++      }
++}
++
++static int
++pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
++{
++      switch (size) {
++      case 1:
++              return write_config_byte(bus, devfn, where, (u8) val);
++      case 2:
++              return write_config_word(bus, devfn, where, (u16) val);
++      default:
++              return write_config_dword(bus, devfn, where, val);
++      }
++}
++
++struct pci_ops mt7621_pci_ops= {
++      .read           =  pci_config_read,
++      .write          = pci_config_write,
++};
++
++static struct resource mt7621_res_pci_mem1 = {
++      .name           = "PCI MEM1",
++      .start          = RALINK_PCI_MM_MAP_BASE,
++      .end            = (u32)((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
++      .flags          = IORESOURCE_MEM,
++};
++static struct resource mt7621_res_pci_io1 = {
++      .name           = "PCI I/O1",
++      .start          = RALINK_PCI_IO_MAP_BASE,
++      .end            = (u32)((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
++      .flags          = IORESOURCE_IO,
++};
++
++static struct pci_controller mt7621_controller = {
++      .pci_ops        = &mt7621_pci_ops,
++      .mem_resource   = &mt7621_res_pci_mem1,
++      .io_resource    = &mt7621_res_pci_io1,
++      .mem_offset     = 0x00000000UL,
++      .io_offset      = 0x00000000UL,
++      .io_map_base    = 0xa0000000,
++};
++
++static void
++read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val)
++{
++      unsigned int address_reg, data_reg, address;
++
++      address_reg = RALINK_PCI_CONFIG_ADDR;
++        data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
++      address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
++        MV_WRITE(address_reg, address);
++        MV_READ(data_reg, val);
++      return;
++}
++
++static void
++write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val)
++{
++      unsigned int address_reg, data_reg, address;
++
++      address_reg = RALINK_PCI_CONFIG_ADDR;
++      data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
++      address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
++      MV_WRITE(address_reg, address);
++      MV_WRITE(data_reg, val);
++      return;
++}
++
++
++int __init
++pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
++{
++      u16 cmd;
++      u32 val;
++      int irq = 0;
++
++      if ((dev->bus->number == 0) && (slot == 0)) {
++              write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
++              read_config(0, 0, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
++              printk("BAR0 at slot 0 = %x\n", val);
++              printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
++      } else if((dev->bus->number == 0) && (slot == 0x1)) {
++              write_config(0, 1, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
++              read_config(0, 1, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
++              printk("BAR0 at slot 1 = %x\n", val);
++              printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
++      } else if((dev->bus->number == 0) && (slot == 0x2)) {
++              write_config(0, 2, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
++              read_config(0, 2, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
++              printk("BAR0 at slot 2 = %x\n", val);
++              printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
++      } else if ((dev->bus->number == 1) && (slot == 0x0)) {
++              switch (pcie_link_status) {
++              case 2:
++              case 6:
++                      irq = RALINK_INT_PCIE1;
++                      break;
++              case 4:
++                      irq = RALINK_INT_PCIE2;
++                      break;
++              default:
++                      irq = RALINK_INT_PCIE0;
++              }
++              printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
++      } else if ((dev->bus->number == 2) && (slot == 0x0)) {
++              switch (pcie_link_status) {
++              case 5:
++              case 6:
++                      irq = RALINK_INT_PCIE2;
++                      break;
++              default:
++                      irq = RALINK_INT_PCIE1;
++              }
++              printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
++      } else if ((dev->bus->number == 2) && (slot == 0x1)) {
++              switch (pcie_link_status) {
++              case 5:
++              case 6:
++                      irq = RALINK_INT_PCIE2;
++                      break;
++              default:
++                      irq = RALINK_INT_PCIE1;
++              }
++              printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
++      } else if ((dev->bus->number ==3) && (slot == 0x0)) {
++              irq = RALINK_INT_PCIE2;
++              printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
++      } else if ((dev->bus->number ==3) && (slot == 0x1)) {
++              irq = RALINK_INT_PCIE2;
++              printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
++      } else if ((dev->bus->number ==3) && (slot == 0x2)) {
++              irq = RALINK_INT_PCIE2;
++              printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
++      } else {
++