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rtl83xx: pr_info->pr_debug
[openwrt/staging/blogic.git] / target / linux / rtl838x / files-5.4 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5
6 #include <asm/mach-rtl838x/mach-rtl838x.h>
7 #include "rtl83xx.h"
8
9
10 extern struct rtl838x_soc_info soc_info;
11
12
13 static void rtl83xx_print_matrix(void)
14 {
15 unsigned volatile int *ptr8;
16 volatile u64 *ptr9;
17 int i;
18
19 if (soc_info.family == RTL8380_FAMILY_ID) {
20 ptr8 = RTL838X_SW_BASE + RTL838X_PORT_ISO_CTRL(0);
21 for (i = 0; i < 28; i += 8)
22 pr_debug("> %8x %8x %8x %8x %8x %8x %8x %8x\n",
23 ptr8[i + 0], ptr8[i + 1], ptr8[i + 2], ptr8[i + 3],
24 ptr8[i + 4], ptr8[i + 5], ptr8[i + 6], ptr8[i + 7]);
25 pr_debug("CPU_PORT> %8x\n", ptr8[28]);
26 } else {
27 ptr9 = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0);
28 for (i = 0; i < 52; i += 4)
29 pr_debug("> %16llx %16llx %16llx %16llx\n",
30 ptr9[i + 0], ptr9[i + 1], ptr9[i + 2], ptr9[i + 3]);
31 pr_debug("CPU_PORT> %16llx\n", ptr9[52]);
32 }
33
34 }
35
36 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
37 {
38 mutex_lock(&priv->reg_mutex);
39
40 /* Enable statistics module: all counters plus debug.
41 * On RTL839x all counters are enabled by default
42 */
43 if (priv->family_id == RTL8380_FAMILY_ID)
44 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
45
46 /* Reset statistics counters */
47 sw_w32_mask(0, 1, priv->r->stat_rst);
48
49 mutex_unlock(&priv->reg_mutex);
50 }
51
52 static void rtl83xx_write_cam(int idx, u32 *r)
53 {
54 u32 cmd = BIT(16) /* Execute cmd */
55 | BIT(15) /* Read */
56 | BIT(13) /* Table type 0b01 */
57 | (idx & 0x3f);
58
59 sw_w32(r[0], RTL838X_TBL_ACCESS_L2_DATA(0));
60 sw_w32(r[1], RTL838X_TBL_ACCESS_L2_DATA(1));
61 sw_w32(r[2], RTL838X_TBL_ACCESS_L2_DATA(2));
62
63 sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
64 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16));
65 }
66
67 static u64 rtl83xx_hash_key(struct rtl838x_switch_priv *priv, u64 mac, u32 vid)
68 {
69 if (priv->family_id == RTL8380_FAMILY_ID)
70 return rtl838x_hash(priv, mac << 12 | vid);
71 else
72 return rtl839x_hash(priv, mac << 12 | vid);
73 }
74
75 static void rtl83xx_write_hash(int idx, u32 *r)
76 {
77 u32 cmd = BIT(16) /* Execute cmd */
78 | 0 << 15 /* Write */
79 | 0 << 13 /* Table type 0b00 */
80 | (idx & 0x1fff);
81
82 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(0));
83 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(1));
84 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(2));
85 sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
86 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16));
87 }
88
89 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
90 {
91 int i;
92 u64 v = 0;
93
94 msleep(1000);
95 /* Enable all ports with a PHY, including the SFP-ports */
96 for (i = 0; i < priv->cpu_port; i++) {
97 if (priv->ports[i].phy)
98 v |= BIT(i);
99 }
100
101 pr_debug("%s: %16llx\n", __func__, v);
102 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
103
104 /* PHY update complete */
105 if (priv->family_id == RTL8390_FAMILY_ID)
106 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
107 else
108 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
109 }
110
111 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
112 MIB_DESC(2, 0xf8, "ifInOctets"),
113 MIB_DESC(2, 0xf0, "ifOutOctets"),
114 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
115 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
116 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
117 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
118 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
119 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
120 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
121 MIB_DESC(1, 0xd0, "ifOutDiscards"),
122 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
123 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
124 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
125 MIB_DESC(1, 0xc0, ".3LateCollisions"),
126 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
127 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
128 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
129 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
130 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
131 MIB_DESC(1, 0xa8, "DropEvents"),
132 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
133 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
134 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
135 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
136 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
137 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
138 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
139 MIB_DESC(1, 0x88, "rx_OversizePkts"),
140 MIB_DESC(1, 0x84, "Fragments"),
141 MIB_DESC(1, 0x80, "Jabbers"),
142 MIB_DESC(1, 0x7c, "Collisions"),
143 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
144 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
145 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
146 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
147 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
148 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
149 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
150 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
151 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
152 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
153 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
154 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
155 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
156 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
157 MIB_DESC(1, 0x40, "rxMacDiscards")
158 };
159
160
161 /* DSA callbacks */
162
163
164 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds, int port)
165 {
166 /* The switch does not tag the frames, instead internally the header
167 * structure for each packet is tagged accordingly.
168 */
169 return DSA_TAG_PROTO_TRAILER;
170 }
171
172 static int rtl83xx_setup(struct dsa_switch *ds)
173 {
174 int i;
175 struct rtl838x_switch_priv *priv = ds->priv;
176 u64 port_bitmap = BIT_ULL(priv->cpu_port);
177
178 pr_debug("%s called\n", __func__);
179
180 /* Disable MAC polling the PHY so that we can start configuration */
181 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
182
183 for (i = 0; i < ds->num_ports; i++)
184 priv->ports[i].enable = false;
185 priv->ports[priv->cpu_port].enable = true;
186
187 /* Isolate ports from each other: traffic only CPU <-> port */
188 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
189 * traffic from source port i to destination port j
190 */
191 for (i = 0; i < priv->cpu_port; i++) {
192 if (priv->ports[i].phy) {
193 priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT(i),
194 priv->r->port_iso_ctrl(i));
195 port_bitmap |= BIT_ULL(i);
196 }
197 }
198 priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
199
200 rtl83xx_print_matrix();
201
202 rtl83xx_init_stats(priv);
203
204 /* Enable MAC Polling PHY again */
205 rtl83xx_enable_phy_polling(priv);
206 pr_debug("Please wait until PHY is settled\n");
207 msleep(1000);
208 return 0;
209 }
210
211 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
212 unsigned long *supported,
213 struct phylink_link_state *state)
214 {
215 struct rtl838x_switch_priv *priv = ds->priv;
216 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
217
218 pr_debug("In %s port %d", __func__, port);
219
220 if (!phy_interface_mode_is_rgmii(state->interface) &&
221 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
222 state->interface != PHY_INTERFACE_MODE_MII &&
223 state->interface != PHY_INTERFACE_MODE_REVMII &&
224 state->interface != PHY_INTERFACE_MODE_GMII &&
225 state->interface != PHY_INTERFACE_MODE_QSGMII &&
226 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
227 state->interface != PHY_INTERFACE_MODE_SGMII) {
228 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
229 dev_err(ds->dev,
230 "Unsupported interface: %d for port %d\n",
231 state->interface, port);
232 return;
233 }
234
235 /* Allow all the expected bits */
236 phylink_set(mask, Autoneg);
237 phylink_set_port_modes(mask);
238 phylink_set(mask, Pause);
239 phylink_set(mask, Asym_Pause);
240
241 /* With the exclusion of MII and Reverse MII, we support Gigabit,
242 * including Half duplex
243 */
244 if (state->interface != PHY_INTERFACE_MODE_MII &&
245 state->interface != PHY_INTERFACE_MODE_REVMII) {
246 phylink_set(mask, 1000baseT_Full);
247 phylink_set(mask, 1000baseT_Half);
248 }
249
250 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
251 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
252 phylink_set(mask, 1000baseX_Full);
253
254 phylink_set(mask, 10baseT_Half);
255 phylink_set(mask, 10baseT_Full);
256 phylink_set(mask, 100baseT_Half);
257 phylink_set(mask, 100baseT_Full);
258
259 bitmap_and(supported, supported, mask,
260 __ETHTOOL_LINK_MODE_MASK_NBITS);
261 bitmap_and(state->advertising, state->advertising, mask,
262 __ETHTOOL_LINK_MODE_MASK_NBITS);
263 }
264
265 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
266 struct phylink_link_state *state)
267 {
268 struct rtl838x_switch_priv *priv = ds->priv;
269 u64 speed;
270
271 if (port < 0 || port > priv->cpu_port)
272 return -EINVAL;
273
274 state->link = 0;
275 if (priv->r->get_port_reg_le(priv->r->mac_link_sts) & BIT_ULL(port))
276 state->link = 1;
277 state->duplex = 0;
278 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
279 state->duplex = 1;
280
281 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
282 speed >>= (port % 16) << 1;
283 switch (speed & 0x3) {
284 case 0:
285 state->speed = SPEED_10;
286 break;
287 case 1:
288 state->speed = SPEED_100;
289 break;
290 case 2:
291 state->speed = SPEED_1000;
292 break;
293 case 3:
294 if (port == 24 || port == 26) /* Internal serdes */
295 state->speed = SPEED_2500;
296 else
297 state->speed = SPEED_100; /* Is in fact 500Mbit */
298 }
299
300 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
301 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
302 state->pause |= MLO_PAUSE_RX;
303 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
304 state->pause |= MLO_PAUSE_TX;
305 return 1;
306 }
307
308 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
309 unsigned int mode,
310 const struct phylink_link_state *state)
311 {
312 struct rtl838x_switch_priv *priv = ds->priv;
313 u32 reg;
314 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
315
316 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
317
318 if (port == priv->cpu_port) {
319 /* Set Speed, duplex, flow control
320 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
321 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
322 * | MEDIA_SEL
323 */
324 if (priv->family_id == RTL8380_FAMILY_ID) {
325 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
326 /* allow CRC errors on CPU-port */
327 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
328 } else {
329 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
330 }
331 return;
332 }
333
334 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
335 /* Auto-Negotiation does not work for MAC in RTL8390 */
336 if (priv->family_id == RTL8380_FAMILY_ID) {
337 if (mode == MLO_AN_PHY) {
338 pr_debug("PHY autonegotiates\n");
339 reg |= BIT(2);
340 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
341 return;
342 }
343 }
344
345 if (mode != MLO_AN_FIXED)
346 pr_debug("Fixed state.\n");
347
348 if (priv->family_id == RTL8380_FAMILY_ID) {
349 /* Clear id_mode_dis bit, and the existing port mode, let
350 * RGMII_MODE_EN bet set by mac_link_{up,down}
351 */
352 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
353
354 if (state->pause & MLO_PAUSE_TXRX_MASK) {
355 if (state->pause & MLO_PAUSE_TX)
356 reg |= TX_PAUSE_EN;
357 reg |= RX_PAUSE_EN;
358 }
359 }
360
361 reg &= ~(3 << speed_bit);
362 switch (state->speed) {
363 case SPEED_1000:
364 reg |= 2 << speed_bit;
365 break;
366 case SPEED_100:
367 reg |= 1 << speed_bit;
368 break;
369 }
370
371 if (priv->family_id == RTL8380_FAMILY_ID) {
372 reg &= ~(DUPLEX_FULL | FORCE_LINK_EN);
373 if (state->link)
374 reg |= FORCE_LINK_EN;
375 if (state->duplex == DUPLEX_FULL)
376 reg |= DUPLX_MODE;
377 }
378
379 // Disable AN
380 if (priv->family_id == RTL8380_FAMILY_ID)
381 reg &= ~BIT(2);
382 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
383 }
384
385 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
386 unsigned int mode,
387 phy_interface_t interface)
388 {
389 struct rtl838x_switch_priv *priv = ds->priv;
390 /* Stop TX/RX to port */
391 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
392 }
393
394 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
395 unsigned int mode,
396 phy_interface_t interface,
397 struct phy_device *phydev)
398 {
399 struct rtl838x_switch_priv *priv = ds->priv;
400 /* Restart TX/RX to port */
401 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
402 }
403
404 static void rtl83xx_get_strings(struct dsa_switch *ds,
405 int port, u32 stringset, u8 *data)
406 {
407 int i;
408
409 if (stringset != ETH_SS_STATS)
410 return;
411
412 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
413 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
414 ETH_GSTRING_LEN);
415 }
416
417 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
418 uint64_t *data)
419 {
420 struct rtl838x_switch_priv *priv = ds->priv;
421 const struct rtl83xx_mib_desc *mib;
422 int i;
423 u64 high;
424
425 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
426 mib = &rtl83xx_mib[i];
427
428 data[i] = sw_r32(priv->r->stat_port_std_mib(port) + 252 - mib->offset);
429 if (mib->size == 2) {
430 high = sw_r32(priv->r->stat_port_std_mib(port) + 252 - mib->offset - 4);
431 data[i] |= high << 32;
432 }
433 }
434 }
435
436 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
437 {
438 if (sset != ETH_SS_STATS)
439 return 0;
440
441 return ARRAY_SIZE(rtl83xx_mib);
442 }
443
444 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
445 struct phy_device *phydev)
446 {
447 struct rtl838x_switch_priv *priv = ds->priv;
448
449 pr_debug("%s: %x %d", __func__, (u32) priv, port);
450 priv->ports[port].enable = true;
451
452 if (dsa_is_cpu_port(ds, port))
453 return 0;
454
455 /* add port to switch mask of CPU_PORT */
456 priv->r->mask_port_reg_be(0ULL, BIT_ULL(port), priv->r->port_iso_ctrl(priv->cpu_port));
457
458 /* add all other ports in the same bridge to switch mask of port */
459 priv->r->mask_port_reg_be(0ULL, priv->ports[port].pm, priv->r->port_iso_ctrl(port));
460
461 return 0;
462 }
463
464 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
465 {
466 struct rtl838x_switch_priv *priv = ds->priv;
467
468 pr_debug("%s %x: %d", __func__, (u32)priv, port);
469 /* you can only disable user ports */
470 if (!dsa_is_user_port(ds, port))
471 return;
472
473 /* remove port from switch mask of CPU_PORT */
474 priv->r->mask_port_reg_be(BIT_ULL(port), 0, priv->r->port_iso_ctrl(priv->cpu_port));
475
476 /* remove all other ports in the same bridge from switch mask of port */
477 priv->r->mask_port_reg_be(priv->ports[port].pm, 0LL, priv->r->port_iso_ctrl(port));
478
479 priv->ports[port].enable = false;
480 }
481
482 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
483 struct ethtool_eee *e)
484 {
485 struct rtl838x_switch_priv *priv = ds->priv;
486
487 pr_debug("%s: port %d", __func__, port);
488 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
489 if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & BIT(9))
490 e->advertised |= ADVERTISED_100baseT_Full;
491
492 if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & BIT(10))
493 e->advertised |= ADVERTISED_1000baseT_Full;
494
495 e->eee_enabled = priv->ports[port].eee_enabled;
496 pr_debug("enabled: %d, active %x\n", e->eee_enabled, e->advertised);
497
498 if (sw_r32(RTL838X_MAC_EEE_ABLTY) & BIT(port)) {
499 e->lp_advertised = ADVERTISED_100baseT_Full;
500 e->lp_advertised |= ADVERTISED_1000baseT_Full;
501 }
502
503 e->eee_active = !!(e->advertised & e->lp_advertised);
504 pr_debug("active: %d, lp %x\n", e->eee_active, e->lp_advertised);
505
506 return 0;
507 }
508
509 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
510 struct ethtool_eee *e)
511 {
512 struct rtl838x_switch_priv *priv = ds->priv;
513
514 pr_debug("%s: port %d", __func__, port);
515 if (e->eee_enabled) {
516 pr_debug("Globally enabling EEE\n");
517 sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL);
518 }
519 if (e->eee_enabled) {
520 pr_debug("Enabling EEE for MAC %d\n", port);
521 sw_w32_mask(0, 3 << 9, priv->r->mac_force_mode_ctrl(port));
522 sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_TX_EN);
523 sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_RX_EN);
524 priv->ports[port].eee_enabled = true;
525 e->eee_enabled = true;
526 } else {
527 pr_debug("Disabling EEE for MAC %d\n", port);
528 sw_w32_mask(3 << 9, 0, priv->r->mac_force_mode_ctrl(port));
529 sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_TX_EN);
530 sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_RX_EN);
531 priv->ports[port].eee_enabled = false;
532 e->eee_enabled = false;
533 }
534 return 0;
535 }
536
537 /*
538 * Set Switch L2 Aging time, t is time in milliseconds
539 * t = 0: aging is disabled
540 */
541 static int rtl83xx_set_l2aging(struct dsa_switch *ds, u32 t)
542 {
543 struct rtl838x_switch_priv *priv = ds->priv;
544 int t_max = priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
545
546 /* Convert time in mseconds to internal value */
547 if (t > 0x10000000) { /* Set to maximum */
548 t = t_max;
549 } else {
550 if (priv->family_id == RTL8380_FAMILY_ID)
551 t = ((t * 625) / 1000 + 127) / 128;
552 else
553 t = (t * 5 + 2) / 3;
554 }
555 sw_w32(t, priv->r->l2_ctrl_1);
556 return 0;
557 }
558
559 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
560 struct net_device *bridge)
561 {
562 struct rtl838x_switch_priv *priv = ds->priv;
563 u64 port_bitmap = BIT_ULL(priv->cpu_port);
564 int i;
565
566 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
567 mutex_lock(&priv->reg_mutex);
568 for (i = 0; i < ds->num_ports; i++) {
569 /* Add this port to the port matrix of the other ports in the
570 * same bridge. If the port is disabled, port matrix is kept
571 * and not being setup until the port becomes enabled.
572 */
573 if (dsa_is_user_port(ds, i) && i != port) {
574 if (dsa_to_port(ds, i)->bridge_dev != bridge)
575 continue;
576 if (priv->ports[i].enable)
577 priv->r->mask_port_reg_be(0, BIT_ULL(port),
578 priv->r->port_iso_ctrl(i));
579 priv->ports[i].pm |= BIT_ULL(port);
580
581 port_bitmap |= BIT_ULL(i);
582 }
583 }
584
585 /* Add all other ports to this port matrix. */
586 if (priv->ports[port].enable) {
587 priv->r->mask_port_reg_be(0, BIT_ULL(port),
588 priv->r->port_iso_ctrl(priv->cpu_port));
589 priv->r->mask_port_reg_be(0, port_bitmap,
590 priv->r->port_iso_ctrl(port));
591 }
592 priv->ports[port].pm |= port_bitmap;
593 mutex_unlock(&priv->reg_mutex);
594
595 return 0;
596 }
597
598 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
599 struct net_device *bridge)
600 {
601 struct rtl838x_switch_priv *priv = ds->priv;
602 u64 port_bitmap = BIT_ULL(priv->cpu_port);
603 int i;
604
605 pr_debug("%s %x: %d", __func__, (u32)priv, port);
606 mutex_lock(&priv->reg_mutex);
607 for (i = 0; i < ds->num_ports; i++) {
608 /* Remove this port from the port matrix of the other ports
609 * in the same bridge. If the port is disabled, port matrix
610 * is kept and not being setup until the port becomes enabled.
611 * And the other port's port matrix cannot be broken when the
612 * other port is still a VLAN-aware port.
613 */
614 if (dsa_is_user_port(ds, i) && i != port) {
615 if (dsa_to_port(ds, i)->bridge_dev != bridge)
616 continue;
617 if (priv->ports[i].enable)
618 priv->r->mask_port_reg_be(BIT_ULL(port), 0,
619 priv->r->port_iso_ctrl(i));
620 priv->ports[i].pm &= ~BIT_ULL(port);
621
622 port_bitmap &= ~BIT_ULL(i);
623 }
624 }
625
626 /* Add all other ports to this port matrix. */
627 if (priv->ports[port].enable)
628 priv->r->mask_port_reg_be(0, port_bitmap, priv->r->port_iso_ctrl(port));
629 priv->ports[port].pm &= ~port_bitmap;
630
631 mutex_unlock(&priv->reg_mutex);
632 }
633
634 static void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port,
635 u8 state)
636 {
637 u32 cmd, msti = 0;
638 u32 port_state[4];
639 int index, bit, i;
640 int pos = port;
641 struct rtl838x_switch_priv *priv = ds->priv;
642 int n = priv->family_id == RTL8380_FAMILY_ID ? 2 : 4;
643
644 pr_debug("%s: port %d state %2x\n", __func__, port, state);
645
646 /* CPU PORT can only be configured on RTL838x */
647 if (port >= priv->cpu_port || port > 51)
648 return;
649
650 mutex_lock(&priv->reg_mutex);
651
652 /* For the RTL839x, the bits are left-aligned in the 128 bit field */
653 if (priv->family_id == RTL8390_FAMILY_ID)
654 pos += 12;
655
656 index = n - (pos >> 4) - 1;
657 bit = (pos << 1) % 32;
658
659 if (priv->family_id == RTL8380_FAMILY_ID) {
660 cmd = BIT(15) /* Execute cmd */
661 | BIT(14) /* Read */
662 | 2 << 12 /* Table type 0b10 */
663 | (msti & 0xfff);
664 } else {
665 cmd = BIT(16) /* Execute cmd */
666 | 0 << 15 /* Read */
667 | 5 << 12 /* Table type 0b101 */
668 | (msti & 0xfff);
669 }
670 priv->r->exec_tbl0_cmd(cmd);
671
672 for (i = 0; i < n; i++)
673 port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
674
675 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
676 port_state[index] &= ~(3 << bit);
677
678 switch (state) {
679 case BR_STATE_DISABLED: /* 0 */
680 port_state[index] |= (0 << bit);
681 break;
682 case BR_STATE_BLOCKING: /* 4 */
683 case BR_STATE_LISTENING: /* 1 */
684 port_state[index] |= (1 << bit);
685 break;
686 case BR_STATE_LEARNING: /* 2 */
687 port_state[index] |= (2 << bit);
688 break;
689 case BR_STATE_FORWARDING: /* 3*/
690 port_state[index] |= (3 << bit);
691 default:
692 break;
693 }
694
695 if (priv->family_id == RTL8380_FAMILY_ID) {
696 cmd = BIT(15) /* Execute cmd */
697 | 0 << 14 /* Write */
698 | 2 << 12 /* Table type 0b10 */
699 | (msti & 0xfff);
700 } else {
701 cmd = 1 << 16 /* Execute cmd */
702 | BIT(15) /* Write */
703 | 5 << 12 /* Table type 0b101 */
704 | (msti & 0xfff);
705 }
706 for (i = 0; i < n; i++)
707 sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
708 priv->r->exec_tbl0_cmd(cmd);
709
710 mutex_unlock(&priv->reg_mutex);
711 }
712
713 static void rtl83xx_fast_age(struct dsa_switch *ds, int port)
714 {
715 struct rtl838x_switch_priv *priv = ds->priv;
716 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
717
718 pr_debug("FAST AGE port %d\n", port);
719 mutex_lock(&priv->reg_mutex);
720 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
721 * port fields:
722 * 0-4: Replacing port
723 * 5-9: Flushed/replaced port
724 * 10-21: FVID
725 * 22: Entry types: 1: dynamic, 0: also static
726 * 23: Match flush port
727 * 24: Match FVID
728 * 25: Flush (0) or replace (1) L2 entries
729 * 26: Status of action (1: Start, 0: Done)
730 */
731 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
732
733 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << (26 + s)));
734
735 mutex_unlock(&priv->reg_mutex);
736 }
737
738 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
739 bool vlan_filtering)
740 {
741 struct rtl838x_switch_priv *priv = ds->priv;
742
743 pr_debug("%s: port %d\n", __func__, port);
744 mutex_lock(&priv->reg_mutex);
745
746 if (vlan_filtering) {
747 /* Enable ingress and egress filtering */
748 if (port != priv->cpu_port)
749 sw_w32_mask(0b10 << ((port % 16) << 1), 0b01 << ((port % 16) << 1),
750 priv->r->vlan_port_igr_filter(port));
751 sw_w32_mask(0, 1 << (port % 32), priv->r->vlan_port_egr_filter(port));
752 } else {
753 /* Disable ingress and egress filtering */
754 if (port != priv->cpu_port)
755 sw_w32_mask(0b11 << ((port % 16) << 1), 0,
756 priv->r->vlan_port_igr_filter(port));
757 sw_w32_mask(1 << (port % 32), 0, priv->r->vlan_port_egr_filter(port));
758 }
759
760 /* Do we need to do something to the CPU-Port, too? */
761 mutex_unlock(&priv->reg_mutex);
762
763 return 0;
764 }
765
766 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
767 const struct switchdev_obj_port_vlan *vlan)
768 {
769 struct rtl838x_vlan_info info;
770 struct rtl838x_switch_priv *priv = ds->priv;
771
772 pr_debug("%s: port %d\n", __func__, port);
773
774 mutex_lock(&priv->reg_mutex);
775
776 if (priv->family_id == RTL8380_FAMILY_ID)
777 rtl838x_vlan_profile_dump(0);
778 else
779 rtl839x_vlan_profile_dump(0);
780
781 priv->r->vlan_tables_read(0, &info);
782
783 pr_debug("Tagged ports %llx, untag %llx, prof %x, MC# %d, UC# %d, FID %x\n",
784 info.tagged_ports, info.untagged_ports, info.profile_id,
785 info.hash_mc, info.hash_uc, info.fid);
786
787 mutex_unlock(&priv->reg_mutex);
788 return 0;
789 }
790
791 static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
792 const struct switchdev_obj_port_vlan *vlan)
793 {
794 struct rtl838x_vlan_info info;
795 struct rtl838x_switch_priv *priv = ds->priv;
796 int v;
797 u64 portmask;
798
799 pr_debug("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
800 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
801
802 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
803 dev_err(priv->dev, "VLAN out of range: %d - %d",
804 vlan->vid_begin, vlan->vid_end);
805 return;
806 }
807
808 mutex_lock(&priv->reg_mutex);
809
810 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) {
811 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
812 /* Set both inner and outer PVID of the port */
813 sw_w32((v << 16) | v, priv->r->vlan_port_pb(port));
814 }
815 }
816
817 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED) {
818 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
819 /* Get untagged port memberships of this vlan */
820 priv->r->vlan_tables_read(v, &info);
821 portmask = info.untagged_ports | BIT(port);
822 pr_debug("Untagged ports, VLAN %d: %llx\n", v, portmask);
823 priv->r->vlan_set_untagged(v, portmask);
824 }
825 } else {
826 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
827 /* Get tagged port memberships of this vlan */
828 priv->r->vlan_tables_read(v, &info);
829 info.tagged_ports |= BIT(port);
830 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
831 priv->r->vlan_set_tagged(v, &info);
832 }
833 }
834
835 mutex_unlock(&priv->reg_mutex);
836 }
837
838 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
839 const struct switchdev_obj_port_vlan *vlan)
840 {
841 struct rtl838x_vlan_info info;
842 struct rtl838x_switch_priv *priv = ds->priv;
843 int v;
844 u64 portmask;
845
846 pr_debug("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
847 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
848
849 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
850 dev_err(priv->dev, "VLAN out of range: %d - %d",
851 vlan->vid_begin, vlan->vid_end);
852 return -ENOTSUPP;
853 }
854
855 mutex_lock(&priv->reg_mutex);
856
857 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
858 /* Reset both inner and out PVID of the port */
859 sw_w32(0, priv->r->vlan_port_pb(port));
860
861 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED) {
862 /* Get untagged port memberships of this vlan */
863 priv->r->vlan_tables_read(v, &info);
864 portmask = info.untagged_ports & (~(1ULL << port));
865 pr_debug("Untagged ports, VLAN %d: %llx\n", v, portmask);
866 priv->r->vlan_set_untagged(v, portmask);
867 }
868
869 /* Get tagged port memberships of this vlan */
870 priv->r->vlan_tables_read(v, &info);
871 info.tagged_ports &= (~(1ULL << port));
872 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
873 priv->r->vlan_set_tagged(v, &info);
874 }
875 mutex_unlock(&priv->reg_mutex);
876
877 return 0;
878 }
879
880 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
881 const unsigned char *addr, u16 vid)
882 {
883 struct rtl838x_switch_priv *priv = ds->priv;
884 u64 mac = ether_addr_to_u64(addr);
885 u32 key = rtl83xx_hash_key(priv, mac, vid);
886 struct rtl838x_l2_entry e;
887 u32 r[3];
888 u64 entry;
889 int idx = -1, err = 0, i;
890
891 mutex_lock(&priv->reg_mutex);
892 for (i = 0; i < 4; i++) {
893 entry = priv->r->read_l2_entry_using_hash(key, i, &e);
894 if (!e.valid) {
895 idx = (key << 2) | i;
896 break;
897 }
898 if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
899 idx = (key << 2) | i;
900 break;
901 }
902 }
903 if (idx >= 0) {
904 r[0] = 3 << 17 | port << 12; // Aging and port
905 r[0] |= vid;
906 r[1] = mac >> 16;
907 r[2] = (mac & 0xffff) << 12; /* rvid = 0 */
908 rtl83xx_write_hash(idx, r);
909 goto out;
910 }
911
912 /* Hash buckets full, try CAM */
913 for (i = 0; i < 64; i++) {
914 entry = priv->r->read_cam(i, &e);
915 if (!e.valid) {
916 if (idx < 0) /* First empty entry? */
917 idx = i;
918 break;
919 } else if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
920 pr_debug("Found entry in CAM\n");
921 idx = i;
922 break;
923 }
924 }
925 if (idx >= 0) {
926 r[0] = 3 << 17 | port << 12; // Aging
927 r[0] |= vid;
928 r[1] = mac >> 16;
929 r[2] = (mac & 0xffff) << 12; /* rvid = 0 */
930 rtl83xx_write_cam(idx, r);
931 goto out;
932 }
933 err = -ENOTSUPP;
934 out:
935 mutex_unlock(&priv->reg_mutex);
936 return err;
937 }
938
939 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
940 const unsigned char *addr, u16 vid)
941 {
942 struct rtl838x_switch_priv *priv = ds->priv;
943 u64 mac = ether_addr_to_u64(addr);
944 u32 key = rtl83xx_hash_key(priv, mac, vid);
945 struct rtl838x_l2_entry e;
946 u32 r[3];
947 u64 entry;
948 int idx = -1, err = 0, i;
949
950 pr_debug("In %s, mac %llx, vid: %d, key: %x\n", __func__, mac, vid, key);
951 mutex_lock(&priv->reg_mutex);
952 for (i = 0; i < 4; i++) {
953 entry = priv->r->read_l2_entry_using_hash(key, i, &e);
954 if (!e.valid)
955 continue;
956 if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
957 idx = (key << 2) | i;
958 break;
959 }
960 }
961
962 if (idx >= 0) {
963 r[0] = r[1] = r[2] = 0;
964 rtl83xx_write_hash(idx, r);
965 goto out;
966 }
967
968 /* Check CAM for spillover from hash buckets */
969 for (i = 0; i < 64; i++) {
970 entry = priv->r->read_cam(i, &e);
971 if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
972 idx = i;
973 break;
974 }
975 }
976 if (idx >= 0) {
977 r[0] = r[1] = r[2] = 0;
978 rtl83xx_write_cam(idx, r);
979 goto out;
980 }
981 err = -ENOENT;
982 out:
983 mutex_unlock(&priv->reg_mutex);
984 return err;
985 }
986
987 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
988 dsa_fdb_dump_cb_t *cb, void *data)
989 {
990 struct rtl838x_l2_entry e;
991 struct rtl838x_switch_priv *priv = ds->priv;
992 int i;
993 u32 fid;
994 u32 pkey;
995 u64 mac;
996
997 mutex_lock(&priv->reg_mutex);
998
999 for (i = 0; i < priv->fib_entries; i++) {
1000 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1001
1002 if (!e.valid)
1003 continue;
1004
1005 if (e.port == port) {
1006 fid = (i & 0x3ff) | (e.rvid & ~0x3ff);
1007 mac = ether_addr_to_u64(&e.mac[0]);
1008 pkey = rtl838x_hash(priv, mac << 12 | fid);
1009 fid = (pkey & 0x3ff) | (fid & ~0x3ff);
1010 pr_debug("-> mac %016llx, fid: %d\n", mac, fid);
1011 cb(e.mac, e.vid, e.is_static, data);
1012 }
1013 }
1014
1015 for (i = 0; i < 64; i++) {
1016 priv->r->read_cam(i, &e);
1017
1018 if (!e.valid)
1019 continue;
1020
1021 if (e.port == port)
1022 cb(e.mac, e.vid, e.is_static, data);
1023 }
1024
1025 mutex_unlock(&priv->reg_mutex);
1026 return 0;
1027 }
1028
1029 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1030 struct dsa_mall_mirror_tc_entry *mirror,
1031 bool ingress)
1032 {
1033 /* We support 4 mirror groups, one destination port per group */
1034 int group;
1035 struct rtl838x_switch_priv *priv = ds->priv;
1036
1037 pr_debug("In %s\n", __func__);
1038
1039 for (group = 0; group < 4; group++) {
1040 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1041 break;
1042 }
1043 if (group >= 4) {
1044 for (group = 0; group < 4; group++) {
1045 if (priv->mirror_group_ports[group] < 0)
1046 break;
1047 }
1048 }
1049
1050 if (group >= 4)
1051 return -ENOSPC;
1052
1053 pr_debug("Using group %d\n", group);
1054 mutex_lock(&priv->reg_mutex);
1055
1056 if (priv->family_id == RTL8380_FAMILY_ID) {
1057 /* Enable mirroring to port across VLANs (bit 11) */
1058 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, RTL838X_MIR_CTRL(group));
1059 } else {
1060 /* Enable mirroring to destination port */
1061 sw_w32((mirror->to_local_port << 4) | 1, RTL839X_MIR_CTRL(group));
1062 }
1063
1064 if (ingress && (priv->r->get_port_reg_be(priv->r->mir_spm(group)) & (1ULL << port))) {
1065 mutex_unlock(&priv->reg_mutex);
1066 return -EEXIST;
1067 }
1068 if ((!ingress) && (priv->r->get_port_reg_be(priv->r->mir_dpm(group)) & (1ULL << port))) {
1069 mutex_unlock(&priv->reg_mutex);
1070 return -EEXIST;
1071 }
1072
1073 if (ingress)
1074 priv->r->mask_port_reg_be(0, 1ULL << port, priv->r->mir_spm(group));
1075 else
1076 priv->r->mask_port_reg_be(0, 1ULL << port, priv->r->mir_dpm(group));
1077
1078 priv->mirror_group_ports[group] = mirror->to_local_port;
1079 mutex_unlock(&priv->reg_mutex);
1080 return 0;
1081 }
1082
1083 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1084 struct dsa_mall_mirror_tc_entry *mirror)
1085 {
1086 int group = 0;
1087 struct rtl838x_switch_priv *priv = ds->priv;
1088
1089 pr_debug("In %s\n", __func__);
1090 for (group = 0; group < 4; group++) {
1091 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1092 break;
1093 }
1094 if (group >= 4)
1095 return;
1096
1097 mutex_lock(&priv->reg_mutex);
1098 if (mirror->ingress) {
1099 /* Ingress, clear source port matrix */
1100 priv->r->mask_port_reg_be(1ULL << port, 0, priv->r->mir_spm(group));
1101 } else {
1102 /* Egress, clear destination port matrix */
1103 priv->r->mask_port_reg_be(1ULL << port, 0, priv->r->mir_dpm(group));
1104 }
1105
1106 if (!(sw_r32(priv->r->mir_spm(group)) || sw_r32(priv->r->mir_dpm(group)))) {
1107 priv->mirror_group_ports[group] = -1;
1108 sw_w32(0, priv->r->mir_ctrl(group));
1109 }
1110
1111 mutex_unlock(&priv->reg_mutex);
1112 }
1113
1114 const struct dsa_switch_ops rtl83xx_switch_ops = {
1115 .get_tag_protocol = rtl83xx_get_tag_protocol,
1116 .setup = rtl83xx_setup,
1117
1118 .phy_read = rtl83xx_dsa_phy_read,
1119 .phy_write = rtl83xx_dsa_phy_write,
1120
1121 .phylink_validate = rtl83xx_phylink_validate,
1122 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
1123 .phylink_mac_config = rtl83xx_phylink_mac_config,
1124 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
1125 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
1126
1127 .get_strings = rtl83xx_get_strings,
1128 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
1129 .get_sset_count = rtl83xx_get_sset_count,
1130
1131 .port_enable = rtl83xx_port_enable,
1132 .port_disable = rtl83xx_port_disable,
1133
1134 .get_mac_eee = rtl83xx_get_mac_eee,
1135 .set_mac_eee = rtl83xx_set_mac_eee,
1136
1137 .set_ageing_time = rtl83xx_set_l2aging,
1138 .port_bridge_join = rtl83xx_port_bridge_join,
1139 .port_bridge_leave = rtl83xx_port_bridge_leave,
1140 .port_stp_state_set = rtl83xx_port_stp_state_set,
1141 .port_fast_age = rtl83xx_fast_age,
1142
1143 .port_vlan_filtering = rtl83xx_vlan_filtering,
1144 .port_vlan_prepare = rtl83xx_vlan_prepare,
1145 .port_vlan_add = rtl83xx_vlan_add,
1146 .port_vlan_del = rtl83xx_vlan_del,
1147
1148 .port_fdb_add = rtl83xx_port_fdb_add,
1149 .port_fdb_del = rtl83xx_port_fdb_del,
1150 .port_fdb_dump = rtl83xx_port_fdb_dump,
1151
1152 .port_mirror_add = rtl83xx_port_mirror_add,
1153 .port_mirror_del = rtl83xx_port_mirror_del,
1154 };
1155
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