ipq40xx: only include ath10k-board-qca4019 for the generic subtarget
[openwrt/staging/chunkeey.git] / target / linux / ramips / dts / mt7620n.dtsi
1 /dts-v1/;
2
3 / {
4 #address-cells = <1>;
5 #size-cells = <1>;
6 compatible = "ralink,mt7620n-soc";
7
8 aliases {
9 spi0 = &spi0;
10 spi1 = &spi1;
11 serial0 = &uartlite;
12 };
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu@0 {
19 compatible = "mips,mips24KEc";
20 reg = <0>;
21 };
22 };
23
24 chosen {
25 bootargs = "console=ttyS0,57600";
26 };
27
28 cpuintc: cpuintc {
29 #address-cells = <0>;
30 #interrupt-cells = <1>;
31 interrupt-controller;
32 compatible = "mti,cpu-interrupt-controller";
33 };
34
35 palmbus: palmbus@10000000 {
36 compatible = "palmbus";
37 reg = <0x10000000 0x200000>;
38 ranges = <0x0 0x10000000 0x1FFFFF>;
39
40 #address-cells = <1>;
41 #size-cells = <1>;
42
43 sysc: sysc@0 {
44 compatible = "ralink,mt7620a-sysc", "ralink,rt3050-sysc", "syscon";
45 reg = <0x0 0x100>;
46 };
47
48 timer: timer@100 {
49 compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer";
50 reg = <0x100 0x20>;
51
52 interrupt-parent = <&intc>;
53 interrupts = <1>;
54 };
55
56 watchdog: watchdog@120 {
57 compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt";
58 reg = <0x120 0x10>;
59
60 resets = <&rstctrl 8>;
61 reset-names = "wdt";
62
63 interrupt-parent = <&intc>;
64 interrupts = <1>;
65 };
66
67 intc: intc@200 {
68 compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
69 reg = <0x200 0x100>;
70
71 resets = <&rstctrl 19>;
72 reset-names = "intc";
73
74 interrupt-controller;
75 #interrupt-cells = <1>;
76
77 interrupt-parent = <&cpuintc>;
78 interrupts = <2>;
79 };
80
81 memc: memc@300 {
82 compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
83 reg = <0x300 0x100>;
84
85 resets = <&rstctrl 20>;
86 reset-names = "mc";
87
88 interrupt-parent = <&intc>;
89 interrupts = <3>;
90 };
91
92 gpio0: gpio@600 {
93 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
94 reg = <0x600 0x34>;
95
96 resets = <&rstctrl 13>;
97 reset-names = "pio";
98
99 interrupt-parent = <&intc>;
100 interrupts = <6>;
101
102 gpio-controller;
103 #gpio-cells = <2>;
104
105 ngpios = <24>;
106 ralink,gpio-base = <0>;
107 ralink,register-map = [ 00 04 08 0c
108 20 24 28 2c
109 30 34 ];
110 };
111
112 gpio1: gpio@638 {
113 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
114 reg = <0x638 0x24>;
115
116 interrupt-parent = <&intc>;
117 interrupts = <6>;
118
119 gpio-controller;
120 #gpio-cells = <2>;
121
122 ngpios = <16>;
123 ralink,gpio-base = <24>;
124 ralink,register-map = [ 00 04 08 0c
125 10 14 18 1c
126 20 24 ];
127
128 status = "disabled";
129 };
130
131 gpio2: gpio@660 {
132 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
133 reg = <0x660 0x24>;
134
135 interrupt-parent = <&intc>;
136 interrupts = <6>;
137
138 gpio-controller;
139 #gpio-cells = <2>;
140
141 ngpios = <32>;
142 ralink,gpio-base = <40>;
143 ralink,register-map = [ 00 04 08 0c
144 10 14 18 1c
145 20 24 ];
146
147 status = "disabled";
148 };
149
150 gpio3: gpio@688 {
151 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
152 reg = <0x688 0x24>;
153
154 interrupt-parent = <&intc>;
155 interrupts = <6>;
156
157 gpio-controller;
158 #gpio-cells = <2>;
159
160 ngpios = <1>;
161 ralink,gpio-base = <72>;
162 ralink,register-map = [ 00 04 08 0c
163 10 14 18 1c
164 20 24 ];
165
166 status = "disabled";
167 };
168
169 i2c: i2c@900 {
170 compatible = "ralink,rt2880-i2c";
171 reg = <0x900 0x100>;
172
173 resets = <&rstctrl 16>;
174 reset-names = "i2c";
175
176 #address-cells = <1>;
177 #size-cells = <0>;
178
179 status = "disabled";
180
181 pinctrl-names = "default";
182 pinctrl-0 = <&i2c_pins>;
183 };
184
185 spi0: spi@b00 {
186 compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
187 reg = <0xb00 0x40>;
188
189 resets = <&rstctrl 18>;
190 reset-names = "spi";
191
192 #address-cells = <1>;
193 #size-cells = <0>;
194
195 status = "disabled";
196
197 pinctrl-names = "default";
198 pinctrl-0 = <&spi_pins>;
199 };
200
201 spi1: spi@b40 {
202 compatible = "ralink,rt2880-spi";
203 reg = <0xb40 0x60>;
204
205 resets = <&rstctrl 18>;
206 reset-names = "spi";
207
208 #address-cells = <1>;
209 #size-cells = <0>;
210
211 status = "disabled";
212
213 pinctrl-names = "default";
214 pinctrl-0 = <&spi_cs1>;
215 };
216
217 uartlite: uartlite@c00 {
218 compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
219 reg = <0xc00 0x100>;
220
221 resets = <&rstctrl 19>;
222 reset-names = "uartl";
223
224 interrupt-parent = <&intc>;
225 interrupts = <12>;
226
227 reg-shift = <2>;
228
229 pinctrl-names = "default";
230 pinctrl-0 = <&uartlite_pins>;
231 };
232
233 systick: systick@d00 {
234 compatible = "ralink,mt7620a-systick", "ralink,cevt-systick";
235 reg = <0xd00 0x10>;
236
237 resets = <&rstctrl 28>;
238 reset-names = "intc";
239
240 interrupt-parent = <&cpuintc>;
241 interrupts = <7>;
242 };
243 };
244
245 pinctrl: pinctrl {
246 compatible = "ralink,rt2880-pinmux";
247 pinctrl-names = "default";
248 pinctrl-0 = <&state_default>;
249
250 state_default: pinctrl0 {
251 };
252
253 ephy_pins: ephy {
254 ephy {
255 groups = "ephy";
256 function = "ephy";
257 };
258 };
259
260 spi_pins: spi_pins {
261 spi_pins {
262 groups = "spi";
263 function = "spi";
264 };
265 };
266
267 spi_cs1: spi1 {
268 spi1 {
269 groups = "spi refclk";
270 function = "spi refclk";
271 };
272 };
273
274 i2c_pins: i2c_pins {
275 i2c_pins {
276 groups = "i2c";
277 function = "i2c";
278 };
279 };
280
281 uartlite_pins: uartlite {
282 uart {
283 groups = "uartlite";
284 function = "uartlite";
285 };
286 };
287 };
288
289 rstctrl: rstctrl {
290 compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
291 #reset-cells = <1>;
292 };
293
294 clkctrl: clkctrl {
295 compatible = "ralink,rt2880-clock";
296 #clock-cells = <1>;
297 };
298
299 usbphy: usbphy {
300 compatible = "mediatek,mt7620-usbphy";
301 #phy-cells = <0>;
302
303 ralink,sysctl = <&sysc>;
304 resets = <&rstctrl 22 &rstctrl 25>;
305 reset-names = "host", "device";
306
307 clocks = <&clkctrl 22 &clkctrl 25>;
308 clock-names = "host", "device";
309 };
310
311 ethernet: ethernet@10100000 {
312 compatible = "mediatek,mt7620-eth";
313 reg = <0x10100000 0x10000>;
314
315 #address-cells = <1>;
316 #size-cells = <0>;
317
318 interrupt-parent = <&cpuintc>;
319 interrupts = <5>;
320
321 resets = <&rstctrl 21 &rstctrl 23>;
322 reset-names = "fe", "esw";
323
324 mediatek,switch = <&gsw>;
325 };
326
327 gsw: gsw@10110000 {
328 compatible = "mediatek,mt7620-gsw";
329 reg = <0x10110000 0x8000>;
330
331 resets = <&rstctrl 23>;
332 reset-names = "esw";
333
334 interrupt-parent = <&intc>;
335 interrupts = <17>;
336 };
337
338 ehci: ehci@101c0000 {
339 #address-cells = <1>;
340 #size-cells = <0>;
341 compatible = "generic-ehci";
342 reg = <0x101c0000 0x1000>;
343
344 interrupt-parent = <&intc>;
345 interrupts = <18>;
346
347 phys = <&usbphy>;
348 phy-names = "usb";
349
350 status = "disabled";
351
352 ehci_port1: port@1 {
353 reg = <1>;
354 #trigger-source-cells = <0>;
355 };
356 };
357
358 ohci: ohci@101c1000 {
359 #address-cells = <1>;
360 #size-cells = <0>;
361 compatible = "generic-ohci";
362 reg = <0x101c1000 0x1000>;
363
364 phys = <&usbphy>;
365 phy-names = "usb";
366
367 interrupt-parent = <&intc>;
368 interrupts = <18>;
369
370 status = "disabled";
371
372 ohci_port1: port@1 {
373 reg = <1>;
374 #trigger-source-cells = <0>;
375 };
376 };
377
378 wmac: wmac@10180000 {
379 compatible = "ralink,rt7620-wmac", "ralink,rt2880-wmac";
380 reg = <0x10180000 0x40000>;
381
382 interrupt-parent = <&cpuintc>;
383 interrupts = <6>;
384
385 ralink,eeprom = "soc_wmac.eeprom";
386 };
387 };