add new target 'oxnas'
authorJohn Crispin <john@openwrt.org>
Wed, 26 Nov 2014 09:00:08 +0000 (09:00 +0000)
committerJohn Crispin <john@openwrt.org>
Wed, 26 Nov 2014 09:00:08 +0000 (09:00 +0000)
This is the oxnas target previously developed at
http://gitorious.org/openwrt-oxnas
Basically, this consolidates the changes and addtionas from
http://github.org/kref/linux-oxnas
into a new OpenWrt hardware target 'oxnas' adding support for
 PLX Technology NAS7820/NAS7821/NAS7825/...
formally known as
 Oxford Semiconductor OXE810SE/OXE815/OX820/...

For now there are 4 supported boards:
Cloud Engines Pogoplug V3 (without PCIe)
 fully supported

Cloud Engines Pogoplug Pro (with PCIe)
 fully supported

MitraStar STG-212
 aka ZyXEL NSA-212,
 aka Medion Akoya P89625 / P89636 / P89626 / P89630,
 aka Medion MD 86407 / MD 86805 / MD 86517 / MD 86587
 fully supported, see http://wiki.openwrt.org/toh/medion/md86587

Shuttle KD-20
 partially supported (S-ATA driver lacks support for 2nd port)

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
SVN-Revision: 43388

54 files changed:
package/kernel/linux/modules/usb.mk
target/linux/oxnas/Makefile [new file with mode: 0644]
target/linux/oxnas/base-files.mk [new file with mode: 0644]
target/linux/oxnas/base-files/etc/board.d/01_leds [new file with mode: 0755]
target/linux/oxnas/base-files/etc/board.d/02_network [new file with mode: 0755]
target/linux/oxnas/base-files/etc/diag.sh [new file with mode: 0755]
target/linux/oxnas/base-files/lib/oxnas.sh [new file with mode: 0755]
target/linux/oxnas/base-files/lib/preinit/03_preinit_do_oxnas.sh [new file with mode: 0644]
target/linux/oxnas/base-files/lib/upgrade/platform.sh [new file with mode: 0644]
target/linux/oxnas/config-3.18 [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/boot/dts/ox820-kd20.dts [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-pro.dts [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-v3.dts [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/boot/dts/ox820-stg212.dts [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/boot/dts/ox820.dtsi [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/configs/ox820_defconfig [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/mach-oxnas/Kconfig [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile.boot [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/mach-oxnas/fiq.S [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/mach-oxnas/headsmp.S [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/mach-oxnas/hotplug.c [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/hardware.h [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/iomap.h [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/irqs.h [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/smp.h [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/timex.h [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/uncompress.h [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/utils.h [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/mach-oxnas/mach-ox820.c [new file with mode: 0644]
target/linux/oxnas/files/arch/arm/mach-oxnas/platsmp.c [new file with mode: 0644]
target/linux/oxnas/files/drivers/ata/sata_oxnas.c [new file with mode: 0644]
target/linux/oxnas/files/drivers/clk/clk-oxnas.c [new file with mode: 0644]
target/linux/oxnas/files/drivers/clocksource/oxnas_rps_timer.c [new file with mode: 0644]
target/linux/oxnas/files/drivers/irqchip/irq-rps.c [new file with mode: 0644]
target/linux/oxnas/files/drivers/mtd/nand/oxnas_nand.c [new file with mode: 0644]
target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c [new file with mode: 0644]
target/linux/oxnas/files/drivers/pinctrl/pinctrl-oxnas.c [new file with mode: 0644]
target/linux/oxnas/files/drivers/reset/reset-ox820.c [new file with mode: 0644]
target/linux/oxnas/files/drivers/usb/host/ehci-oxnas.c [new file with mode: 0644]
target/linux/oxnas/image/Makefile [new file with mode: 0644]
target/linux/oxnas/patches-3.18/010-arm_introduce-dma-fiq-irq-broadcast.patch [new file with mode: 0644]
target/linux/oxnas/patches-3.18/250-add-plxtech-vendor-prefix.patch [new file with mode: 0644]
target/linux/oxnas/patches-3.18/300-introduce-oxnas-platform.patch [new file with mode: 0644]
target/linux/oxnas/patches-3.18/310-oxnas-clocksource.patch [new file with mode: 0644]
target/linux/oxnas/patches-3.18/320-oxnas-irqchip.patch [new file with mode: 0644]
target/linux/oxnas/patches-3.18/330-oxnas-pinctrl.patch [new file with mode: 0644]
target/linux/oxnas/patches-3.18/340-oxnas-pcie.patch [new file with mode: 0644]
target/linux/oxnas/patches-3.18/350-oxnas-reset.patch [new file with mode: 0644]
target/linux/oxnas/patches-3.18/400-oxnas-nand.patch [new file with mode: 0644]
target/linux/oxnas/patches-3.18/500-oxnas-sata.patch [new file with mode: 0644]
target/linux/oxnas/patches-3.18/800-oxnas-ehci.patch [new file with mode: 0644]
target/linux/oxnas/patches-3.18/900-more-boards.patch [new file with mode: 0644]
target/linux/oxnas/profiles/100-Generic.mk [new file with mode: 0644]

index 74de4461fb0e2ed602933f6e6782eb1a8871599e..4cd3bf091ae86aecb0ef676737408001b0dd7519 100644 (file)
@@ -467,6 +467,23 @@ endef
 $(eval $(call KernelPackage,usb-dwc2))
 
 
+define KernelPackage/usb2-oxnas
+  TITLE:=OXNAS USB controller driver
+  DEPENDS:=@TARGET_oxnas +kmod-usb2
+  KCONFIG:=CONFIG_USB_EHCI_OXNAS
+  FILES:=$(LINUX_DIR)/drivers/usb/host/ehci-oxnas.ko
+  AUTOLOAD:=$(call AutoLoad,55,ehci-oxnas,1)
+  $(call AddDepends/usb)
+endef
+
+define KernelPackage/usb2-oxnas/description
+ This driver provides USB Device Controller support for the
+ EHCI USB host built-in to the PLXTECH NAS782x SoC
+endef
+
+$(eval $(call KernelPackage,usb2-oxnas))
+
+
 define KernelPackage/usb-acm
   TITLE:=Support for modems/isdn controllers
   KCONFIG:=CONFIG_USB_ACM
diff --git a/target/linux/oxnas/Makefile b/target/linux/oxnas/Makefile
new file mode 100644 (file)
index 0000000..67d45bc
--- /dev/null
@@ -0,0 +1,28 @@
+#
+# Copyright (C) 2013 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+include $(TOPDIR)/rules.mk
+
+ARCH:=arm
+BOARD:=oxnas
+BOARDNAME:=PLXTECH NAS782X
+DEVICE_TYPE:=nas
+FEATURES:=gpio nand pcie usb usbgadget ramdisk rtc squashfs
+CPU_TYPE:=mpcore
+
+MAINTAINER:=Daniel Golle <daniel@makrotopia.org>
+
+KERNEL_PATCHVER:=3.18
+
+include $(INCLUDE_DIR)/target.mk
+
+DEFAULT_PACKAGES += \
+       kmod-button-hotplug kmod-input-gpio-keys-polled kmod-leds-gpio          \
+       kmod-i2c-gpio uboot-envtools uboot-oxnas-ox820
+
+KERNELNAME:=zImage dtbs
+
+$(eval $(call BuildTarget))
diff --git a/target/linux/oxnas/base-files.mk b/target/linux/oxnas/base-files.mk
new file mode 100644 (file)
index 0000000..fdd2c71
--- /dev/null
@@ -0,0 +1,3 @@
+define Package/base-files/install-target
+       rm -f $(1)/etc/config/network
+endef
diff --git a/target/linux/oxnas/base-files/etc/board.d/01_leds b/target/linux/oxnas/base-files/etc/board.d/01_leds
new file mode 100755 (executable)
index 0000000..17e37cd
--- /dev/null
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+. /lib/functions/uci-defaults-new.sh
+. /lib/oxnas.sh
+
+board=$(oxnas_board_name)
+board_config_update
+
+case $board in
+       stg-212)
+               ucidef_set_led_default "power" "power" "zyxel:blue:status" "1"
+               ucidef_set_led_usbdev "usb" "USB" "$1" "1-1"
+               ;;
+       kd20)
+               ucidef_set_led_default "power" "power" "kd20:blue:status" "1"
+               ;;
+       pogoplugpro | pogoplugv3)
+               ucidef_set_led_default "power" "power" "pogoplug:blue:internal" "1"
+               ;;
+
+esac
+
+board_config_flush
+
+exit 0
diff --git a/target/linux/oxnas/base-files/etc/board.d/02_network b/target/linux/oxnas/base-files/etc/board.d/02_network
new file mode 100755 (executable)
index 0000000..3a10584
--- /dev/null
@@ -0,0 +1,12 @@
+#!/bin/sh
+
+. /lib/functions/uci-defaults-new.sh
+. /lib/functions/system.sh
+
+board_config_update
+
+ucidef_set_interface_lan "eth0"
+
+board_config_flush
+
+exit 0
diff --git a/target/linux/oxnas/base-files/etc/diag.sh b/target/linux/oxnas/base-files/etc/diag.sh
new file mode 100755 (executable)
index 0000000..ba42218
--- /dev/null
@@ -0,0 +1,35 @@
+#!/bin/sh
+# Copyright (C) 2009-2013 OpenWrt.org
+
+. /lib/functions/leds.sh
+. /lib/oxnas.sh
+
+get_status_led() {
+       case $(oxnas_board_name) in
+       stg212)
+               status_led="zyxel:blue:status"
+               ;;
+       kd20)
+               status_led="kd20:blue:status"
+               ;;
+       pogoplugpro | pogoplugv3)
+               status_led="pogoplug:blue:internal"
+               ;;
+       esac
+}
+
+set_state() {
+       get_status_led
+
+       case "$1" in
+       preinit)
+               status_led_blink_preinit
+               ;;
+       failsafe)
+               status_led_blink_failsafe
+               ;;
+       done)
+               status_led_on
+               ;;
+       esac
+}
diff --git a/target/linux/oxnas/base-files/lib/oxnas.sh b/target/linux/oxnas/base-files/lib/oxnas.sh
new file mode 100755 (executable)
index 0000000..1a04d55
--- /dev/null
@@ -0,0 +1,48 @@
+#!/bin/sh
+#
+# Copyright (C) 2013 OpenWrt.org
+#
+
+OXNAS_BOARD_NAME=
+OXNAS_MODEL=
+
+oxnas_board_detect() {
+       local machine
+       local name
+
+       machine=$(cat /proc/device-tree/model)
+
+       case "$machine" in
+       *"MitraStar Technology Corp. STG-212"*)
+               name="stg212"
+               ;;
+       *"Shuttle KD20"*)
+               name="kd20"
+               ;;
+       *"Pogoplug Pro"*)
+               name="pogoplugpro"
+               ;;
+       *"Pogoplug V3"*)
+               name="pogoplugv3"
+               ;;
+       esac
+
+       [ -z "$name" ] && name="unknown"
+
+       [ -z "$OXNAS_BOARD_NAME" ] && OXNAS_BOARD_NAME="$name"
+       [ -z "$OXNAS_MODEL" ] && OXNAS_MODEL="$machine"
+
+       [ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/"
+
+       echo "$OXNAS_BOARD_NAME" > /tmp/sysinfo/board_name
+       echo "$OXNAS_MODEL" > /tmp/sysinfo/model
+}
+
+oxnas_board_name() {
+       local name
+
+       [ -f /tmp/sysinfo/board_name ] && name=$(cat /tmp/sysinfo/board_name)
+       [ -z "$name" ] && name="unknown"
+
+       echo "$name"
+}
diff --git a/target/linux/oxnas/base-files/lib/preinit/03_preinit_do_oxnas.sh b/target/linux/oxnas/base-files/lib/preinit/03_preinit_do_oxnas.sh
new file mode 100644 (file)
index 0000000..ca7bce1
--- /dev/null
@@ -0,0 +1,9 @@
+#!/bin/sh
+
+do_oxnas() {
+       . /lib/oxnas.sh
+
+       oxnas_board_detect
+}
+
+boot_hook_add preinit_main do_oxnas
diff --git a/target/linux/oxnas/base-files/lib/upgrade/platform.sh b/target/linux/oxnas/base-files/lib/upgrade/platform.sh
new file mode 100644 (file)
index 0000000..8591c7d
--- /dev/null
@@ -0,0 +1,35 @@
+#
+# Copyright (C) 2014 OpenWrt.org
+#
+
+. /lib/oxnas.sh
+
+RAMFS_COPY_DATA=/lib/oxnas.sh
+
+platform_check_image() {
+       local board=$(oxnas_board_name)
+
+       [ "$ARGC" -gt 1 ] && return 1
+
+       nand_do_platform_check $board $1
+       return $?
+}
+
+platform_do_upgrade() {
+       if [ $$ -ne 1 ]; then
+               echo "not PID 1, upgrade aborted."
+               return 1;
+       fi
+       platform_do_upgrade_phase2 "$1" "$CONF_TAR" "$SAVE_CONFIG"
+}
+
+
+disable_watchdog() {
+       killall watchdog
+       ( ps | grep -v 'grep' | grep '/dev/watchdog' ) && {
+               echo 'Could not disable watchdog'
+               return 1
+       }
+}
+
+append sysupgrade_pre_upgrade disable_watchdog
diff --git a/target/linux/oxnas/config-3.18 b/target/linux/oxnas/config-3.18
new file mode 100644 (file)
index 0000000..4997dc1
--- /dev/null
@@ -0,0 +1,366 @@
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+# CONFIG_ARCH_HAS_SG_CHAIN is not set
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OXNAS=y
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_ARM=y
+# CONFIG_ARM_CPU_SUSPEND is not set
+CONFIG_ARM_GIC=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ATA=y
+# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
+CONFIG_AUTO_ZRELADDR=y
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=1
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_OF=y
+CONFIG_CLKSRC_RPS_TIMER=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="console=ttyS0,115200n8 earlyprintk=serial"
+CONFIG_COMMON_CLK=y
+# CONFIG_COMMON_CLK_PXA is not set
+CONFIG_COMPACTION=y
+CONFIG_CONSOLE_POLL=y
+CONFIG_COREDUMP=y
+CONFIG_CPU_32v6=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_ABRT_EV6=y
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_HAS_ASID=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_PABRT_V6=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_V6K=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_XZ=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+# CONFIG_DEBUG_LL_UART_8250 is not set
+CONFIG_DEBUG_LL_UART_NONE=y
+# CONFIG_DEBUG_LL_UART_PL01X is not set
+# CONFIG_DEBUG_UART_8250 is not set
+# CONFIG_DEBUG_UART_BCM63XX is not set
+# CONFIG_DEBUG_UART_PL01X is not set
+# CONFIG_DEBUG_USER is not set
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=8
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DIRECT_IO=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_CACHE_FIQ_BROADCAST=y
+# CONFIG_DMA_CACHE_RWFO is not set
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DNOTIFY=y
+CONFIG_DTC=y
+# CONFIG_DW_DMAC_CORE is not set
+# CONFIG_DW_DMAC_PCI is not set
+CONFIG_EARLY_PRINTK=y
+CONFIG_FIQ=y
+# CONFIG_FSL_EDMA is not set
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_NET_UTILS=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+# CONFIG_GPIO_SYSCON is not set
+CONFIG_GPIO_SYSFS=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_ARM_SCU=y
+CONFIG_HAVE_ARM_TWD=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_BPF_JIT=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZ4=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_HAVE_KERNEL_XZ=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SMP=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_UID16=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_LRO=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_INET_UDP_DIAG=y
+CONFIG_INPUT=y
+# CONFIG_INPUT_MISC is not set
+# CONFIG_INTEL_SOC_PMIC is not set
+CONFIG_IOMMU_HELPER=y
+CONFIG_IOMMU_SUPPORT=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_MULTICAST is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_BOOTP is not set
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_ISDN is not set
+# CONFIG_JFFS2_FS is not set
+CONFIG_JUMP_LABEL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KERNFS=y
+CONFIG_KGDB=y
+# CONFIG_KGDB_KDB is not set
+CONFIG_KGDB_SERIAL_CONSOLE=y
+# CONFIG_KGDB_TESTS is not set
+# CONFIG_LDM_DEBUG is not set
+CONFIG_LDM_PARTITION=y
+# CONFIG_LEDS_SYSCON is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+# CONFIG_LEDS_TRIGGER_NETDEV is not set
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+CONFIG_LIBFDT=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MACH_OX820=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAILBOX=y
+CONFIG_MDIO_BOARDINFO=y
+# CONFIG_MFD_AXP20X is not set
+CONFIG_MFD_CORE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MFD_VEXPRESS_SYSREG=y
+CONFIG_MIGHT_HAVE_PCI=y
+CONFIG_MIGRATION=y
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MODULE_STRIPPED is not set
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_OXNAS=y
+CONFIG_MTD_NAND_PLATFORM=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+# CONFIG_MTD_UBI_FASTMAP is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UIMAGE_SPLIT=y
+CONFIG_MULTI_IRQ_HANDLER=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+# CONFIG_NBPFAXI_DMA is not set
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NLS=y
+CONFIG_NO_BOOTMEM=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=2
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IOMMU=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_MTD=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_PACKET_DIAG=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+# CONFIG_PCIEASPM_DEBUG is not set
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_OXNAS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PHYLIB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_OXNAS=y
+CONFIG_PLXTECH_RPS=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_PPS=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_PRINTK_TIME=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PWM=y
+# CONFIG_PWM_FSL_FTM is not set
+CONFIG_PWM_SYSFS=y
+CONFIG_RAS=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RELAY=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_CONTROLLER_OXNAS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_CMOS is not set
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_SATA_OXNAS=y
+CONFIG_SCHED_HRTICK=y
+CONFIG_SCSI=y
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+CONFIG_SERIAL_EARLYCON=y
+# CONFIG_SERIAL_KGDB_NMI is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SOCK_DIAG=y
+CONFIG_STMMAC_DA=y
+CONFIG_STMMAC_DEBUG_FS=y
+CONFIG_STMMAC_ETH=y
+# CONFIG_STMMAC_PCI is not set
+CONFIG_STMMAC_PLATFORM=y
+CONFIG_STOP_MACHINE=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_SWIOTLB=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_TREE_RCU=y
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_XZ=y
+CONFIG_UBIFS_FS_ZLIB=y
+CONFIG_UID16=y
+CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h"
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+# CONFIG_USB_EHCI_HCD is not set
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_UHCI_HCD is not set
+CONFIG_USE_OF=y
+CONFIG_VECTORS_BASE=0xffff0000
+# CONFIG_VEXPRESS_CONFIG is not set
+# CONFIG_VEXPRESS_SYSCFG is not set
+# CONFIG_VFP is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_XPS=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA_FLAG=0
diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-kd20.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-kd20.dts
new file mode 100644 (file)
index 0000000..e7ee587
--- /dev/null
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2014 Daniel Golle <daniel@makrotopia.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include "ox820.dtsi"
+
+/ {
+       model = "Shuttle KD20";
+
+       chosen {
+               bootargs = "console=ttyS0,115200n8 earlyprintk=serial";
+       };
+
+       pcie-controller@47C00000 {
+               status = "okay";
+       };
+
+       uart@44200000 {
+               status = "okay";
+       };
+
+       sata@45900000 {
+               status = "okay";
+       };
+
+       nand@41000000 {
+               status = "okay";
+
+               partition@0 {
+                       label = "boot";
+                       reg = <0x00000000 0x00e00000>;
+                       /*read-only;*/
+               };
+
+               partition@e00000 {
+                       label = "ubi";
+                       reg = <0x00e00000 0x07200000>;
+               };
+       };
+
+       ethernet@40400000 {
+               status = "okay";
+               snps,phy-addr = <1>;
+               phy-mode = "rgmii-id";
+       };
+
+       ehci@40200100 {
+               status = "okay";
+       };
+
+       i2c-gpio {
+               compatible = "i2c-gpio";
+               gpios = <&GPIOB 9 0 &GPIOB 10 0>;
+               i2c-gpio,delay-us = <10>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               pcf8563: rtc@51 {
+                       compatible = "nxp,pcf8563";
+                       reg = <0x51>;
+               };
+       };
+
+       gpio-keys-polled {
+               compatible = "gpio-keys-polled";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               poll-interval = <100>;
+
+               power {
+                       label = "power";
+                       gpios = <&GPIOA 10 1>;
+                       linux,code = <116>;
+               };
+               reset {
+                       label = "reset";
+                       gpios = <&GPIOA 11 1>;
+                       linux,code = <0x198>;
+               };
+               eject1 {
+                       label = "eject1";
+                       gpios = <&GPIOA 5 1>;
+                       linux,code = <161>;
+               };
+               eject2 {
+                       label = "eject2";
+                       gpios = <&GPIOA 6 1>;
+                       linux,code = <162>;
+               };
+       };
+
+       gpio-leds {
+               compatible = "gpio-leds";
+               status {
+                       label = "kd20:blue:status";
+                       gpios = <&GPIOB 16 0>;
+               };
+               status2 {
+                       label = "kd20:red:status";
+                       gpios = <&GPIOB 17 0>;
+               };
+               hdd1blue {
+                       label = "kd20:blue:hdd1";
+                       gpios = <&GPIOA 27 0>;
+               };
+               hdd1red {
+                       label = "kd20:red:hdd1";
+                       gpios = <&GPIOB 4 0>;
+               };
+               hdd2blue {
+                       label = "kd20:blue:hdd2";
+                       gpios = <&GPIOB 6 0>;
+               };
+               hdd2red {
+                       label = "kd20:red:hdd2";
+                       gpios = <&GPIOB 7 0>;
+               };
+               usb {
+                       label = "kd20:blue:usb";
+                       gpios = <&GPIOB 8 0>;
+               };
+               buzzer {
+                       label = "kd20:buzzer";
+                       gpios = <&GPIOB 11 0>;
+               };
+       };
+
+       gpio-fan {
+               compatible = "gpio-fan";
+               gpios = <&GPIOA 2 1>;
+       };
+};
diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-pro.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-pro.dts
new file mode 100644 (file)
index 0000000..f3730c3
--- /dev/null
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include "ox820.dtsi"
+
+/ {
+       model = "Pogoplug Pro";
+
+       chosen {
+               bootargs = "console=ttyS0,115200n8 earlyprintk=serial";
+       };
+
+       pcie-controller@47C00000 {
+               status = "okay";
+       };
+
+       uart@44200000 {
+               status = "okay";
+       };
+
+       sata@45900000 {
+               status = "okay";
+       };
+
+       nand@41000000 {
+               status = "okay";
+
+               partition@0 {
+                       label = "boot";
+                       reg = <0x00000000 0x00e00000>;
+                       /*read-only;*/
+               };
+
+               partition@e00000 {
+                       label = "ubi";
+                       reg = <0x00e00000 0x07200000>;
+               };
+       };
+
+       ethernet@40400000 {
+               status = "okay";
+       };
+
+       ehci@40200100 {
+               status = "okay";
+       };
+
+       pinctrl {
+               leds {
+                       pinctrl_leds: leds-0 {
+                               plxtech,pins =
+                                       <0 2 0 0        /* MF_A2 */
+                                        1 16 0 0       /* MF_B16 */
+                                        1 17 0 0>;     /* MF_B17 */
+                       };
+               };
+       };
+
+       leds {
+               compatible = "gpio-leds";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_leds>;
+
+               blue {
+                       label = "pogoplug:blue:internal";
+                       gpios = <&GPIOA 2 0>;
+
+               };
+
+               orange {
+                       label = "pogoplug:orange:usr";
+                       gpios = <&GPIOB 16 1>;
+               };
+
+               green {
+                       label = "pogoplug:green:usr";
+                       gpios = <&GPIOB 17 1>;
+               };
+       };
+};
diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-v3.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-v3.dts
new file mode 100644 (file)
index 0000000..8029132
--- /dev/null
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2014 Daniel Golle <daniel@makrotopia.org>
+ * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include "ox820.dtsi"
+
+/ {
+       model = "Pogoplug V3";
+
+       chosen {
+               bootargs = "console=ttyS0,115200n8 earlyprintk=serial";
+       };
+
+       uart@44200000 {
+               status = "okay";
+       };
+
+       sata@45900000 {
+               status = "okay";
+       };
+
+       nand@41000000 {
+               status = "okay";
+
+               partition@0 {
+                       label = "boot";
+                       reg = <0x00000000 0x00e00000>;
+                       /*read-only;*/
+               };
+
+               partition@e00000 {
+                       label = "ubi";
+                       reg = <0x00e00000 0x07200000>;
+               };
+       };
+
+       ethernet@40400000 {
+               status = "okay";
+       };
+
+       ehci@40200100 {
+               status = "okay";
+       };
+
+       pinctrl {
+               leds {
+                       pinctrl_leds: leds-0 {
+                               plxtech,pins =
+                                       <0 2 0 0        /* MF_A2 */
+                                        1 16 0 0       /* MF_B16 */
+                                        1 17 0 0>;     /* MF_B17 */
+                       };
+               };
+       };
+
+       leds {
+               compatible = "gpio-leds";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_leds>;
+
+               blue {
+                       label = "pogoplug:blue:internal";
+                       gpios = <&GPIOA 2 0>;
+               };
+
+               orange {
+                       label = "pogoplug:orange:usr";
+                       gpios = <&GPIOB 16 1>;
+               };
+
+               green {
+                       label = "pogoplug:green:usr";
+                       gpios = <&GPIOB 17 1>;
+               };
+       };
+
+};
diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-stg212.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-stg212.dts
new file mode 100644 (file)
index 0000000..5d83806
--- /dev/null
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2013 OpenWrt.org
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "ox820.dtsi"
+
+/ {
+       model = "MitraStar Technology Corp. STG-212";
+
+       chosen {
+               bootargs = "console=ttyS0,115200n8 earlyprintk=serial";
+       };
+
+       uart@44200000 {
+               status = "okay";
+       };
+
+       sata@45900000 {
+               status = "okay";
+       };
+
+       nand@41000000 {
+               status = "okay";
+
+               partition@0 {
+                       label = "boot";
+                       reg = <0x00000000 0x00e00000>;
+                       /*read-only;*/
+               };
+
+               partition@e00000 {
+                       label = "ubi";
+                       reg = <0x00e00000 0x07200000>;
+               };
+       };
+
+       ethernet@40400000 {
+               status = "okay";
+       };
+
+       ehci@40200100 {
+               status = "okay";
+       };
+
+       gpio-keys-polled {
+               compatible = "gpio-keys-polled";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               poll-interval = <100>;
+
+               reset {
+                       label = "reset";
+                       gpios = <&GPIOB 11 1>;
+                       linux,code = <0x198>;
+               };
+               copy {
+                       label = "copy";
+                       gpios = <&GPIOB 13 1>;
+                       linux,code = <0x85>;
+               };
+       };
+
+       gpio-leds {
+               compatible = "gpio-leds";
+               status {
+                       label = "zyxel:blue:status";
+                       gpios = <&GPIOB 5 0>;
+               };
+               status2 {
+                       label = "zyxel:red:status";
+                       gpios = <&GPIOB 6 1>;
+               };
+               copy {
+                       label = "zyxel:orange:copy";
+                       gpios = <&GPIOB 8 1>;
+               };
+       };
+
+       i2c-gpio {
+               compatible = "i2c-gpio";
+               gpios = <&GPIOB 9 0 &GPIOB 10 0>;
+               i2c-gpio,delay-us = <10>;
+       };
+
+};
diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820.dtsi b/target/linux/oxnas/files/arch/arm/boot/dts/ox820.dtsi
new file mode 100644 (file)
index 0000000..0a643a4
--- /dev/null
@@ -0,0 +1,342 @@
+/*
+ * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+       compatible = "plxtech,nas7820", "plxtech,nas782x";
+       interrupt-parent = <&gic>;
+
+       aliases {
+               serial0 = &uart0;
+               /* alias to determine bank index */
+               gpio0 = &GPIOA;
+               gpio1 = &GPIOB;
+
+               ethernet0 = &gmac;
+       };
+
+       cpus {
+               cpu@0 {
+                       compatible = "arm,arm11mpcore";
+               };
+               cpu@1 {
+                       compatible = "arm,arm11mpcore";
+               };
+       };
+
+       gic: gic@47001000 {
+               compatible = "arm,arm11mp-gic";
+               interrupt-controller;
+               #interrupt-cells = <3>;
+               reg = <0x47001000 0x1000>,
+                     <0x47000100 0x0100>;
+       };
+
+       rst: reset-controller@44E00034 {
+               compatible = "plxtech,nas782x-reset";
+               #reset-cells = <1>;
+               reg = <0x44E00034 0x8>; /* currently not used */
+       };
+
+       rps: rps@44400000 {
+               compatible = "plxtech,nas782x-rps";
+               interrupt-controller;
+               #interrupt-cells = <1>;
+               reg = <0x44400000 0x14>;
+               interrupts = <0 5 0x304>;
+       };
+
+       /* external oscillator */
+       osc: oscillator {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency  = <25000000>;
+       };
+
+       sysclk: sysclk {
+               compatible = "fixed-factor-clock";
+               #clock-cells = <0>;
+               clock-div = <4>;
+               clock-mult = <1>;
+               clocks = <&osc>;
+       };
+
+       plla: plla@44e001f0 {
+               compatible = "plxtech,nas782x-plla";
+               #clock-cells = <0>;
+               clocks = <&osc>;
+               reg = <0x44e001f0 0x10>;
+       };
+
+       pllb: pllb@44f001f0 {
+               compatible = "plxtech,nas782x-pllb";
+               #clock-cells = <0>;
+               clocks = <&osc>;
+               reg = <0x44f001f0 0x10>;
+               resets = <&rst 31>;
+       };
+
+       stdclk: stdclk {
+               compatible = "plxtech,nas782x-stdclk";
+               #clock-cells = <1>;
+               clocks = <&osc>;
+       };
+
+       twdclk: twdclk {
+               compatible = "fixed-factor-clock";
+               #clock-cells = <0>;
+               clock-div = <2>;
+               clock-mult = <1>;
+               clocks = <&plla>;
+       };
+
+       gmacclk: gmacclk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency  = <125000000>;
+       };
+
+       pinctrl {
+               /* act as a simple bus, so children will be probed automatically */
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "plxtech,nas782x-pinctrl", "simple-bus";
+               ranges;
+
+               plxtech,mux-mask = <
+                        0xFFFFFFFF 0xCC0FFDF9 0xFC000E60 0x0F03F7E0 0xF00C0FE0
+                        0x0003FFFF 0x00037FFF 0x0003FFF8 0x00000F00 0x0003F7F3
+                       >;
+
+               GPIOA: gpio@44000000 {
+                       compatible = "plxtech,nas782x-gpio";
+                       reg = <0x44000000 0x100>, <0x44E00000 0x200>;
+                       interrupts = <0 21 0x304>;
+                       #gpio-cells = <2>;
+                       gpio-controller;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       #gpio-lines = <32>; /* real gpio pin count */
+               };
+
+               GPIOB: gpio@44100000 {
+                       compatible = "plxtech,nas782x-gpio";
+                       reg = <0x44100000 0x100>, <0x44F00000 0x200>;
+                       interrupts = <0 22 0x304>;
+                       #gpio-cells = <2>;
+                       gpio-controller;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       #gpio-lines = <18>; /* real gpio pin count */
+               };
+
+               uart0 {
+                       pinctrl_uart0: uart0-0 {
+                               plxtech,pins =
+                                       <0 30 5 0       /* MF_A30 PINMUX_ALT PINMUX_UARTA_SIN */
+                                        0 31 5 0>;     /* MF_A31 PINMUX_ALT PINMUX_UARTA_SOUT */
+                       };
+               };
+
+               gmac0 {
+                       pinctrl_gmac0: gmac0-0 {
+                               plxtech,pins =
+                                       <0 3 1 0        /* MF_A3 PINMUX_2 PINMUX_MACA_MDC */
+                                        0 4 1 0>;      /* MF_A4 PINMUX_2 PINMUX_MACA_MDIO */
+                       };
+               };
+
+               nand0 {
+                       pinctrl_nand0: nand0-0 {
+                               plxtech,pins =
+                                       <0 12 1 0       /* MF_A12 PINMUX_2 PINMUX_STATIC_DATA0 */
+                                        0 13 1 0       /* MF_A13 PINMUX_2 PINMUX_STATIC_DATA1 */
+                                        0 14 1 0       /* MF_A14 PINMUX_2 PINMUX_STATIC_DATA2 */
+                                        0 15 1 0       /* MF_A15 PINMUX_2 PINMUX_STATIC_DATA3 */
+                                        0 16 1 0       /* MF_A16 PINMUX_2 PINMUX_STATIC_DATA4 */
+                                        0 17 1 0       /* MF_A17 PINMUX_2 PINMUX_STATIC_DATA5 */
+                                        0 18 1 0       /* MF_A18 PINMUX_2 PINMUX_STATIC_DATA6 */
+                                        0 19 1 0       /* MF_A19 PINMUX_2 PINMUX_STATIC_DATA7 */
+
+                                        0 20 1 0       /* MF_A20 PINMUX_2 PINMUX_STATIC_NWE */
+                                        0 21 1 0       /* MF_A21 PINMUX_2 PINMUX_STATIC_NOE */
+                                        0 22 1 0       /* MF_A22 PINMUX_2 PINMUX_STATIC_NCS */
+                                        0 23 1 0       /* MF_A23 PINMUX_2 PINMUX_STATIC_ADDR18 */
+                                        0 24 1 0>;     /* MF_A24 PINMUX_2 PINMUX_STATIC_ADDR19 */
+                       };
+               };
+       };
+
+       pcie-controller@47C00000 {
+               compatible = "plxtech,nas782x-pcie";
+               device_type = "pci";
+               #address-cells = <3>;
+               #size-cells = <2>;
+
+               /*              flag & space    bus address     host address    size */
+               ranges = <      0x82000000      0 0x48000000    0x48000000      0 0x2000000
+                               0xC2000000      0 0x4A000000    0x4A000000      0 0x1E00000
+                               0x81000000      0 0x4BE00000    0x4BE00000      0 0x0100000
+                               0x80000000      0 0x4BF00000    0x4BF00000      0 0x0100000>;
+
+               bus-range = <0x00 0x7f>;
+
+               /*      cfg                     inbound translator      phy*/
+               reg =   <0x47C00000 0x1000>,    <0x47D00000 0x100>,      <0x44A00000 0x10>;
+
+               #interrupt-cells = <1>;
+               /* wild card mask, match all bus address & interrupt specifier */
+               /* format: bus address mask, interrupt specifier mask */
+               /* each bit 1 means need match, 0 means ignored when match */
+               interrupt-map-mask = <0 0 0 0>;
+               /* format: a list of: bus address, interrupt specifier,
+                * parent interrupt controller & specifier */
+               interrupt-map = <0 0 0 0 &gic 0 19 0x304>;
+
+               gpios = <&GPIOB 12 0>;
+               clocks = <&stdclk 8>, <&pllb>;
+               clock-names = "pcie", "busclk";
+               resets = <&rst 7>, <&rst 14>;
+               reset-names = "pcie", "phy";
+
+               plxtech,pcie-hcsl-bit = <2>;
+               plxtech,pcie-ctrl-offset = <0x120>;
+               plxtech,pcie-outbound-offset = <0x138>;
+               status = "disabled";
+       };
+
+       pcie-controller@47E00000 {
+               compatible = "plxtech,nas782x-pcie";
+               device_type = "pci";
+               #address-cells = <3>;
+               #size-cells = <2>;
+
+               /*              flag & space    bus address     host address    size */
+               ranges = <      0x82000000      0 0x4C000000    0x4C000000      0 0x2000000
+                               0xC2000000      0 0x4E000000    0x4E000000      0 0x1E00000
+                               0x81000000      0 0x4FE00000    0x4FE00000      0 0x0100000
+                               0x80000000      0 0x4FF00000    0x4FF00000      0 0x0100000>;
+
+               bus-range = <0x80 0xff>;
+
+               /*      cfg                     inbound translator      phy*/
+               reg =   <0x47E00000 0x1000>,    <0x47F00000 0x100>,     <0x44A00000 0x10>;
+
+               #interrupt-cells = <1>;
+               /* wild card mask, match all bus address & interrupt specifier */
+               /* format: bus address mask, interrupt specifier mask */
+               /* each bit 1 means need match, 0 means ignored when match */
+               interrupt-map-mask = <0 0 0 0>;
+               /* format: a list of: bus address, interrupt specifier,
+                * parent interrupt controller & specifier */
+               interrupt-map = <0 0 0 0 &gic 0 20 0x304>;
+
+               /* gpios = <&GPIOB 12 0>; */
+               clocks = <&stdclk 11>, <&pllb>;
+               clock-names = "pcie", "busclk";
+               resets = <&rst 23>, <&rst 14>;
+               reset-names = "pcie", "phy";
+
+               plxtech,pcie-hcsl-bit = <3>;
+               plxtech,pcie-ctrl-offset = <0x124>;
+               plxtech,pcie-outbound-offset = <0x174>;
+               status = "disabled";
+       };
+
+       local-timer@47000600 {
+               compatible = "arm,arm11mp-twd-timer";
+               reg = <0x47000600 0x20>;
+               interrupts = <1 13 0x304>;      /* percpu, irq 29, cpu mask 3, level high */
+               clocks = <&twdclk>;
+       };
+
+       watchdog@47000620 {
+               compatible = "mpcore_wdt";
+               reg = <0x47000620 0x20>;
+               interrupts = <1 14 0x304>;      /* percpu, irq 30, cpu mask 3, level high */
+               clocks = <&twdclk>;
+       };
+
+       timer@44400200 {
+               compatible = "plxtech,nas782x-rps-timer";
+               reg = <0x44400200 0x40>;
+               clocks = <&sysclk>;
+       };
+
+       uart0: uart@44200000 {
+               compatible = "ns16550a";
+               reg = <0x44200000 0x100>;
+               clock-frequency = <6250000>;
+               interrupts = <0 23 0x304>;
+               reg-shift = <0>;
+               fifo-size = <16>;
+               reg-io-width = <1>;
+               current-speed = <115200>;
+               no-loopback-test;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_uart0>;
+               status = "disabled";
+       };
+
+       sata@45900000 {
+               compatible = "plxtech,nas782x-sata";
+                       /*      port            sgdma           core    */
+               reg = <0x45900000 0x100>, <0x459B0000 0x10>, <0x459E0000 0x2000>,
+                       /*      phy             descriptors (optional)  */
+                       <0x44900000 0x0C>, <0x50000000 0x1000>;
+               interrupts = <0 18 0x304>;
+               clocks = <&stdclk 4>;
+               resets = <&rst 11>, <&rst 12>, <&rst 13>;
+               reset-names = "sata", "link", "phy";
+               status = "disabled";
+       };
+
+       nand@41000000 {
+               compatible = "plxtech,nand-nas782x", "gen_nand";
+               reg = <0x41000000 0x100000>, <0x41C00000 0x20>;
+               nand-ecc-mode = "soft";
+               clocks = <&stdclk 9>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_nand0>;
+               resets = <&rst 15>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               status = "disabled";
+       };
+
+       gmac: ethernet@40400000 {
+               compatible = "plxtech,nas782x-gmac", "snps,dwmac";
+               reg = <0x40400000 0x2000>;
+               interrupts = <0 8 0x304>, <0 17 0x304>;
+               interrupt-names = "macirq", "eth_wake_irq";
+               mac-address = [000000000000]; /* Filled in by U-Boot */
+               phy-mode = "rgmii";
+               clocks = <&stdclk 7>, <&gmacclk>;
+               clock-names = "gmac", "stmmaceth";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_gmac0>;
+               resets = <&rst 6>;
+               status = "disabled";
+       };
+
+       ehci@40200100 {
+               compatible = "plxtech,nas782x-ehci";
+               reg = <0x40200100 0xf00>;
+               interrupts = <0 7 0x304>;
+               clocks = <&stdclk 6>, <&pllb>, <&stdclk 12>;
+               clock-names = "usb", "refsrc", "phyref";
+               resets = <&rst 4>, <&rst 5>, <&rst 26>;
+               reset-names = "host", "phya", "phyb";
+               /* Otherwise ref300 is used, which is derived from sata phy
+                * in that case, usb depends on sata initialization */
+               /* FIXME: how to make this dependency explicit ? */
+               plxtch,ehci_use_pllb;
+               status = "disabled";
+       };
+};
diff --git a/target/linux/oxnas/files/arch/arm/configs/ox820_defconfig b/target/linux/oxnas/files/arch/arm/configs/ox820_defconfig
new file mode 100644 (file)
index 0000000..bb0a9d6
--- /dev/null
@@ -0,0 +1,104 @@
+CONFIG_CROSS_COMPILE="arm-linux-gnueabi-"
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_CGROUPS=y
+CONFIG_NAMESPACES=y
+CONFIG_EMBEDDED=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_JUMP_LABEL=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_ARCH_OXNAS=y
+# CONFIG_DMA_CACHE_RWFO is not set
+CONFIG_DMA_CACHE_FIQ_BROADCAST=y
+CONFIG_PCI=y
+CONFIG_PCI_OXNAS=y
+CONFIG_SMP=y
+# CONFIG_SMP_ON_UP is not set
+CONFIG_NR_CPUS=2
+CONFIG_HOTPLUG_CPU=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_UACCESS_WITH_MEMCPY=y
+CONFIG_USE_OF=y
+CONFIG_BINFMT_MISC=y
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IPV6=y
+CONFIG_CFG80211=y
+CONFIG_MAC80211=y
+CONFIG_MAC80211_RC_PID=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_OXNAS=y
+CONFIG_MTD_UBI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_ATA=y
+CONFIG_SATA_OXNAS=y
+CONFIG_NETDEVICES=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_DEBUG_FS=y
+CONFIG_STMMAC_DA=y
+CONFIG_ATH_CARDS=y
+CONFIG_ATH9K=y
+CONFIG_ATH9K_LEGACY_RATE_CONTROL=y
+# CONFIG_RTL_CARDS is not set
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_OXNAS=y
+CONFIG_USB_STORAGE=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_COMMON_CLK_DEBUG=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=m
+CONFIG_NTFS_RW=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_UBIFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+CONFIG_PRINTK_TIME=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_UART_8250=y
+CONFIG_DEBUG_UART_PHYS=0x44200000
+CONFIG_DEBUG_UART_VIRT=0xF0000000
+CONFIG_DEBUG_UART_8250_SHIFT=0
+CONFIG_EARLY_PRINTK=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/Kconfig b/target/linux/oxnas/files/arch/arm/mach-oxnas/Kconfig
new file mode 100644 (file)
index 0000000..eb96f1b
--- /dev/null
@@ -0,0 +1,24 @@
+choice
+       prompt "Oxnas platform type"
+       default MACH_OXNAS
+       depends on ARCH_OXNAS
+
+config MACH_OX820
+       bool "Generic NAS7820 Support"
+       select ARM_GIC
+       select GENERIC_CLOCKEVENTS
+       select CPU_V6K
+       select HAVE_ARM_SCU if SMP
+       select HAVE_ARM_TWD if SMP
+       select HAVE_SMP
+       select PLXTECH_RPS
+       select CLKSRC_OF
+       select CLKSRC_RPS_TIMER
+       select USB_ARCH_HAS_EHCI
+       select PINCTRL_OXNAS
+       select PINCTRL
+       select RESET_CONTROLLER_OXNAS
+       help
+         Include support for the ox820 platform.
+
+endchoice
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile b/target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile
new file mode 100644 (file)
index 0000000..6862c34
--- /dev/null
@@ -0,0 +1,8 @@
+#
+# Makefile for the linux kernel.
+#
+
+obj-$(CONFIG_MACH_OX820)               += mach-ox820.o
+obj-$(CONFIG_SMP)                      += platsmp.o headsmp.o
+obj-$(CONFIG_DMA_CACHE_FIQ_BROADCAST)  += fiq.o
+obj-$(CONFIG_HOTPLUG_CPU)              += hotplug.o
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile.boot b/target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile.boot
new file mode 100644 (file)
index 0000000..b52e473
--- /dev/null
@@ -0,0 +1,2 @@
+   zreladdr-y  += 0x60008000
+params_phys-y  := 0x60000100
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/fiq.S b/target/linux/oxnas/files/arch/arm/mach-oxnas/fiq.S
new file mode 100644 (file)
index 0000000..6acd5a7
--- /dev/null
@@ -0,0 +1,87 @@
+/*
+ *  Copyright (C) 2012 Gateworks Corporation
+ *      Chris Lang <clang@gateworks.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/asm-offsets.h>
+
+#define D_CACHE_LINE_SIZE 32
+
+       .text
+
+/*
+ * R8  - DMA Start Address
+ * R9  - DMA Length
+ * R10 - DMA Direction
+ * R11 - DMA type
+ * R12 - fiq_buffer Address
+*/
+
+       .global ox820_fiq_end
+ENTRY(ox820_fiq_start)
+       str     r8, [r13]
+
+       ldmia   r12, {r8, r9, r10}
+       and     r11, r10, #0x3000000
+       and     r10, r10, #0xff
+
+       teq     r11, #0x1000000
+       beq     ox820_dma_map_area
+       teq     r11, #0x2000000
+       beq     ox820_dma_unmap_area
+       /* fall through */
+ox820_dma_flush_range:
+       bic     r8, r8, #D_CACHE_LINE_SIZE - 1
+1:
+       mcr     p15, 0, r8, c7, c14, 1          @ clean & invalidate D line
+       add     r8, r8, #D_CACHE_LINE_SIZE
+       cmp     r8, r9
+       blo     1b
+       /* fall through */
+ox820_fiq_exit:
+       mov     r8, #0
+       str     r8, [r12, #8]
+       mcr     p15, 0, r8, c7, c10, 4          @ drain write buffer
+       subs    pc, lr, #4
+
+ox820_dma_map_area:
+       add     r9, r9, r8
+       teq     r10, #DMA_FROM_DEVICE
+       beq     ox820_dma_inv_range
+       teq     r10, #DMA_TO_DEVICE
+       bne     ox820_dma_flush_range
+       /* fall through */
+ox820_dma_clean_range:
+       bic     r8, r8, #D_CACHE_LINE_SIZE - 1
+1:
+       mcr     p15, 0, r8, c7, c10, 1          @ clean D line
+       add     r8, r8, #D_CACHE_LINE_SIZE
+       cmp     r8, r9
+       blo     1b
+       b       ox820_fiq_exit
+
+ox820_dma_unmap_area:
+       add     r9, r9, r8
+       teq     r10, #DMA_TO_DEVICE
+       beq     ox820_fiq_exit
+       /* fall through */
+ox820_dma_inv_range:
+       tst     r8, #D_CACHE_LINE_SIZE - 1
+       bic     r8, r8, #D_CACHE_LINE_SIZE - 1
+       mcrne   p15, 0, r8, c7, c10, 1          @ clean D line
+       tst     r9, #D_CACHE_LINE_SIZE - 1
+       bic     r9, r9, #D_CACHE_LINE_SIZE - 1
+       mcrne   p15, 0, r9, c7, c14, 1          @ clean & invalidate D line
+1:
+       mcr     p15, 0, r8, c7, c6, 1           @ invalidate D line
+       add     r8, r8, #D_CACHE_LINE_SIZE
+       cmp     r8, r9
+       blo     1b
+       b       ox820_fiq_exit
+
+ox820_fiq_end:
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/headsmp.S b/target/linux/oxnas/files/arch/arm/mach-oxnas/headsmp.S
new file mode 100644 (file)
index 0000000..a63edae
--- /dev/null
@@ -0,0 +1,27 @@
+/*
+ *  linux/arch/arm/mach-ox820/headsmp.S
+ *
+ *  Copyright (c) 2003 ARM Limited
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+       __INIT
+
+/*
+ * OX820 specific entry point for secondary CPUs.
+ */
+ENTRY(ox820_secondary_startup)
+       mov r4, #0
+       /* invalidate both caches and branch target cache */
+       mcr p15, 0, r4, c7, c7, 0
+       /*
+        * we've been released from the holding pen: secondary_stack
+        * should now contain the SVC stack for this core
+        */
+       b       secondary_startup
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/hotplug.c b/target/linux/oxnas/files/arch/arm/mach-oxnas/hotplug.c
new file mode 100644 (file)
index 0000000..861beee
--- /dev/null
@@ -0,0 +1,112 @@
+/*
+ *  linux/arch/arm/mach-realview/hotplug.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+
+#include <asm/cp15.h>
+#include <asm/smp_plat.h>
+#include <mach/smp.h>
+
+static inline void cpu_enter_lowpower(void)
+{
+       unsigned int v;
+
+       asm volatile(
+       "       mcr     p15, 0, %1, c7, c5, 0\n"
+       "       mcr     p15, 0, %1, c7, c10, 4\n"
+       /*
+        * Turn off coherency
+        */
+       "       mrc     p15, 0, %0, c1, c0, 1\n"
+       "       bic     %0, %0, #0x20\n"
+       "       mcr     p15, 0, %0, c1, c0, 1\n"
+       "       mrc     p15, 0, %0, c1, c0, 0\n"
+       "       bic     %0, %0, %2\n"
+       "       mcr     p15, 0, %0, c1, c0, 0\n"
+         : "=&r" (v)
+         : "r" (0), "Ir" (CR_C)
+         : "cc");
+}
+
+static inline void cpu_leave_lowpower(void)
+{
+       unsigned int v;
+
+       asm volatile("mrc       p15, 0, %0, c1, c0, 0\n"
+       "       orr     %0, %0, %1\n"
+       "       mcr     p15, 0, %0, c1, c0, 0\n"
+       "       mrc     p15, 0, %0, c1, c0, 1\n"
+       "       orr     %0, %0, #0x20\n"
+       "       mcr     p15, 0, %0, c1, c0, 1\n"
+         : "=&r" (v)
+         : "Ir" (CR_C)
+         : "cc");
+}
+
+static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
+{
+       /*
+        * there is no power-control hardware on this platform, so all
+        * we can do is put the core into WFI; this is safe as the calling
+        * code will have already disabled interrupts
+        */
+       for (;;) {
+               /*
+                * here's the WFI
+                */
+               asm(".word      0xe320f003\n"
+                   :
+                   :
+                   : "memory", "cc");
+
+               if (read_pen_release() == cpu_logical_map(cpu)) {
+                       /*
+                        * OK, proper wakeup, we're done
+                        */
+                       break;
+               }
+
+               /*
+                * Getting here, means that we have come out of WFI without
+                * having been woken up - this shouldn't happen
+                *
+                * Just note it happening - when we're woken, we can report
+                * its occurrence.
+                */
+               (*spurious)++;
+       }
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void __ref ox820_cpu_die(unsigned int cpu)
+{
+       int spurious = 0;
+
+       /*
+        * we're ready for shutdown now, so do it
+        */
+       cpu_enter_lowpower();
+       platform_do_lowpower(cpu, &spurious);
+
+       /*
+        * bring this CPU back into the world of cache
+        * coherency, and then restore interrupts
+        */
+       cpu_leave_lowpower();
+
+       if (spurious)
+               pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
+}
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/hardware.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/hardware.h
new file mode 100644 (file)
index 0000000..caae772
--- /dev/null
@@ -0,0 +1,233 @@
+/*
+ * arch/arm/mach-0x820/include/mach/hardware.h
+ *
+ * Copyright (C) 2009 Oxford Semiconductor Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <linux/io.h>
+#include <mach/iomap.h>
+
+/*
+ * Location of flags and vectors in SRAM for controlling the booting of the
+ * secondary ARM11 processors.
+ */
+
+#define OXNAS_SCU_BASE_VA              OXNAS_PERCPU_BASE_VA
+#define OXNAS_GICN_BASE_VA(n)          (OXNAS_PERCPU_BASE_VA + 0x200 + n*0x100)
+
+#define HOLDINGPEN_CPU                 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc8)
+#define HOLDINGPEN_LOCATION            IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc4)
+
+/**
+ * System block reset and clock control
+ */
+#define SYS_CTRL_PCI_STAT              IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x20)
+#define SYSCTRL_CLK_STAT               IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x24)
+#define SYS_CTRL_CLK_SET_CTRL          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x2C)
+#define SYS_CTRL_CLK_CLR_CTRL          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x30)
+#define SYS_CTRL_RST_SET_CTRL          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x34)
+#define SYS_CTRL_RST_CLR_CTRL          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x38)
+
+#define SYS_CTRL_PLLSYS_CTRL           IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x48)
+#define SYS_CTRL_CLK_CTRL              IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x64)
+#define SYS_CTRL_PLLSYS_KEY_CTRL       IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x6C)
+#define SYS_CTRL_GMAC_CTRL             IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x78)
+#define SYS_CTRL_GMAC_DELAY_CTRL       IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x100)
+
+/* Scratch registers */
+#define SYS_CTRL_SCRATCHWORD0          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc4)
+#define SYS_CTRL_SCRATCHWORD1          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc8)
+#define SYS_CTRL_SCRATCHWORD2          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xcc)
+#define SYS_CTRL_SCRATCHWORD3          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xd0)
+
+#define SYS_CTRL_PLLA_CTRL0            IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F0)
+#define SYS_CTRL_PLLA_CTRL1            IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F4)
+#define SYS_CTRL_PLLA_CTRL2            IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F8)
+#define SYS_CTRL_PLLA_CTRL3            IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1FC)
+
+#define SYS_CTRL_USBHSMPH_CTRL         IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x40)
+#define SYS_CTRL_USBHSMPH_STAT         IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x44)
+#define SYS_CTRL_REF300_DIV            IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xF8)
+#define SYS_CTRL_USBHSPHY_CTRL         IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x84)
+#define SYS_CTRL_USB_CTRL              IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x90)
+
+/* pcie */
+#define SYS_CTRL_HCSL_CTRL             IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x114)
+
+/* System control multi-function pin function selection */
+#define SYS_CTRL_SECONDARY_SEL         IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x14)
+#define SYS_CTRL_TERTIARY_SEL          IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x8c)
+#define SYS_CTRL_QUATERNARY_SEL                IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x94)
+#define SYS_CTRL_DEBUG_SEL             IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x9c)
+#define SYS_CTRL_ALTERNATIVE_SEL       IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xa4)
+#define SYS_CTRL_PULLUP_SEL            IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xac)
+
+/* Secure control multi-function pin function selection */
+#define SEC_CTRL_SECONDARY_SEL         IOMEM(OXNAS_SECCRTL_BASE_VA + 0x14)
+#define SEC_CTRL_TERTIARY_SEL          IOMEM(OXNAS_SECCRTL_BASE_VA + 0x8c)
+#define SEC_CTRL_QUATERNARY_SEL                IOMEM(OXNAS_SECCRTL_BASE_VA + 0x94)
+#define SEC_CTRL_DEBUG_SEL             IOMEM(OXNAS_SECCRTL_BASE_VA + 0x9c)
+#define SEC_CTRL_ALTERNATIVE_SEL       IOMEM(OXNAS_SECCRTL_BASE_VA + 0xa4)
+#define SEC_CTRL_PULLUP_SEL            IOMEM(OXNAS_SECCRTL_BASE_VA + 0xac)
+
+#define SEC_CTRL_COPRO_CTRL            IOMEM(OXNAS_SECCRTL_BASE_VA + 0x68)
+#define SEC_CTRL_SECURE_CTRL           IOMEM(OXNAS_SECCRTL_BASE_VA + 0x98)
+#define SEC_CTRL_LEON_DEBUG            IOMEM(OXNAS_SECCRTL_BASE_VA + 0xF0)
+#define SEC_CTRL_PLLB_DIV_CTRL         IOMEM(OXNAS_SECCRTL_BASE_VA + 0xF8)
+#define SEC_CTRL_PLLB_CTRL0            IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F0)
+#define SEC_CTRL_PLLB_CTRL1            IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F4)
+#define SEC_CTRL_PLLB_CTRL8            IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F4)
+
+#define RPSA_IRQ_SOFT                  IOMEM(OXNAS_RPSA_BASE_VA + 0x10)
+#define RPSA_FIQ_ENABLE                        IOMEM(OXNAS_RPSA_BASE_VA + 0x108)
+#define RPSA_FIQ_DISABLE               IOMEM(OXNAS_RPSA_BASE_VA + 0x10C)
+#define RPSA_FIQ_IRQ_TO_FIQ            IOMEM(OXNAS_RPSA_BASE_VA + 0x1FC)
+
+#define RPSC_IRQ_SOFT                  IOMEM(OXNAS_RPSC_BASE_VA + 0x10)
+#define RPSC_FIQ_ENABLE                        IOMEM(OXNAS_RPSC_BASE_VA + 0x108)
+#define RPSC_FIQ_DISABLE               IOMEM(OXNAS_RPSC_BASE_VA + 0x10C)
+#define RPSC_FIQ_IRQ_TO_FIQ            IOMEM(OXNAS_RPSC_BASE_VA + 0x1FC)
+
+#define RPSA_TIMER2_VAL                        IOMEM(OXNAS_RPSA_BASE_VA + 0x224)
+
+#define REF300_DIV_INT_SHIFT           8
+#define REF300_DIV_FRAC_SHIFT          0
+#define REF300_DIV_INT(val)            ((val) << REF300_DIV_INT_SHIFT)
+#define REF300_DIV_FRAC(val)           ((val) << REF300_DIV_FRAC_SHIFT)
+
+#define USBHSPHY_SUSPENDM_MANUAL_ENABLE                16
+#define USBHSPHY_SUSPENDM_MANUAL_STATE         15
+#define USBHSPHY_ATE_ESET                      14
+#define USBHSPHY_TEST_DIN                      6
+#define USBHSPHY_TEST_ADD                      2
+#define USBHSPHY_TEST_DOUT_SEL                 1
+#define USBHSPHY_TEST_CLK                      0
+
+#define USB_CTRL_USBAPHY_CKSEL_SHIFT   5
+#define USB_CLK_XTAL0_XTAL1            (0 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
+#define USB_CLK_XTAL0                  (1 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
+#define USB_CLK_INTERNAL               (2 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
+
+#define USBAMUX_DEVICE                 BIT(4)
+
+#define USBPHY_REFCLKDIV_SHIFT         2
+#define USB_PHY_REF_12MHZ              (0 << USBPHY_REFCLKDIV_SHIFT)
+#define USB_PHY_REF_24MHZ              (1 << USBPHY_REFCLKDIV_SHIFT)
+#define USB_PHY_REF_48MHZ              (2 << USBPHY_REFCLKDIV_SHIFT)
+
+#define USB_CTRL_USB_CKO_SEL_BIT       0
+
+#define USB_INT_CLK_XTAL               0
+#define USB_INT_CLK_REF300             2
+#define USB_INT_CLK_PLLB               3
+
+#define SYS_CTRL_GMAC_CKEN_RX_IN       14
+#define SYS_CTRL_GMAC_CKEN_RXN_OUT     13
+#define SYS_CTRL_GMAC_CKEN_RX_OUT      12
+#define SYS_CTRL_GMAC_CKEN_TX_IN       10
+#define SYS_CTRL_GMAC_CKEN_TXN_OUT     9
+#define SYS_CTRL_GMAC_CKEN_TX_OUT      8
+#define SYS_CTRL_GMAC_RX_SOURCE                7
+#define SYS_CTRL_GMAC_TX_SOURCE                6
+#define SYS_CTRL_GMAC_LOW_TX_SOURCE    4
+#define SYS_CTRL_GMAC_AUTO_TX_SOURCE   3
+#define SYS_CTRL_GMAC_RGMII            2
+#define SYS_CTRL_GMAC_SIMPLE_MUX       1
+#define SYS_CTRL_GMAC_CKEN_GTX         0
+#define SYS_CTRL_GMAC_TX_VARDELAY_SHIFT                0
+#define SYS_CTRL_GMAC_TXN_VARDELAY_SHIFT       8
+#define SYS_CTRL_GMAC_RX_VARDELAY_SHIFT                16
+#define SYS_CTRL_GMAC_RXN_VARDELAY_SHIFT       24
+#define SYS_CTRL_GMAC_TX_VARDELAY(d)   ((d)<<SYS_CTRL_GMAC_TX_VARDELAY_SHIFT)
+#define SYS_CTRL_GMAC_TXN_VARDELAY(d)  ((d)<<SYS_CTRL_GMAC_TXN_VARDELAY_SHIFT)
+#define SYS_CTRL_GMAC_RX_VARDELAY(d)   ((d)<<SYS_CTRL_GMAC_RX_VARDELAY_SHIFT)
+#define SYS_CTRL_GMAC_RXN_VARDELAY(d)  ((d)<<SYS_CTRL_GMAC_RXN_VARDELAY_SHIFT)
+
+#define PLLB_BYPASS                    1
+#define PLLB_ENSAT                     3
+#define PLLB_OUTDIV                    4
+#define PLLB_REFDIV                    8
+#define PLLB_DIV_INT_SHIFT             8
+#define PLLB_DIV_FRAC_SHIFT            0
+#define PLLB_DIV_INT(val)              ((val) << PLLB_DIV_INT_SHIFT)
+#define PLLB_DIV_FRAC(val)             ((val) << PLLB_DIV_FRAC_SHIFT)
+
+#define SYS_CTRL_CKCTRL_PCI_DIV_BIT    0
+#define SYS_CTRL_CKCTRL_SLOW_BIT       8
+
+#define SYS_CTRL_UART2_DEQ_EN          0
+#define SYS_CTRL_UART3_DEQ_EN          1
+#define SYS_CTRL_UART3_IQ_EN           2
+#define SYS_CTRL_UART4_IQ_EN           3
+#define SYS_CTRL_UART4_NOT_PCI_MODE    4
+
+#define SYS_CTRL_PCI_CTRL1_PCI_STATIC_RQ_BIT   11
+
+#define PLLA_REFDIV_MASK               0x3F
+#define PLLA_REFDIV_SHIFT              8
+#define PLLA_OUTDIV_MASK               0x7
+#define PLLA_OUTDIV_SHIFT              4
+
+/* bit numbers of clock control register */
+#define SYS_CTRL_CLK_COPRO             0
+#define SYS_CTRL_CLK_DMA               1
+#define SYS_CTRL_CLK_CIPHER            2
+#define SYS_CTRL_CLK_SD                        3
+#define SYS_CTRL_CLK_SATA              4
+#define SYS_CTRL_CLK_I2S               5
+#define SYS_CTRL_CLK_USBHS             6
+#define SYS_CTRL_CLK_MACA              7
+#define SYS_CTRL_CLK_MAC               SYS_CTRL_CLK_MACA
+#define SYS_CTRL_CLK_PCIEA             8
+#define SYS_CTRL_CLK_STATIC            9
+#define SYS_CTRL_CLK_MACB              10
+#define SYS_CTRL_CLK_PCIEB             11
+#define SYS_CTRL_CLK_REF600            12
+#define SYS_CTRL_CLK_USBDEV            13
+#define SYS_CTRL_CLK_DDR               14
+#define SYS_CTRL_CLK_DDRPHY            15
+#define SYS_CTRL_CLK_DDRCK             16
+
+
+/* bit numbers of reset control register */
+#define SYS_CTRL_RST_SCU               0
+#define SYS_CTRL_RST_COPRO             1
+#define SYS_CTRL_RST_ARM0              2
+#define SYS_CTRL_RST_ARM1              3
+#define SYS_CTRL_RST_USBHS             4
+#define SYS_CTRL_RST_USBHSPHYA         5
+#define SYS_CTRL_RST_MACA              6
+#define SYS_CTRL_RST_MAC               SYS_CTRL_RST_MACA
+#define SYS_CTRL_RST_PCIEA             7
+#define SYS_CTRL_RST_SGDMA             8
+#define SYS_CTRL_RST_CIPHER            9
+#define SYS_CTRL_RST_DDR               10
+#define SYS_CTRL_RST_SATA              11
+#define SYS_CTRL_RST_SATA_LINK         12
+#define SYS_CTRL_RST_SATA_PHY          13
+#define SYS_CTRL_RST_PCIEPHY           14
+#define SYS_CTRL_RST_STATIC            15
+#define SYS_CTRL_RST_GPIO              16
+#define SYS_CTRL_RST_UART1             17
+#define SYS_CTRL_RST_UART2             18
+#define SYS_CTRL_RST_MISC              19
+#define SYS_CTRL_RST_I2S               20
+#define SYS_CTRL_RST_SD                        21
+#define SYS_CTRL_RST_MACB              22
+#define SYS_CTRL_RST_PCIEB             23
+#define SYS_CTRL_RST_VIDEO             24
+#define SYS_CTRL_RST_DDR_PHY           25
+#define SYS_CTRL_RST_USBHSPHYB         26
+#define SYS_CTRL_RST_USBDEV            27
+#define SYS_CTRL_RST_ARMDBG            29
+#define SYS_CTRL_RST_PLLA              30
+#define SYS_CTRL_RST_PLLB              31
+
+#endif
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/iomap.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/iomap.h
new file mode 100644 (file)
index 0000000..01de7b7
--- /dev/null
@@ -0,0 +1,33 @@
+#ifndef __MACH_OXNAS_IOMAP_H
+#define __MACH_OXNAS_IOMAP_H
+
+#include <linux/sizes.h>
+
+#define OXNAS_UART1_BASE       0x44200000
+#define OXNAS_UART1_SIZE       SZ_32
+#define OXNAS_UART1_BASE_VA    0xF0000000
+
+#define OXNAS_UART2_BASE       0x44300000
+#define OXNAS_UART2_SIZE       SZ_32
+
+#define OXNAS_PERCPU_BASE      0x47000000
+#define OXNAS_PERCPU_SIZE      SZ_8K
+#define OXNAS_PERCPU_BASE_VA   0xF0002000
+
+#define OXNAS_SYSCRTL_BASE     0x44E00000
+#define OXNAS_SYSCRTL_SIZE     SZ_4K
+#define OXNAS_SYSCRTL_BASE_VA  0xF0004000
+
+#define OXNAS_SECCRTL_BASE     0x44F00000
+#define OXNAS_SECCRTL_SIZE     SZ_4K
+#define OXNAS_SECCRTL_BASE_VA  0xF0005000
+
+#define OXNAS_RPSA_BASE                0x44400000
+#define OXNAS_RPSA_SIZE                SZ_4K
+#define OXNAS_RPSA_BASE_VA     0xF0006000
+
+#define OXNAS_RPSC_BASE                0x44500000
+#define OXNAS_RPSC_SIZE                SZ_4K
+#define OXNAS_RPSC_BASE_VA     0xF0007000
+
+#endif
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/irqs.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/irqs.h
new file mode 100644 (file)
index 0000000..bcafd10
--- /dev/null
@@ -0,0 +1,7 @@
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#define IRQ_SOFT       1
+#define NR_IRQS                160
+
+#endif
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/smp.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/smp.h
new file mode 100644 (file)
index 0000000..1128635
--- /dev/null
@@ -0,0 +1,34 @@
+/*
+ * smp.h
+ *
+ *  Created on: Sep 24, 2013
+ *      Author: mahaijun
+ */
+
+#ifndef _NAS782X_SMP_H_
+#define _NAS782X_SMP_H_
+
+#include <mach/hardware.h>
+
+extern void ox820_secondary_startup(void);
+extern void ox820_cpu_die(unsigned int cpu);
+
+static inline void write_pen_release(int val)
+{
+       writel(val, HOLDINGPEN_CPU);
+}
+
+static inline int read_pen_release(void)
+{
+       return readl(HOLDINGPEN_CPU);
+}
+
+extern struct smp_operations ox820_smp_ops;
+
+extern unsigned char ox820_fiq_start, ox820_fiq_end;
+extern void v6_dma_map_area(const void *, size_t, int);
+extern void v6_dma_unmap_area(const void *, size_t, int);
+extern void v6_dma_flush_range(const void *, const void *);
+extern void v6_flush_kern_dcache_area(void *, size_t);
+
+#endif /* _NAS782X_SMP_H_ */
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/timex.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/timex.h
new file mode 100644 (file)
index 0000000..4133594
--- /dev/null
@@ -0,0 +1,6 @@
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+#define CLOCK_TICK_RATE                6250000
+
+#endif
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/uncompress.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/uncompress.h
new file mode 100644 (file)
index 0000000..fbc3727
--- /dev/null
@@ -0,0 +1,32 @@
+/* linux/include/asm-arm/arch-oxnas/uncompress.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#define OXNAS_UART1_BASE 0x44200000
+
+static inline void putc(int c)
+{
+       static volatile unsigned char *uart =
+               (volatile unsigned char *)OXNAS_UART1_BASE;
+
+       while (!(uart[5] & 0x20)) {     /* LSR reg THR empty bit */
+               barrier();
+       }
+       uart[0] = c;                    /* THR register */
+}
+
+static inline void flush(void)
+{
+}
+
+#define arch_decomp_setup()
+
+#define arch_decomp_wdog()
+
+#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/utils.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/utils.h
new file mode 100644 (file)
index 0000000..910d701
--- /dev/null
@@ -0,0 +1,34 @@
+#ifndef _NAS782X_UTILS_H
+#define _NAS782X_UTILS_H
+
+#include <linux/io.h>
+#include <mach/hardware.h>
+
+static inline void oxnas_register_clear_mask(void __iomem *p, unsigned mask)
+{
+       u32 val = readl_relaxed(p);
+
+       val &= ~mask;
+       writel_relaxed(val, p);
+}
+
+static inline void oxnas_register_set_mask(void __iomem *p, unsigned mask)
+{
+       u32 val = readl_relaxed(p);
+
+       val |= mask;
+       writel_relaxed(val, p);
+}
+
+static inline void oxnas_register_value_mask(void __iomem *p,
+                                            unsigned mask, unsigned new_value)
+{
+       /* TODO sanity check mask & new_value = new_value */
+       u32 val = readl_relaxed(p);
+
+       val &= ~mask;
+       val |= new_value;
+       writel_relaxed(val, p);
+}
+
+#endif /* _NAS782X_UTILS_H */
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/mach-ox820.c b/target/linux/oxnas/files/arch/arm/mach-oxnas/mach-ox820.c
new file mode 100644 (file)
index 0000000..4b247b6
--- /dev/null
@@ -0,0 +1,284 @@
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/bug.h>
+#include <linux/of_platform.h>
+#include <linux/clocksource.h>
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+#include <linux/stmmac.h>
+#include <linux/slab.h>
+#include <linux/gfp.h>
+#include <linux/reset.h>
+#include <asm/mach-types.h>
+#include <asm/mach/map.h>
+#include <asm/mach/arch.h>
+#include <asm/page.h>
+#include <mach/iomap.h>
+#include <mach/hardware.h>
+#include <mach/utils.h>
+#include <mach/smp.h>
+
+static struct map_desc ox820_io_desc[] __initdata = {
+       {
+               .virtual = (unsigned long)OXNAS_PERCPU_BASE_VA,
+               .pfn = __phys_to_pfn(OXNAS_PERCPU_BASE),
+               .length = OXNAS_PERCPU_SIZE,
+               .type = MT_DEVICE,
+       },
+       {
+               .virtual = (unsigned long)OXNAS_SYSCRTL_BASE_VA,
+               .pfn = __phys_to_pfn(OXNAS_SYSCRTL_BASE),
+               .length = OXNAS_SYSCRTL_SIZE,
+               .type = MT_DEVICE,
+       },
+       {
+               .virtual = (unsigned long)OXNAS_SECCRTL_BASE_VA,
+               .pfn = __phys_to_pfn(OXNAS_SECCRTL_BASE),
+               .length = OXNAS_SECCRTL_SIZE,
+               .type = MT_DEVICE,
+       },
+       {
+               .virtual = (unsigned long)OXNAS_RPSA_BASE_VA,
+               .pfn = __phys_to_pfn(OXNAS_RPSA_BASE),
+               .length = OXNAS_RPSA_SIZE,
+               .type = MT_DEVICE,
+       },
+       {
+               .virtual = (unsigned long)OXNAS_RPSC_BASE_VA,
+               .pfn = __phys_to_pfn(OXNAS_RPSC_BASE),
+               .length = OXNAS_RPSC_SIZE,
+               .type = MT_DEVICE,
+       },
+};
+
+void __init ox820_map_common_io(void)
+{
+       debug_ll_io_init();
+       iotable_init(ox820_io_desc, ARRAY_SIZE(ox820_io_desc));
+}
+
+struct plat_gmac_data {
+       struct plat_stmmacenet_data stmmac;
+       struct clk *clk;
+};
+
+void *ox820_gmac_setup(struct platform_device *pdev)
+{
+       struct plat_gmac_data *pdata = pdev->dev.platform_data;
+
+       pdata->clk = clk_get(&pdev->dev, "gmac");
+       return (void *) pdata->clk;
+};
+
+int ox820_gmac_init(struct platform_device *pdev, void *priv)
+{
+       int ret;
+       unsigned value;
+
+       ret = device_reset(&pdev->dev);
+       if (ret)
+               return ret;
+
+       if (IS_ERR(priv))
+               return PTR_ERR(priv);
+       clk_prepare_enable(priv);
+
+       value = readl(SYS_CTRL_GMAC_CTRL);
+
+       /* Enable GMII_GTXCLK to follow GMII_REFCLK, required for gigabit PHY */
+       value |= BIT(SYS_CTRL_GMAC_CKEN_GTX);
+       /* Use simple mux for 25/125 Mhz clock switching */
+       value |= BIT(SYS_CTRL_GMAC_SIMPLE_MUX);
+       /* set auto switch tx clock source */
+       value |= BIT(SYS_CTRL_GMAC_AUTO_TX_SOURCE);
+       /* enable tx & rx vardelay */
+       value |= BIT(SYS_CTRL_GMAC_CKEN_TX_OUT);
+       value |= BIT(SYS_CTRL_GMAC_CKEN_TXN_OUT);
+       value |= BIT(SYS_CTRL_GMAC_CKEN_TX_IN);
+       value |= BIT(SYS_CTRL_GMAC_CKEN_RX_OUT);
+       value |= BIT(SYS_CTRL_GMAC_CKEN_RXN_OUT);
+       value |= BIT(SYS_CTRL_GMAC_CKEN_RX_IN);
+       writel(value, SYS_CTRL_GMAC_CTRL);
+
+       /* set tx & rx vardelay */
+       value = 0;
+       value |= SYS_CTRL_GMAC_TX_VARDELAY(4);
+       value |= SYS_CTRL_GMAC_TXN_VARDELAY(2);
+       value |= SYS_CTRL_GMAC_RX_VARDELAY(10);
+       value |= SYS_CTRL_GMAC_RXN_VARDELAY(8);
+       writel(value, SYS_CTRL_GMAC_DELAY_CTRL);
+
+       return 0;
+}
+
+void ox820_gmac_exit(struct platform_device *pdev, void *priv)
+{
+       struct reset_control *rstc;
+
+       clk_disable_unprepare(priv);
+       clk_put(priv);
+
+       rstc = reset_control_get(&pdev->dev, NULL);
+       if (!IS_ERR(rstc)) {
+               reset_control_assert(rstc);
+               reset_control_put(rstc);
+       }
+}
+
+static int __init ox820_ether_init(void)
+{
+       struct device_node *node;
+       struct platform_device *pdev;
+       struct plat_gmac_data *pdata;
+
+       node = of_find_compatible_node(NULL, NULL, "plxtech,nas782x-gmac");
+       if (!node)
+               return -ENOENT;
+
+       pdev = of_find_device_by_node(node);
+       of_node_put(node);
+
+       if (!pdev)
+               return -EINVAL;
+
+       pdata = kzalloc(sizeof(struct plat_gmac_data), GFP_KERNEL);
+       if (!pdata)
+               return -ENOMEM;
+
+       pdata->stmmac.setup = ox820_gmac_setup;
+       pdata->stmmac.init = ox820_gmac_init;
+       pdata->stmmac.exit = ox820_gmac_exit;
+       pdev->dev.platform_data = pdata;
+
+       return 0;
+}
+
+static void __init ox820_dt_init(void)
+{
+       int ret;
+
+       ret = of_platform_populate(NULL, of_default_bus_match_table, NULL,
+                                       NULL);
+
+       if (ret) {
+               pr_err("of_platform_populate failed: %d\n", ret);
+               BUG();
+       }
+
+       ret = ox820_ether_init();
+
+       if (ret)
+               pr_info("ox820_ether_init failed: %d\n", ret);
+}
+
+static void __init ox820_timer_init(void)
+{
+       of_clk_init(NULL);
+       clocksource_of_init();
+}
+
+void ox820_init_early(void)
+{
+
+}
+
+void ox820_assert_system_reset(enum reboot_mode mode, const char *cmd)
+{
+       u32 value;
+
+/* Assert reset to cores as per power on defaults
+ * Don't touch the DDR interface as things will come to an impromptu stop
+ * NB Possibly should be asserting reset for PLLB, but there are timing
+ *    concerns here according to the docs */
+       value = BIT(SYS_CTRL_RST_COPRO)         |
+               BIT(SYS_CTRL_RST_USBHS)         |
+               BIT(SYS_CTRL_RST_USBHSPHYA)     |
+               BIT(SYS_CTRL_RST_MACA)          |
+               BIT(SYS_CTRL_RST_PCIEA)         |
+               BIT(SYS_CTRL_RST_SGDMA)         |
+               BIT(SYS_CTRL_RST_CIPHER)        |
+               BIT(SYS_CTRL_RST_SATA)          |
+               BIT(SYS_CTRL_RST_SATA_LINK)     |
+               BIT(SYS_CTRL_RST_SATA_PHY)      |
+               BIT(SYS_CTRL_RST_PCIEPHY)       |
+               BIT(SYS_CTRL_RST_STATIC)        |
+               BIT(SYS_CTRL_RST_UART1)         |
+               BIT(SYS_CTRL_RST_UART2)         |
+               BIT(SYS_CTRL_RST_MISC)          |
+               BIT(SYS_CTRL_RST_I2S)           |
+               BIT(SYS_CTRL_RST_SD)            |
+               BIT(SYS_CTRL_RST_MACB)          |
+               BIT(SYS_CTRL_RST_PCIEB)         |
+               BIT(SYS_CTRL_RST_VIDEO)         |
+               BIT(SYS_CTRL_RST_USBHSPHYB)     |
+               BIT(SYS_CTRL_RST_USBDEV);
+
+       writel(value, SYS_CTRL_RST_SET_CTRL);
+
+       /* Release reset to cores as per power on defaults */
+       writel(BIT(SYS_CTRL_RST_GPIO), SYS_CTRL_RST_CLR_CTRL);
+
+       /* Disable clocks to cores as per power-on defaults - must leave DDR
+        * related clocks enabled otherwise we'll stop rather abruptly. */
+       value =
+               BIT(SYS_CTRL_CLK_COPRO)         |
+               BIT(SYS_CTRL_CLK_DMA)           |
+               BIT(SYS_CTRL_CLK_CIPHER)        |
+               BIT(SYS_CTRL_CLK_SD)            |
+               BIT(SYS_CTRL_CLK_SATA)          |
+               BIT(SYS_CTRL_CLK_I2S)           |
+               BIT(SYS_CTRL_CLK_USBHS)         |
+               BIT(SYS_CTRL_CLK_MAC)           |
+               BIT(SYS_CTRL_CLK_PCIEA)         |
+               BIT(SYS_CTRL_CLK_STATIC)        |
+               BIT(SYS_CTRL_CLK_MACB)          |
+               BIT(SYS_CTRL_CLK_PCIEB)         |
+               BIT(SYS_CTRL_CLK_REF600)        |
+               BIT(SYS_CTRL_CLK_USBDEV);
+
+       writel(value, SYS_CTRL_CLK_CLR_CTRL);
+
+       /* Enable clocks to cores as per power-on defaults */
+
+       /* Set sys-control pin mux'ing as per power-on defaults */
+       writel(0, SYS_CTRL_SECONDARY_SEL);
+       writel(0, SYS_CTRL_TERTIARY_SEL);
+       writel(0, SYS_CTRL_QUATERNARY_SEL);
+       writel(0, SYS_CTRL_DEBUG_SEL);
+       writel(0, SYS_CTRL_ALTERNATIVE_SEL);
+       writel(0, SYS_CTRL_PULLUP_SEL);
+
+       writel(0, SYS_CTRL_SECONDARY_SEL);
+       writel(0, SYS_CTRL_TERTIARY_SEL);
+       writel(0, SYS_CTRL_QUATERNARY_SEL);
+       writel(0, SYS_CTRL_DEBUG_SEL);
+       writel(0, SYS_CTRL_ALTERNATIVE_SEL);
+       writel(0, SYS_CTRL_PULLUP_SEL);
+
+       /* No need to save any state, as the ROM loader can determine whether
+        * reset is due to power cycling or programatic action, just hit the
+        * (self-clearing) CPU reset bit of the block reset register */
+       value =
+               BIT(SYS_CTRL_RST_SCU) |
+               BIT(SYS_CTRL_RST_ARM0) |
+               BIT(SYS_CTRL_RST_ARM1);
+
+       writel(value, SYS_CTRL_RST_SET_CTRL);
+}
+
+static const char * const ox820_dt_board_compat[] = {
+       "plxtech,nas7820",
+       "plxtech,nas7821",
+       "plxtech,nas7825",
+       NULL
+};
+
+DT_MACHINE_START(OX820_DT, "PLXTECH NAS782X SoC (Flattened Device Tree)")
+       .map_io         = ox820_map_common_io,
+       .smp            = smp_ops(ox820_smp_ops),
+       .init_early     = ox820_init_early,
+       .init_time      = ox820_timer_init,
+       .init_machine   = ox820_dt_init,
+       .restart        = ox820_assert_system_reset,
+       .dt_compat      = ox820_dt_board_compat,
+MACHINE_END
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/platsmp.c b/target/linux/oxnas/files/arch/arm/mach-oxnas/platsmp.c
new file mode 100644 (file)
index 0000000..c41a3d1
--- /dev/null
@@ -0,0 +1,315 @@
+/*
+ *  arch/arm/mach-ox820/platsmp.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/jiffies.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/dma-mapping.h>
+#include <linux/cache.h>
+#include <asm/cacheflush.h>
+#include <asm/smp_scu.h>
+#include <asm/tlbflush.h>
+#include <asm/cputype.h>
+#include <linux/delay.h>
+#include <asm/fiq.h>
+
+#include <linux/irqchip/arm-gic.h>
+#include <mach/iomap.h>
+#include <mach/smp.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+
+#ifdef CONFIG_DMA_CACHE_FIQ_BROADCAST
+
+#define FIQ_GENERATE           0x00000002
+#define OXNAS_MAP_AREA         0x01000000
+#define OXNAS_UNMAP_AREA       0x02000000
+#define OXNAS_FLUSH_RANGE      0x03000000
+
+struct fiq_req {
+       union {
+               struct {
+                       const void *addr;
+                       size_t size;
+               } map;
+               struct {
+                       const void *addr;
+                       size_t size;
+               } unmap;
+               struct {
+                       const void *start;
+                       const void *end;
+               } flush;
+       };
+       volatile uint flags;
+       void __iomem *reg;
+} ____cacheline_aligned;
+
+static struct fiq_handler fh = {
+       .name = "oxnas-fiq"
+};
+
+DEFINE_PER_CPU(struct fiq_req, fiq_data);
+
+static inline void __cpuinit ox820_set_fiq_regs(unsigned int cpu)
+{
+       struct pt_regs FIQ_regs;
+       struct fiq_req *fiq_req = &per_cpu(fiq_data, !cpu);
+
+       FIQ_regs.ARM_r8 = 0;
+       FIQ_regs.ARM_ip = (unsigned int)fiq_req;
+       FIQ_regs.ARM_sp = (int)(cpu ? RPSC_IRQ_SOFT : RPSA_IRQ_SOFT);
+       fiq_req->reg = cpu ? RPSC_IRQ_SOFT : RPSA_IRQ_SOFT;
+
+       set_fiq_regs(&FIQ_regs);
+}
+
+static void __init ox820_init_fiq(void)
+{
+       void *fiqhandler_start;
+       unsigned int fiqhandler_length;
+       int ret;
+
+       fiqhandler_start = &ox820_fiq_start;
+       fiqhandler_length = &ox820_fiq_end - &ox820_fiq_start;
+
+       ret = claim_fiq(&fh);
+
+       if (ret)
+               return;
+
+       set_fiq_handler(fiqhandler_start, fiqhandler_length);
+
+       writel(IRQ_SOFT, RPSA_FIQ_IRQ_TO_FIQ);
+       writel(1, RPSA_FIQ_ENABLE);
+       writel(IRQ_SOFT, RPSC_FIQ_IRQ_TO_FIQ);
+       writel(1, RPSC_FIQ_ENABLE);
+}
+
+void fiq_dma_map_area(const void *addr, size_t size, int dir)
+{
+       unsigned long flags;
+       struct fiq_req *req;
+
+       raw_local_irq_save(flags);
+       /* currently, not possible to take cpu0 down, so only check cpu1 */
+       if (!cpu_online(1)) {
+               raw_local_irq_restore(flags);
+               v6_dma_map_area(addr, size, dir);
+               return;
+       }
+
+       req = this_cpu_ptr(&fiq_data);
+       req->map.addr = addr;
+       req->map.size = size;
+       req->flags = dir | OXNAS_MAP_AREA;
+       smp_mb();
+
+       writel_relaxed(FIQ_GENERATE, req->reg);
+
+       v6_dma_map_area(addr, size, dir);
+       while (req->flags)
+               barrier();
+
+       raw_local_irq_restore(flags);
+}
+
+void fiq_dma_unmap_area(const void *addr, size_t size, int dir)
+{
+       unsigned long flags;
+       struct fiq_req *req;
+
+       raw_local_irq_save(flags);
+       /* currently, not possible to take cpu0 down, so only check cpu1 */
+       if (!cpu_online(1)) {
+               raw_local_irq_restore(flags);
+               v6_dma_unmap_area(addr, size, dir);
+               return;
+       }
+
+       req = this_cpu_ptr(&fiq_data);
+       req->unmap.addr = addr;
+       req->unmap.size = size;
+       req->flags = dir | OXNAS_UNMAP_AREA;
+       smp_mb();
+
+       writel_relaxed(FIQ_GENERATE, req->reg);
+
+       v6_dma_unmap_area(addr, size, dir);
+       while (req->flags)
+               barrier();
+
+       raw_local_irq_restore(flags);
+}
+
+void fiq_dma_flush_range(const void *start, const void *end)
+{
+       unsigned long flags;
+       struct fiq_req *req;
+
+       raw_local_irq_save(flags);
+       /* currently, not possible to take cpu0 down, so only check cpu1 */
+       if (!cpu_online(1)) {
+               raw_local_irq_restore(flags);
+               v6_dma_flush_range(start, end);
+               return;
+       }
+
+       req = this_cpu_ptr(&fiq_data);
+
+       req->flush.start = start;
+       req->flush.end = end;
+       req->flags = OXNAS_FLUSH_RANGE;
+       smp_mb();
+
+       writel_relaxed(FIQ_GENERATE, req->reg);
+
+       v6_dma_flush_range(start, end);
+
+       while (req->flags)
+               barrier();
+
+       raw_local_irq_restore(flags);
+}
+
+void fiq_flush_kern_dcache_area(void *addr, size_t size)
+{
+       fiq_dma_flush_range(addr, addr + size);
+}
+#else
+
+#define ox820_set_fiq_regs(cpu)        do {} while (0) /* nothing */
+#define ox820_init_fiq()       do {} while (0) /* nothing */
+
+#endif /* DMA_CACHE_FIQ_BROADCAST */
+
+static DEFINE_SPINLOCK(boot_lock);
+
+void __cpuinit ox820_secondary_init(unsigned int cpu)
+{
+       /*
+        * Setup Secondary Core FIQ regs
+        */
+       ox820_set_fiq_regs(1);
+
+       /*
+        * let the primary processor know we're out of the
+        * pen, then head off into the C entry point
+        */
+       write_pen_release(-1);
+
+       /*
+        * Synchronise with the boot thread.
+        */
+       spin_lock(&boot_lock);
+       spin_unlock(&boot_lock);
+}
+
+int __cpuinit ox820_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+       unsigned long timeout;
+
+       /*
+        * Set synchronisation state between this boot processor
+        * and the secondary one
+        */
+       spin_lock(&boot_lock);
+
+       /*
+        * This is really belt and braces; we hold unintended secondary
+        * CPUs in the holding pen until we're ready for them.  However,
+        * since we haven't sent them a soft interrupt, they shouldn't
+        * be there.
+        */
+       write_pen_release(cpu);
+
+       writel(1, IOMEM(OXNAS_GICN_BASE_VA(cpu) + GIC_CPU_CTRL));
+
+       /*
+        * Send the secondary CPU a soft interrupt, thereby causing
+        * the boot monitor to read the system wide flags register,
+        * and branch to the address found there.
+        */
+
+       arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+       timeout = jiffies + (1 * HZ);
+       while (time_before(jiffies, timeout)) {
+               smp_rmb();
+               if (read_pen_release() == -1)
+                       break;
+
+               udelay(10);
+       }
+
+       /*
+        * now the secondary core is starting up let it run its
+        * calibrations, then wait for it to finish
+        */
+       spin_unlock(&boot_lock);
+
+       return read_pen_release() != -1 ? -ENOSYS : 0;
+}
+
+void *scu_base_addr(void)
+{
+       return IOMEM(OXNAS_SCU_BASE_VA);
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+static void __init ox820_smp_init_cpus(void)
+{
+       void __iomem *scu_base = scu_base_addr();
+       unsigned int i, ncores;
+
+       ncores = scu_base ? scu_get_core_count(scu_base) : 1;
+
+       /* sanity check */
+       if (ncores > nr_cpu_ids) {
+               pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
+                       ncores, nr_cpu_ids);
+               ncores = nr_cpu_ids;
+       }
+
+       for (i = 0; i < ncores; i++)
+               set_cpu_possible(i, true);
+}
+
+static void __init ox820_smp_prepare_cpus(unsigned int max_cpus)
+{
+
+       scu_enable(scu_base_addr());
+
+       /*
+        * Write the address of secondary startup into the
+        * system-wide flags register. The BootMonitor waits
+        * until it receives a soft interrupt, and then the
+        * secondary CPU branches to this address.
+        */
+       writel(virt_to_phys(ox820_secondary_startup),
+                                       HOLDINGPEN_LOCATION);
+       ox820_init_fiq();
+
+       ox820_set_fiq_regs(0);
+}
+
+struct smp_operations ox820_smp_ops __initdata = {
+       .smp_init_cpus          = ox820_smp_init_cpus,
+       .smp_prepare_cpus       = ox820_smp_prepare_cpus,
+       .smp_secondary_init     = ox820_secondary_init,
+       .smp_boot_secondary     = ox820_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+       .cpu_die                = ox820_cpu_die,
+#endif
+};
diff --git a/target/linux/oxnas/files/drivers/ata/sata_oxnas.c b/target/linux/oxnas/files/drivers/ata/sata_oxnas.c
new file mode 100644 (file)
index 0000000..b3685bd
--- /dev/null
@@ -0,0 +1,1889 @@
+#include <linux/ata.h>
+#include <linux/libata.h>
+#include <linux/of_platform.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+
+#include <mach/utils.h>
+
+/* sgdma request structure */
+struct sgdma_request {
+       volatile u32 qualifier;
+       volatile u32 control;
+       dma_addr_t src_pa;
+       dma_addr_t dst_pa;
+} __packed __aligned(4);
+
+
+/* Controller information */
+enum {
+       SATA_OXNAS_MAX_PRD = 254,
+       SATA_OXNAS_DMA_SIZE = SATA_OXNAS_MAX_PRD *
+                               sizeof(struct ata_bmdma_prd) +
+                               sizeof(struct sgdma_request),
+       SATA_OXNAS_MAX_PORTS    = 1,
+       /** The different Oxsemi SATA core version numbers */
+       SATA_OXNAS_CORE_VERSION = 0x1f3,
+       SATA_OXNAS_IRQ_FLAG     = IRQF_SHARED,
+       SATA_OXNAS_HOST_FLAGS   = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
+                       ATA_FLAG_NO_ATAPI /*| ATA_FLAG_NCQ*/),
+       SATA_OXNAS_QUEUE_DEPTH  = 32,
+
+       SATA_OXNAS_DMA_BOUNDARY = 0xFFFFFFFF,
+};
+
+
+/*
+ * SATA Port Registers
+ */
+enum {
+       /** sata host port register offsets */
+       ORB1 = 0x00,
+       ORB2 = 0x04,
+       ORB3 = 0x08,
+       ORB4 = 0x0C,
+       ORB5 = 0x10,
+       MASTER_STATUS = 0x10,
+       FIS_CTRL = 0x18,
+       FIS_DATA = 0x1C,
+       INT_STATUS = 0x30,
+       INT_CLEAR = 0x30,
+       INT_ENABLE = 0x34,
+       INT_DISABLE = 0x38,
+       VERSION = 0x3C,
+       SATA_CONTROL = 0x5C,
+       SATA_COMMAND = 0x60,
+       HID_FEATURES = 0x64,
+       PORT_CONTROL = 0x68,
+       DRIVE_CONTROL = 0x6C,
+       /** These registers allow access to the link layer registers
+       that reside in a different clock domain to the processor bus */
+       LINK_DATA = 0x70,
+       LINK_RD_ADDR = 0x74,
+       LINK_WR_ADDR = 0x78,
+       LINK_CONTROL = 0x7C,
+       /* window control */
+       WIN1LO = 0x80,
+       WIN1HI = 0x84,
+       WIN2LO = 0x88,
+       WIN2HI = 0x8C,
+       WIN0_CONTROL = 0x90,
+
+};
+
+/** sata port register bits */
+enum{
+       /**
+        * commands to issue in the master status to tell it to move shadow ,
+        * registers to the actual device ,
+        */
+       SATA_OPCODE_MASK = 0x00000007,
+       CMD_WRITE_TO_ORB_REGS_NO_COMMAND = 0x4,
+       CMD_WRITE_TO_ORB_REGS = 0x2,
+       CMD_SYNC_ESCAPE = 0x7,
+       CMD_CORE_BUSY = (1 << 7),
+       CMD_DRIVE_SELECT_SHIFT = 12,
+       CMD_DRIVE_SELECT_MASK = (0xf << CMD_DRIVE_SELECT_SHIFT),
+
+       /** interrupt bits */
+       INT_END_OF_CMD = 1 << 0,
+       INT_LINK_SERROR = 1 << 1,
+       INT_ERROR = 1 << 2,
+       INT_LINK_IRQ = 1 << 3,
+       INT_REG_ACCESS_ERR = 1 << 7,
+       INT_BIST_FIS = 1 << 11,
+       INT_MASKABLE =  INT_END_OF_CMD |
+                       INT_LINK_SERROR |
+                       INT_ERROR |
+                       INT_LINK_IRQ |
+                       INT_REG_ACCESS_ERR |
+                       INT_BIST_FIS,
+       INT_WANT =      INT_END_OF_CMD |
+                       INT_LINK_SERROR |
+                       INT_REG_ACCESS_ERR |
+                       INT_ERROR,
+       INT_ERRORS =    INT_LINK_SERROR |
+                       INT_REG_ACCESS_ERR |
+                       INT_ERROR,
+
+       /** raw interrupt bits, unmaskable, but do not generate interrupts */
+       RAW_END_OF_CMD  = INT_END_OF_CMD << 16,
+       RAW_LINK_SERROR = INT_LINK_SERROR  << 16,
+       RAW_ERROR  = INT_ERROR << 16,
+       RAW_LINK_IRQ  = INT_LINK_IRQ << 16,
+       RAW_REG_ACCESS_ERR = INT_REG_ACCESS_ERR << 16,
+       RAW_BIST_FIS  = INT_BIST_FIS << 16,
+       RAW_WANT  = INT_WANT << 16,
+       RAW_ERRORS  = INT_ERRORS << 16,
+
+       /**
+        * variables to write to the device control register to set the current
+        * device, ie. master or slave.
+        */
+       DR_CON_48 = 2,
+       DR_CON_28 = 0,
+
+       SATA_CTL_ERR_MASK = 0x00000016,
+
+};
+
+/* ATA SGDMA register offsets */
+enum {
+       SGDMA_CONTROL = 0x0,
+       SGDMA_STATUS = 0x4,
+       SGDMA_REQUESTPTR = 0x8,
+       SGDMA_RESETS = 0xC,
+       SGDMA_CORESIZE = 0x10,
+};
+
+enum {
+       /* see DMA core docs for the values. Out means from memory (bus A) out
+        * to disk (bus B) */
+       SGDMA_REQCTL0OUT = 0x0497c03d,
+       /* burst mode disabled when no micro code used */
+       SGDMA_REQCTL0IN = 0x0493a3c1,
+       SGDMA_REQCTL1OUT = 0x0497c07d,
+       SGDMA_REQCTL1IN = 0x0497a3c5,
+       SGDMA_CONTROL_NOGO = 0x3e,
+       SGDMA_CONTROL_GO = SGDMA_CONTROL_NOGO | 1,
+       SGDMA_ERRORMASK = 0x3f,
+       SGDMA_BUSY = 0x80,
+
+       SGDMA_RESETS_CTRL = 1 << 0,
+       SGDMA_RESETS_ARBT = 1 << 1,
+       SGDMA_RESETS_AHB = 1 << 2,
+       SGDMA_RESETS_ALL =      SGDMA_RESETS_CTRL |
+                               SGDMA_RESETS_ARBT |
+                               SGDMA_RESETS_AHB,
+
+       /* Final EOTs */
+       SGDMA_REQQUAL = 0x00220001,
+
+};
+
+/** SATA core register offsets */
+enum {
+       DM_DBG1 = 0x000,
+       RAID_SET = 0x004,
+       DM_DBG2 = 0x008,
+       DATACOUNT_PORT0 = 0x010,
+       DATACOUNT_PORT1 = 0x014,
+       CORE_INT_STATUS = 0x030,
+       CORE_INT_CLEAR = 0x030,
+       CORE_INT_ENABLE = 0x034,
+       CORE_INT_DISABLE  = 0x038,
+       CORE_REBUILD_ENABLE = 0x050,
+       CORE_FAILED_PORT_R = 0x054,
+       DEVICE_CONTROL = 0x068,
+       EXCESS = 0x06C,
+       RAID_SIZE_LOW = 0x070,
+       RAID_SIZE_HIGH = 0x074,
+       PORT_ERROR_MASK = 0x078,
+       IDLE_STATUS = 0x07C,
+       RAID_CONTROL = 0x090,
+       DATA_PLANE_CTRL = 0x0AC,
+       CORE_DATAPLANE_STAT = 0x0b8,
+       PROC_PC = 0x100,
+       CONFIG_IN = 0x3d8,
+       PROC_START = 0x3f0,
+       PROC_RESET = 0x3f4,
+       UCODE_STORE = 0x1000,
+       RAID_WP_BOT_LOW = 0x1FF0,
+       RAID_WP_BOT_HIGH  = 0x1FF4,
+       RAID_WP_TOP_LOW = 0x1FF8,
+       RAID_WP_TOP_HIGH = 0x1FFC,
+       DATA_MUX_RAM0 = 0x8000,
+       DATA_MUX_RAM1 = 0xA000,
+};
+
+enum {
+       /* Sata core debug1 register bits */
+       CORE_PORT0_DATA_DIR_BIT = 20,
+       CORE_PORT1_DATA_DIR_BIT = 21,
+       CORE_PORT0_DATA_DIR = 1 << CORE_PORT0_DATA_DIR_BIT,
+       CORE_PORT1_DATA_DIR = 1 << CORE_PORT1_DATA_DIR_BIT,
+
+       /** sata core control register bits */
+       SCTL_CLR_ERR = 0x00003016,
+       RAID_CLR_ERR = 0x0000011e,
+
+       /* Interrupts direct from the ports */
+       NORMAL_INTS_WANTED = 0x00000303,
+
+       /* shift these left by port number */
+       COREINT_HOST = 0x00000001,
+       COREINT_END = 0x00000100,
+       CORERAW_HOST = COREINT_HOST << 16,
+       CORERAW_END = COREINT_END  << 16,
+
+       /* Interrupts from the RAID controller only */
+       RAID_INTS_WANTED = 0x00008300,
+
+       /* The bits in the IDLE_STATUS that, when set indicate an idle core */
+       IDLE_CORES = (1 << 18) | (1 << 19),
+
+       /* Data plane control error-mask mask and bit, these bit in the data
+        * plane control mask out errors from the ports that prevent the SGDMA
+        * care from sending an interrupt */
+       DPC_ERROR_MASK = 0x00000300,
+       DPC_ERROR_MASK_BIT = 0x00000100,
+       /* enable jbod micro-code */
+       DPC_JBOD_UCODE = 1 << 0,
+       DPC_FIS_SWCH = 1 << 1,
+
+       /** Device Control register bits */
+       DEVICE_CONTROL_DMABT = 1 << 4,
+       DEVICE_CONTROL_ABORT = 1 << 2,
+       DEVICE_CONTROL_PAD = 1 << 3,
+       DEVICE_CONTROL_PADPAT = 1 << 16,
+       DEVICE_CONTROL_PRTRST = 1 << 8,
+       DEVICE_CONTROL_RAMRST = 1 << 12,
+       DEVICE_CONTROL_ATA_ERR_OVERRIDE = 1 << 28,
+
+       /** oxsemi HW raid modes */
+       OXNASSATA_NOTRAID = 0,
+       OXNASSATA_RAID0 = 1,
+       OXNASSATA_RAID1 = 2,
+       /** OX820 specific HW-RAID register values */
+       RAID_TWODISKS = 3,
+       UNKNOWN_MODE = ~0,
+};
+
+/* SATA PHY Registers */
+enum {
+       PHY_STAT = 0x00,
+       PHY_DATA = 0x04,
+};
+
+enum {
+       STAT_READ_VALID = (1 << 21),
+       STAT_CR_ACK = (1 << 20),
+       STAT_CR_READ = (1 << 19),
+       STAT_CR_WRITE = (1 << 18),
+       STAT_CAP_DATA = (1 << 17),
+       STAT_CAP_ADDR = (1 << 16),
+
+       STAT_ACK_ANY =  STAT_CR_ACK |
+                       STAT_CR_READ |
+                       STAT_CR_WRITE |
+                       STAT_CAP_DATA |
+                       STAT_CAP_ADDR,
+
+       CR_READ_ENABLE = (1 << 16),
+       CR_WRITE_ENABLE = (1 << 17),
+       CR_CAP_DATA = (1 << 18),
+};
+
+enum {
+       /* Link layer registers */
+       SERROR_IRQ_MASK = 5,
+};
+
+enum {
+       OXNAS_SATA_SOFTRESET = 1,
+       OXNAS_SATA_REINIT = 2,
+};
+
+enum {
+               OXNAS_SATA_UCODE_RAID0,
+               OXNAS_SATA_UCODE_RAID1,
+               OXNAS_SATA_UCODE_JBOD,
+               OXNAS_SATA_UCODE_NONE,
+};
+
+struct sata_oxnas_host_priv {
+       void __iomem *port_base[SATA_OXNAS_MAX_PORTS];
+       void __iomem *sgdma_base[SATA_OXNAS_MAX_PORTS];
+       void __iomem *core_base;
+       void __iomem *phy_base;
+       dma_addr_t dma_base;
+       void __iomem *dma_base_va;
+       size_t dma_size;
+       int irq;
+       u32 port_in_eh;
+       struct clk *clk;
+       struct reset_control *rst_sata;
+       struct reset_control *rst_link;
+       struct reset_control *rst_phy;
+};
+
+
+struct sata_oxnas_port_priv {
+       void __iomem *port_base;
+       void __iomem *sgdma_base;
+       void __iomem *core_base;
+       struct sgdma_request *sgdma_request;
+       dma_addr_t sgdma_request_pa;
+};
+
+static u8 sata_oxnas_check_status(struct ata_port *ap);
+static int sata_oxnas_cleanup(struct ata_host *ah);
+static void sata_oxnas_tf_load(struct ata_port *ap,
+                               const struct ata_taskfile *tf);
+static void sata_oxnas_irq_on(struct ata_port *ap);
+static void sata_oxnas_post_reset_init(struct ata_port *ap);
+
+/* ??????????????????????????????????? */
+static void wait_cr_ack(void __iomem *phy_base)
+{
+       while ((ioread32(phy_base + PHY_STAT) >> 16) & 0x1f)
+               ; /* wait for an ack bit to be set */
+}
+
+static u16 read_cr(void __iomem *phy_base, u16 address)
+{
+       iowrite32((u32)address, phy_base + PHY_STAT);
+       wait_cr_ack(phy_base);
+       iowrite32(CR_READ_ENABLE, phy_base + PHY_DATA);
+       wait_cr_ack(phy_base);
+       return (u16)ioread32(phy_base + PHY_STAT);
+}
+
+static void write_cr(void __iomem *phy_base, u16 data, u16 address)
+{
+       iowrite32((u32)address, phy_base + PHY_STAT);
+       wait_cr_ack(phy_base);
+       iowrite32((data | CR_CAP_DATA), phy_base + PHY_DATA);
+       wait_cr_ack(phy_base);
+       iowrite32(CR_WRITE_ENABLE, phy_base + PHY_DATA);
+       wait_cr_ack(phy_base);
+}
+
+#define PH_GAIN                 2
+#define FR_GAIN                 3
+#define PH_GAIN_OFFSET  6
+#define FR_GAIN_OFFSET  8
+#define PH_GAIN_MASK  (0x3 << PH_GAIN_OFFSET)
+#define FR_GAIN_MASK  (0x3 << FR_GAIN_OFFSET)
+#define USE_INT_SETTING  (1<<5)
+
+void workaround5458(struct ata_host *ah)
+{
+       struct sata_oxnas_host_priv *hd = ah->private_data;
+       void __iomem *phy_base = hd->phy_base;
+       u16 rx_control;
+       unsigned i;
+
+       for (i = 0; i < 2; i++) {
+               rx_control = read_cr(phy_base, 0x201d + (i << 8));
+               rx_control &= ~(PH_GAIN_MASK | FR_GAIN_MASK);
+               rx_control |= PH_GAIN << PH_GAIN_OFFSET;
+               rx_control |= (FR_GAIN << FR_GAIN_OFFSET) | USE_INT_SETTING;
+               write_cr(phy_base, rx_control, 0x201d+(i<<8));
+       }
+}
+
+/**
+ * allows access to the link layer registers
+ * @param link_reg the link layer register to access (oxsemi indexing ie
+ *             00 = static config, 04 = phy ctrl)
+ */
+void sata_oxnas_link_write(struct ata_port *ap, unsigned int link_reg, u32 val)
+{
+       struct sata_oxnas_port_priv *port_priv = ap->private_data;
+       void __iomem *port_base = port_priv->port_base;
+       u32 patience;
+
+       DPRINTK("[0x%02x]->0x%08x\n", link_reg, val);
+
+       iowrite32(val, port_base + LINK_DATA);
+
+       /* accessed twice as a work around for a bug in the SATA abp bridge
+        * hardware (bug 6828) */
+       iowrite32(link_reg , port_base + LINK_WR_ADDR);
+       ioread32(port_base + LINK_WR_ADDR);
+
+       for (patience = 0x100000; patience > 0; --patience) {
+               if (ioread32(port_base + LINK_CONTROL) & 0x00000001)
+                       break;
+       }
+}
+
+static int sata_oxnas_scr_write_port(struct ata_port *ap, unsigned int sc_reg,
+                                       u32 val)
+{
+       sata_oxnas_link_write(ap, 0x20 + (sc_reg * 4), val);
+       return 0;
+}
+
+static int sata_oxnas_scr_write(struct ata_link *link, unsigned int sc_reg,
+                               u32 val)
+{
+       return sata_oxnas_scr_write_port(link->ap, sc_reg, val);
+}
+
+/* FIXME lock */
+u32 sata_oxnas_link_read(struct ata_port *ap, unsigned int link_reg)
+{
+       struct sata_oxnas_port_priv *pd = ap->private_data;
+       void __iomem *port_base = pd->port_base;
+       u32 result;
+       u32 patience;
+
+       /* accessed twice as a work around for a bug in the SATA abp bridge
+        * hardware (bug 6828) */
+       iowrite32(link_reg, port_base + LINK_RD_ADDR);
+       ioread32(port_base + LINK_RD_ADDR);
+
+       for (patience = 0x100000; patience > 0; --patience) {
+               if (ioread32(port_base + LINK_CONTROL) & 0x00000001)
+                       break;
+       }
+       if (patience == 0)
+               DPRINTK("link read timed out\n");
+
+       result = readl(port_base + LINK_DATA);
+
+       return result;
+}
+
+static int sata_oxnas_scr_read_port(struct ata_port *ap, unsigned int sc_reg,
+                                       u32 *val)
+{
+       *val = sata_oxnas_link_read(ap, 0x20 + (sc_reg*4));
+       return 0;
+}
+
+static int sata_oxnas_scr_read(struct ata_link *link,
+                            unsigned int sc_reg, u32 *val)
+{
+
+       return sata_oxnas_scr_read_port(link->ap, sc_reg, val);
+}
+
+/**
+ * sata_oxnas_irq_clear is called during probe just before the interrupt handler is
+ * registered, to be sure hardware is quiet. It clears and masks interrupt bits
+ * in the SATA core.
+ *
+ * @param ap hardware with the registers in
+ */
+static void sata_oxnas_irq_clear(struct ata_port *ap)
+{
+       struct sata_oxnas_port_priv *port_priv = ap->private_data;
+
+       /* clear pending interrupts */
+       iowrite32(~0, port_priv->port_base + INT_CLEAR);
+       iowrite32(COREINT_END, port_priv->core_base + CORE_INT_CLEAR);
+}
+
+/**
+ * qc_issue is used to make a command active, once the hardware and S/G tables
+ * have been prepared. IDE BMDMA drivers use the helper function
+ * ata_qc_issue_prot() for taskfile protocol-based dispatch. More advanced
+ * drivers roll their own ->qc_issue implementation, using this as the
+ * "issue new ATA command to hardware" hook.
+ * @param qc the queued command to issue
+ */
+static unsigned int sata_oxnas_qc_issue(struct ata_queued_cmd *qc)
+{
+       struct sata_oxnas_port_priv *pd = qc->ap->private_data;
+       void __iomem *port_base = pd->port_base;
+       void __iomem *core_base = pd->core_base;
+       int port_no = qc->ap->port_no;
+       u32 reg;
+
+       /* check the core is idle */
+       if (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY) {
+               int count = 0;
+
+               DPRINTK("core busy for a command on port %d\n",
+                       qc->ap->port_no);
+               do {
+                       mdelay(1);
+                       if (++count > 100) {
+                               DPRINTK("core busy for a command on port %d\n",
+                                       qc->ap->port_no);
+                               /* CrazyDumpDebug(); */
+                               sata_oxnas_cleanup(qc->ap->host);
+                       }
+               } while (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY);
+       }
+
+       /* enable passing of error signals to DMA sub-core by clearing the
+        * appropriate bit (all transfers are on dma channel 0) */
+       reg = ioread32(core_base + DATA_PLANE_CTRL);
+       reg &= ~(DPC_ERROR_MASK_BIT << port_no);
+       iowrite32(reg, core_base + DATA_PLANE_CTRL);
+
+       /* Disable all interrupts for ports and RAID controller */
+       iowrite32(~0, port_base + INT_DISABLE);
+
+       /* Disable all interrupts for core */
+       iowrite32(~0, core_base + CORE_INT_DISABLE);
+       wmb();
+
+       /* Load the command settings into the orb registers */
+       sata_oxnas_tf_load(qc->ap, &qc->tf);
+
+       /* both pio and dma commands use dma */
+       if (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) {
+               /* Start the DMA */
+               iowrite32(SGDMA_CONTROL_GO,     pd->sgdma_base + SGDMA_CONTROL);
+               wmb();
+       }
+
+       /* enable End of command interrupt */
+       iowrite32(INT_WANT, port_base + INT_ENABLE);
+       iowrite32(COREINT_END, core_base + CORE_INT_ENABLE);
+       wmb();
+
+       /* Start the command */
+       reg = ioread32(port_base + SATA_COMMAND);
+       reg &= ~SATA_OPCODE_MASK;
+       reg |= CMD_WRITE_TO_ORB_REGS;
+       iowrite32(reg , port_base + SATA_COMMAND);
+       wmb();
+
+       return 0;
+}
+
+/**
+ * Will schedule the libATA error handler on the premise that there has
+ * been a hotplug event on the port specified
+ */
+void sata_oxnas_checkforhotplug(struct ata_port *ap)
+{
+       DPRINTK("ENTER\n");
+
+       ata_ehi_hotplugged(&ap->link.eh_info);
+       ata_port_freeze(ap);
+}
+
+
+static inline int sata_oxnas_is_host_frozen(struct ata_host *ah)
+{
+       struct sata_oxnas_host_priv *hd = ah->private_data;
+
+       smp_rmb();
+       return hd->port_in_eh;
+}
+
+static inline u32 sata_oxnas_hostportbusy(struct ata_port *ap)
+{
+       struct sata_oxnas_port_priv *pd = ap->private_data;
+
+       return ioread32(pd->port_base + SATA_COMMAND) & CMD_CORE_BUSY;
+}
+
+static inline u32 sata_oxnas_hostdmabusy(struct ata_port *ap)
+{
+       struct sata_oxnas_port_priv *pd = ap->private_data;
+
+       return ioread32(pd->sgdma_base + SGDMA_STATUS) & SGDMA_BUSY;
+}
+
+
+/**
+ * Turns on the cores clock and resets it
+ */
+static void sata_oxnas_reset_core(struct ata_host *ah)
+{
+       struct sata_oxnas_host_priv *host_priv = ah->private_data;
+
+       DPRINTK("ENTER\n");
+       clk_prepare_enable(host_priv->clk);
+
+       reset_control_assert(host_priv->rst_sata);
+       reset_control_assert(host_priv->rst_link);
+       reset_control_assert(host_priv->rst_phy);
+
+       udelay(50);
+
+       /* un-reset the PHY, then Link and Controller */
+       reset_control_deassert(host_priv->rst_phy);
+       udelay(50);
+
+       reset_control_deassert(host_priv->rst_sata);
+       reset_control_deassert(host_priv->rst_link);
+       udelay(50);
+
+       workaround5458(ah);
+       /* tune for sata compatability */
+       sata_oxnas_link_write(ah->ports[0], 0x60, 0x2988);
+
+       /* each port in turn */
+       sata_oxnas_link_write(ah->ports[0], 0x70, 0x55629);
+       udelay(50);
+}
+
+
+/**
+ * Called after an identify device command has worked out what kind of device
+ * is on the port
+ *
+ * @param port The port to configure
+ * @param pdev The hardware associated with controlling the port
+ */
+static void sata_oxnas_dev_config(struct ata_device *pdev)
+{
+       struct sata_oxnas_port_priv *pd = pdev->link->ap->private_data;
+       void __iomem *port_base = pd->port_base;
+       u32 reg;
+
+       DPRINTK("ENTER\n");
+       /* Set the bits to put the port into 28 or 48-bit node */
+       reg = ioread32(port_base + DRIVE_CONTROL);
+       reg &= ~3;
+       reg |= (pdev->flags & ATA_DFLAG_LBA48) ? DR_CON_48 : DR_CON_28;
+       iowrite32(reg, port_base + DRIVE_CONTROL);
+
+       /* if this is an ATA-6 disk, put port into ATA-5 auto translate mode */
+       if (pdev->flags & ATA_DFLAG_LBA48) {
+               reg = ioread32(port_base + PORT_CONTROL);
+               reg |= 2;
+               iowrite32(reg, port_base + PORT_CONTROL);
+       }
+}
+/**
+ * called to write a taskfile into the ORB registers
+ * @param ap hardware with the registers in
+ * @param tf taskfile to write to the registers
+ */
+static void sata_oxnas_tf_load(struct ata_port *ap,
+                               const struct ata_taskfile *tf)
+{
+       u32 count = 0;
+       u32 Orb1 = 0;
+       u32 Orb2 = 0;
+       u32 Orb3 = 0;
+       u32 Orb4 = 0;
+       u32 Command_Reg;
+
+       struct sata_oxnas_port_priv *port_priv = ap->private_data;
+       void __iomem *port_base = port_priv->port_base;
+       unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
+
+       /* wait a maximum of 10ms for the core to be idle */
+       do {
+               Command_Reg = ioread32(port_base + SATA_COMMAND);
+               if (!(Command_Reg & CMD_CORE_BUSY))
+                       break;
+               count++;
+               udelay(50);
+       } while (count < 200);
+
+       /* check if the ctl register has interrupts disabled or enabled and
+        * modify the interrupt enable registers on the ata core as required */
+       if (tf->ctl & ATA_NIEN) {
+               /* interrupts disabled */
+               u32 mask = (COREINT_END << ap->port_no);
+
+               iowrite32(mask, port_priv->core_base + CORE_INT_DISABLE);
+               sata_oxnas_irq_clear(ap);
+       } else {
+               sata_oxnas_irq_on(ap);
+       }
+
+       Orb2 |= (tf->command) << 24;
+
+       /* write 48 or 28 bit tf parameters */
+       if (is_addr) {
+               /* set LBA bit as it's an address */
+               Orb1 |= (tf->device & ATA_LBA) << 24;
+
+               if (tf->flags & ATA_TFLAG_LBA48) {
+                       Orb1 |= ATA_LBA << 24;
+                       Orb2 |= (tf->hob_nsect) << 8;
+                       Orb3 |= (tf->hob_lbal) << 24;
+                       Orb4 |= (tf->hob_lbam) << 0;
+                       Orb4 |= (tf->hob_lbah) << 8;
+                       Orb4 |= (tf->hob_feature) << 16;
+               } else {
+                       Orb3 |= (tf->device & 0xf) << 24;
+               }
+
+               /* write 28-bit lba */
+               Orb2 |= (tf->nsect) << 0;
+               Orb2 |= (tf->feature) << 16;
+               Orb3 |= (tf->lbal) << 0;
+               Orb3 |= (tf->lbam) << 8;
+               Orb3 |= (tf->lbah) << 16;
+               Orb4 |= (tf->ctl) << 24;
+       }
+
+       if (tf->flags & ATA_TFLAG_DEVICE)
+               Orb1 |= (tf->device) << 24;
+
+       ap->last_ctl = tf->ctl;
+
+       /* write values to registers */
+       iowrite32(Orb1, port_base + ORB1);
+       iowrite32(Orb2, port_base + ORB2);
+       iowrite32(Orb3, port_base + ORB3);
+       iowrite32(Orb4, port_base + ORB4);
+}
+
+
+void sata_oxnas_set_mode(struct ata_port *ap, u32 mode, u32 force)
+{
+       struct sata_oxnas_port_priv *port_priv = ap->private_data;
+       void __iomem *core_base = port_priv->core_base;
+
+       unsigned int *src;
+       void __iomem *dst;
+       unsigned int progmicrocode = 0;
+       unsigned int changeparameters = 0;
+       static u32 previous_mode = UNKNOWN_MODE;
+
+       /* these micro-code programs _should_ include the version word */
+
+       /* JBOD */
+       static const unsigned int jbod[] = {
+               0x07B400AC, 0x0228A280, 0x00200001, 0x00204002, 0x00224001,
+               0x00EE0009, 0x00724901, 0x01A24903, 0x00E40009, 0x00224001,
+               0x00621120, 0x0183C908, 0x00E20005, 0x00718908, 0x0198A206,
+               0x00621124, 0x0183C908, 0x00E20046, 0x00621104, 0x0183C908,
+               0x00E20015, 0x00EE009D, 0x01A3E301, 0x00E2001B, 0x0183C900,
+               0x00E2001B, 0x00210001, 0x00EE0020, 0x01A3E302, 0x00E2009D,
+               0x0183C901, 0x00E2009D, 0x00210002, 0x0235D700, 0x0208A204,
+               0x0071C908, 0x000F8207, 0x000FC207, 0x0071C920, 0x000F8507,
+               0x000FC507, 0x0228A240, 0x02269A40, 0x00094004, 0x00621104,
+               0x0180C908, 0x00E40031, 0x00621112, 0x01A3C801, 0x00E2002B,
+               0x00294000, 0x0228A220, 0x01A69ABF, 0x002F8000, 0x002FC000,
+               0x0198A204, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
+               0x0183C903, 0x00E2009D, 0x0228A220, 0x0071890C, 0x0208A206,
+               0x0198A206, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
+               0x00EE009D, 0x00621104, 0x0183C908, 0x00E2004A, 0x00EE009D,
+               0x01A3C901, 0x00E20050, 0x0021E7FF, 0x0183E007, 0x00E2009D,
+               0x00EE0054, 0x0061600B, 0x0021E7FF, 0x0183C507, 0x00E2009D,
+               0x01A3E301, 0x00E2005A, 0x0183C900, 0x00E2005A, 0x00210001,
+               0x00EE005F, 0x01A3E302, 0x00E20005, 0x0183C901, 0x00E20005,
+               0x00210002, 0x0235D700, 0x0208A204, 0x000F8109, 0x000FC109,
+               0x0071C918, 0x000F8407, 0x000FC407, 0x0001C022, 0x01A1A2BF,
+               0x0001C106, 0x00088007, 0x02269A40, 0x00094004, 0x00621112,
+               0x01A3C801, 0x00E4007F, 0x00621104, 0x0180C908, 0x00E4008D,
+               0x00621128, 0x0183C908, 0x00E2006C, 0x01A3C901, 0x00E2007B,
+               0x0021E7FF, 0x0183E007, 0x00E2007F, 0x00EE006C, 0x0061600B,
+               0x0021E7FF, 0x0183C507, 0x00E4006C, 0x00621111, 0x01A3C801,
+               0x00E2007F, 0x00621110, 0x01A3C801, 0x00E20082, 0x0228A220,
+               0x00621119, 0x01A3C801, 0x00E20086, 0x0001C022, 0x01B1A220,
+               0x0001C106, 0x00088007, 0x0198A204, 0x00294000, 0x01A69ABF,
+               0x002F8000, 0x002FC000, 0x0183C903, 0x00E20005, 0x0228A220,
+               0x0071890C, 0x0208A206, 0x0198A206, 0x0001C022, 0x01B1A220,
+               0x0001C106, 0x00088007, 0x00EE009D, 0x00621128, 0x0183C908,
+               0x00E20005, 0x00621104, 0x0183C908, 0x00E200A6, 0x0062111C,
+               0x0183C908, 0x00E20005, 0x0071890C, 0x0208A206, 0x0198A206,
+               0x00718908, 0x0208A206, 0x00EE0005, ~0
+       };
+
+       /* Bi-Modal RAID-0/1 */
+       static const unsigned int raid[] = {
+               0x00F20145, 0x00EE20FA, 0x00EE20A7, 0x0001C009, 0x00EE0004,
+               0x00220000, 0x0001000B, 0x037003FF, 0x00700018, 0x037003FE,
+               0x037043FD, 0x00704118, 0x037043FC, 0x01A3D240, 0x00E20017,
+               0x00B3C235, 0x00E40018, 0x0093C104, 0x00E80014, 0x0093C004,
+               0x00E80017, 0x01020000, 0x00274020, 0x00EE0083, 0x0080C904,
+               0x0093C104, 0x00EA0020, 0x0093C103, 0x00EC001F, 0x00220002,
+               0x00924104, 0x0005C009, 0x00EE0058, 0x0093CF04, 0x00E80026,
+               0x00900F01, 0x00600001, 0x00910400, 0x00EE0058, 0x00601604,
+               0x01A00003, 0x00E2002C, 0x01018000, 0x00274040, 0x00EE0083,
+               0x0093CF03, 0x00EC0031, 0x00220003, 0x00924F04, 0x0005C009,
+               0x00810104, 0x00B3C235, 0x00E20037, 0x0022C000, 0x00218210,
+               0x00EE0039, 0x0022C001, 0x00218200, 0x00600401, 0x00A04901,
+               0x00604101, 0x01A0C401, 0x00E20040, 0x00216202, 0x00EE0041,
+               0x00216101, 0x02018506, 0x00EE2141, 0x00904901, 0x00E20049,
+               0x00A00401, 0x00600001, 0x02E0C301, 0x00EE2141, 0x00216303,
+               0x037003EE, 0x01A3C001, 0x00E40105, 0x00250080, 0x00204000,
+               0x002042F1, 0x0004C001, 0x00230001, 0x00100006, 0x02C18605,
+               0x00100006, 0x01A3D502, 0x00E20055, 0x00EE0053, 0x00004009,
+               0x00000004, 0x00B3C235, 0x00E40062, 0x0022C001, 0x0020C000,
+               0x00EE2141, 0x0020C001, 0x00EE2141, 0x00EE006B, 0x0022C000,
+               0x0060D207, 0x00EE2141, 0x00B3C242, 0x00E20069, 0x01A3D601,
+               0x00E2006E, 0x02E0C301, 0x00EE2141, 0x00230001, 0x00301303,
+               0x00EE007B, 0x00218210, 0x01A3C301, 0x00E20073, 0x00216202,
+               0x00EE0074, 0x00216101, 0x02018506, 0x00214000, 0x037003EE,
+               0x01A3C001, 0x00E40108, 0x00230001, 0x00100006, 0x00250080,
+               0x00204000, 0x002042F1, 0x0004C001, 0x00EE007F, 0x0024C000,
+               0x01A3D1F0, 0x00E20088, 0x00230001, 0x00300000, 0x01A3D202,
+               0x00E20085, 0x00EE00A5, 0x00B3C800, 0x00E20096, 0x00218000,
+               0x00924709, 0x0005C009, 0x00B20802, 0x00E40093, 0x037103FD,
+               0x00710418, 0x037103FC, 0x00EE0006, 0x00220000, 0x0001000F,
+               0x00EE0006, 0x00800B0C, 0x00B00001, 0x00204000, 0x00208550,
+               0x00208440, 0x002083E0, 0x00208200, 0x00208100, 0x01008000,
+               0x037083EE, 0x02008212, 0x02008216, 0x01A3C201, 0x00E400A5,
+               0x0100C000, 0x00EE20FA, 0x02800000, 0x00208000, 0x00B24C00,
+               0x00E400AD, 0x00224001, 0x00724910, 0x0005C009, 0x00B3CDC4,
+               0x00E200D5, 0x00B3CD29, 0x00E200D5, 0x00B3CD20, 0x00E200D5,
+               0x00B3CD24, 0x00E200D5, 0x00B3CDC5, 0x00E200D2, 0x00B3CD39,
+               0x00E200D2, 0x00B3CD30, 0x00E200D2, 0x00B3CD34, 0x00E200D2,
+               0x00B3CDCA, 0x00E200CF, 0x00B3CD35, 0x00E200CF, 0x00B3CDC8,
+               0x00E200CC, 0x00B3CD25, 0x00E200CC, 0x00B3CD40, 0x00E200CB,
+               0x00B3CD42, 0x00E200CB, 0x01018000, 0x00EE0083, 0x0025C000,
+               0x036083EE, 0x0000800D, 0x00EE00D8, 0x036083EE, 0x00208035,
+               0x00EE00DA, 0x036083EE, 0x00208035, 0x00EE00DA, 0x00208007,
+               0x036083EE, 0x00208025, 0x036083EF, 0x02400000, 0x01A3D208,
+               0x00E200D8, 0x0067120A, 0x0021C000, 0x0021C224, 0x00220000,
+               0x00404B1C, 0x00600105, 0x00800007, 0x0020C00E, 0x00214000,
+               0x01004000, 0x01A0411F, 0x00404E01, 0x01A3C101, 0x00E200F1,
+               0x00B20800, 0x00E400D8, 0x00220001, 0x0080490B, 0x00B04101,
+               0x0040411C, 0x00EE00E1, 0x02269A01, 0x01020000, 0x02275D80,
+               0x01A3D202, 0x00E200F4, 0x01B75D80, 0x01030000, 0x01B69A01,
+               0x00EE00D8, 0x01A3D204, 0x00E40104, 0x00224000, 0x0020C00E,
+               0x0020001E, 0x00214000, 0x01004000, 0x0212490E, 0x00214001,
+               0x01004000, 0x02400000, 0x00B3D702, 0x00E80112, 0x00EE010E,
+               0x00B3D702, 0x00E80112, 0x00B3D702, 0x00E4010E, 0x00230001,
+               0x00EE0140, 0x00200005, 0x036003EE, 0x00204001, 0x00EE0116,
+               0x00230001, 0x00100006, 0x02C18605, 0x00100006, 0x01A3D1F0,
+               0x00E40083, 0x037003EE, 0x01A3C002, 0x00E20121, 0x0020A300,
+               0x0183D102, 0x00E20124, 0x037003EE, 0x01A00005, 0x036003EE,
+               0x01A0910F, 0x00B3C20F, 0x00E2012F, 0x01A3D502, 0x00E20116,
+               0x01A3C002, 0x00E20116, 0x00B3D702, 0x00E4012C, 0x00300000,
+               0x00EE011F, 0x02C18605, 0x00100006, 0x00EE0116, 0x01A3D1F0,
+               0x00E40083, 0x037003EE, 0x01A3C004, 0x00E20088, 0x00200003,
+               0x036003EE, 0x01A3D502, 0x00E20136, 0x00230001, 0x00B3C101,
+               0x00E4012C, 0x00100006, 0x02C18605, 0x00100006, 0x00204000,
+               0x00EE0116, 0x00100006, 0x01A3D1F0, 0x00E40083, 0x01000000,
+               0x02400000, ~0
+       };
+
+       if (force)
+               previous_mode = UNKNOWN_MODE;
+
+       if (mode == previous_mode)
+               return;
+
+       /* decide what needs to be done using the STD in my logbook */
+       switch (previous_mode) {
+       case OXNASSATA_RAID1:
+               switch (mode) {
+               case OXNASSATA_RAID0:
+                       changeparameters = 1;
+                       break;
+               case OXNASSATA_NOTRAID:
+                       changeparameters = 1;
+                       progmicrocode = 1;
+                       break;
+               }
+               break;
+       case OXNASSATA_RAID0:
+               switch (mode) {
+               case OXNASSATA_RAID1:
+                       changeparameters = 1;
+                       break;
+               case OXNASSATA_NOTRAID:
+                       changeparameters = 1;
+                       progmicrocode = 1;
+                       break;
+               }
+               break;
+       case OXNASSATA_NOTRAID:
+       case UNKNOWN_MODE:
+               changeparameters = 1;
+               progmicrocode = 1;
+               break;
+       }
+
+       /* no need to reprogram everything if already in the right mode */
+       if (progmicrocode) {
+               /* reset micro-code processor */
+               iowrite32(1, core_base + PROC_RESET);
+               wmb();
+
+               /* select micro-code */
+               switch (mode) {
+               case OXNASSATA_RAID1:
+               case OXNASSATA_RAID0:
+                       VPRINTK("Loading RAID micro-code\n");
+                       src = (unsigned int *)&raid[1];
+                       break;
+               case OXNASSATA_NOTRAID:
+                       VPRINTK("Loading JBOD micro-code\n");
+                       src = (unsigned int *)&jbod[1];
+                       break;
+               default:
+                       BUG();
+                       break;
+               }
+
+               /* load micro code */
+               dst = core_base + UCODE_STORE;
+               while (*src != ~0) {
+                       iowrite32(*src, dst);
+                       src++;
+                       dst += sizeof(*src);
+               }
+               wmb();
+       }
+
+       if (changeparameters) {
+               u32 reg;
+               /* set other mode dependent flags */
+               switch (mode) {
+               case OXNASSATA_RAID1:
+                       /* clear JBOD mode */
+                       reg = ioread32(core_base + DATA_PLANE_CTRL);
+                       reg |= DPC_JBOD_UCODE;
+                       reg &= ~DPC_FIS_SWCH;
+                       iowrite32(reg, core_base + DATA_PLANE_CTRL);
+                       wmb();
+
+                       /* set the hardware up for RAID-1 */
+                       iowrite32(0, core_base + RAID_WP_BOT_LOW);
+                       iowrite32(0, core_base + RAID_WP_BOT_HIGH);
+                       iowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW);
+                       iowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH);
+                       iowrite32(0, core_base + RAID_SIZE_LOW);
+                       iowrite32(0, core_base + RAID_SIZE_HIGH);
+                       wmb();
+                       break;
+               case OXNASSATA_RAID0:
+                       /* clear JBOD mode */
+                       reg = ioread32(core_base + DATA_PLANE_CTRL);
+                       reg |= DPC_JBOD_UCODE;
+                       reg &= ~DPC_FIS_SWCH;
+                       iowrite32(reg, core_base + DATA_PLANE_CTRL);
+                       wmb();
+
+                       /* set the hardware up for RAID-1 */
+                       iowrite32(0, core_base + RAID_WP_BOT_LOW);
+                       iowrite32(0, core_base + RAID_WP_BOT_HIGH);
+                       iowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW);
+                       iowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH);
+                       iowrite32(0xffffffff, core_base + RAID_SIZE_LOW);
+                       iowrite32(0x7fffffff, core_base + RAID_SIZE_HIGH);
+                       wmb();
+                       break;
+               case OXNASSATA_NOTRAID:
+                       /* enable jbod mode */
+                       reg = ioread32(core_base + DATA_PLANE_CTRL);
+                       reg &= ~DPC_JBOD_UCODE;
+                       reg |= DPC_FIS_SWCH;
+                       iowrite32(reg, core_base + DATA_PLANE_CTRL);
+                       wmb();
+
+                       /* start micro-code processor*/
+                       iowrite32(1, core_base + PROC_START);
+                       break;
+               default:
+                       break;
+               }
+       }
+
+       previous_mode = mode;
+}
+
+/**
+ * sends a sync-escape if there is a link present
+ */
+static inline void sata_oxnas_send_sync_escape(struct ata_port *ap)
+{
+       struct sata_oxnas_port_priv *pd = ap->private_data;
+       u32 reg;
+
+       /* read the SSTATUS register and only send a sync escape if there is a
+       * link active */
+       if ((sata_oxnas_link_read(ap, 0x20) & 3) == 3) {
+               reg = ioread32(pd->port_base + SATA_COMMAND);
+               reg &= ~SATA_OPCODE_MASK;
+               reg |= CMD_SYNC_ESCAPE;
+               iowrite32(reg, pd->port_base + SATA_COMMAND);
+       }
+}
+
+/* clears errors */
+static inline void sata_oxnas_clear_CS_error(u32 *base)
+{
+       u32 reg;
+
+       reg = ioread32(base + SATA_CONTROL);
+       reg &= SATA_CTL_ERR_MASK;
+       iowrite32(reg, base + SATA_CONTROL);
+}
+
+/**
+ * Clears the error caused by the core's registers being accessed when the
+ * core is busy.
+ */
+static inline void sata_oxnas_clear_reg_access_error(u32 *base)
+{
+       u32 reg;
+
+       reg = ioread32(base + INT_STATUS);
+
+       DPRINTK("ENTER\n");
+       if (reg & INT_REG_ACCESS_ERR) {
+               printk(KERN_INFO "clearing register access error\n");
+               iowrite32(INT_REG_ACCESS_ERR, base + INT_STATUS);
+       }
+       if (reg & INT_REG_ACCESS_ERR)
+               printk(KERN_INFO "register access error didn't clear\n");
+}
+
+/**
+ * Clean up all the state machines in the sata core.
+ * @return post cleanup action required
+ */
+static int sata_oxnas_cleanup(struct ata_host *ah)
+{
+       int actions_required = 0;
+
+       printk(KERN_INFO "ox820sata: reseting SATA core\n");
+
+       /* core not recovering, reset it */
+       mdelay(5);
+       sata_oxnas_reset_core(ah);
+       mdelay(5);
+       actions_required |= OXNAS_SATA_REINIT;
+       /* Perform any SATA core re-initialisation after reset post reset init
+        * needs to be called for both ports as there's one reset for both
+        * ports */
+
+       sata_oxnas_post_reset_init(ah->ports[0]);
+
+       return actions_required;
+}
+
+void sata_oxnas_freeze_host(struct ata_port *ap)
+{
+       struct sata_oxnas_host_priv *hd = ap->host->private_data;
+
+       DPRINTK("ENTER\n");
+       hd->port_in_eh |= BIT(ap->port_no);
+       smp_wmb();
+}
+
+void sata_oxnas_thaw_host(struct ata_port *ap)
+{
+       struct sata_oxnas_host_priv *hd = ap->host->private_data;
+
+       DPRINTK("ENTER\n");
+       hd->port_in_eh &= ~BIT(ap->port_no);
+       smp_wmb();
+}
+
+static void sata_oxnas_post_internal_cmd(struct ata_queued_cmd *qc)
+{
+       DPRINTK("ENTER\n");
+       /* If the core is busy here, make it idle */
+       if (qc->flags & ATA_QCFLAG_FAILED)
+               sata_oxnas_cleanup(qc->ap->host);
+}
+
+
+/**
+ * turn on the interrupts
+ *
+ * @param ap Hardware with the registers in
+ */
+static void sata_oxnas_irq_on(struct ata_port *ap)
+{
+       struct sata_oxnas_port_priv *pd = ap->private_data;
+       u32 mask = (COREINT_END << ap->port_no);
+
+       /* Clear pending interrupts */
+       iowrite32(~0, pd->port_base + INT_CLEAR);
+       iowrite32(mask, pd->core_base + CORE_INT_STATUS);
+       wmb();
+
+       /* enable End of command interrupt */
+       iowrite32(INT_WANT, pd->port_base + INT_ENABLE);
+       iowrite32(mask, pd->core_base + CORE_INT_ENABLE);
+}
+
+
+/** @return true if the port has a cable connected */
+int sata_oxnas_check_link(struct ata_port *ap)
+{
+       int reg;
+
+       sata_oxnas_scr_read_port(ap, SCR_STATUS, &reg);
+       /* Check for the cable present indicated by SCR status bit-0 set */
+       return reg & 0x1;
+}
+
+/**
+ *     ata_std_postreset - standard postreset callback
+ *     @link: the target ata_link
+ *     @classes: classes of attached devices
+ *
+ *     This function is invoked after a successful reset. Note that
+ *     the device might have been reset more than once using
+ *     different reset methods before postreset is invoked.
+ *
+ *     LOCKING:
+ *     Kernel thread context (may sleep)
+ */
+static void sata_oxnas_postreset(struct ata_link *link, unsigned int *classes)
+{
+       struct ata_port *ap = link->ap;
+
+       unsigned int dev;
+
+       DPRINTK("ENTER\n");
+       ata_std_postreset(link, classes);
+
+       /* turn on phy error detection by removing the masks */
+       sata_oxnas_link_write(ap , 0x0c, 0x30003);
+
+       /* bail out if no device is present */
+       if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
+               DPRINTK("EXIT, no device\n");
+               return;
+       }
+
+       /* go through all the devices and configure them */
+       for (dev = 0; dev < ATA_MAX_DEVICES; ++dev) {
+               if (ap->link.device[dev].class == ATA_DEV_ATA)
+                       sata_oxnas_dev_config(&(ap->link.device[dev]));
+       }
+
+       DPRINTK("EXIT\n");
+}
+
+/**
+ * Called to read the hardware registers / DMA buffers, to
+ * obtain the current set of taskfile register values.
+ * @param ap hardware with the registers in
+ * @param tf taskfile to read the registers into
+ */
+static void sata_oxnas_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
+{
+       struct sata_oxnas_port_priv *port_priv = ap->private_data;
+       void __iomem *port_base = port_priv->port_base;
+       /* read the orb registers */
+       u32 Orb1 = ioread32(port_base + ORB1);
+       u32 Orb2 = ioread32(port_base + ORB2);
+       u32 Orb3 = ioread32(port_base + ORB3);
+       u32 Orb4 = ioread32(port_base + ORB4);
+
+       /* read common 28/48 bit tf parameters */
+       tf->device = (Orb1 >> 24);
+       tf->nsect = (Orb2 >> 0);
+       tf->feature = (Orb2 >> 16);
+       tf->command = sata_oxnas_check_status(ap);
+
+       /* read 48 or 28 bit tf parameters */
+       if (tf->flags & ATA_TFLAG_LBA48) {
+               tf->hob_nsect = (Orb2 >> 8);
+               tf->lbal = (Orb3 >> 0);
+               tf->lbam = (Orb3 >> 8);
+               tf->lbah = (Orb3 >> 16);
+               tf->hob_lbal = (Orb3 >> 24);
+               tf->hob_lbam = (Orb4 >> 0);
+               tf->hob_lbah = (Orb4 >> 8);
+               /* feature ext and control are write only */
+       } else {
+               /* read 28-bit lba */
+               tf->lbal = (Orb3 >> 0);
+               tf->lbam = (Orb3 >> 8);
+               tf->lbah = (Orb3 >> 16);
+       }
+}
+
+/**
+ * Read a result task-file from the sata core registers.
+ */
+static bool sata_oxnas_qc_fill_rtf(struct ata_queued_cmd *qc)
+{
+       /* Read the most recently received FIS from the SATA core ORB registers
+        and convert to an ATA taskfile */
+       sata_oxnas_tf_read(qc->ap, &qc->result_tf);
+       return true;
+}
+
+/**
+ * Reads the Status ATA shadow register from hardware.
+ *
+ * @return The status register
+ */
+static u8 sata_oxnas_check_status(struct ata_port *ap)
+{
+       u32 Reg;
+       u8 status;
+       struct sata_oxnas_port_priv *port_priv = ap->private_data;
+       void __iomem *port_base = port_priv->port_base;
+
+       /* read byte 3 of Orb2 register */
+       status = ioread32(port_base + ORB2) >> 24;
+
+       /* check for the drive going missing indicated by SCR status bits
+        * 0-3 = 0 */
+       sata_oxnas_scr_read_port(ap, SCR_STATUS, &Reg);
+
+       if (!(Reg & 0x1)) {
+               status |= ATA_DF;
+               status |= ATA_ERR;
+       }
+
+       return status;
+}
+
+/**
+ * Prepare as much as possible for a command without involving anything that is
+ * shared between ports.
+ */
+static void sata_oxnas_qc_prep(struct ata_queued_cmd *qc)
+{
+       struct sata_oxnas_port_priv *pd;
+       int port_no = qc->ap->port_no;
+
+       /* if the port's not connected, complete now with an error */
+       /*
+       if (!sata_oxnas_check_link(qc->ap)) {
+               printk(KERN_ERR "port %d not connected completing with error\n",
+                       qc->ap->port_no);
+               qc->err_mask |= AC_ERR_ATA_BUS;
+               ata_qc_complete(qc);
+       }
+       */
+       /* both pio and dma commands use dma */
+       if (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) {
+               /* program the scatterlist into the prd table */
+               ata_bmdma_qc_prep(qc);
+
+               /* point the sgdma controller at the dma request structure */
+               pd = qc->ap->private_data;
+
+               iowrite32(pd->sgdma_request_pa,
+                               pd->sgdma_base + SGDMA_REQUESTPTR);
+
+               /* setup the request table */
+               if (port_no == 0) {
+                       pd->sgdma_request->control =
+                               (qc->dma_dir == DMA_FROM_DEVICE) ?
+                                       SGDMA_REQCTL0IN : SGDMA_REQCTL0OUT;
+               } else {
+                       pd->sgdma_request->control =
+                               (qc->dma_dir == DMA_FROM_DEVICE) ?
+                                       SGDMA_REQCTL1IN : SGDMA_REQCTL1OUT;
+               }
+               pd->sgdma_request->qualifier = SGDMA_REQQUAL;
+               pd->sgdma_request->src_pa = qc->ap->bmdma_prd_dma;
+               pd->sgdma_request->dst_pa = qc->ap->bmdma_prd_dma;
+               smp_wmb();
+
+               /* tell it to wait */
+               iowrite32(SGDMA_CONTROL_NOGO, pd->sgdma_base + SGDMA_CONTROL);
+       }
+}
+
+static int sata_oxnas_port_start(struct ata_port *ap)
+{
+       struct sata_oxnas_host_priv *host_priv = ap->host->private_data;
+       struct device *dev = ap->host->dev;
+       struct sata_oxnas_port_priv *pp;
+       void *mem;
+       dma_addr_t mem_dma;
+
+       DPRINTK("ENTER\n");
+
+       pp = kzalloc(sizeof(*pp), GFP_KERNEL);
+       if (!pp)
+               return -ENOMEM;
+
+       pp->port_base = host_priv->port_base[ap->port_no];
+       pp->sgdma_base = host_priv->sgdma_base[ap->port_no];
+       pp->core_base = host_priv->core_base;
+
+       /* preallocated */
+       if (host_priv->dma_size >= SATA_OXNAS_DMA_SIZE * SATA_OXNAS_MAX_PORTS) {
+               mem_dma = host_priv->dma_base +
+                               ap->port_no * SATA_OXNAS_DMA_SIZE;
+               mem = ioremap(mem_dma, SATA_OXNAS_DMA_SIZE);
+
+       } else {
+               mem = dma_alloc_coherent(dev, SATA_OXNAS_DMA_SIZE, &mem_dma,
+                                        GFP_KERNEL);
+       }
+       if (!mem)
+               goto err_ret;
+
+       pp->sgdma_request_pa = mem_dma;
+       pp->sgdma_request = mem;
+       ap->bmdma_prd_dma = mem_dma + sizeof(struct sgdma_request);
+       ap->bmdma_prd = mem +  sizeof(struct sgdma_request);
+
+       ap->private_data = pp;
+
+       sata_oxnas_post_reset_init(ap);
+
+       return 0;
+
+err_ret:
+       kfree(pp);
+       return -ENOMEM;
+
+}
+
+static void sata_oxnas_port_stop(struct ata_port *ap)
+{
+       struct device *dev = ap->host->dev;
+       struct sata_oxnas_port_priv *pp = ap->private_data;
+       struct sata_oxnas_host_priv *host_priv = ap->host->private_data;
+
+       DPRINTK("ENTER\n");
+       ap->private_data = NULL;
+       if (host_priv->dma_size) {
+               iounmap(pp->sgdma_request);
+       } else {
+               dma_free_coherent(dev, SATA_OXNAS_DMA_SIZE,
+                                 pp->sgdma_request, pp->sgdma_request_pa);
+       }
+
+       kfree(pp);
+}
+
+static void sata_oxnas_post_reset_init(struct ata_port *ap)
+{
+       struct sata_oxnas_port_priv *pd = ap->private_data;
+       uint dev;
+       int no_microcode = 0;
+
+       DPRINTK("ENTER\n");
+       if (no_microcode) {
+               u32 reg;
+               sata_oxnas_set_mode(ap, UNKNOWN_MODE, 1);
+               reg = readl(pd->core_base + DEVICE_CONTROL);
+               reg |= DEVICE_CONTROL_ATA_ERR_OVERRIDE;
+               writel(reg, pd->core_base + DEVICE_CONTROL);
+       } else {
+               /* JBOD uCode */
+               sata_oxnas_set_mode(ap, OXNASSATA_NOTRAID, 1);
+               /* Turn the work around off as it may have been left on by any
+                * HW-RAID code that we've been working with */
+               writel(0x0, pd->core_base + PORT_ERROR_MASK);
+       }
+       /* turn on phy error detection by removing the masks */
+       sata_oxnas_link_write(ap, 0x0C, 0x30003);
+
+       /* enable hotplug event detection */
+       sata_oxnas_scr_write_port(ap, SCR_ERROR, ~0);
+       sata_oxnas_scr_write_port(ap, SERROR_IRQ_MASK, 0x03feffff);
+       sata_oxnas_scr_write_port(ap, SCR_ACTIVE, ~0 & ~(1 << 26) & ~(1 << 16));
+
+       /* enable interrupts for ports */
+       sata_oxnas_irq_on(ap);
+
+       /* go through all the devices and configure them */
+       for (dev = 0; dev < ATA_MAX_DEVICES; ++dev) {
+               if (ap->link.device[dev].class == ATA_DEV_ATA) {
+                       sata_std_hardreset(&ap->link, NULL, jiffies + HZ);
+                       sata_oxnas_dev_config(&(ap->link.device[dev]));
+               }
+       }
+
+       /* clean up any remaining errors */
+       sata_oxnas_scr_write_port(ap, SCR_ERROR, ~0);
+       VPRINTK("done\n");
+}
+
+/**
+ * host_stop() is called when the rmmod or hot unplug process begins. The
+ * hook must stop all hardware interrupts, DMA engines, etc.
+ *
+ * @param ap hardware with the registers in
+ */
+static void sata_oxnas_host_stop(struct ata_host *host_set)
+{
+       DPRINTK("\n");
+}
+
+
+#define ERROR_HW_ACQUIRE_TIMEOUT_JIFFIES (10 * HZ)
+static void sata_oxnas_error_handler(struct ata_port *ap)
+{
+       DPRINTK("Enter port_no %d\n", ap->port_no);
+       sata_oxnas_freeze_host(ap);
+
+       /* If the core is busy here, make it idle */
+       sata_oxnas_cleanup(ap->host);
+
+       ata_std_error_handler(ap);
+
+       sata_oxnas_thaw_host(ap);
+}
+
+static int sata_oxnas_softreset(struct ata_link *link, unsigned int *class,
+                                unsigned long deadline)
+{
+       struct ata_port *ap = link->ap;
+       struct sata_oxnas_port_priv *pd = ap->private_data;
+       void __iomem *port_base = pd->port_base;
+       int rc;
+
+       struct ata_taskfile tf;
+       u32 Command_Reg;
+
+       DPRINTK("ENTER\n");
+
+       port_base = pd->port_base;
+
+       if (ata_link_offline(link)) {
+               DPRINTK("PHY reports no device\n");
+               *class = ATA_DEV_NONE;
+               goto out;
+       }
+
+       /* write value to register */
+       iowrite32((ap->ctl) << 24, port_base + ORB4);
+
+       /* command the core to send a control FIS */
+       Command_Reg = ioread32(port_base + SATA_COMMAND);
+       Command_Reg &= ~SATA_OPCODE_MASK;
+       Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
+       iowrite32(Command_Reg, port_base + SATA_COMMAND);
+       udelay(20);     /* FIXME: flush */
+
+       /* write value to register */
+       iowrite32((ap->ctl | ATA_SRST) << 24, port_base + ORB4);
+
+       /* command the core to send a control FIS */
+       Command_Reg &= ~SATA_OPCODE_MASK;
+       Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
+       iowrite32(Command_Reg, port_base + SATA_COMMAND);
+       udelay(20);     /* FIXME: flush */
+
+       /* write value to register */
+       iowrite32((ap->ctl) << 24, port_base + ORB4);
+
+       /* command the core to send a control FIS */
+       Command_Reg &= ~SATA_OPCODE_MASK;
+       Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
+       iowrite32(Command_Reg, port_base + SATA_COMMAND);
+
+       msleep(150);
+
+       rc = ata_sff_wait_ready(link, deadline);
+
+       /* if link is occupied, -ENODEV too is an error */
+       if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
+               ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
+               return rc;
+       }
+
+       /* determine by signature whether we have ATA or ATAPI devices */
+       sata_oxnas_tf_read(ap, &tf);
+       *class = ata_dev_classify(&tf);
+
+       if (*class == ATA_DEV_UNKNOWN)
+               *class = ATA_DEV_NONE;
+
+out:
+       DPRINTK("EXIT, class=%u\n", *class);
+       return 0;
+}
+
+
+int    sata_oxnas_init_controller(struct ata_host *host)
+{
+       return 0;
+}
+
+/**
+ * Ref bug-6320
+ *
+ * This code is a work around for a DMA hardware bug that will repeat the
+ * penultimate 8-bytes on some reads. This code will check that the amount
+ * of data transferred is a multiple of 512 bytes, if not the in it will
+ * fetch the correct data from a buffer in the SATA core and copy it into
+ * memory.
+ *
+ * @param port SATA port to check and if necessary, correct.
+ */
+static int ox820sata_bug_6320_workaround(struct ata_port *ap)
+{
+       struct sata_oxnas_port_priv *pd = ap->private_data;
+       void __iomem *core_base = pd->core_base;
+       int is_read;
+       int quads_transferred;
+       int remainder;
+       int sector_quads_remaining;
+       int bug_present = 0;
+
+       /* Only want to apply fix to reads */
+       is_read = !(readl(core_base + DM_DBG1) & (ap->port_no ?
+                       BIT(CORE_PORT1_DATA_DIR_BIT) :
+                               BIT(CORE_PORT0_DATA_DIR_BIT)));
+
+       /* Check for an incomplete transfer, i.e. not a multiple of 512 bytes
+          transferred (datacount_port register counts quads transferred) */
+       quads_transferred =
+               readl(core_base + (ap->port_no ?
+                                       DATACOUNT_PORT1 : DATACOUNT_PORT0));
+
+       remainder = quads_transferred & 0x7f;
+       sector_quads_remaining = remainder ? (0x80 - remainder) : 0;
+
+       if (is_read && (sector_quads_remaining == 2)) {
+               bug_present = 1;
+       } else if (sector_quads_remaining) {
+               if (is_read) {
+                       printk(KERN_WARNING "SATA read fixup cannot deal with" \
+                               " %d quads remaining\n",
+                               sector_quads_remaining);
+               } else {
+                       printk(KERN_WARNING "SATA write fixup of %d quads" \
+                               " remaining not supported\n",
+                               sector_quads_remaining);
+               }
+       }
+
+       return bug_present;
+}
+
+/* This port done an interrupt */
+static void sata_oxnas_port_irq(struct ata_port *ap, int force_error)
+{
+       struct ata_queued_cmd *qc;
+       struct sata_oxnas_port_priv *pd = ap->private_data;
+       void __iomem *port_base = pd->port_base;
+
+       u32 int_status;
+       unsigned long flags = 0;
+
+       /* DPRINTK("ENTER irqstatus %x\n", ioread32(port_base + INT_STATUS)); */
+/*
+       if (ap->qc_active & (1 << ATA_TAG_INTERNAL)) {
+                       qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
+                       DPRINTK("completing non-ncq cmd\n");
+
+                       if (qc) {
+                               ata_qc_complete(qc);
+                       }
+                       return;
+       }
+*/
+
+       qc = ata_qc_from_tag(ap, ap->link.active_tag);
+
+
+       /* record the port's interrupt */
+       int_status = ioread32(port_base + INT_STATUS);
+
+       /* If there's no command associated with this IRQ, ignore it. We may get
+        * spurious interrupts when cleaning-up after a failed command, ignore
+        * these too. */
+       if (likely(qc)) {
+               /* get the status before any error cleanup */
+               qc->err_mask = ac_err_mask(sata_oxnas_check_status(ap));
+               if (force_error) {
+                       /* Pretend there has been a link error */
+                       qc->err_mask |= AC_ERR_ATA_BUS;
+                       DPRINTK(" ####force error####\n");
+               }
+               /* tell libata we're done */
+               local_irq_save(flags);
+               sata_oxnas_irq_clear(ap);
+               local_irq_restore(flags);
+               ata_qc_complete(qc);
+       } else {
+               VPRINTK("Ignoring interrupt, can't find the command tag=" \
+                       "%d %08x\n", ap->link.active_tag, ap->qc_active);
+       }
+
+       /* maybe a hotplug event */
+       if (unlikely(int_status & INT_LINK_SERROR)) {
+               u32 serror;
+
+               sata_oxnas_scr_read_port(ap, SCR_ERROR, &serror);
+               if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) {
+                       ata_ehi_hotplugged(&ap->link.eh_info);
+                       ata_port_freeze(ap);
+               }
+       }
+}
+
+/**
+ * irq_handler is the interrupt handling routine registered with the system,
+ * by libata.
+ */
+static irqreturn_t sata_oxnas_interrupt(int irq, void *dev_instance)
+{
+       struct ata_host *ah = dev_instance;
+       struct sata_oxnas_host_priv *hd = ah->private_data;
+       void __iomem *core_base = hd->core_base;
+
+       u32 int_status;
+       irqreturn_t ret = IRQ_NONE;
+       u32 port_no;
+       u32 mask;
+       int bug_present;
+
+       /* loop until there are no more interrupts */
+       while ((int_status = ioread32(core_base + CORE_INT_STATUS)) &
+               COREINT_END) {
+
+               /* clear any interrupt */
+               iowrite32(int_status, core_base + CORE_INT_CLEAR);
+
+               /* Only need this workaround for single disk systems as dual
+                * disk will use uCode which prevents this read underrun problem
+                * from occuring.
+                * All single disk systems will use port 0 */
+
+               for (port_no = 0; port_no < SATA_OXNAS_MAX_PORTS; ++port_no) {
+                       /* check the raw end of command interrupt to see if the
+                        * port is done */
+                       mask = (CORERAW_HOST << port_no);
+                       if (int_status & mask) {
+                               /* this port had an interrupt, clear it */
+                               iowrite32(mask, core_base + CORE_INT_CLEAR);
+                               bug_present = ox820sata_bug_6320_workaround(
+                                               ah->ports[port_no]);
+                               sata_oxnas_port_irq(ah->ports[port_no],
+                                                       bug_present);
+                               ret = IRQ_HANDLED;
+                       }
+               }
+       }
+
+       return ret;
+}
+
+/*
+ * scsi mid-layer and libata interface structures
+ */
+static struct scsi_host_template sata_oxnas_sht = {
+       ATA_NCQ_SHT("sata_oxnas"),
+       .can_queue = SATA_OXNAS_QUEUE_DEPTH,
+       .sg_tablesize = SATA_OXNAS_MAX_PRD,
+       .dma_boundary = ATA_DMA_BOUNDARY,
+       .unchecked_isa_dma  = 0,
+};
+
+
+static struct ata_port_operations sata_oxnas_ops = {
+       .inherits = &sata_port_ops,
+       .qc_prep = sata_oxnas_qc_prep,
+       .qc_issue = sata_oxnas_qc_issue,
+       .qc_fill_rtf = sata_oxnas_qc_fill_rtf,
+
+       .scr_read = sata_oxnas_scr_read,
+       .scr_write = sata_oxnas_scr_write,
+
+       /* .freeze = sata_oxnas_freeze, */
+       /* .thaw = sata_oxnas_thaw, */
+       .softreset = sata_oxnas_softreset,
+       /* .hardreset = sata_oxnas_hardreset, */
+       .postreset = sata_oxnas_postreset,
+       .error_handler = sata_oxnas_error_handler,
+       .post_internal_cmd = sata_oxnas_post_internal_cmd,
+
+       .port_start = sata_oxnas_port_start,
+       .port_stop = sata_oxnas_port_stop,
+
+       .host_stop = sata_oxnas_host_stop,
+       /* .pmp_attach = sata_oxnas_pmp_attach, */
+       /* .pmp_detach = sata_oxnas_pmp_detach, */
+       .sff_check_status = sata_oxnas_check_status,
+};
+
+static const struct ata_port_info sata_oxnas_port_info = {
+       .flags = SATA_OXNAS_HOST_FLAGS,
+       .pio_mask = ATA_PIO4,
+       .udma_mask = ATA_UDMA6,
+       .port_ops = &sata_oxnas_ops,
+};
+
+static int sata_oxnas_probe(struct platform_device *ofdev)
+{
+       int retval = -ENXIO;
+       void __iomem *port_base = NULL;
+       void __iomem *sgdma_base = NULL;
+       void __iomem *core_base = NULL;
+       void __iomem *phy_base = NULL;
+       struct reset_control *rstc;
+
+       struct resource res = {};
+       struct sata_oxnas_host_priv *host_priv = NULL;
+       int irq = 0;
+       struct ata_host *host = NULL;
+       struct clk *clk = NULL;
+
+       const struct ata_port_info *ppi[] = { &sata_oxnas_port_info, NULL };
+
+       port_base = of_iomap(ofdev->dev.of_node, 0);
+       if (!port_base)
+               goto error_exit_with_cleanup;
+
+       sgdma_base = of_iomap(ofdev->dev.of_node, 1);
+       if (!sgdma_base)
+               goto error_exit_with_cleanup;
+
+       core_base = of_iomap(ofdev->dev.of_node, 2);
+       if (!core_base)
+               goto error_exit_with_cleanup;
+
+       phy_base = of_iomap(ofdev->dev.of_node, 3);
+       if (!phy_base)
+               goto error_exit_with_cleanup;
+
+       host_priv = devm_kzalloc(&ofdev->dev,
+                                       sizeof(struct sata_oxnas_host_priv),
+                                       GFP_KERNEL);
+       if (!host_priv)
+               goto error_exit_with_cleanup;
+
+       host_priv->port_base[0] = port_base;
+       host_priv->sgdma_base[0] = sgdma_base;
+       host_priv->core_base = core_base;
+       host_priv->phy_base = phy_base;
+
+       if (!of_address_to_resource(ofdev->dev.of_node, 4, &res)) {
+               host_priv->dma_base = res.start;
+               host_priv->dma_size = resource_size(&res);
+       }
+
+       irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
+       if (!irq) {
+               dev_err(&ofdev->dev, "invalid irq from platform\n");
+               goto error_exit_with_cleanup;
+       }
+       host_priv->irq = irq;
+
+       clk = of_clk_get(ofdev->dev.of_node, 0);
+       if (IS_ERR(clk)) {
+               retval = PTR_ERR(clk);
+               clk = NULL;
+               goto error_exit_with_cleanup;
+       }
+       host_priv->clk = clk;
+
+       rstc = devm_reset_control_get(&ofdev->dev, "sata");
+       if (IS_ERR(rstc)) {
+               retval = PTR_ERR(rstc);
+               goto error_exit_with_cleanup;
+       }
+       host_priv->rst_sata = rstc;
+
+       rstc = devm_reset_control_get(&ofdev->dev, "link");
+       if (IS_ERR(rstc)) {
+               retval = PTR_ERR(rstc);
+               goto error_exit_with_cleanup;
+       }
+       host_priv->rst_link = rstc;
+
+       rstc = devm_reset_control_get(&ofdev->dev, "phy");
+       if (IS_ERR(rstc)) {
+               retval = PTR_ERR(rstc);
+               goto error_exit_with_cleanup;
+       }
+       host_priv->rst_phy = rstc;
+
+       /* allocate host structure */
+       host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_OXNAS_MAX_PORTS);
+       if (!host) {
+               retval = -ENOMEM;
+               goto error_exit_with_cleanup;
+       }
+       host->private_data = host_priv;
+       host->iomap = port_base;
+
+       /* initialize host controller */
+       retval = sata_oxnas_init_controller(host);
+       if (retval)
+               goto error_exit_with_cleanup;
+
+       /*
+        * Now, register with libATA core, this will also initiate the
+        * device discovery process, invoking our port_start() handler &
+        * error_handler() to execute a dummy softreset EH session
+        */
+       ata_host_activate(host, irq, sata_oxnas_interrupt, SATA_OXNAS_IRQ_FLAG,
+                         &sata_oxnas_sht);
+
+       return 0;
+
+error_exit_with_cleanup:
+       if (irq)
+               irq_dispose_mapping(host_priv->irq);
+       if (clk)
+               clk_put(clk);
+       if (host)
+               ata_host_detach(host);
+       if (port_base)
+               iounmap(port_base);
+       if (sgdma_base)
+               iounmap(sgdma_base);
+       if (core_base)
+               iounmap(core_base);
+       if (phy_base)
+               iounmap(phy_base);
+       return retval;
+}
+
+
+static int sata_oxnas_remove(struct platform_device *ofdev)
+{
+       struct ata_host *host = dev_get_drvdata(&ofdev->dev);
+       struct sata_oxnas_host_priv *host_priv = host->private_data;
+
+       ata_host_detach(host);
+
+       irq_dispose_mapping(host_priv->irq);
+       iounmap(host_priv->port_base);
+       iounmap(host_priv->sgdma_base);
+       iounmap(host_priv->core_base);
+
+       /* reset Controller, Link and PHY */
+       reset_control_assert(host_priv->rst_sata);
+       reset_control_assert(host_priv->rst_link);
+       reset_control_assert(host_priv->rst_phy);
+
+       /* Disable the clock to the SATA block */
+       clk_disable_unprepare(host_priv->clk);
+       clk_put(host_priv->clk);
+
+       return 0;
+}
+
+#ifdef CONFIG_PM
+static int sata_oxnas_suspend(struct platform_device *op, pm_message_t state)
+{
+       struct ata_host *host = dev_get_drvdata(&op->dev);
+
+       return ata_host_suspend(host, state);
+}
+
+static int sata_oxnas_resume(struct platform_device *op)
+{
+       struct ata_host *host = dev_get_drvdata(&op->dev);
+       int ret;
+
+       ret = sata_oxnas_init_controller(host);
+       if (ret) {
+               dev_err(&op->dev, "Error initializing hardware\n");
+               return ret;
+       }
+       ata_host_resume(host);
+       return 0;
+}
+#endif
+
+
+
+static struct of_device_id oxnas_sata_match[] = {
+       {
+               .compatible = "plxtech,nas782x-sata",
+       },
+       {},
+};
+
+MODULE_DEVICE_TABLE(of, oxnas_sata_match);
+
+static struct platform_driver oxnas_sata_driver = {
+       .driver = {
+               .name = "oxnas-sata",
+               .owner = THIS_MODULE,
+               .of_match_table = oxnas_sata_match,
+       },
+       .probe          = sata_oxnas_probe,
+       .remove         = sata_oxnas_remove,
+#ifdef CONFIG_PM
+       .suspend        = sata_oxnas_suspend,
+       .resume         = sata_oxnas_resume,
+#endif
+};
+
+module_platform_driver(oxnas_sata_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_VERSION("1.0");
+MODULE_AUTHOR("Oxford Semiconductor Ltd.");
+MODULE_DESCRIPTION("934 SATA core controler");
diff --git a/target/linux/oxnas/files/drivers/clk/clk-oxnas.c b/target/linux/oxnas/files/drivers/clk/clk-oxnas.c
new file mode 100644 (file)
index 0000000..8d80c4f
--- /dev/null
@@ -0,0 +1,262 @@
+/*
+ * Copyright (C) 2010 Broadcom
+ * Copyright (C) 2012 Stephen Warren
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/delay.h>
+#include <linux/stringify.h>
+#include <linux/reset.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/utils.h>
+
+#define MHZ (1000 * 1000)
+
+static unsigned long plla_clk_recalc_rate(struct clk_hw *hw,
+       unsigned long parent_rate)
+{
+       unsigned long fin = parent_rate;
+       unsigned long pll0;
+       unsigned long fbdiv, refdiv, outdiv;
+
+       pll0 = readl_relaxed(SYS_CTRL_PLLA_CTRL0);
+       refdiv = (pll0 >> PLLA_REFDIV_SHIFT) & PLLA_REFDIV_MASK;
+       refdiv += 1;
+       outdiv = (pll0 >> PLLA_OUTDIV_SHIFT) & PLLA_OUTDIV_MASK;
+       outdiv += 1;
+       fbdiv = readl_relaxed(SYS_CTRL_PLLA_CTRL1);
+
+       /* seems we will not be here when pll is bypassed, so ignore this
+        * case */
+
+       return fin / MHZ * fbdiv / (refdiv * outdiv) / 32768 * MHZ;
+}
+
+static const char *pll_clk_parents[] = {
+       "oscillator",
+};
+
+static struct clk_ops plla_ops = {
+       .recalc_rate = plla_clk_recalc_rate,
+};
+
+static struct clk_init_data clk_plla_init = {
+       .name = "plla",
+       .ops = &plla_ops,
+       .parent_names = pll_clk_parents,
+       .num_parents = ARRAY_SIZE(pll_clk_parents),
+};
+
+static struct clk_hw plla_hw = {
+       .init = &clk_plla_init,
+};
+
+static struct device_node *node_pllb;
+
+int pllb_clk_enable(struct clk_hw *hw)
+{
+       struct reset_control *rstc;
+
+       rstc = of_reset_control_get(node_pllb, NULL);
+       if (IS_ERR(rstc))
+               return PTR_ERR(rstc);
+
+       /* put PLL into bypass */
+       oxnas_register_set_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS));
+       wmb();
+       udelay(10);
+       reset_control_assert(rstc);
+       udelay(10);
+       /* set PLL B control information */
+       writel((1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV),
+                               SEC_CTRL_PLLB_CTRL0);
+       reset_control_deassert(rstc);
+       reset_control_put(rstc);
+       udelay(100);
+       oxnas_register_clear_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS));
+
+       return 0;
+}
+
+void pllb_clk_disable(struct clk_hw *hw)
+{
+       struct reset_control *rstc;
+
+       /* put PLL into bypass */
+       oxnas_register_set_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS));
+       wmb();
+       udelay(10);
+
+       rstc = of_reset_control_get(node_pllb, NULL);
+       if (!IS_ERR(rstc))
+               reset_control_assert(rstc);
+}
+
+static struct clk_ops pllb_ops = {
+       .enable = pllb_clk_enable,
+       .disable = pllb_clk_disable,
+};
+
+static struct clk_init_data clk_pllb_init = {
+       .name = "pllb",
+       .ops = &pllb_ops,
+       .parent_names = pll_clk_parents,
+       .num_parents = ARRAY_SIZE(pll_clk_parents),
+};
+
+static struct clk_hw pllb_hw = {
+       .init = &clk_pllb_init,
+};
+
+/* standard gate clock */
+struct clk_std {
+       struct clk_hw hw;
+       signed char bit;
+};
+
+#define NUM_STD_CLKS 17
+#define to_stdclk(_hw) container_of(_hw, struct clk_std, hw)
+
+static int std_clk_is_enabled(struct clk_hw *hw)
+{
+       struct clk_std *std = to_stdclk(hw);
+
+       return readl_relaxed(SYSCTRL_CLK_STAT) & BIT(std->bit);
+}
+
+static int std_clk_enable(struct clk_hw *hw)
+{
+       struct clk_std *std = to_stdclk(hw);
+
+       writel(BIT(std->bit), SYS_CTRL_CLK_SET_CTRL);
+       return 0;
+}
+
+static void std_clk_disable(struct clk_hw *hw)
+{
+       struct clk_std *std = to_stdclk(hw);
+
+       writel(BIT(std->bit), SYS_CTRL_CLK_CLR_CTRL);
+}
+
+static struct clk_ops std_clk_ops = {
+       .enable = std_clk_enable,
+       .disable = std_clk_disable,
+       .is_enabled = std_clk_is_enabled,
+};
+
+static const char *std_clk_parents[] = {
+       "oscillator",
+};
+
+static const char *eth_parents[] = {
+       "gmacclk",
+};
+
+#define DECLARE_STD_CLKP(__clk, __bit, __parent)       \
+static struct clk_init_data clk_##__clk##_init = {     \
+       .name = __stringify(__clk),                     \
+       .ops = &std_clk_ops,                            \
+       .parent_names = __parent,               \
+       .num_parents = ARRAY_SIZE(__parent),    \
+};                                                     \
+                                                       \
+static struct clk_std clk_##__clk = {                  \
+       .bit = __bit,                                   \
+       .hw = {                                         \
+               .init = &clk_##__clk##_init,            \
+       },                                              \
+}
+
+#define DECLARE_STD_CLK(__clk, __bit) DECLARE_STD_CLKP(__clk, __bit, \
+                                                       std_clk_parents)
+
+DECLARE_STD_CLK(leon, 0);
+DECLARE_STD_CLK(dma_sgdma, 1);
+DECLARE_STD_CLK(cipher, 2);
+DECLARE_STD_CLK(sd, 3);
+DECLARE_STD_CLK(sata, 4);
+DECLARE_STD_CLK(audio, 5);
+DECLARE_STD_CLK(usbmph, 6);
+DECLARE_STD_CLKP(etha, 7, eth_parents);
+DECLARE_STD_CLK(pciea, 8);
+DECLARE_STD_CLK(static, 9);
+DECLARE_STD_CLK(ethb, 10);
+DECLARE_STD_CLK(pcieb, 11);
+DECLARE_STD_CLK(ref600, 12);
+DECLARE_STD_CLK(usbdev, 13);
+
+struct clk_hw *std_clk_hw_tbl[] = {
+       &clk_leon.hw,
+       &clk_dma_sgdma.hw,
+       &clk_cipher.hw,
+       &clk_sd.hw,
+       &clk_sata.hw,
+       &clk_audio.hw,
+       &clk_usbmph.hw,
+       &clk_etha.hw,
+       &clk_pciea.hw,
+       &clk_static.hw,
+       &clk_ethb.hw,
+       &clk_pcieb.hw,
+       &clk_ref600.hw,
+       &clk_usbdev.hw,
+};
+
+struct clk *std_clk_tbl[ARRAY_SIZE(std_clk_hw_tbl)];
+
+static struct clk_onecell_data std_clk_data;
+
+void __init oxnas_init_stdclk(struct device_node *np)
+{
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(std_clk_hw_tbl); i++) {
+               std_clk_tbl[i] = clk_register(NULL, std_clk_hw_tbl[i]);
+               BUG_ON(IS_ERR(std_clk_tbl[i]));
+       }
+       std_clk_data.clks = std_clk_tbl;
+       std_clk_data.clk_num = ARRAY_SIZE(std_clk_tbl);
+       of_clk_add_provider(np, of_clk_src_onecell_get, &std_clk_data);
+}
+CLK_OF_DECLARE(oxnas_pllstd, "plxtech,nas782x-stdclk", oxnas_init_stdclk);
+
+void __init oxnas_init_plla(struct device_node *np)
+{
+       struct clk *clk;
+
+       clk = clk_register(NULL, &plla_hw);
+       BUG_ON(IS_ERR(clk));
+       /* mark it as enabled */
+       clk_prepare_enable(clk);
+       of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(oxnas_plla, "plxtech,nas782x-plla", oxnas_init_plla);
+
+void __init oxnas_init_pllb(struct device_node *np)
+{
+       struct clk *clk;
+
+       node_pllb = np;
+
+       clk = clk_register(NULL, &pllb_hw);
+       BUG_ON(IS_ERR(clk));
+       of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(oxnas_pllb, "plxtech,nas782x-pllb", oxnas_init_pllb);
diff --git a/target/linux/oxnas/files/drivers/clocksource/oxnas_rps_timer.c b/target/linux/oxnas/files/drivers/clocksource/oxnas_rps_timer.c
new file mode 100644 (file)
index 0000000..7c8c4cf
--- /dev/null
@@ -0,0 +1,96 @@
+/*
+ * arch/arm/mach-ox820/rps-time.c
+ *
+ * Copyright (C) 2009 Oxford Semiconductor Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/sched_clock.h>
+#include <mach/hardware.h>
+
+enum {
+       TIMER_LOAD = 0,
+       TIMER_CURR = 4,
+       TIMER_CTRL = 8,
+       TIMER_CLRINT = 0xC,
+
+       TIMER_BITS = 24,
+
+       TIMER_MAX_VAL = (1 << TIMER_BITS) - 1,
+
+       TIMER_PERIODIC = (1 << 6),
+       TIMER_ENABLE = (1 << 7),
+
+       TIMER_DIV1  = (0 << 2),
+       TIMER_DIV16  = (1 << 2),
+       TIMER_DIV256  = (2 << 2),
+
+       TIMER1_OFFSET = 0,
+       TIMER2_OFFSET = 0x20,
+
+};
+
+static u64 notrace rps_read_sched_clock(void)
+{
+       return ~readl_relaxed(RPSA_TIMER2_VAL);
+}
+
+static void __init rps_clocksource_init(void __iomem *base, ulong ref_rate)
+{
+       int ret;
+       ulong clock_rate;
+       /* use prescale 16 */
+       clock_rate = ref_rate / 16;
+
+       iowrite32(TIMER_MAX_VAL, base + TIMER_LOAD);
+       iowrite32(TIMER_PERIODIC | TIMER_ENABLE | TIMER_DIV16,
+                       base + TIMER_CTRL);
+
+       ret = clocksource_mmio_init(base + TIMER_CURR, "rps_clocksource_timer",
+                                       clock_rate, 250, TIMER_BITS,
+                                       clocksource_mmio_readl_down);
+       if (ret)
+               panic("can't register clocksource\n");
+
+       sched_clock_register(rps_read_sched_clock, TIMER_BITS, clock_rate);
+}
+
+static void __init rps_timer_init(struct device_node *np)
+{
+       struct clk *refclk;
+       unsigned long ref_rate;
+       void __iomem *base;
+
+       refclk = of_clk_get(np, 0);
+
+       if (IS_ERR(refclk) || clk_prepare_enable(refclk))
+               panic("rps_timer_init: failed to get refclk\n");
+       ref_rate = clk_get_rate(refclk);
+
+       base = of_iomap(np, 0);
+       if (!base)
+               panic("rps_timer_init: failed to map io\n");
+
+       rps_clocksource_init(base + TIMER2_OFFSET, ref_rate);
+}
+
+CLOCKSOURCE_OF_DECLARE(nas782x, "plxtech,nas782x-rps-timer", rps_timer_init);
diff --git a/target/linux/oxnas/files/drivers/irqchip/irq-rps.c b/target/linux/oxnas/files/drivers/irqchip/irq-rps.c
new file mode 100644 (file)
index 0000000..5795406
--- /dev/null
@@ -0,0 +1,146 @@
+#include <linux/irqdomain.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include "irqchip.h"
+
+struct rps_chip_data {
+       void __iomem *base;
+       struct irq_chip chip;
+       struct irq_domain *domain;
+} rps_data;
+
+enum {
+       RPS_IRQ_BASE = 64,
+       RPS_IRQ_COUNT = 32,
+       PRS_HWIRQ_BASE = 0,
+
+       RPS_STATUS = 0,
+       RPS_RAW_STATUS = 4,
+       RPS_UNMASK = 8,
+       RPS_MASK = 0xc,
+};
+
+/*
+ * Routines to acknowledge, disable and enable interrupts
+ */
+static void rps_mask_irq(struct irq_data *d)
+{
+       struct rps_chip_data *chip_data = irq_data_get_irq_chip_data(d);
+       u32 mask = BIT(d->hwirq);
+
+       iowrite32(mask, chip_data->base + RPS_MASK);
+}
+
+static void rps_unmask_irq(struct irq_data *d)
+{
+       struct rps_chip_data *chip_data = irq_data_get_irq_chip_data(d);
+       u32 mask = BIT(d->hwirq);
+
+       iowrite32(mask, chip_data->base + RPS_UNMASK);
+}
+
+static struct irq_chip rps_chip = {
+       .name                   = "RPS",
+       .irq_mask               = rps_mask_irq,
+       .irq_unmask             = rps_unmask_irq,
+};
+
+static int rps_irq_domain_xlate(struct irq_domain *d,
+                               struct device_node *controller,
+                               const u32 *intspec, unsigned int intsize,
+                               unsigned long *out_hwirq,
+                               unsigned int *out_type)
+{
+       if (d->of_node != controller)
+               return -EINVAL;
+       if (intsize < 1)
+               return -EINVAL;
+
+       *out_hwirq = intspec[0];
+       /* Honestly I do not know the type */
+       *out_type = IRQ_TYPE_LEVEL_HIGH;
+
+       return 0;
+}
+
+static int rps_irq_domain_map(struct irq_domain *d, unsigned int irq,
+                               irq_hw_number_t hw)
+{
+       irq_set_chip_and_handler(irq, &rps_chip, handle_level_irq);
+       set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+       irq_set_chip_data(irq, d->host_data);
+       return 0;
+}
+
+const struct irq_domain_ops rps_irq_domain_ops = {
+       .map = rps_irq_domain_map,
+       .xlate = rps_irq_domain_xlate,
+};
+
+static void rps_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
+{
+       struct rps_chip_data *chip_data = irq_get_handler_data(irq);
+       struct irq_chip *chip = irq_get_chip(irq);
+       unsigned int cascade_irq, rps_irq;
+       u32 status;
+
+       chained_irq_enter(chip, desc);
+
+       status = ioread32(chip_data->base + RPS_STATUS);
+       rps_irq = __ffs(status);
+       cascade_irq = irq_find_mapping(chip_data->domain, rps_irq);
+
+       if (unlikely(rps_irq >= RPS_IRQ_COUNT))
+               handle_bad_irq(cascade_irq, desc);
+       else
+               generic_handle_irq(cascade_irq);
+
+       chained_irq_exit(chip, desc);
+}
+
+#ifdef CONFIG_OF
+int __init rps_of_init(struct device_node *node, struct device_node *parent)
+{
+       void __iomem *rps_base;
+       int irq_start = RPS_IRQ_BASE;
+       int irq_base;
+       int irq;
+
+       if (WARN_ON(!node))
+               return -ENODEV;
+
+       rps_base = of_iomap(node, 0);
+       WARN(!rps_base, "unable to map rps registers\n");
+       rps_data.base = rps_base;
+
+       irq_base = irq_alloc_descs(irq_start, 0, RPS_IRQ_COUNT, numa_node_id());
+       if (IS_ERR_VALUE(irq_base)) {
+               WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
+                    irq_start);
+               irq_base = irq_start;
+       }
+
+       rps_data.domain = irq_domain_add_legacy(node, RPS_IRQ_COUNT, irq_base,
+                       PRS_HWIRQ_BASE, &rps_irq_domain_ops, &rps_data);
+
+       if (WARN_ON(!rps_data.domain))
+               return -ENOMEM;
+
+       if (parent) {
+               irq = irq_of_parse_and_map(node, 0);
+               if (irq_set_handler_data(irq, &rps_data) != 0)
+                       BUG();
+               irq_set_chained_handler(irq, rps_handle_cascade_irq);
+       }
+       return 0;
+
+}
+
+IRQCHIP_DECLARE(nas782x, "plxtech,nas782x-rps", rps_of_init);
+#endif
diff --git a/target/linux/oxnas/files/drivers/mtd/nand/oxnas_nand.c b/target/linux/oxnas/files/drivers/mtd/nand/oxnas_nand.c
new file mode 100644 (file)
index 0000000..55eb009
--- /dev/null
@@ -0,0 +1,102 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/mtd/nand.h>
+#include <linux/of_gpio.h>
+#include <linux/of_platform.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <mach/utils.h>
+
+/* nand commands */
+#define NAND_CMD_ALE           BIT(18)
+#define NAND_CMD_CLE           BIT(19)
+#define NAND_CMD_CS            0
+#define NAND_CMD_RESET         0xff
+#define NAND_CMD               (NAND_CMD_CS | NAND_CMD_CLE)
+#define NAND_ADDR              (NAND_CMD_CS | NAND_CMD_ALE)
+#define NAND_DATA              (NAND_CMD_CS)
+
+static void oxnas_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+       struct nand_chip *this = mtd->priv;
+       unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
+
+       if (ctrl & NAND_CTRL_CHANGE) {
+               nandaddr &= ~(NAND_CMD | NAND_ADDR);
+               if (ctrl & NAND_CLE)
+                       nandaddr |= NAND_CMD;
+               else if (ctrl & NAND_ALE)
+                       nandaddr |= NAND_ADDR;
+               this->IO_ADDR_W = (void __iomem *) nandaddr;
+       }
+
+       if (cmd != NAND_CMD_NONE)
+               writeb(cmd, (void __iomem *) nandaddr);
+}
+
+static int oxnas_nand_probe(struct platform_device *pdev)
+{
+       /* enable clock and release static block reset */
+       struct clk *clk = of_clk_get(pdev->dev.of_node, 0);
+
+       if (IS_ERR(clk))
+               return PTR_ERR(clk);
+
+       clk_prepare_enable(clk);
+       device_reset(&pdev->dev);
+
+       return 0;
+}
+
+/* allow users to override the partition in DT using the cmdline */
+static const char * part_probes[] = { "cmdlinepart", "ofpart", NULL };
+
+static struct platform_nand_data oxnas_nand_data = {
+       .chip = {
+               .nr_chips               = 1,
+               .chip_delay             = 30,
+               .part_probe_types       = part_probes,
+       },
+       .ctrl = {
+               .probe          = oxnas_nand_probe,
+               .cmd_ctrl       = oxnas_cmd_ctrl,
+       }
+};
+
+/*
+ * Try to find the node inside the DT. If it is available attach out
+ * platform_nand_data
+ */
+static int __init oxnas_register_nand(void)
+{
+       struct device_node *node;
+       struct platform_device *pdev;
+
+       node = of_find_compatible_node(NULL, NULL, "plxtech,nand-nas782x");
+       if (!node)
+               return -ENOENT;
+       pdev = of_find_device_by_node(node);
+       if (!pdev)
+               return -EINVAL;
+       pdev->dev.platform_data = &oxnas_nand_data;
+       of_node_put(node);
+       return 0;
+}
+
+subsys_initcall(oxnas_register_nand);
+
+static const struct of_device_id oxnas_nand_ids[] = {
+       { .compatible = "plxtech,nand-nas782x"},
+       { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, oxnas_nand_ids);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Ma Haijun");
+MODULE_DESCRIPTION("NAND glue for Oxnas platforms");
+MODULE_ALIAS("platform:oxnas_nand");
diff --git a/target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c b/target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c
new file mode 100644 (file)
index 0000000..9e8d6d9
--- /dev/null
@@ -0,0 +1,676 @@
+/*
+ * PCIe driver for PLX NAS782X SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/mbus.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/of_address.h>
+#include <linux/of_pci.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/of_gpio.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <mach/iomap.h>
+#include <mach/hardware.h>
+#include <mach/utils.h>
+
+#define VERSION_ID_MAGIC               0x082510b5
+#define LINK_UP_TIMEOUT_SECONDS                1
+#define NUM_CONTROLLERS                        1
+
+enum {
+       PCIE_DEVICE_TYPE_MASK = 0x0F,
+       PCIE_DEVICE_TYPE_ENDPOINT = 0,
+       PCIE_DEVICE_TYPE_LEGACY_ENDPOINT = 1,
+       PCIE_DEVICE_TYPE_ROOT = 4,
+
+       PCIE_LTSSM = BIT(4),
+       PCIE_READY_ENTR_L23 = BIT(9),
+       PCIE_LINK_UP = BIT(11),
+       PCIE_OBTRANS = BIT(12),
+};
+
+enum {
+       HCSL_BIAS_ON = BIT(0),
+       HCSL_PCIE_EN = BIT(1),
+       HCSL_PCIEA_EN = BIT(2),
+       HCSL_PCIEB_EN = BIT(3),
+};
+
+enum {
+       /* pcie phy reg offset */
+       PHY_ADDR = 0,
+       PHY_DATA = 4,
+       /* phy data reg bits */
+       READ_EN = BIT(16),
+       WRITE_EN = BIT(17),
+       CAP_DATA = BIT(18),
+};
+
+/* core config registers */
+enum {
+       PCI_CONFIG_VERSION_DEVICEID = 0,
+       PCI_CONFIG_COMMAND_STATUS = 4,
+};
+
+/* inbound config registers */
+enum {
+       IB_ADDR_XLATE_ENABLE = 0xFC,
+
+       /* bits */
+       ENABLE_IN_ADDR_TRANS = BIT(0),
+};
+
+/* outbound config registers, offset relative to PCIE_POM0_MEM_ADDR */
+enum {
+       PCIE_POM0_MEM_ADDR      = 0,
+       PCIE_POM1_MEM_ADDR      = 4,
+       PCIE_IN0_MEM_ADDR       = 8,
+       PCIE_IN1_MEM_ADDR       = 12,
+       PCIE_IN_IO_ADDR         = 16,
+       PCIE_IN_CFG0_ADDR       = 20,
+       PCIE_IN_CFG1_ADDR       = 24,
+       PCIE_IN_MSG_ADDR        = 28,
+       PCIE_IN0_MEM_LIMIT      = 32,
+       PCIE_IN1_MEM_LIMIT      = 36,
+       PCIE_IN_IO_LIMIT        = 40,
+       PCIE_IN_CFG0_LIMIT      = 44,
+       PCIE_IN_CFG1_LIMIT      = 48,
+       PCIE_IN_MSG_LIMIT       = 52,
+       PCIE_AHB_SLAVE_CTRL     = 56,
+
+       PCIE_SLAVE_BE_SHIFT     = 22,
+};
+
+#define ADDR_VAL(val)  ((val) & 0xFFFF)
+#define DATA_VAL(val)  ((val) & 0xFFFF)
+
+#define PCIE_SLAVE_BE(val)     ((val) << PCIE_SLAVE_BE_SHIFT)
+#define PCIE_SLAVE_BE_MASK     PCIE_SLAVE_BE(0xF)
+
+struct oxnas_pcie_shared {
+       /* seems all access are serialized, no lock required */
+       int refcount;
+};
+
+/* Structure representing one PCIe interfaces */
+struct oxnas_pcie {
+       void __iomem *cfgbase;
+       void __iomem *base;
+       void __iomem *inbound;
+       void __iomem *outbound;
+       void __iomem *pcie_ctrl;
+
+       int haslink;
+       struct platform_device *pdev;
+       struct resource io;
+       struct resource cfg;
+       struct resource pre_mem;        /* prefetchable */
+       struct resource non_mem;        /* non-prefetchable */
+       struct resource busn;           /* max available bus numbers */
+       int card_reset;                 /* gpio pin, optional */
+       unsigned hcsl_en;               /* hcsl pci enable bit */
+       struct clk *clk;
+       struct clk *busclk;             /* for pcie bus, actually the PLLB */
+       void *private_data[1];
+       spinlock_t lock;
+};
+
+static struct oxnas_pcie_shared pcie_shared = {
+       .refcount = 0,
+};
+
+static inline struct oxnas_pcie *sys_to_pcie(struct pci_sys_data *sys)
+{
+       return sys->private_data;
+}
+
+
+static inline void set_out_lanes(struct oxnas_pcie *pcie, unsigned lanes)
+{
+       oxnas_register_value_mask(pcie->outbound + PCIE_AHB_SLAVE_CTRL,
+                                 PCIE_SLAVE_BE_MASK, PCIE_SLAVE_BE(lanes));
+       wmb();
+}
+
+static int oxnas_pcie_link_up(struct oxnas_pcie *pcie)
+{
+       unsigned long end;
+
+       /* Poll for PCIE link up */
+       end = jiffies + (LINK_UP_TIMEOUT_SECONDS * HZ);
+       while (!time_after(jiffies, end)) {
+               if (readl(pcie->pcie_ctrl) & PCIE_LINK_UP)
+                       return 1;
+       }
+       return 0;
+}
+
+static void __init oxnas_pcie_setup_hw(struct oxnas_pcie *pcie)
+{
+       /* We won't have any inbound address translation. This allows PCI
+        * devices to access anywhere in the AHB address map. Might be regarded
+        * as a bit dangerous, but let's get things working before we worry
+        * about that
+        */
+       oxnas_register_clear_mask(pcie->inbound + IB_ADDR_XLATE_ENABLE,
+                                 ENABLE_IN_ADDR_TRANS);
+       wmb();
+
+       /*
+        * Program outbound translation windows
+        *
+        * Outbound window is what is referred to as "PCI client" region in HRM
+        *
+        * Could use the larger alternative address space to get >>64M regions
+        * for graphics cards etc., but will not bother at this point.
+        *
+        * IP bug means that AMBA window size must be a power of 2
+        *
+        * Set mem0 window for first 16MB of outbound window non-prefetchable
+        * Set mem1 window for second 16MB of outbound window prefetchable
+        * Set io window for next 16MB of outbound window
+        * Set cfg0 for final 1MB of outbound window
+        *
+        * Ignore mem1, cfg1 and msg windows for now as no obvious use cases for
+        * 820 that would need them
+        *
+        * Probably ideally want no offset between mem0 window start as seen by
+        * ARM and as seen on PCI bus and get Linux to assign memory regions to
+        * PCI devices using the same "PCI client" region start address as seen
+        * by ARM
+        */
+
+       /* Set PCIeA mem0 region to be 1st 16MB of the 64MB PCIeA window */
+       writel_relaxed(pcie->non_mem.start, pcie->outbound + PCIE_IN0_MEM_ADDR);
+       writel_relaxed(pcie->non_mem.end, pcie->outbound + PCIE_IN0_MEM_LIMIT);
+       writel_relaxed(pcie->non_mem.start, pcie->outbound + PCIE_POM0_MEM_ADDR);
+
+       /* Set PCIeA mem1 region to be 2nd 16MB of the 64MB PCIeA window */
+       writel_relaxed(pcie->pre_mem.start, pcie->outbound + PCIE_IN1_MEM_ADDR);
+       writel_relaxed(pcie->pre_mem.end, pcie->outbound + PCIE_IN1_MEM_LIMIT);
+       writel_relaxed(pcie->pre_mem.start, pcie->outbound + PCIE_POM1_MEM_ADDR);
+
+       /* Set PCIeA io to be third 16M region of the 64MB PCIeA window*/
+       writel_relaxed(pcie->io.start,  pcie->outbound + PCIE_IN_IO_ADDR);
+       writel_relaxed(pcie->io.end,    pcie->outbound + PCIE_IN_IO_LIMIT);
+
+       /* Set PCIeA cgf0 to be last 16M region of the 64MB PCIeA window*/
+       writel_relaxed(pcie->cfg.start, pcie->outbound + PCIE_IN_CFG0_ADDR);
+       writel_relaxed(pcie->cfg.end, pcie->outbound + PCIE_IN_CFG0_LIMIT);
+       wmb();
+
+       /* Enable outbound address translation */
+       oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_OBTRANS);
+       wmb();
+
+       /*
+        * Program PCIe command register for core to:
+        *  enable memory space
+        *  enable bus master
+        *  enable io
+        */
+       writel_relaxed(7, pcie->base + PCI_CONFIG_COMMAND_STATUS);
+       /* which is which */
+       wmb();
+}
+
+static unsigned oxnas_pcie_cfg_to_offset(
+       struct pci_sys_data *sys,
+       unsigned char bus_number,
+       unsigned int devfn,
+       int where)
+{
+       unsigned int function = PCI_FUNC(devfn);
+       unsigned int slot = PCI_SLOT(devfn);
+       unsigned char bus_number_offset;
+
+       bus_number_offset = bus_number - sys->busnr;
+
+       /*
+        * We'll assume for now that the offset, function, slot, bus encoding
+        * should map onto linear, contiguous addresses in PCIe config space,
+        * albeit that the majority will be unused as only slot 0 is valid for
+        * any PCIe bus and most devices have only function 0
+        *
+        * Could be that PCIe in fact works by not encoding the slot number into
+        * the config space address as it's known that only slot 0 is valid.
+        * We'll have to experiment if/when we get a PCIe switch connected to
+        * the PCIe host
+        */
+       return (bus_number_offset << 20) | (slot << 15) | (function << 12) |
+               (where & ~3);
+}
+
+/* PCI configuration space write function */
+static int oxnas_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
+                             int where, int size, u32 val)
+{
+       unsigned long flags;
+       struct oxnas_pcie *pcie = sys_to_pcie(bus->sysdata);
+       unsigned offset;
+       u32 value;
+       u32 lanes;
+
+       /* Only a single device per bus for PCIe point-to-point links */
+       if (PCI_SLOT(devfn) > 0)
+               return PCIBIOS_DEVICE_NOT_FOUND;
+
+       if (!pcie->haslink)
+               return PCIBIOS_DEVICE_NOT_FOUND;
+
+       offset = oxnas_pcie_cfg_to_offset(bus->sysdata, bus->number, devfn,
+                                         where);
+
+       value = val << (8 * (where & 3));
+       lanes = (0xf >> (4-size)) << (where & 3);
+       /* it race with mem and io write, but the possibility is low, normally
+        * all config writes happens at driver initialize stage, wont interleave
+        * with others.
+        * and many pcie cards use dword (4bytes) access mem/io access only,
+        * so not bother to copy that ugly work-around now. */
+       spin_lock_irqsave(&pcie->lock, flags);
+       set_out_lanes(pcie, lanes);
+       writel_relaxed(value, pcie->cfgbase + offset);
+       set_out_lanes(pcie, 0xf);
+       spin_unlock_irqrestore(&pcie->lock, flags);
+
+       return PCIBIOS_SUCCESSFUL;
+}
+
+/* PCI configuration space read function */
+static int oxnas_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+                             int size, u32 *val)
+{
+       struct oxnas_pcie *pcie = sys_to_pcie(bus->sysdata);
+       unsigned offset;
+       u32 value;
+       u32 left_bytes, right_bytes;
+
+       /* Only a single device per bus for PCIe point-to-point links */
+       if (PCI_SLOT(devfn) > 0) {
+               *val = 0xffffffff;
+               return PCIBIOS_DEVICE_NOT_FOUND;
+       }
+
+       if (!pcie->haslink) {
+               *val = 0xffffffff;
+               return PCIBIOS_DEVICE_NOT_FOUND;
+       }
+
+       offset = oxnas_pcie_cfg_to_offset(bus->sysdata, bus->number, devfn,
+                                         where);
+       value = readl_relaxed(pcie->cfgbase + offset);
+       left_bytes = where & 3;
+       right_bytes = 4 - left_bytes - size;
+       value <<= right_bytes * 8;
+       value >>= (left_bytes + right_bytes) * 8;
+       *val = value;
+
+       return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops oxnas_pcie_ops = {
+       .read = oxnas_pcie_rd_conf,
+       .write = oxnas_pcie_wr_conf,
+};
+
+static int __init oxnas_pcie_setup(int nr, struct pci_sys_data *sys)
+{
+       struct oxnas_pcie *pcie = sys_to_pcie(sys);
+
+       pci_add_resource_offset(&sys->resources, &pcie->non_mem, sys->mem_offset);
+       pci_add_resource_offset(&sys->resources, &pcie->pre_mem, sys->mem_offset);
+       pci_add_resource_offset(&sys->resources, &pcie->io, sys->io_offset);
+       pci_add_resource(&sys->resources, &pcie->busn);
+       if (sys->busnr == 0) { /* default one */
+               sys->busnr = pcie->busn.start;
+       }
+       /* do not use devm_ioremap_resource, it does not like cfg resource */
+       pcie->cfgbase = devm_ioremap(&pcie->pdev->dev, pcie->cfg.start,
+                                    resource_size(&pcie->cfg));
+       if (!pcie->cfgbase)
+               return -ENOMEM;
+
+       oxnas_pcie_setup_hw(pcie);
+
+       return 1;
+}
+
+static void __init oxnas_pcie_enable(struct device *dev, struct oxnas_pcie *pcie)
+{
+       struct hw_pci hw;
+       int i;
+
+       memset(&hw, 0, sizeof(hw));
+       for (i = 0; i < NUM_CONTROLLERS; i++)
+               pcie->private_data[i] = pcie;
+
+       hw.nr_controllers = NUM_CONTROLLERS;
+/* I think use stack pointer is a bad idea though it is valid in this case */
+       hw.private_data   = pcie->private_data;
+       hw.setup          = oxnas_pcie_setup;
+       hw.map_irq        = of_irq_parse_and_map_pci;
+       hw.ops            = &oxnas_pcie_ops;
+
+       /* pass dev to maintain of tree, interrupt mapping rely on this */
+       pci_common_init_dev(dev, &hw);
+}
+
+void oxnas_pcie_init_shared_hw(struct platform_device *pdev,
+                              void __iomem *phybase)
+{
+       struct reset_control *rstc;
+       int ret;
+
+       /* generate clocks from HCSL buffers, shared parts */
+       writel(HCSL_BIAS_ON|HCSL_PCIE_EN, SYS_CTRL_HCSL_CTRL);
+
+       /* Ensure PCIe PHY is properly reset */
+       rstc = reset_control_get(&pdev->dev, "phy");
+       if (IS_ERR(rstc)) {
+               ret = PTR_ERR(rstc);
+       } else {
+               ret = reset_control_reset(rstc);
+               reset_control_put(rstc);
+       }
+
+       if (ret) {
+               dev_err(&pdev->dev, "phy reset failed %d\n", ret);
+               return;
+       }
+
+       /* Enable PCIe Pre-Emphasis: What these value means? */
+
+       writel(ADDR_VAL(0x0014), phybase + PHY_ADDR);
+       writel(DATA_VAL(0xce10) | CAP_DATA, phybase + PHY_DATA);
+       writel(DATA_VAL(0xce10) | WRITE_EN, phybase + PHY_DATA);
+
+       writel(ADDR_VAL(0x2004), phybase + PHY_ADDR);
+       writel(DATA_VAL(0x82c7) | CAP_DATA, phybase + PHY_DATA);
+       writel(DATA_VAL(0x82c7) | WRITE_EN, phybase + PHY_DATA);
+}
+
+static int oxnas_pcie_shared_init(struct platform_device *pdev)
+{
+       if (++pcie_shared.refcount == 1) {
+               /* we are the first */
+               struct device_node *np = pdev->dev.of_node;
+               void __iomem *phy = of_iomap(np, 2);
+               if (!phy) {
+                       --pcie_shared.refcount;
+                       return -ENOMEM;
+               }
+               oxnas_pcie_init_shared_hw(pdev, phy);
+               iounmap(phy);
+               return 0;
+       } else {
+               return 0;
+       }
+}
+
+#if 0
+/* maybe we will call it when enter low power state */
+static void oxnas_pcie_shared_deinit(struct platform_device *pdev)
+{
+       if (--pcie_shared.refcount == 0) {
+               /* no cleanup needed */;
+       }
+}
+#endif
+
+static int __init
+oxnas_pcie_map_registers(struct platform_device *pdev,
+                        struct device_node *np,
+                        struct oxnas_pcie *pcie)
+{
+       struct resource regs;
+       int ret = 0;
+       u32 outbound_ctrl_offset;
+       u32 pcie_ctrl_offset;
+
+       /* 2 is reserved for shared phy */
+       ret = of_address_to_resource(np, 0, &regs);
+       if (ret)
+               return -EINVAL;
+       pcie->base = devm_ioremap_resource(&pdev->dev, &regs);
+       if (!pcie->base)
+               return -ENOMEM;
+
+       ret = of_address_to_resource(np, 1, &regs);
+       if (ret)
+               return -EINVAL;
+       pcie->inbound = devm_ioremap_resource(&pdev->dev, &regs);
+       if (!pcie->inbound)
+               return -ENOMEM;
+
+
+       if (of_property_read_u32(np, "plxtech,pcie-outbound-offset",
+                                &outbound_ctrl_offset))
+               return -EINVAL;
+       /* SYSCRTL is shared by too many drivers, so is mapped by board file */
+       pcie->outbound = IOMEM(OXNAS_SYSCRTL_BASE_VA + outbound_ctrl_offset);
+
+       if (of_property_read_u32(np, "plxtech,pcie-ctrl-offset",
+                                &pcie_ctrl_offset))
+               return -EINVAL;
+       pcie->pcie_ctrl = IOMEM(OXNAS_SYSCRTL_BASE_VA + pcie_ctrl_offset);
+
+       return 0;
+}
+
+static int __init oxnas_pcie_init_res(struct platform_device *pdev,
+                                     struct oxnas_pcie *pcie,
+                                     struct device_node *np)
+{
+       struct of_pci_range range;
+       struct of_pci_range_parser parser;
+       int ret;
+
+       if (of_pci_range_parser_init(&parser, np))
+               return -EINVAL;
+
+       /* Get the I/O and memory ranges from DT */
+       for_each_of_pci_range(&parser, &range) {
+
+               unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
+               if (restype == IORESOURCE_IO) {
+                       of_pci_range_to_resource(&range, np, &pcie->io);
+                       pcie->io.name = "I/O";
+               }
+               if (restype == IORESOURCE_MEM) {
+                       if (range.flags & IORESOURCE_PREFETCH) {
+                               of_pci_range_to_resource(&range, np, &pcie->pre_mem);
+                               pcie->pre_mem.name = "PRE MEM";
+                       } else {
+                               of_pci_range_to_resource(&range, np, &pcie->non_mem);
+                               pcie->non_mem.name = "NON MEM";
+                       }
+
+               }
+               if (restype == 0)
+                       of_pci_range_to_resource(&range, np, &pcie->cfg);
+       }
+
+       /* Get the bus range */
+       ret = of_pci_parse_bus_range(np, &pcie->busn);
+
+       if (ret) {
+               dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
+                       ret);
+               return ret;
+       }
+
+       pcie->card_reset = of_get_gpio(np, 0);
+       if (pcie->card_reset < 0)
+               dev_info(&pdev->dev, "card reset gpio pin not exists\n");
+
+       if (of_property_read_u32(np, "plxtech,pcie-hcsl-bit", &pcie->hcsl_en))
+               return -EINVAL;
+
+       pcie->clk = of_clk_get_by_name(np, "pcie");
+       if (IS_ERR(pcie->clk)) {
+               return PTR_ERR(pcie->clk);
+       }
+
+       pcie->busclk = of_clk_get_by_name(np, "busclk");
+       if (IS_ERR(pcie->busclk)) {
+               clk_put(pcie->clk);
+               return PTR_ERR(pcie->busclk);
+       }
+
+       return 0;
+}
+
+static void oxnas_pcie_init_hw(struct platform_device *pdev,
+                              struct oxnas_pcie *pcie)
+{
+       u32 version_id;
+       int ret;
+
+       clk_prepare_enable(pcie->busclk);
+
+       /* reset PCIe cards use hard-wired gpio pin */
+       if (pcie->card_reset >= 0 &&
+           !gpio_direction_output(pcie->card_reset, 0)) {
+               wmb();
+               mdelay(10);
+               /* must tri-state the pin to pull it up */
+               gpio_direction_input(pcie->card_reset);
+               wmb();
+               mdelay(100);
+       }
+
+       oxnas_register_set_mask(SYS_CTRL_HCSL_CTRL, BIT(pcie->hcsl_en));
+
+       /* core */
+       ret = device_reset(&pdev->dev);
+       if (ret) {
+               dev_err(&pdev->dev, "core reset failed %d\n", ret);
+               return;
+       }
+
+       /* Start PCIe core clocks */
+       clk_prepare_enable(pcie->clk);
+
+       version_id = readl_relaxed(pcie->base + PCI_CONFIG_VERSION_DEVICEID);
+       dev_info(&pdev->dev, "PCIe version/deviceID 0x%x\n", version_id);
+
+       if (version_id != VERSION_ID_MAGIC) {
+               dev_info(&pdev->dev, "PCIe controller not found\n");
+               pcie->haslink = 0;
+               return;
+       }
+
+       /* allow entry to L23 state */
+       oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_READY_ENTR_L23);
+
+       /* Set PCIe core into RootCore mode */
+       oxnas_register_value_mask(pcie->pcie_ctrl, PCIE_DEVICE_TYPE_MASK,
+                                 PCIE_DEVICE_TYPE_ROOT);
+       wmb();
+
+       /* Bring up the PCI core */
+       oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_LTSSM);
+       wmb();
+}
+
+static int __init oxnas_pcie_probe(struct platform_device *pdev)
+{
+       struct oxnas_pcie *pcie;
+       struct device_node *np = pdev->dev.of_node;
+       int ret;
+
+       pcie = devm_kzalloc(&pdev->dev, sizeof(struct oxnas_pcie),
+                           GFP_KERNEL);
+       if (!pcie)
+               return -ENOMEM;
+
+       pcie->pdev = pdev;
+       pcie->haslink = 1;
+       spin_lock_init(&pcie->lock);
+
+       ret = oxnas_pcie_init_res(pdev, pcie, np);
+       if (ret)
+               return ret;
+       if (pcie->card_reset >= 0) {
+               ret = gpio_request_one(pcie->card_reset, GPIOF_DIR_IN,
+                                      dev_name(&pdev->dev));
+               if (ret) {
+                       dev_err(&pdev->dev, "cannot request gpio pin %d\n",
+                               pcie->card_reset);
+                       return ret;
+               }
+       }
+
+       ret = oxnas_pcie_map_registers(pdev, np, pcie);
+       if (ret) {
+               dev_err(&pdev->dev, "cannot map registers\n");
+               goto err_free_gpio;
+       }
+
+       ret = oxnas_pcie_shared_init(pdev);
+       if (ret)
+               goto err_free_gpio;
+
+       /* if hw not found, haslink cleared */
+       oxnas_pcie_init_hw(pdev, pcie);
+
+       if (pcie->haslink && oxnas_pcie_link_up(pcie)) {
+               pcie->haslink = 1;
+               dev_info(&pdev->dev, "link up\n");
+       } else {
+               pcie->haslink = 0;
+               dev_info(&pdev->dev, "link down\n");
+       }
+       /* should we register our controller even when pcie->haslink is 0 ? */
+       /* register the controller with framework */
+       oxnas_pcie_enable(&pdev->dev, pcie);
+
+       return 0;
+
+err_free_gpio:
+       if (pcie->card_reset)
+               gpio_free(pcie->card_reset);
+
+       return ret;
+}
+
+static const struct of_device_id oxnas_pcie_of_match_table[] = {
+       { .compatible = "plxtech,nas782x-pcie", },
+       {},
+};
+MODULE_DEVICE_TABLE(of, oxnas_pcie_of_match_table);
+
+static struct platform_driver oxnas_pcie_driver = {
+       .driver = {
+               .owner = THIS_MODULE,
+               .name = "oxnas-pcie",
+               .of_match_table =
+                  of_match_ptr(oxnas_pcie_of_match_table),
+       },
+};
+
+static int __init oxnas_pcie_init(void)
+{
+       return platform_driver_probe(&oxnas_pcie_driver,
+                                    oxnas_pcie_probe);
+}
+
+subsys_initcall(oxnas_pcie_init);
+
+MODULE_AUTHOR("Ma Haijun <mahaijuns@gmail.com>");
+MODULE_DESCRIPTION("NAS782x PCIe driver");
+MODULE_LICENSE("GPLv2");
diff --git a/target/linux/oxnas/files/drivers/pinctrl/pinctrl-oxnas.c b/target/linux/oxnas/files/drivers/pinctrl/pinctrl-oxnas.c
new file mode 100644 (file)
index 0000000..6cc8f72
--- /dev/null
@@ -0,0 +1,1480 @@
+/*
+ * oxnas pinctrl driver based on at91 pinctrl driver
+ *
+ * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2 only
+ */
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+/* Since we request GPIOs from ourself */
+#include <linux/pinctrl/consumer.h>
+
+#include "core.h"
+
+#include <mach/utils.h>
+
+#define MAX_NB_GPIO_PER_BANK   32
+#define MAX_GPIO_BANKS         2
+
+struct oxnas_gpio_chip {
+       struct gpio_chip        chip;
+       struct pinctrl_gpio_range range;
+       void __iomem            *regbase;  /* GPIOA/B virtual address */
+       void __iomem            *ctrlbase; /* SYS/SEC_CTRL virtual address */
+       struct irq_domain       *domain;   /* associated irq domain */
+};
+
+#define to_oxnas_gpio_chip(c) container_of(c, struct oxnas_gpio_chip, chip)
+
+static struct oxnas_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
+
+static int gpio_banks;
+
+#define PULL_UP                (1 << 0)
+#define PULL_DOWN      (1 << 1)
+#define DEBOUNCE       (1 << 2)
+
+/**
+ * struct oxnas_pmx_func - describes pinmux functions
+ * @name: the name of this specific function
+ * @groups: corresponding pin groups
+ * @ngroups: the number of groups
+ */
+struct oxnas_pmx_func {
+       const char      *name;
+       const char      **groups;
+       unsigned        ngroups;
+};
+
+enum oxnas_mux {
+       OXNAS_PINMUX_GPIO,
+       OXNAS_PINMUX_FUNC2,
+       OXNAS_PINMUX_FUNC3,
+       OXNAS_PINMUX_FUNC4,
+       OXNAS_PINMUX_DEBUG,
+       OXNAS_PINMUX_ALT,
+};
+
+enum {
+       INPUT_VALUE = 0,
+       OUTPUT_ENABLE = 4,
+       IRQ_PENDING = 0xC,
+       OUTPUT_VALUE = 0x10,
+       OUTPUT_SET = 0x14,
+       OUTPUT_CLEAR = 0x18,
+       OUTPUT_EN_SET = 0x1C,
+       OUTPUT_EN_CLEAR = 0x20,
+       DEBOUNCE_ENABLE = 0x24,
+       RE_IRQ_ENABLE = 0x28, /* rising edge */
+       FE_IRQ_ENABLE = 0x2C, /* falling edge */
+       RE_IRQ_PENDING = 0x30, /* rising edge */
+       FE_IRQ_PENDING = 0x34, /* falling edge */
+       CLOCK_DIV = 0x48,
+       PULL_ENABLE = 0x50,
+       PULL_SENSE = 0x54, /* 1 up, 0 down */
+
+
+       DEBOUNCE_MASK = 0x3FFF0000,
+       /* put hw debounce and soft config at same bit position*/
+       DEBOUNCE_SHIFT = 16
+};
+
+enum {
+       PINMUX_SECONDARY_SEL = 0x14,
+       PINMUX_TERTIARY_SEL = 0x8c,
+       PINMUX_QUATERNARY_SEL = 0x94,
+       PINMUX_DEBUG_SEL = 0x9c,
+       PINMUX_ALTERNATIVE_SEL = 0xa4,
+       PINMUX_PULLUP_SEL = 0xac,
+};
+
+/**
+ * struct oxnas_pmx_pin - describes an pin mux
+ * @bank: the bank of the pin
+ * @pin: the pin number in the @bank
+ * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
+ * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
+ */
+struct oxnas_pmx_pin {
+       uint32_t        bank;
+       uint32_t        pin;
+       enum oxnas_mux  mux;
+       unsigned long   conf;
+};
+
+/**
+ * struct oxnas_pin_group - describes an pin group
+ * @name: the name of this specific pin group
+ * @pins_conf: the mux mode for each pin in this group. The size of this
+ *     array is the same as pins.
+ * @pins: an array of discrete physical pins used in this group, taken
+ *     from the driver-local pin enumeration space
+ * @npins: the number of pins in this group array, i.e. the number of
+ *     elements in .pins so we can iterate over that array
+ */
+struct oxnas_pin_group {
+       const char              *name;
+       struct oxnas_pmx_pin    *pins_conf;
+       unsigned int            *pins;
+       unsigned                npins;
+};
+
+struct oxnas_pinctrl {
+       struct device           *dev;
+       struct pinctrl_dev      *pctl;
+
+       int                     nbanks;
+
+       uint32_t                *mux_mask;
+       int                     nmux;
+
+       struct oxnas_pmx_func   *functions;
+       int                     nfunctions;
+
+       struct oxnas_pin_group  *groups;
+       int                     ngroups;
+};
+
+static const inline struct oxnas_pin_group *oxnas_pinctrl_find_group_by_name(
+                               const struct oxnas_pinctrl *info,
+                               const char *name)
+{
+       const struct oxnas_pin_group *grp = NULL;
+       int i;
+
+       for (i = 0; i < info->ngroups; i++) {
+               if (strcmp(info->groups[i].name, name))
+                       continue;
+
+               grp = &info->groups[i];
+               dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins,
+                       grp->pins[0]);
+               break;
+       }
+
+       return grp;
+}
+
+static int oxnas_get_groups_count(struct pinctrl_dev *pctldev)
+{
+       struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+
+       return info->ngroups;
+}
+
+static const char *oxnas_get_group_name(struct pinctrl_dev *pctldev,
+                                      unsigned selector)
+{
+       struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+
+       return info->groups[selector].name;
+}
+
+static int oxnas_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
+                              const unsigned **pins,
+                              unsigned *npins)
+{
+       struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+
+       if (selector >= info->ngroups)
+               return -EINVAL;
+
+       *pins = info->groups[selector].pins;
+       *npins = info->groups[selector].npins;
+
+       return 0;
+}
+
+static void oxnas_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
+                  unsigned offset)
+{
+       seq_printf(s, "%s", dev_name(pctldev->dev));
+}
+
+static int oxnas_dt_node_to_map(struct pinctrl_dev *pctldev,
+                       struct device_node *np,
+                       struct pinctrl_map **map, unsigned *num_maps)
+{
+       struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+       const struct oxnas_pin_group *grp;
+       struct pinctrl_map *new_map;
+       struct device_node *parent;
+       int map_num = 1;
+       int i;
+
+       /*
+        * first find the group of this node and check if we need create
+        * config maps for pins
+        */
+       grp = oxnas_pinctrl_find_group_by_name(info, np->name);
+       if (!grp) {
+               dev_err(info->dev, "unable to find group for node %s\n",
+                       np->name);
+               return -EINVAL;
+       }
+
+       map_num += grp->npins;
+       new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
+                              GFP_KERNEL);
+       if (!new_map)
+               return -ENOMEM;
+
+       *map = new_map;
+       *num_maps = map_num;
+
+       /* create mux map */
+       parent = of_get_parent(np);
+       if (!parent) {
+               devm_kfree(pctldev->dev, new_map);
+               return -EINVAL;
+       }
+       new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
+       new_map[0].data.mux.function = parent->name;
+       new_map[0].data.mux.group = np->name;
+       of_node_put(parent);
+
+       /* create config map */
+       new_map++;
+       for (i = 0; i < grp->npins; i++) {
+               new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
+               new_map[i].data.configs.group_or_pin =
+                               pin_get_name(pctldev, grp->pins[i]);
+               new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
+               new_map[i].data.configs.num_configs = 1;
+       }
+
+       dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
+               (*map)->data.mux.function, (*map)->data.mux.group, map_num);
+
+       return 0;
+}
+
+static void oxnas_dt_free_map(struct pinctrl_dev *pctldev,
+                               struct pinctrl_map *map, unsigned num_maps)
+{
+}
+
+static const struct pinctrl_ops oxnas_pctrl_ops = {
+       .get_groups_count       = oxnas_get_groups_count,
+       .get_group_name         = oxnas_get_group_name,
+       .get_group_pins         = oxnas_get_group_pins,
+       .pin_dbg_show           = oxnas_pin_dbg_show,
+       .dt_node_to_map         = oxnas_dt_node_to_map,
+       .dt_free_map            = oxnas_dt_free_map,
+};
+
+static void __iomem *pin_to_gpioctrl(struct oxnas_pinctrl *info,
+                                unsigned int bank)
+{
+       return gpio_chips[bank]->regbase;
+}
+
+static void __iomem *pin_to_muxctrl(struct oxnas_pinctrl *info,
+                                unsigned int bank)
+{
+       return gpio_chips[bank]->ctrlbase;
+}
+
+
+static inline int pin_to_bank(unsigned pin)
+{
+       return pin / MAX_NB_GPIO_PER_BANK;
+}
+
+static unsigned pin_to_mask(unsigned int pin)
+{
+       return 1 << pin;
+}
+
+static void oxnas_mux_disable_interrupt(void __iomem *pio, unsigned mask)
+{
+       oxnas_register_clear_mask(pio + RE_IRQ_ENABLE, mask);
+       oxnas_register_clear_mask(pio + FE_IRQ_ENABLE, mask);
+}
+
+static unsigned oxnas_mux_get_pullup(void __iomem *pio, unsigned pin)
+{
+       return (readl_relaxed(pio + PULL_ENABLE) & BIT(pin)) &&
+               (readl_relaxed(pio + PULL_SENSE) & BIT(pin));
+}
+
+static void oxnas_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
+{
+       if (on) {
+               oxnas_register_set_mask(pio + PULL_SENSE, mask);
+               oxnas_register_set_mask(pio + PULL_ENABLE, mask);
+       } else {
+               oxnas_register_clear_mask(pio + PULL_ENABLE, mask);
+       }
+}
+
+static bool oxnas_mux_get_pulldown(void __iomem *pio, unsigned pin)
+{
+       return (readl_relaxed(pio + PULL_ENABLE) & BIT(pin)) &&
+                       (!(readl_relaxed(pio + PULL_SENSE) & BIT(pin)));
+}
+
+static void oxnas_mux_set_pulldown(void __iomem *pio, unsigned mask, bool on)
+{
+       if (on) {
+               oxnas_register_clear_mask(pio + PULL_SENSE, mask);
+               oxnas_register_set_mask(pio + PULL_ENABLE, mask);
+       } else {
+               oxnas_register_clear_mask(pio + PULL_ENABLE, mask);
+       };
+}
+
+/* unfortunately debounce control are shared */
+static bool oxnas_mux_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
+{
+       *div = __raw_readl(pio + CLOCK_DIV) & DEBOUNCE_MASK;
+       return __raw_readl(pio + DEBOUNCE_ENABLE) & BIT(pin);
+}
+
+static void oxnas_mux_set_debounce(void __iomem *pio, unsigned mask,
+                               bool is_on, u32 div)
+{
+       if (is_on) {
+               oxnas_register_value_mask(pio + CLOCK_DIV, DEBOUNCE_MASK, div);
+               oxnas_register_set_mask(pio + DEBOUNCE_ENABLE, mask);
+       } else {
+               oxnas_register_clear_mask(pio + DEBOUNCE_ENABLE, mask);
+       }
+}
+
+
+static void oxnas_mux_set_func2(void __iomem *cio, unsigned mask)
+{
+/* in fact, SECONDARY takes precedence, so clear others is not necessary */
+       oxnas_register_set_mask(cio + PINMUX_SECONDARY_SEL, mask);
+       oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask);
+       oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask);
+       oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask);
+       oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask);
+}
+
+static void oxnas_mux_set_func3(void __iomem *cio, unsigned mask)
+{
+       oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask);
+       oxnas_register_set_mask(cio + PINMUX_TERTIARY_SEL, mask);
+       oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask);
+       oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask);
+       oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask);
+}
+
+static void oxnas_mux_set_func4(void __iomem *cio, unsigned mask)
+{
+       oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask);
+       oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask);
+       oxnas_register_set_mask(cio + PINMUX_QUATERNARY_SEL, mask);
+       oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask);
+       oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask);
+}
+
+static void oxnas_mux_set_func_dbg(void __iomem *cio, unsigned mask)
+{
+       oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask);
+       oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask);
+       oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask);
+       oxnas_register_set_mask(cio + PINMUX_DEBUG_SEL, mask);
+       oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask);
+}
+
+static void oxnas_mux_set_func_alt(void __iomem *cio, unsigned mask)
+{
+       oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask);
+       oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask);
+       oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask);
+       oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask);
+       oxnas_register_set_mask(cio + PINMUX_ALTERNATIVE_SEL, mask);
+}
+
+static void oxnas_mux_set_gpio(void __iomem *cio, unsigned mask)
+{
+       oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask);
+       oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask);
+       oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask);
+       oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask);
+       oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask);
+}
+
+static enum oxnas_mux oxnas_mux_get_func(void __iomem *cio, unsigned mask)
+{
+       if (readl_relaxed(cio + PINMUX_SECONDARY_SEL) & mask)
+               return OXNAS_PINMUX_FUNC2;
+       if (readl_relaxed(cio + PINMUX_TERTIARY_SEL) & mask)
+               return OXNAS_PINMUX_FUNC3;
+       if (readl_relaxed(cio + PINMUX_QUATERNARY_SEL) & mask)
+               return OXNAS_PINMUX_FUNC4;
+       if (readl_relaxed(cio + PINMUX_DEBUG_SEL) & mask)
+               return OXNAS_PINMUX_DEBUG;
+       if (readl_relaxed(cio + PINMUX_ALTERNATIVE_SEL) & mask)
+               return OXNAS_PINMUX_ALT;
+       return OXNAS_PINMUX_GPIO;
+}
+
+
+static void oxnas_pin_dbg(const struct device *dev,
+                         const struct oxnas_pmx_pin *pin)
+{
+       if (pin->mux) {
+               dev_dbg(dev,
+                       "MF_%c%d configured as periph%c with conf = 0x%lu\n",
+                       pin->bank + 'A', pin->pin, pin->mux - 1 + 'A',
+                       pin->conf);
+       } else {
+               dev_dbg(dev, "MF_%c%d configured as gpio with conf = 0x%lu\n",
+                       pin->bank + 'A', pin->pin, pin->conf);
+       }
+}
+
+static int pin_check_config(struct oxnas_pinctrl *info, const char *name,
+                           int index, const struct oxnas_pmx_pin *pin)
+{
+       int mux;
+
+       /* check if it's a valid config */
+       if (pin->bank >= info->nbanks) {
+               dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
+                       name, index, pin->bank, info->nbanks);
+               return -EINVAL;
+       }
+
+       if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
+               dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
+                       name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
+               return -EINVAL;
+       }
+       /* gpio always allowed */
+       if (!pin->mux)
+               return 0;
+
+       mux = pin->mux - 1;
+
+       if (mux >= info->nmux) {
+               dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
+                       name, index, mux, info->nmux);
+               return -EINVAL;
+       }
+
+       if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
+               dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for MF_%c%d\n",
+                       name, index, mux, pin->bank + 'A', pin->pin);
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static void oxnas_mux_gpio_enable(void __iomem *cio, void __iomem *pio,
+                                 unsigned mask, bool input)
+{
+       oxnas_mux_set_gpio(cio, mask);
+       if (input)
+               writel_relaxed(mask, pio + OUTPUT_EN_CLEAR);
+       else
+               writel_relaxed(mask, pio + OUTPUT_EN_SET);
+}
+
+static void oxnas_mux_gpio_disable(void __iomem *cio, void __iomem *pio,
+                                  unsigned mask)
+{
+       /* when switch to other function,  gpio is disabled automatically */
+       return;
+}
+
+static int oxnas_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
+                           unsigned group)
+{
+       struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+       const struct oxnas_pmx_pin *pins_conf = info->groups[group].pins_conf;
+       const struct oxnas_pmx_pin *pin;
+       uint32_t npins = info->groups[group].npins;
+       int i, ret;
+       unsigned mask;
+       void __iomem *pio;
+       void __iomem *cio;
+
+       dev_dbg(info->dev, "enable function %s group %s\n",
+               info->functions[selector].name, info->groups[group].name);
+
+       /* first check that all the pins of the group are valid with a valid
+        * paramter */
+       for (i = 0; i < npins; i++) {
+               pin = &pins_conf[i];
+               ret = pin_check_config(info, info->groups[group].name, i, pin);
+               if (ret)
+                       return ret;
+       }
+
+       for (i = 0; i < npins; i++) {
+               pin = &pins_conf[i];
+               oxnas_pin_dbg(info->dev, pin);
+
+               pio = pin_to_gpioctrl(info, pin->bank);
+               cio = pin_to_muxctrl(info, pin->bank);
+
+               mask = pin_to_mask(pin->pin);
+               oxnas_mux_disable_interrupt(pio, mask);
+
+               switch (pin->mux) {
+               case OXNAS_PINMUX_GPIO:
+                       oxnas_mux_gpio_enable(cio, pio, mask, 1);
+                       break;
+               case OXNAS_PINMUX_FUNC2:
+                       oxnas_mux_set_func2(cio, mask);
+                       break;
+               case OXNAS_PINMUX_FUNC3:
+                       oxnas_mux_set_func3(cio, mask);
+                       break;
+               case OXNAS_PINMUX_FUNC4:
+                       oxnas_mux_set_func4(cio, mask);
+                       break;
+               case OXNAS_PINMUX_DEBUG:
+                       oxnas_mux_set_func_dbg(cio, mask);
+                       break;
+               case OXNAS_PINMUX_ALT:
+                       oxnas_mux_set_func_alt(cio, mask);
+                       break;
+               }
+               if (pin->mux)
+                       oxnas_mux_gpio_disable(cio, pio, mask);
+       }
+
+       return 0;
+}
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0))
+static void oxnas_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
+                             unsigned group)
+{
+       struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+       const struct oxnas_pmx_pin *pins_conf = info->groups[group].pins_conf;
+       const struct oxnas_pmx_pin *pin;
+       uint32_t npins = info->groups[group].npins;
+       int i;
+       unsigned mask;
+       void __iomem *pio;
+       void __iomem *cio;
+
+       for (i = 0; i < npins; i++) {
+               pin = &pins_conf[i];
+               oxnas_pin_dbg(info->dev, pin);
+               pio = pin_to_gpioctrl(info, pin->bank);
+               cio = pin_to_muxctrl(info, pin->bank);
+               mask = pin_to_mask(pin->pin);
+               oxnas_mux_gpio_enable(cio, pio, mask, 1);
+       }
+}
+#endif
+
+static int oxnas_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+       struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+
+       return info->nfunctions;
+}
+
+static const char *oxnas_pmx_get_func_name(struct pinctrl_dev *pctldev,
+                                          unsigned selector)
+{
+       struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+
+       return info->functions[selector].name;
+}
+
+static int oxnas_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
+                               const char * const **groups,
+                               unsigned * const num_groups)
+{
+       struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+
+       *groups = info->functions[selector].groups;
+       *num_groups = info->functions[selector].ngroups;
+
+       return 0;
+}
+
+static int oxnas_gpio_request_enable(struct pinctrl_dev *pctldev,
+                                    struct pinctrl_gpio_range *range,
+                                    unsigned offset)
+{
+       struct oxnas_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
+       struct oxnas_gpio_chip *oxnas_chip;
+       struct gpio_chip *chip;
+       unsigned mask;
+
+       if (!range) {
+               dev_err(npct->dev, "invalid range\n");
+               return -EINVAL;
+       }
+       if (!range->gc) {
+               dev_err(npct->dev, "missing GPIO chip in range\n");
+               return -EINVAL;
+       }
+       chip = range->gc;
+       oxnas_chip = container_of(chip, struct oxnas_gpio_chip, chip);
+
+       dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
+
+       mask = 1 << (offset - chip->base);
+
+       dev_dbg(npct->dev, "enable pin %u as MF_%c%d 0x%x\n",
+               offset, 'A' + range->id, offset - chip->base, mask);
+
+       oxnas_mux_set_gpio(oxnas_chip->ctrlbase, mask);
+
+       return 0;
+}
+
+static void oxnas_gpio_disable_free(struct pinctrl_dev *pctldev,
+                                   struct pinctrl_gpio_range *range,
+                                   unsigned offset)
+{
+       struct oxnas_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
+
+       dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
+       /* Set the pin to some default state, GPIO is usually default */
+}
+
+static const struct pinmux_ops oxnas_pmx_ops = {
+       .get_functions_count    = oxnas_pmx_get_funcs_count,
+       .get_function_name      = oxnas_pmx_get_func_name,
+       .get_function_groups    = oxnas_pmx_get_groups,
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0))
+       .set_mux                = oxnas_pmx_set_mux,
+#else
+       .enable                 = oxnas_pmx_set_mux,
+#endif
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0))
+       .disable                = oxnas_pmx_disable,
+#endif
+       .gpio_request_enable    = oxnas_gpio_request_enable,
+       .gpio_disable_free      = oxnas_gpio_disable_free,
+};
+
+static int oxnas_pinconf_get(struct pinctrl_dev *pctldev,
+                            unsigned pin_id, unsigned long *config)
+{
+       struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+       void __iomem *pio;
+       unsigned pin;
+       int div;
+
+       dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__,
+               __LINE__, pin_id, *config);
+       pio = pin_to_gpioctrl(info, pin_to_bank(pin_id));
+       pin = pin_id % MAX_NB_GPIO_PER_BANK;
+
+       if (oxnas_mux_get_pullup(pio, pin))
+               *config |= PULL_UP;
+
+       if (oxnas_mux_get_pulldown(pio, pin))
+               *config |= PULL_DOWN;
+
+       if (oxnas_mux_get_debounce(pio, pin, &div))
+               *config |= DEBOUNCE | div;
+       return 0;
+}
+
+static int oxnas_pinconf_set(struct pinctrl_dev *pctldev,
+                            unsigned pin_id, unsigned long *configs,
+                            unsigned num_configs)
+{
+       struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+       unsigned mask;
+       void __iomem *pio;
+       int i;
+       unsigned long config;
+
+       pio = pin_to_gpioctrl(info, pin_to_bank(pin_id));
+       mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK);
+
+       for (i = 0; i < num_configs; i++) {
+               config = configs[i];
+
+               dev_dbg(info->dev,
+                       "%s:%d, pin_id=%d, config=0x%lx",
+                       __func__, __LINE__, pin_id, config);
+
+               if ((config & PULL_UP) && (config & PULL_DOWN))
+                       return -EINVAL;
+
+               oxnas_mux_set_pullup(pio, mask, config & PULL_UP);
+               oxnas_mux_set_pulldown(pio, mask, config & PULL_DOWN);
+               oxnas_mux_set_debounce(pio, mask, config & DEBOUNCE,
+                                      config & DEBOUNCE_MASK);
+
+       } /* for each config */
+
+       return 0;
+}
+
+static void oxnas_pinconf_dbg_show(struct pinctrl_dev *pctldev,
+                                  struct seq_file *s, unsigned pin_id)
+{
+
+}
+
+static void oxnas_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
+                                        struct seq_file *s, unsigned group)
+{
+}
+
+static const struct pinconf_ops oxnas_pinconf_ops = {
+       .pin_config_get                 = oxnas_pinconf_get,
+       .pin_config_set                 = oxnas_pinconf_set,
+       .pin_config_dbg_show            = oxnas_pinconf_dbg_show,
+       .pin_config_group_dbg_show      = oxnas_pinconf_group_dbg_show,
+};
+
+static struct pinctrl_desc oxnas_pinctrl_desc = {
+       .pctlops        = &oxnas_pctrl_ops,
+       .pmxops         = &oxnas_pmx_ops,
+       .confops        = &oxnas_pinconf_ops,
+       .owner          = THIS_MODULE,
+};
+
+static const char *gpio_compat = "plxtech,nas782x-gpio";
+
+static void oxnas_pinctrl_child_count(struct oxnas_pinctrl *info,
+                                     struct device_node *np)
+{
+       struct device_node *child;
+
+       for_each_child_of_node(np, child) {
+               if (of_device_is_compatible(child, gpio_compat)) {
+                       info->nbanks++;
+               } else {
+                       info->nfunctions++;
+                       info->ngroups += of_get_child_count(child);
+               }
+       }
+}
+
+static int oxnas_pinctrl_mux_mask(struct oxnas_pinctrl *info,
+                                 struct device_node *np)
+{
+       int ret = 0;
+       int size;
+       const __be32 *list;
+
+       list = of_get_property(np, "plxtech,mux-mask", &size);
+       if (!list) {
+               dev_err(info->dev, "can not read the mux-mask of %d\n", size);
+               return -EINVAL;
+       }
+
+       size /= sizeof(*list);
+       if (!size || size % info->nbanks) {
+               dev_err(info->dev, "wrong mux mask array should be by %d\n",
+                       info->nbanks);
+               return -EINVAL;
+       }
+       info->nmux = size / info->nbanks;
+
+       info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
+       if (!info->mux_mask) {
+               dev_err(info->dev, "could not alloc mux_mask\n");
+               return -ENOMEM;
+       }
+
+       ret = of_property_read_u32_array(np, "plxtech,mux-mask",
+                                         info->mux_mask, size);
+       if (ret)
+               dev_err(info->dev, "can not read the mux-mask of %d\n", size);
+       return ret;
+}
+
+static int oxnas_pinctrl_parse_groups(struct device_node *np,
+                                     struct oxnas_pin_group *grp,
+                                     struct oxnas_pinctrl *info, u32 index)
+{
+       struct oxnas_pmx_pin *pin;
+       int size;
+       const __be32 *list;
+       int i, j;
+
+       dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
+
+       /* Initialise group */
+       grp->name = np->name;
+
+       /*
+        * the binding format is plxtech,pins = <bank pin mux CONFIG ...>,
+        * do sanity check and calculate pins number
+        */
+       list = of_get_property(np, "plxtech,pins", &size);
+       /* we do not check return since it's safe node passed down */
+       size /= sizeof(*list);
+       if (!size || size % 4) {
+               dev_err(info->dev, "wrong pins number or pins and configs"
+                       " should be divisible by 4\n");
+               return -EINVAL;
+       }
+
+       grp->npins = size / 4;
+       pin = grp->pins_conf = devm_kzalloc(info->dev,
+                               grp->npins * sizeof(struct oxnas_pmx_pin),
+                               GFP_KERNEL);
+       grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
+                               GFP_KERNEL);
+       if (!grp->pins_conf || !grp->pins)
+               return -ENOMEM;
+
+       for (i = 0, j = 0; i < size; i += 4, j++) {
+               pin->bank = be32_to_cpu(*list++);
+               pin->pin = be32_to_cpu(*list++);
+               grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
+               pin->mux = be32_to_cpu(*list++);
+               pin->conf = be32_to_cpu(*list++);
+
+               oxnas_pin_dbg(info->dev, pin);
+               pin++;
+       }
+
+       return 0;
+}
+
+static int oxnas_pinctrl_parse_functions(struct device_node *np,
+                                       struct oxnas_pinctrl *info, u32 index)
+{
+       struct device_node *child;
+       struct oxnas_pmx_func *func;
+       struct oxnas_pin_group *grp;
+       int ret;
+       static u32 grp_index;
+       u32 i = 0;
+
+       dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
+
+       func = &info->functions[index];
+
+       /* Initialise function */
+       func->name = np->name;
+       func->ngroups = of_get_child_count(np);
+       if (func->ngroups <= 0) {
+               dev_err(info->dev, "no groups defined\n");
+               return -EINVAL;
+       }
+       func->groups = devm_kzalloc(info->dev,
+                       func->ngroups * sizeof(char *), GFP_KERNEL);
+       if (!func->groups)
+               return -ENOMEM;
+
+       for_each_child_of_node(np, child) {
+               func->groups[i] = child->name;
+               grp = &info->groups[grp_index++];
+               ret = oxnas_pinctrl_parse_groups(child, grp, info, i++);
+               if (ret)
+                       return ret;
+       }
+
+       return 0;
+}
+
+static struct of_device_id oxnas_pinctrl_of_match[] = {
+       { .compatible = "plxtech,nas782x-pinctrl"},
+       { /* sentinel */ }
+};
+
+static int oxnas_pinctrl_probe_dt(struct platform_device *pdev,
+                                struct oxnas_pinctrl *info)
+{
+       int ret = 0;
+       int i, j;
+       uint32_t *tmp;
+       struct device_node *np = pdev->dev.of_node;
+       struct device_node *child;
+
+       if (!np)
+               return -ENODEV;
+
+       info->dev = &pdev->dev;
+
+       oxnas_pinctrl_child_count(info, np);
+
+       if (info->nbanks < 1) {
+               dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n");
+               return -EINVAL;
+       }
+
+       ret = oxnas_pinctrl_mux_mask(info, np);
+       if (ret)
+               return ret;
+
+       dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
+
+       dev_dbg(&pdev->dev, "mux-mask\n");
+       tmp = info->mux_mask;
+       for (i = 0; i < info->nbanks; i++)
+               for (j = 0; j < info->nmux; j++, tmp++)
+                       dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
+
+       dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
+       dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
+       info->functions = devm_kzalloc(&pdev->dev, info->nfunctions *
+                                               sizeof(struct oxnas_pmx_func),
+                                       GFP_KERNEL);
+       if (!info->functions)
+               return -ENOMEM;
+
+       info->groups = devm_kzalloc(&pdev->dev, info->ngroups *
+                                       sizeof(struct oxnas_pin_group),
+                                   GFP_KERNEL);
+       if (!info->groups)
+               return -ENOMEM;
+
+       dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks);
+       dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
+       dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
+
+       i = 0;
+
+       for_each_child_of_node(np, child) {
+               if (of_device_is_compatible(child, gpio_compat))
+                       continue;
+               ret = oxnas_pinctrl_parse_functions(child, info, i++);
+               if (ret) {
+                       dev_err(&pdev->dev, "failed to parse function\n");
+                       return ret;
+               }
+       }
+
+       return 0;
+}
+
+static int oxnas_pinctrl_probe(struct platform_device *pdev)
+{
+       struct oxnas_pinctrl *info;
+       struct pinctrl_pin_desc *pdesc;
+       int ret, i, j, k;
+
+       info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
+       if (!info)
+               return -ENOMEM;
+
+       ret = oxnas_pinctrl_probe_dt(pdev, info);
+       if (ret)
+               return ret;
+
+       /*
+        * We need all the GPIO drivers to probe FIRST, or we will not be able
+        * to obtain references to the struct gpio_chip * for them, and we
+        * need this to proceed.
+        */
+       for (i = 0; i < info->nbanks; i++) {
+               if (!gpio_chips[i]) {
+                       dev_warn(&pdev->dev,
+                                "GPIO chip %d not registered yet\n", i);
+                       devm_kfree(&pdev->dev, info);
+                       return -EPROBE_DEFER;
+               }
+       }
+
+       oxnas_pinctrl_desc.name = dev_name(&pdev->dev);
+       oxnas_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK;
+       oxnas_pinctrl_desc.pins = pdesc =
+               devm_kzalloc(&pdev->dev, sizeof(*pdesc) *
+                               oxnas_pinctrl_desc.npins, GFP_KERNEL);
+
+       if (!oxnas_pinctrl_desc.pins)
+               return -ENOMEM;
+
+       for (i = 0 , k = 0; i < info->nbanks; i++) {
+               for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
+                       pdesc->number = k;
+                       pdesc->name = kasprintf(GFP_KERNEL, "MF_%c%d", i + 'A',
+                                               j);
+                       pdesc++;
+               }
+       }
+
+       platform_set_drvdata(pdev, info);
+       info->pctl = pinctrl_register(&oxnas_pinctrl_desc, &pdev->dev, info);
+
+       if (!info->pctl) {
+               dev_err(&pdev->dev, "could not register OX820 pinctrl driver\n");
+               ret = -EINVAL;
+               goto err;
+       }
+
+       /* We will handle a range of GPIO pins */
+       for (i = 0; i < info->nbanks; i++)
+               pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
+
+       dev_info(&pdev->dev, "initialized OX820 pinctrl driver\n");
+
+       return 0;
+
+err:
+       return ret;
+}
+
+static int oxnas_pinctrl_remove(struct platform_device *pdev)
+{
+       struct oxnas_pinctrl *info = platform_get_drvdata(pdev);
+
+       pinctrl_unregister(info->pctl);
+
+       return 0;
+}
+
+static int oxnas_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+       /*
+        * Map back to global GPIO space and request muxing, the direction
+        * parameter does not matter for this controller.
+        */
+       int gpio = chip->base + offset;
+       int bank = chip->base / chip->ngpio;
+
+       dev_dbg(chip->dev, "%s:%d MF_%c%d(%d)\n", __func__, __LINE__,
+               'A' + bank, offset, gpio);
+
+       return pinctrl_request_gpio(gpio);
+}
+
+static void oxnas_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+       int gpio = chip->base + offset;
+
+       pinctrl_free_gpio(gpio);
+}
+
+static int oxnas_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+       struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip);
+       void __iomem *pio = oxnas_gpio->regbase;
+
+       writel_relaxed(BIT(offset), pio + OUTPUT_EN_CLEAR);
+       return 0;
+}
+
+static int oxnas_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+       struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip);
+       void __iomem *pio = oxnas_gpio->regbase;
+       unsigned mask = 1 << offset;
+       u32 pdsr;
+
+       pdsr = readl_relaxed(pio + INPUT_VALUE);
+       return (pdsr & mask) != 0;
+}
+
+static void oxnas_gpio_set(struct gpio_chip *chip, unsigned offset,
+                               int val)
+{
+       struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip);
+       void __iomem *pio = oxnas_gpio->regbase;
+
+       if (val)
+               writel_relaxed(BIT(offset), pio + OUTPUT_SET);
+       else
+               writel_relaxed(BIT(offset), pio + OUTPUT_CLEAR);
+
+}
+
+static int oxnas_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
+                               int val)
+{
+       struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip);
+       void __iomem *pio = oxnas_gpio->regbase;
+
+       if (val)
+               writel_relaxed(BIT(offset), pio + OUTPUT_SET);
+       else
+               writel_relaxed(BIT(offset), pio + OUTPUT_CLEAR);
+
+       writel_relaxed(BIT(offset), pio + OUTPUT_EN_SET);
+
+       return 0;
+}
+
+static int oxnas_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+       struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip);
+       int virq;
+
+       if (offset < chip->ngpio)
+               virq = irq_create_mapping(oxnas_gpio->domain, offset);
+       else
+               virq = -ENXIO;
+
+       dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
+                               chip->label, offset + chip->base, virq);
+       return virq;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static void oxnas_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
+{
+       enum oxnas_mux mode;
+       int i;
+       struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip);
+       void __iomem *pio = oxnas_gpio->regbase;
+       void __iomem *cio = oxnas_gpio->ctrlbase;
+
+       for (i = 0; i < chip->ngpio; i++) {
+               unsigned pin = chip->base + i;
+               unsigned mask = pin_to_mask(pin);
+               const char *gpio_label;
+               u32 pdsr;
+
+               gpio_label = gpiochip_is_requested(chip, i);
+               if (!gpio_label)
+                       continue;
+               /* FIXME */
+               mode = oxnas_mux_get_func(cio, mask);
+               seq_printf(s, "[%s] GPIO%s%d: ",
+                          gpio_label, chip->label, i);
+               if (mode == OXNAS_PINMUX_GPIO) {
+                       pdsr = readl_relaxed(pio + INPUT_VALUE);
+
+                       seq_printf(s, "[gpio] %s\n",
+                                  pdsr & mask ?
+                                  "set" : "clear");
+               } else {
+                       seq_printf(s, "[periph %c]\n",
+                                  mode + 'A' - 1);
+               }
+       }
+}
+#else
+#define oxnas_gpio_dbg_show    NULL
+#endif
+
+/* Several AIC controller irqs are dispatched through this GPIO handler.
+ * To use any AT91_PIN_* as an externally triggered IRQ, first call
+ * oxnas_set_gpio_input() then maybe enable its glitch filter.
+ * Then just request_irq() with the pin ID; it works like any ARM IRQ
+ * handler.
+ */
+
+static void gpio_irq_mask(struct irq_data *d)
+{
+       struct oxnas_gpio_chip *oxnas_gpio = irq_data_get_irq_chip_data(d);
+       void __iomem    *pio = oxnas_gpio->regbase;
+       unsigned        mask = 1 << d->hwirq;
+       unsigned        type = irqd_get_trigger_type(d);
+
+       /* FIXME: need proper lock */
+       if (type & IRQ_TYPE_EDGE_RISING)
+               oxnas_register_clear_mask(pio + RE_IRQ_ENABLE, mask);
+       if (type & IRQ_TYPE_EDGE_FALLING)
+               oxnas_register_clear_mask(pio + FE_IRQ_ENABLE, mask);
+}
+
+static void gpio_irq_unmask(struct irq_data *d)
+{
+       struct oxnas_gpio_chip *oxnas_gpio = irq_data_get_irq_chip_data(d);
+       void __iomem    *pio = oxnas_gpio->regbase;
+       unsigned        mask = 1 << d->hwirq;
+       unsigned        type = irqd_get_trigger_type(d);
+
+       /* FIXME: need proper lock */
+       if (type & IRQ_TYPE_EDGE_RISING)
+               oxnas_register_set_mask(pio + RE_IRQ_ENABLE, mask);
+       if (type & IRQ_TYPE_EDGE_FALLING)
+               oxnas_register_set_mask(pio + FE_IRQ_ENABLE, mask);
+}
+
+
+static int gpio_irq_type(struct irq_data *d, unsigned type)
+{
+       if ((type & IRQ_TYPE_EDGE_BOTH) == 0) {
+               pr_warn("OX820: Unsupported type for irq %d\n",
+                       gpio_to_irq(d->irq));
+               return -EINVAL;
+       }
+       /* seems no way to set trigger type without enable irq, so leave it to unmask time */
+
+       return 0;
+}
+
+static struct irq_chip gpio_irqchip = {
+       .name           = "GPIO",
+       .irq_disable    = gpio_irq_mask,
+       .irq_mask       = gpio_irq_mask,
+       .irq_unmask     = gpio_irq_unmask,
+       .irq_set_type   = gpio_irq_type,
+};
+
+static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
+{
+       struct irq_chip *chip = irq_desc_get_chip(desc);
+       struct irq_data *idata = irq_desc_get_irq_data(desc);
+       struct oxnas_gpio_chip *oxnas_gpio = irq_data_get_irq_chip_data(idata);
+       void __iomem *pio = oxnas_gpio->regbase;
+       unsigned long isr;
+       int n;
+
+       chained_irq_enter(chip, desc);
+       for (;;) {
+               /* TODO: see if it works */
+               isr = readl_relaxed(pio + IRQ_PENDING);
+               if (!isr)
+                       break;
+               /* acks pending interrupts */
+               writel_relaxed(isr, pio + IRQ_PENDING);
+
+               for_each_set_bit(n, &isr, BITS_PER_LONG) {
+                       generic_handle_irq(irq_find_mapping(oxnas_gpio->domain,
+                                                           n));
+               }
+       }
+       chained_irq_exit(chip, desc);
+       /* now it may re-trigger */
+}
+
+/*
+ * This lock class tells lockdep that GPIO irqs are in a different
+ * category than their parents, so it won't report false recursion.
+ */
+static struct lock_class_key gpio_lock_class;
+
+static int oxnas_gpio_irq_map(struct irq_domain *h, unsigned int virq,
+                             irq_hw_number_t hw)
+{
+       struct oxnas_gpio_chip *oxnas_gpio = h->host_data;
+
+       irq_set_lockdep_class(virq, &gpio_lock_class);
+
+       irq_set_chip_and_handler(virq, &gpio_irqchip, handle_edge_irq);
+       set_irq_flags(virq, IRQF_VALID);
+       irq_set_chip_data(virq, oxnas_gpio);
+
+       return 0;
+}
+
+static int oxnas_gpio_irq_domain_xlate(struct irq_domain *d,
+                                      struct device_node *ctrlr,
+                                      const u32 *intspec,
+                                      unsigned int intsize,
+                                      irq_hw_number_t *out_hwirq,
+                                      unsigned int *out_type)
+{
+       struct oxnas_gpio_chip *oxnas_gpio = d->host_data;
+       int ret;
+       int pin = oxnas_gpio->chip.base + intspec[0];
+
+       if (WARN_ON(intsize < 2))
+               return -EINVAL;
+       *out_hwirq = intspec[0];
+       *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
+
+       ret = gpio_request(pin, ctrlr->full_name);
+       if (ret)
+               return ret;
+
+       ret = gpio_direction_input(pin);
+       if (ret)
+               return ret;
+
+       return 0;
+}
+
+static struct irq_domain_ops oxnas_gpio_ops = {
+       .map    = oxnas_gpio_irq_map,
+       .xlate  = oxnas_gpio_irq_domain_xlate,
+};
+
+static int oxnas_gpio_of_irq_setup(struct device_node *node,
+                                  struct oxnas_gpio_chip *oxnas_gpio,
+                                  unsigned int irq)
+{
+       /* Disable irqs of this controller */
+       writel_relaxed(0, oxnas_gpio->regbase + RE_IRQ_ENABLE);
+       writel_relaxed(0, oxnas_gpio->regbase + FE_IRQ_ENABLE);
+
+       /* Setup irq domain */
+       oxnas_gpio->domain = irq_domain_add_linear(node, oxnas_gpio->chip.ngpio,
+                                                  &oxnas_gpio_ops, oxnas_gpio);
+       if (!oxnas_gpio->domain)
+               panic("oxnas_gpio: couldn't allocate irq domain (DT).\n");
+
+       irq_set_chip_data(irq, oxnas_gpio);
+       irq_set_chained_handler(irq, gpio_irq_handler);
+
+       return 0;
+}
+
+/* This structure is replicated for each GPIO block allocated at probe time */
+static struct gpio_chip oxnas_gpio_template = {
+       .request                = oxnas_gpio_request,
+       .free                   = oxnas_gpio_free,
+       .direction_input        = oxnas_gpio_direction_input,
+       .get                    = oxnas_gpio_get,
+       .direction_output       = oxnas_gpio_direction_output,
+       .set                    = oxnas_gpio_set,
+       .to_irq                 = oxnas_gpio_to_irq,
+       .dbg_show               = oxnas_gpio_dbg_show,
+       .can_sleep              = 0,
+       .ngpio                  = MAX_NB_GPIO_PER_BANK,
+};
+
+static struct of_device_id oxnas_gpio_of_match[] = {
+       { .compatible = "plxtech,nas782x-gpio"},
+       { /* sentinel */ }
+};
+
+static int oxnas_gpio_probe(struct platform_device *pdev)
+{
+       struct device_node *np = pdev->dev.of_node;
+       struct resource *res;
+       struct oxnas_gpio_chip *oxnas_chip = NULL;
+       struct gpio_chip *chip;
+       struct pinctrl_gpio_range *range;
+       int ret = 0;
+       int irq, i;
+       int alias_idx = of_alias_get_id(np, "gpio");
+       uint32_t ngpio;
+       char **names;
+
+       BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
+       if (gpio_chips[alias_idx]) {
+               ret = -EBUSY;
+               goto err;
+       }
+
+       irq = platform_get_irq(pdev, 0);
+       if (irq < 0) {
+               ret = irq;
+               goto err;
+       }
+
+       oxnas_chip = devm_kzalloc(&pdev->dev, sizeof(*oxnas_chip), GFP_KERNEL);
+       if (!oxnas_chip) {
+               ret = -ENOMEM;
+               goto err;
+       }
+
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       oxnas_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
+       if (IS_ERR(oxnas_chip->regbase)) {
+               ret = PTR_ERR(oxnas_chip->regbase);
+               goto err;
+       }
+
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+       oxnas_chip->ctrlbase = devm_ioremap_resource(&pdev->dev, res);
+       if (IS_ERR(oxnas_chip->ctrlbase)) {
+               ret = PTR_ERR(oxnas_chip->ctrlbase);
+               goto err;
+       }
+
+       oxnas_chip->chip = oxnas_gpio_template;
+
+       chip = &oxnas_chip->chip;
+       chip->of_node = np;
+       chip->label = dev_name(&pdev->dev);
+       chip->dev = &pdev->dev;
+       chip->owner = THIS_MODULE;
+       chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
+
+       if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
+               if (ngpio > MAX_NB_GPIO_PER_BANK)
+                       pr_err("oxnas_gpio.%d, gpio-nb >= %d failback to %d\n",
+                              alias_idx, MAX_NB_GPIO_PER_BANK,
+                              MAX_NB_GPIO_PER_BANK);
+               else
+                       chip->ngpio = ngpio;
+       }
+
+       names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio,
+                            GFP_KERNEL);
+
+       if (!names) {
+               ret = -ENOMEM;
+               goto err;
+       }
+
+       for (i = 0; i < chip->ngpio; i++)
+               names[i] = kasprintf(GFP_KERNEL, "MF_%c%d", alias_idx + 'A', i);
+
+       chip->names = (const char *const *)names;
+
+       range = &oxnas_chip->range;
+       range->name = chip->label;
+       range->id = alias_idx;
+       range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
+
+       range->npins = chip->ngpio;
+       range->gc = chip;
+
+       ret = gpiochip_add(chip);
+       if (ret)
+               goto err;
+
+       gpio_chips[alias_idx] = oxnas_chip;
+       gpio_banks = max(gpio_banks, alias_idx + 1);
+
+       oxnas_gpio_of_irq_setup(np, oxnas_chip, irq);
+
+       dev_info(&pdev->dev, "at address %p\n", oxnas_chip->regbase);
+
+       return 0;
+err:
+       dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
+
+       return ret;
+}
+
+static struct platform_driver oxnas_gpio_driver = {
+       .driver = {
+               .name = "gpio-oxnas",
+               .owner = THIS_MODULE,
+               .of_match_table = of_match_ptr(oxnas_gpio_of_match),
+       },
+       .probe = oxnas_gpio_probe,
+};
+
+static struct platform_driver oxnas_pinctrl_driver = {
+       .driver = {
+               .name = "pinctrl-oxnas",
+               .owner = THIS_MODULE,
+               .of_match_table = of_match_ptr(oxnas_pinctrl_of_match),
+       },
+       .probe = oxnas_pinctrl_probe,
+       .remove = oxnas_pinctrl_remove,
+};
+
+static int __init oxnas_pinctrl_init(void)
+{
+       int ret;
+
+       ret = platform_driver_register(&oxnas_gpio_driver);
+       if (ret)
+               return ret;
+       return platform_driver_register(&oxnas_pinctrl_driver);
+}
+arch_initcall(oxnas_pinctrl_init);
+
+static void __exit oxnas_pinctrl_exit(void)
+{
+       platform_driver_unregister(&oxnas_pinctrl_driver);
+}
+
+module_exit(oxnas_pinctrl_exit);
+MODULE_AUTHOR("Ma Hajun <mahaijuns@gmail.com>");
+MODULE_DESCRIPTION("Plxtech Nas782x pinctrl driver");
+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/oxnas/files/drivers/reset/reset-ox820.c b/target/linux/oxnas/files/drivers/reset/reset-ox820.c
new file mode 100644 (file)
index 0000000..0a28de5
--- /dev/null
@@ -0,0 +1,107 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <mach/hardware.h>
+
+static int ox820_reset_reset(struct reset_controller_dev *rcdev,
+                             unsigned long id)
+{
+       writel(BIT(id), SYS_CTRL_RST_SET_CTRL);
+       writel(BIT(id), SYS_CTRL_RST_CLR_CTRL);
+       return 0;
+}
+
+static int ox820_reset_assert(struct reset_controller_dev *rcdev,
+                             unsigned long id)
+{
+       writel(BIT(id), SYS_CTRL_RST_SET_CTRL);
+
+       return 0;
+}
+
+static int ox820_reset_deassert(struct reset_controller_dev *rcdev,
+                               unsigned long id)
+{
+       writel(BIT(id), SYS_CTRL_RST_CLR_CTRL);
+
+       return 0;
+}
+
+static struct reset_control_ops ox820_reset_ops = {
+       .reset          = ox820_reset_reset,
+       .assert         = ox820_reset_assert,
+       .deassert       = ox820_reset_deassert,
+};
+
+static const struct of_device_id ox820_reset_dt_ids[] = {
+        { .compatible = "plxtech,nas782x-reset", },
+        { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, ox820_reset_dt_ids);
+
+struct reset_controller_dev rcdev;
+
+static int ox820_reset_probe(struct platform_device *pdev)
+{
+       struct reset_controller_dev *rcdev;
+
+       rcdev = devm_kzalloc(&pdev->dev, sizeof(*rcdev), GFP_KERNEL);
+       if (!rcdev)
+               return -ENOMEM;
+
+       /* note: reset controller is statically mapped */
+
+       rcdev->owner = THIS_MODULE;
+       rcdev->nr_resets = 32;
+       rcdev->ops = &ox820_reset_ops;
+       rcdev->of_node = pdev->dev.of_node;
+       reset_controller_register(rcdev);
+       platform_set_drvdata(pdev, rcdev);
+
+       return 0;
+}
+
+static int ox820_reset_remove(struct platform_device *pdev)
+{
+       struct reset_controller_dev *rcdev = platform_get_drvdata(pdev);
+
+       reset_controller_unregister(rcdev);
+
+       return 0;
+}
+
+static struct platform_driver ox820_reset_driver = {
+       .probe  = ox820_reset_probe,
+       .remove = ox820_reset_remove,
+       .driver = {
+               .name           = "ox820-reset",
+               .owner          = THIS_MODULE,
+               .of_match_table = ox820_reset_dt_ids,
+       },
+};
+
+static int __init ox820_reset_init(void)
+{
+       return platform_driver_probe(&ox820_reset_driver,
+                                    ox820_reset_probe);
+}
+/*
+ * reset controller does not support probe deferral, so it has to be
+ * initialized before any user, in particular, PCIE uses subsys_initcall.
+ */
+arch_initcall(ox820_reset_init);
+
+MODULE_AUTHOR("Ma Haijun");
+MODULE_LICENSE("GPL");
diff --git a/target/linux/oxnas/files/drivers/usb/host/ehci-oxnas.c b/target/linux/oxnas/files/drivers/usb/host/ehci-oxnas.c
new file mode 100644 (file)
index 0000000..23c5061
--- /dev/null
@@ -0,0 +1,316 @@
+/*
+ * drivers/usb/host/ehci-oxnas.c
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/usb.h>
+#include <linux/usb/hcd.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <mach/hardware.h>
+#include <mach/utils.h>
+
+#include "ehci.h"
+
+struct oxnas_hcd {
+       struct clk *clk;
+       struct clk *refsrc;
+       struct clk *phyref;
+       int use_pllb;
+       int use_phya;
+       struct reset_control *rst_host;
+       struct reset_control *rst_phya;
+       struct reset_control *rst_phyb;
+};
+
+#define DRIVER_DESC "Oxnas On-Chip EHCI Host Controller"
+
+static struct hc_driver __read_mostly oxnas_hc_driver;
+
+static void start_oxnas_usb_ehci(struct oxnas_hcd *oxnas)
+{
+       u32 reg;
+
+       if (oxnas->use_pllb) {
+               /* enable pllb */
+               clk_prepare_enable(oxnas->refsrc);
+               /* enable ref600 */
+               clk_prepare_enable(oxnas->phyref);
+               /* 600MHz pllb divider for 12MHz */
+               writel(PLLB_DIV_INT(50) | PLLB_DIV_FRAC(0),
+                       SEC_CTRL_PLLB_DIV_CTRL);
+
+       } else {
+               /* ref 300 divider for 12MHz */
+               writel(REF300_DIV_INT(25) | REF300_DIV_FRAC(0),
+                       SYS_CTRL_REF300_DIV);
+       }
+
+       /* Ensure the USB block is properly reset */
+       reset_control_reset(oxnas->rst_host);
+       reset_control_reset(oxnas->rst_phya);
+       reset_control_reset(oxnas->rst_phyb);
+
+       /* Force the high speed clock to be generated all the time, via serial
+        programming of the USB HS PHY */
+       writel((2UL << USBHSPHY_TEST_ADD) |
+                  (0xe0UL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
+
+       writel((1UL << USBHSPHY_TEST_CLK) |
+                  (2UL << USBHSPHY_TEST_ADD) |
+                  (0xe0UL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
+
+       writel((0xfUL << USBHSPHY_TEST_ADD) |
+                  (0xaaUL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
+
+       writel((1UL << USBHSPHY_TEST_CLK) |
+                  (0xfUL << USBHSPHY_TEST_ADD) |
+                  (0xaaUL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
+
+       if (oxnas->use_pllb) /* use pllb clock */
+               writel(USB_CLK_INTERNAL | USB_INT_CLK_PLLB, SYS_CTRL_USB_CTRL);
+       else /* use ref300 derived clock */
+               writel(USB_CLK_INTERNAL | USB_INT_CLK_REF300,
+                       SYS_CTRL_USB_CTRL);
+
+       if (oxnas->use_phya) {
+               /* Configure USB PHYA as a host */
+               reg = readl(SYS_CTRL_USB_CTRL);
+               reg &= ~USBAMUX_DEVICE;
+               writel(reg, SYS_CTRL_USB_CTRL);
+       }
+
+       /* Enable the clock to the USB block */
+       clk_prepare_enable(oxnas->clk);
+}
+
+static void stop_oxnas_usb_ehci(struct oxnas_hcd *oxnas)
+{
+       reset_control_assert(oxnas->rst_host);
+       reset_control_assert(oxnas->rst_phya);
+       reset_control_assert(oxnas->rst_phyb);
+
+       if (oxnas->use_pllb) {
+               clk_disable_unprepare(oxnas->phyref);
+               clk_disable_unprepare(oxnas->refsrc);
+       }
+       clk_disable_unprepare(oxnas->clk);
+}
+
+static int ehci_oxnas_reset(struct usb_hcd *hcd)
+{
+       #define  txttfill_tuning        reserved2[0]
+
+       struct ehci_hcd *ehci;
+       u32 tmp;
+       int retval = ehci_setup(hcd);
+       if (retval)
+               return retval;
+
+       ehci = hcd_to_ehci(hcd);
+       tmp = ehci_readl(ehci, &ehci->regs->txfill_tuning);
+       tmp &= ~0x00ff0000;
+       tmp |= 0x003f0000; /* set burst pre load count to 0x40 (63 * 4 bytes)  */
+       tmp |= 0x16; /* set sheduler overhead to 22 * 1.267us (HS) or 22 * 6.33us (FS/LS)*/
+       ehci_writel(ehci, tmp,  &ehci->regs->txfill_tuning);
+
+       tmp = ehci_readl(ehci, &ehci->regs->txttfill_tuning);
+       tmp |= 0x2; /* set sheduler overhead to 2 * 6.333us */
+       ehci_writel(ehci, tmp,  &ehci->regs->txttfill_tuning);
+
+       return retval;
+}
+
+static int ehci_oxnas_drv_probe(struct platform_device *ofdev)
+{
+       struct device_node *np = ofdev->dev.of_node;
+       struct usb_hcd *hcd;
+       struct ehci_hcd *ehci;
+       struct resource res;
+       struct oxnas_hcd *oxnas;
+       int irq, err;
+       struct reset_control *rstc;
+
+       if (usb_disabled())
+               return -ENODEV;
+
+       if (!ofdev->dev.dma_mask)
+               ofdev->dev.dma_mask = &ofdev->dev.coherent_dma_mask;
+       if (!ofdev->dev.coherent_dma_mask)
+               ofdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+
+       hcd = usb_create_hcd(&oxnas_hc_driver,  &ofdev->dev,
+                                       dev_name(&ofdev->dev));
+       if (!hcd)
+               return -ENOMEM;
+
+       err = of_address_to_resource(np, 0, &res);
+       if (err)
+               goto err_res;
+
+       hcd->rsrc_start = res.start;
+       hcd->rsrc_len = resource_size(&res);
+
+       hcd->regs = devm_ioremap_resource(&ofdev->dev, &res);
+       if (IS_ERR(hcd->regs)) {
+               dev_err(&ofdev->dev, "devm_ioremap_resource failed\n");
+               err = PTR_ERR(hcd->regs);
+               goto err_ioremap;
+       }
+
+       oxnas = (struct oxnas_hcd *)hcd_to_ehci(hcd)->priv;
+
+       oxnas->use_pllb = of_property_read_bool(np, "plxtch,ehci_use_pllb");
+       oxnas->use_phya = of_property_read_bool(np, "plxtch,ehci_use_phya");
+
+       oxnas->clk = of_clk_get_by_name(np, "usb");
+       if (IS_ERR(oxnas->clk)) {
+               err = PTR_ERR(oxnas->clk);
+               goto err_clk;
+       }
+
+       if (oxnas->use_pllb) {
+               oxnas->refsrc = of_clk_get_by_name(np, "refsrc");
+               if (IS_ERR(oxnas->refsrc)) {
+                       err = PTR_ERR(oxnas->refsrc);
+                       goto err_refsrc;
+               }
+               oxnas->phyref = of_clk_get_by_name(np, "phyref");
+               if (IS_ERR(oxnas->refsrc)) {
+                       err = PTR_ERR(oxnas->refsrc);
+                       goto err_phyref;
+               }
+
+       } else {
+               oxnas->refsrc = NULL;
+               oxnas->phyref = NULL;
+       }
+
+       rstc = devm_reset_control_get(&ofdev->dev, "host");
+       if (IS_ERR(rstc)) {
+               err = PTR_ERR(rstc);
+               goto err_rst;
+       }
+       oxnas->rst_host = rstc;
+
+       rstc = devm_reset_control_get(&ofdev->dev, "phya");
+       if (IS_ERR(rstc)) {
+               err = PTR_ERR(rstc);
+               goto err_rst;
+       }
+       oxnas->rst_phya = rstc;
+
+       rstc = devm_reset_control_get(&ofdev->dev, "phyb");
+       if (IS_ERR(rstc)) {
+               err = PTR_ERR(rstc);
+               goto err_rst;
+       }
+       oxnas->rst_phyb = rstc;
+
+       irq = irq_of_parse_and_map(np, 0);
+       if (!irq) {
+               dev_err(&ofdev->dev, "irq_of_parse_and_map failed\n");
+               err = -EBUSY;
+               goto err_irq;
+       }
+
+       hcd->has_tt = 1;
+       ehci = hcd_to_ehci(hcd);
+       ehci->caps = hcd->regs;
+
+       start_oxnas_usb_ehci(oxnas);
+
+       err = usb_add_hcd(hcd, irq, IRQF_SHARED | IRQF_DISABLED);
+       if (err)
+               goto err_hcd;
+
+       return 0;
+
+err_hcd:
+       stop_oxnas_usb_ehci(oxnas);
+err_irq:
+err_rst:
+       if (oxnas->phyref)
+               clk_put(oxnas->phyref);
+err_phyref:
+       if (oxnas->refsrc)
+               clk_put(oxnas->refsrc);
+err_refsrc:
+       clk_put(oxnas->clk);
+err_clk:
+err_ioremap:
+err_res:
+       usb_put_hcd(hcd);
+
+       return err;
+}
+
+static int ehci_oxnas_drv_remove(struct platform_device *pdev)
+{
+       struct usb_hcd *hcd = platform_get_drvdata(pdev);
+       struct oxnas_hcd *oxnas = (struct oxnas_hcd *)hcd_to_ehci(hcd)->priv;
+
+       usb_remove_hcd(hcd);
+       if (oxnas->use_pllb) {
+               clk_disable_unprepare(oxnas->phyref);
+               clk_put(oxnas->phyref);
+               clk_disable_unprepare(oxnas->refsrc);
+               clk_put(oxnas->refsrc);
+       }
+       clk_disable_unprepare(oxnas->clk);
+       usb_put_hcd(hcd);
+
+       return 0;
+}
+
+static const struct of_device_id oxnas_ehci_dt_ids[] = {
+       { .compatible = "plxtch,nas782x-ehci" },
+       { /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, oxnas_ehci_dt_ids);
+
+static struct platform_driver ehci_oxnas_driver = {
+       .probe          = ehci_oxnas_drv_probe,
+       .remove         = ehci_oxnas_drv_remove,
+       .shutdown       = usb_hcd_platform_shutdown,
+       .driver.name    = "oxnas-ehci",
+       .driver.of_match_table  = oxnas_ehci_dt_ids,
+};
+
+static const struct ehci_driver_overrides oxnas_overrides __initconst = {
+       .reset = ehci_oxnas_reset,
+       .extra_priv_size = sizeof(struct oxnas_hcd),
+};
+
+static int __init ehci_oxnas_init(void)
+{
+       if (usb_disabled())
+               return -ENODEV;
+
+       ehci_init_driver(&oxnas_hc_driver, &oxnas_overrides);
+       return platform_driver_register(&ehci_oxnas_driver);
+}
+module_init(ehci_oxnas_init);
+
+static void __exit ehci_oxnas_cleanup(void)
+{
+       platform_driver_unregister(&ehci_oxnas_driver);
+}
+module_exit(ehci_oxnas_cleanup);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_ALIAS("platform:oxnas-ehci");
+MODULE_LICENSE("GPL");
diff --git a/target/linux/oxnas/image/Makefile b/target/linux/oxnas/image/Makefile
new file mode 100644 (file)
index 0000000..3a2a58d
--- /dev/null
@@ -0,0 +1,135 @@
+#
+# Copyright (C) 2013 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/image.mk
+
+STG212_UBI_OPTS = -m 2048 -p 128KiB -s 512
+STG212_UBIFS_OPTS = -m 2048 -e 126KiB -c 4096
+
+KD20_UBI_OPTS = -m 2048 -p 128KiB -s 512
+KD20_UBIFS_OPTS = -m 2048 -e 126KiB -c 4096
+
+POGOPLUG_PRO_UBI_OPTS = -m 2048 -p 128KiB -s 512
+POGOPLUG_PRO_UBIFS_OPTS = -m 2048 -e 126KiB -c 4096
+
+POGOPLUG_V3_UBI_OPTS = -m 2048 -p 128KiB -s 512
+POGOPLUG_V3_UBIFS_OPTS = -m 2048 -e 126KiB -c 4096
+
+KDIR_TMP:=$(KDIR)/tmp
+VMLINUX:=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux
+UIMAGE:=$(BIN_DIR)/$(IMG_PREFIX)-uImage
+
+define sanitize_profile_name
+$(shell echo $(PROFILE) | tr '[:upper:]' '[:lower:]' | sed 's/_/-/g')
+endef
+
+define Image/BuildKernel/Template
+       $(CP) $(LINUX_DIR)/arch/arm/boot/dts/ox820-$(1).dtb $(BIN_DIR)/$(IMG_PREFIX)-$(1).dtb
+
+       $(call Image/BuildKernel/MkFIT,$(1),$(KDIR)/zImage,$(BIN_DIR)/$(IMG_PREFIX)-$(1).dtb,none,0x60008000,0x60008000)
+       $(CP) $(KDIR)/fit-$(1).itb $(BIN_DIR)/$(IMG_PREFIX)-$(1)-fit-uImage.bin
+
+ ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
+       $(call Image/BuildKernel/MkFIT,$(1),$(KDIR)/zImage-initramfs,$(BIN_DIR)/$(IMG_PREFIX)-$(1).dtb,none,0x60008000,0x60008000,-initramfs)
+       $(CP) $(KDIR)/fit-$(1)-initramfs.itb $(BIN_DIR)/$(IMG_PREFIX)-$(1)-fit-uImage-initramfs.itb
+       if [ -e "$(BIN_DIR)/$(IMG_PREFIX)-ox820-u-boot.bin" ]; then \
+       ( dd if=$(BIN_DIR)/$(IMG_PREFIX)-ox820-u-boot.bin bs=128k conv=sync ; dd if=$(KDIR)/fit-$(1)-initramfs.itb bs=128k conv=sync ) \
+               > $(BIN_DIR)/$(IMG_PREFIX)-$(1)-u-boot-initramfs.itb; \
+       fi
+ endif
+
+       $(CP) $(KDIR)/zImage $(BIN_DIR)/$(IMG_PREFIX)-zImage
+       $(call Image/BuildKernel/MkuImage, \
+               none, 0x60008000, 0x60008000, \
+               $(BIN_DIR)/$(IMG_PREFIX)-zImage, \
+               $(BIN_DIR)/$(IMG_PREFIX)-uImage \
+       )
+
+ ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
+       $(CP) $(KDIR)/zImage-initramfs $(BIN_DIR)/$(IMG_PREFIX)-zImage-initramfs
+       $(call Image/BuildKernel/MkuImage, \
+               none, 0x60008000, 0x60008000, \
+               $(BIN_DIR)/$(IMG_PREFIX)-zImage-initramfs, \
+               $(BIN_DIR)/$(IMG_PREFIX)-uImage-initramfs \
+       )
+ endif
+endef
+
+define Image/InstallKernel/Template
+
+ ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_KERNEL),)
+       $(INSTALL_DIR) $(TARGET_DIR)/boot
+   ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_UIMAGE),)
+       $(CP) $(BIN_DIR)/$(IMG_PREFIX)-uImage $(TARGET_DIR)/boot/
+       ln -sf $(IMG_PREFIX)-uImage $(TARGET_DIR)/boot/uImage
+   endif
+   ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_ZIMAGE),)
+       $(CP) $(BIN_DIR)/$(IMG_PREFIX)-zImage $(TARGET_DIR)/boot/
+       ln -sf $(IMG_PREFIX)-zImage $(TARGET_DIR)/boot/zImage
+   endif
+   ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_FIT),)
+       $(CP) $(BIN_DIR)/$(IMG_PREFIX)-$(1)-fit-uImage.itb $(TARGET_DIR)/boot/
+       ln -sf $(IMG_PREFIX)-$(1)-fit-uImage.itb $(TARGET_DIR)/boot/uImage.itb
+   endif
+ endif
+
+ ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_DTB),)
+       $(INSTALL_DIR) $(TARGET_DIR)/boot
+  ifneq ($(1),)
+       $(CP) $(BIN_DIR)/$(IMG_PREFIX)-$(1).dtb $(TARGET_DIR)/boot/
+       ln -sf $(IMG_PREFIX)-$(1).dtb $(TARGET_DIR)/boot/$(1).dtb
+  endif
+ endif
+endef
+
+define Image/Build/squashfs
+       $(call Image/Build/SysupgradeNAND,$(call sanitize_profile_name),$(1),$(KDIR)/fit-$(call sanitize_profile_name).itb)
+       $(call Image/Build/UbinizeImage,$(call sanitize_profile_name),--uboot-env --kernel $(KDIR)/fit-$(call sanitize_profile_name).itb,$(1),$($(PROFILE)_UBI_OPTS))
+endef
+
+define Image/mkfs/targz
+
+       $(TAR) -czpf $(BIN_DIR)/$(IMG_PREFIX)-$(call sanitize_profile_name)-rootfs.tar.gz --numeric-owner --owner=0 --group=0 -C $(TARGET_DIR)/ .
+endef
+
+define Image/Build/ubifs
+
+ ifneq ($($(PROFILE)_UBIFS_OPTS),)
+       $(call Image/Build/SysupgradeNAND,$(call sanitize_profile_name),ubifs,$(KDIR)/fit-$(call sanitize_profile_name).itb)
+       $(call Image/Build/UbinizeImage,$(call sanitize_profile_name),--uboot-env --kernel $(KDIR)/fit-$(call sanitize_profile_name).itb,ubifs,$($(PROFILE)_UBI_OPTS))
+ endif
+
+endef
+
+Image/BuildKernel/Template/POGOPLUG_PRO=$(call Image/BuildKernel/Template,pogoplug-pro)
+Image/InstallKernel/Template/POGOPLUG_PRO=$(call Image/InstallKernel/Template,pogoplug-pro)
+
+Image/BuildKernel/Template/POGOPLUG_V3=$(call Image/BuildKernel/Template,pogoplug-v3)
+Image/InstallKernel/Template/POGOPLUG_V3=$(call Image/InstallKernel/Template,pogoplug-v3)
+
+Image/BuildKernel/Template/STG212=$(call Image/BuildKernel/Template,stg212)
+Image/InstallKernel/Template/STG212=$(call Image/InstallKernel/Template,stg212)
+
+Image/BuildKernel/Template/KD20=$(call Image/BuildKernel/Template,kd20)
+Image/InstallKernel/Template/KD20=$(call Image/InstallKernel/Template,kd20)
+
+define Image/BuildKernel
+       $(call Image/BuildKernel/Template/$(PROFILE))
+endef
+
+define Image/InstallKernel
+       $(call Image/InstallKernel/Template/$(PROFILE))
+endef
+
+define Image/Build
+       $(if $(Image/Build/$(1)), \
+               $(call Image/Build/$(1),$(1)), \
+               $(CP) $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(call sanitize_profile_name)-$(1).img \
+       )
+endef
+
+$(eval $(call BuildImage))
diff --git a/target/linux/oxnas/patches-3.18/010-arm_introduce-dma-fiq-irq-broadcast.patch b/target/linux/oxnas/patches-3.18/010-arm_introduce-dma-fiq-irq-broadcast.patch
new file mode 100644 (file)
index 0000000..fb7547f
--- /dev/null
@@ -0,0 +1,62 @@
+Index: linux-3.18-rc4/arch/arm/include/asm/glue-cache.h
+===================================================================
+--- linux-3.18-rc4.orig/arch/arm/include/asm/glue-cache.h
++++ linux-3.18-rc4/arch/arm/include/asm/glue-cache.h
+@@ -156,11 +156,19 @@ static inline void nop_dma_unmap_area(co
+ #define __cpuc_flush_user_range               __glue(_CACHE,_flush_user_cache_range)
+ #define __cpuc_coherent_kern_range    __glue(_CACHE,_coherent_kern_range)
+ #define __cpuc_coherent_user_range    __glue(_CACHE,_coherent_user_range)
++#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST
+ #define __cpuc_flush_dcache_area      __glue(_CACHE,_flush_kern_dcache_area)
+ #define dmac_map_area                 __glue(_CACHE,_dma_map_area)
+ #define dmac_unmap_area                       __glue(_CACHE,_dma_unmap_area)
+ #define dmac_flush_range              __glue(_CACHE,_dma_flush_range)
++#else
++#define __cpuc_flush_dcache_area      __glue(fiq,_flush_kern_dcache_area)
++
++#define dmac_map_area                 __glue(fiq,_dma_map_area)
++#define dmac_unmap_area                       __glue(fiq,_dma_unmap_area)
++#define dmac_flush_range              __glue(fiq,_dma_flush_range)
++#endif /* CONFIG_DMA_CACHE_FIQ_BROADCAST */
+ #endif
+ #endif
+Index: linux-3.18-rc4/arch/arm/mm/Kconfig
+===================================================================
+--- linux-3.18-rc4.orig/arch/arm/mm/Kconfig
++++ linux-3.18-rc4/arch/arm/mm/Kconfig
+@@ -843,6 +843,17 @@ config DMA_CACHE_RWFO
+         in hardware, other workarounds are needed (e.g. cache
+         maintenance broadcasting in software via FIQ).
++config DMA_CACHE_FIQ_BROADCAST
++      bool "Enable fiq broadcast DMA cache maintenance"
++      depends on CPU_V6K && SMP
++      select FIQ
++      help
++        The Snoop Control Unit on ARM11MPCore does not detect the
++        cache maintenance operations and the dma_{map,unmap}_area()
++        functions may leave stale cache entries on other CPUs. By
++        enabling this option, fiq broadcast in the ARMv6
++        DMA cache maintenance functions is performed.
++
+ config OUTER_CACHE
+       bool
+Index: linux-3.18-rc4/arch/arm/mm/flush.c
+===================================================================
+--- linux-3.18-rc4.orig/arch/arm/mm/flush.c
++++ linux-3.18-rc4/arch/arm/mm/flush.c
+@@ -314,7 +314,11 @@ void flush_dcache_page(struct page *page
+       mapping = page_mapping(page);
++#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST
+       if (!cache_ops_need_broadcast() &&
++#else
++      if (
++#endif
+           mapping && !page_mapped(page))
+               clear_bit(PG_dcache_clean, &page->flags);
+       else {
diff --git a/target/linux/oxnas/patches-3.18/250-add-plxtech-vendor-prefix.patch b/target/linux/oxnas/patches-3.18/250-add-plxtech-vendor-prefix.patch
new file mode 100644 (file)
index 0000000..c495258
--- /dev/null
@@ -0,0 +1,12 @@
+Index: linux-3.18-rc4/Documentation/devicetree/bindings/vendor-prefixes.txt
+===================================================================
+--- linux-3.18-rc4.orig/Documentation/devicetree/bindings/vendor-prefixes.txt
++++ linux-3.18-rc4/Documentation/devicetree/bindings/vendor-prefixes.txt
+@@ -113,6 +113,7 @@ panasonic  Panasonic Corporation
+ phytec        PHYTEC Messtechnik GmbH
+ picochip      Picochip Ltd
+ plathome      Plat'Home Co., Ltd.
++plxtech       PLX Technology, Inc.
+ pixcir  PIXCIR MICROELECTRONICS Co., Ltd
+ powervr       PowerVR (deprecated, use img)
+ qca   Qualcomm Atheros, Inc.
diff --git a/target/linux/oxnas/patches-3.18/300-introduce-oxnas-platform.patch b/target/linux/oxnas/patches-3.18/300-introduce-oxnas-platform.patch
new file mode 100644 (file)
index 0000000..17ec83b
--- /dev/null
@@ -0,0 +1,79 @@
+Index: linux-3.18-rc4/arch/arm/Kconfig
+===================================================================
+--- linux-3.18-rc4.orig/arch/arm/Kconfig
++++ linux-3.18-rc4/arch/arm/Kconfig
+@@ -369,6 +369,17 @@ config ARCH_VERSATILE
+       help
+         This enables support for ARM Ltd Versatile board.
++config ARCH_OXNAS
++      bool "Oxford Semiconductor 815/820/825 NAS SoC"
++      select ARCH_REQUIRE_GPIOLIB
++      select CLKDEV_LOOKUP
++      select GENERIC_CLOCKEVENTS
++      select COMMON_CLK
++      select MIGHT_HAVE_PCI
++      select ARCH_HAS_RESET_CONTROLLER
++      help
++              This enables support for Oxsemi 815/820/825 NAS SoC
++
+ config ARCH_AT91
+       bool "Atmel AT91"
+       select ARCH_REQUIRE_GPIOLIB
+@@ -922,6 +933,8 @@ source "arch/arm/mach-omap2/Kconfig"
+ source "arch/arm/mach-orion5x/Kconfig"
++source "arch/arm/mach-oxnas/Kconfig"
++
+ source "arch/arm/mach-picoxcell/Kconfig"
+ source "arch/arm/mach-pxa/Kconfig"
+Index: linux-3.18-rc4/arch/arm/Makefile
+===================================================================
+--- linux-3.18-rc4.orig/arch/arm/Makefile
++++ linux-3.18-rc4/arch/arm/Makefile
+@@ -187,6 +187,7 @@ machine-$(CONFIG_ARCH_NSPIRE)              += nspire
+ machine-$(CONFIG_ARCH_OMAP1)          += omap1
+ machine-$(CONFIG_ARCH_OMAP2PLUS)      += omap2
+ machine-$(CONFIG_ARCH_ORION5X)                += orion5x
++machine-$(CONFIG_ARCH_OXNAS)          += oxnas
+ machine-$(CONFIG_ARCH_PICOXCELL)      += picoxcell
+ machine-$(CONFIG_ARCH_PXA)            += pxa
+ machine-$(CONFIG_ARCH_QCOM)           += qcom
+Index: linux-3.18-rc4/arch/arm/boot/dts/Makefile
+===================================================================
+--- linux-3.18-rc4.orig/arch/arm/boot/dts/Makefile
++++ linux-3.18-rc4/arch/arm/boot/dts/Makefile
+@@ -352,6 +352,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += orion5x-la
+       orion5x-lacie-ethernet-disk-mini-v2.dtb \
+       orion5x-maxtor-shared-storage-2.dtb \
+       orion5x-rd88f5182-nas.dtb
++dtb-$(CONFIG_ARCH_OXNAS) += ox820-pogoplug-pro.dtb
+ dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
+ dtb-$(CONFIG_ARCH_QCOM) += \
+       qcom-apq8064-cm-qs600.dtb \
+Index: linux-3.18-rc4/arch/arm/tools/mach-types
+===================================================================
+--- linux-3.18-rc4.orig/arch/arm/tools/mach-types
++++ linux-3.18-rc4/arch/arm/tools/mach-types
+@@ -228,6 +228,7 @@ edb9302a           MACH_EDB9302A           EDB9302A                1127
+ edb9307a              MACH_EDB9307A           EDB9307A                1128
+ omap_3430sdp          MACH_OMAP_3430SDP       OMAP_3430SDP            1138
+ vstms                 MACH_VSTMS              VSTMS                   1140
++ox820                 MACH_OX820              OX820                   1152
+ micro9m                       MACH_MICRO9M            MICRO9M                 1169
+ bug                   MACH_BUG                BUG                     1179
+ at91sam9263ek         MACH_AT91SAM9263EK      AT91SAM9263EK           1202
+Index: linux-3.18-rc4/drivers/clk/Makefile
+===================================================================
+--- linux-3.18-rc4.orig/drivers/clk/Makefile
++++ linux-3.18-rc4/drivers/clk/Makefile
+@@ -29,6 +29,7 @@ obj-$(CONFIG_COMMON_CLK_MAX77802)    += clk
+ obj-$(CONFIG_ARCH_MOXART)             += clk-moxart.o
+ obj-$(CONFIG_ARCH_NOMADIK)            += clk-nomadik.o
+ obj-$(CONFIG_ARCH_NSPIRE)             += clk-nspire.o
++obj-$(CONFIG_ARCH_OXNAS)              += clk-oxnas.o
+ obj-$(CONFIG_COMMON_CLK_PALMAS)               += clk-palmas.o
+ obj-$(CONFIG_CLK_PPC_CORENET)         += clk-ppc-corenet.o
+ obj-$(CONFIG_COMMON_CLK_RK808)                += clk-rk808.o
diff --git a/target/linux/oxnas/patches-3.18/310-oxnas-clocksource.patch b/target/linux/oxnas/patches-3.18/310-oxnas-clocksource.patch
new file mode 100644 (file)
index 0000000..0959e53
--- /dev/null
@@ -0,0 +1,29 @@
+Index: linux-3.18-rc4/drivers/clocksource/Kconfig
+===================================================================
+--- linux-3.18-rc4.orig/drivers/clocksource/Kconfig
++++ linux-3.18-rc4/drivers/clocksource/Kconfig
+@@ -156,6 +156,12 @@ config VF_PIT_TIMER
+       help
+         Support for Period Interrupt Timer on Freescale Vybrid Family SoCs.
++config CLKSRC_RPS_TIMER
++      def_bool y if ARCH_OXNAS
++      select CLKSRC_MMIO
++      help
++        This option enables support for the oxnas rps timers.
++
+ config SYS_SUPPORTS_SH_CMT
+         bool
+Index: linux-3.18-rc4/drivers/clocksource/Makefile
+===================================================================
+--- linux-3.18-rc4.orig/drivers/clocksource/Makefile
++++ linux-3.18-rc4/drivers/clocksource/Makefile
+@@ -36,6 +36,7 @@ obj-$(CONFIG_CLKSRC_EFM32)   += time-efm32
+ obj-$(CONFIG_CLKSRC_EXYNOS_MCT)       += exynos_mct.o
+ obj-$(CONFIG_CLKSRC_SAMSUNG_PWM)      += samsung_pwm_timer.o
+ obj-$(CONFIG_FSL_FTM_TIMER)   += fsl_ftm_timer.o
++obj-$(CONFIG_CLKSRC_RPS_TIMER)        += oxnas_rps_timer.o
+ obj-$(CONFIG_VF_PIT_TIMER)    += vf_pit_timer.o
+ obj-$(CONFIG_CLKSRC_QCOM)     += qcom-timer.o
+ obj-$(CONFIG_MTK_TIMER)               += mtk_timer.o
diff --git a/target/linux/oxnas/patches-3.18/320-oxnas-irqchip.patch b/target/linux/oxnas/patches-3.18/320-oxnas-irqchip.patch
new file mode 100644 (file)
index 0000000..e6262da
--- /dev/null
@@ -0,0 +1,40 @@
+Index: linux-3.18-rc4/drivers/irqchip/Kconfig
+===================================================================
+--- linux-3.18-rc4.orig/drivers/irqchip/Kconfig
++++ linux-3.18-rc4/drivers/irqchip/Kconfig
+@@ -15,6 +15,11 @@ config ARM_GIC_V3
+       select IRQ_DOMAIN
+       select MULTI_IRQ_HANDLER
++config PLXTECH_RPS
++      def_bool y if ARHC_OXNAS
++      depends on ARCH_OXNAS
++      select IRQ_DOMAIN
++
+ config ARM_NVIC
+       bool
+       select IRQ_DOMAIN
+Index: linux-3.18-rc4/drivers/irqchip/Makefile
+===================================================================
+--- linux-3.18-rc4.orig/drivers/irqchip/Makefile
++++ linux-3.18-rc4/drivers/irqchip/Makefile
+@@ -28,6 +28,7 @@ obj-$(CONFIG_IMGPDC_IRQ)             += irq-imgpdc.
+ obj-$(CONFIG_SIRF_IRQ)                        += irq-sirfsoc.o
+ obj-$(CONFIG_RENESAS_INTC_IRQPIN)     += irq-renesas-intc-irqpin.o
+ obj-$(CONFIG_RENESAS_IRQC)            += irq-renesas-irqc.o
++obj-$(CONFIG_PLXTECH_RPS)             += irq-rps.o
+ obj-$(CONFIG_VERSATILE_FPGA_IRQ)      += irq-versatile-fpga.o
+ obj-$(CONFIG_ARCH_NSPIRE)             += irq-zevio.o
+ obj-$(CONFIG_ARCH_VT8500)             += irq-vt8500.o
+Index: linux-3.18-rc4/drivers/irqchip/irq-gic.c
+===================================================================
+--- linux-3.18-rc4.orig/drivers/irqchip/irq-gic.c
++++ linux-3.18-rc4/drivers/irqchip/irq-gic.c
+@@ -1044,6 +1044,7 @@ IRQCHIP_DECLARE(gic_400, "arm,gic-400",
+ IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
+ IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
+ IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
++IRQCHIP_DECLARE(arm11_mpcore_gic, "arm,arm11mp-gic", gic_of_init);
+ IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
+ IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
diff --git a/target/linux/oxnas/patches-3.18/330-oxnas-pinctrl.patch b/target/linux/oxnas/patches-3.18/330-oxnas-pinctrl.patch
new file mode 100644 (file)
index 0000000..3ecc6eb
--- /dev/null
@@ -0,0 +1,32 @@
+Index: linux-3.18-rc4/drivers/pinctrl/Kconfig
+===================================================================
+--- linux-3.18-rc4.orig/drivers/pinctrl/Kconfig
++++ linux-3.18-rc4/drivers/pinctrl/Kconfig
+@@ -67,6 +67,15 @@ config PINCTRL_AT91
+       help
+         Say Y here to enable the at91 pinctrl driver
++config PINCTRL_OXNAS
++      bool "OXNAS pinctrl driver"
++      depends on OF
++      depends on ARCH_OXNAS
++      select PINMUX
++      select PINCONF
++      help
++        Say Y here to enable the oxnas pinctrl driver
++
+ config PINCTRL_BAYTRAIL
+       bool "Intel Baytrail GPIO pin control"
+       depends on GPIOLIB && ACPI && X86
+Index: linux-3.18-rc4/drivers/pinctrl/Makefile
+===================================================================
+--- linux-3.18-rc4.orig/drivers/pinctrl/Makefile
++++ linux-3.18-rc4/drivers/pinctrl/Makefile
+@@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_BCM2835)        += pinctrl
+ obj-$(CONFIG_PINCTRL_BAYTRAIL)        += pinctrl-baytrail.o
+ obj-$(CONFIG_PINCTRL_BCM281XX)        += pinctrl-bcm281xx.o
+ obj-$(CONFIG_PINCTRL_FALCON)  += pinctrl-falcon.o
++obj-$(CONFIG_PINCTRL_OXNAS)   += pinctrl-oxnas.o
+ obj-$(CONFIG_PINCTRL_PALMAS)  += pinctrl-palmas.o
+ obj-$(CONFIG_PINCTRL_ROCKCHIP)        += pinctrl-rockchip.o
+ obj-$(CONFIG_PINCTRL_SINGLE)  += pinctrl-single.o
diff --git a/target/linux/oxnas/patches-3.18/340-oxnas-pcie.patch b/target/linux/oxnas/patches-3.18/340-oxnas-pcie.patch
new file mode 100644 (file)
index 0000000..6549db0
--- /dev/null
@@ -0,0 +1,26 @@
+Index: linux-3.18-rc4/drivers/pci/host/Kconfig
+===================================================================
+--- linux-3.18-rc4.orig/drivers/pci/host/Kconfig
++++ linux-3.18-rc4/drivers/pci/host/Kconfig
+@@ -91,4 +91,9 @@ config PCI_XGENE
+         There are 5 internal PCIe ports available. Each port is GEN3 capable
+         and have varied lanes from x1 to x8.
++config PCI_OXNAS
++      bool "PLX Oxnas PCIe controller"
++      depends on ARCH_OXNAS
++      select PCIEPORTBUS
++
+ endmenu
+Index: linux-3.18-rc4/drivers/pci/host/Makefile
+===================================================================
+--- linux-3.18-rc4.orig/drivers/pci/host/Makefile
++++ linux-3.18-rc4/drivers/pci/host/Makefile
+@@ -3,6 +3,7 @@ obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
+ obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
+ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
+ obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
++obj-$(CONFIG_PCI_OXNAS) += pcie-oxnas.o
+ obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
+ obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
+ obj-$(CONFIG_PCI_RCAR_GEN2_PCIE) += pcie-rcar.o
diff --git a/target/linux/oxnas/patches-3.18/350-oxnas-reset.patch b/target/linux/oxnas/patches-3.18/350-oxnas-reset.patch
new file mode 100644 (file)
index 0000000..5540920
--- /dev/null
@@ -0,0 +1,24 @@
+Index: linux-3.18-rc4/drivers/reset/Kconfig
+===================================================================
+--- linux-3.18-rc4.orig/drivers/reset/Kconfig
++++ linux-3.18-rc4/drivers/reset/Kconfig
+@@ -12,4 +12,9 @@ menuconfig RESET_CONTROLLER
+         If unsure, say no.
++config RESET_CONTROLLER_OXNAS
++      bool
++      select RESET_CONTROLLER
++
+ source "drivers/reset/sti/Kconfig"
++
+Index: linux-3.18-rc4/drivers/reset/Makefile
+===================================================================
+--- linux-3.18-rc4.orig/drivers/reset/Makefile
++++ linux-3.18-rc4/drivers/reset/Makefile
+@@ -1,4 +1,5 @@
+ obj-$(CONFIG_RESET_CONTROLLER) += core.o
++obj-$(CONFIG_RESET_CONTROLLER_OXNAS) += reset-ox820.o
+ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
+ obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
+ obj-$(CONFIG_ARCH_STI) += sti/
diff --git a/target/linux/oxnas/patches-3.18/400-oxnas-nand.patch b/target/linux/oxnas/patches-3.18/400-oxnas-nand.patch
new file mode 100644 (file)
index 0000000..90827e5
--- /dev/null
@@ -0,0 +1,28 @@
+Index: linux-3.18-rc4/drivers/mtd/nand/Kconfig
+===================================================================
+--- linux-3.18-rc4.orig/drivers/mtd/nand/Kconfig
++++ linux-3.18-rc4/drivers/mtd/nand/Kconfig
+@@ -516,4 +516,12 @@ config MTD_NAND_XWAY
+         Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached
+         to the External Bus Unit (EBU).
++config MTD_NAND_OXNAS
++      tristate "Support for NAND on Plxtech NAS782X SoC"
++      depends on ARCH_OXNAS
++      select MTD_NAND_PLATFORM
++      help
++        Enables support for NAND Flash chips on Plxtech NAS782X SoCs. NAND is attached
++        to the STATIC Unit.
++
+ endif # MTD_NAND
+Index: linux-3.18-rc4/drivers/mtd/nand/Makefile
+===================================================================
+--- linux-3.18-rc4.orig/drivers/mtd/nand/Makefile
++++ linux-3.18-rc4/drivers/mtd/nand/Makefile
+@@ -50,5 +50,6 @@ obj-$(CONFIG_MTD_NAND_JZ4740)                += jz4740
+ obj-$(CONFIG_MTD_NAND_GPMI_NAND)      += gpmi-nand/
+ obj-$(CONFIG_MTD_NAND_XWAY)           += xway_nand.o
+ obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH)  += bcm47xxnflash/
++obj-$(CONFIG_MTD_NAND_OXNAS)          += oxnas_nand.o
+ nand-objs := nand_base.o nand_bbt.o nand_timings.o
diff --git a/target/linux/oxnas/patches-3.18/500-oxnas-sata.patch b/target/linux/oxnas/patches-3.18/500-oxnas-sata.patch
new file mode 100644 (file)
index 0000000..94b792b
--- /dev/null
@@ -0,0 +1,30 @@
+Index: linux-3.18-rc4/drivers/ata/Kconfig
+===================================================================
+--- linux-3.18-rc4.orig/drivers/ata/Kconfig
++++ linux-3.18-rc4/drivers/ata/Kconfig
+@@ -385,6 +385,13 @@ config SATA_VITESSE
+         If unsure, say N.
++config SATA_OXNAS
++      tristate "PLXTECH NAS782X SATA support"
++      help
++        This option enables support for Nas782x Serial ATA controller.
++
++        If unsure, say N.
++
+ comment "PATA SFF controllers with BMDMA"
+ config PATA_ALI
+Index: linux-3.18-rc4/drivers/ata/Makefile
+===================================================================
+--- linux-3.18-rc4.orig/drivers/ata/Makefile
++++ linux-3.18-rc4/drivers/ata/Makefile
+@@ -37,6 +37,7 @@ obj-$(CONFIG_SATA_SVW)               += sata_svw.o
+ obj-$(CONFIG_SATA_ULI)                += sata_uli.o
+ obj-$(CONFIG_SATA_VIA)                += sata_via.o
+ obj-$(CONFIG_SATA_VITESSE)    += sata_vsc.o
++obj-$(CONFIG_SATA_OXNAS)      += sata_oxnas.o
+ # SFF PATA w/ BMDMA
+ obj-$(CONFIG_PATA_ALI)                += pata_ali.o
diff --git a/target/linux/oxnas/patches-3.18/800-oxnas-ehci.patch b/target/linux/oxnas/patches-3.18/800-oxnas-ehci.patch
new file mode 100644 (file)
index 0000000..f2221dd
--- /dev/null
@@ -0,0 +1,30 @@
+Index: linux-3.18-rc4/drivers/usb/host/Kconfig
+===================================================================
+--- linux-3.18-rc4.orig/drivers/usb/host/Kconfig
++++ linux-3.18-rc4/drivers/usb/host/Kconfig
+@@ -302,6 +302,13 @@ config USB_OCTEON_EHCI
+         USB 2.0 device support.  All CN6XXX based chips with USB are
+         supported.
++config USB_EHCI_OXNAS
++      tristate "OXNAS EHCI Module"
++      depends on USB_EHCI_HCD && ARCH_OXNAS
++      select USB_EHCI_ROOT_HUB_TT
++      ---help---
++        Enable support for the OX820 SOC's on-chip EHCI controller.
++
+ endif # USB_EHCI_HCD
+ config USB_OXU210HP_HCD
+Index: linux-3.18-rc4/drivers/usb/host/Makefile
+===================================================================
+--- linux-3.18-rc4.orig/drivers/usb/host/Makefile
++++ linux-3.18-rc4/drivers/usb/host/Makefile
+@@ -44,6 +44,7 @@ obj-$(CONFIG_USB_EHCI_HCD_AT91) += ehci-
+ obj-$(CONFIG_USB_EHCI_MSM)    += ehci-msm.o
+ obj-$(CONFIG_USB_EHCI_TEGRA)  += ehci-tegra.o
+ obj-$(CONFIG_USB_W90X900_EHCI)        += ehci-w90x900.o
++obj-$(CONFIG_USB_EHCI_OXNAS)  += ehci-oxnas.o
+ obj-$(CONFIG_USB_OXU210HP_HCD)        += oxu210hp-hcd.o
+ obj-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o
diff --git a/target/linux/oxnas/patches-3.18/900-more-boards.patch b/target/linux/oxnas/patches-3.18/900-more-boards.patch
new file mode 100644 (file)
index 0000000..b31967a
--- /dev/null
@@ -0,0 +1,16 @@
+Index: linux-3.18-rc4/arch/arm/boot/dts/Makefile
+===================================================================
+--- linux-3.18-rc4.orig/arch/arm/boot/dts/Makefile
++++ linux-3.18-rc4/arch/arm/boot/dts/Makefile
+@@ -352,7 +352,10 @@ dtb-$(CONFIG_ARCH_ORION5X) += orion5x-la
+       orion5x-lacie-ethernet-disk-mini-v2.dtb \
+       orion5x-maxtor-shared-storage-2.dtb \
+       orion5x-rd88f5182-nas.dtb
+-dtb-$(CONFIG_ARCH_OXNAS) += ox820-pogoplug-pro.dtb
++dtb-$(CONFIG_ARCH_OXNAS) += ox820-pogoplug-pro.dtb \
++      ox820-pogoplug-v3.dtb \
++      ox820-stg212.dtb \
++      ox820-kd20.dtb
+ dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
+ dtb-$(CONFIG_ARCH_QCOM) += \
+       qcom-apq8064-cm-qs600.dtb \
diff --git a/target/linux/oxnas/profiles/100-Generic.mk b/target/linux/oxnas/profiles/100-Generic.mk
new file mode 100644 (file)
index 0000000..734b123
--- /dev/null
@@ -0,0 +1,53 @@
+#
+# Copyright (C) 2014 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+define Profile/POGOPLUG_PRO
+  NAME:=PogoPlug Pro
+  PACKAGES:= \
+       uboot-envtools kmod-usb2-oxnas
+endef
+
+define Profile/POGOPLUG_PRO/Description
+ Profile with built-in ox820 PogoPlug Pro device-tree
+ (board with miniPCIe slot)
+endef
+
+define Profile/POGOPLUG_V3
+  NAME:=PogoPlug V3
+  PACKAGES:= \
+       uboot-envtools kmod-usb2-oxnas
+endef
+
+define Profile/POGOPLUG_V3/Description
+ Profile with built-in ox820 PogoPlug V3 device-tree
+ (board without miniPCIe slot)
+endef
+
+define Profile/STG212
+  NAME:=MitraStar STG-212
+  PACKAGES:= \
+       uboot-envtools kmod-usb2-oxnas
+endef
+
+define Profile/STG212/Description
+ Profile with built-in ox820 STG-212 device-tree
+endef
+
+define Profile/KD20
+  NAME:=Shuttle KD20
+  PACKAGES:= \
+       uboot-envtools kmod-usb2-oxnas kmod-usb3 kmod-rtc-pcf8563
+endef
+
+define Profile/KD20/Description
+ Profile with built-in ox820 KD20 device-tree
+endef
+
+$(eval $(call Profile,POGOPLUG_PRO))
+$(eval $(call Profile,POGOPLUG_V3))
+$(eval $(call Profile,STG212))
+$(eval $(call Profile,KD20))