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ath79: add support for TP-LINK Archer C7 v4
[openwrt/staging/jogo.git] / target / linux / brcm2708 / patches-4.9 / 950-0173-drm-vc4-Add-DSI-driver.patch
1 From 38ea3f3665eaa9deedc3588196fe9ba9bb4032ec Mon Sep 17 00:00:00 2001
2 From: Eric Anholt <eric@anholt.net>
3 Date: Wed, 10 Feb 2016 11:42:32 -0800
4 Subject: [PATCH] drm/vc4: Add DSI driver
5
6 The DSI0 and DSI1 blocks on the 2835 are related hardware blocks.
7 Some registers move around, and the featureset is slightly different,
8 as DSI1 (the 4-lane DSI) is a later version of the hardware block.
9 This driver doesn't yet enable DSI0, since we don't have any hardware
10 to test against, but it does put a lot of the register definitions and
11 code in place.
12
13 Signed-off-by: Eric Anholt <eric@anholt.net>
14 ---
15 drivers/gpu/drm/vc4/Kconfig | 2 +
16 drivers/gpu/drm/vc4/Makefile | 1 +
17 drivers/gpu/drm/vc4/vc4_debugfs.c | 1 +
18 drivers/gpu/drm/vc4/vc4_drv.c | 1 +
19 drivers/gpu/drm/vc4/vc4_drv.h | 5 +
20 drivers/gpu/drm/vc4/vc4_dsi.c | 1725 +++++++++++++++++++++++++++++++++++++
21 6 files changed, 1735 insertions(+)
22 create mode 100644 drivers/gpu/drm/vc4/vc4_dsi.c
23
24 --- a/drivers/gpu/drm/vc4/Kconfig
25 +++ b/drivers/gpu/drm/vc4/Kconfig
26 @@ -2,10 +2,12 @@ config DRM_VC4
27 tristate "Broadcom VC4 Graphics"
28 depends on ARCH_BCM2835 || COMPILE_TEST
29 depends on DRM
30 + depends on COMMON_CLK
31 select DRM_KMS_HELPER
32 select DRM_KMS_CMA_HELPER
33 select DRM_GEM_CMA_HELPER
34 select DRM_PANEL
35 + select DRM_MIPI_DSI
36 help
37 Choose this option if you have a system that has a Broadcom
38 VC4 GPU, such as the Raspberry Pi or other BCM2708/BCM2835.
39 --- a/drivers/gpu/drm/vc4/Makefile
40 +++ b/drivers/gpu/drm/vc4/Makefile
41 @@ -8,6 +8,7 @@ vc4-y := \
42 vc4_crtc.o \
43 vc4_drv.o \
44 vc4_dpi.o \
45 + vc4_dsi.o \
46 vc4_firmware_kms.o \
47 vc4_kms.o \
48 vc4_gem.o \
49 --- a/drivers/gpu/drm/vc4/vc4_debugfs.c
50 +++ b/drivers/gpu/drm/vc4/vc4_debugfs.c
51 @@ -18,6 +18,7 @@
52 static const struct drm_info_list vc4_debugfs_list[] = {
53 {"bo_stats", vc4_bo_stats_debugfs, 0},
54 {"dpi_regs", vc4_dpi_debugfs_regs, 0},
55 + {"dsi1_regs", vc4_dsi_debugfs_regs, 0, (void *)(uintptr_t)1},
56 {"hdmi_regs", vc4_hdmi_debugfs_regs, 0},
57 {"vec_regs", vc4_vec_debugfs_regs, 0},
58 {"hvs_regs", vc4_hvs_debugfs_regs, 0},
59 --- a/drivers/gpu/drm/vc4/vc4_drv.c
60 +++ b/drivers/gpu/drm/vc4/vc4_drv.c
61 @@ -296,6 +296,7 @@ static struct platform_driver *const com
62 &vc4_hdmi_driver,
63 &vc4_vec_driver,
64 &vc4_dpi_driver,
65 + &vc4_dsi_driver,
66 &vc4_hvs_driver,
67 &vc4_crtc_driver,
68 &vc4_firmware_kms_driver,
69 --- a/drivers/gpu/drm/vc4/vc4_drv.h
70 +++ b/drivers/gpu/drm/vc4/vc4_drv.h
71 @@ -20,6 +20,7 @@ struct vc4_dev {
72 struct vc4_crtc *crtc[3];
73 struct vc4_v3d *v3d;
74 struct vc4_dpi *dpi;
75 + struct vc4_dsi *dsi1;
76 struct vc4_vec *vec;
77
78 struct drm_fbdev_cma *fbdev;
79 @@ -468,6 +469,10 @@ void __iomem *vc4_ioremap_regs(struct pl
80 extern struct platform_driver vc4_dpi_driver;
81 int vc4_dpi_debugfs_regs(struct seq_file *m, void *unused);
82
83 +/* vc4_dsi.c */
84 +extern struct platform_driver vc4_dsi_driver;
85 +int vc4_dsi_debugfs_regs(struct seq_file *m, void *unused);
86 +
87 /* vc4_firmware_kms.c */
88 extern struct platform_driver vc4_firmware_kms_driver;
89 void vc4_fkms_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file);
90 --- /dev/null
91 +++ b/drivers/gpu/drm/vc4/vc4_dsi.c
92 @@ -0,0 +1,1725 @@
93 +/*
94 + * Copyright (C) 2016 Broadcom
95 + *
96 + * This program is free software; you can redistribute it and/or modify it
97 + * under the terms of the GNU General Public License version 2 as published by
98 + * the Free Software Foundation.
99 + *
100 + * This program is distributed in the hope that it will be useful, but WITHOUT
101 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
102 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
103 + * more details.
104 + *
105 + * You should have received a copy of the GNU General Public License along with
106 + * this program. If not, see <http://www.gnu.org/licenses/>.
107 + */
108 +
109 +/**
110 + * DOC: VC4 DSI0/DSI1 module
111 + *
112 + * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
113 + * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
114 + * controller.
115 + *
116 + * Most Raspberry Pi boards expose DSI1 as their "DISPLAY" connector,
117 + * while the compute module brings both DSI0 and DSI1 out.
118 + *
119 + * This driver has been tested for DSI1 video-mode display only
120 + * currently, with most of the information necessary for DSI0
121 + * hopefully present.
122 + */
123 +
124 +#include "drm_atomic_helper.h"
125 +#include "drm_crtc_helper.h"
126 +#include "drm_edid.h"
127 +#include "drm_mipi_dsi.h"
128 +#include "drm_panel.h"
129 +#include "linux/clk.h"
130 +#include "linux/clk-provider.h"
131 +#include "linux/completion.h"
132 +#include "linux/component.h"
133 +#include "linux/dmaengine.h"
134 +#include "linux/i2c.h"
135 +#include "linux/of_address.h"
136 +#include "linux/of_platform.h"
137 +#include "linux/pm_runtime.h"
138 +#include "vc4_drv.h"
139 +#include "vc4_regs.h"
140 +
141 +#define DSI_CMD_FIFO_DEPTH 16
142 +#define DSI_PIX_FIFO_DEPTH 256
143 +#define DSI_PIX_FIFO_WIDTH 4
144 +
145 +#define DSI0_CTRL 0x00
146 +
147 +/* Command packet control. */
148 +#define DSI0_TXPKT1C 0x04 /* AKA PKTC */
149 +#define DSI1_TXPKT1C 0x04
150 +# define DSI_TXPKT1C_TRIG_CMD_MASK VC4_MASK(31, 24)
151 +# define DSI_TXPKT1C_TRIG_CMD_SHIFT 24
152 +# define DSI_TXPKT1C_CMD_REPEAT_MASK VC4_MASK(23, 10)
153 +# define DSI_TXPKT1C_CMD_REPEAT_SHIFT 10
154 +
155 +# define DSI_TXPKT1C_DISPLAY_NO_MASK VC4_MASK(9, 8)
156 +# define DSI_TXPKT1C_DISPLAY_NO_SHIFT 8
157 +/* Short, trigger, BTA, or a long packet that fits all in CMDFIFO. */
158 +# define DSI_TXPKT1C_DISPLAY_NO_SHORT 0
159 +/* Primary display where cmdfifo provides part of the payload and
160 + * pixelvalve the rest.
161 + */
162 +# define DSI_TXPKT1C_DISPLAY_NO_PRIMARY 1
163 +/* Secondary display where cmdfifo provides part of the payload and
164 + * pixfifo the rest.
165 + */
166 +# define DSI_TXPKT1C_DISPLAY_NO_SECONDARY 2
167 +
168 +# define DSI_TXPKT1C_CMD_TX_TIME_MASK VC4_MASK(7, 6)
169 +# define DSI_TXPKT1C_CMD_TX_TIME_SHIFT 6
170 +
171 +# define DSI_TXPKT1C_CMD_CTRL_MASK VC4_MASK(5, 4)
172 +# define DSI_TXPKT1C_CMD_CTRL_SHIFT 4
173 +/* Command only. Uses TXPKT1H and DISPLAY_NO */
174 +# define DSI_TXPKT1C_CMD_CTRL_TX 0
175 +/* Command with BTA for either ack or read data. */
176 +# define DSI_TXPKT1C_CMD_CTRL_RX 1
177 +/* Trigger according to TRIG_CMD */
178 +# define DSI_TXPKT1C_CMD_CTRL_TRIG 2
179 +/* BTA alone for getting error status after a command, or a TE trigger
180 + * without a previous command.
181 + */
182 +# define DSI_TXPKT1C_CMD_CTRL_BTA 3
183 +
184 +# define DSI_TXPKT1C_CMD_MODE_LP BIT(3)
185 +# define DSI_TXPKT1C_CMD_TYPE_LONG BIT(2)
186 +# define DSI_TXPKT1C_CMD_TE_EN BIT(1)
187 +# define DSI_TXPKT1C_CMD_EN BIT(0)
188 +
189 +/* Command packet header. */
190 +#define DSI0_TXPKT1H 0x08 /* AKA PKTH */
191 +#define DSI1_TXPKT1H 0x08
192 +# define DSI_TXPKT1H_BC_CMDFIFO_MASK VC4_MASK(31, 24)
193 +# define DSI_TXPKT1H_BC_CMDFIFO_SHIFT 24
194 +# define DSI_TXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
195 +# define DSI_TXPKT1H_BC_PARAM_SHIFT 8
196 +# define DSI_TXPKT1H_BC_DT_MASK VC4_MASK(7, 0)
197 +# define DSI_TXPKT1H_BC_DT_SHIFT 0
198 +
199 +#define DSI0_RXPKT1H 0x0c /* AKA RX1_PKTH */
200 +#define DSI1_RXPKT1H 0x14
201 +# define DSI_RXPKT1H_CRC_ERR BIT(31)
202 +# define DSI_RXPKT1H_DET_ERR BIT(30)
203 +# define DSI_RXPKT1H_ECC_ERR BIT(29)
204 +# define DSI_RXPKT1H_COR_ERR BIT(28)
205 +# define DSI_RXPKT1H_INCOMP_PKT BIT(25)
206 +# define DSI_RXPKT1H_PKT_TYPE_LONG BIT(24)
207 +/* Byte count if DSI_RXPKT1H_PKT_TYPE_LONG */
208 +# define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
209 +# define DSI_RXPKT1H_BC_PARAM_SHIFT 8
210 +/* Short return bytes if !DSI_RXPKT1H_PKT_TYPE_LONG */
211 +# define DSI_RXPKT1H_SHORT_1_MASK VC4_MASK(23, 16)
212 +# define DSI_RXPKT1H_SHORT_1_SHIFT 16
213 +# define DSI_RXPKT1H_SHORT_0_MASK VC4_MASK(15, 8)
214 +# define DSI_RXPKT1H_SHORT_0_SHIFT 8
215 +# define DSI_RXPKT1H_DT_LP_CMD_MASK VC4_MASK(7, 0)
216 +# define DSI_RXPKT1H_DT_LP_CMD_SHIFT 0
217 +
218 +#define DSI0_RXPKT2H 0x10 /* AKA RX2_PKTH */
219 +#define DSI1_RXPKT2H 0x18
220 +# define DSI_RXPKT1H_DET_ERR BIT(30)
221 +# define DSI_RXPKT1H_ECC_ERR BIT(29)
222 +# define DSI_RXPKT1H_COR_ERR BIT(28)
223 +# define DSI_RXPKT1H_INCOMP_PKT BIT(25)
224 +# define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
225 +# define DSI_RXPKT1H_BC_PARAM_SHIFT 8
226 +# define DSI_RXPKT1H_DT_MASK VC4_MASK(7, 0)
227 +# define DSI_RXPKT1H_DT_SHIFT 0
228 +
229 +#define DSI0_TXPKT_CMD_FIFO 0x14 /* AKA CMD_DATAF */
230 +#define DSI1_TXPKT_CMD_FIFO 0x1c
231 +
232 +#define DSI0_DISP0_CTRL 0x18
233 +# define DSI_DISP0_PIX_CLK_DIV_MASK VC4_MASK(21, 13)
234 +# define DSI_DISP0_PIX_CLK_DIV_SHIFT 13
235 +# define DSI_DISP0_LP_STOP_CTRL_MASK VC4_MASK(12, 11)
236 +# define DSI_DISP0_LP_STOP_CTRL_SHIFT 11
237 +# define DSI_DISP0_LP_STOP_DISABLE 0
238 +# define DSI_DISP0_LP_STOP_PERLINE 1
239 +# define DSI_DISP0_LP_STOP_PERFRAME 2
240 +
241 +/* Transmit RGB pixels and null packets only during HACTIVE, instead
242 + * of going to LP-STOP.
243 + */
244 +# define DSI_DISP_HACTIVE_NULL BIT(10)
245 +/* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */
246 +# define DSI_DISP_VBLP_CTRL BIT(9)
247 +/* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */
248 +# define DSI_DISP_HFP_CTRL BIT(8)
249 +/* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */
250 +# define DSI_DISP_HBP_CTRL BIT(7)
251 +# define DSI_DISP0_CHANNEL_MASK VC4_MASK(6, 5)
252 +# define DSI_DISP0_CHANNEL_SHIFT 5
253 +/* Enables end events for HSYNC/VSYNC, not just start events. */
254 +# define DSI_DISP0_ST_END BIT(4)
255 +# define DSI_DISP0_PFORMAT_MASK VC4_MASK(3, 2)
256 +# define DSI_DISP0_PFORMAT_SHIFT 2
257 +# define DSI_PFORMAT_RGB565 0
258 +# define DSI_PFORMAT_RGB666_PACKED 1
259 +# define DSI_PFORMAT_RGB666 2
260 +# define DSI_PFORMAT_RGB888 3
261 +/* Default is VIDEO mode. */
262 +# define DSI_DISP0_COMMAND_MODE BIT(1)
263 +# define DSI_DISP0_ENABLE BIT(0)
264 +
265 +#define DSI0_DISP1_CTRL 0x1c
266 +#define DSI1_DISP1_CTRL 0x2c
267 +/* Format of the data written to TXPKT_PIX_FIFO. */
268 +# define DSI_DISP1_PFORMAT_MASK VC4_MASK(2, 1)
269 +# define DSI_DISP1_PFORMAT_SHIFT 1
270 +# define DSI_DISP1_PFORMAT_16BIT 0
271 +# define DSI_DISP1_PFORMAT_24BIT 1
272 +# define DSI_DISP1_PFORMAT_32BIT_LE 2
273 +# define DSI_DISP1_PFORMAT_32BIT_BE 3
274 +
275 +/* DISP1 is always command mode. */
276 +# define DSI_DISP1_ENABLE BIT(0)
277 +
278 +#define DSI0_TXPKT_PIX_FIFO 0x20 /* AKA PIX_FIFO */
279 +
280 +#define DSI0_INT_STAT 0x24
281 +#define DSI0_INT_EN 0x28
282 +# define DSI1_INT_PHY_D3_ULPS BIT(30)
283 +# define DSI1_INT_PHY_D3_STOP BIT(29)
284 +# define DSI1_INT_PHY_D2_ULPS BIT(28)
285 +# define DSI1_INT_PHY_D2_STOP BIT(27)
286 +# define DSI1_INT_PHY_D1_ULPS BIT(26)
287 +# define DSI1_INT_PHY_D1_STOP BIT(25)
288 +# define DSI1_INT_PHY_D0_ULPS BIT(24)
289 +# define DSI1_INT_PHY_D0_STOP BIT(23)
290 +# define DSI1_INT_FIFO_ERR BIT(22)
291 +# define DSI1_INT_PHY_DIR_RTF BIT(21)
292 +# define DSI1_INT_PHY_RXLPDT BIT(20)
293 +# define DSI1_INT_PHY_RXTRIG BIT(19)
294 +# define DSI1_INT_PHY_D0_LPDT BIT(18)
295 +# define DSI1_INT_PHY_DIR_FTR BIT(17)
296 +
297 +/* Signaled when the clock lane enters the given state. */
298 +# define DSI1_INT_PHY_CLOCK_ULPS BIT(16)
299 +# define DSI1_INT_PHY_CLOCK_HS BIT(15)
300 +# define DSI1_INT_PHY_CLOCK_STOP BIT(14)
301 +
302 +/* Signaled on timeouts */
303 +# define DSI1_INT_PR_TO BIT(13)
304 +# define DSI1_INT_TA_TO BIT(12)
305 +# define DSI1_INT_LPRX_TO BIT(11)
306 +# define DSI1_INT_HSTX_TO BIT(10)
307 +
308 +/* Contention on a line when trying to drive the line low */
309 +# define DSI1_INT_ERR_CONT_LP1 BIT(9)
310 +# define DSI1_INT_ERR_CONT_LP0 BIT(8)
311 +
312 +/* Control error: incorrect line state sequence on data lane 0. */
313 +# define DSI1_INT_ERR_CONTROL BIT(7)
314 +/* LPDT synchronization error (bits received not a multiple of 8. */
315 +
316 +# define DSI1_INT_ERR_SYNC_ESC BIT(6)
317 +/* Signaled after receiving an error packet from the display in
318 + * response to a read.
319 + */
320 +# define DSI1_INT_RXPKT2 BIT(5)
321 +/* Signaled after receiving a packet. The header and optional short
322 + * response will be in RXPKT1H, and a long response will be in the
323 + * RXPKT_FIFO.
324 + */
325 +# define DSI1_INT_RXPKT1 BIT(4)
326 +# define DSI1_INT_TXPKT2_DONE BIT(3)
327 +# define DSI1_INT_TXPKT2_END BIT(2)
328 +/* Signaled after all repeats of TXPKT1 are transferred. */
329 +# define DSI1_INT_TXPKT1_DONE BIT(1)
330 +/* Signaled after each TXPKT1 repeat is scheduled. */
331 +# define DSI1_INT_TXPKT1_END BIT(0)
332 +
333 +#define DSI1_INTERRUPTS_ALWAYS_ENABLED (DSI1_INT_ERR_SYNC_ESC | \
334 + DSI1_INT_ERR_CONTROL | \
335 + DSI1_INT_ERR_CONT_LP0 | \
336 + DSI1_INT_ERR_CONT_LP1 | \
337 + DSI1_INT_HSTX_TO | \
338 + DSI1_INT_LPRX_TO | \
339 + DSI1_INT_TA_TO | \
340 + DSI1_INT_PR_TO)
341 +
342 +#define DSI0_STAT 0x2c
343 +#define DSI0_HSTX_TO_CNT 0x30
344 +#define DSI0_LPRX_TO_CNT 0x34
345 +#define DSI0_TA_TO_CNT 0x38
346 +#define DSI0_PR_TO_CNT 0x3c
347 +#define DSI0_PHYC 0x40
348 +# define DSI1_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(25, 20)
349 +# define DSI1_PHYC_ESC_CLK_LPDT_SHIFT 20
350 +# define DSI1_PHYC_HS_CLK_CONTINUOUS BIT(18)
351 +# define DSI0_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(17, 12)
352 +# define DSI0_PHYC_ESC_CLK_LPDT_SHIFT 12
353 +# define DSI1_PHYC_CLANE_ULPS BIT(17)
354 +# define DSI1_PHYC_CLANE_ENABLE BIT(16)
355 +# define DSI_PHYC_DLANE3_ULPS BIT(13)
356 +# define DSI_PHYC_DLANE3_ENABLE BIT(12)
357 +# define DSI0_PHYC_HS_CLK_CONTINUOUS BIT(10)
358 +# define DSI0_PHYC_CLANE_ULPS BIT(9)
359 +# define DSI_PHYC_DLANE2_ULPS BIT(9)
360 +# define DSI0_PHYC_CLANE_ENABLE BIT(8)
361 +# define DSI_PHYC_DLANE2_ENABLE BIT(8)
362 +# define DSI_PHYC_DLANE1_ULPS BIT(5)
363 +# define DSI_PHYC_DLANE1_ENABLE BIT(4)
364 +# define DSI_PHYC_DLANE0_FORCE_STOP BIT(2)
365 +# define DSI_PHYC_DLANE0_ULPS BIT(1)
366 +# define DSI_PHYC_DLANE0_ENABLE BIT(0)
367 +
368 +#define DSI0_HS_CLT0 0x44
369 +#define DSI0_HS_CLT1 0x48
370 +#define DSI0_HS_CLT2 0x4c
371 +#define DSI0_HS_DLT3 0x50
372 +#define DSI0_HS_DLT4 0x54
373 +#define DSI0_HS_DLT5 0x58
374 +#define DSI0_HS_DLT6 0x5c
375 +#define DSI0_HS_DLT7 0x60
376 +
377 +#define DSI0_PHY_AFEC0 0x64
378 +# define DSI0_PHY_AFEC0_DDR2CLK_EN BIT(26)
379 +# define DSI0_PHY_AFEC0_DDRCLK_EN BIT(25)
380 +# define DSI0_PHY_AFEC0_LATCH_ULPS BIT(24)
381 +# define DSI1_PHY_AFEC0_IDR_DLANE3_MASK VC4_MASK(31, 29)
382 +# define DSI1_PHY_AFEC0_IDR_DLANE3_SHIFT 29
383 +# define DSI1_PHY_AFEC0_IDR_DLANE2_MASK VC4_MASK(28, 26)
384 +# define DSI1_PHY_AFEC0_IDR_DLANE2_SHIFT 26
385 +# define DSI1_PHY_AFEC0_IDR_DLANE1_MASK VC4_MASK(27, 23)
386 +# define DSI1_PHY_AFEC0_IDR_DLANE1_SHIFT 23
387 +# define DSI1_PHY_AFEC0_IDR_DLANE0_MASK VC4_MASK(22, 20)
388 +# define DSI1_PHY_AFEC0_IDR_DLANE0_SHIFT 20
389 +# define DSI1_PHY_AFEC0_IDR_CLANE_MASK VC4_MASK(19, 17)
390 +# define DSI1_PHY_AFEC0_IDR_CLANE_SHIFT 17
391 +# define DSI0_PHY_AFEC0_ACTRL_DLANE1_MASK VC4_MASK(23, 20)
392 +# define DSI0_PHY_AFEC0_ACTRL_DLANE1_SHIFT 20
393 +# define DSI0_PHY_AFEC0_ACTRL_DLANE0_MASK VC4_MASK(19, 16)
394 +# define DSI0_PHY_AFEC0_ACTRL_DLANE0_SHIFT 16
395 +# define DSI0_PHY_AFEC0_ACTRL_CLANE_MASK VC4_MASK(15, 12)
396 +# define DSI0_PHY_AFEC0_ACTRL_CLANE_SHIFT 12
397 +# define DSI1_PHY_AFEC0_DDR2CLK_EN BIT(16)
398 +# define DSI1_PHY_AFEC0_DDRCLK_EN BIT(15)
399 +# define DSI1_PHY_AFEC0_LATCH_ULPS BIT(14)
400 +# define DSI1_PHY_AFEC0_RESET BIT(13)
401 +# define DSI1_PHY_AFEC0_PD BIT(12)
402 +# define DSI0_PHY_AFEC0_RESET BIT(11)
403 +# define DSI1_PHY_AFEC0_PD_BG BIT(11)
404 +# define DSI0_PHY_AFEC0_PD BIT(10)
405 +# define DSI1_PHY_AFEC0_PD_DLANE3 BIT(10)
406 +# define DSI0_PHY_AFEC0_PD_BG BIT(9)
407 +# define DSI1_PHY_AFEC0_PD_DLANE2 BIT(9)
408 +# define DSI0_PHY_AFEC0_PD_DLANE1 BIT(8)
409 +# define DSI1_PHY_AFEC0_PD_DLANE1 BIT(8)
410 +# define DSI_PHY_AFEC0_PTATADJ_MASK VC4_MASK(7, 4)
411 +# define DSI_PHY_AFEC0_PTATADJ_SHIFT 4
412 +# define DSI_PHY_AFEC0_CTATADJ_MASK VC4_MASK(3, 0)
413 +# define DSI_PHY_AFEC0_CTATADJ_SHIFT 0
414 +
415 +#define DSI0_PHY_AFEC1 0x68
416 +# define DSI0_PHY_AFEC1_IDR_DLANE1_MASK VC4_MASK(10, 8)
417 +# define DSI0_PHY_AFEC1_IDR_DLANE1_SHIFT 8
418 +# define DSI0_PHY_AFEC1_IDR_DLANE0_MASK VC4_MASK(6, 4)
419 +# define DSI0_PHY_AFEC1_IDR_DLANE0_SHIFT 4
420 +# define DSI0_PHY_AFEC1_IDR_CLANE_MASK VC4_MASK(2, 0)
421 +# define DSI0_PHY_AFEC1_IDR_CLANE_SHIFT 0
422 +
423 +#define DSI0_TST_SEL 0x6c
424 +#define DSI0_TST_MON 0x70
425 +#define DSI0_ID 0x74
426 +# define DSI_ID_VALUE 0x00647369
427 +
428 +#define DSI1_CTRL 0x00
429 +# define DSI_CTRL_HS_CLKC_MASK VC4_MASK(15, 14)
430 +# define DSI_CTRL_HS_CLKC_SHIFT 14
431 +# define DSI_CTRL_HS_CLKC_BYTE 0
432 +# define DSI_CTRL_HS_CLKC_DDR2 1
433 +# define DSI_CTRL_HS_CLKC_DDR 2
434 +
435 +# define DSI_CTRL_RX_LPDT_EOT_DISABLE BIT(13)
436 +# define DSI_CTRL_LPDT_EOT_DISABLE BIT(12)
437 +# define DSI_CTRL_HSDT_EOT_DISABLE BIT(11)
438 +# define DSI_CTRL_SOFT_RESET_CFG BIT(10)
439 +# define DSI_CTRL_CAL_BYTE BIT(9)
440 +# define DSI_CTRL_INV_BYTE BIT(8)
441 +# define DSI_CTRL_CLR_LDF BIT(7)
442 +# define DSI0_CTRL_CLR_PBCF BIT(6)
443 +# define DSI1_CTRL_CLR_RXF BIT(6)
444 +# define DSI0_CTRL_CLR_CPBCF BIT(5)
445 +# define DSI1_CTRL_CLR_PDF BIT(5)
446 +# define DSI0_CTRL_CLR_PDF BIT(4)
447 +# define DSI1_CTRL_CLR_CDF BIT(4)
448 +# define DSI0_CTRL_CLR_CDF BIT(3)
449 +# define DSI0_CTRL_CTRL2 BIT(2)
450 +# define DSI1_CTRL_DISABLE_DISP_CRCC BIT(2)
451 +# define DSI0_CTRL_CTRL1 BIT(1)
452 +# define DSI1_CTRL_DISABLE_DISP_ECCC BIT(1)
453 +# define DSI0_CTRL_CTRL0 BIT(0)
454 +# define DSI1_CTRL_EN BIT(0)
455 +# define DSI0_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \
456 + DSI0_CTRL_CLR_PBCF | \
457 + DSI0_CTRL_CLR_CPBCF | \
458 + DSI0_CTRL_CLR_PDF | \
459 + DSI0_CTRL_CLR_CDF)
460 +# define DSI1_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \
461 + DSI1_CTRL_CLR_RXF | \
462 + DSI1_CTRL_CLR_PDF | \
463 + DSI1_CTRL_CLR_CDF)
464 +
465 +#define DSI1_TXPKT2C 0x0c
466 +#define DSI1_TXPKT2H 0x10
467 +#define DSI1_TXPKT_PIX_FIFO 0x20
468 +#define DSI1_RXPKT_FIFO 0x24
469 +#define DSI1_DISP0_CTRL 0x28
470 +#define DSI1_INT_STAT 0x30
471 +#define DSI1_INT_EN 0x34
472 +/* State reporting bits. These mostly behave like INT_STAT, where
473 + * writing a 1 clears the bit.
474 + */
475 +#define DSI1_STAT 0x38
476 +# define DSI1_STAT_PHY_D3_ULPS BIT(31)
477 +# define DSI1_STAT_PHY_D3_STOP BIT(30)
478 +# define DSI1_STAT_PHY_D2_ULPS BIT(29)
479 +# define DSI1_STAT_PHY_D2_STOP BIT(28)
480 +# define DSI1_STAT_PHY_D1_ULPS BIT(27)
481 +# define DSI1_STAT_PHY_D1_STOP BIT(26)
482 +# define DSI1_STAT_PHY_D0_ULPS BIT(25)
483 +# define DSI1_STAT_PHY_D0_STOP BIT(24)
484 +# define DSI1_STAT_FIFO_ERR BIT(23)
485 +# define DSI1_STAT_PHY_RXLPDT BIT(22)
486 +# define DSI1_STAT_PHY_RXTRIG BIT(21)
487 +# define DSI1_STAT_PHY_D0_LPDT BIT(20)
488 +/* Set when in forward direction */
489 +# define DSI1_STAT_PHY_DIR BIT(19)
490 +# define DSI1_STAT_PHY_CLOCK_ULPS BIT(18)
491 +# define DSI1_STAT_PHY_CLOCK_HS BIT(17)
492 +# define DSI1_STAT_PHY_CLOCK_STOP BIT(16)
493 +# define DSI1_STAT_PR_TO BIT(15)
494 +# define DSI1_STAT_TA_TO BIT(14)
495 +# define DSI1_STAT_LPRX_TO BIT(13)
496 +# define DSI1_STAT_HSTX_TO BIT(12)
497 +# define DSI1_STAT_ERR_CONT_LP1 BIT(11)
498 +# define DSI1_STAT_ERR_CONT_LP0 BIT(10)
499 +# define DSI1_STAT_ERR_CONTROL BIT(9)
500 +# define DSI1_STAT_ERR_SYNC_ESC BIT(8)
501 +# define DSI1_STAT_RXPKT2 BIT(7)
502 +# define DSI1_STAT_RXPKT1 BIT(6)
503 +# define DSI1_STAT_TXPKT2_BUSY BIT(5)
504 +# define DSI1_STAT_TXPKT2_DONE BIT(4)
505 +# define DSI1_STAT_TXPKT2_END BIT(3)
506 +# define DSI1_STAT_TXPKT1_BUSY BIT(2)
507 +# define DSI1_STAT_TXPKT1_DONE BIT(1)
508 +# define DSI1_STAT_TXPKT1_END BIT(0)
509 +
510 +#define DSI1_HSTX_TO_CNT 0x3c
511 +#define DSI1_LPRX_TO_CNT 0x40
512 +#define DSI1_TA_TO_CNT 0x44
513 +#define DSI1_PR_TO_CNT 0x48
514 +#define DSI1_PHYC 0x4c
515 +
516 +#define DSI1_HS_CLT0 0x50
517 +# define DSI_HS_CLT0_CZERO_MASK VC4_MASK(26, 18)
518 +# define DSI_HS_CLT0_CZERO_SHIFT 18
519 +# define DSI_HS_CLT0_CPRE_MASK VC4_MASK(17, 9)
520 +# define DSI_HS_CLT0_CPRE_SHIFT 9
521 +# define DSI_HS_CLT0_CPREP_MASK VC4_MASK(8, 0)
522 +# define DSI_HS_CLT0_CPREP_SHIFT 0
523 +
524 +#define DSI1_HS_CLT1 0x54
525 +# define DSI_HS_CLT1_CTRAIL_MASK VC4_MASK(17, 9)
526 +# define DSI_HS_CLT1_CTRAIL_SHIFT 9
527 +# define DSI_HS_CLT1_CPOST_MASK VC4_MASK(8, 0)
528 +# define DSI_HS_CLT1_CPOST_SHIFT 0
529 +
530 +#define DSI1_HS_CLT2 0x58
531 +# define DSI_HS_CLT2_WUP_MASK VC4_MASK(23, 0)
532 +# define DSI_HS_CLT2_WUP_SHIFT 0
533 +
534 +#define DSI1_HS_DLT3 0x5c
535 +# define DSI_HS_DLT3_EXIT_MASK VC4_MASK(26, 18)
536 +# define DSI_HS_DLT3_EXIT_SHIFT 18
537 +# define DSI_HS_DLT3_ZERO_MASK VC4_MASK(17, 9)
538 +# define DSI_HS_DLT3_ZERO_SHIFT 9
539 +# define DSI_HS_DLT3_PRE_MASK VC4_MASK(8, 0)
540 +# define DSI_HS_DLT3_PRE_SHIFT 0
541 +
542 +#define DSI1_HS_DLT4 0x60
543 +# define DSI_HS_DLT4_ANLAT_MASK VC4_MASK(22, 18)
544 +# define DSI_HS_DLT4_ANLAT_SHIFT 18
545 +# define DSI_HS_DLT4_TRAIL_MASK VC4_MASK(17, 9)
546 +# define DSI_HS_DLT4_TRAIL_SHIFT 9
547 +# define DSI_HS_DLT4_LPX_MASK VC4_MASK(8, 0)
548 +# define DSI_HS_DLT4_LPX_SHIFT 0
549 +
550 +#define DSI1_HS_DLT5 0x64
551 +# define DSI_HS_DLT5_INIT_MASK VC4_MASK(23, 0)
552 +# define DSI_HS_DLT5_INIT_SHIFT 0
553 +
554 +#define DSI1_HS_DLT6 0x68
555 +# define DSI_HS_DLT6_TA_GET_MASK VC4_MASK(31, 24)
556 +# define DSI_HS_DLT6_TA_GET_SHIFT 24
557 +# define DSI_HS_DLT6_TA_SURE_MASK VC4_MASK(23, 16)
558 +# define DSI_HS_DLT6_TA_SURE_SHIFT 16
559 +# define DSI_HS_DLT6_TA_GO_MASK VC4_MASK(15, 8)
560 +# define DSI_HS_DLT6_TA_GO_SHIFT 8
561 +# define DSI_HS_DLT6_LP_LPX_MASK VC4_MASK(7, 0)
562 +# define DSI_HS_DLT6_LP_LPX_SHIFT 0
563 +
564 +#define DSI1_HS_DLT7 0x6c
565 +# define DSI_HS_DLT7_LP_WUP_MASK VC4_MASK(23, 0)
566 +# define DSI_HS_DLT7_LP_WUP_SHIFT 0
567 +
568 +#define DSI1_PHY_AFEC0 0x70
569 +
570 +#define DSI1_PHY_AFEC1 0x74
571 +# define DSI1_PHY_AFEC1_ACTRL_DLANE3_MASK VC4_MASK(19, 16)
572 +# define DSI1_PHY_AFEC1_ACTRL_DLANE3_SHIFT 16
573 +# define DSI1_PHY_AFEC1_ACTRL_DLANE2_MASK VC4_MASK(15, 12)
574 +# define DSI1_PHY_AFEC1_ACTRL_DLANE2_SHIFT 12
575 +# define DSI1_PHY_AFEC1_ACTRL_DLANE1_MASK VC4_MASK(11, 8)
576 +# define DSI1_PHY_AFEC1_ACTRL_DLANE1_SHIFT 8
577 +# define DSI1_PHY_AFEC1_ACTRL_DLANE0_MASK VC4_MASK(7, 4)
578 +# define DSI1_PHY_AFEC1_ACTRL_DLANE0_SHIFT 4
579 +# define DSI1_PHY_AFEC1_ACTRL_CLANE_MASK VC4_MASK(3, 0)
580 +# define DSI1_PHY_AFEC1_ACTRL_CLANE_SHIFT 0
581 +
582 +#define DSI1_TST_SEL 0x78
583 +#define DSI1_TST_MON 0x7c
584 +#define DSI1_PHY_TST1 0x80
585 +#define DSI1_PHY_TST2 0x84
586 +#define DSI1_PHY_FIFO_STAT 0x88
587 +/* Actually, all registers in the range that aren't otherwise claimed
588 + * will return the ID.
589 + */
590 +#define DSI1_ID 0x8c
591 +
592 +/* General DSI hardware state. */
593 +struct vc4_dsi {
594 + struct platform_device *pdev;
595 +
596 + struct mipi_dsi_host dsi_host;
597 + struct drm_encoder *encoder;
598 + struct drm_connector *connector;
599 + struct drm_panel *panel;
600 +
601 + void __iomem *regs;
602 +
603 + struct dma_chan *reg_dma_chan;
604 + dma_addr_t reg_dma_paddr;
605 + u32 *reg_dma_mem;
606 + dma_addr_t reg_paddr;
607 +
608 + /* Whether we're on bcm2835's DSI0 or DSI1. */
609 + int port;
610 +
611 + /* DSI channel for the panel we're connected to. */
612 + u32 channel;
613 + u32 lanes;
614 + enum mipi_dsi_pixel_format format;
615 + u32 mode_flags;
616 +
617 + /* Input clock from CPRMAN to the digital PHY, for the DSI
618 + * escape clock.
619 + */
620 + struct clk *escape_clock;
621 +
622 + /* Input clock to the analog PHY, used to generate the DSI bit
623 + * clock.
624 + */
625 + struct clk *pll_phy_clock;
626 +
627 + /* HS Clocks generated within the DSI analog PHY. */
628 + struct clk_fixed_factor phy_clocks[3];
629 +
630 + struct clk_onecell_data clk_onecell;
631 +
632 + /* Pixel clock output to the pixelvalve, generated from the HS
633 + * clock.
634 + */
635 + struct clk *pixel_clock;
636 +
637 + struct completion xfer_completion;
638 + int xfer_result;
639 +};
640 +
641 +#define host_to_dsi(host) container_of(host, struct vc4_dsi, dsi_host)
642 +
643 +static inline void
644 +dsi_dma_workaround_write(struct vc4_dsi *dsi, u32 offset, u32 val)
645 +{
646 + struct dma_chan *chan = dsi->reg_dma_chan;
647 + struct dma_async_tx_descriptor *tx;
648 + dma_cookie_t cookie;
649 + int ret;
650 +
651 + /* DSI0 should be able to write normally. */
652 + if (!chan) {
653 + writel(val, dsi->regs + offset);
654 + return;
655 + }
656 +
657 + *dsi->reg_dma_mem = val;
658 +
659 + tx = chan->device->device_prep_dma_memcpy(chan,
660 + dsi->reg_paddr + offset,
661 + dsi->reg_dma_paddr,
662 + 4, 0);
663 + if (!tx) {
664 + DRM_ERROR("Failed to set up DMA register write\n");
665 + return;
666 + }
667 +
668 + cookie = tx->tx_submit(tx);
669 + ret = dma_submit_error(cookie);
670 + if (ret) {
671 + DRM_ERROR("Failed to submit DMA: %d\n", ret);
672 + return;
673 + }
674 + ret = dma_sync_wait(chan, cookie);
675 + if (ret)
676 + DRM_ERROR("Failed to wait for DMA: %d\n", ret);
677 +}
678 +
679 +#define DSI_READ(offset) readl(dsi->regs + (offset))
680 +#define DSI_WRITE(offset, val) dsi_dma_workaround_write(dsi, offset, val)
681 +#define DSI_PORT_READ(offset) \
682 + DSI_READ(dsi->port ? DSI1_##offset : DSI0_##offset)
683 +#define DSI_PORT_WRITE(offset, val) \
684 + DSI_WRITE(dsi->port ? DSI1_##offset : DSI0_##offset, val)
685 +#define DSI_PORT_BIT(bit) (dsi->port ? DSI1_##bit : DSI0_##bit)
686 +
687 +/* VC4 DSI encoder KMS struct */
688 +struct vc4_dsi_encoder {
689 + struct vc4_encoder base;
690 + struct vc4_dsi *dsi;
691 +};
692 +
693 +static inline struct vc4_dsi_encoder *
694 +to_vc4_dsi_encoder(struct drm_encoder *encoder)
695 +{
696 + return container_of(encoder, struct vc4_dsi_encoder, base.base);
697 +}
698 +
699 +/* VC4 DSI connector KMS struct */
700 +struct vc4_dsi_connector {
701 + struct drm_connector base;
702 + struct vc4_dsi *dsi;
703 +};
704 +
705 +static inline struct vc4_dsi_connector *
706 +to_vc4_dsi_connector(struct drm_connector *connector)
707 +{
708 + return container_of(connector, struct vc4_dsi_connector, base);
709 +}
710 +
711 +#define DSI_REG(reg) { reg, #reg }
712 +static const struct {
713 + u32 reg;
714 + const char *name;
715 +} dsi0_regs[] = {
716 + DSI_REG(DSI0_CTRL),
717 + DSI_REG(DSI0_STAT),
718 + DSI_REG(DSI0_HSTX_TO_CNT),
719 + DSI_REG(DSI0_LPRX_TO_CNT),
720 + DSI_REG(DSI0_TA_TO_CNT),
721 + DSI_REG(DSI0_PR_TO_CNT),
722 + DSI_REG(DSI0_DISP0_CTRL),
723 + DSI_REG(DSI0_DISP1_CTRL),
724 + DSI_REG(DSI0_INT_STAT),
725 + DSI_REG(DSI0_INT_EN),
726 + DSI_REG(DSI0_PHYC),
727 + DSI_REG(DSI0_HS_CLT0),
728 + DSI_REG(DSI0_HS_CLT1),
729 + DSI_REG(DSI0_HS_CLT2),
730 + DSI_REG(DSI0_HS_DLT3),
731 + DSI_REG(DSI0_HS_DLT4),
732 + DSI_REG(DSI0_HS_DLT5),
733 + DSI_REG(DSI0_HS_DLT6),
734 + DSI_REG(DSI0_HS_DLT7),
735 + DSI_REG(DSI0_PHY_AFEC0),
736 + DSI_REG(DSI0_PHY_AFEC1),
737 + DSI_REG(DSI0_ID),
738 +};
739 +
740 +static const struct {
741 + u32 reg;
742 + const char *name;
743 +} dsi1_regs[] = {
744 + DSI_REG(DSI1_CTRL),
745 + DSI_REG(DSI1_STAT),
746 + DSI_REG(DSI1_HSTX_TO_CNT),
747 + DSI_REG(DSI1_LPRX_TO_CNT),
748 + DSI_REG(DSI1_TA_TO_CNT),
749 + DSI_REG(DSI1_PR_TO_CNT),
750 + DSI_REG(DSI1_DISP0_CTRL),
751 + DSI_REG(DSI1_DISP1_CTRL),
752 + DSI_REG(DSI1_INT_STAT),
753 + DSI_REG(DSI1_INT_EN),
754 + DSI_REG(DSI1_PHYC),
755 + DSI_REG(DSI1_HS_CLT0),
756 + DSI_REG(DSI1_HS_CLT1),
757 + DSI_REG(DSI1_HS_CLT2),
758 + DSI_REG(DSI1_HS_DLT3),
759 + DSI_REG(DSI1_HS_DLT4),
760 + DSI_REG(DSI1_HS_DLT5),
761 + DSI_REG(DSI1_HS_DLT6),
762 + DSI_REG(DSI1_HS_DLT7),
763 + DSI_REG(DSI1_PHY_AFEC0),
764 + DSI_REG(DSI1_PHY_AFEC1),
765 + DSI_REG(DSI1_ID),
766 +};
767 +
768 +static void vc4_dsi_dump_regs(struct vc4_dsi *dsi)
769 +{
770 + int i;
771 +
772 + if (dsi->port == 0) {
773 + for (i = 0; i < ARRAY_SIZE(dsi0_regs); i++) {
774 + DRM_INFO("0x%04x (%s): 0x%08x\n",
775 + dsi0_regs[i].reg, dsi0_regs[i].name,
776 + DSI_READ(dsi0_regs[i].reg));
777 + }
778 + } else {
779 + for (i = 0; i < ARRAY_SIZE(dsi1_regs); i++) {
780 + DRM_INFO("0x%04x (%s): 0x%08x\n",
781 + dsi1_regs[i].reg, dsi1_regs[i].name,
782 + DSI_READ(dsi1_regs[i].reg));
783 + }
784 + }
785 +}
786 +
787 +#ifdef CONFIG_DEBUG_FS
788 +int vc4_dsi_debugfs_regs(struct seq_file *m, void *unused)
789 +{
790 + struct drm_info_node *node = (struct drm_info_node *)m->private;
791 + struct drm_device *drm = node->minor->dev;
792 + struct vc4_dev *vc4 = to_vc4_dev(drm);
793 + int dsi_index = (uintptr_t)node->info_ent->data;
794 + struct vc4_dsi *dsi = (dsi_index == 1 ? vc4->dsi1 : NULL);
795 + int i;
796 +
797 + if (!dsi)
798 + return 0;
799 +
800 + if (dsi->port == 0) {
801 + for (i = 0; i < ARRAY_SIZE(dsi0_regs); i++) {
802 + seq_printf(m, "0x%04x (%s): 0x%08x\n",
803 + dsi0_regs[i].reg, dsi0_regs[i].name,
804 + DSI_READ(dsi0_regs[i].reg));
805 + }
806 + } else {
807 + for (i = 0; i < ARRAY_SIZE(dsi1_regs); i++) {
808 + seq_printf(m, "0x%04x (%s): 0x%08x\n",
809 + dsi1_regs[i].reg, dsi1_regs[i].name,
810 + DSI_READ(dsi1_regs[i].reg));
811 + }
812 + }
813 +
814 + return 0;
815 +}
816 +#endif
817 +
818 +static enum drm_connector_status
819 +vc4_dsi_connector_detect(struct drm_connector *connector, bool force)
820 +{
821 + struct vc4_dsi_connector *vc4_connector =
822 + to_vc4_dsi_connector(connector);
823 + struct vc4_dsi *dsi = vc4_connector->dsi;
824 +
825 + if (dsi->panel)
826 + return connector_status_connected;
827 + else
828 + return connector_status_disconnected;
829 +}
830 +
831 +static void vc4_dsi_connector_destroy(struct drm_connector *connector)
832 +{
833 + drm_connector_unregister(connector);
834 + drm_connector_cleanup(connector);
835 +}
836 +
837 +static int vc4_dsi_connector_get_modes(struct drm_connector *connector)
838 +{
839 + struct vc4_dsi_connector *vc4_connector =
840 + to_vc4_dsi_connector(connector);
841 + struct vc4_dsi *dsi = vc4_connector->dsi;
842 +
843 + if (dsi->panel)
844 + return drm_panel_get_modes(dsi->panel);
845 +
846 + return 0;
847 +}
848 +
849 +static const struct drm_connector_funcs vc4_dsi_connector_funcs = {
850 + .dpms = drm_atomic_helper_connector_dpms,
851 + .detect = vc4_dsi_connector_detect,
852 + .fill_modes = drm_helper_probe_single_connector_modes,
853 + .destroy = vc4_dsi_connector_destroy,
854 + .reset = drm_atomic_helper_connector_reset,
855 + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
856 + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
857 +};
858 +
859 +static const struct drm_connector_helper_funcs vc4_dsi_connector_helper_funcs = {
860 + .get_modes = vc4_dsi_connector_get_modes,
861 +};
862 +
863 +static struct drm_connector *vc4_dsi_connector_init(struct drm_device *dev,
864 + struct vc4_dsi *dsi)
865 +{
866 + struct drm_connector *connector = NULL;
867 + struct vc4_dsi_connector *dsi_connector;
868 + int ret = 0;
869 +
870 + dsi_connector = devm_kzalloc(dev->dev, sizeof(*dsi_connector),
871 + GFP_KERNEL);
872 + if (!dsi_connector) {
873 + ret = -ENOMEM;
874 + goto fail;
875 + }
876 + connector = &dsi_connector->base;
877 +
878 + dsi_connector->dsi = dsi;
879 +
880 + drm_connector_init(dev, connector, &vc4_dsi_connector_funcs,
881 + DRM_MODE_CONNECTOR_DSI);
882 + drm_connector_helper_add(connector, &vc4_dsi_connector_helper_funcs);
883 +
884 + connector->polled = 0;
885 + connector->interlace_allowed = 0;
886 + connector->doublescan_allowed = 0;
887 +
888 + drm_mode_connector_attach_encoder(connector, dsi->encoder);
889 +
890 + return connector;
891 +
892 +fail:
893 + if (connector)
894 + vc4_dsi_connector_destroy(connector);
895 +
896 + return ERR_PTR(ret);
897 +}
898 +
899 +static void vc4_dsi_encoder_destroy(struct drm_encoder *encoder)
900 +{
901 + drm_encoder_cleanup(encoder);
902 +}
903 +
904 +static const struct drm_encoder_funcs vc4_dsi_encoder_funcs = {
905 + .destroy = vc4_dsi_encoder_destroy,
906 +};
907 +
908 +static void vc4_dsi_latch_ulps(struct vc4_dsi *dsi, bool latch)
909 +{
910 + u32 afec0 = DSI_PORT_READ(PHY_AFEC0);
911 +
912 + if (latch)
913 + afec0 |= DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS);
914 + else
915 + afec0 &= ~DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS);
916 +
917 + DSI_PORT_WRITE(PHY_AFEC0, afec0);
918 +}
919 +
920 +/* Enters or exits Ultra Low Power State. */
921 +static void vc4_dsi_ulps(struct vc4_dsi *dsi, bool ulps)
922 +{
923 + bool continuous = dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS;
924 + u32 phyc_ulps = ((continuous ? DSI_PORT_BIT(PHYC_CLANE_ULPS) : 0) |
925 + DSI_PHYC_DLANE0_ULPS |
926 + (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) |
927 + (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) |
928 + (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0));
929 + u32 stat_ulps = ((continuous ? DSI1_STAT_PHY_CLOCK_ULPS : 0) |
930 + DSI1_STAT_PHY_D0_ULPS |
931 + (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) |
932 + (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) |
933 + (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0));
934 + u32 stat_stop = ((continuous ? DSI1_STAT_PHY_CLOCK_STOP : 0) |
935 + DSI1_STAT_PHY_D0_STOP |
936 + (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) |
937 + (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) |
938 + (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0));
939 + int ret;
940 +
941 + DSI_PORT_WRITE(STAT, stat_ulps);
942 + DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) | phyc_ulps);
943 + ret = wait_for((DSI_PORT_READ(STAT) & stat_ulps) == stat_ulps, 200);
944 + if (ret) {
945 + dev_warn(&dsi->pdev->dev,
946 + "Timeout waiting for DSI ULPS entry: STAT 0x%08x",
947 + DSI_PORT_READ(STAT));
948 + DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
949 + vc4_dsi_latch_ulps(dsi, false);
950 + return;
951 + }
952 +
953 + /* The DSI module can't be disabled while the module is
954 + * generating ULPS state. So, to be able to disable the
955 + * module, we have the AFE latch the ULPS state and continue
956 + * on to having the module enter STOP.
957 + */
958 + vc4_dsi_latch_ulps(dsi, ulps);
959 +
960 + DSI_PORT_WRITE(STAT, stat_stop);
961 + DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
962 + ret = wait_for((DSI_PORT_READ(STAT) & stat_stop) == stat_stop, 200);
963 + if (ret) {
964 + dev_warn(&dsi->pdev->dev,
965 + "Timeout waiting for DSI STOP entry: STAT 0x%08x",
966 + DSI_PORT_READ(STAT));
967 + DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
968 + return;
969 + }
970 +}
971 +
972 +static u32
973 +dsi_hs_timing(u32 ui_ns, u32 ns, u32 ui)
974 +{
975 + /* The HS timings have to be rounded up to a multiple of 8
976 + * because we're using the byte clock.
977 + */
978 + return roundup(ui + DIV_ROUND_UP(ns, ui_ns), 8);
979 +}
980 +
981 +/* ESC always runs at 100Mhz. */
982 +#define ESC_TIME_NS 10
983 +
984 +static u32
985 +dsi_esc_timing(u32 ns)
986 +{
987 + return DIV_ROUND_UP(ns, ESC_TIME_NS);
988 +}
989 +
990 +static void vc4_dsi_encoder_disable(struct drm_encoder *encoder)
991 +{
992 + struct vc4_dsi_encoder *vc4_encoder = to_vc4_dsi_encoder(encoder);
993 + struct vc4_dsi *dsi = vc4_encoder->dsi;
994 + struct device *dev = &dsi->pdev->dev;
995 +
996 + drm_panel_disable(dsi->panel);
997 +
998 + vc4_dsi_ulps(dsi, true);
999 +
1000 + drm_panel_unprepare(dsi->panel);
1001 +
1002 + clk_disable_unprepare(dsi->pll_phy_clock);
1003 + clk_disable_unprepare(dsi->escape_clock);
1004 + clk_disable_unprepare(dsi->pixel_clock);
1005 +
1006 + pm_runtime_put(dev);
1007 +}
1008 +
1009 +static void vc4_dsi_encoder_enable(struct drm_encoder *encoder)
1010 +{
1011 + struct drm_display_mode *mode = &encoder->crtc->mode;
1012 + struct vc4_dsi_encoder *vc4_encoder = to_vc4_dsi_encoder(encoder);
1013 + struct vc4_dsi *dsi = vc4_encoder->dsi;
1014 + struct device *dev = &dsi->pdev->dev;
1015 + u32 format = 0, divider = 0;
1016 + bool debug_dump_regs = false;
1017 + unsigned long hs_clock;
1018 + u32 ui_ns;
1019 + /* Minimum LP state duration in escape clock cycles. */
1020 + u32 lpx = dsi_esc_timing(60);
1021 + unsigned long pixel_clock_hz = mode->clock * 1000;
1022 + unsigned long dsip_clock;
1023 + unsigned long phy_clock;
1024 + int ret;
1025 +
1026 + ret = pm_runtime_get_sync(dev);
1027 + if (ret) {
1028 + DRM_ERROR("Failed to runtime PM enable on DSI%d\n", dsi->port);
1029 + return;
1030 + }
1031 +
1032 + ret = drm_panel_prepare(dsi->panel);
1033 + if (ret) {
1034 + DRM_ERROR("Panel failed to prepare\n");
1035 + return;
1036 + }
1037 +
1038 + if (debug_dump_regs) {
1039 + DRM_INFO("DSI regs before:\n");
1040 + vc4_dsi_dump_regs(dsi);
1041 + }
1042 +
1043 + switch (dsi->format) {
1044 + case MIPI_DSI_FMT_RGB888:
1045 + format = DSI_PFORMAT_RGB888;
1046 + divider = 24 / dsi->lanes;
1047 + break;
1048 + case MIPI_DSI_FMT_RGB666:
1049 + format = DSI_PFORMAT_RGB666;
1050 + divider = 24 / dsi->lanes;
1051 + break;
1052 + case MIPI_DSI_FMT_RGB666_PACKED:
1053 + format = DSI_PFORMAT_RGB666_PACKED;
1054 + divider = 18 / dsi->lanes;
1055 + break;
1056 + case MIPI_DSI_FMT_RGB565:
1057 + format = DSI_PFORMAT_RGB565;
1058 + divider = 16 / dsi->lanes;
1059 + break;
1060 + }
1061 +
1062 + phy_clock = pixel_clock_hz * divider;
1063 + ret = clk_set_rate(dsi->pll_phy_clock, phy_clock);
1064 + if (ret) {
1065 + dev_err(&dsi->pdev->dev,
1066 + "Failed to set phy clock to %ld: %d\n", phy_clock, ret);
1067 + }
1068 +
1069 + /* Reset the DSI and all its fifos. */
1070 + DSI_PORT_WRITE(CTRL,
1071 + DSI_CTRL_SOFT_RESET_CFG |
1072 + DSI_PORT_BIT(CTRL_RESET_FIFOS));
1073 +
1074 + DSI_PORT_WRITE(CTRL,
1075 + DSI_CTRL_HSDT_EOT_DISABLE |
1076 + DSI_CTRL_RX_LPDT_EOT_DISABLE);
1077 +
1078 + /* Clear all stat bits so we see what has happened during enable. */
1079 + DSI_PORT_WRITE(STAT, DSI_PORT_READ(STAT));
1080 +
1081 + /* Set AFE CTR00/CTR1 to release powerdown of analog. */
1082 + if (dsi->port == 0) {
1083 + u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |
1084 + VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ));
1085 +
1086 + if (dsi->lanes < 2)
1087 + afec0 |= DSI0_PHY_AFEC0_PD_DLANE1;
1088 +
1089 + if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO))
1090 + afec0 |= DSI0_PHY_AFEC0_RESET;
1091 +
1092 + DSI_PORT_WRITE(PHY_AFEC0, afec0);
1093 +
1094 + DSI_PORT_WRITE(PHY_AFEC1,
1095 + VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE1) |
1096 + VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE0) |
1097 + VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_CLANE));
1098 + } else {
1099 + u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |
1100 + VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) |
1101 + VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_CLANE) |
1102 + VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE0) |
1103 + VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE1) |
1104 + VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE2) |
1105 + VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE3));
1106 +
1107 + if (dsi->lanes < 4)
1108 + afec0 |= DSI1_PHY_AFEC0_PD_DLANE3;
1109 + if (dsi->lanes < 3)
1110 + afec0 |= DSI1_PHY_AFEC0_PD_DLANE2;
1111 + if (dsi->lanes < 2)
1112 + afec0 |= DSI1_PHY_AFEC0_PD_DLANE1;
1113 +
1114 + afec0 |= DSI1_PHY_AFEC0_RESET;
1115 +
1116 + DSI_PORT_WRITE(PHY_AFEC0, afec0);
1117 +
1118 + DSI_PORT_WRITE(PHY_AFEC1, 0);
1119 +
1120 + /* AFEC reset hold time */
1121 + mdelay(1);
1122 + }
1123 +
1124 + ret = clk_prepare_enable(dsi->escape_clock);
1125 + if (ret) {
1126 + DRM_ERROR("Failed to turn on DSI escape clock: %d\n", ret);
1127 + return;
1128 + }
1129 +
1130 + ret = clk_prepare_enable(dsi->pll_phy_clock);
1131 + if (ret) {
1132 + DRM_ERROR("Failed to turn on DSI PLL: %d\n", ret);
1133 + return;
1134 + }
1135 +
1136 + hs_clock = clk_get_rate(dsi->pll_phy_clock);
1137 +
1138 + /* Yes, we set the DSI0P/DSI1P pixel clock to the byte rate,
1139 + * not the pixel clock rate. DSIxP take from the APHY's byte,
1140 + * DDR2, or DDR4 clock (we use byte) and feed into the PV at
1141 + * that rate. Separately, a value derived from PIX_CLK_DIV
1142 + * and HS_CLKC is fed into the PV to divide down to the actual
1143 + * pixel clock for pushing pixels into DSI.
1144 + */
1145 + dsip_clock = phy_clock / 8;
1146 + ret = clk_set_rate(dsi->pixel_clock, dsip_clock);
1147 + if (ret) {
1148 + dev_err(dev, "Failed to set pixel clock to %ldHz: %d\n",
1149 + dsip_clock, ret);
1150 + }
1151 +
1152 + ret = clk_prepare_enable(dsi->pixel_clock);
1153 + if (ret) {
1154 + DRM_ERROR("Failed to turn on DSI pixel clock: %d\n", ret);
1155 + return;
1156 + }
1157 +
1158 + /* How many ns one DSI unit interval is. Note that the clock
1159 + * is DDR, so there's an extra divide by 2.
1160 + */
1161 + ui_ns = DIV_ROUND_UP(500000000, hs_clock);
1162 +
1163 + DSI_PORT_WRITE(HS_CLT0,
1164 + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 262, 0),
1165 + DSI_HS_CLT0_CZERO) |
1166 + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 0, 8),
1167 + DSI_HS_CLT0_CPRE) |
1168 + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 38, 0),
1169 + DSI_HS_CLT0_CPREP));
1170 +
1171 + DSI_PORT_WRITE(HS_CLT1,
1172 + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 0),
1173 + DSI_HS_CLT1_CTRAIL) |
1174 + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 52),
1175 + DSI_HS_CLT1_CPOST));
1176 +
1177 + DSI_PORT_WRITE(HS_CLT2,
1178 + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1000000, 0),
1179 + DSI_HS_CLT2_WUP));
1180 +
1181 + DSI_PORT_WRITE(HS_DLT3,
1182 + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 100, 0),
1183 + DSI_HS_DLT3_EXIT) |
1184 + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 105, 6),
1185 + DSI_HS_DLT3_ZERO) |
1186 + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 40, 4),
1187 + DSI_HS_DLT3_PRE));
1188 +
1189 + DSI_PORT_WRITE(HS_DLT4,
1190 + VC4_SET_FIELD(dsi_hs_timing(ui_ns, lpx * ESC_TIME_NS, 0),
1191 + DSI_HS_DLT4_LPX) |
1192 + VC4_SET_FIELD(max(dsi_hs_timing(ui_ns, 0, 8),
1193 + dsi_hs_timing(ui_ns, 60, 4)),
1194 + DSI_HS_DLT4_TRAIL) |
1195 + VC4_SET_FIELD(0, DSI_HS_DLT4_ANLAT));
1196 +
1197 + DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1000, 5000),
1198 + DSI_HS_DLT5_INIT));
1199 +
1200 + DSI_PORT_WRITE(HS_DLT6,
1201 + VC4_SET_FIELD(lpx * 5, DSI_HS_DLT6_TA_GET) |
1202 + VC4_SET_FIELD(lpx, DSI_HS_DLT6_TA_SURE) |
1203 + VC4_SET_FIELD(lpx * 4, DSI_HS_DLT6_TA_GO) |
1204 + VC4_SET_FIELD(lpx, DSI_HS_DLT6_LP_LPX));
1205 +
1206 + DSI_PORT_WRITE(HS_DLT7,
1207 + VC4_SET_FIELD(dsi_esc_timing(1000000),
1208 + DSI_HS_DLT7_LP_WUP));
1209 +
1210 + DSI_PORT_WRITE(PHYC,
1211 + DSI_PHYC_DLANE0_ENABLE |
1212 + (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) |
1213 + (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) |
1214 + (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) |
1215 + DSI_PORT_BIT(PHYC_CLANE_ENABLE) |
1216 + ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ?
1217 + 0 : DSI_PORT_BIT(PHYC_HS_CLK_CONTINUOUS)) |
1218 + (dsi->port == 0 ?
1219 + VC4_SET_FIELD(lpx - 1, DSI0_PHYC_ESC_CLK_LPDT) :
1220 + VC4_SET_FIELD(lpx - 1, DSI1_PHYC_ESC_CLK_LPDT)));
1221 +
1222 + DSI_PORT_WRITE(CTRL,
1223 + DSI_PORT_READ(CTRL) |
1224 + DSI_CTRL_CAL_BYTE);
1225 +
1226 + /* HS timeout in HS clock cycles: disabled. */
1227 + DSI_PORT_WRITE(HSTX_TO_CNT, 0);
1228 + /* LP receive timeout in HS clocks. */
1229 + DSI_PORT_WRITE(LPRX_TO_CNT, 0xffffff);
1230 + /* Bus turnaround timeout */
1231 + DSI_PORT_WRITE(TA_TO_CNT, 100000);
1232 + /* Display reset sequence timeout */
1233 + DSI_PORT_WRITE(PR_TO_CNT, 100000);
1234 +
1235 + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
1236 + DSI_PORT_WRITE(DISP0_CTRL,
1237 + VC4_SET_FIELD(divider, DSI_DISP0_PIX_CLK_DIV) |
1238 + VC4_SET_FIELD(format, DSI_DISP0_PFORMAT) |
1239 + VC4_SET_FIELD(DSI_DISP0_LP_STOP_PERFRAME,
1240 + DSI_DISP0_LP_STOP_CTRL) |
1241 + DSI_DISP0_ST_END |
1242 + DSI_DISP0_ENABLE);
1243 + } else {
1244 + DSI_PORT_WRITE(DISP0_CTRL,
1245 + DSI_DISP0_COMMAND_MODE |
1246 + DSI_DISP0_ENABLE);
1247 + }
1248 +
1249 + /* Set up DISP1 for transferring long command payloads through
1250 + * the pixfifo.
1251 + */
1252 + DSI_PORT_WRITE(DISP1_CTRL,
1253 + VC4_SET_FIELD(DSI_DISP1_PFORMAT_32BIT_LE,
1254 + DSI_DISP1_PFORMAT) |
1255 + DSI_DISP1_ENABLE);
1256 +
1257 + /* Ungate the block. */
1258 + if (dsi->port == 0)
1259 + DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI0_CTRL_CTRL0);
1260 + else
1261 + DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI1_CTRL_EN);
1262 +
1263 + /* Bring AFE out of reset. */
1264 + if (dsi->port == 0) {
1265 + } else {
1266 + DSI_PORT_WRITE(PHY_AFEC0,
1267 + DSI_PORT_READ(PHY_AFEC0) &
1268 + ~DSI1_PHY_AFEC0_RESET);
1269 + }
1270 +
1271 + vc4_dsi_ulps(dsi, false);
1272 +
1273 + if (debug_dump_regs) {
1274 + DRM_INFO("DSI regs after:\n");
1275 + vc4_dsi_dump_regs(dsi);
1276 + }
1277 +
1278 + ret = drm_panel_enable(dsi->panel);
1279 + if (ret) {
1280 + DRM_ERROR("Panel failed to enable\n");
1281 + drm_panel_unprepare(dsi->panel);
1282 + return;
1283 + }
1284 +}
1285 +
1286 +static ssize_t vc4_dsi_host_transfer(struct mipi_dsi_host *host,
1287 + const struct mipi_dsi_msg *msg)
1288 +{
1289 + struct vc4_dsi *dsi = host_to_dsi(host);
1290 + struct mipi_dsi_packet packet;
1291 + u32 pkth = 0, pktc = 0;
1292 + int i, ret;
1293 + bool is_long = mipi_dsi_packet_format_is_long(msg->type);
1294 + u32 cmd_fifo_len = 0, pix_fifo_len = 0;
1295 +
1296 + mipi_dsi_create_packet(&packet, msg);
1297 +
1298 + pkth |= VC4_SET_FIELD(packet.header[0], DSI_TXPKT1H_BC_DT);
1299 + pkth |= VC4_SET_FIELD(packet.header[1] |
1300 + (packet.header[2] << 8),
1301 + DSI_TXPKT1H_BC_PARAM);
1302 + if (is_long) {
1303 + /* Divide data across the various FIFOs we have available.
1304 + * The command FIFO takes byte-oriented data, but is of
1305 + * limited size. The pixel FIFO (never actually used for
1306 + * pixel data in reality) is word oriented, and substantially
1307 + * larger. So, we use the pixel FIFO for most of the data,
1308 + * sending the residual bytes in the command FIFO at the start.
1309 + *
1310 + * With this arrangement, the command FIFO will never get full.
1311 + */
1312 + if (packet.payload_length <= 16) {
1313 + cmd_fifo_len = packet.payload_length;
1314 + pix_fifo_len = 0;
1315 + } else {
1316 + cmd_fifo_len = (packet.payload_length %
1317 + DSI_PIX_FIFO_WIDTH);
1318 + pix_fifo_len = ((packet.payload_length - cmd_fifo_len) /
1319 + DSI_PIX_FIFO_WIDTH);
1320 + }
1321 +
1322 + WARN_ON_ONCE(pix_fifo_len >= DSI_PIX_FIFO_DEPTH);
1323 +
1324 + pkth |= VC4_SET_FIELD(cmd_fifo_len, DSI_TXPKT1H_BC_CMDFIFO);
1325 + }
1326 +
1327 + if (msg->rx_len) {
1328 + pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_RX,
1329 + DSI_TXPKT1C_CMD_CTRL);
1330 + } else {
1331 + pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_TX,
1332 + DSI_TXPKT1C_CMD_CTRL);
1333 + }
1334 +
1335 + for (i = 0; i < cmd_fifo_len; i++)
1336 + DSI_PORT_WRITE(TXPKT_CMD_FIFO, packet.payload[i]);
1337 + for (i = 0; i < pix_fifo_len; i++) {
1338 + const u8 *pix = packet.payload + cmd_fifo_len + i * 4;
1339 +
1340 + DSI_PORT_WRITE(TXPKT_PIX_FIFO,
1341 + pix[0] |
1342 + pix[1] << 8 |
1343 + pix[2] << 16 |
1344 + pix[3] << 24);
1345 + }
1346 +
1347 + if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1348 + pktc |= DSI_TXPKT1C_CMD_MODE_LP;
1349 + if (is_long)
1350 + pktc |= DSI_TXPKT1C_CMD_TYPE_LONG;
1351 +
1352 + /* Send one copy of the packet. Larger repeats are used for pixel
1353 + * data in command mode.
1354 + */
1355 + pktc |= VC4_SET_FIELD(1, DSI_TXPKT1C_CMD_REPEAT);
1356 +
1357 + pktc |= DSI_TXPKT1C_CMD_EN;
1358 + if (pix_fifo_len) {
1359 + pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SECONDARY,
1360 + DSI_TXPKT1C_DISPLAY_NO);
1361 + } else {
1362 + pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SHORT,
1363 + DSI_TXPKT1C_DISPLAY_NO);
1364 + }
1365 +
1366 + /* Enable the appropriate interrupt for the transfer completion. */
1367 + dsi->xfer_result = 0;
1368 + reinit_completion(&dsi->xfer_completion);
1369 + DSI_PORT_WRITE(INT_STAT, DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF);
1370 + if (msg->rx_len) {
1371 + DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
1372 + DSI1_INT_PHY_DIR_RTF));
1373 + } else {
1374 + DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
1375 + DSI1_INT_TXPKT1_DONE));
1376 + }
1377 +
1378 + /* Send the packet. */
1379 + DSI_PORT_WRITE(TXPKT1H, pkth);
1380 + DSI_PORT_WRITE(TXPKT1C, pktc);
1381 +
1382 + if (!wait_for_completion_timeout(&dsi->xfer_completion,
1383 + msecs_to_jiffies(1000))) {
1384 + dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout");
1385 + dev_err(&dsi->pdev->dev, "instat: 0x%08x\n",
1386 + DSI_PORT_READ(INT_STAT));
1387 + ret = -ETIMEDOUT;
1388 + } else {
1389 + ret = dsi->xfer_result;
1390 + }
1391 +
1392 + DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
1393 +
1394 + if (ret)
1395 + goto reset_fifo_and_return;
1396 +
1397 + if (ret == 0 && msg->rx_len) {
1398 + u32 rxpkt1h = DSI_PORT_READ(RXPKT1H);
1399 + u8 *msg_rx = msg->rx_buf;
1400 +
1401 + if (rxpkt1h & DSI_RXPKT1H_PKT_TYPE_LONG) {
1402 + u32 rxlen = VC4_GET_FIELD(rxpkt1h,
1403 + DSI_RXPKT1H_BC_PARAM);
1404 +
1405 + if (rxlen != msg->rx_len) {
1406 + DRM_ERROR("DSI returned %db, expecting %db\n",
1407 + rxlen, (int)msg->rx_len);
1408 + ret = -ENXIO;
1409 + goto reset_fifo_and_return;
1410 + }
1411 +
1412 + for (i = 0; i < msg->rx_len; i++)
1413 + msg_rx[i] = DSI_READ(DSI1_RXPKT_FIFO);
1414 + } else {
1415 + /* FINISHME: Handle AWER */
1416 +
1417 + msg_rx[0] = VC4_GET_FIELD(rxpkt1h,
1418 + DSI_RXPKT1H_SHORT_0);
1419 + if (msg->rx_len > 1) {
1420 + msg_rx[1] = VC4_GET_FIELD(rxpkt1h,
1421 + DSI_RXPKT1H_SHORT_1);
1422 + }
1423 + }
1424 + }
1425 +
1426 + return ret;
1427 +
1428 +reset_fifo_and_return:
1429 + DRM_ERROR("DSI transfer failed, resetting: %d\n", ret);
1430 +
1431 + DSI_PORT_WRITE(TXPKT1C, DSI_PORT_READ(TXPKT1C) & ~DSI_TXPKT1C_CMD_EN);
1432 + udelay(1);
1433 + DSI_PORT_WRITE(CTRL,
1434 + DSI_PORT_READ(CTRL) |
1435 + DSI_PORT_BIT(CTRL_RESET_FIFOS));
1436 +
1437 + DSI_PORT_WRITE(TXPKT1C, 0);
1438 + DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
1439 + return ret;
1440 +}
1441 +
1442 +static int vc4_dsi_host_attach(struct mipi_dsi_host *host,
1443 + struct mipi_dsi_device *device)
1444 +{
1445 + struct vc4_dsi *dsi = host_to_dsi(host);
1446 + int ret = 0;
1447 +
1448 + dsi->lanes = device->lanes;
1449 + dsi->channel = device->channel;
1450 + dsi->format = device->format;
1451 + dsi->mode_flags = device->mode_flags;
1452 +
1453 + if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1454 + dev_err(&dsi->pdev->dev,
1455 + "Only VIDEO mode panels supported currently.\n");
1456 + return 0;
1457 + }
1458 +
1459 + dsi->panel = of_drm_find_panel(device->dev.of_node);
1460 + if (!dsi->panel)
1461 + return 0;
1462 +
1463 + ret = drm_panel_attach(dsi->panel, dsi->connector);
1464 + if (ret != 0)
1465 + return ret;
1466 +
1467 + drm_helper_hpd_irq_event(dsi->connector->dev);
1468 +
1469 + return 0;
1470 +}
1471 +
1472 +static int vc4_dsi_host_detach(struct mipi_dsi_host *host,
1473 + struct mipi_dsi_device *device)
1474 +{
1475 + struct vc4_dsi *dsi = host_to_dsi(host);
1476 +
1477 + if (dsi->panel) {
1478 + int ret = drm_panel_detach(dsi->panel);
1479 +
1480 + if (ret)
1481 + return ret;
1482 +
1483 + dsi->panel = NULL;
1484 +
1485 + drm_helper_hpd_irq_event(dsi->connector->dev);
1486 + }
1487 +
1488 + return 0;
1489 +}
1490 +
1491 +static const struct mipi_dsi_host_ops vc4_dsi_host_ops = {
1492 + .attach = vc4_dsi_host_attach,
1493 + .detach = vc4_dsi_host_detach,
1494 + .transfer = vc4_dsi_host_transfer,
1495 +};
1496 +
1497 +static const struct drm_encoder_helper_funcs vc4_dsi_encoder_helper_funcs = {
1498 + .disable = vc4_dsi_encoder_disable,
1499 + .enable = vc4_dsi_encoder_enable,
1500 +};
1501 +
1502 +static const struct of_device_id vc4_dsi_dt_match[] = {
1503 + { .compatible = "brcm,bcm2835-dsi1", (void *)(uintptr_t)1 },
1504 + {}
1505 +};
1506 +
1507 +static void dsi_handle_error(struct vc4_dsi *dsi,
1508 + irqreturn_t *ret, u32 stat, u32 bit,
1509 + const char *type)
1510 +{
1511 + if (!(stat & bit))
1512 + return;
1513 +
1514 + DRM_ERROR("DSI%d: %s error\n", dsi->port, type);
1515 + *ret = IRQ_HANDLED;
1516 +}
1517 +
1518 +static irqreturn_t vc4_dsi_irq_handler(int irq, void *data)
1519 +{
1520 + struct vc4_dsi *dsi = data;
1521 + u32 stat = DSI_PORT_READ(INT_STAT);
1522 + irqreturn_t ret = IRQ_NONE;
1523 +
1524 + DSI_PORT_WRITE(INT_STAT, stat);
1525 +
1526 + dsi_handle_error(dsi, &ret, stat,
1527 + DSI1_INT_ERR_SYNC_ESC, "LPDT sync");
1528 + dsi_handle_error(dsi, &ret, stat,
1529 + DSI1_INT_ERR_CONTROL, "data lane 0 sequence");
1530 + dsi_handle_error(dsi, &ret, stat,
1531 + DSI1_INT_ERR_CONT_LP0, "LP0 contention");
1532 + dsi_handle_error(dsi, &ret, stat,
1533 + DSI1_INT_ERR_CONT_LP1, "LP1 contention");
1534 + dsi_handle_error(dsi, &ret, stat,
1535 + DSI1_INT_HSTX_TO, "HSTX timeout");
1536 + dsi_handle_error(dsi, &ret, stat,
1537 + DSI1_INT_LPRX_TO, "LPRX timeout");
1538 + dsi_handle_error(dsi, &ret, stat,
1539 + DSI1_INT_TA_TO, "turnaround timeout");
1540 + dsi_handle_error(dsi, &ret, stat,
1541 + DSI1_INT_PR_TO, "peripheral reset timeout");
1542 +
1543 + if (stat & (DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF)) {
1544 + complete(&dsi->xfer_completion);
1545 + ret = IRQ_HANDLED;
1546 + } else if (stat & DSI1_INT_HSTX_TO) {
1547 + complete(&dsi->xfer_completion);
1548 + dsi->xfer_result = -ETIMEDOUT;
1549 + ret = IRQ_HANDLED;
1550 + }
1551 +
1552 + return ret;
1553 +}
1554 +
1555 +/**
1556 + * Exposes clocks generated by the analog PHY that are consumed by
1557 + * CPRMAN (clk-bcm2835.c).
1558 + */
1559 +static int
1560 +vc4_dsi_init_phy_clocks(struct vc4_dsi *dsi)
1561 +{
1562 + struct device *dev = &dsi->pdev->dev;
1563 + const char *parent_name = __clk_get_name(dsi->pll_phy_clock);
1564 + static const struct {
1565 + const char *dsi0_name, *dsi1_name;
1566 + int div;
1567 + } phy_clocks[] = {
1568 + { "dsi0_byte", "dsi1_byte", 8 },
1569 + { "dsi0_ddr2", "dsi1_ddr2", 4 },
1570 + { "dsi0_ddr", "dsi1_ddr", 2 },
1571 + };
1572 + int i;
1573 +
1574 + dsi->clk_onecell.clk_num = ARRAY_SIZE(phy_clocks);
1575 + dsi->clk_onecell.clks = devm_kcalloc(dev,
1576 + dsi->clk_onecell.clk_num,
1577 + sizeof(*dsi->clk_onecell.clks),
1578 + GFP_KERNEL);
1579 + if (!dsi->clk_onecell.clks)
1580 + return -ENOMEM;
1581 +
1582 + for (i = 0; i < ARRAY_SIZE(phy_clocks); i++) {
1583 + struct clk_fixed_factor *fix = &dsi->phy_clocks[i];
1584 + struct clk_init_data init;
1585 + struct clk *clk;
1586 +
1587 + /* We just use core fixed factor clock ops for the PHY
1588 + * clocks. The clocks are actually gated by the
1589 + * PHY_AFEC0_DDRCLK_EN bits, which we should be
1590 + * setting if we use the DDR/DDR2 clocks. However,
1591 + * vc4_dsi_encoder_enable() is setting up both AFEC0,
1592 + * setting both our parent DSI PLL's rate and this
1593 + * clock's rate, so it knows if DDR/DDR2 are going to
1594 + * be used and could enable the gates itself.
1595 + */
1596 + fix->mult = 1;
1597 + fix->div = phy_clocks[i].div;
1598 + fix->hw.init = &init;
1599 +
1600 + memset(&init, 0, sizeof(init));
1601 + init.parent_names = &parent_name;
1602 + init.num_parents = 1;
1603 + if (dsi->port == 1)
1604 + init.name = phy_clocks[i].dsi1_name;
1605 + else
1606 + init.name = phy_clocks[i].dsi0_name;
1607 + init.ops = &clk_fixed_factor_ops;
1608 + init.flags = CLK_IS_BASIC;
1609 +
1610 + clk = devm_clk_register(dev, &fix->hw);
1611 + if (IS_ERR(clk))
1612 + return PTR_ERR(clk);
1613 +
1614 + dsi->clk_onecell.clks[i] = clk;
1615 + }
1616 +
1617 + return of_clk_add_provider(dev->of_node,
1618 + of_clk_src_onecell_get,
1619 + &dsi->clk_onecell);
1620 +}
1621 +
1622 +static int vc4_dsi_bind(struct device *dev, struct device *master, void *data)
1623 +{
1624 + struct platform_device *pdev = to_platform_device(dev);
1625 + struct drm_device *drm = dev_get_drvdata(master);
1626 + struct vc4_dev *vc4 = to_vc4_dev(drm);
1627 + struct vc4_dsi *dsi;
1628 + struct vc4_dsi_encoder *vc4_dsi_encoder;
1629 + const struct of_device_id *match;
1630 + dma_cap_mask_t dma_mask;
1631 + int ret;
1632 +
1633 + dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1634 + if (!dsi)
1635 + return -ENOMEM;
1636 +
1637 + match = of_match_device(vc4_dsi_dt_match, dev);
1638 + if (!match)
1639 + return -ENODEV;
1640 +
1641 + dsi->port = (uintptr_t)match->data;
1642 +
1643 + vc4_dsi_encoder = devm_kzalloc(dev, sizeof(*vc4_dsi_encoder),
1644 + GFP_KERNEL);
1645 + if (!vc4_dsi_encoder)
1646 + return -ENOMEM;
1647 + vc4_dsi_encoder->base.type = VC4_ENCODER_TYPE_DSI1;
1648 + vc4_dsi_encoder->dsi = dsi;
1649 + dsi->encoder = &vc4_dsi_encoder->base.base;
1650 +
1651 + dsi->pdev = pdev;
1652 + dsi->regs = vc4_ioremap_regs(pdev, 0);
1653 + if (IS_ERR(dsi->regs))
1654 + return PTR_ERR(dsi->regs);
1655 +
1656 + if (DSI_PORT_READ(ID) != DSI_ID_VALUE) {
1657 + dev_err(dev, "Port returned 0x%08x for ID instead of 0x%08x\n",
1658 + DSI_PORT_READ(ID), DSI_ID_VALUE);
1659 + return -ENODEV;
1660 + }
1661 +
1662 + /* DSI1 has a broken AXI slave that doesn't respond to writes
1663 + * from the ARM. It does handle writes from the DMA engine,
1664 + * so set up a channel for talking to it.
1665 + */
1666 + if (dsi->port == 1) {
1667 + dsi->reg_dma_mem = dma_alloc_coherent(dev, 4,
1668 + &dsi->reg_dma_paddr,
1669 + GFP_KERNEL);
1670 + if (!dsi->reg_dma_mem) {
1671 + DRM_ERROR("Failed to get DMA memory\n");
1672 + return -ENOMEM;
1673 + }
1674 +
1675 + dma_cap_zero(dma_mask);
1676 + dma_cap_set(DMA_MEMCPY, dma_mask);
1677 + dsi->reg_dma_chan = dma_request_chan_by_mask(&dma_mask);
1678 + if (IS_ERR(dsi->reg_dma_chan)) {
1679 + ret = PTR_ERR(dsi->reg_dma_chan);
1680 + if (ret != -EPROBE_DEFER)
1681 + DRM_ERROR("Failed to get DMA channel: %d\n",
1682 + ret);
1683 + return ret;
1684 + }
1685 +
1686 + /* Get the physical address of the device's registers. The
1687 + * struct resource for the regs gives us the bus address
1688 + * instead.
1689 + */
1690 + dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node,
1691 + 0, NULL, NULL));
1692 + }
1693 +
1694 + init_completion(&dsi->xfer_completion);
1695 + /* At startup enable error-reporting interrupts and nothing else. */
1696 + DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
1697 + /* Clear any existing interrupt state. */
1698 + DSI_PORT_WRITE(INT_STAT, DSI_PORT_READ(INT_STAT));
1699 +
1700 + ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1701 + vc4_dsi_irq_handler, 0, "vc4 dsi", dsi);
1702 + if (ret) {
1703 + if (ret != -EPROBE_DEFER)
1704 + dev_err(dev, "Failed to get interrupt: %d\n", ret);
1705 + return ret;
1706 + }
1707 +
1708 + dsi->escape_clock = devm_clk_get(dev, "escape");
1709 + if (IS_ERR(dsi->escape_clock)) {
1710 + ret = PTR_ERR(dsi->escape_clock);
1711 + if (ret != -EPROBE_DEFER)
1712 + dev_err(dev, "Failed to get escape clock: %d\n", ret);
1713 + return ret;
1714 + }
1715 +
1716 + dsi->pll_phy_clock = devm_clk_get(dev, "phy");
1717 + if (IS_ERR(dsi->pll_phy_clock)) {
1718 + ret = PTR_ERR(dsi->pll_phy_clock);
1719 + if (ret != -EPROBE_DEFER)
1720 + dev_err(dev, "Failed to get phy clock: %d\n", ret);
1721 + return ret;
1722 + }
1723 +
1724 + dsi->pixel_clock = devm_clk_get(dev, "pixel");
1725 + if (IS_ERR(dsi->pixel_clock)) {
1726 + ret = PTR_ERR(dsi->pixel_clock);
1727 + if (ret != -EPROBE_DEFER)
1728 + dev_err(dev, "Failed to get pixel clock: %d\n", ret);
1729 + return ret;
1730 + }
1731 +
1732 + /* The esc clock rate is supposed to always be 100Mhz. */
1733 + ret = clk_set_rate(dsi->escape_clock, 100 * 1000000);
1734 + if (ret) {
1735 + dev_err(dev, "Failed to set esc clock: %d\n", ret);
1736 + return ret;
1737 + }
1738 +
1739 + ret = vc4_dsi_init_phy_clocks(dsi);
1740 + if (ret)
1741 + return ret;
1742 +
1743 + if (dsi->port == 1)
1744 + vc4->dsi1 = dsi;
1745 +
1746 + drm_encoder_init(drm, dsi->encoder, &vc4_dsi_encoder_funcs,
1747 + DRM_MODE_ENCODER_DSI, NULL);
1748 + drm_encoder_helper_add(dsi->encoder, &vc4_dsi_encoder_helper_funcs);
1749 +
1750 + dsi->connector = vc4_dsi_connector_init(drm, dsi);
1751 + if (IS_ERR(dsi->connector)) {
1752 + ret = PTR_ERR(dsi->connector);
1753 + goto err_destroy_encoder;
1754 + }
1755 +
1756 + dsi->dsi_host.ops = &vc4_dsi_host_ops;
1757 + dsi->dsi_host.dev = dev;
1758 +
1759 + mipi_dsi_host_register(&dsi->dsi_host);
1760 +
1761 + dev_set_drvdata(dev, dsi);
1762 +
1763 + pm_runtime_enable(dev);
1764 +
1765 + return 0;
1766 +
1767 +err_destroy_encoder:
1768 + vc4_dsi_encoder_destroy(dsi->encoder);
1769 +
1770 + return ret;
1771 +}
1772 +
1773 +static void vc4_dsi_unbind(struct device *dev, struct device *master,
1774 + void *data)
1775 +{
1776 + struct drm_device *drm = dev_get_drvdata(master);
1777 + struct vc4_dev *vc4 = to_vc4_dev(drm);
1778 + struct vc4_dsi *dsi = dev_get_drvdata(dev);
1779 +
1780 + pm_runtime_disable(dev);
1781 +
1782 + vc4_dsi_connector_destroy(dsi->connector);
1783 + vc4_dsi_encoder_destroy(dsi->encoder);
1784 +
1785 + mipi_dsi_host_unregister(&dsi->dsi_host);
1786 +
1787 + clk_disable_unprepare(dsi->pll_phy_clock);
1788 + clk_disable_unprepare(dsi->escape_clock);
1789 +
1790 + if (dsi->port == 1)
1791 + vc4->dsi1 = NULL;
1792 +}
1793 +
1794 +static const struct component_ops vc4_dsi_ops = {
1795 + .bind = vc4_dsi_bind,
1796 + .unbind = vc4_dsi_unbind,
1797 +};
1798 +
1799 +static int vc4_dsi_dev_probe(struct platform_device *pdev)
1800 +{
1801 + return component_add(&pdev->dev, &vc4_dsi_ops);
1802 +}
1803 +
1804 +static int vc4_dsi_dev_remove(struct platform_device *pdev)
1805 +{
1806 + component_del(&pdev->dev, &vc4_dsi_ops);
1807 + return 0;
1808 +}
1809 +
1810 +struct platform_driver vc4_dsi_driver = {
1811 + .probe = vc4_dsi_dev_probe,
1812 + .remove = vc4_dsi_dev_remove,
1813 + .driver = {
1814 + .name = "vc4_dsi",
1815 + .of_match_table = vc4_dsi_dt_match,
1816 + },
1817 +};
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