target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c

   1 /*
   2  * PCIe driver for PLX NAS782X SoCs
   3  *
   4  * Author: Ma Haijun <mahaijuns@gmail.com>
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/pci.h>
  13 #include <linux/clk.h>
  14 #include <linux/module.h>
  15 #include <linux/mbus.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/slab.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_device.h>
  21 #include <linux/of_gpio.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/of_pci.h>
  24 #include <linux/of_platform.h>
  25 #include <linux/gpio.h>
  26 #include <linux/delay.h>
  27 #include <linux/clk.h>
  28 #include <linux/regmap.h>
  29 #include <linux/reset.h>
  30 #include <linux/io.h>
  31 #include <linux/sizes.h>
  32
  33 #define SYS_CTRL_HCSL_CTRL_REGOFFSET    0x114
  34
  35 static inline void oxnas_register_clear_mask(void __iomem *p, unsigned mask)
  36 {
  37         u32 val = readl_relaxed(p);
  38
  39         val &= ~mask;
  40         writel_relaxed(val, p);
  41 }
  42
  43 static inline void oxnas_register_set_mask(void __iomem *p, unsigned mask)
  44 {
  45         u32 val = readl_relaxed(p);
  46
  47         val |= mask;
  48         writel_relaxed(val, p);
  49 }
  50
  51 static inline void oxnas_register_value_mask(void __iomem *p,
  52                                              unsigned mask, unsigned new_value)
  53 {
  54         /* TODO sanity check mask & new_value = new_value */
  55         u32 val = readl_relaxed(p);
  56
  57         val &= ~mask;
  58         val |= new_value;
  59         writel_relaxed(val, p);
  60 }
  61
  62 #define VERSION_ID_MAGIC                0x082510b5
  63 #define LINK_UP_TIMEOUT_SECONDS         1
  64 #define NUM_CONTROLLERS                 1
  65
  66 enum {
  67         PCIE_DEVICE_TYPE_MASK = 0x0F,
  68         PCIE_DEVICE_TYPE_ENDPOINT = 0,
  69         PCIE_DEVICE_TYPE_LEGACY_ENDPOINT = 1,
  70         PCIE_DEVICE_TYPE_ROOT = 4,
  71
  72         PCIE_LTSSM = BIT(4),
  73         PCIE_READY_ENTR_L23 = BIT(9),
  74         PCIE_LINK_UP = BIT(11),
  75         PCIE_OBTRANS = BIT(12),
  76 };
  77
  78 enum {
  79         HCSL_BIAS_ON = BIT(0),
  80         HCSL_PCIE_EN = BIT(1),
  81         HCSL_PCIEA_EN = BIT(2),
  82         HCSL_PCIEB_EN = BIT(3),
  83 };
  84
  85 enum {
  86         /* pcie phy reg offset */
  87         PHY_ADDR = 0,
  88         PHY_DATA = 4,
  89         /* phy data reg bits */
  90         READ_EN = BIT(16),
  91         WRITE_EN = BIT(17),
  92         CAP_DATA = BIT(18),
  93 };
  94
  95 /* core config registers */
  96 enum {
  97         PCI_CONFIG_VERSION_DEVICEID = 0,
  98         PCI_CONFIG_COMMAND_STATUS = 4,
  99 };
 100
 101 /* inbound config registers */
 102 enum {
 103         IB_ADDR_XLATE_ENABLE = 0xFC,
 104
 105         /* bits */
 106         ENABLE_IN_ADDR_TRANS = BIT(0),
 107 };
 108
 109 /* outbound config registers, offset relative to PCIE_POM0_MEM_ADDR */
 110 enum {
 111         PCIE_POM0_MEM_ADDR      = 0,
 112         PCIE_POM1_MEM_ADDR      = 4,
 113         PCIE_IN0_MEM_ADDR       = 8,
 114         PCIE_IN1_MEM_ADDR       = 12,
 115         PCIE_IN_IO_ADDR         = 16,
 116         PCIE_IN_CFG0_ADDR       = 20,
 117         PCIE_IN_CFG1_ADDR       = 24,
 118         PCIE_IN_MSG_ADDR        = 28,
 119         PCIE_IN0_MEM_LIMIT      = 32,
 120         PCIE_IN1_MEM_LIMIT      = 36,
 121         PCIE_IN_IO_LIMIT        = 40,
 122         PCIE_IN_CFG0_LIMIT      = 44,
 123         PCIE_IN_CFG1_LIMIT      = 48,
 124         PCIE_IN_MSG_LIMIT       = 52,
 125         PCIE_AHB_SLAVE_CTRL     = 56,
 126
 127         PCIE_SLAVE_BE_SHIFT     = 22,
 128 };
 129
 130 #define ADDR_VAL(val)   ((val) & 0xFFFF)
 131 #define DATA_VAL(val)   ((val) & 0xFFFF)
 132
 133 #define PCIE_SLAVE_BE(val)      ((val) << PCIE_SLAVE_BE_SHIFT)
 134 #define PCIE_SLAVE_BE_MASK      PCIE_SLAVE_BE(0xF)
 135
 136 struct oxnas_pcie_shared {
 137         /* seems all access are serialized, no lock required */
 138         int refcount;
 139 };
 140
 141 /* Structure representing one PCIe interfaces */
 142 struct oxnas_pcie {
 143         void __iomem *cfgbase;
 144         void __iomem *base;
 145         void __iomem *inbound;
 146         struct regmap *sys_ctrl;
 147         unsigned int outbound_offset;
 148         unsigned int pcie_ctrl_offset;
 149
 150         int haslink;
 151         struct platform_device *pdev;
 152         struct resource io;
 153         struct resource cfg;
 154         struct resource pre_mem;        /* prefetchable */
 155         struct resource non_mem;        /* non-prefetchable */
 156         struct resource busn;           /* max available bus numbers */
 157         int card_reset;                 /* gpio pin, optional */
 158         unsigned hcsl_en;               /* hcsl pci enable bit */
 159         struct clk *clk;
 160         struct clk *busclk;             /* for pcie bus, actually the PLLB */
 161         void *private_data[1];
 162         spinlock_t lock;
 163 };
 164
 165 static struct oxnas_pcie_shared pcie_shared = {
 166         .refcount = 0,
 167 };
 168
 169 static inline struct oxnas_pcie *sys_to_pcie(struct pci_sys_data *sys)
 170 {
 171         return sys->private_data;
 172 }
 173
 174
 175 static inline void set_out_lanes(struct oxnas_pcie *pcie, unsigned lanes)
 176 {
 177         regmap_update_bits(pcie->sys_ctrl, pcie->outbound_offset + PCIE_AHB_SLAVE_CTRL,
 178                                   PCIE_SLAVE_BE_MASK, PCIE_SLAVE_BE(lanes));
 179         wmb();
 180 }
 181
 182 static int oxnas_pcie_link_up(struct oxnas_pcie *pcie)
 183 {
 184         unsigned long end;
 185         unsigned int val;
 186
 187         /* Poll for PCIE link up */
 188         end = jiffies + (LINK_UP_TIMEOUT_SECONDS * HZ);
 189         while (!time_after(jiffies, end)) {
 190                 regmap_read(pcie->sys_ctrl, pcie->pcie_ctrl_offset, &val);
 191                 if (val & PCIE_LINK_UP)
 192                         return 1;
 193         }
 194         return 0;
 195 }
 196
 197 static void oxnas_pcie_setup_hw(struct oxnas_pcie *pcie)
 198 {
 199         /* We won't have any inbound address translation. This allows PCI
 200          * devices to access anywhere in the AHB address map. Might be regarded
 201          * as a bit dangerous, but let's get things working before we worry
 202          * about that
 203          */
 204         oxnas_register_clear_mask(pcie->inbound + IB_ADDR_XLATE_ENABLE,
 205                                   ENABLE_IN_ADDR_TRANS);
 206         wmb();
 207
 208         /*
 209          * Program outbound translation windows
 210          *
 211          * Outbound window is what is referred to as "PCI client" region in HRM
 212          *
 213          * Could use the larger alternative address space to get >>64M regions
 214          * for graphics cards etc., but will not bother at this point.
 215          *
 216          * IP bug means that AMBA window size must be a power of 2
 217          *
 218          * Set mem0 window for first 16MB of outbound window non-prefetchable
 219          * Set mem1 window for second 16MB of outbound window prefetchable
 220          * Set io window for next 16MB of outbound window
 221          * Set cfg0 for final 1MB of outbound window
 222          *
 223          * Ignore mem1, cfg1 and msg windows for now as no obvious use cases for
 224          * 820 that would need them
 225          *
 226          * Probably ideally want no offset between mem0 window start as seen by
 227          * ARM and as seen on PCI bus and get Linux to assign memory regions to
 228          * PCI devices using the same "PCI client" region start address as seen
 229          * by ARM
 230          */
 231
 232         /* Set PCIeA mem0 region to be 1st 16MB of the 64MB PCIeA window */
 233         regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN0_MEM_ADDR, pcie->non_mem.start);
 234         regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN0_MEM_LIMIT, pcie->non_mem.end);
 235         regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_POM0_MEM_ADDR, pcie->non_mem.start);
 236
 237         /* Set PCIeA mem1 region to be 2nd 16MB of the 64MB PCIeA window */
 238         regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN1_MEM_ADDR, pcie->pre_mem.start);
 239         regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN1_MEM_LIMIT, pcie->pre_mem.end);
 240         regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_POM1_MEM_ADDR, pcie->pre_mem.start);
 241
 242         /* Set PCIeA io to be third 16M region of the 64MB PCIeA window*/
 243         regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_IO_ADDR, pcie->io.start);
 244         regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_IO_LIMIT, pcie->io.end);
 245
 246
 247         /* Set PCIeA cgf0 to be last 16M region of the 64MB PCIeA window*/
 248         regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_CFG0_ADDR, pcie->cfg.start);
 249         regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_CFG0_LIMIT, pcie->cfg.end);
 250         wmb();
 251
 252         /* Enable outbound address translation */
 253         regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset, PCIE_OBTRANS, PCIE_OBTRANS);
 254         wmb();
 255
 256         /*
 257          * Program PCIe command register for core to:
 258          *  enable memory space
 259          *  enable bus master
 260          *  enable io
 261          */
 262         writel_relaxed(7, pcie->base + PCI_CONFIG_COMMAND_STATUS);
 263         /* which is which */
 264         wmb();
 265 }
 266
 267 static unsigned oxnas_pcie_cfg_to_offset(
 268         struct pci_sys_data *sys,
 269         unsigned char bus_number,
 270         unsigned int devfn,
 271         int where)
 272 {
 273         unsigned int function = PCI_FUNC(devfn);
 274         unsigned int slot = PCI_SLOT(devfn);
 275         unsigned char bus_number_offset;
 276
 277         bus_number_offset = bus_number - sys->busnr;
 278
 279         /*
 280          * We'll assume for now that the offset, function, slot, bus encoding
 281          * should map onto linear, contiguous addresses in PCIe config space,
 282          * albeit that the majority will be unused as only slot 0 is valid for
 283          * any PCIe bus and most devices have only function 0
 284          *
 285          * Could be that PCIe in fact works by not encoding the slot number into
 286          * the config space address as it's known that only slot 0 is valid.
 287          * We'll have to experiment if/when we get a PCIe switch connected to
 288          * the PCIe host
 289          */
 290         return (bus_number_offset << 20) | (slot << 15) | (function << 12) |
 291                 (where & ~3);
 292 }
 293
 294 /* PCI configuration space write function */
 295 static int oxnas_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 296                               int where, int size, u32 val)
 297 {
 298         unsigned long flags;
 299         struct oxnas_pcie *pcie = sys_to_pcie(bus->sysdata);
 300         unsigned offset;
 301         u32 value;
 302         u32 lanes;
 303
 304         /* Only a single device per bus for PCIe point-to-point links */
 305         if (PCI_SLOT(devfn) > 0)
 306                 return PCIBIOS_DEVICE_NOT_FOUND;
 307
 308         if (!pcie->haslink)
 309                 return PCIBIOS_DEVICE_NOT_FOUND;
 310
 311         offset = oxnas_pcie_cfg_to_offset(bus->sysdata, bus->number, devfn,
 312                                           where);
 313
 314         value = val << (8 * (where & 3));
 315         lanes = (0xf >> (4-size)) << (where & 3);
 316         /* it race with mem and io write, but the possibility is low, normally
 317          * all config writes happens at driver initialize stage, wont interleave
 318          * with others.
 319          * and many pcie cards use dword (4bytes) access mem/io access only,
 320          * so not bother to copy that ugly work-around now. */
 321         spin_lock_irqsave(&pcie->lock, flags);
 322         set_out_lanes(pcie, lanes);
 323         writel_relaxed(value, pcie->cfgbase + offset);
 324         set_out_lanes(pcie, 0xf);
 325         spin_unlock_irqrestore(&pcie->lock, flags);
 326
 327         return PCIBIOS_SUCCESSFUL;
 328 }
 329
 330 /* PCI configuration space read function */
 331 static int oxnas_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 332                               int size, u32 *val)
 333 {
 334         struct oxnas_pcie *pcie = sys_to_pcie(bus->sysdata);
 335         unsigned offset;
 336         u32 value;
 337         u32 left_bytes, right_bytes;
 338
 339         /* Only a single device per bus for PCIe point-to-point links */
 340         if (PCI_SLOT(devfn) > 0) {
 341                 *val = 0xffffffff;
 342                 return PCIBIOS_DEVICE_NOT_FOUND;
 343         }
 344
 345         if (!pcie->haslink) {
 346                 *val = 0xffffffff;
 347                 return PCIBIOS_DEVICE_NOT_FOUND;
 348         }
 349
 350         offset = oxnas_pcie_cfg_to_offset(bus->sysdata, bus->number, devfn,
 351                                           where);
 352         value = readl_relaxed(pcie->cfgbase + offset);
 353         left_bytes = where & 3;
 354         right_bytes = 4 - left_bytes - size;
 355         value <<= right_bytes * 8;
 356         value >>= (left_bytes + right_bytes) * 8;
 357         *val = value;
 358
 359         return PCIBIOS_SUCCESSFUL;
 360 }
 361
 362 static struct pci_ops oxnas_pcie_ops = {
 363         .read = oxnas_pcie_rd_conf,
 364         .write = oxnas_pcie_wr_conf,
 365 };
 366
 367 static int oxnas_pcie_setup(int nr, struct pci_sys_data *sys)
 368 {
 369         struct oxnas_pcie *pcie = sys_to_pcie(sys);
 370
 371         pci_add_resource_offset(&sys->resources, &pcie->non_mem, sys->mem_offset);
 372         pci_add_resource_offset(&sys->resources, &pcie->pre_mem, sys->mem_offset);
 373         pci_add_resource_offset(&sys->resources, &pcie->io, sys->io_offset);
 374         pci_add_resource(&sys->resources, &pcie->busn);
 375         if (sys->busnr == 0) { /* default one */
 376                 sys->busnr = pcie->busn.start;
 377         }
 378         /* do not use devm_ioremap_resource, it does not like cfg resource */
 379         pcie->cfgbase = devm_ioremap(&pcie->pdev->dev, pcie->cfg.start,
 380                                      resource_size(&pcie->cfg));
 381         if (!pcie->cfgbase)
 382                 return -ENOMEM;
 383
 384         oxnas_pcie_setup_hw(pcie);
 385
 386         return 1;
 387 }
 388
 389 static void oxnas_pcie_enable(struct device *dev, struct oxnas_pcie *pcie)
 390 {
 391         struct hw_pci hw;
 392         int i;
 393
 394         memset(&hw, 0, sizeof(hw));
 395         for (i = 0; i < NUM_CONTROLLERS; i++)
 396                 pcie->private_data[i] = pcie;
 397
 398         hw.nr_controllers = NUM_CONTROLLERS;
 399 /* I think use stack pointer is a bad idea though it is valid in this case */
 400         hw.private_data   = pcie->private_data;
 401         hw.setup          = oxnas_pcie_setup;
 402         hw.map_irq        = of_irq_parse_and_map_pci;
 403         hw.ops            = &oxnas_pcie_ops;
 404
 405         /* pass dev to maintain of tree, interrupt mapping rely on this */
 406         pci_common_init_dev(dev, &hw);
 407 }
 408
 409 void oxnas_pcie_init_shared_hw(struct platform_device *pdev,
 410                                void __iomem *phybase,
 411                                struct regmap *sys_ctrl)
 412 {
 413         struct reset_control *rstc;
 414         int ret;
 415
 416         /* generate clocks from HCSL buffers, shared parts */
 417         regmap_write(sys_ctrl, SYS_CTRL_HCSL_CTRL_REGOFFSET, HCSL_BIAS_ON|HCSL_PCIE_EN);
 418
 419         /* Ensure PCIe PHY is properly reset */
 420         rstc = reset_control_get(&pdev->dev, "phy");
 421         if (IS_ERR(rstc)) {
 422                 ret = PTR_ERR(rstc);
 423         } else {
 424                 ret = reset_control_reset(rstc);
 425                 reset_control_put(rstc);
 426         }
 427
 428         if (ret) {
 429                 dev_err(&pdev->dev, "phy reset failed %d\n", ret);
 430                 return;
 431         }
 432
 433         /* Enable PCIe Pre-Emphasis: What these value means? */
 434         writel(ADDR_VAL(0x0014), phybase + PHY_ADDR);
 435         writel(DATA_VAL(0xce10) | CAP_DATA, phybase + PHY_DATA);
 436         writel(DATA_VAL(0xce10) | WRITE_EN, phybase + PHY_DATA);
 437
 438         writel(ADDR_VAL(0x2004), phybase + PHY_ADDR);
 439         writel(DATA_VAL(0x82c7) | CAP_DATA, phybase + PHY_DATA);
 440         writel(DATA_VAL(0x82c7) | WRITE_EN, phybase + PHY_DATA);
 441 }
 442
 443 static int oxnas_pcie_shared_init(struct platform_device *pdev, struct regmap *sys_ctrl)
 444 {
 445         if (++pcie_shared.refcount == 1) {
 446                 /* we are the first */
 447                 struct device_node *np = pdev->dev.of_node;
 448                 void __iomem *phy = of_iomap(np, 2);
 449                 if (!phy) {
 450                         --pcie_shared.refcount;
 451                         return -ENOMEM;
 452                 }
 453                 oxnas_pcie_init_shared_hw(pdev, phy, sys_ctrl);
 454                 iounmap(phy);
 455                 return 0;
 456         } else {
 457                 return 0;
 458         }
 459 }
 460
 461 #if 0
 462 /* maybe we will call it when enter low power state */
 463 static void oxnas_pcie_shared_deinit(struct platform_device *pdev)
 464 {
 465         if (--pcie_shared.refcount == 0) {
 466                 /* no cleanup needed */;
 467         }
 468 }
 469 #endif
 470
 471 static int
 472 oxnas_pcie_map_registers(struct platform_device *pdev,
 473                          struct device_node *np,
 474                          struct oxnas_pcie *pcie)
 475 {
 476         struct resource regs;
 477         int ret = 0;
 478         u32 outbound_ctrl_offset;
 479         u32 pcie_ctrl_offset;
 480
 481         /* 2 is reserved for shared phy */
 482         ret = of_address_to_resource(np, 0, &regs);
 483         if (ret)
 484                 return -EINVAL;
 485         pcie->base = devm_ioremap_resource(&pdev->dev, &regs);
 486         if (!pcie->base)
 487                 return -ENOMEM;
 488
 489         ret = of_address_to_resource(np, 1, &regs);
 490         if (ret)
 491                 return -EINVAL;
 492         pcie->inbound = devm_ioremap_resource(&pdev->dev, &regs);
 493         if (!pcie->inbound)
 494                 return -ENOMEM;
 495
 496
 497         if (of_property_read_u32(np, "plxtech,pcie-outbound-offset",
 498                                  &outbound_ctrl_offset))
 499                 return -EINVAL;
 500         pcie->outbound_offset = outbound_ctrl_offset;
 501
 502         if (of_property_read_u32(np, "plxtech,pcie-ctrl-offset",
 503                                  &pcie_ctrl_offset))
 504                 return -EINVAL;
 505         pcie->pcie_ctrl_offset = pcie_ctrl_offset;
 506
 507         return 0;
 508 }
 509
 510 static int oxnas_pcie_init_res(struct platform_device *pdev,
 511                                       struct oxnas_pcie *pcie,
 512                                       struct device_node *np)
 513 {
 514         struct of_pci_range range;
 515         struct of_pci_range_parser parser;
 516         int ret;
 517
 518         if (of_pci_range_parser_init(&parser, np))
 519                 return -EINVAL;
 520
 521         /* Get the I/O and memory ranges from DT */
 522         for_each_of_pci_range(&parser, &range) {
 523
 524                 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
 525                 if (restype == IORESOURCE_IO) {
 526                         of_pci_range_to_resource(&range, np, &pcie->io);
 527                         pcie->io.name = "I/O";
 528                 }
 529                 if (restype == IORESOURCE_MEM) {
 530                         if (range.flags & IORESOURCE_PREFETCH) {
 531                                 of_pci_range_to_resource(&range, np, &pcie->pre_mem);
 532                                 pcie->pre_mem.name = "PRE MEM";
 533                         } else {
 534                                 of_pci_range_to_resource(&range, np, &pcie->non_mem);
 535                                 pcie->non_mem.name = "NON MEM";
 536                         }
 537
 538                 }
 539                 if (restype == 0)
 540                         of_pci_range_to_resource(&range, np, &pcie->cfg);
 541         }
 542
 543         /* Get the bus range */
 544         ret = of_pci_parse_bus_range(np, &pcie->busn);
 545
 546         if (ret) {
 547                 dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
 548                         ret);
 549                 return ret;
 550         }
 551
 552         pcie->card_reset = of_get_gpio(np, 0);
 553         if (pcie->card_reset < 0)
 554                 dev_info(&pdev->dev, "card reset gpio pin not exists\n");
 555
 556         if (of_property_read_u32(np, "plxtech,pcie-hcsl-bit", &pcie->hcsl_en))
 557                 return -EINVAL;
 558
 559         pcie->clk = of_clk_get_by_name(np, "pcie");
 560         if (IS_ERR(pcie->clk)) {
 561                 return PTR_ERR(pcie->clk);
 562         }
 563
 564         pcie->busclk = of_clk_get_by_name(np, "busclk");
 565         if (IS_ERR(pcie->busclk)) {
 566                 clk_put(pcie->clk);
 567                 return PTR_ERR(pcie->busclk);
 568         }
 569
 570         return 0;
 571 }
 572
 573 static void oxnas_pcie_init_hw(struct platform_device *pdev,
 574                                struct oxnas_pcie *pcie)
 575 {
 576         u32 version_id;
 577         int ret;
 578
 579         clk_prepare_enable(pcie->busclk);
 580
 581         /* reset PCIe cards use hard-wired gpio pin */
 582         if (pcie->card_reset >= 0 &&
 583             !gpio_direction_output(pcie->card_reset, 0)) {
 584                 wmb();
 585                 mdelay(10);
 586                 /* must tri-state the pin to pull it up */
 587                 gpio_direction_input(pcie->card_reset);
 588                 wmb();
 589                 mdelay(100);
 590         }
 591
 592         regmap_update_bits(pcie->sys_ctrl, SYS_CTRL_HCSL_CTRL_REGOFFSET,
 593                            BIT(pcie->hcsl_en), BIT(pcie->hcsl_en));
 594
 595         /* core */
 596         ret = device_reset(&pdev->dev);
 597         if (ret) {
 598                 dev_err(&pdev->dev, "core reset failed %d\n", ret);
 599                 return;
 600         }
 601
 602         /* Start PCIe core clocks */
 603         clk_prepare_enable(pcie->clk);
 604
 605         version_id = readl_relaxed(pcie->base + PCI_CONFIG_VERSION_DEVICEID);
 606         dev_info(&pdev->dev, "PCIe version/deviceID 0x%x\n", version_id);
 607
 608         if (version_id != VERSION_ID_MAGIC) {
 609                 dev_info(&pdev->dev, "PCIe controller not found\n");
 610                 pcie->haslink = 0;
 611                 return;
 612         }
 613
 614         /* allow entry to L23 state */
 615         regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset,
 616                           PCIE_READY_ENTR_L23, PCIE_READY_ENTR_L23);
 617
 618         /* Set PCIe core into RootCore mode */
 619         regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset,
 620                           PCIE_DEVICE_TYPE_MASK, PCIE_DEVICE_TYPE_ROOT);
 621         wmb();
 622
 623         /* Bring up the PCI core */
 624         regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset,
 625                           PCIE_LTSSM, PCIE_LTSSM);
 626         wmb();
 627 }
 628
 629 static int oxnas_pcie_probe(struct platform_device *pdev)
 630 {
 631         struct oxnas_pcie *pcie;
 632         struct device_node *np = pdev->dev.of_node;
 633         int ret;
 634
 635         pcie = devm_kzalloc(&pdev->dev, sizeof(struct oxnas_pcie),
 636                             GFP_KERNEL);
 637         if (!pcie)
 638                 return -ENOMEM;
 639
 640         pcie->pdev = pdev;
 641         pcie->haslink = 1;
 642         spin_lock_init(&pcie->lock);
 643
 644         pcie->sys_ctrl = syscon_regmap_lookup_by_compatible("oxsemi,ox820-sys-ctrl");
 645         if (IS_ERR(pcie->sys_ctrl))
 646                 return PTR_ERR(pcie->sys_ctrl);
 647
 648         ret = oxnas_pcie_init_res(pdev, pcie, np);
 649         if (ret)
 650                 return ret;
 651         if (pcie->card_reset >= 0) {
 652                 ret = gpio_request_one(pcie->card_reset, GPIOF_DIR_IN,
 653                                        dev_name(&pdev->dev));
 654                 if (ret) {
 655                         dev_err(&pdev->dev, "cannot request gpio pin %d\n",
 656                                 pcie->card_reset);
 657                         return ret;
 658                 }
 659         }
 660
 661         ret = oxnas_pcie_map_registers(pdev, np, pcie);
 662         if (ret) {
 663                 dev_err(&pdev->dev, "cannot map registers\n");
 664                 goto err_free_gpio;
 665         }
 666
 667         ret = oxnas_pcie_shared_init(pdev, pcie->sys_ctrl);
 668         if (ret)
 669                 goto err_free_gpio;
 670
 671         /* if hw not found, haslink cleared */
 672         oxnas_pcie_init_hw(pdev, pcie);
 673
 674         if (pcie->haslink && oxnas_pcie_link_up(pcie)) {
 675                 pcie->haslink = 1;
 676                 dev_info(&pdev->dev, "link up\n");
 677         } else {
 678                 pcie->haslink = 0;
 679                 dev_info(&pdev->dev, "link down\n");
 680         }
 681         /* should we register our controller even when pcie->haslink is 0 ? */
 682         /* register the controller with framework */
 683         oxnas_pcie_enable(&pdev->dev, pcie);
 684
 685         return 0;
 686
 687 err_free_gpio:
 688         if (pcie->card_reset)
 689                 gpio_free(pcie->card_reset);
 690
 691         return ret;
 692 }
 693
 694 static const struct of_device_id oxnas_pcie_of_match_table[] = {
 695         { .compatible = "plxtech,nas782x-pcie", },
 696         {},
 697 };
 698
 699 static struct platform_driver oxnas_pcie_driver = {
 700         .driver = {
 701                 .name = "oxnas-pcie",
 702                 .suppress_bind_attrs = true,
 703                 .of_match_table = oxnas_pcie_of_match_table,
 704         },
 705         .probe = oxnas_pcie_probe,
 706 };
 707
 708 builtin_platform_driver(oxnas_pcie_driver);