kernel: backport upstream commit to fix MIPS cache shift with secondary cache enabled
authorFelix Fietkau <nbd@openwrt.org>
Sun, 18 Jan 2015 09:25:27 +0000 (09:25 +0000)
committerFelix Fietkau <nbd@openwrt.org>
Sun, 18 Jan 2015 09:25:27 +0000 (09:25 +0000)
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 44024

target/linux/generic/patches-3.14/010-MIPS-Allow-MIPS_CPU_SCACHE-to-be-used-with-different.patch [new file with mode: 0644]
target/linux/generic/patches-3.14/132-mips_inline_dma_ops.patch
target/linux/generic/patches-3.14/301-mips_image_cmdline_hack.patch
target/linux/generic/patches-3.14/304-mips_disable_fpu.patch

diff --git a/target/linux/generic/patches-3.14/010-MIPS-Allow-MIPS_CPU_SCACHE-to-be-used-with-different.patch b/target/linux/generic/patches-3.14/010-MIPS-Allow-MIPS_CPU_SCACHE-to-be-used-with-different.patch
new file mode 100644 (file)
index 0000000..f5cdc6d
--- /dev/null
@@ -0,0 +1,42 @@
+From a7ef1eaddbf4bd50bfee92d9dfbecadc61467bbf Mon Sep 17 00:00:00 2001
+From: Kevin Cernekee <cernekee@gmail.com>
+Date: Mon, 20 Oct 2014 21:27:57 -0700
+Subject: [PATCH] MIPS: Allow MIPS_CPU_SCACHE to be used with different line
+ sizes
+
+CONFIG_MIPS_CPU_SCACHE determines whether to build sc-mips.c.  However,
+it is currently hardwired to use an L1_SHIFT of 6 (64 bytes).  Move the
+L1_SHIFT selection into the CPU or SoC section so that other SoCs can
+select different values.
+
+Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
+Cc: f.fainelli@gmail.com
+Cc: mbizon@freebox.fr
+Cc: jogo@openwrt.org
+Cc: jfraser@broadcom.com
+Cc: linux-mips@linux-mips.org
+Cc: devicetree@vger.kernel.org
+Patchwork: https://patchwork.linux-mips.org/patch/8162/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -315,6 +315,7 @@ config MIPS_MALTA
+       select I8259
+       select MIPS_BONITO64
+       select MIPS_CPU_SCACHE
++      select MIPS_L1_CACHE_SHIFT_6
+       select PCI_GT64XXX_PCI0
+       select MIPS_MSC
+       select SWAP_IO_SPACE
+@@ -1820,7 +1821,6 @@ config IP22_CPU_SCACHE
+ config MIPS_CPU_SCACHE
+       bool
+       select BOARD_SCACHE
+-      select MIPS_L1_CACHE_SHIFT_6
+ config R5000_CPU_SCACHE
+       bool
index e43de025e6acaca04f2cead812393d4e50a64a03..e8486c9a4719bda7249506ab2cb72953a5c8025c 100644 (file)
@@ -19,7 +19,7 @@ Signed-off-by: Felix Fietkau <nbd@openwrt.org>
 
 --- a/arch/mips/Kconfig
 +++ b/arch/mips/Kconfig
-@@ -1620,6 +1620,9 @@ config SYS_HAS_CPU_XLR
+@@ -1621,6 +1621,9 @@ config SYS_HAS_CPU_XLR
  config SYS_HAS_CPU_XLP
        bool
  
@@ -510,7 +510,7 @@ Signed-off-by: Felix Fietkau <nbd@openwrt.org>
  
  
  void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr,
-@@ -159,8 +137,8 @@ void dma_free_noncoherent(struct device
+@@ -159,8 +137,8 @@ void dma_free_noncoherent(struct device 
  }
  EXPORT_SYMBOL(dma_free_noncoherent);
  
@@ -650,7 +650,7 @@ Signed-off-by: Felix Fietkau <nbd@openwrt.org>
  
  void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
                         enum dma_data_direction direction)
-@@ -347,23 +225,10 @@ void dma_cache_sync(struct device *dev,
+@@ -347,23 +225,10 @@ void dma_cache_sync(struct device *dev, 
  
  EXPORT_SYMBOL(dma_cache_sync);
  
index 38574386163237dcba35f3f710a937c56c80d48d..7f1b6bcc314caffff64ce7219b7f1b0059eb4f4d 100644 (file)
@@ -1,6 +1,6 @@
 --- a/arch/mips/Kconfig
 +++ b/arch/mips/Kconfig
-@@ -946,6 +946,10 @@ config SYNC_R4K
+@@ -947,6 +947,10 @@ config SYNC_R4K
  config MIPS_MACHINE
        def_bool n
  
index 4536ce6dae80710e530dd7c67c8c8728f95ee3e6..adc934642a936d9e4cae5218af573ef432e02f53 100644 (file)
@@ -8,7 +8,7 @@ Signed-off-by: Florian Fainelli <florian@openwrt.org>
 --
 --- a/arch/mips/Kconfig
 +++ b/arch/mips/Kconfig
-@@ -934,6 +934,17 @@ config I8259
+@@ -935,6 +935,17 @@ config I8259
  config MIPS_BONITO64
        bool