projects / openwrt / staging / mkresin.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
bugfix for the rb532 block2mtd code
[openwrt/staging/mkresin.git] / openwrt / target / linux / rb532-2.6 / patches / 100-rb5xx_support.patch
1 diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig
2 --- linux.old/arch/mips/Kconfig 2006-07-29 19:53:20.000000000 +0200
3 +++ linux.dev/arch/mips/Kconfig 2006-07-29 19:31:51.000000000 +0200
4 @@ -742,6 +742,19 @@
5 select SYS_SUPPORTS_BIG_ENDIAN
6 select TOSHIBA_BOARDS
7
8 +config MIKROTIK_RB500
9 + bool "Support for RB5xx boards"
10 + select HW_HAS_PCI
11 + select IRQ_CPU
12 + select SYS_HAS_CPU_MIPS32_R1
13 + select SYS_SUPPORTS_LITTLE_ENDIAN
14 + select SYS_SUPPORTS_32BIT_KERNEL
15 + select SWAP_IO_SPACE
16 + select DMA_NONCOHERENT
17 + help
18 + Support the Mikrotik(tm) Routerboard 500 series,
19 + such as the RB532.
20 +
21 config TOSHIBA_RBTX4927
22 bool "Toshiba TBTX49[23]7 board"
23 select DMA_NONCOHERENT
24 @@ -1028,7 +1041,7 @@
25
26 config MIPS_L1_CACHE_SHIFT
27 int
28 - default "4" if MACH_DECSTATION
29 + default "4" if MACH_DECSTATION || MIKROTIK_RB500
30 default "7" if SGI_IP27
31 default "5"
32
33 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
34 --- linux.old/arch/mips/Makefile 2006-07-29 19:53:20.000000000 +0200
35 +++ linux.dev/arch/mips/Makefile 2006-07-29 19:31:51.000000000 +0200
36 @@ -580,6 +580,13 @@
37 load-$(CONFIG_TOSHIBA_JMR3927) += 0xffffffff80050000
38
39 #
40 +# Routerboard 532 board
41 +#
42 +core-$(CONFIG_MIKROTIK_RB500) += arch/mips/rb500/
43 +cflags-$(CONFIG_MIKROTIK_RB500) += -Iinclude/asm-mips/rc32434
44 +load-$(CONFIG_MIKROTIK_RB500) += 0xffffffff80101000
45 +
46 +#
47 # Toshiba RBTX4927 board or
48 # Toshiba RBTX4937 board
49 #
50 diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
51 --- linux.old/arch/mips/mm/tlbex.c 2006-07-29 19:53:20.000000000 +0200
52 +++ linux.dev/arch/mips/mm/tlbex.c 2006-07-29 19:31:51.000000000 +0200
53 @@ -876,7 +876,6 @@
54 case CPU_R10000:
55 case CPU_R12000:
56 case CPU_R14000:
57 - case CPU_4KC:
58 case CPU_SB1:
59 case CPU_SB1A:
60 case CPU_4KSC:
61 @@ -904,6 +903,7 @@
62 tlbw(p);
63 break;
64
65 + case CPU_4KC:
66 case CPU_4KEC:
67 case CPU_24K:
68 case CPU_34K:
69 diff -urN linux.old/arch/mips/pci/fixup-rb500.c linux.dev/arch/mips/pci/fixup-rb500.c
70 --- linux.old/arch/mips/pci/fixup-rb500.c 1970-01-01 01:00:00.000000000 +0100
71 +++ linux.dev/arch/mips/pci/fixup-rb500.c 2006-07-29 19:31:51.000000000 +0200
72 @@ -0,0 +1,49 @@
73 +/*
74 + * Copyright 2001 MontaVista Software Inc.
75 + * Author: MontaVista Software, Inc.
76 + * stevel@mvista.com or source@mvista.com
77 + *
78 + * This program is free software; you can redistribute it and/or modify it
79 + * under the terms of the GNU General Public License as published by the
80 + * Free Software Foundation; either version 2 of the License, or (at your
81 + * option) any later version.
82 + *
83 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
84 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
85 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
86 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
87 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
88 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
89 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
90 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
91 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
92 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
93 + *
94 + * You should have received a copy of the GNU General Public License along
95 + * with this program; if not, write to the Free Software Foundation, Inc.,
96 + * 675 Mass Ave, Cambridge, MA 02139, USA.
97 + */
98 +
99 +#include <linux/config.h>
100 +#include <linux/types.h>
101 +#include <linux/pci.h>
102 +#include <linux/kernel.h>
103 +#include <linux/init.h>
104 +
105 +#include <asm/rc32434/rc32434.h>
106 +
107 +static int __devinitdata irq_map[2][12] = {
108 + { 0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1 },
109 + { 0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3 }
110 +};
111 +
112 +int __devinit pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
113 +{
114 + int irq = 0;
115 +
116 + if (dev->bus->number < 2 && PCI_SLOT(dev->devfn) < 12) {
117 + irq = irq_map[dev->bus->number][PCI_SLOT(dev->devfn)];
118 + }
119 + return irq + GROUP4_IRQ_BASE + 4;
120 +}
121 +
122 diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
123 --- linux.old/arch/mips/pci/Makefile 2006-07-29 19:53:20.000000000 +0200
124 +++ linux.dev/arch/mips/pci/Makefile 2006-07-29 19:31:51.000000000 +0200
125 @@ -57,3 +57,4 @@
126 obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o
127 obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
128 obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
129 +obj-$(CONFIG_MIKROTIK_RB500) += pci-rc32434.o ops-rc32434.o fixup-rb500.o
130 diff -urN linux.old/arch/mips/pci/ops-rc32434.c linux.dev/arch/mips/pci/ops-rc32434.c
131 --- linux.old/arch/mips/pci/ops-rc32434.c 1970-01-01 01:00:00.000000000 +0100
132 +++ linux.dev/arch/mips/pci/ops-rc32434.c 2006-07-29 19:31:51.000000000 +0200
133 @@ -0,0 +1,195 @@
134 +/**************************************************************************
135 + *
136 + * BRIEF MODULE DESCRIPTION
137 + * pci_ops for IDT EB434 board
138 + *
139 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
140 + *
141 + * This program is free software; you can redistribute it and/or modify it
142 + * under the terms of the GNU General Public License as published by the
143 + * Free Software Foundation; either version 2 of the License, or (at your
144 + * option) any later version.
145 + *
146 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
147 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
148 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
149 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
150 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
151 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
152 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
153 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
154 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
155 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
156 + *
157 + * You should have received a copy of the GNU General Public License along
158 + * with this program; if not, write to the Free Software Foundation, Inc.,
159 + * 675 Mass Ave, Cambridge, MA 02139, USA.
160 + *
161 + *
162 + **************************************************************************
163 + * May 2004 rkt, neb
164 + *
165 + * Initial Release
166 + *
167 + *
168 + *
169 + **************************************************************************
170 + */
171 +
172 +#include <linux/config.h>
173 +#include <linux/init.h>
174 +#include <linux/pci.h>
175 +#include <linux/types.h>
176 +#include <linux/delay.h>
177 +
178 +#include <asm/cpu.h>
179 +#include <asm/io.h>
180 +
181 +#include <asm/rc32434/rc32434.h>
182 +#include <asm/rc32434/pci.h>
183 +
184 +#define PCI_ACCESS_READ 0
185 +#define PCI_ACCESS_WRITE 1
186 +
187 +
188 +#define PCI_CFG_SET(bus,slot,func,off) \
189 + (rc32434_pci->pcicfga = (0x80000000 | \
190 + ((bus) << 16) | ((slot)<<11) | \
191 + ((func)<<8) | (off)))
192 +
193 +static inline int config_access(unsigned char access_type, struct pci_bus *bus,
194 + unsigned int devfn, unsigned char where,
195 + u32 * data)
196 +{
197 + unsigned int slot = PCI_SLOT(devfn);
198 + u8 func = PCI_FUNC(devfn);
199 +
200 + /* Setup address */
201 + PCI_CFG_SET(bus->number, slot, func, where);
202 + rc32434_sync();
203 +
204 + if (access_type == PCI_ACCESS_WRITE)
205 + rc32434_pci->pcicfgd = *data;
206 + else
207 + *data = rc32434_pci->pcicfgd;
208 +
209 + rc32434_sync();
210 +
211 + return 0;
212 +}
213 +
214 +
215 +/*
216 + * We can't address 8 and 16 bit words directly. Instead we have to
217 + * read/write a 32bit word and mask/modify the data we actually want.
218 + */
219 +static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
220 + int where, u8 * val)
221 +{
222 + u32 data;
223 + int ret;
224 +
225 + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
226 + *val = (data >> ((where & 3) << 3)) & 0xff;
227 + return ret;
228 +}
229 +
230 +static int read_config_word(struct pci_bus *bus, unsigned int devfn,
231 + int where, u16 * val)
232 +{
233 + u32 data;
234 + int ret;
235 +
236 + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
237 + *val = (data >> ((where & 3) << 3)) & 0xffff;
238 + return ret;
239 +}
240 +
241 +static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
242 + int where, u32 * val)
243 +{
244 + int ret;
245 +
246 + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
247 + return ret;
248 +}
249 +
250 +static int
251 +write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
252 + u8 val)
253 +{
254 + u32 data = 0;
255 +
256 + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
257 + return -1;
258 +
259 + data = (data & ~(0xff << ((where & 3) << 3))) |
260 + (val << ((where & 3) << 3));
261 +
262 + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
263 + return -1;
264 +
265 + return PCIBIOS_SUCCESSFUL;
266 +}
267 +
268 +
269 +static int
270 +write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
271 + u16 val)
272 +{
273 + u32 data = 0;
274 +
275 + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
276 + return -1;
277 +
278 + data = (data & ~(0xffff << ((where & 3) << 3))) |
279 + (val << ((where & 3) << 3));
280 +
281 + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
282 + return -1;
283 +
284 +
285 + return PCIBIOS_SUCCESSFUL;
286 +}
287 +
288 +
289 +static int
290 +write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
291 + u32 val)
292 +{
293 + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
294 + return -1;
295 +
296 + return PCIBIOS_SUCCESSFUL;
297 +}
298 +
299 +static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
300 + int where, int size, u32 * val)
301 +{
302 + switch (size) {
303 + case 1:
304 + return read_config_byte(bus, devfn, where, (u8 *) val);
305 + case 2:
306 + return read_config_word(bus, devfn, where, (u16 *) val);
307 + default:
308 + return read_config_dword(bus, devfn, where, val);
309 + }
310 +}
311 +
312 +static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
313 + int where, int size, u32 val)
314 +{
315 + switch (size) {
316 + case 1:
317 + return write_config_byte(bus, devfn, where, (u8) val);
318 + case 2:
319 + return write_config_word(bus, devfn, where, (u16) val);
320 + default:
321 + return write_config_dword(bus, devfn, where, val);
322 + }
323 +}
324 +
325 +struct pci_ops rc32434_pci_ops = {
326 + .read = pci_config_read,
327 + .write = pci_config_write,
328 +};
329 diff -urN linux.old/arch/mips/pci/pci-rc32434.c linux.dev/arch/mips/pci/pci-rc32434.c
330 --- linux.old/arch/mips/pci/pci-rc32434.c 1970-01-01 01:00:00.000000000 +0100
331 +++ linux.dev/arch/mips/pci/pci-rc32434.c 2006-07-29 19:31:51.000000000 +0200
332 @@ -0,0 +1,234 @@
333 +/**************************************************************************
334 + *
335 + * BRIEF MODULE DESCRIPTION
336 + * PCI initialization for IDT EB434 board
337 + *
338 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
339 + *
340 + * This program is free software; you can redistribute it and/or modify it
341 + * under the terms of the GNU General Public License as published by the
342 + * Free Software Foundation; either version 2 of the License, or (at your
343 + * option) any later version.
344 + *
345 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
346 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
347 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
348 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
349 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
350 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
351 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
352 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
353 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
354 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
355 + *
356 + * You should have received a copy of the GNU General Public License along
357 + * with this program; if not, write to the Free Software Foundation, Inc.,
358 + * 675 Mass Ave, Cambridge, MA 02139, USA.
359 + *
360 + *
361 + **************************************************************************
362 + * May 2004 rkt, neb
363 + *
364 + * Initial Release
365 + *
366 + *
367 + *
368 + **************************************************************************
369 + */
370 +
371 +#include <linux/config.h>
372 +#include <linux/types.h>
373 +#include <linux/pci.h>
374 +#include <linux/kernel.h>
375 +#include <linux/init.h>
376 +
377 +#include <asm/rc32434/rc32434.h>
378 +#include <asm/rc32434/pci.h>
379 +
380 +#define PCI_ACCESS_READ 0
381 +#define PCI_ACCESS_WRITE 1
382 +
383 +/* define an unsigned array for the PCI registers */
384 +unsigned int korinaCnfgRegs[25] = {
385 + KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4,
386 + KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8,
387 + KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
388 + KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
389 + KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
390 + KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
391 +};
392 +static struct resource rc32434_res_pci_mem1;
393 +static struct resource rc32434_res_pci_mem2;
394 +
395 +static struct resource rc32434_res_pci_mem1 = {
396 + .name = "PCI MEM1",
397 + .start = 0x50000000,
398 + .end = 0x5FFFFFFF,
399 + .flags = IORESOURCE_MEM,
400 + .parent = &rc32434_res_pci_mem1,
401 + .sibling = NULL,
402 + .child = &rc32434_res_pci_mem2
403 +};
404 +
405 +static struct resource rc32434_res_pci_mem2 = {
406 + .name = "PCI Mem2",
407 + .start = 0x60000000,
408 + .end = 0x6FFFFFFF,
409 + .flags = IORESOURCE_MEM,
410 + .parent = &rc32434_res_pci_mem1,
411 + .sibling = NULL,
412 + .child = NULL
413 +};
414 +
415 +static struct resource rc32434_res_pci_io1 = {
416 + .name = "PCI I/O1",
417 + .start = 0x18800000,
418 + .end = 0x188FFFFF,
419 + .flags = IORESOURCE_IO,
420 +};
421 +
422 +extern struct pci_ops rc32434_pci_ops;
423 +
424 +#define PCI_MEM1_START PCI_ADDR_START
425 +#define PCI_MEM1_END PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1
426 +#define PCI_MEM2_START PCI_ADDR_START + CPUTOPCI_MEM_WIN
427 +#define PCI_MEM2_END PCI_ADDR_START + ( 2* CPUTOPCI_MEM_WIN) - 1
428 +#define PCI_IO1_START PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN)
429 +#define PCI_IO1_END PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN -1
430 +#define PCI_IO2_START PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN
431 +#define PCI_IO2_END PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) -1
432 +
433 +
434 +struct pci_controller rc32434_controller2;
435 +
436 +struct pci_controller rc32434_controller = {
437 + .pci_ops = &rc32434_pci_ops,
438 + .mem_resource = &rc32434_res_pci_mem1,
439 + .io_resource = &rc32434_res_pci_io1,
440 + .mem_offset = 0,
441 + .io_offset = 0,
442 +
443 +};
444 +
445 +#ifdef __MIPSEB__
446 +#define PCI_ENDIAN_FLAG PCILBAC_sb_m
447 +#else
448 +#define PCI_ENDIAN_FLAG 0
449 +#endif
450 +
451 +static int __init rc32434_pcibridge_init(void)
452 +{
453 + unsigned int pcicValue, pcicData = 0;
454 + unsigned int dummyRead, pciCntlVal;
455 + int loopCount;
456 + unsigned int pciConfigAddr;
457 +
458 + pcicValue = rc32434_pci->pcic;
459 + pcicValue = (pcicValue >> PCIM_SHFT) & PCIM_BIT_LEN;
460 + if (!((pcicValue == PCIM_H_EA) ||
461 + (pcicValue == PCIM_H_IA_FIX) ||
462 + (pcicValue == PCIM_H_IA_RR))) {
463 + printk("PCI init error!!!\n");
464 + /* Not in Host Mode, return ERROR */
465 + return -1;
466 + }
467 + /* Enables the Idle Grant mode, Arbiter Parking */
468 + pcicData |=(PCIC_igm_m|PCIC_eap_m|PCIC_en_m);
469 + rc32434_pci->pcic = pcicData; /* Enable the PCI bus Interface */
470 + /* Zero out the PCI status & PCI Status Mask */
471 + for(;;)
472 + {
473 + pcicData = rc32434_pci->pcis;
474 + if (!(pcicData & PCIS_rip_m))
475 + break;
476 + }
477 +
478 + rc32434_pci->pcis = 0;
479 + rc32434_pci->pcism = 0xFFFFFFFF;
480 + /* Zero out the PCI decoupled registers */
481 + rc32434_pci->pcidac=0; /* disable PCI decoupled accesses at initialization */
482 + rc32434_pci->pcidas=0; /* clear the status */
483 + rc32434_pci->pcidasm=0x0000007F; /* Mask all the interrupts */
484 + /* Mask PCI Messaging Interrupts */
485 + rc32434_pci_msg->pciiic = 0;
486 + rc32434_pci_msg->pciiim = 0xFFFFFFFF;
487 + rc32434_pci_msg->pciioic = 0;
488 + rc32434_pci_msg->pciioim = 0;
489 +
490 +
491 + /* Setup PCILB0 as Memory Window */
492 + rc32434_pci->pcilba[0].a = (unsigned int) (PCI_ADDR_START);
493 +
494 + /* setup the PCI map address as same as the local address */
495 +
496 + rc32434_pci->pcilba[0].m = (unsigned int) (PCI_ADDR_START);
497 +
498 +
499 + /* Setup PCILBA1 as MEM */
500 + rc32434_pci->pcilba[0].c = ( ((SIZE_256MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG);
501 + dummyRead = rc32434_pci->pcilba[0].c; /* flush the CPU write Buffers */
502 + rc32434_pci->pcilba[1].a = 0x60000000;
503 + rc32434_pci->pcilba[1].m = 0x60000000;
504 +
505 + /* setup PCILBA2 as IO Window*/
506 + rc32434_pci->pcilba[1].c = (((SIZE_256MB & 0x1f) << PCILBAC_size_b )| PCI_ENDIAN_FLAG);
507 + dummyRead = rc32434_pci->pcilba[1].c; /* flush the CPU write Buffers */
508 + rc32434_pci->pcilba[2].a = 0x18C00000;
509 + rc32434_pci->pcilba[2].m = 0x18FFFFFF;
510 +
511 + /* setup PCILBA2 as IO Window*/
512 + rc32434_pci->pcilba[2].c = (((SIZE_4MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG );
513 + dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */
514 +
515 + /* Setup PCILBA3 as IO Window */
516 + rc32434_pci->pcilba[3].a = 0x18800000;
517 + rc32434_pci->pcilba[3].m = 0x18800000;
518 + rc32434_pci->pcilba[3].c = ( (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m) | PCI_ENDIAN_FLAG);
519 + dummyRead = rc32434_pci->pcilba[3].c; /* flush the CPU write Buffers */
520 +
521 + pciConfigAddr=(unsigned int)(0x80000004);
522 + for(loopCount=0;loopCount<24;loopCount++){
523 + rc32434_pci->pcicfga=pciConfigAddr;
524 + dummyRead=rc32434_pci->pcicfga;
525 + rc32434_pci->pcicfgd = korinaCnfgRegs[loopCount];
526 + dummyRead=rc32434_pci->pcicfgd;
527 + pciConfigAddr += 4;
528 + }
529 + rc32434_pci->pcitc = (unsigned int)((PCITC_RTIMER_VAL&0xff) << PCITC_rtimer_b)
530 + | ((PCITC_DTIMER_VAL&0xff) << PCITC_dtimer_b);
531 +
532 + pciCntlVal=rc32434_pci->pcic;
533 + pciCntlVal &=~(PCIC_tnr_m);
534 + rc32434_pci->pcic = pciCntlVal;
535 + pciCntlVal=rc32434_pci->pcic;
536 + return 0;
537 +}
538 +
539 +/* Do platform specific device initialization at pci_enable_device() time */
540 +int pcibios_plat_dev_init(struct pci_dev *dev)
541 +{
542 + if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) {
543 + /* disable prefetched memory range */
544 + pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
545 + pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
546 +
547 + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
548 + }
549 + return 0;
550 +}
551 +
552 +static int __init rc32434_pci_init(void)
553 +{
554 + printk("PCI: Initializing PCI\n");
555 +
556 + ioport_resource.start = rc32434_res_pci_io1.start;
557 + ioport_resource.end = rc32434_res_pci_io1.end;
558 +
559 + rc32434_pcibridge_init();
560 +
561 + register_pci_controller(&rc32434_controller);
562 + rc32434_sync();
563 +}
564 +
565 +arch_initcall(rc32434_pci_init);
566 +
567 diff -urN linux.old/arch/mips/rb500/devices.c linux.dev/arch/mips/rb500/devices.c
568 --- linux.old/arch/mips/rb500/devices.c 1970-01-01 01:00:00.000000000 +0100
569 +++ linux.dev/arch/mips/rb500/devices.c 2006-07-29 19:31:51.000000000 +0200
570 @@ -0,0 +1,211 @@
571 +#include <linux/kernel.h>
572 +#include <linux/init.h>
573 +#include <linux/module.h>
574 +#include <linux/ctype.h>
575 +#include <linux/string.h>
576 +#include <linux/platform_device.h>
577 +#include <asm/unaligned.h>
578 +#include <asm/io.h>
579 +
580 +#include <asm/rc32434/rc32434.h>
581 +#include <asm/rc32434/dma.h>
582 +#include <asm/rc32434/dma_v.h>
583 +#include <asm/rc32434/eth.h>
584 +#include <asm/rc32434/rb.h>
585 +
586 +#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
587 +#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
588 +#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
589 +#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
590 +
591 +#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
592 +#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
593 +
594 +static struct resource korina_dev0_res[] = {
595 + {
596 + .name = "korina_regs",
597 + .start = ETH0_PhysicalAddress,
598 + .end = ETH0_PhysicalAddress + sizeof(ETH_t),
599 + .flags = IORESOURCE_MEM,
600 + },
601 + {
602 + .name = "korina_rx",
603 + .start = ETH0_DMA_RX_IRQ,
604 + .end = ETH0_DMA_RX_IRQ,
605 + .flags = IORESOURCE_IRQ
606 + },
607 + {
608 + .name = "korina_tx",
609 + .start = ETH0_DMA_TX_IRQ,
610 + .end = ETH0_DMA_TX_IRQ,
611 + .flags = IORESOURCE_IRQ
612 + },
613 + {
614 + .name = "korina_ovr",
615 + .start = ETH0_RX_OVR_IRQ,
616 + .end = ETH0_RX_OVR_IRQ,
617 + .flags = IORESOURCE_IRQ
618 + },
619 + {
620 + .name = "korina_und",
621 + .start = ETH0_TX_UND_IRQ,
622 + .end = ETH0_TX_UND_IRQ,
623 + .flags = IORESOURCE_IRQ
624 + },
625 + {
626 + .name = "korina_dma_rx",
627 + .start = ETH0_RX_DMA_ADDR,
628 + .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
629 + .flags = IORESOURCE_MEM,
630 + },
631 + {
632 + .name = "korina_dma_tx",
633 + .start = ETH0_TX_DMA_ADDR,
634 + .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
635 + .flags = IORESOURCE_MEM,
636 + }
637 +};
638 +
639 +static struct korina_device korina_dev0_data = {
640 + .name = "korina0",
641 + .mac = { 0xde, 0xca, 0xff, 0xc0, 0xff, 0xee }
642 +};
643 +
644 +static struct platform_device korina_dev0 = {
645 + .id = 0,
646 + .name = "korina",
647 + .dev.platform_data = &korina_dev0_data,
648 + .resource = korina_dev0_res,
649 + .num_resources = ARRAY_SIZE(korina_dev0_res),
650 +};
651 +
652 +
653 +#define CF_GPIO_NUM 13
654 +
655 +static struct resource cf_slot0_res[] = {
656 + {
657 + .name = "cf_membase",
658 + .flags = IORESOURCE_MEM
659 + },
660 + {
661 + .name = "cf_irq",
662 + .start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */
663 + .end = (8 + 4 * 32 + CF_GPIO_NUM),
664 + .flags = IORESOURCE_IRQ
665 + }
666 +};
667 +
668 +static struct cf_device cf_slot0_data = {
669 + .gpio_pin = 13
670 +};
671 +
672 +static struct platform_device cf_slot0 = {
673 + .id = 0,
674 + .name = "rb500-cf",
675 + .dev.platform_data = &cf_slot0_data,
676 + .resource = cf_slot0_res,
677 + .num_resources = ARRAY_SIZE(cf_slot0_res),
678 +};
679 +
680 +
681 +
682 +static struct platform_device *rb500_devs[] = {
683 + &korina_dev0,
684 + &cf_slot0
685 +};
686 +
687 +static void __init parse_mac_addr(char* macstr)
688 +{
689 + int i, j;
690 + unsigned char result, value;
691 +
692 + for (i=0; i<6; i++) {
693 + result = 0;
694 + if (i != 5 && *(macstr+2) != ':') {
695 + return;
696 + }
697 + for (j=0; j<2; j++) {
698 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
699 + toupper(*macstr)-'A'+10) < 16) {
700 + result = result*16 + value;
701 + macstr++;
702 + }
703 + else return;
704 + }
705 +
706 + macstr++;
707 + korina_dev0_data.mac[i] = result;
708 + }
709 +}
710 +
711 +
712 +/* DEVICE CONTROLLER 1 */
713 +#define CFG_DC_DEV1 (void*)0xb8010010
714 +#define CFG_DC_DEVBASE 0x0
715 +#define CFG_DC_DEVMASK 0x4
716 +#define CFG_DC_DEVC 0x8
717 +#define CFG_DC_DEVTC 0xC
718 +
719 +
720 +static int __init plat_setup_devices(void)
721 +{
722 + /* Look for the CF card reader */
723 + if (!readl(CFG_DC_DEV1 + CFG_DC_DEVMASK))
724 + rb500_devs[1] = NULL;
725 + else {
726 + cf_slot0_res[0].start = readl(CFG_DC_DEV1 + CFG_DC_DEVBASE);
727 + cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
728 + }
729 +
730 + return platform_add_devices(rb500_devs, ARRAY_SIZE(rb500_devs));
731 +}
732 +
733 +static int __init setup_kmac(char *s)
734 +{
735 + printk("korina mac = %s\n",s);
736 + parse_mac_addr(s);
737 + return 0;
738 +}
739 +
740 +__setup("kmac=", setup_kmac);
741 +arch_initcall(plat_setup_devices);
742 +
743 +
744 +#if defined(CONFIG_MTD_BLOCK2MTD) && defined(CONFIG_BLK_DEV_CF_MIPS)
745 +extern void block2mtd_setup(char *initstr);
746 +extern void mount_devfs_fs(void);
747 +
748 +static int __init setup_mtd(void)
749 +{
750 + struct hd_struct **part;
751 + int num = 0, i;
752 + char initstr[64];
753 +
754 + if (cf_slot0_data.gd == NULL)
755 + return 0;
756 +
757 + /* count partitions */
758 + part = cf_slot0_data.gd->part;
759 + while (part[num] != NULL) {
760 + num++;
761 + }
762 +
763 + if (num < 2)
764 + return 0;
765 +
766 + mount_devfs_fs();
767 + printk("Setting up block2mtd devices\n");
768 +
769 + block2mtd_setup("/dev/cf/card0/part1,131072,kernel");
770 + block2mtd_setup("/dev/cf/card0/part2,131072,rootfs");
771 +
772 + for (i = 2; part[i]; i++) {
773 + sprintf(initstr, "/dev/cf/card0/part%d,131072,part%d", i + 1, i + 1);
774 + block2mtd_setup(initstr);
775 + }
776 +
777 + return 0;
778 +}
779 +
780 +late_initcall(setup_mtd);
781 +#endif
782 diff -urN linux.old/arch/mips/rb500/early_serial.c linux.dev/arch/mips/rb500/early_serial.c
783 --- linux.old/arch/mips/rb500/early_serial.c 1970-01-01 01:00:00.000000000 +0100
784 +++ linux.dev/arch/mips/rb500/early_serial.c 2006-07-29 19:31:51.000000000 +0200
785 @@ -0,0 +1,199 @@
786 +/**************************************************************************
787 + *
788 + * BRIEF MODULE DESCRIPTION
789 + * EB434 specific polling driver for 16550 UART.
790 + *
791 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
792 + *
793 + * This program is free software; you can redistribute it and/or modify it
794 + * under the terms of the GNU General Public License as published by the
795 + * Free Software Foundation; either version 2 of the License, or (at your
796 + * option) any later version.
797 + *
798 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
799 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
800 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
801 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
802 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
803 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
804 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
805 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
806 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
807 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
808 + *
809 + * You should have received a copy of the GNU General Public License along
810 + * with this program; if not, write to the Free Software Foundation, Inc.,
811 + * 675 Mass Ave, Cambridge, MA 02139, USA.
812 + *
813 + *
814 + **************************************************************************
815 + * Copyright (C) 2000 by Lineo, Inc.
816 + * Written by Quinn Jensen (jensenq@lineo.com)
817 + **************************************************************************
818 + * P. Sadik Oct 20, 2003
819 + *
820 + * DIVISOR is made a function of idt_cpu_freq
821 + **************************************************************************
822 + * P. Sadik Oct 30, 2003
823 + *
824 + * added reset_cons_port
825 + **************************************************************************
826 + */
827 +
828 +#include <linux/serial_reg.h>
829 +
830 +/* turn this on to watch the debug protocol echoed on the console port */
831 +#define DEBUG_REMOTE_DEBUG
832 +
833 +#define CONS_BAUD 115200
834 +
835 +extern unsigned int idt_cpu_freq;
836 +
837 +#define EXT_FREQ 24000000
838 +#define INT_FREQ idt_cpu_freq
839 +
840 +#define EXT_PORT 0xb9800000u
841 +#define EXT_SHIFT 0
842 +
843 +#ifdef __MIPSEB__
844 +#define INT_PORT 0xb8058003u
845 +#else
846 +#define INT_PORT 0xb8058000u
847 +#endif
848 +#define INT_SHIFT 2
849 +
850 +#define INT_FCR UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14
851 +#define EXT_FCR UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT
852 +
853 +typedef struct
854 +{
855 + volatile unsigned char *base;
856 + unsigned int shift;
857 + unsigned int freq;
858 + unsigned int fcr;
859 +} ser_port;
860 +
861 +ser_port ports[2] =
862 +{
863 + { (volatile unsigned char *)INT_PORT, INT_SHIFT, 0, INT_FCR},
864 + { (volatile unsigned char *)EXT_PORT, EXT_SHIFT, EXT_FREQ, EXT_FCR}
865 +};
866 +
867 +#define CONS_PORT 0
868 +
869 +void cons_putc(char c);
870 +int port_getc(int port);
871 +void port_putc(int port, char c);
872 +
873 +int cons_getc(void)
874 +{
875 + return port_getc(CONS_PORT);
876 +}
877 +
878 +void cons_putc(char c)
879 +{
880 + port_putc(CONS_PORT, c);
881 +}
882 +
883 +void cons_puts(char *s)
884 +{
885 + while(*s) {
886 + if(*s == '\n') cons_putc('\r');
887 + cons_putc(*s);
888 + s++;
889 + }
890 +}
891 +
892 +void cons_do_putn(int n)
893 +{
894 + if(n) {
895 + cons_do_putn(n / 10);
896 + cons_putc(n % 10 + '0');
897 + }
898 +}
899 +
900 +void cons_putn(int n)
901 +{
902 + if(n < 0) {
903 + cons_putc('-');
904 + n = -n;
905 + }
906 +
907 + if (n == 0) {
908 + cons_putc('0');
909 + } else {
910 + cons_do_putn(n);
911 + }
912 +}
913 +
914 +int port_getc(int p)
915 +{
916 + volatile unsigned char *port = ports[p].base;
917 + int s = ports[p].shift;
918 + int c;
919 +
920 + while((*(port + (UART_LSR << s)) & UART_LSR_DR) == 0) {
921 + continue;
922 + }
923 +
924 + c = *(port + (UART_RX << s));
925 +
926 + return c;
927 +}
928 +
929 +int port_getc_ready(int p)
930 +{
931 + volatile unsigned char *port = ports[p].base;
932 + int s = ports[p].shift;
933 +
934 + return *(port + (UART_LSR << s)) & UART_LSR_DR;
935 +}
936 +
937 +#define OK_TO_XMT (UART_LSR_TEMT | UART_LSR_THRE)
938 +
939 +void port_putc(int p, char c)
940 +{
941 + volatile unsigned char *port = ports[p].base;
942 + int s = ports[p].shift;
943 + volatile unsigned char *lsr = port + (UART_LSR << s);
944 +
945 + while((*lsr & OK_TO_XMT) != OK_TO_XMT) {
946 + continue;
947 + }
948 +
949 + *(port + (UART_TX << s)) = c;
950 +}
951 +
952 +void reset_cons_port(void)
953 +{
954 + volatile unsigned char *port = ports[CONS_PORT].base;
955 + unsigned int s = ports[CONS_PORT].shift;
956 + unsigned int DIVISOR;
957 +
958 + if (ports[CONS_PORT].freq)
959 + DIVISOR = (ports[CONS_PORT].freq / 16 / CONS_BAUD);
960 + else
961 + DIVISOR = (idt_cpu_freq / 16 / CONS_BAUD);
962 +
963 + /* reset the port */
964 + *(port + (UART_CSR << s)) = 0;
965 +
966 + /* clear and enable the FIFOs */
967 + *(port + (UART_FCR << s)) = ports[CONS_PORT].fcr;
968 +
969 + /* set the baud rate */
970 + *(port + (UART_LCR << s)) = UART_LCR_DLAB; /* enable DLL, DLM registers */
971 +
972 + *(port + (UART_DLL << s)) = DIVISOR;
973 + *(port + (UART_DLM << s)) = DIVISOR >> 8;
974 + /* set the line control stuff and disable DLL, DLM regs */
975 +
976 + *(port + (UART_LCR << s)) = UART_LCR_STOP | /* 2 stop bits */
977 + UART_LCR_WLEN8; /* 8 bit word length */
978 +
979 + /* leave interrupts off */
980 + *(port + (UART_IER << s)) = 0;
981 +
982 + /* the modem controls don't leave the chip on this port, so leave them alone */
983 + *(port + (UART_MCR << s)) = 0;
984 +}
985 diff -urN linux.old/arch/mips/rb500/irq.c linux.dev/arch/mips/rb500/irq.c
986 --- linux.old/arch/mips/rb500/irq.c 1970-01-01 01:00:00.000000000 +0100
987 +++ linux.dev/arch/mips/rb500/irq.c 2006-07-29 19:31:51.000000000 +0200
988 @@ -0,0 +1,264 @@
989 +/*
990 + * BRIEF MODULE DESCRIPTION
991 + * RC32434 interrupt routines.
992 + *
993 + * Copyright 2002 MontaVista Software Inc.
994 + * Author: MontaVista Software, Inc.
995 + * stevel@mvista.com or source@mvista.com
996 + *
997 + * This program is free software; you can redistribute it and/or modify it
998 + * under the terms of the GNU General Public License as published by the
999 + * Free Software Foundation; either version 2 of the License, or (at your
1000 + * option) any later version.
1001 + *
1002 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1003 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1004 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1005 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1006 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1007 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1008 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1009 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1010 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1011 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1012 + *
1013 + * You should have received a copy of the GNU General Public License along
1014 + * with this program; if not, write to the Free Software Foundation, Inc.,
1015 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1016 + */
1017 +
1018 +#include <linux/errno.h>
1019 +#include <linux/init.h>
1020 +#include <linux/kernel_stat.h>
1021 +#include <linux/module.h>
1022 +#include <linux/signal.h>
1023 +#include <linux/sched.h>
1024 +#include <linux/types.h>
1025 +#include <linux/interrupt.h>
1026 +#include <linux/ioport.h>
1027 +#include <linux/timex.h>
1028 +#include <linux/slab.h>
1029 +#include <linux/random.h>
1030 +#include <linux/delay.h>
1031 +
1032 +#include <asm/bitops.h>
1033 +#include <asm/bootinfo.h>
1034 +#include <asm/io.h>
1035 +#include <asm/irq.h>
1036 +#include <asm/time.h>
1037 +#include <asm/mipsregs.h>
1038 +#include <asm/system.h>
1039 +#include <asm/rc32434/rc32434.h>
1040 +#include <asm/rc32434/gpio.h>
1041 +
1042 +extern void set_debug_traps(void);
1043 +extern irq_cpustat_t irq_stat [NR_CPUS];
1044 +unsigned int local_bh_count[NR_CPUS];
1045 +unsigned int local_irq_count[NR_CPUS];
1046 +
1047 +static unsigned int startup_irq(unsigned int irq);
1048 +static void rb500_end_irq(unsigned int irq_nr);
1049 +static void mask_and_ack_irq(unsigned int irq_nr);
1050 +static void rb500_enable_irq(unsigned int irq_nr);
1051 +static void rb500_disable_irq(unsigned int irq_nr);
1052 +
1053 +extern void __init init_generic_irq(void);
1054 +
1055 +typedef struct {
1056 + u32 mask; /* mask of valid bits in pending/mask registers */
1057 + volatile u32 *base_addr;
1058 +} intr_group_t;
1059 +
1060 +#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
1061 +
1062 +#if (NR_IRQS < RC32434_NR_IRQS)
1063 +#error Too little irqs defined. Did you override <asm/irq.h> ?
1064 +#endif
1065 +
1066 +static const intr_group_t intr_group[NUM_INTR_GROUPS] = {
1067 + { 0x0000efff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET) },
1068 + { 0x00001fff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET) },
1069 + { 0x00000007, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET) },
1070 + { 0x0003ffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET) },
1071 + { 0xffffffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET) }
1072 +};
1073 +
1074 +#define READ_PEND(base) (*(base))
1075 +#define READ_MASK(base) (*(base + 2))
1076 +#define WRITE_MASK(base, val) (*(base + 2) = (val))
1077 +
1078 +static inline int irq_to_group(unsigned int irq_nr)
1079 +{
1080 + return ((irq_nr - GROUP0_IRQ_BASE) >> 5);
1081 +}
1082 +
1083 +static inline int group_to_ip(unsigned int group)
1084 +{
1085 + return group + 2;
1086 +}
1087 +
1088 +static inline void enable_local_irq(unsigned int ip)
1089 +{
1090 + int ipnum = 0x100 << ip;
1091 + clear_c0_cause(ipnum);
1092 + set_c0_status(ipnum);
1093 +}
1094 +
1095 +static inline void disable_local_irq(unsigned int ip)
1096 +{
1097 + int ipnum = 0x100 << ip;
1098 + clear_c0_status(ipnum);
1099 +}
1100 +
1101 +static inline void ack_local_irq(unsigned int ip)
1102 +{
1103 + int ipnum = 0x100 << ip;
1104 + clear_c0_cause(ipnum);
1105 +}
1106 +
1107 +static void rb500_enable_irq(unsigned int irq_nr)
1108 +{
1109 + int ip = irq_nr - GROUP0_IRQ_BASE;
1110 + unsigned int group, intr_bit;
1111 + volatile unsigned int *addr;
1112 +
1113 +
1114 + if (ip < 0)
1115 + enable_local_irq(irq_nr);
1116 + else {
1117 + group = ip >> 5;
1118 +
1119 + ip &= (1<<5)-1;
1120 + intr_bit = 1 << ip;
1121 +
1122 + enable_local_irq(group_to_ip(group));
1123 +
1124 + addr = intr_group[group].base_addr;
1125 + WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
1126 + }
1127 +}
1128 +
1129 +static void rb500_disable_irq(unsigned int irq_nr)
1130 +{
1131 + int ip = irq_nr - GROUP0_IRQ_BASE;
1132 + unsigned int group, intr_bit, mask;
1133 + volatile unsigned int *addr;
1134 +
1135 + if (ip < 0) {
1136 + disable_local_irq(irq_nr);
1137 + }else{
1138 + group = ip >> 5;
1139 +
1140 + ip &= (1<<5) -1;
1141 + intr_bit = 1 << ip;
1142 + addr = intr_group[group].base_addr;
1143 + mask = READ_MASK(addr);
1144 + mask |= intr_bit;
1145 + WRITE_MASK(addr,mask);
1146 +
1147 + /*
1148 + * if there are no more interrupts enabled in this
1149 + * group, disable corresponding IP
1150 + */
1151 + if (mask == intr_group[group].mask)
1152 + disable_local_irq(group_to_ip(group));
1153 + }
1154 +}
1155 +
1156 +static unsigned int startup_irq(unsigned int irq_nr)
1157 +{
1158 + rb500_enable_irq(irq_nr);
1159 + return 0;
1160 +}
1161 +
1162 +static void shutdown_irq(unsigned int irq_nr)
1163 +{
1164 + rb500_disable_irq(irq_nr);
1165 + return;
1166 +}
1167 +
1168 +static void mask_and_ack_irq(unsigned int irq_nr)
1169 +{
1170 + rb500_disable_irq(irq_nr);
1171 + ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
1172 +}
1173 +
1174 +static void rb500_end_irq(unsigned int irq_nr)
1175 +{
1176 +
1177 + int ip = irq_nr - GROUP0_IRQ_BASE;
1178 + unsigned int intr_bit, group;
1179 + volatile unsigned int *addr;
1180 +
1181 + if ((irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
1182 + printk("warning: end_irq %d did not enable (%x)\n",
1183 + irq_nr, irq_desc[irq_nr].status);
1184 + return;
1185 + }
1186 +
1187 + if (ip < 0) {
1188 + enable_local_irq(irq_nr);
1189 + } else {
1190 + group = ip >> 5;
1191 +
1192 + ip &= (1 << 5) - 1;
1193 + intr_bit = 1 << ip;
1194 +
1195 + if (irq_nr >= GROUP4_IRQ_BASE && irq_nr <= (GROUP4_IRQ_BASE + 13)) {
1196 + gpio->gpioistat = gpio->gpioistat & ~intr_bit;
1197 + }
1198 +
1199 + enable_local_irq(group_to_ip(group));
1200 +
1201 + addr = intr_group[group].base_addr;
1202 + WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
1203 + }
1204 +}
1205 +
1206 +static struct hw_interrupt_type rc32434_irq_type = {
1207 + .typename = "RB500",
1208 + .startup = startup_irq,
1209 + .shutdown = shutdown_irq,
1210 + .enable = rb500_enable_irq,
1211 + .disable = rb500_disable_irq,
1212 + .ack = mask_and_ack_irq,
1213 + .end = rb500_end_irq,
1214 +};
1215 +
1216 +
1217 +void __init arch_init_irq(void)
1218 +{
1219 + int i;
1220 +
1221 + printk("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
1222 + memset(irq_desc, 0, sizeof(irq_desc));
1223 +
1224 + for (i = 0; i < RC32434_NR_IRQS; i++) {
1225 + irq_desc[i].status = IRQ_DISABLED;
1226 + irq_desc[i].action = NULL;
1227 + irq_desc[i].depth = 1;
1228 + irq_desc[i].handler = &rc32434_irq_type;
1229 + spin_lock_init(&irq_desc[i].lock);
1230 + }
1231 +}
1232 +
1233 +/* Main Interrupt dispatcher */
1234 +asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
1235 +{
1236 + unsigned int ip, pend, group;
1237 + volatile unsigned int *addr;
1238 + unsigned int cp0_cause = read_c0_cause() & read_c0_status();
1239 +
1240 + if (cp0_cause & CAUSEF_IP7) {
1241 + ll_timer_interrupt(7, regs);
1242 + } else if ((ip = (cp0_cause & 0x7c00))) {
1243 + group = 21 - rc32434_clz(ip);
1244 +
1245 + addr = intr_group[group].base_addr;
1246 +
1247 + pend = READ_PEND(addr);
1248 + pend &= ~READ_MASK(addr); // only unmasked interrupts
1249 + pend = 39 - rc32434_clz(pend);
1250 + do_IRQ((group << 5) + pend, regs);
1251 + }
1252 +}
1253 diff -urN linux.old/arch/mips/rb500/Makefile linux.dev/arch/mips/rb500/Makefile
1254 --- linux.old/arch/mips/rb500/Makefile 1970-01-01 01:00:00.000000000 +0100
1255 +++ linux.dev/arch/mips/rb500/Makefile 2006-07-29 19:31:51.000000000 +0200
1256 @@ -0,0 +1,5 @@
1257 +#
1258 +# Makefile for the RB500 board specific parts of the kernel
1259 +#
1260 +
1261 +obj-y += irq.o time.o setup.o serial.o early_serial.o prom.o misc.o devices.o
1262 diff -urN linux.old/arch/mips/rb500/misc.c linux.dev/arch/mips/rb500/misc.c
1263 --- linux.old/arch/mips/rb500/misc.c 1970-01-01 01:00:00.000000000 +0100
1264 +++ linux.dev/arch/mips/rb500/misc.c 2006-07-29 19:31:51.000000000 +0200
1265 @@ -0,0 +1,54 @@
1266 +#include <linux/module.h>
1267 +#include <linux/kernel.h> /* printk() */
1268 +#include <linux/types.h> /* size_t */
1269 +#include <linux/pci.h>
1270 +#include <linux/spinlock.h>
1271 +#include <asm/rc32434/rb.h>
1272 +
1273 +#define GPIO_BADDR 0xb8050000
1274 +
1275 +
1276 +static unsigned char *devCtl3Base = (unsigned char *) KSEG1ADDR(0x18010030);
1277 +static unsigned char latchU5State = 0;
1278 +static spinlock_t clu5Lock = SPIN_LOCK_UNLOCKED;
1279 +
1280 +void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val) {
1281 + unsigned flags, data;
1282 + unsigned i = 0;
1283 + spin_lock_irqsave(&clu5Lock, flags);
1284 + data = *(volatile unsigned *) (IDT434_REG_BASE + regOffs);
1285 + for (i = 0; i != len; ++i) {
1286 + if (val & (1 << i)) data |= (1 << (i + bit));
1287 + else data &= ~(1 << (i + bit));
1288 + }
1289 + *(volatile unsigned *) (IDT434_REG_BASE + regOffs) = data;
1290 + spin_unlock_irqrestore(&clu5Lock, flags);
1291 +}
1292 +
1293 +void changeLatchU5(unsigned char orMask, unsigned char nandMask) {
1294 + unsigned flags;
1295 + spin_lock_irqsave(&clu5Lock, flags);
1296 + latchU5State = (latchU5State | orMask) & ~nandMask;
1297 + *devCtl3Base = latchU5State;
1298 + spin_unlock_irqrestore(&clu5Lock, flags);
1299 +}
1300 +
1301 +u32 gpio_get(gpio_func func)
1302 +{
1303 + return readl((void *) GPIO_BADDR + func);
1304 +}
1305 +
1306 +void gpio_set(gpio_func func, u32 mask, u32 value)
1307 +{
1308 + u32 val = readl((void *) GPIO_BADDR + func);
1309 +
1310 + val &= ~mask;
1311 + val |= value & mask;
1312 +
1313 + writel(val, (void *) GPIO_BADDR + func);
1314 +}
1315 +
1316 +EXPORT_SYMBOL(gpio_set);
1317 +EXPORT_SYMBOL(gpio_get);
1318 +EXPORT_SYMBOL(set434Reg);
1319 +EXPORT_SYMBOL(changeLatchU5);
1320 diff -urN linux.old/arch/mips/rb500/prom.c linux.dev/arch/mips/rb500/prom.c
1321 --- linux.old/arch/mips/rb500/prom.c 1970-01-01 01:00:00.000000000 +0100
1322 +++ linux.dev/arch/mips/rb500/prom.c 2006-07-29 19:31:51.000000000 +0200
1323 @@ -0,0 +1,181 @@
1324 +/*
1325 +* prom.c
1326 +**********************************************************************
1327 +* P . Sadik Oct 10, 2003
1328 +*
1329 +* Started change log
1330 +* idt_cpu_freq is make a kernel configuration parameter
1331 +* idt_cpu_freq is exported so that other modules can use it.
1332 +* Code cleanup
1333 +**********************************************************************
1334 +* P. Sadik Oct 20, 2003
1335 +*
1336 +* Removed NVRAM code from here, since they are already available under
1337 +* nvram directory.
1338 +* Added serial port initialisation.
1339 +**********************************************************************
1340 +**********************************************************************
1341 +* P. Sadik Oct 30, 2003
1342 +*
1343 +* Added reset_cons_port
1344 +**********************************************************************
1345 +
1346 + P.Christeas, 2005-2006
1347 + Port to 2.6, add 2.6 cmdline parsing
1348 +
1349 +*/
1350 +
1351 +#include <linux/config.h>
1352 +#include <linux/init.h>
1353 +#include <linux/mm.h>
1354 +#include <linux/module.h>
1355 +#include <linux/string.h>
1356 +#include <linux/console.h>
1357 +#include <asm/bootinfo.h>
1358 +#include <linux/bootmem.h>
1359 +#include <linux/ioport.h>
1360 +#include <linux/blkdev.h>
1361 +#include <asm/rc32434/ddr.h>
1362 +
1363 +#define PROM_ENTRY(x) (0xbfc00000+((x)*8))
1364 +extern void __init setup_serial_port(void);
1365 +extern void cons_putc(char c);
1366 +extern void cons_puts(char *s);
1367 +
1368 +unsigned int idt_cpu_freq = 132000000;
1369 +EXPORT_SYMBOL(idt_cpu_freq);
1370 +unsigned int board_type = 500;
1371 +EXPORT_SYMBOL(board_type);
1372 +unsigned int gpio_bootup_state = 0;
1373 +EXPORT_SYMBOL(gpio_bootup_state);
1374 +
1375 +
1376 +char mips_mac_address[18] = "08:00:06:05:40:01";
1377 +EXPORT_SYMBOL(mips_mac_address);
1378 +
1379 +/* what to append to cmdline when button is [not] pressed */
1380 +#define GPIO_INIT_NOBUTTON ""
1381 +#define GPIO_INIT_BUTTON " 2"
1382 +
1383 +#ifdef CONFIG_MIKROTIK_RB500
1384 +unsigned soft_reboot = 0;
1385 +EXPORT_SYMBOL(soft_reboot);
1386 +#endif
1387 +
1388 +#define SR_NMI 0x00180000 /* NMI */
1389 +#define SERIAL_SPEED_ENTRY 0x00000001
1390 +
1391 +#ifdef CONFIG_REMOTE_DEBUG
1392 +extern int remote_debug;
1393 +#endif
1394 +
1395 +extern unsigned long mips_machgroup;
1396 +extern unsigned long mips_machtype;
1397 +
1398 +#define FREQ_TAG "HZ="
1399 +#define GPIO_TAG "gpio="
1400 +#define KMAC_TAG "kmac="
1401 +#define MEM_TAG "mem="
1402 +#define BOARD_TAG "board="
1403 +#define IGNORE_CMDLINE_MEM 1
1404 +#define DEBUG_DDR
1405 +
1406 +void parse_soft_settings(unsigned *ptr, unsigned size);
1407 +void parse_hard_settings(unsigned *ptr, unsigned size);
1408 +
1409 +void __init prom_setup_cmdline(void);
1410 +
1411 +#ifdef DEBUG_DDR
1412 +void cons_puthex4(u32 h){
1413 + h&=0x0f;
1414 + if (h>=10)
1415 + cons_putc((h-10)+'a');
1416 + else
1417 + cons_putc(h+'0');
1418 +}
1419 +
1420 +void cons_putreg32(u32 reg){
1421 + char c;
1422 + cons_putc('0');
1423 + cons_putc('x');
1424 + for (c=28;c>=0;c-=4)
1425 + cons_puthex4(reg>>c);
1426 +}
1427 +#endif
1428 +
1429 +void __init prom_init(void)
1430 +{
1431 + DDR_t ddr = (DDR_t) DDR_VirtualAddress; /* define the pointer to the DDR registers */
1432 + phys_t memsize = 0-ddr->ddrmask;
1433 +
1434 + /* this should be the very first message, even before serial is properly initialized */
1435 + prom_setup_cmdline();
1436 + setup_serial_port();
1437 +
1438 + mips_machgroup = MACH_GROUP_MIKROTIK;
1439 + soft_reboot = read_c0_status() & SR_NMI;
1440 + pm_power_off = NULL;
1441 +
1442 + /*
1443 + * give all RAM to boot allocator,
1444 + * except for the first 0x400 and the last 0x200 bytes
1445 + */
1446 + add_memory_region(ddr->ddrbase + 0x400, memsize - 0x600, BOOT_MEM_RAM);
1447 +}
1448 +
1449 +void prom_free_prom_memory(void)
1450 +{
1451 + /* FIXME: STUB */
1452 +}
1453 +
1454 +void __init prom_setup_cmdline(void){
1455 + char cmd_line[CL_SIZE];
1456 + char *cp;
1457 + int prom_argc;
1458 + char **prom_argv, **prom_envp;
1459 + int i;
1460 +
1461 + prom_argc = fw_arg0;
1462 + prom_argv = (char **) fw_arg1;
1463 + prom_envp = (char **) fw_arg2;
1464 +
1465 + cp=cmd_line;
1466 + /* Note: it is common that parameters start at argv[1] and not argv[0],
1467 + however, our elf loader starts at [0] */
1468 + for(i=0;i<prom_argc;i++){
1469 + if (strncmp(prom_argv[i], FREQ_TAG, sizeof(FREQ_TAG) - 1) == 0) {
1470 + idt_cpu_freq = simple_strtoul(prom_argv[i] + sizeof(FREQ_TAG) - 1, 0, 10);
1471 + continue;
1472 + }
1473 +#ifdef IGNORE_CMDLINE_MEM
1474 + /* parses out the "mem=xx" arg */
1475 + if (strncmp(prom_argv[i], MEM_TAG, sizeof(MEM_TAG) - 1) == 0) {
1476 + continue;
1477 + }
1478 +#endif
1479 + if (i>0) *(cp++) = ' ';
1480 + if (strncmp(prom_argv[i], BOARD_TAG, sizeof(BOARD_TAG) - 1) == 0) {
1481 + board_type = simple_strtoul(prom_argv[i] + sizeof(BOARD_TAG) - 1, 0, 10);
1482 + }
1483 + if (strncmp(prom_argv[i], GPIO_TAG, sizeof(GPIO_TAG) - 1) == 0) {
1484 + gpio_bootup_state = simple_strtoul(prom_argv[i] + sizeof(GPIO_TAG) - 1, 0, 10);
1485 + }
1486 + strcpy(cp,prom_argv[i]);
1487 + cp+=strlen(prom_argv[i]);
1488 + }
1489 +
1490 + i=strlen(arcs_cmdline);
1491 + if (i>0){
1492 + *(cp++) = ' ';
1493 + strcpy(cp,arcs_cmdline);
1494 + cp+=strlen(arcs_cmdline);
1495 + }
1496 + if (gpio_bootup_state&0x02)
1497 + strcpy(cp,GPIO_INIT_NOBUTTON);
1498 + else
1499 + strcpy(cp,GPIO_INIT_BUTTON);
1500 + cmd_line[CL_SIZE-1] = '\0';
1501 +
1502 + strcpy(arcs_cmdline,cmd_line);
1503 +}
1504 +
1505 diff -urN linux.old/arch/mips/rb500/serial.c linux.dev/arch/mips/rb500/serial.c
1506 --- linux.old/arch/mips/rb500/serial.c 1970-01-01 01:00:00.000000000 +0100
1507 +++ linux.dev/arch/mips/rb500/serial.c 2006-07-29 19:31:51.000000000 +0200
1508 @@ -0,0 +1,79 @@
1509 +/**************************************************************************
1510 + *
1511 + * BRIEF MODULE DESCRIPTION
1512 + * Serial port initialisation.
1513 + *
1514 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1515 + *
1516 + * This program is free software; you can redistribute it and/or modify it
1517 + * under the terms of the GNU General Public License as published by the
1518 + * Free Software Foundation; either version 2 of the License, or (at your
1519 + * option) any later version.
1520 + *
1521 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1522 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1523 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1524 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1525 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1526 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1527 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1528 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1529 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1530 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1531 + *
1532 + * You should have received a copy of the GNU General Public License along
1533 + * with this program; if not, write to the Free Software Foundation, Inc.,
1534 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1535 + *
1536 + *
1537 + **************************************************************************
1538 + * May 2004 rkt, neb
1539 + *
1540 + * Initial Release
1541 + *
1542 + *
1543 + *
1544 + **************************************************************************
1545 + */
1546 +
1547 +
1548 +#include <linux/config.h>
1549 +#include <linux/init.h>
1550 +#include <linux/sched.h>
1551 +#include <linux/pci.h>
1552 +#include <linux/interrupt.h>
1553 +#include <linux/tty.h>
1554 +#include <linux/serial.h>
1555 +#include <linux/serial_core.h>
1556 +
1557 +#include <asm/time.h>
1558 +#include <asm/cpu.h>
1559 +#include <asm/bootinfo.h>
1560 +#include <asm/irq.h>
1561 +#include <asm/serial.h>
1562 +#include <asm/rc32434/rc32434.h>
1563 +
1564 +extern unsigned int idt_cpu_freq;
1565 +
1566 +static struct uart_port serial_req = {
1567 + .type = PORT_16550A,
1568 + .line = 0,
1569 + .irq = RC32434_UART0_IRQ,
1570 + .flags = STD_COM_FLAGS,
1571 + .iotype = UPIO_MEM,
1572 + .membase = (char *) KSEG1ADDR(RC32434_UART0_BASE),
1573 +// .fifosize = 14
1574 + .regshift = 2
1575 +};
1576 +
1577 +int __init setup_serial_port(void)
1578 +{
1579 + serial_req.uartclk = idt_cpu_freq;
1580 +
1581 + if (early_serial_setup(&serial_req)){
1582 + cons_puts("Serial setup failed!\n");
1583 + return -ENODEV;
1584 + }
1585 +
1586 + return(0);
1587 +}
1588 diff -urN linux.old/arch/mips/rb500/setup.c linux.dev/arch/mips/rb500/setup.c
1589 --- linux.old/arch/mips/rb500/setup.c 1970-01-01 01:00:00.000000000 +0100
1590 +++ linux.dev/arch/mips/rb500/setup.c 2006-07-29 19:31:51.000000000 +0200
1591 @@ -0,0 +1,84 @@
1592 +/*
1593 + * setup.c - boot time setup code
1594 + */
1595 +
1596 +#include <linux/init.h>
1597 +#include <linux/mm.h>
1598 +#include <linux/sched.h>
1599 +#include <linux/irq.h>
1600 +#include <asm/bootinfo.h>
1601 +#include <asm/io.h>
1602 +#include <linux/ioport.h>
1603 +#include <asm/mipsregs.h>
1604 +#include <asm/pgtable.h>
1605 +#include <asm/reboot.h>
1606 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
1607 +#include <asm/rc32434/rc32434.h>
1608 +#include <linux/pm.h>
1609 +#include <asm/rc32434/pci.h>
1610 +
1611 +extern void (*board_time_init)(void);
1612 +extern void (*board_timer_setup)(struct irqaction *irq);
1613 +extern void rc32434_time_init(void);
1614 +extern void rc32434_timer_setup(struct irqaction *irq);
1615 +#ifdef CONFIG_PCI
1616 +extern int __init rc32434_pcibridge_init(void);
1617 +#endif
1618 +
1619 +#define epldMask ((volatile unsigned char *)0xB900000d)
1620 +
1621 +static void rb_machine_restart(char *command)
1622 +{
1623 + /* just jump to the reset vector */
1624 + * (volatile unsigned *) KSEG1ADDR(0x18008000) = 0x80000001;
1625 + ((void (*)(void))KSEG1ADDR(0x1FC00000u))();
1626 +}
1627 +
1628 +static void rb_machine_halt(void)
1629 +{
1630 + for(;;) continue;
1631 +}
1632 +
1633 +#ifdef CONFIG_CPU_HAS_WB
1634 +void (*__wbflush) (void);
1635 +
1636 +static void rb_write_buffer_flush(void)
1637 +{
1638 + __asm__ __volatile__
1639 + ("sync\n\t" "nop\n\t" "loop: bc0f loop\n\t" "nop\n\t");
1640 +}
1641 +#endif
1642 +
1643 +void __init plat_setup(void)
1644 +{
1645 + unsigned int pciCntlVal;
1646 +
1647 + board_time_init = rc32434_time_init;
1648 + board_timer_setup = rc32434_timer_setup;
1649 +
1650 +#ifdef CONFIG_CPU_HAS_WB
1651 + __wbflush = rb_write_buffer_flush;
1652 +#endif
1653 + _machine_restart = rb_machine_restart;
1654 + _machine_halt = rb_machine_halt;
1655 + /*_machine_power_off = rb_machine_power_halt;*/
1656 + pm_power_off = rb_machine_halt;
1657 +
1658 + set_io_port_base(KSEG1);
1659 +
1660 + pciCntlVal=rc32434_pci->pcic;
1661 + pciCntlVal &= 0xFFFFFF7;
1662 + rc32434_pci->pcic = pciCntlVal;
1663 +
1664 +#ifdef CONFIG_PCI
1665 + /* Enable PCI interrupts in EPLD Mask register */
1666 + *epldMask = 0x0;
1667 + *(epldMask + 1) = 0x0;
1668 +#endif
1669 + write_c0_wired(0);
1670 +}
1671 +
1672 +const char *get_system_type(void)
1673 +{
1674 + return "MIPS RB500";
1675 +}
1676 diff -urN linux.old/arch/mips/rb500/time.c linux.dev/arch/mips/rb500/time.c
1677 --- linux.old/arch/mips/rb500/time.c 1970-01-01 01:00:00.000000000 +0100
1678 +++ linux.dev/arch/mips/rb500/time.c 2006-07-29 19:31:51.000000000 +0200
1679 @@ -0,0 +1,94 @@
1680 +/*
1681 +****************************************************************************
1682 +* Carsten Langgaard, carstenl@mips.com
1683 +* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1684 +*
1685 +***************************************************************************
1686 +*
1687 +* This program is free software; you can distribute it and/or modify it
1688 +* under the terms of the GNU General Public License (Version 2) as
1689 +* published by the Free Software Foundation.
1690 +*
1691 +* This program is distributed in the hope it will be useful, but WITHOUT
1692 +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1693 +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1694 +* for more details.
1695 +*
1696 +* You should have received a copy of the GNU General Public License along
1697 +* with this program; if not, write to the Free Software Foundation, Inc.,
1698 +* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1699 +*
1700 +****************************************************************************
1701 +*
1702 +* Setting up the clock on the MIPS boards.
1703 +*
1704 +****************************************************************************
1705 +* P. Sadik Oct 10, 2003
1706 +*
1707 +* Started change log.
1708 +* mips_counter_frequency is now calculated at run time, based on idt_cpu_freq.
1709 +* Code cleanup
1710 +****************************************************************************
1711 +*/
1712 +
1713 +#include <linux/config.h>
1714 +#include <linux/init.h>
1715 +#include <linux/kernel_stat.h>
1716 +#include <linux/sched.h>
1717 +#include <linux/spinlock.h>
1718 +#include <linux/mc146818rtc.h>
1719 +#include <linux/irq.h>
1720 +#include <linux/timex.h>
1721 +
1722 +#include <asm/mipsregs.h>
1723 +#include <asm/ptrace.h>
1724 +#include <asm/debug.h>
1725 +#include <asm/rc32434/rc32434.h>
1726 +
1727 +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
1728 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
1729 +extern void ll_timer_interrupt(int irq, struct pt_regs *regs);
1730 +extern unsigned int mips_hpt_frequency;
1731 +extern unsigned int idt_cpu_freq;
1732 +
1733 +/*
1734 + * Figure out the r4k offset, the amount to increment the compare
1735 + * register for each time tick. There is no RTC available.
1736 + *
1737 + * The RC32434 counts at half the CPU *core* speed.
1738 + */
1739 +static unsigned long __init cal_r4koff(void)
1740 +{
1741 + mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
1742 + return (mips_hpt_frequency / HZ);
1743 +}
1744 +
1745 +
1746 +void __init rc32434_time_init(void)
1747 +{
1748 + unsigned int est_freq, flags;
1749 +
1750 + local_irq_save(flags);
1751 +
1752 + printk("calculating r4koff... ");
1753 + r4k_offset = cal_r4koff();
1754 + printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
1755 +
1756 + est_freq = 2*r4k_offset*HZ;
1757 + est_freq += 5000; /* round */
1758 + est_freq -= est_freq%10000;
1759 + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
1760 + (est_freq%1000000)*100/1000000);
1761 + local_irq_restore(flags);
1762 +}
1763 +
1764 +void __init rc32434_timer_setup(struct irqaction *irq)
1765 +{
1766 + /* we are using the cpu counter for timer interrupts */
1767 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1768 +
1769 + /* to generate the first timer interrupt */
1770 + r4k_cur = (read_c0_count() + r4k_offset);
1771 + write_c0_compare(r4k_cur);
1772 +}
1773 +
1774 diff -urN linux.old/drivers/mtd/devices/block2mtd.c linux.dev/drivers/mtd/devices/block2mtd.c
1775 --- linux.old/drivers/mtd/devices/block2mtd.c 2006-07-29 19:53:54.000000000 +0200
1776 +++ linux.dev/drivers/mtd/devices/block2mtd.c 2006-07-29 19:47:03.000000000 +0200
1777 @@ -26,7 +26,6 @@
1778 #define ERROR(fmt, args...) printk(KERN_ERR "block2mtd: " fmt "\n" , ## args)
1779 #define INFO(fmt, args...) printk(KERN_INFO "block2mtd: " fmt "\n" , ## args)
1780
1781 -
1782 /* Info for the block device */
1783 struct block2mtd_dev {
1784 struct list_head list;
1785 @@ -62,10 +61,8 @@
1786 read_lock_irq(&mapping->tree_lock);
1787 for (i = 0; i < PAGE_READAHEAD; i++) {
1788 pagei = index + i;
1789 - if (pagei > end_index) {
1790 - INFO("Overrun end of disk in cache readahead\n");
1791 + if (pagei > end_index)
1792 break;
1793 - }
1794 page = radix_tree_lookup(&mapping->page_tree, pagei);
1795 if (page && (!i))
1796 break;
1797 @@ -106,7 +103,7 @@
1798
1799 while (pages) {
1800 page = page_readahead(mapping, index);
1801 - if (!page)
1802 + if (!page || !page_address(page))
1803 return -ENOMEM;
1804 if (IS_ERR(page))
1805 return PTR_ERR(page);
1806 @@ -285,7 +282,7 @@
1807
1808
1809 /* FIXME: ensure that mtd->size % erase_size == 0 */
1810 -static struct block2mtd_dev *add_device(char *devname, int erase_size)
1811 +static struct block2mtd_dev *add_device(char *devname, int erase_size, char *alias)
1812 {
1813 struct block_device *bdev;
1814 struct block2mtd_dev *dev;
1815 @@ -315,14 +312,15 @@
1816
1817 /* Setup the MTD structure */
1818 /* make the name contain the block device in */
1819 - dev->mtd.name = kmalloc(sizeof("block2mtd: ") + strlen(devname),
1820 + dev->mtd.name = kmalloc(strlen((alias ?: devname)),
1821 GFP_KERNEL);
1822 if (!dev->mtd.name)
1823 goto devinit_err;
1824
1825 - sprintf(dev->mtd.name, "block2mtd: %s", devname);
1826 + strcpy(dev->mtd.name, (alias ?: devname));
1827
1828 dev->mtd.size = dev->blkdev->bd_inode->i_size & PAGE_MASK;
1829 + dev->mtd.size -= dev->mtd.size % erase_size;
1830 dev->mtd.erasesize = erase_size;
1831 dev->mtd.type = MTD_RAM;
1832 dev->mtd.flags = MTD_CAP_RAM;
1833 @@ -341,7 +339,7 @@
1834 }
1835 list_add(&dev->list, &blkmtd_device_list);
1836 INFO("mtd%d: [%s] erase_size = %dKiB [%d]", dev->mtd.index,
1837 - dev->mtd.name + strlen("blkmtd: "),
1838 + dev->mtd.name,
1839 dev->mtd.erasesize >> 10, dev->mtd.erasesize);
1840 return dev;
1841
1842 @@ -416,10 +414,10 @@
1843 return 0; \
1844 } while (0)
1845
1846 -static int block2mtd_setup(const char *val, struct kernel_param *kp)
1847 +int block2mtd_setup(const char *val, struct kernel_param *kp)
1848 {
1849 char buf[80+12], *str=buf; /* 80 for device, 12 for erase size */
1850 - char *token[2];
1851 + char *token[3];
1852 char *name;
1853 size_t erase_size = PAGE_SIZE;
1854 int i, ret;
1855 @@ -430,7 +428,7 @@
1856 strcpy(str, val);
1857 kill_final_newline(str);
1858
1859 - for (i=0; i<2; i++)
1860 + for (i=0; i<3; i++)
1861 token[i] = strsep(&str, ",");
1862
1863 if (str)
1864 @@ -453,7 +451,7 @@
1865 parse_err("illegal erase size");
1866 }
1867
1868 - add_device(name, erase_size);
1869 + add_device(name, erase_size, token[2]);
1870
1871 return 0;
1872 }
1873 @@ -461,6 +459,7 @@
1874
1875 module_param_call(block2mtd, block2mtd_setup, NULL, NULL, 0200);
1876 MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=<dev>[,<erasesize>]\"");
1877 +EXPORT_SYMBOL(block2mtd_setup);
1878
1879 static int __init block2mtd_init(void)
1880 {
1881 diff -urN linux.old/drivers/pci/Makefile linux.dev/drivers/pci/Makefile
1882 --- linux.old/drivers/pci/Makefile 2006-07-29 19:53:20.000000000 +0200
1883 +++ linux.dev/drivers/pci/Makefile 2006-07-29 19:31:51.000000000 +0200
1884 @@ -27,6 +27,7 @@
1885 obj-$(CONFIG_MIPS) += setup-bus.o setup-irq.o
1886 obj-$(CONFIG_X86_VISWS) += setup-irq.o
1887 obj-$(CONFIG_PCI_MSI) += msi.o
1888 +obj-$(CONFIG_MIKROTIK_RB500) += setup-irq.o
1889
1890 #
1891 # ACPI Related PCI FW Functions
1892 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
1893 --- linux.old/include/asm-mips/bootinfo.h 2006-07-29 19:53:20.000000000 +0200
1894 +++ linux.dev/include/asm-mips/bootinfo.h 2006-07-29 19:31:51.000000000 +0200
1895 @@ -218,6 +218,8 @@
1896 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
1897 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
1898
1899 +#define MACH_GROUP_MIKROTIK 24 /* Mikrotik Boards */
1900 +
1901 #define CL_SIZE COMMAND_LINE_SIZE
1902
1903 const char *get_system_type(void);
1904 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
1905 --- linux.old/include/asm-mips/cpu.h 2006-07-29 19:53:20.000000000 +0200
1906 +++ linux.dev/include/asm-mips/cpu.h 2006-07-29 19:31:51.000000000 +0200
1907 @@ -200,7 +200,8 @@
1908 #define CPU_SB1A 62
1909 #define CPU_74K 63
1910 #define CPU_R14000 64
1911 -#define CPU_LAST 64
1912 +#define CPU_RC32300 65
1913 +#define CPU_LAST 65
1914
1915 /*
1916 * ISA Level encodings
1917 diff -urN linux.old/include/asm-mips/rc32434/crom.h linux.dev/include/asm-mips/rc32434/crom.h
1918 --- linux.old/include/asm-mips/rc32434/crom.h 1970-01-01 01:00:00.000000000 +0100
1919 +++ linux.dev/include/asm-mips/rc32434/crom.h 2006-07-29 19:31:51.000000000 +0200
1920 @@ -0,0 +1,98 @@
1921 +#ifndef __IDT_CROM_H__
1922 +#define __IDT_CROM_H__
1923 +
1924 +/*******************************************************************************
1925 + *
1926 + * Copyright 2002 Integrated Device Technology, Inc.
1927 + * All rights reserved.
1928 + *
1929 + * Configuration ROM register definitions.
1930 + *
1931 + * File : $Id: crom.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
1932 + *
1933 + * Author : Allen.Stichter@idt.com
1934 + * Date : 20020118
1935 + * Update :
1936 + * $Log: crom.h,v $
1937 + * Revision 1.2 2002/06/06 18:34:03 astichte
1938 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
1939 + *
1940 + * Revision 1.1 2002/05/29 17:33:21 sysarch
1941 + * jba File moved from vcode/include/idt/acacia
1942 + *
1943 + *
1944 + ******************************************************************************/
1945 +
1946 +#include <asm/rc32434/types.h>
1947 +
1948 +enum
1949 +{
1950 + CROM0_PhysicalAddress = 0x100b8000,
1951 + CROM_PhysicalAddress = CROM0_PhysicalAddress,
1952 +
1953 + CROM0_VirtualAddress = 0xb00b8000,
1954 + CROM_VirtualAddress = CROM0_VirtualAddress,
1955 +} ;
1956 +
1957 +typedef struct CROM_s
1958 +{
1959 + U32 cromw0 ; // use CROMW0_
1960 + U32 cromw1 ; // use CROMW1_
1961 + U32 cromw2 ; // use CROMW2_
1962 +} volatile * CROM_t ;
1963 +
1964 +enum
1965 +{
1966 + CROMW0_xloc_b = 0,
1967 + CROMW0_xloc_m = 0x0000003f,
1968 + CROMW0_yloc_b = 8,
1969 + CROMW0_yloc_m = 0x00003f00,
1970 + CROMW0_speed_b = 16,
1971 + CROMW0_speed_m = 0x01ff0000,
1972 + CROMW1_wafer_b = 0,
1973 + CROMW1_wafer_m = 0x0000001f,
1974 + CROMW1_lot_b = 8,
1975 + CROMW1_lot_m = 0x0fffff00,
1976 + CROMW1_fab_b = 28,
1977 + CROMW1_fab_m = 0xf0000000,
1978 + CROMW2_pci_b = 0,
1979 + CROMW2_pci_m = 0x00000001,
1980 + CROMW2_eth0_b = 1,
1981 + CROMW2_eth0_m = 0x00000002,
1982 + CROMW2_eth1_b = 2,
1983 + CROMW2_eth1_m = 0x00000004
1984 + CROMW2_i2c_b = 3,
1985 + CROMW2_i2c_m = 0x00000008,
1986 + CROMW2_rng_b = 4,
1987 + CROMW2_rng_m = 0x00000010,
1988 + CROMW2_se_b = 5,
1989 + CROMW2_se_m = 0x00000020,
1990 + CROMW2_des_b = 6,
1991 + CROMW2_des_m = 0x00000040,
1992 + CROMW2_tdes_b = 7,
1993 + CROMW2_tdes_m = 0x00000080,
1994 + CROMW2_a128_b = 8,
1995 + CROMW2_a128_m = 0x00000100,
1996 + CROMW2_a192_b = 9,
1997 + CROMW2_a192_m = 0x00000200,
1998 + CROMW2_a256_b = 10,
1999 + CROMW2_a256_m = 0x00000400,
2000 + CROMW2_md5_b = 11,
2001 + CROMW2_md5_m = 0x00000800,
2002 + CROMW2_s1_b = 12,
2003 + CROMW2_s1_m = 0x00001000,
2004 + CROMW2_s256_b = 13,
2005 + CROMW2_s256_m = 0x00002000,
2006 + CROMW2_pka_b = 14,
2007 + CROMW2_pka_m = 0x00004000,
2008 + CROMW2_exp_b = 15,
2009 + CROMW2_exp_m = 0x00018000,
2010 + CROMW2_exp_8192_v = 0,
2011 + CROMW2_exp_1536_v = 1,
2012 + CROMW2_exp_1024_v = 2,
2013 + CROMW2_exp_512_v = 3,
2014 + CROMW2_rocfg_b = 17,
2015 + CROMW2_rocfg_m = 0x000e0000,
2016 +} ;
2017 +
2018 +#endif // __IDT_CROM_H__
2019 diff -urN linux.old/include/asm-mips/rc32434/ddr.h linux.dev/include/asm-mips/rc32434/ddr.h
2020 --- linux.old/include/asm-mips/rc32434/ddr.h 1970-01-01 01:00:00.000000000 +0100
2021 +++ linux.dev/include/asm-mips/rc32434/ddr.h 2006-07-29 19:31:51.000000000 +0200
2022 @@ -0,0 +1,175 @@
2023 +#ifndef __IDT_DDR_H__
2024 +#define __IDT_DDR_H__
2025 +
2026 +/*******************************************************************************
2027 + *
2028 + * Copyright 2002 Integrated Device Technology, Inc.
2029 + * All rights reserved.
2030 + *
2031 + * DDR register definition.
2032 + *
2033 + * File : $Id: ddr.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
2034 + *
2035 + * Author : ryan.holmQVist@idt.com
2036 + * Date : 20011005
2037 + * Update :
2038 + * $Log: ddr.h,v $
2039 + * Revision 1.2 2002/06/06 18:34:03 astichte
2040 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2041 + *
2042 + * Revision 1.1 2002/05/29 17:33:21 sysarch
2043 + * jba File moved from vcode/include/idt/acacia
2044 + *
2045 + *
2046 + ******************************************************************************/
2047 +
2048 +#include <asm/rc32434/types.h>
2049 +
2050 +enum
2051 +{
2052 + DDR0_PhysicalAddress = 0x18018000,
2053 + DDR_PhysicalAddress = DDR0_PhysicalAddress, // Default
2054 +
2055 + DDR0_VirtualAddress = 0xb8018000,
2056 + DDR_VirtualAddress = DDR0_VirtualAddress, // Default
2057 +} ;
2058 +
2059 +typedef struct DDR_s
2060 +{
2061 + U32 ddrbase ;
2062 + U32 ddrmask ;
2063 + U32 res1;
2064 + U32 res2;
2065 + U32 ddrc ;
2066 + U32 ddrabase ;
2067 + U32 ddramask ;
2068 + U32 ddramap ;
2069 + U32 ddrcust;
2070 + U32 ddrrdc;
2071 + U32 ddrspare;
2072 +} volatile *DDR_t ;
2073 +
2074 +enum
2075 +{
2076 + DDR0BASE_baseaddr_b = 16,
2077 + DDR0BASE_baseaddr_m = 0xffff0000,
2078 +
2079 + DDR0MASK_mask_b = 16,
2080 + DDR0MASK_mask_m = 0xffff0000,
2081 +
2082 + DDR1BASE_baseaddr_b = 16,
2083 + DDR1BASE_baseaddr_m = 0xffff0000,
2084 +
2085 + DDR1MASK_mask_b = 16,
2086 + DDR1MASK_mask_m = 0xffff0000,
2087 +
2088 + DDRC_ata_b = 5,
2089 + DDRC_ata_m = 0x000000E0,
2090 + DDRC_dbw_b = 8,
2091 + DDRC_dbw_m = 0x00000100,
2092 + DDRC_wr_b = 9,
2093 + DDRC_wr_m = 0x00000600,
2094 + DDRC_ps_b = 11,
2095 + DDRC_ps_m = 0x00001800,
2096 + DDRC_dtype_b = 13,
2097 + DDRC_dtype_m = 0x0000e000,
2098 + DDRC_rfc_b = 16,
2099 + DDRC_rfc_m = 0x000f0000,
2100 + DDRC_rp_b = 20,
2101 + DDRC_rp_m = 0x00300000,
2102 + DDRC_ap_b = 22,
2103 + DDRC_ap_m = 0x00400000,
2104 + DDRC_rcd_b = 23,
2105 + DDRC_rcd_m = 0x01800000,
2106 + DDRC_cl_b = 25,
2107 + DDRC_cl_m = 0x06000000,
2108 + DDRC_dbm_b = 27,
2109 + DDRC_dbm_m = 0x08000000,
2110 + DDRC_sds_b = 28,
2111 + DDRC_sds_m = 0x10000000,
2112 + DDRC_atp_b = 29,
2113 + DDRC_atp_m = 0x60000000,
2114 + DDRC_re_b = 31,
2115 + DDRC_re_m = 0x80000000,
2116 +
2117 + DDRRDC_ces_b = 0,
2118 + DDRRDC_ces_m = 0x00000001,
2119 + DDRRDC_ace_b = 1,
2120 + DDRRDC_ace_m = 0x00000002,
2121 +
2122 + DDRABASE_baseaddr_b = 16,
2123 + DDRABASE_baseaddr_m = 0xffff0000,
2124 +
2125 + DDRAMASK_mask_b = 16,
2126 + DDRAMASK_mask_m = 0xffff0000,
2127 +
2128 + DDRAMAP_map_b = 16,
2129 + DDRAMAP_map_m = 0xffff0000,
2130 +
2131 + DDRCUST_cs_b = 0,
2132 + DDRCUST_cs_m = 0x00000003,
2133 + DDRCUST_we_b = 2,
2134 + DDRCUST_we_m = 0x00000004,
2135 + DDRCUST_ras_b = 3,
2136 + DDRCUST_ras_m = 0x00000008,
2137 + DDRCUST_cas_b = 4,
2138 + DDRCUST_cas_m = 0x00000010,
2139 + DDRCUST_cke_b = 5,
2140 + DDRCUST_cke_m = 0x00000020,
2141 + DDRCUST_ba_b = 6,
2142 + DDRCUST_ba_m = 0x000000c0,
2143 +
2144 + RCOUNT_rcount_b = 0,
2145 + RCOUNT_rcount_m = 0x0000ffff,
2146 +
2147 + RCOMPARE_rcompare_b = 0,
2148 + RCOMPARE_rcompare_m = 0x0000ffff,
2149 +
2150 + RTC_ce_b = 0,
2151 + RTC_ce_m = 0x00000001,
2152 + RTC_to_b = 1,
2153 + RTC_to_m = 0x00000002,
2154 + RTC_rqe_b = 2,
2155 + RTC_rqe_m = 0x00000004,
2156 +
2157 + DDRDQSC_dm_b = 0,
2158 + DDRDQSC_dm_m = 0x00000003,
2159 + DDRDQSC_dqsbs_b = 2,
2160 + DDRDQSC_dqsbs_m = 0x000000fc,
2161 + DDRDQSC_db_b = 8,
2162 + DDRDQSC_db_m = 0x00000100,
2163 + DDRDQSC_dbsp_b = 9,
2164 + DDRDQSC_dbsp_m = 0x01fffe00,
2165 + DDRDQSC_bdp_b = 25,
2166 + DDRDQSC_bdp_m = 0x7e000000,
2167 +
2168 + DDRDLLC_eao_b = 0,
2169 + DDRDLLC_eao_m = 0x00000001,
2170 + DDRDLLC_eo_b = 1,
2171 + DDRDLLC_eo_m = 0x0000003e,
2172 + DDRDLLC_fs_b = 6,
2173 + DDRDLLC_fs_m = 0x000000c0,
2174 + DDRDLLC_as_b = 8,
2175 + DDRDLLC_as_m = 0x00000700,
2176 + DDRDLLC_sp_b = 11,
2177 + DDRDLLC_sp_m = 0x001ff800,
2178 +
2179 + DDRDLLFC_men_b = 0,
2180 + DDRDLLFC_men_m = 0x00000001,
2181 + DDRDLLFC_aen_b = 1,
2182 + DDRDLLFC_aen_m = 0x00000002,
2183 + DDRDLLFC_ff_b = 2,
2184 + DDRDLLFC_ff_m = 0x00000004,
2185 +
2186 + DDRDLLTA_addr_b = 2,
2187 + DDRDLLTA_addr_m = 0xfffffffc,
2188 +
2189 + DDRDLLED_dbe_b = 0,
2190 + DDRDLLED_dbe_m = 0x00000001,
2191 + DDRDLLED_dte_b = 1,
2192 + DDRDLLED_dte_m = 0x00000002,
2193 +
2194 +
2195 +} ;
2196 +
2197 +#endif // __IDT_DDR_H__
2198 diff -urN linux.old/include/asm-mips/rc32434/dev.h linux.dev/include/asm-mips/rc32434/dev.h
2199 --- linux.old/include/asm-mips/rc32434/dev.h 1970-01-01 01:00:00.000000000 +0100
2200 +++ linux.dev/include/asm-mips/rc32434/dev.h 2006-07-29 19:31:51.000000000 +0200
2201 @@ -0,0 +1,134 @@
2202 +#ifndef __IDT_DEV_H__
2203 +#define __IDT_DEV_H__
2204 +
2205 +/*******************************************************************************
2206 + *
2207 + * Copyright 2002 Integrated Device Technology, Inc.
2208 + * All rights reserved.
2209 + *
2210 + * Device Controller register definition.
2211 + *
2212 + * File : $Id: dev.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
2213 + *
2214 + * Author : John.Ahrens@idt.com
2215 + * Date : 200112013
2216 + * Update :
2217 + * $Log: dev.h,v $
2218 + * Revision 1.2 2002/06/06 18:34:03 astichte
2219 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2220 + *
2221 + * Revision 1.1 2002/05/29 17:33:21 sysarch
2222 + * jba File moved from vcode/include/idt/acacia
2223 + *
2224 + *
2225 + ******************************************************************************/
2226 +
2227 +#include <asm/rc32434/types.h>
2228 +
2229 +enum
2230 +{
2231 + DEV0_PhysicalAddress = 0x18010000,
2232 + DEV_PhysicalAddress = DEV0_PhysicalAddress, // Default
2233 +
2234 + DEV0_VirtualAddress = 0xb8010000,
2235 + DEV_VirtualAddress = DEV0_VirtualAddress, // Default
2236 +} ;
2237 +
2238 +typedef struct DEVICE_s
2239 +{
2240 + U32 devbase ; // Device Base
2241 + U32 devmask ; // Device Mask
2242 + U32 devc ; // Device Control
2243 + U32 devtc ; // Device Timing Control
2244 +} volatile *DEVICE_t ;
2245 +
2246 +enum
2247 +{
2248 + DEV_Count = 3,
2249 +} ;
2250 +
2251 +typedef struct DEV_s
2252 +{
2253 + struct DEVICE_s dev [DEV_Count] ;
2254 + U32 btcs ; // Bus timeout control / status
2255 + U32 btcompare ; // Compare
2256 + U32 btaddr ; // Timeout address.
2257 + U32 devdacs ; // Decoupled access control.
2258 + U32 devdaa ; // Decoupled access address.
2259 + U32 devdad ; // Decoupled access address.
2260 + U32 devspare ; // spare.
2261 +} volatile *DEV_t ;
2262 +
2263 +enum
2264 +{
2265 + DEVBASE_baseaddr_b = 16,
2266 + DEVBASE_baseaddr_m = 0xffff0000,
2267 + DEVMASK_mask_b = 16,
2268 + DEVMASK_mask_m = 0xffff0000,
2269 +
2270 + DEVC_ds_b = 0,
2271 + DEVC_ds_m = 0x00000003,
2272 + DEVC_ds_8_v = 0, // 8-bit device.
2273 + DEVC_ds_16_v = 1, // reserved
2274 + DEVC_ds_res_v = 2, // reserved.
2275 + DEVC_ds_res2_v = 3, // reserved.
2276 + DEVC_be_b = 2,
2277 + DEVC_be_m = 0x00000004,
2278 + DEVC_wp_b = 3,
2279 + DEVC_wp_m = 0x00000008,
2280 + DEVC_csd_b = 4,
2281 + DEVC_csd_m = 0x000000f0,
2282 + DEVC_oed_b = 8,
2283 + DEVC_oed_m = 0x00000f00,
2284 + DEVC_bwd_b = 12,
2285 + DEVC_bwd_m = 0x0000f000,
2286 + DEVC_rws_b = 16,
2287 + DEVC_rws_m = 0x003f0000,
2288 + DEVC_wws_b = 22,
2289 + DEVC_wws_m = 0x0fc00000,
2290 + DEVC_bre_b = 28,
2291 + DEVC_bre_m = 0x10000000,
2292 + DEVC_bwe_b = 29,
2293 + DEVC_bwe_m = 0x20000000,
2294 + DEVC_wam_b = 30,
2295 + DEVC_wam_m = 0x40000000,
2296 +
2297 + DEVTC_prd_b = 0,
2298 + DEVTC_prd_m = 0x0000000f,
2299 + DEVTC_pwd_b = 4,
2300 + DEVTC_pwd_m = 0x000000f0,
2301 + DEVTC_wdh_b = 8,
2302 + DEVTC_wdh_m = 0x00000700,
2303 + DEVTC_csh_b = 11,
2304 + DEVTC_csh_m = 0x00001800,
2305 +
2306 + BTCS_tt_b = 0,
2307 + BTCS_tt_m = 0x00000001,
2308 + BTCS_tt_write = 0,
2309 + BTCS_tt_read = 1,
2310 + BTCS_bto_b = 1, // In btcs
2311 + BTCS_bto_m = 0x00000002, // In btcs
2312 + BTCS_bte_b = 2, // In btcs
2313 + BTCS_bte_m = 0x00000004, // In btcs
2314 +
2315 + BTCOMPARE_compare_b = 0, // In btcompare
2316 + BTCOMPARE_compare_m = 0x0000ffff, // In btcompare
2317 +
2318 + DEVDACS_op_b = 0, // In devdacs
2319 + DEVDACS_op_m = 0x00000001, // In devdacs
2320 + DEVDACS_op_write_v = 0,
2321 + DEVDACS_op_read_v = 1,
2322 + DEVDACS_size_b = 1, // In devdacs
2323 + DEVDACS_size_m = 0x00000006, // In devdacs
2324 + DEVDACS_size_byte_v = 0,
2325 + DEVDACS_size_halfword = 1,
2326 + DEVDACS_size_triplebyte = 2,
2327 + DEVDACS_size_word = 3,
2328 + DEVDACS_err_b = 3, // In devdacs
2329 + DEVDACS_err_m = 0x00000008, // In devdacs
2330 + DEVDACS_f_b = 4, // In devdacs
2331 + DEVDACS_f_m = 0x00000010, // In devdacs
2332 +} ;
2333 +
2334 +#endif //__IDT_DEV_H__
2335 +
2336 diff -urN linux.old/include/asm-mips/rc32434/dma.h linux.dev/include/asm-mips/rc32434/dma.h
2337 --- linux.old/include/asm-mips/rc32434/dma.h 1970-01-01 01:00:00.000000000 +0100
2338 +++ linux.dev/include/asm-mips/rc32434/dma.h 2006-07-29 19:31:51.000000000 +0200
2339 @@ -0,0 +1,202 @@
2340 +#ifndef __IDT_DMA_H__
2341 +#define __IDT_DMA_H__
2342 +
2343 +/*******************************************************************************
2344 + *
2345 + * Copyright 2002 Integrated Device Technology, Inc.
2346 + * All rights reserved.
2347 + *
2348 + * DMA register definition.
2349 + *
2350 + * File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
2351 + *
2352 + * Author : ryan.holmQVist@idt.com
2353 + * Date : 20011005
2354 + * Update :
2355 + * $Log: dma.h,v $
2356 + * Revision 1.3 2002/06/06 18:34:03 astichte
2357 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2358 + *
2359 + * Revision 1.2 2002/06/05 18:30:46 astichte
2360 + * Removed IDTField
2361 + *
2362 + * Revision 1.1 2002/05/29 17:33:21 sysarch
2363 + * jba File moved from vcode/include/idt/acacia
2364 + *
2365 + *
2366 + ******************************************************************************/
2367 +
2368 +#include <asm/rc32434/types.h>
2369 +enum
2370 +{
2371 + DMA0_PhysicalAddress = 0x18040000,
2372 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
2373 +
2374 + DMA0_VirtualAddress = 0xb8040000,
2375 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
2376 +} ;
2377 +
2378 +/*
2379 + * DMA descriptor (in physical memory).
2380 + */
2381 +
2382 +typedef struct DMAD_s
2383 +{
2384 + U32 control ; // Control. use DMAD_*
2385 + U32 ca ; // Current Address.
2386 + U32 devcs ; // Device control and status.
2387 + U32 link ; // Next descriptor in chain.
2388 +} volatile *DMAD_t ;
2389 +
2390 +enum
2391 +{
2392 + DMAD_size = sizeof (struct DMAD_s),
2393 + DMAD_count_b = 0, // in DMAD_t -> control
2394 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
2395 + DMAD_ds_b = 20, // in DMAD_t -> control
2396 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
2397 + DMAD_ds_ethRcv_v = 0,
2398 + DMAD_ds_ethXmt_v = 0,
2399 + DMAD_ds_memToFifo_v = 0,
2400 + DMAD_ds_fifoToMem_v = 0,
2401 + DMAD_ds_pciToMem_v = 0,
2402 + DMAD_ds_memToPci_v = 0,
2403 +
2404 + DMAD_devcmd_b = 22, // in DMAD_t -> control
2405 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
2406 + DMAD_devcmd_byte_v = 0, //memory-to-memory
2407 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
2408 + DMAD_devcmd_word_v = 2, //memory-to-memory
2409 + DMAD_devcmd_2words_v = 3, //memory-to-memory
2410 + DMAD_devcmd_4words_v = 4, //memory-to-memory
2411 + DMAD_devcmd_6words_v = 5, //memory-to-memory
2412 + DMAD_devcmd_8words_v = 6, //memory-to-memory
2413 + DMAD_devcmd_16words_v = 7, //memory-to-memory
2414 + DMAD_cof_b = 25, // chain on finished
2415 + DMAD_cof_m = 0x02000000, //
2416 + DMAD_cod_b = 26, // chain on done
2417 + DMAD_cod_m = 0x04000000, //
2418 + DMAD_iof_b = 27, // interrupt on finished
2419 + DMAD_iof_m = 0x08000000, //
2420 + DMAD_iod_b = 28, // interrupt on done
2421 + DMAD_iod_m = 0x10000000, //
2422 + DMAD_t_b = 29, // terminated
2423 + DMAD_t_m = 0x20000000, //
2424 + DMAD_d_b = 30, // done
2425 + DMAD_d_m = 0x40000000, //
2426 + DMAD_f_b = 31, // finished
2427 + DMAD_f_m = 0x80000000, //
2428 +} ;
2429 +
2430 +/*
2431 + * DMA register (within Internal Register Map).
2432 + */
2433 +
2434 +struct DMA_Chan_s
2435 +{
2436 + U32 dmac ; // Control.
2437 + U32 dmas ; // Status.
2438 + U32 dmasm ; // Mask.
2439 + U32 dmadptr ; // Descriptor pointer.
2440 + U32 dmandptr ; // Next descriptor pointer.
2441 +};
2442 +
2443 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
2444 +
2445 +//DMA_Channels use DMACH_count instead
2446 +
2447 +enum
2448 +{
2449 + DMAC_run_b = 0, //
2450 + DMAC_run_m = 0x00000001, //
2451 + DMAC_dm_b = 1, // done mask
2452 + DMAC_dm_m = 0x00000002, //
2453 + DMAC_mode_b = 2, //
2454 + DMAC_mode_m = 0x0000000c, //
2455 + DMAC_mode_auto_v = 0,
2456 + DMAC_mode_burst_v = 1,
2457 + DMAC_mode_transfer_v = 2, //usually used
2458 + DMAC_mode_reserved_v = 3,
2459 + DMAC_a_b = 4, //
2460 + DMAC_a_m = 0x00000010, //
2461 +
2462 + DMAS_f_b = 0, // finished (sticky)
2463 + DMAS_f_m = 0x00000001, //
2464 + DMAS_d_b = 1, // done (sticky)
2465 + DMAS_d_m = 0x00000002, //
2466 + DMAS_c_b = 2, // chain (sticky)
2467 + DMAS_c_m = 0x00000004, //
2468 + DMAS_e_b = 3, // error (sticky)
2469 + DMAS_e_m = 0x00000008, //
2470 + DMAS_h_b = 4, // halt (sticky)
2471 + DMAS_h_m = 0x00000010, //
2472 +
2473 + DMASM_f_b = 0, // finished (1=mask)
2474 + DMASM_f_m = 0x00000001, //
2475 + DMASM_d_b = 1, // done (1=mask)
2476 + DMASM_d_m = 0x00000002, //
2477 + DMASM_c_b = 2, // chain (1=mask)
2478 + DMASM_c_m = 0x00000004, //
2479 + DMASM_e_b = 3, // error (1=mask)
2480 + DMASM_e_m = 0x00000008, //
2481 + DMASM_h_b = 4, // halt (1=mask)
2482 + DMASM_h_m = 0x00000010, //
2483 +} ;
2484 +
2485 +/*
2486 + * DMA channel definitions
2487 + */
2488 +
2489 +enum
2490 +{
2491 + DMACH_ethRcv = 0,
2492 + DMACH_ethXmt = 1,
2493 + DMACH_memToFifo = 2,
2494 + DMACH_fifoToMem = 3,
2495 + DMACH_pciToMem = 4,
2496 + DMACH_memToPci = 5,
2497 +
2498 + DMACH_count //must be last
2499 +};
2500 +
2501 +
2502 +typedef struct DMAC_s
2503 +{
2504 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
2505 +} volatile *DMA_t ;
2506 +
2507 +
2508 +/*
2509 + * External DMA parameters
2510 +*/
2511 +#if 0
2512 +enum
2513 +{
2514 + DMADEVCMD_ts_b = 0, // ts field in devcmd
2515 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
2516 + DMADEVCMD_ts_byte_v = 0,
2517 + DMADEVCMD_ts_halfword_v = 1,
2518 + DMADEVCMD_ts_word_v = 2,
2519 + DMADEVCMD_ts_2word_v = 3,
2520 + DMADEVCMD_ts_4word_v = 4,
2521 + DMADEVCMD_ts_6word_v = 5,
2522 + DMADEVCMD_ts_8word_v = 6,
2523 + DMADEVCMD_ts_16word_v = 7
2524 +};
2525 +#endif
2526 +
2527 +#if 1 // aws - Compatibility.
2528 +# define EXTDMA_ts_b DMADEVCMD_ts_b
2529 +# define EXTDMA_ts_m DMADEVCMD_ts_m
2530 +# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
2531 +# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
2532 +# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
2533 +# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
2534 +# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
2535 +# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
2536 +# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
2537 +# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
2538 +#endif // aws - Compatibility.
2539 +
2540 +#endif // __IDT_DMA_H__
2541 +
2542 diff -urN linux.old/include/asm-mips/rc32434/dma_v.h linux.dev/include/asm-mips/rc32434/dma_v.h
2543 --- linux.old/include/asm-mips/rc32434/dma_v.h 1970-01-01 01:00:00.000000000 +0100
2544 +++ linux.dev/include/asm-mips/rc32434/dma_v.h 2006-07-29 19:31:51.000000000 +0200
2545 @@ -0,0 +1,73 @@
2546 +#ifndef __IDT_DMA_V_H__
2547 +#define __IDT_DMA_V_H__
2548 +
2549 +/*******************************************************************************
2550 + *
2551 + * Copyright 2002 Integrated Device Technology, Inc.
2552 + * All rights reserved.
2553 + *
2554 + * DMA register definition.
2555 + *
2556 + * File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
2557 + *
2558 + * Author : ryan.holmQVist@idt.com
2559 + * Date : 20011005
2560 + * Update :
2561 + * $Log: dma.h,v $
2562 + * Revision 1.3 2002/06/06 18:34:03 astichte
2563 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2564 + *
2565 + * Revision 1.2 2002/06/05 18:30:46 astichte
2566 + * Removed IDTField
2567 + *
2568 + * Revision 1.1 2002/05/29 17:33:21 sysarch
2569 + * jba File moved from vcode/include/idt/acacia
2570 + *
2571 + *
2572 + ******************************************************************************/
2573 +#include <asm/rc32434/types.h>
2574 +#include <asm/rc32434/dma.h>
2575 +#include <asm/rc32434/rc32434.h>
2576 +#define DMA_CHAN_OFFSET 0x14
2577 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
2578 +#define DMA_COUNT(count) \
2579 + ((count) & DMAD_count_m)
2580 +
2581 +#define DMA_HALT_TIMEOUT 500
2582 +
2583 +
2584 +static inline int rc32434_halt_dma(DMA_Chan_t ch)
2585 +{
2586 + int timeout=1;
2587 + if (local_readl(&ch->dmac) & DMAC_run_m) {
2588 + local_writel(0, &ch->dmac);
2589 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
2590 + if (local_readl(&ch->dmas) & DMAS_h_m) {
2591 + local_writel(0, &ch->dmas);
2592 + break;
2593 + }
2594 + }
2595 + }
2596 +
2597 + return timeout ? 0 : 1;
2598 +}
2599 +
2600 +static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
2601 +{
2602 + local_writel(0, &ch->dmandptr);
2603 + local_writel(dma_addr, &ch->dmadptr);
2604 +}
2605 +
2606 +static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
2607 +{
2608 + local_writel(dma_addr, &ch->dmandptr);
2609 +}
2610 +
2611 +#endif // __IDT_DMA_V_H__
2612 +
2613 +
2614 +
2615 +
2616 +
2617 +
2618 +
2619 diff -urN linux.old/include/asm-mips/rc32434/eth.h linux.dev/include/asm-mips/rc32434/eth.h
2620 --- linux.old/include/asm-mips/rc32434/eth.h 1970-01-01 01:00:00.000000000 +0100
2621 +++ linux.dev/include/asm-mips/rc32434/eth.h 2006-07-29 19:31:51.000000000 +0200
2622 @@ -0,0 +1,322 @@
2623 +#ifndef __IDT_ETH_H__
2624 +#define __IDT_ETH_H__
2625 +
2626 +/*******************************************************************************
2627 + *
2628 + * Copyright 2002 Integrated Device Technology, Inc.
2629 + * All rights reserved.
2630 + *
2631 + * Ethernet register definition.
2632 + *
2633 + * File : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
2634 + *
2635 + * Author : Allen.Stichter@idt.com
2636 + * Date : 20020605
2637 + * Update :
2638 + * $Log: eth.h,v $
2639 + * Revision 1.3 2002/06/06 18:34:04 astichte
2640 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2641 + *
2642 + * Revision 1.2 2002/06/05 18:19:46 astichte
2643 + * Added
2644 + *
2645 + * Revision 1.1 2002/05/29 17:33:22 sysarch
2646 + * jba File moved from vcode/include/idt/acacia
2647 + *
2648 + ******************************************************************************/
2649 +
2650 +#include <asm/rc32434/types.h>
2651 +
2652 +enum
2653 +{
2654 + ETH0_PhysicalAddress = 0x18060000,
2655 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
2656 +
2657 + ETH0_VirtualAddress = 0xb8060000,
2658 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
2659 +} ;
2660 +
2661 +typedef struct
2662 +{
2663 + U32 ethintfc ;
2664 + U32 ethfifott ;
2665 + U32 etharc ;
2666 + U32 ethhash0 ;
2667 + U32 ethhash1 ;
2668 + U32 ethu0 [4] ; // Reserved.
2669 + U32 ethpfs ;
2670 + U32 ethmcp ;
2671 + U32 eth_u1 [10] ; // Reserved.
2672 + U32 ethspare ;
2673 + U32 eth_u2 [42] ; // Reserved.
2674 + U32 ethsal0 ;
2675 + U32 ethsah0 ;
2676 + U32 ethsal1 ;
2677 + U32 ethsah1 ;
2678 + U32 ethsal2 ;
2679 + U32 ethsah2 ;
2680 + U32 ethsal3 ;
2681 + U32 ethsah3 ;
2682 + U32 ethrbc ;
2683 + U32 ethrpc ;
2684 + U32 ethrupc ;
2685 + U32 ethrfc ;
2686 + U32 ethtbc ;
2687 + U32 ethgpf ;
2688 + U32 eth_u9 [50] ; // Reserved.
2689 + U32 ethmac1 ;
2690 + U32 ethmac2 ;
2691 + U32 ethipgt ;
2692 + U32 ethipgr ;
2693 + U32 ethclrt ;
2694 + U32 ethmaxf ;
2695 + U32 eth_u10 ; // Reserved.
2696 + U32 ethmtest ;
2697 + U32 miimcfg ;
2698 + U32 miimcmd ;
2699 + U32 miimaddr ;
2700 + U32 miimwtd ;
2701 + U32 miimrdd ;
2702 + U32 miimind ;
2703 + U32 eth_u11 ; // Reserved.
2704 + U32 eth_u12 ; // Reserved.
2705 + U32 ethcfsa0 ;
2706 + U32 ethcfsa1 ;
2707 + U32 ethcfsa2 ;
2708 +} volatile *ETH_t;
2709 +
2710 +enum
2711 +{
2712 + ETHINTFC_en_b = 0,
2713 + ETHINTFC_en_m = 0x00000001,
2714 + ETHINTFC_its_b = 1,
2715 + ETHINTFC_its_m = 0x00000002,
2716 + ETHINTFC_rip_b = 2,
2717 + ETHINTFC_rip_m = 0x00000004,
2718 + ETHINTFC_jam_b = 3,
2719 + ETHINTFC_jam_m = 0x00000008,
2720 + ETHINTFC_ovr_b = 4,
2721 + ETHINTFC_ovr_m = 0x00000010,
2722 + ETHINTFC_und_b = 5,
2723 + ETHINTFC_und_m = 0x00000020,
2724 + ETHINTFC_iom_b = 6,
2725 + ETHINTFC_iom_m = 0x000000c0,
2726 +
2727 + ETHFIFOTT_tth_b = 0,
2728 + ETHFIFOTT_tth_m = 0x0000007f,
2729 +
2730 + ETHARC_pro_b = 0,
2731 + ETHARC_pro_m = 0x00000001,
2732 + ETHARC_am_b = 1,
2733 + ETHARC_am_m = 0x00000002,
2734 + ETHARC_afm_b = 2,
2735 + ETHARC_afm_m = 0x00000004,
2736 + ETHARC_ab_b = 3,
2737 + ETHARC_ab_m = 0x00000008,
2738 +
2739 + ETHSAL_byte5_b = 0,
2740 + ETHSAL_byte5_m = 0x000000ff,
2741 + ETHSAL_byte4_b = 8,
2742 + ETHSAL_byte4_m = 0x0000ff00,
2743 + ETHSAL_byte3_b = 16,
2744 + ETHSAL_byte3_m = 0x00ff0000,
2745 + ETHSAL_byte2_b = 24,
2746 + ETHSAL_byte2_m = 0xff000000,
2747 +
2748 + ETHSAH_byte1_b = 0,
2749 + ETHSAH_byte1_m = 0x000000ff,
2750 + ETHSAH_byte0_b = 8,
2751 + ETHSAH_byte0_m = 0x0000ff00,
2752 +
2753 + ETHGPF_ptv_b = 0,
2754 + ETHGPF_ptv_m = 0x0000ffff,
2755 +
2756 + ETHPFS_pfd_b = 0,
2757 + ETHPFS_pfd_m = 0x00000001,
2758 +
2759 + ETHCFSA0_cfsa4_b = 0,
2760 + ETHCFSA0_cfsa4_m = 0x000000ff,
2761 + ETHCFSA0_cfsa5_b = 8,
2762 + ETHCFSA0_cfsa5_m = 0x0000ff00,
2763 +
2764 + ETHCFSA1_cfsa2_b = 0,
2765 + ETHCFSA1_cfsa2_m = 0x000000ff,
2766 + ETHCFSA1_cfsa3_b = 8,
2767 + ETHCFSA1_cfsa3_m = 0x0000ff00,
2768 +
2769 + ETHCFSA2_cfsa0_b = 0,
2770 + ETHCFSA2_cfsa0_m = 0x000000ff,
2771 + ETHCFSA2_cfsa1_b = 8,
2772 + ETHCFSA2_cfsa1_m = 0x0000ff00,
2773 +
2774 + ETHMAC1_re_b = 0,
2775 + ETHMAC1_re_m = 0x00000001,
2776 + ETHMAC1_paf_b = 1,
2777 + ETHMAC1_paf_m = 0x00000002,
2778 + ETHMAC1_rfc_b = 2,
2779 + ETHMAC1_rfc_m = 0x00000004,
2780 + ETHMAC1_tfc_b = 3,
2781 + ETHMAC1_tfc_m = 0x00000008,
2782 + ETHMAC1_lb_b = 4,
2783 + ETHMAC1_lb_m = 0x00000010,
2784 + ETHMAC1_mr_b = 31,
2785 + ETHMAC1_mr_m = 0x80000000,
2786 +
2787 + ETHMAC2_fd_b = 0,
2788 + ETHMAC2_fd_m = 0x00000001,
2789 + ETHMAC2_flc_b = 1,
2790 + ETHMAC2_flc_m = 0x00000002,
2791 + ETHMAC2_hfe_b = 2,
2792 + ETHMAC2_hfe_m = 0x00000004,
2793 + ETHMAC2_dc_b = 3,
2794 + ETHMAC2_dc_m = 0x00000008,
2795 + ETHMAC2_cen_b = 4,
2796 + ETHMAC2_cen_m = 0x00000010,
2797 + ETHMAC2_pe_b = 5,
2798 + ETHMAC2_pe_m = 0x00000020,
2799 + ETHMAC2_vpe_b = 6,
2800 + ETHMAC2_vpe_m = 0x00000040,
2801 + ETHMAC2_ape_b = 7,
2802 + ETHMAC2_ape_m = 0x00000080,
2803 + ETHMAC2_ppe_b = 8,
2804 + ETHMAC2_ppe_m = 0x00000100,
2805 + ETHMAC2_lpe_b = 9,
2806 + ETHMAC2_lpe_m = 0x00000200,
2807 + ETHMAC2_nb_b = 12,
2808 + ETHMAC2_nb_m = 0x00001000,
2809 + ETHMAC2_bp_b = 13,
2810 + ETHMAC2_bp_m = 0x00002000,
2811 + ETHMAC2_ed_b = 14,
2812 + ETHMAC2_ed_m = 0x00004000,
2813 +
2814 + ETHIPGT_ipgt_b = 0,
2815 + ETHIPGT_ipgt_m = 0x0000007f,
2816 +
2817 + ETHIPGR_ipgr2_b = 0,
2818 + ETHIPGR_ipgr2_m = 0x0000007f,
2819 + ETHIPGR_ipgr1_b = 8,
2820 + ETHIPGR_ipgr1_m = 0x00007f00,
2821 +
2822 + ETHCLRT_maxret_b = 0,
2823 + ETHCLRT_maxret_m = 0x0000000f,
2824 + ETHCLRT_colwin_b = 8,
2825 + ETHCLRT_colwin_m = 0x00003f00,
2826 +
2827 + ETHMAXF_maxf_b = 0,
2828 + ETHMAXF_maxf_m = 0x0000ffff,
2829 +
2830 + ETHMTEST_tb_b = 2,
2831 + ETHMTEST_tb_m = 0x00000004,
2832 +
2833 + ETHMCP_div_b = 0,
2834 + ETHMCP_div_m = 0x000000ff,
2835 +
2836 + MIIMCFG_rsv_b = 0,
2837 + MIIMCFG_rsv_m = 0x0000000c,
2838 +
2839 + MIIMCMD_rd_b = 0,
2840 + MIIMCMD_rd_m = 0x00000001,
2841 + MIIMCMD_scn_b = 1,
2842 + MIIMCMD_scn_m = 0x00000002,
2843 +
2844 + MIIMADDR_regaddr_b = 0,
2845 + MIIMADDR_regaddr_m = 0x0000001f,
2846 + MIIMADDR_phyaddr_b = 8,
2847 + MIIMADDR_phyaddr_m = 0x00001f00,
2848 +
2849 + MIIMWTD_wdata_b = 0,
2850 + MIIMWTD_wdata_m = 0x0000ffff,
2851 +
2852 + MIIMRDD_rdata_b = 0,
2853 + MIIMRDD_rdata_m = 0x0000ffff,
2854 +
2855 + MIIMIND_bsy_b = 0,
2856 + MIIMIND_bsy_m = 0x00000001,
2857 + MIIMIND_scn_b = 1,
2858 + MIIMIND_scn_m = 0x00000002,
2859 + MIIMIND_nv_b = 2,
2860 + MIIMIND_nv_m = 0x00000004,
2861 +
2862 +} ;
2863 +
2864 +/*
2865 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
2866 + */
2867 +enum
2868 +{
2869 + ETHRX_fd_b = 0,
2870 + ETHRX_fd_m = 0x00000001,
2871 + ETHRX_ld_b = 1,
2872 + ETHRX_ld_m = 0x00000002,
2873 + ETHRX_rok_b = 2,
2874 + ETHRX_rok_m = 0x00000004,
2875 + ETHRX_fm_b = 3,
2876 + ETHRX_fm_m = 0x00000008,
2877 + ETHRX_mp_b = 4,
2878 + ETHRX_mp_m = 0x00000010,
2879 + ETHRX_bp_b = 5,
2880 + ETHRX_bp_m = 0x00000020,
2881 + ETHRX_vlt_b = 6,
2882 + ETHRX_vlt_m = 0x00000040,
2883 + ETHRX_cf_b = 7,
2884 + ETHRX_cf_m = 0x00000080,
2885 + ETHRX_ovr_b = 8,
2886 + ETHRX_ovr_m = 0x00000100,
2887 + ETHRX_crc_b = 9,
2888 + ETHRX_crc_m = 0x00000200,
2889 + ETHRX_cv_b = 10,
2890 + ETHRX_cv_m = 0x00000400,
2891 + ETHRX_db_b = 11,
2892 + ETHRX_db_m = 0x00000800,
2893 + ETHRX_le_b = 12,
2894 + ETHRX_le_m = 0x00001000,
2895 + ETHRX_lor_b = 13,
2896 + ETHRX_lor_m = 0x00002000,
2897 + ETHRX_ces_b = 14,
2898 + ETHRX_ces_m = 0x00004000,
2899 + ETHRX_length_b = 16,
2900 + ETHRX_length_m = 0xffff0000,
2901 +
2902 + ETHTX_fd_b = 0,
2903 + ETHTX_fd_m = 0x00000001,
2904 + ETHTX_ld_b = 1,
2905 + ETHTX_ld_m = 0x00000002,
2906 + ETHTX_oen_b = 2,
2907 + ETHTX_oen_m = 0x00000004,
2908 + ETHTX_pen_b = 3,
2909 + ETHTX_pen_m = 0x00000008,
2910 + ETHTX_cen_b = 4,
2911 + ETHTX_cen_m = 0x00000010,
2912 + ETHTX_hen_b = 5,
2913 + ETHTX_hen_m = 0x00000020,
2914 + ETHTX_tok_b = 6,
2915 + ETHTX_tok_m = 0x00000040,
2916 + ETHTX_mp_b = 7,
2917 + ETHTX_mp_m = 0x00000080,
2918 + ETHTX_bp_b = 8,
2919 + ETHTX_bp_m = 0x00000100,
2920 + ETHTX_und_b = 9,
2921 + ETHTX_und_m = 0x00000200,
2922 + ETHTX_of_b = 10,
2923 + ETHTX_of_m = 0x00000400,
2924 + ETHTX_ed_b = 11,
2925 + ETHTX_ed_m = 0x00000800,
2926 + ETHTX_ec_b = 12,
2927 + ETHTX_ec_m = 0x00001000,
2928 + ETHTX_lc_b = 13,
2929 + ETHTX_lc_m = 0x00002000,
2930 + ETHTX_td_b = 14,
2931 + ETHTX_td_m = 0x00004000,
2932 + ETHTX_crc_b = 15,
2933 + ETHTX_crc_m = 0x00008000,
2934 + ETHTX_le_b = 16,
2935 + ETHTX_le_m = 0x00010000,
2936 + ETHTX_cc_b = 17,
2937 + ETHTX_cc_m = 0x001E0000,
2938 +} ;
2939 +
2940 +#endif // __IDT_ETH_H__
2941 +
2942 +
2943 +
2944 +
2945 diff -urN linux.old/include/asm-mips/rc32434/eth_v.h linux.dev/include/asm-mips/rc32434/eth_v.h
2946 --- linux.old/include/asm-mips/rc32434/eth_v.h 1970-01-01 01:00:00.000000000 +0100
2947 +++ linux.dev/include/asm-mips/rc32434/eth_v.h 2006-07-29 19:31:51.000000000 +0200
2948 @@ -0,0 +1,64 @@
2949 +#ifndef __IDT_ETH_V_H__
2950 +#define __IDT_ETH_V_H__
2951 +
2952 +/*******************************************************************************
2953 + *
2954 + * Copyright 2002 Integrated Device Technology, Inc.
2955 + * All rights reserved.
2956 + *
2957 + * Ethernet register definition.
2958 + *
2959 + * File : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
2960 + *
2961 + * Author : Allen.Stichter@idt.com
2962 + * Date : 20020605
2963 + * Update :
2964 + * $Log: eth.h,v $
2965 + * Revision 1.3 2002/06/06 18:34:04 astichte
2966 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2967 + *
2968 + * Revision 1.2 2002/06/05 18:19:46 astichte
2969 + * Added
2970 + *
2971 + * Revision 1.1 2002/05/29 17:33:22 sysarch
2972 + * jba File moved from vcode/include/idt/acacia
2973 + *
2974 + ******************************************************************************/
2975 +
2976 +#include <asm/rc32434/types.h>
2977 +#include <asm/rc32434/eth.h>
2978 +
2979 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
2980 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
2981 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
2982 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
2983 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
2984 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
2985 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
2986 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
2987 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
2988 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
2989 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
2990 +
2991 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
2992 +
2993 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
2994 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
2995 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
2996 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
2997 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
2998 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
2999 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
3000 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
3001 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
3002 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
3003 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
3004 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
3005 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
3006 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
3007 +#endif // __IDT_ETH_V_H__
3008 +
3009 +
3010 +
3011 +
3012 +
3013 diff -urN linux.old/include/asm-mips/rc32434/gpio.h linux.dev/include/asm-mips/rc32434/gpio.h
3014 --- linux.old/include/asm-mips/rc32434/gpio.h 1970-01-01 01:00:00.000000000 +0100
3015 +++ linux.dev/include/asm-mips/rc32434/gpio.h 2006-07-29 19:31:51.000000000 +0200
3016 @@ -0,0 +1,182 @@
3017 +#ifndef __IDT_GPIO_H__
3018 +#define __IDT_GPIO_H__
3019 +
3020 +/*******************************************************************************
3021 + *
3022 + * Copyright 2002 Integrated Device Technology, Inc.
3023 + * All rights reserved.
3024 + *
3025 + * GPIO register definition.
3026 + *
3027 + * File : $Id: gpio.h,v 1.2 2002/06/06 18:34:04 astichte Exp $
3028 + *
3029 + * Author : ryan.holmQVist@idt.com
3030 + * Date : 20011005
3031 + * Update :
3032 + * $Log: gpio.h,v $
3033 + * Revision 1.2 2002/06/06 18:34:04 astichte
3034 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
3035 + *
3036 + * Revision 1.1 2002/05/29 17:33:22 sysarch
3037 + * jba File moved from vcode/include/idt/acacia
3038 + *
3039 + *
3040 + ******************************************************************************/
3041 +
3042 +#include <asm/rc32434/types.h>
3043 +enum
3044 +{
3045 + GPIO0_PhysicalAddress = 0x18050000,
3046 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
3047 +
3048 + GPIO0_VirtualAddress = 0xb8050000,
3049 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
3050 +} ;
3051 +
3052 +typedef struct
3053 +{
3054 + U32 gpiofunc; /* GPIO Function Register
3055 + * gpiofunc[x]==0 bit = gpio
3056 + * func[x]==1 bit = altfunc
3057 + */
3058 + U32 gpiocfg; /* GPIO Configuration Register
3059 + * gpiocfg[x]==0 bit = input
3060 + * gpiocfg[x]==1 bit = output
3061 + */
3062 + U32 gpiod; /* GPIO Data Register
3063 + * gpiod[x] read/write gpio pinX status
3064 + */
3065 + U32 gpioilevel; /* GPIO Interrupt Status Register
3066 + * interrupt level (see gpioistat)
3067 + */
3068 + U32 gpioistat; /* Gpio Interrupt Status Register
3069 + * istat[x] = (gpiod[x] == level[x])
3070 + * cleared in ISR (STICKY bits)
3071 + */
3072 + U32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
3073 +} volatile * GPIO_t ;
3074 +
3075 +typedef enum
3076 +{
3077 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
3078 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
3079 + GPIO_input_v = 0, // gpiocfg use pin as input.
3080 + GPIO_output_v = 1, // gpiocfg use pin as output.
3081 + GPIO_pin0_b = 0,
3082 + GPIO_pin0_m = 0x00000001,
3083 + GPIO_pin1_b = 1,
3084 + GPIO_pin1_m = 0x00000002,
3085 + GPIO_pin2_b = 2,
3086 + GPIO_pin2_m = 0x00000004,
3087 + GPIO_pin3_b = 3,
3088 + GPIO_pin3_m = 0x00000008,
3089 + GPIO_pin4_b = 4,
3090 + GPIO_pin4_m = 0x00000010,
3091 + GPIO_pin5_b = 5,
3092 + GPIO_pin5_m = 0x00000020,
3093 + GPIO_pin6_b = 6,
3094 + GPIO_pin6_m = 0x00000040,
3095 + GPIO_pin7_b = 7,
3096 + GPIO_pin7_m = 0x00000080,
3097 + GPIO_pin8_b = 8,
3098 + GPIO_pin8_m = 0x00000100,
3099 + GPIO_pin9_b = 9,
3100 + GPIO_pin9_m = 0x00000200,
3101 + GPIO_pin10_b = 10,
3102 + GPIO_pin10_m = 0x00000400,
3103 + GPIO_pin11_b = 11,
3104 + GPIO_pin11_m = 0x00000800,
3105 + GPIO_pin12_b = 12,
3106 + GPIO_pin12_m = 0x00001000,
3107 + GPIO_pin13_b = 13,
3108 + GPIO_pin13_m = 0x00002000,
3109 + GPIO_pin14_b = 14,
3110 + GPIO_pin14_m = 0x00004000,
3111 + GPIO_pin15_b = 15,
3112 + GPIO_pin15_m = 0x00008000,
3113 + GPIO_pin16_b = 16,
3114 + GPIO_pin16_m = 0x00010000,
3115 + GPIO_pin17_b = 17,
3116 + GPIO_pin17_m = 0x00020000,
3117 + GPIO_pin18_b = 18,
3118 + GPIO_pin18_m = 0x00040000,
3119 + GPIO_pin19_b = 19,
3120 + GPIO_pin19_m = 0x00080000,
3121 + GPIO_pin20_b = 20,
3122 + GPIO_pin20_m = 0x00100000,
3123 + GPIO_pin21_b = 21,
3124 + GPIO_pin21_m = 0x00200000,
3125 + GPIO_pin22_b = 22,
3126 + GPIO_pin22_m = 0x00400000,
3127 + GPIO_pin23_b = 23,
3128 + GPIO_pin23_m = 0x00800000,
3129 + GPIO_pin24_b = 24,
3130 + GPIO_pin24_m = 0x01000000,
3131 + GPIO_pin25_b = 25,
3132 + GPIO_pin25_m = 0x02000000,
3133 + GPIO_pin26_b = 26,
3134 + GPIO_pin26_m = 0x04000000,
3135 + GPIO_pin27_b = 27,
3136 + GPIO_pin27_m = 0x08000000,
3137 + GPIO_pin28_b = 28,
3138 + GPIO_pin28_m = 0x10000000,
3139 + GPIO_pin29_b = 29,
3140 + GPIO_pin29_m = 0x20000000,
3141 + GPIO_pin30_b = 30,
3142 + GPIO_pin30_m = 0x40000000,
3143 + GPIO_pin31_b = 31,
3144 + GPIO_pin31_m = 0x80000000,
3145 +
3146 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
3147 +
3148 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
3149 + GPIO_u0sout_m = GPIO_pin0_m,
3150 + GPIO_u0sout_cfg_v = GPIO_output_v,
3151 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
3152 + GPIO_u0sinp_m = GPIO_pin1_m,
3153 + GPIO_u0sinp_cfg_v = GPIO_input_v,
3154 + GPIO_u0rtsn_b = GPIO_pin2_b, // UART 0 req. to send.
3155 + GPIO_u0rtsn_m = GPIO_pin2_m,
3156 + GPIO_u0rtsn_cfg_v = GPIO_output_v,
3157 + GPIO_u0ctsn_b = GPIO_pin3_b, // UART 0 clear to send.
3158 + GPIO_u0ctsn_m = GPIO_pin3_m,
3159 + GPIO_u0ctsn_cfg_v = GPIO_input_v,
3160 + GPIO_maddr22_b = GPIO_pin4_b, // M&P bus bit 22.
3161 + GPIO_maddr22_m = GPIO_pin4_m,
3162 + GPIO_maddr22_cfg_v = GPIO_output_v,
3163 +
3164 + GPIO_maddr23_b = GPIO_pin5_b, // M&P bus bit 23.
3165 + GPIO_maddr23_m = GPIO_pin5_m,
3166 + GPIO_maddr23_cfg_v = GPIO_output_v,
3167 +
3168 + GPIO_maddr24_b = GPIO_pin6_b, // M&P bus bit 24.
3169 + GPIO_maddr24_m = GPIO_pin6_m,
3170 + GPIO_maddr24_cfg_v = GPIO_output_v,
3171 +
3172 + GPIO_maddr25_b = GPIO_pin7_b, // M&P bus bit 25.
3173 + GPIO_maddr25_m = GPIO_pin7_m,
3174 + GPIO_maddr25_cfg_v = GPIO_output_v,
3175 +
3176 + GPIO_cpu_b = GPIO_pin8_b, // M&P bus bit 25.
3177 + GPIO_cpu_m = GPIO_pin8_m,
3178 + GPIO_cpu_cfg_v = GPIO_output_v,
3179 + GPIO_afspare6_b = GPIO_pin9_b, // reserved.
3180 + GPIO_afspare6_m = GPIO_pin9_m,
3181 + GPIO_afspare6_cfg_v = GPIO_input_v,
3182 + GPIO_afspare4_b = GPIO_pin10_b, // reserved.
3183 + GPIO_afspare4_m = GPIO_pin10_m,
3184 + GPIO_afspare4_cfg_v = GPIO_input_v,
3185 + GPIO_afspare3_b = GPIO_pin11_b, // reserved.
3186 + GPIO_afspare3_m = GPIO_pin11_m,
3187 + GPIO_afspare3_cfg_v = GPIO_input_v,
3188 + GPIO_afspare2_b = GPIO_pin12_b, // reserved.
3189 + GPIO_afspare2_m = GPIO_pin12_m,
3190 + GPIO_afspare2_cfg_v = GPIO_input_v,
3191 + GPIO_pcimuintn_b = GPIO_pin13_b, // PCI messaging int.
3192 + GPIO_pcimuintn_m = GPIO_pin13_m,
3193 + GPIO_pcimuintn_cfg_v = GPIO_output_v,
3194 +
3195 +} GPIO_DEFS_t;
3196 +
3197 +#endif // __IDT_GPIO_H__
3198 +
3199 diff -urN linux.old/include/asm-mips/rc32434/i2c.h linux.dev/include/asm-mips/rc32434/i2c.h
3200 --- linux.old/include/asm-mips/rc32434/i2c.h 1970-01-01 01:00:00.000000000 +0100
3201 +++ linux.dev/include/asm-mips/rc32434/i2c.h 2006-07-29 19:31:51.000000000 +0200
3202 @@ -0,0 +1,147 @@
3203 +#ifndef __IDT_I2C_H__
3204 +#define __IDT_I2C_H__
3205 +
3206 +/*******************************************************************************
3207 + *
3208 + * Copyright 2002 Integrated Device Technology, Inc.
3209 + * All rights reserved.
3210 + *
3211 + * I2C register definitions.
3212 + *
3213 + * File : $Id: i2c.h,v 1.2 2002/06/06 18:34:04 astichte Exp $
3214 + *
3215 + * Author : Allen.Stichter@idt.com
3216 + * Date : 20020120
3217 + * Update :
3218 + * $Log: i2c.h,v $
3219 + * Revision 1.2 2002/06/06 18:34:04 astichte
3220 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
3221 + *
3222 + * Revision 1.1 2002/05/29 17:33:22 sysarch
3223 + * jba File moved from vcode/include/idt/acacia
3224 + *
3225 + *
3226 + ******************************************************************************/
3227 +
3228 +#include <asm/rc32434/types.h>
3229 +
3230 +enum
3231 +{
3232 + I2C0_PhysicalAddress = 0x18068000,
3233 + I2C_PhysicalAddress = I2C0_PhysicalAddress,
3234 +
3235 + I2C0_VirtualAddress = 0xb8068000,
3236 + I2C_VirtualAddress = I2C0_VirtualAddress,
3237 +} ;
3238 +
3239 +typedef struct
3240 +{
3241 + U32 i2cc ;
3242 + U32 i2cdi ;
3243 + U32 i2cdo ;
3244 + U32 i2ccp ; // I2C clk = ICLK / div / 8
3245 + U32 i2cmcmd ;
3246 + U32 i2cms ;
3247 + U32 i2cmsm ;
3248 + U32 i2css ;
3249 + U32 i2cssm ;
3250 + U32 i2csaddr ;
3251 + U32 i2csack ;
3252 +} volatile * I2C_t ;
3253 +enum
3254 +{
3255 + I2CC_men_b = 0, // In I2C-> i2cc
3256 + I2CC_men_m = 0x00000001,
3257 + I2CC_sen_b = 1, // In I2C-> i2cc
3258 + I2CC_sen_m = 0x00000002,
3259 + I2CC_iom_b = 2, // In I2C-> i2cc
3260 + I2CC_iom_m = 0x00000004,
3261 +
3262 + I2CDI_data_b = 0, // In I2C-> i2cdi
3263 + I2CDI_data_m = 0x000000ff,
3264 +
3265 + I2CDO_data_b = 0, // In I2C-> i2cdo
3266 + I2CDO_data_m = 0x000000ff,
3267 +
3268 + I2CCP_div_b = 0, // In I2C-> i2ccp
3269 + I2CCP_div_m = 0x0000ffff,
3270 +
3271 + I2CMCMD_cmd_b = 0, // In I2C-> i2cmcmd
3272 + I2CMCMD_cmd_m = 0x0000000f,
3273 + I2CMCMD_cmd_nop_v = 0,
3274 + I2CMCMD_cmd_start_v = 1,
3275 + I2CMCMD_cmd_stop_v = 2,
3276 + I2CMCMD_cmd_res3_v = 3,
3277 + I2CMCMD_cmd_rd_v = 4,
3278 + I2CMCMD_cmd_rdack_v = 5,
3279 + I2CMCMD_cmd_wd_v = 6,
3280 + I2CMCMD_cmd_wdack_v = 7,
3281 + I2CMCMD_cmd_res8_v = 8,
3282 + I2CMCMD_cmd_res9_v = 9,
3283 + I2CMCMD_cmd_res10_v = 10,
3284 + I2CMCMD_cmd_res11_v = 11,
3285 + I2CMCMD_cmd_res12_v = 12,
3286 + I2CMCMD_cmd_res13_v = 13,
3287 + I2CMCMD_cmd_res14_v = 14,
3288 + I2CMCMD_cmd_res15_v = 15,
3289 +
3290 + I2CMS_d_b = 0, // In I2C-> i2cms
3291 + I2CMS_d_m = 0x00000001,
3292 + I2CMS_na_b = 1, // In I2C-> i2cms
3293 + I2CMS_na_m = 0x00000002,
3294 + I2CMS_la_b = 2, // In I2C-> i2cms
3295 + I2CMS_la_m = 0x00000004,
3296 + I2CMS_err_b = 3, // In I2C-> i2cms
3297 + I2CMS_err_m = 0x00000008,
3298 +
3299 + I2CMSM_d_b = 0, // In I2C-> i2cmsm
3300 + I2CMSM_d_m = 0x00000001,
3301 + I2CMSM_na_b = 1, // In I2C-> i2cmsm
3302 + I2CMSM_na_m = 0x00000002,
3303 + I2CMSM_la_b = 2, // In I2C-> i2cmsm
3304 + I2CMSM_la_m = 0x00000004,
3305 + I2CMSM_err_b = 3, // In I2C-> i2cmsm
3306 + I2CMSM_err_m = 0x00000008,
3307 +
3308 + I2CSS_rr_b = 0, // In I2C-> i2css
3309 + I2CSS_rr_m = 0x00000001,
3310 + I2CSS_wr_b = 1, // In I2C-> i2css
3311 + I2CSS_wr_m = 0x00000002,
3312 + I2CSS_sa_b = 2, // In I2C-> i2css
3313 + I2CSS_sa_m = 0x00000004,
3314 + I2CSS_tf_b = 3, // In I2C-> i2css
3315 + I2CSS_tf_m = 0x00000008,
3316 + I2CSS_gc_b = 4, // In I2C-> i2css
3317 + I2CSS_gc_m = 0x00000010,
3318 + I2CSS_na_b = 5, // In I2C-> i2css
3319 + I2CSS_na_m = 0x00000020,
3320 + I2CSS_err_b = 6, // In I2C-> i2css
3321 + I2CSS_err_m = 0x00000040,
3322 +
3323 + I2CSSM_rr_b = 0, // In I2C-> i2cssm
3324 + I2CSSM_rr_m = 0x00000001,
3325 + I2CSSM_wr_b = 1, // In I2C-> i2cssm
3326 + I2CSSM_wr_m = 0x00000002,
3327 + I2CSSM_sa_b = 2, // In I2C-> i2cssm
3328 + I2CSSM_sa_m = 0x00000004,
3329 + I2CSSM_tf_b = 3, // In I2C-> i2cssm
3330 + I2CSSM_tf_m = 0x00000008,
3331 + I2CSSM_gc_b = 4, // In I2C-> i2cssm
3332 + I2CSSM_gc_m = 0x00000010,
3333 + I2CSSM_na_b = 5, // In I2C-> i2cssm
3334 + I2CSSM_na_m = 0x00000020,
3335 + I2CSSM_err_b = 6, // In I2C-> i2cssm
3336 + I2CSSM_err_m = 0x00000040,
3337 +
3338 + I2CSADDR_addr_b = 0, // In I2C-> i2csaddr
3339 + I2CSADDR_addr_m = 0x000003ff,
3340 + I2CSADDR_a_gc_b = 10, // In I2C-> i2csaddr
3341 + I2CSADDR_a_gc_m = 0x00000400,
3342 + I2CSADDR_a10_b = 11, // In I2C-> i2csaddr
3343 + I2CSADDR_a10_m = 0x00000800,
3344 +
3345 + I2CSACK_ack_b = 0, // In I2C-> i2csack
3346 + I2CSACK_ack_m = 0x00000001,
3347 +
3348 +} ;
3349 +#endif // __IDT_I2C_H__
3350 diff -urN linux.old/include/asm-mips/rc32434/integ.h linux.dev/include/asm-mips/rc32434/integ.h
3351 --- linux.old/include/asm-mips/rc32434/integ.h 1970-01-01 01:00:00.000000000 +0100
3352 +++ linux.dev/include/asm-mips/rc32434/integ.h 2006-07-29 19:31:51.000000000 +0200
3353 @@ -0,0 +1,78 @@
3354 +#ifndef __IDT_INTEG_H__
3355 +#define __IDT_INTEG_H__
3356 +
3357 +/*******************************************************************************
3358 + *
3359 + * Copyright 2002 Integrated Device Technology, Inc.
3360 + * All rights reserved.
3361 + *
3362 + * System Integrity register definition.
3363 + *
3364 + * File : $Id: integ.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
3365 + *
3366 + * Author : ryan.holmQVist@idt.com
3367 + * Date : 20011005
3368 + * Update :
3369 + * $Log: integ.h,v $
3370 + * Revision 1.3 2002/06/06 18:34:04 astichte
3371 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
3372 + *
3373 + * Revision 1.2 2002/06/05 18:32:33 astichte
3374 + * Removed IDTField
3375 + *
3376 + * Revision 1.1 2002/05/29 17:33:22 sysarch
3377 + * jba File moved from vcode/include/idt/acacia
3378 + *
3379 + ******************************************************************************/
3380 +
3381 +#include <asm/rc32434/types.h>
3382 +
3383 +enum
3384 +{
3385 + INTEG0_PhysicalAddress = 0x18030000,
3386 + INTEG_PhysicalAddress = INTEG0_PhysicalAddress, // Default
3387 +
3388 + INTEG0_VirtualAddress = 0xb8030000,
3389 + INTEG_VirtualAddress = INTEG0_VirtualAddress, // Default
3390 +} ;
3391 +
3392 +// if you are looing for CEA, try rst.h
3393 +typedef struct
3394 +{
3395 + U32 filler [0xc] ; // 0x30 bytes unused.
3396 + U32 errcs ; // sticky use ERRCS_
3397 + U32 wtcount ; // Watchdog timer count reg.
3398 + U32 wtcompare ; // Watchdog timer timeout value.
3399 + U32 wtc ; // Watchdog timer control. use WTC_
3400 +} volatile *INTEG_t ;
3401 +
3402 +enum
3403 +{
3404 + ERRCS_wto_b = 0, // In INTEG_t -> errcs
3405 + ERRCS_wto_m = 0x00000001,
3406 + ERRCS_wne_b = 1, // In INTEG_t -> errcs
3407 + ERRCS_wne_m = 0x00000002,
3408 + ERRCS_ucw_b = 2, // In INTEG_t -> errcs
3409 + ERRCS_ucw_m = 0x00000004,
3410 + ERRCS_ucr_b = 3, // In INTEG_t -> errcs
3411 + ERRCS_ucr_m = 0x00000008,
3412 + ERRCS_upw_b = 4, // In INTEG_t -> errcs
3413 + ERRCS_upw_m = 0x00000010,
3414 + ERRCS_upr_b = 5, // In INTEG_t -> errcs
3415 + ERRCS_upr_m = 0x00000020,
3416 + ERRCS_udw_b = 6, // In INTEG_t -> errcs
3417 + ERRCS_udw_m = 0x00000040,
3418 + ERRCS_udr_b = 7, // In INTEG_t -> errcs
3419 + ERRCS_udr_m = 0x00000080,
3420 + ERRCS_sae_b = 8, // In INTEG_t -> errcs
3421 + ERRCS_sae_m = 0x00000100,
3422 + ERRCS_wre_b = 9, // In INTEG_t -> errcs
3423 + ERRCS_wre_m = 0x00000200,
3424 +
3425 + WTC_en_b = 0, // In INTEG_t -> wtc
3426 + WTC_en_m = 0x00000001,
3427 + WTC_to_b = 1, // In INTEG_t -> wtc
3428 + WTC_to_m = 0x00000002,
3429 +} ;
3430 +
3431 +#endif // __IDT_INTEG_H__
3432 diff -urN linux.old/include/asm-mips/rc32434/int.h linux.dev/include/asm-mips/rc32434/int.h
3433 --- linux.old/include/asm-mips/rc32434/int.h 1970-01-01 01:00:00.000000000 +0100
3434 +++ linux.dev/include/asm-mips/rc32434/int.h 2006-07-29 19:31:51.000000000 +0200
3435 @@ -0,0 +1,167 @@
3436 +#ifndef __IDT_INT_H__
3437 +#define __IDT_INT_H__
3438 +
3439 +/*******************************************************************************
3440 + *
3441 + * Copyright 2002 Integrated Device Technology, Inc.
3442 + * All rights reserved.
3443 + *
3444 + * Interrupt Controller register definition.
3445 + *
3446 + * File : $Id: int.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
3447 + *
3448 + * Author : ryan.holmqvist@idt.com
3449 + * Date : 20011005
3450 + * Update :
3451 + * $Log: int.h,v $
3452 + * Revision 1.3 2002/06/06 18:34:04 astichte
3453 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
3454 + *
3455 + * Revision 1.2 2002/06/05 18:47:33 astichte
3456 + * Removed IDTField
3457 + *
3458 + * Revision 1.1 2002/05/29 17:33:22 sysarch
3459 + * jba File moved from vcode/include/idt/acacia
3460 + *
3461 + *
3462 + ******************************************************************************/
3463 +
3464 +#include <asm/rc32434/types.h>
3465 +
3466 +enum
3467 +{
3468 + INT0_PhysicalAddress = 0x18038000,
3469 + INT_PhysicalAddress = INT0_PhysicalAddress, // Default
3470 +
3471 + INT0_VirtualAddress = 0xb8038000,
3472 + INT_VirtualAddress = INT0_VirtualAddress, // Default
3473 +} ;
3474 +
3475 +struct INT_s
3476 +{
3477 + U32 ipend ; //Pending interrupts. use INT?_
3478 + U32 itest ; //Test bits. use INT?_
3479 + U32 imask ; //Interrupt disabled when set. use INT?_
3480 +} ;
3481 +
3482 +enum
3483 +{
3484 + IPEND2 = 0, // HW 2 interrupt to core. use INT2_
3485 + IPEND3 = 1, // HW 3 interrupt to core. use INT3_
3486 + IPEND4 = 2, // HW 4 interrupt to core. use INT4_
3487 + IPEND5 = 3, // HW 5 interrupt to core. use INT5_
3488 + IPEND6 = 4, // HW 6 interrupt to core. use INT6_
3489 +
3490 + IPEND_count, // must be last (used in loops)
3491 + IPEND_min = IPEND2 // min IPEND (used in loops)
3492 +};
3493 +
3494 +typedef struct INTC_s
3495 +{
3496 + struct INT_s i [IPEND_count] ;// use i[IPEND?] = INT?_
3497 + U32 nmips ; // use NMIPS_
3498 +} volatile *INT_t ;
3499 +
3500 +enum
3501 +{
3502 + INT2_timer0_b = 0,
3503 + INT2_timer0_m = 0x00000001,
3504 + INT2_timer1_b = 1,
3505 + INT2_timer1_m = 0x00000002,
3506 + INT2_timer2_b = 2,
3507 + INT2_timer2_m = 0x00000004,
3508 + INT2_refresh_b = 3,
3509 + INT2_refresh_m = 0x00000008,
3510 + INT2_watchdogTimeout_b = 4,
3511 + INT2_watchdogTimeout_m = 0x00000010,
3512 + INT2_undecodedCpuWrite_b = 5,
3513 + INT2_undecodedCpuWrite_m = 0x00000020,
3514 + INT2_undecodedCpuRead_b = 6,
3515 + INT2_undecodedCpuRead_m = 0x00000040,
3516 + INT2_undecodedPciWrite_b = 7,
3517 + INT2_undecodedPciWrite_m = 0x00000080,
3518 + INT2_undecodedPciRead_b = 8,
3519 + INT2_undecodedPciRead_m = 0x00000100,
3520 + INT2_undecodedDmaWrite_b = 9,
3521 + INT2_undecodedDmaWrite_m = 0x00000200,
3522 + INT2_undecodedDmaRead_b = 10,
3523 + INT2_undecodedDmaRead_m = 0x00000400,
3524 + INT2_ipBusSlaveAckError_b = 11,
3525 + INT2_ipBusSlaveAckError_m = 0x00000800,
3526 +
3527 + INT3_dmaChannel0_b = 0,
3528 + INT3_dmaChannel0_m = 0x00000001,
3529 + INT3_dmaChannel1_b = 1,
3530 + INT3_dmaChannel1_m = 0x00000002,
3531 + INT3_dmaChannel2_b = 2,
3532 + INT3_dmaChannel2_m = 0x00000004,
3533 + INT3_dmaChannel3_b = 3,
3534 + INT3_dmaChannel3_m = 0x00000008,
3535 + INT3_dmaChannel4_b = 4,
3536 + INT3_dmaChannel4_m = 0x00000010,
3537 + INT3_dmaChannel5_b = 5,
3538 + INT3_dmaChannel5_m = 0x00000020,
3539 +
3540 + INT5_uartGeneral0_b = 0,
3541 + INT5_uartGeneral0_m = 0x00000001,
3542 + INT5_uartTxrdy0_b = 1,
3543 + INT5_uartTxrdy0_m = 0x00000002,
3544 + INT5_uartRxrdy0_b = 2,
3545 + INT5_uartRxrdy0_m = 0x00000004,
3546 + INT5_pci_b = 3,
3547 + INT5_pci_m = 0x00000008,
3548 + INT5_pciDecoupled_b = 4,
3549 + INT5_pciDecoupled_m = 0x00000010,
3550 + INT5_spi_b = 5,
3551 + INT5_spi_m = 0x00000020,
3552 + INT5_deviceDecoupled_b = 6,
3553 + INT5_deviceDecoupled_m = 0x00000040,
3554 + INT5_i2cMaster_b = 7,
3555 + INT5_i2cMaster_m = 0x00000080,
3556 + INT5_i2cSlave_b = 8,
3557 + INT5_i2cSlave_m = 0x00000100,
3558 + INT5_ethOvr_b = 9,
3559 + INT5_ethOvr_m = 0x00000200,
3560 + INT5_ethUnd_b = 10,
3561 + INT5_ethUnd_m = 0x00000400,
3562 + INT5_ethPfd_b = 11,
3563 + INT5_ethPfd_m = 0x00000800,
3564 + INT5_nvram_b = 12,
3565 + INT5_nvram_m = 0x00001000,
3566 +
3567 + INT6_gpio0_b = 0,
3568 + INT6_gpio0_m = 0x00000001,
3569 + INT6_gpio1_b = 1,
3570 + INT6_gpio1_m = 0x00000002,
3571 + INT6_gpio2_b = 2,
3572 + INT6_gpio2_m = 0x00000004,
3573 + INT6_gpio3_b = 3,
3574 + INT6_gpio3_m = 0x00000008,
3575 + INT6_gpio4_b = 4,
3576 + INT6_gpio4_m = 0x00000010,
3577 + INT6_gpio5_b = 5,
3578 + INT6_gpio5_m = 0x00000020,
3579 + INT6_gpio6_b = 6,
3580 + INT6_gpio6_m = 0x00000040,
3581 + INT6_gpio7_b = 7,
3582 + INT6_gpio7_m = 0x00000080,
3583 + INT6_gpio8_b = 8,
3584 + INT6_gpio8_m = 0x00000100,
3585 + INT6_gpio9_b = 9,
3586 + INT6_gpio9_m = 0x00000200,
3587 + INT6_gpio10_b = 10,
3588 + INT6_gpio10_m = 0x00000400,
3589 + INT6_gpio11_b = 11,
3590 + INT6_gpio11_m = 0x00000800,
3591 + INT6_gpio12_b = 12,
3592 + INT6_gpio12_m = 0x00001000,
3593 + INT6_gpio13_b = 13,
3594 + INT6_gpio13_m = 0x00002000,
3595 +
3596 + NMIPS_gpio_b = 0,
3597 + NMIPS_gpio_m = 0x00000001,
3598 +} ;
3599 +
3600 +#endif // __IDT_INT_H__
3601 +
3602 +
3603 diff -urN linux.old/include/asm-mips/rc32434/iparb.h linux.dev/include/asm-mips/rc32434/iparb.h
3604 --- linux.old/include/asm-mips/rc32434/iparb.h 1970-01-01 01:00:00.000000000 +0100
3605 +++ linux.dev/include/asm-mips/rc32434/iparb.h 2006-07-29 19:31:51.000000000 +0200
3606 @@ -0,0 +1,95 @@
3607 +#ifndef __IDT_IPARB_H__
3608 +#define __IDT_IPARB_H__
3609 +
3610 +/*******************************************************************************
3611 + *
3612 + * Copyright 2002 Integrated Device Technology, Inc.
3613 + * All rights reserved.
3614 + *
3615 + * IP Arbiter register definitions.
3616 + *
3617 + * File : $Id: iparb.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
3618 + *
3619 + * Author : Allen.Stichter@idt.com
3620 + * Date : 20020120
3621 + * Update :
3622 + * $Log: iparb.h,v $
3623 + * Revision 1.3 2002/06/06 18:34:04 astichte
3624 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
3625 + *
3626 + * Revision 1.2 2002/06/05 19:01:42 astichte
3627 + * Removed IDTField
3628 + *
3629 + * Revision 1.1 2002/05/29 17:33:23 sysarch
3630 + * jba File moved from vcode/include/idt/acacia
3631 + *
3632 + ******************************************************************************/
3633 +
3634 +#include <asm/rc32434/types.h>
3635 +
3636 +enum
3637 +{
3638 + IPARB0_PhysicalAddress = 0x18048000,
3639 + IPARB_PhysicalAddress = IPARB0_PhysicalAddress, // Default
3640 +
3641 + IPARB0_VirtualAddress = 0xb8048000,
3642 + IPARB_VirtualAddress = IPARB0_VirtualAddress, // Default
3643 +} ;
3644 +
3645 +enum
3646 +{
3647 + IPABMXC_ethernetReceive = 0,
3648 + IPABMXC_ethernetTransmit = 1,
3649 + IPABMXC_memoryToHoldFifo = 2,
3650 + IPABMXC_holdFifoToMemory = 3,
3651 + IPABMXC_pciToMemory = 4,
3652 + IPABMXC_memoryToPci = 5,
3653 + IPABMXC_pciTarget = 6,
3654 + IPABMXC_pciTargetStart = 7,
3655 + IPABMXC_cpuToIpBus = 8,
3656 +
3657 + IPABMXC_Count, // Must be last in list !
3658 + IPABMXC_Min = IPABMXC_ethernetReceive,
3659 +
3660 + IPAPXC_PriorityCount = 4, // 3-highest, 0-lowest.
3661 +} ;
3662 +
3663 +typedef struct
3664 +{
3665 + U32 ipapc [IPAPXC_PriorityCount] ; // ipapc[IPAPXC_] = IPAPC_
3666 + U32 ipabmc [IPABMXC_Count] ; // ipabmc[IPABMXC_] = IPABMC_
3667 + U32 ipac ; // use IPAC_
3668 + U32 ipaitcc; // use IPAITCC_
3669 + U32 ipaspare ;
3670 +} volatile * IPARB_t ;
3671 +
3672 +enum
3673 +{
3674 + IPAC_dwm_b = 2,
3675 + IPAC_dwm_m = 0x00000004,
3676 + IPAC_drm_b = 3,
3677 + IPAC_drm_m = 0x00000008,
3678 + IPAC_msk_b = 4,
3679 + IPAC_msk_m = 0x00000010,
3680 +
3681 + IPAPC_ptc_b = 0,
3682 + IPAPC_ptc_m = 0x00003fff,
3683 + IPAPC_mf_b = 14,
3684 + IPAPC_mf_m = 0x00004000,
3685 + IPAPC_cptc_b = 16,
3686 + IPAPC_cptc_m = 0x3fff0000,
3687 +
3688 + IPAITCC_itcc = 0,
3689 + IPAITCC_itcc, = 0x000001ff,
3690 +
3691 + IPABMC_mtc_b = 0,
3692 + IPABMC_mtc_m = 0x00000fff,
3693 + IPABMC_p_b = 12,
3694 + IPABMC_p_m = 0x00003000,
3695 + IPABMC_msk_b = 14,
3696 + IPABMC_msk_m = 0x00004000,
3697 + IPABMC_cmtc_b = 16,
3698 + IPABMC_cmtc_m = 0x0fff0000,
3699 +};
3700 +
3701 +#endif // __IDT_IPARB_H__
3702 diff -urN linux.old/include/asm-mips/rc32434/irm.h linux.dev/include/asm-mips/rc32434/irm.h
3703 --- linux.old/include/asm-mips/rc32434/irm.h 1970-01-01 01:00:00.000000000 +0100
3704 +++ linux.dev/include/asm-mips/rc32434/irm.h 2006-07-29 19:31:51.000000000 +0200
3705 @@ -0,0 +1,55 @@
3706 +#ifndef __IDT_IRM_H__
3707 +#define __IDT_IRM_H__
3708 +
3709 +/*******************************************************************************
3710 + *
3711 + * Copyright 2002 Integrated Device Technology, Inc.
3712 + * All rights reserved.
3713 + *
3714 + * Internal Register Map
3715 + *
3716 + * File : $Id: irm.h,v 1.2 2002/06/05 14:51:06 astichte Exp $
3717 + *
3718 + * Author : Allen.Stichter@idt.com
3719 + * Date : 20020605
3720 + * Update :
3721 + * $Log: irm.h,v $
3722 + * Revision 1.2 2002/06/05 14:51:06 astichte
3723 + * *** empty log message ***
3724 + *
3725 + * Revision 1.1 2002/05/29 17:33:23 sysarch
3726 + * jba File moved from vcode/include/idt/acacia
3727 + *
3728 + ******************************************************************************/
3729 +
3730 +/*
3731 + * NOTE --
3732 + * This file is here for backwards compatibility.
3733 + * DO NOT USE !!!!
3734 + */
3735 +
3736 +typedef enum
3737 +{
3738 + IRM_Physical = 0x18000000, // Internal Reg. map physical.
3739 + RST_Offset = 0x00000000, // Includes sysid and RST.
3740 + DEV_Offset = 0x00010000, // Device Controller 0.
3741 + DDR_Offset = 0x00018000, // Double-Data-Rate mem. controller.
3742 + PMARB_Offset = 0x00020000, // PM bus arbiter.
3743 + TIM_Offset = 0x00028000, // Counter / timer.
3744 + INTEG_Offset = 0x00030000, // System Integrity.
3745 + INT_Offset = 0x00038000, // Interrupt controller.
3746 + DMA_Offset = 0x00040000, // DMA.
3747 + IPARB_Offset = 0x00044000, // IP bus arbiter.
3748 + GPIO_Offset = 0x00050000, // GPIO.
3749 + UART_Offset = 0x00058000, // UART
3750 + ETH_Offset = 0x00060000, // Ethernet 1.
3751 + I2C_Offset = 0x00068000, // I2C interface.
3752 + SPI_Offset = 0x00070000, // Serial Peripheral Interface.
3753 + NVRAM_Offset = 0x00078000, // NVRAM interface
3754 + AUTH_Offset = 0x0007c000, // Authorization unit
3755 + PCI_Offset = 0x00080000,
3756 + CROM_Offset = 0x000b8000, // Configuration ROM.
3757 + IRM_Size = 0x00200000, // Internal Reg. map size.
3758 +} IRM_Offset_t ;
3759 +
3760 +#endif // __IDT_IRM_H__
3761 diff -urN linux.old/include/asm-mips/rc32434/irq.h linux.dev/include/asm-mips/rc32434/irq.h
3762 --- linux.old/include/asm-mips/rc32434/irq.h 1970-01-01 01:00:00.000000000 +0100
3763 +++ linux.dev/include/asm-mips/rc32434/irq.h 2006-07-29 19:31:51.000000000 +0200
3764 @@ -0,0 +1,8 @@
3765 +#ifndef __ASM_MACH_MIPS_IRQ_H
3766 +#define __ASM_MACH_MIPS_IRQ_H
3767 +
3768 +#include <linux/config.h>
3769 +
3770 +#define NR_IRQS 256
3771 +
3772 +#endif /* __ASM_MACH_MIPS_IRQ_H */
3773 diff -urN linux.old/include/asm-mips/rc32434/nvram.h linux.dev/include/asm-mips/rc32434/nvram.h
3774 --- linux.old/include/asm-mips/rc32434/nvram.h 1970-01-01 01:00:00.000000000 +0100
3775 +++ linux.dev/include/asm-mips/rc32434/nvram.h 2006-07-29 19:31:51.000000000 +0200
3776 @@ -0,0 +1,97 @@
3777 +#ifndef __IDT_NVRAM_H
3778 +#define __IDT_NVRAM_H
3779 +
3780 +/*******************************************************************************
3781 + *
3782 + * Copyright 2002 Integrated Device Technology, Inc.
3783 + * All rights reserved.
3784 + *
3785 + * IP Arbiter register definitions.
3786 + *
3787 + * File : $Id: nvram.h,v 1.3 2003/07/24 18:34:04 astichte Exp $
3788 + *
3789 + * Author : kiran.rao@idt.com
3790 + * Date : 20030724
3791 + * Update :
3792 + * $Log: nvram.h,v $
3793 + *
3794 + *
3795 + ******************************************************************************/
3796 +#include <asm/rc32434/tpes.h>
3797 +
3798 +
3799 +enum
3800 +{
3801 + NVRAM0_PhysicalAddress = 0xba000000,
3802 + NVRAM_PhysicalAddress = NVRAM0_PhysicalAddress, // Default
3803 +
3804 + NVRAM0_VirtualAddress = 0xba000000,
3805 + NVRAM_VirtualAddress = NVRAM0_VirtualAddress, // Default
3806 +} ;
3807 +
3808 +enum
3809 +{
3810 + NVRCMD_cmd_b = 0,
3811 + NVRCMD_cmd_m = 0x0000007f,
3812 +
3813 + NVRS_r_b = 0,
3814 + NVRS_r_m = 0x00000001,
3815 + NVRS_e_b = 1,
3816 + NVRS_e_m = 0x00000002,
3817 + NVRS_k_b = 2,
3818 + NVRS_k_m = 0x00000004,
3819 +
3820 + NVRSM_r_b = 0,
3821 + NVRSM_r_m = 0x00000001,
3822 + NVRSM_e_b = 1,
3823 + NVRSM_e_m = 0x00000002,
3824 + NVRSM_k_b = 2,
3825 + NVRSM_k_m = 0x00000004,
3826 +
3827 + NVRCFG0_pwidth_b = 0,
3828 + NVRCFG0_pwidth_m = 0x00000003,
3829 + NVRCFG0_nmax_b = 2,
3830 + NVRCFG0_nmax_m = 0x0000000C,
3831 + NVRCFG0_vppl_b = 4,
3832 + NVRCFG0_vppl_m = 0x000000f0,
3833 + NVRCFG0_vppm_b = 8,
3834 + NVRCFG0_vppm_m = 0x00000300,
3835 + NVRCFG0_dvpp_b = 10,
3836 + NVRCFG0_dvpp_m = 0x00000c00,
3837 + NVRCFG0_x_b = 12,
3838 + NVRCFG0_x_m = 0x00007000,
3839 +
3840 + NVRCFG1_t1tecc_b = 0,
3841 + NVRCFG1_t1tecc_m = 0x00000003,
3842 + NVRCFG1_t1mrcl_b = 2,
3843 + NVRCFG1_t1mrcl_m = 0x0000000c,
3844 + NVRCFG1_t1bias_b = 4,
3845 + NVRCFG1_t1bias_m = 0x00000030,
3846 + NVRCFG1_t2tecc_b = 6,
3847 + NVRCFG1_t2tecc_m = 0x000000c0,
3848 + NVRCFG1_t2mrcl_b = 8,
3849 + NVRCFG1_t2mrcl_m = 0x00000300,
3850 + NVRCFG1_t2bias_b = 10,
3851 + NVRCFG1_t2bias_m = 0x00000c00,
3852 + NVRCFG1_t3tecc_b = 12,
3853 + NVRCFG1_t3tecc_m = 0x00003000,
3854 + NVRCFG1_t3mrcl_b = 14,
3855 + NVRCFG1_t3mrcl_m = 0x0000c000,
3856 + NVRCFG1_t3bias_b = 16,
3857 + NVRCFG1_t3bias_m = 0x00030000,
3858 + NVRCFG1_t4tecc_b = 18,
3859 + NVRCFG1_t4tecc_m = 0x000c0000,
3860 + NVRCFG1_t4mrcl_b = 20,
3861 + NVRCFG1_t4mrcl_m = 0x00300000,
3862 + NVRCFG1_t4bias_b = 22,
3863 + NVRCFG1_t4bias_m = 0x00c00000,
3864 + NVRCFG1_t5tecc_b = 24,
3865 + NVRCFG1_t5tecc_m = 0x03000000,
3866 + NVRCFG1_t5mrcl_b = 26,
3867 + NVRCFG1_t5mrcl_m = 0x0c000000,
3868 + NVRCFG1_t5bias_b = 28,
3869 + NVRCFG1_t5bias_m = 0x30000000,
3870 +}
3871 +
3872 +#endif // __IDT_NVRAM_H__
3873 +
3874 diff -urN linux.old/include/asm-mips/rc32434/pci.h linux.dev/include/asm-mips/rc32434/pci.h
3875 --- linux.old/include/asm-mips/rc32434/pci.h 1970-01-01 01:00:00.000000000 +0100
3876 +++ linux.dev/include/asm-mips/rc32434/pci.h 2006-07-29 19:31:51.000000000 +0200
3877 @@ -0,0 +1,695 @@
3878 +/**************************************************************************
3879 + *
3880 + * BRIEF MODULE DESCRIPTION
3881 + * PCI register definitio
3882 + *
3883 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
3884 + *
3885 + * This program is free software; you can redistribute it and/or modify it
3886 + * under the terms of the GNU General Public License as published by the
3887 + * Free Software Foundation; either version 2 of the License, or (at your
3888 + * option) any later version.
3889 + *
3890 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3891 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3892 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3893 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3894 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3895 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3896 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3897 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3898 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3899 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3900 + *
3901 + * You should have received a copy of the GNU General Public License along
3902 + * with this program; if not, write to the Free Software Foundation, Inc.,
3903 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3904 + *
3905 + *
3906 + **************************************************************************
3907 + * May 2004 rkt, neb.
3908 + *
3909 + * Initial Release
3910 + *
3911 + *
3912 + *
3913 + **************************************************************************
3914 + */
3915 +
3916 +#ifndef __IDT_PCI_H__
3917 +#define __IDT_PCI_H__
3918 +
3919 +enum
3920 +{
3921 + PCI0_PhysicalAddress = 0x18080000,
3922 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
3923 +
3924 + PCI0_VirtualAddress = 0xB8080000,
3925 + PCI_VirtualAddress = PCI0_VirtualAddress,
3926 +} ;
3927 +
3928 +enum
3929 +{
3930 + PCI_LbaCount = 4, // Local base addresses.
3931 +} ;
3932 +
3933 +typedef struct
3934 +{
3935 + u32 a ; // Address.
3936 + u32 c ; // Control.
3937 + u32 m ; // mapping.
3938 +} PCI_Map_s ;
3939 +
3940 +typedef struct
3941 +{
3942 + u32 pcic ;
3943 + u32 pcis ;
3944 + u32 pcism ;
3945 + u32 pcicfga ;
3946 + u32 pcicfgd ;
3947 + PCI_Map_s pcilba [PCI_LbaCount] ;
3948 + u32 pcidac ;
3949 + u32 pcidas ;
3950 + u32 pcidasm ;
3951 + u32 pcidad ;
3952 + u32 pcidma8c ;
3953 + u32 pcidma9c ;
3954 + u32 pcitc ;
3955 +} volatile *PCI_t ;
3956 +
3957 +// PCI messaging unit.
3958 +enum
3959 +{
3960 + PCIM_Count = 2,
3961 +} ;
3962 +typedef struct
3963 +{
3964 + u32 pciim [PCIM_Count] ;
3965 + u32 pciom [PCIM_Count] ;
3966 + u32 pciid ;
3967 + u32 pciiic ;
3968 + u32 pciiim ;
3969 + u32 pciiod ;
3970 + u32 pciioic ;
3971 + u32 pciioim ;
3972 +} volatile *PCIM_t ;
3973 +
3974 +/*******************************************************************************
3975 + *
3976 + * PCI Control Register
3977 + *
3978 + ******************************************************************************/
3979 +enum
3980 +{
3981 + PCIC_en_b = 0,
3982 + PCIC_en_m = 0x00000001,
3983 + PCIC_tnr_b = 1,
3984 + PCIC_tnr_m = 0x00000002,
3985 + PCIC_sce_b = 2,
3986 + PCIC_sce_m = 0x00000004,
3987 + PCIC_ien_b = 3,
3988 + PCIC_ien_m = 0x00000008,
3989 + PCIC_aaa_b = 4,
3990 + PCIC_aaa_m = 0x00000010,
3991 + PCIC_eap_b = 5,
3992 + PCIC_eap_m = 0x00000020,
3993 + PCIC_pcim_b = 6,
3994 + PCIC_pcim_m = 0x000001c0,
3995 + PCIC_pcim_disabled_v = 0,
3996 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
3997 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
3998 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
3999 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
4000 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
4001 + PCIC_pcim_reserved6_v = 6,
4002 + PCIC_pcim_reserved7_v = 7,
4003 + PCIC_igm_b = 9,
4004 + PCIC_igm_m = 0x00000200,
4005 +} ;
4006 +
4007 +/*******************************************************************************
4008 + *
4009 + * PCI Status Register
4010 + *
4011 + ******************************************************************************/
4012 +enum {
4013 + PCIS_eed_b = 0,
4014 + PCIS_eed_m = 0x00000001,
4015 + PCIS_wr_b = 1,
4016 + PCIS_wr_m = 0x00000002,
4017 + PCIS_nmi_b = 2,
4018 + PCIS_nmi_m = 0x00000004,
4019 + PCIS_ii_b = 3,
4020 + PCIS_ii_m = 0x00000008,
4021 + PCIS_cwe_b = 4,
4022 + PCIS_cwe_m = 0x00000010,
4023 + PCIS_cre_b = 5,
4024 + PCIS_cre_m = 0x00000020,
4025 + PCIS_mdpe_b = 6,
4026 + PCIS_mdpe_m = 0x00000040,
4027 + PCIS_sta_b = 7,
4028 + PCIS_sta_m = 0x00000080,
4029 + PCIS_rta_b = 8,
4030 + PCIS_rta_m = 0x00000100,
4031 + PCIS_rma_b = 9,
4032 + PCIS_rma_m = 0x00000200,
4033 + PCIS_sse_b = 10,
4034 + PCIS_sse_m = 0x00000400,
4035 + PCIS_ose_b = 11,
4036 + PCIS_ose_m = 0x00000800,
4037 + PCIS_pe_b = 12,
4038 + PCIS_pe_m = 0x00001000,
4039 + PCIS_tae_b = 13,
4040 + PCIS_tae_m = 0x00002000,
4041 + PCIS_rle_b = 14,
4042 + PCIS_rle_m = 0x00004000,
4043 + PCIS_bme_b = 15,
4044 + PCIS_bme_m = 0x00008000,
4045 + PCIS_prd_b = 16,
4046 + PCIS_prd_m = 0x00010000,
4047 + PCIS_rip_b = 17,
4048 + PCIS_rip_m = 0x00020000,
4049 +} ;
4050 +
4051 +/*******************************************************************************
4052 + *
4053 + * PCI Status Mask Register
4054 + *
4055 + ******************************************************************************/
4056 +enum {
4057 + PCISM_eed_b = 0,
4058 + PCISM_eed_m = 0x00000001,
4059 + PCISM_wr_b = 1,
4060 + PCISM_wr_m = 0x00000002,
4061 + PCISM_nmi_b = 2,
4062 + PCISM_nmi_m = 0x00000004,
4063 + PCISM_ii_b = 3,
4064 + PCISM_ii_m = 0x00000008,
4065 + PCISM_cwe_b = 4,
4066 + PCISM_cwe_m = 0x00000010,
4067 + PCISM_cre_b = 5,
4068 + PCISM_cre_m = 0x00000020,
4069 + PCISM_mdpe_b = 6,
4070 + PCISM_mdpe_m = 0x00000040,
4071 + PCISM_sta_b = 7,
4072 + PCISM_sta_m = 0x00000080,
4073 + PCISM_rta_b = 8,
4074 + PCISM_rta_m = 0x00000100,
4075 + PCISM_rma_b = 9,
4076 + PCISM_rma_m = 0x00000200,
4077 + PCISM_sse_b = 10,
4078 + PCISM_sse_m = 0x00000400,
4079 + PCISM_ose_b = 11,
4080 + PCISM_ose_m = 0x00000800,
4081 + PCISM_pe_b = 12,
4082 + PCISM_pe_m = 0x00001000,
4083 + PCISM_tae_b = 13,
4084 + PCISM_tae_m = 0x00002000,
4085 + PCISM_rle_b = 14,
4086 + PCISM_rle_m = 0x00004000,
4087 + PCISM_bme_b = 15,
4088 + PCISM_bme_m = 0x00008000,
4089 + PCISM_prd_b = 16,
4090 + PCISM_prd_m = 0x00010000,
4091 + PCISM_rip_b = 17,
4092 + PCISM_rip_m = 0x00020000,
4093 +} ;
4094 +
4095 +/*******************************************************************************
4096 + *
4097 + * PCI Configuration Address Register
4098 + *
4099 + ******************************************************************************/
4100 +enum {
4101 + PCICFGA_reg_b = 2,
4102 + PCICFGA_reg_m = 0x000000fc,
4103 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
4104 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
4105 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
4106 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
4107 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
4108 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
4109 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
4110 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
4111 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
4112 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
4113 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
4114 + PCICFGA_reg_pba0m_v = 0x48>>2,
4115 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
4116 + PCICFGA_reg_pba1m_v = 0x50>>2,
4117 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
4118 + PCICFGA_reg_pba2m_v = 0x58>>2,
4119 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
4120 + PCICFGA_reg_pba3m_v = 0x60>>2,
4121 + PCICFGA_reg_pmgt_v = 0x64>>2,
4122 + PCICFGA_func_b = 8,
4123 + PCICFGA_func_m = 0x00000700,
4124 + PCICFGA_dev_b = 11,
4125 + PCICFGA_dev_m = 0x0000f800,
4126 + PCICFGA_dev_internal_v = 0,
4127 + PCICFGA_bus_b = 16,
4128 + PCICFGA_bus_m = 0x00ff0000,
4129 + PCICFGA_bus_type0_v = 0, //local bus
4130 + PCICFGA_en_b = 31, // read only
4131 + PCICFGA_en_m = 0x80000000,
4132 +} ;
4133 +
4134 +enum {
4135 + PCFGID_vendor_b = 0,
4136 + PCFGID_vendor_m = 0x0000ffff,
4137 + PCFGID_vendor_IDT_v = 0x111d,
4138 + PCFGID_device_b = 16,
4139 + PCFGID_device_m = 0xffff0000,
4140 + PCFGID_device_Korinade_v = 0x0214,
4141 +
4142 + PCFG04_command_ioena_b = 1,
4143 + PCFG04_command_ioena_m = 0x00000001,
4144 + PCFG04_command_memena_b = 2,
4145 + PCFG04_command_memena_m = 0x00000002,
4146 + PCFG04_command_bmena_b = 3,
4147 + PCFG04_command_bmena_m = 0x00000004,
4148 + PCFG04_command_mwinv_b = 5,
4149 + PCFG04_command_mwinv_m = 0x00000010,
4150 + PCFG04_command_parena_b = 7,
4151 + PCFG04_command_parena_m = 0x00000040,
4152 + PCFG04_command_serrena_b = 9,
4153 + PCFG04_command_serrena_m = 0x00000100,
4154 + PCFG04_command_fastbbena_b = 10,
4155 + PCFG04_command_fastbbena_m = 0x00000200,
4156 + PCFG04_status_b = 16,
4157 + PCFG04_status_m = 0xffff0000,
4158 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
4159 + PCFG04_status_66MHz_m = 0x00200000,
4160 + PCFG04_status_fbb_b = 23,
4161 + PCFG04_status_fbb_m = 0x00800000,
4162 + PCFG04_status_mdpe_b = 24,
4163 + PCFG04_status_mdpe_m = 0x01000000,
4164 + PCFG04_status_dst_b = 25,
4165 + PCFG04_status_dst_m = 0x06000000,
4166 + PCFG04_status_sta_b = 27,
4167 + PCFG04_status_sta_m = 0x08000000,
4168 + PCFG04_status_rta_b = 28,
4169 + PCFG04_status_rta_m = 0x10000000,
4170 + PCFG04_status_rma_b = 29,
4171 + PCFG04_status_rma_m = 0x20000000,
4172 + PCFG04_status_sse_b = 30,
4173 + PCFG04_status_sse_m = 0x40000000,
4174 + PCFG04_status_pe_b = 31,
4175 + PCFG04_status_pe_m = 0x40000000,
4176 +
4177 + PCFG08_revId_b = 0,
4178 + PCFG08_revId_m = 0x000000ff,
4179 + PCFG08_classCode_b = 0,
4180 + PCFG08_classCode_m = 0xffffff00,
4181 + PCFG08_classCode_bridge_v = 06,
4182 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
4183 + PCFG0C_cacheline_b = 0,
4184 + PCFG0C_cacheline_m = 0x000000ff,
4185 + PCFG0C_masterLatency_b = 8,
4186 + PCFG0C_masterLatency_m = 0x0000ff00,
4187 + PCFG0C_headerType_b = 16,
4188 + PCFG0C_headerType_m = 0x00ff0000,
4189 + PCFG0C_bist_b = 24,
4190 + PCFG0C_bist_m = 0xff000000,
4191 +
4192 + PCIPBA_msi_b = 0,
4193 + PCIPBA_msi_m = 0x00000001,
4194 + PCIPBA_p_b = 3,
4195 + PCIPBA_p_m = 0x00000004,
4196 + PCIPBA_baddr_b = 8,
4197 + PCIPBA_baddr_m = 0xffffff00,
4198 +
4199 + PCFGSS_vendorId_b = 0,
4200 + PCFGSS_vendorId_m = 0x0000ffff,
4201 + PCFGSS_id_b = 16,
4202 + PCFGSS_id_m = 0xffff0000,
4203 +
4204 + PCFG3C_interruptLine_b = 0,
4205 + PCFG3C_interruptLine_m = 0x000000ff,
4206 + PCFG3C_interruptPin_b = 8,
4207 + PCFG3C_interruptPin_m = 0x0000ff00,
4208 + PCFG3C_minGrant_b = 16,
4209 + PCFG3C_minGrant_m = 0x00ff0000,
4210 + PCFG3C_maxLat_b = 24,
4211 + PCFG3C_maxLat_m = 0xff000000,
4212 +
4213 + PCIPBAC_msi_b = 0,
4214 + PCIPBAC_msi_m = 0x00000001,
4215 + PCIPBAC_p_b = 1,
4216 + PCIPBAC_p_m = 0x00000002,
4217 + PCIPBAC_size_b = 2,
4218 + PCIPBAC_size_m = 0x0000007c,
4219 + PCIPBAC_sb_b = 7,
4220 + PCIPBAC_sb_m = 0x00000080,
4221 + PCIPBAC_pp_b = 8,
4222 + PCIPBAC_pp_m = 0x00000100,
4223 + PCIPBAC_mr_b = 9,
4224 + PCIPBAC_mr_m = 0x00000600,
4225 + PCIPBAC_mr_read_v =0, //no prefetching
4226 + PCIPBAC_mr_readLine_v =1,
4227 + PCIPBAC_mr_readMult_v =2,
4228 + PCIPBAC_mrl_b = 11,
4229 + PCIPBAC_mrl_m = 0x00000800,
4230 + PCIPBAC_mrm_b = 12,
4231 + PCIPBAC_mrm_m = 0x00001000,
4232 + PCIPBAC_trp_b = 13,
4233 + PCIPBAC_trp_m = 0x00002000,
4234 +
4235 + PCFG40_trdyTimeout_b = 0,
4236 + PCFG40_trdyTimeout_m = 0x000000ff,
4237 + PCFG40_retryLim_b = 8,
4238 + PCFG40_retryLim_m = 0x0000ff00,
4239 +};
4240 +
4241 +/*******************************************************************************
4242 + *
4243 + * PCI Local Base Address [0|1|2|3] Register
4244 + *
4245 + ******************************************************************************/
4246 +enum {
4247 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
4248 + PCILBA_baddr_m = 0xffffff00,
4249 +} ;
4250 +/*******************************************************************************
4251 + *
4252 + * PCI Local Base Address Control Register
4253 + *
4254 + ******************************************************************************/
4255 +enum {
4256 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
4257 + PCILBAC_msi_m = 0x00000001,
4258 + PCILBAC_msi_mem_v = 0,
4259 + PCILBAC_msi_io_v = 1,
4260 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
4261 + PCILBAC_size_m = 0x0000007c,
4262 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
4263 + PCILBAC_sb_m = 0x00000080,
4264 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
4265 + PCILBAC_rt_m = 0x00000100,
4266 + PCILBAC_rt_noprefetch_v = 0, // mem read
4267 + PCILBAC_rt_prefetch_v = 1, // mem readline
4268 +} ;
4269 +
4270 +/*******************************************************************************
4271 + *
4272 + * PCI Local Base Address [0|1|2|3] Mapping Register
4273 + *
4274 + ******************************************************************************/
4275 +enum {
4276 + PCILBAM_maddr_b = 8,
4277 + PCILBAM_maddr_m = 0xffffff00,
4278 +} ;
4279 +
4280 +/*******************************************************************************
4281 + *
4282 + * PCI Decoupled Access Control Register
4283 + *
4284 + ******************************************************************************/
4285 +enum {
4286 + PCIDAC_den_b = 0,
4287 + PCIDAC_den_m = 0x00000001,
4288 +} ;
4289 +
4290 +/*******************************************************************************
4291 + *
4292 + * PCI Decoupled Access Status Register
4293 + *
4294 + ******************************************************************************/
4295 +enum {
4296 + PCIDAS_d_b = 0,
4297 + PCIDAS_d_m = 0x00000001,
4298 + PCIDAS_b_b = 1,
4299 + PCIDAS_b_m = 0x00000002,
4300 + PCIDAS_e_b = 2,
4301 + PCIDAS_e_m = 0x00000004,
4302 + PCIDAS_ofe_b = 3,
4303 + PCIDAS_ofe_m = 0x00000008,
4304 + PCIDAS_off_b = 4,
4305 + PCIDAS_off_m = 0x00000010,
4306 + PCIDAS_ife_b = 5,
4307 + PCIDAS_ife_m = 0x00000020,
4308 + PCIDAS_iff_b = 6,
4309 + PCIDAS_iff_m = 0x00000040,
4310 +} ;
4311 +
4312 +/*******************************************************************************
4313 + *
4314 + * PCI DMA Channel 8 Configuration Register
4315 + *
4316 + ******************************************************************************/
4317 +enum
4318 +{
4319 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
4320 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
4321 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
4322 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
4323 +} ;
4324 +
4325 +/*******************************************************************************
4326 + *
4327 + * PCI DMA Channel 9 Configuration Register
4328 + *
4329 + ******************************************************************************/
4330 +enum
4331 +{
4332 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
4333 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
4334 +} ;
4335 +
4336 +/*******************************************************************************
4337 + *
4338 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
4339 + *
4340 + ******************************************************************************/
4341 +enum {
4342 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
4343 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
4344 + // These are for reads (DMA channel 8)
4345 + PCIDMAD_devcmd_mr_v = 0, //memory read
4346 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
4347 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
4348 + PCIDMAD_devcmd_ior_v = 3, //I/O read
4349 + // These are for writes (DMA channel 9)
4350 + PCIDMAD_devcmd_mw_v = 0, //memory write
4351 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
4352 + PCIDMAD_devcmd_iow_v = 3, //I/O write
4353 +
4354 + // Swap byte field applies to both DMA channel 8 and 9
4355 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
4356 + PCIDMAD_sb_m = 0x01000000, // swap byte field
4357 +} ;
4358 +
4359 +
4360 +/*******************************************************************************
4361 + *
4362 + * PCI Target Control Register
4363 + *
4364 + ******************************************************************************/
4365 +enum
4366 +{
4367 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
4368 + PCITC_rtimer_m = 0x000000ff,
4369 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
4370 + PCITC_dtimer_m = 0x0000ff00,
4371 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
4372 + PCITC_rdr_m = 0x00040000,
4373 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
4374 + PCITC_ddt_m = 0x00080000,
4375 +} ;
4376 +/*******************************************************************************
4377 + *
4378 + * PCI messaging unit [applies to both inbound and outbound registers ]
4379 + *
4380 + ******************************************************************************/
4381 +enum
4382 +{
4383 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
4384 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
4385 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
4386 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
4387 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
4388 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
4389 +};
4390 +
4391 +
4392 +
4393 +
4394 +
4395 +
4396 +#define PCI_MSG_VirtualAddress 0xB8088010
4397 +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
4398 +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
4399 +
4400 +#define PCIM_SHFT 0x6
4401 +#define PCIM_BIT_LEN 0x7
4402 +#define PCIM_H_EA 0x3
4403 +#define PCIM_H_IA_FIX 0x4
4404 +#define PCIM_H_IA_RR 0x5
4405 +#if 0
4406 +#define PCI_ADDR_START 0x13000000
4407 +#endif
4408 +
4409 +#define PCI_ADDR_START 0x50000000
4410 +
4411 +#define CPUTOPCI_MEM_WIN 0x02000000
4412 +#define CPUTOPCI_IO_WIN 0x00100000
4413 +#define PCILBA_SIZE_SHFT 2
4414 +#define PCILBA_SIZE_MASK 0x1F
4415 +#define SIZE_256MB 0x1C
4416 +#define SIZE_128MB 0x1B
4417 +#define SIZE_64MB 0x1A
4418 +#define SIZE_32MB 0x19
4419 +#define SIZE_16MB 0x18
4420 +#define SIZE_4MB 0x16
4421 +#define SIZE_2MB 0x15
4422 +#define SIZE_1MB 0x14
4423 +#define KORINA_CONFIG0_ADDR 0x80000000
4424 +#define KORINA_CONFIG1_ADDR 0x80000004
4425 +#define KORINA_CONFIG2_ADDR 0x80000008
4426 +#define KORINA_CONFIG3_ADDR 0x8000000C
4427 +#define KORINA_CONFIG4_ADDR 0x80000010
4428 +#define KORINA_CONFIG5_ADDR 0x80000014
4429 +#define KORINA_CONFIG6_ADDR 0x80000018
4430 +#define KORINA_CONFIG7_ADDR 0x8000001C
4431 +#define KORINA_CONFIG8_ADDR 0x80000020
4432 +#define KORINA_CONFIG9_ADDR 0x80000024
4433 +#define KORINA_CONFIG10_ADDR 0x80000028
4434 +#define KORINA_CONFIG11_ADDR 0x8000002C
4435 +#define KORINA_CONFIG12_ADDR 0x80000030
4436 +#define KORINA_CONFIG13_ADDR 0x80000034
4437 +#define KORINA_CONFIG14_ADDR 0x80000038
4438 +#define KORINA_CONFIG15_ADDR 0x8000003C
4439 +#define KORINA_CONFIG16_ADDR 0x80000040
4440 +#define KORINA_CONFIG17_ADDR 0x80000044
4441 +#define KORINA_CONFIG18_ADDR 0x80000048
4442 +#define KORINA_CONFIG19_ADDR 0x8000004C
4443 +#define KORINA_CONFIG20_ADDR 0x80000050
4444 +#define KORINA_CONFIG21_ADDR 0x80000054
4445 +#define KORINA_CONFIG22_ADDR 0x80000058
4446 +#define KORINA_CONFIG23_ADDR 0x8000005C
4447 +#define KORINA_CONFIG24_ADDR 0x80000060
4448 +#define KORINA_CONFIG25_ADDR 0x80000064
4449 +#define KORINA_CMD (PCFG04_command_ioena_m | \
4450 + PCFG04_command_memena_m | \
4451 + PCFG04_command_bmena_m | \
4452 + PCFG04_command_mwinv_m | \
4453 + PCFG04_command_parena_m | \
4454 + PCFG04_command_serrena_m )
4455 +
4456 +#define KORINA_STAT (PCFG04_status_mdpe_m | \
4457 + PCFG04_status_sta_m | \
4458 + PCFG04_status_rta_m | \
4459 + PCFG04_status_rma_m | \
4460 + PCFG04_status_sse_m | \
4461 + PCFG04_status_pe_m)
4462 +
4463 +#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
4464 +
4465 +#define KORINA_REVID 0
4466 +#define KORINA_CLASS_CODE 0
4467 +#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
4468 + KORINA_REVID)
4469 +
4470 +#define KORINA_CACHE_LINE_SIZE 4
4471 +#define KORINA_MASTER_LAT 0x3c
4472 +#define KORINA_HEADER_TYPE 0
4473 +#define KORINA_BIST 0
4474 +
4475 +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
4476 + (KORINA_HEADER_TYPE<<16) | \
4477 + (KORINA_MASTER_LAT<<8) | \
4478 + KORINA_CACHE_LINE_SIZE )
4479 +
4480 +#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
4481 +#define KORINA_BAR1 0x18800001 /* 1 MB IO */
4482 +#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
4483 + internal Registers */
4484 +#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
4485 +
4486 +#define KORINA_CNFG4 KORINA_BAR0
4487 +#define KORINA_CNFG5 KORINA_BAR1
4488 +#define KORINA_CNFG6 KORINA_BAR2
4489 +#define KORINA_CNFG7 KORINA_BAR3
4490 +
4491 +#define KORINA_SUBSYS_VENDOR_ID 0x011d
4492 +#define KORINA_SUBSYSTEM_ID 0x0214
4493 +#define KORINA_CNFG8 0
4494 +#define KORINA_CNFG9 0
4495 +#define KORINA_CNFG10 0
4496 +#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
4497 + KORINA_SUBSYSTEM_ID)
4498 +#define KORINA_INT_LINE 1
4499 +#define KORINA_INT_PIN 1
4500 +#define KORINA_MIN_GNT 8
4501 +#define KORINA_MAX_LAT 0x38
4502 +#define KORINA_CNFG12 0
4503 +#define KORINA_CNFG13 0
4504 +#define KORINA_CNFG14 0
4505 +#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
4506 + (KORINA_MIN_GNT<<16) | \
4507 + (KORINA_INT_PIN<<8) | \
4508 + KORINA_INT_LINE)
4509 +#define KORINA_RETRY_LIMIT 0x80
4510 +#define KORINA_TRDY_LIMIT 0x80
4511 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
4512 + KORINA_TRDY_LIMIT)
4513 +#define PCI_PBAxC_R 0x0
4514 +#define PCI_PBAxC_RL 0x1
4515 +#define PCI_PBAxC_RM 0x2
4516 +#define SIZE_SHFT 2
4517 +
4518 +#if defined(__MIPSEB__)
4519 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
4520 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
4521 + PCIPBAC_pp_m | \
4522 + (SIZE_128MB<<SIZE_SHFT) | \
4523 + PCIPBAC_p_m)
4524 +#else
4525 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | \
4526 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
4527 + PCIPBAC_pp_m | \
4528 + (SIZE_128MB<<SIZE_SHFT) | \
4529 + PCIPBAC_p_m)
4530 +#endif
4531 +#define KORINA_CNFG17 KORINA_PBA0C
4532 +#define KORINA_PBA0M 0x0
4533 +#define KORINA_CNFG18 KORINA_PBA0M
4534 +
4535 +#if defined(__MIPSEB__)
4536 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
4537 + PCIPBAC_msi_m)
4538 +#else
4539 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
4540 + PCIPBAC_msi_m)
4541 +#endif
4542 +#define KORINA_CNFG19 KORINA_PBA1C
4543 +#define KORINA_PBA1M 0x0
4544 +#define KORINA_CNFG20 KORINA_PBA1M
4545 +
4546 +#if defined(__MIPSEB__)
4547 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
4548 + PCIPBAC_msi_m)
4549 +#else
4550 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
4551 + PCIPBAC_msi_m)
4552 +#endif
4553 +#define KORINA_CNFG21 KORINA_PBA2C
4554 +#define KORINA_PBA2M 0x18000000
4555 +#define KORINA_CNFG22 KORINA_PBA2M
4556 +#define KORINA_PBA3C 0
4557 +#define KORINA_CNFG23 KORINA_PBA3C
4558 +#define KORINA_PBA3M 0
4559 +#define KORINA_CNFG24 KORINA_PBA3M
4560 +
4561 +
4562 +
4563 +#define PCITC_DTIMER_VAL 8
4564 +#define PCITC_RTIMER_VAL 0x10
4565 +
4566 +
4567 +
4568 +
4569 +#endif // __IDT_PCI_H__
4570 +
4571 +
4572 +
4573 diff -urN linux.old/include/asm-mips/rc32434/pcikorina.h linux.dev/include/asm-mips/rc32434/pcikorina.h
4574 --- linux.old/include/asm-mips/rc32434/pcikorina.h 1970-01-01 01:00:00.000000000 +0100
4575 +++ linux.dev/include/asm-mips/rc32434/pcikorina.h 2006-07-29 19:31:51.000000000 +0200
4576 @@ -0,0 +1,209 @@
4577 +/* $Id: pciacacia.h,v 1.5 2001/05/01 10:09:17 carstenl Exp $
4578 + *
4579 + * This file is subject to the terms and conditions of the GNU General Public
4580 + * License. See the file "COPYING" in the main directory of this archive
4581 + * for more details.
4582 + */
4583 +#ifndef _PCIKORINA_H
4584 +#define _PCIKORINA_H
4585 +
4586 +
4587 +#define PCI_MSG_VirtualAddress 0xB8088010
4588 +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
4589 +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
4590 +
4591 +#define PCIM_SHFT 0x6
4592 +#define PCIM_BIT_LEN 0x7
4593 +#define PCIM_H_EA 0x3
4594 +#define PCIM_H_IA_FIX 0x4
4595 +#define PCIM_H_IA_RR 0x5
4596 +#if 0
4597 +#define PCI_ADDR_START 0x13000000
4598 +#endif
4599 +
4600 +#define PCI_ADDR_START 0x50000000
4601 +
4602 +#define CPUTOPCI_MEM_WIN 0x02000000
4603 +#define CPUTOPCI_IO_WIN 0x00100000
4604 +#define PCILBA_SIZE_SHFT 2
4605 +#define PCILBA_SIZE_MASK 0x1F
4606 +#define SIZE_256MB 0x1C
4607 +#define SIZE_128MB 0x1B
4608 +#define SIZE_64MB 0x1A
4609 +#define SIZE_32MB 0x19
4610 +#define SIZE_16MB 0x18
4611 +#define SIZE_4MB 0x16
4612 +#define SIZE_2MB 0x15
4613 +#define SIZE_1MB 0x14
4614 +#define KORINA_CONFIG0_ADDR 0x80000000
4615 +#define KORINA_CONFIG1_ADDR 0x80000004
4616 +#define KORINA_CONFIG2_ADDR 0x80000008
4617 +#define KORINA_CONFIG3_ADDR 0x8000000C
4618 +#define KORINA_CONFIG4_ADDR 0x80000010
4619 +#define KORINA_CONFIG5_ADDR 0x80000014
4620 +#define KORINA_CONFIG6_ADDR 0x80000018
4621 +#define KORINA_CONFIG7_ADDR 0x8000001C
4622 +#define KORINA_CONFIG8_ADDR 0x80000020
4623 +#define KORINA_CONFIG9_ADDR 0x80000024
4624 +#define KORINA_CONFIG10_ADDR 0x80000028
4625 +#define KORINA_CONFIG11_ADDR 0x8000002C
4626 +#define KORINA_CONFIG12_ADDR 0x80000030
4627 +#define KORINA_CONFIG13_ADDR 0x80000034
4628 +#define KORINA_CONFIG14_ADDR 0x80000038
4629 +#define KORINA_CONFIG15_ADDR 0x8000003C
4630 +#define KORINA_CONFIG16_ADDR 0x80000040
4631 +#define KORINA_CONFIG17_ADDR 0x80000044
4632 +#define KORINA_CONFIG18_ADDR 0x80000048
4633 +#define KORINA_CONFIG19_ADDR 0x8000004C
4634 +#define KORINA_CONFIG20_ADDR 0x80000050
4635 +#define KORINA_CONFIG21_ADDR 0x80000054
4636 +#define KORINA_CONFIG22_ADDR 0x80000058
4637 +#define KORINA_CONFIG23_ADDR 0x8000005C
4638 +#define KORINA_CONFIG24_ADDR 0x80000060
4639 +#define KORINA_CONFIG25_ADDR 0x80000064
4640 +#define KORINA_CMD (PCFG04_command_ioena_m | \
4641 + PCFG04_command_memena_m | \
4642 + PCFG04_command_bmena_m | \
4643 + PCFG04_command_mwinv_m | \
4644 + PCFG04_command_parena_m | \
4645 + PCFG04_command_serrena_m )
4646 +
4647 +#define KORINA_STAT (PCFG04_status_mdpe_m | \
4648 + PCFG04_status_sta_m | \
4649 + PCFG04_status_rta_m | \
4650 + PCFG04_status_rma_m | \
4651 + PCFG04_status_sse_m | \
4652 + PCFG04_status_pe_m)
4653 +
4654 +#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
4655 +
4656 +#define KORINA_REVID 0
4657 +#define KORINA_CLASS_CODE 0
4658 +#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
4659 + KORINA_REVID)
4660 +
4661 +#define KORINA_CACHE_LINE_SIZE 4
4662 +#define KORINA_MASTER_LAT 0x3c
4663 +#define KORINA_HEADER_TYPE 0
4664 +#define KORINA_BIST 0
4665 +
4666 +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
4667 + (KORINA_HEADER_TYPE<<16) | \
4668 + (KORINA_MASTER_LAT<<8) | \
4669 + KORINA_CACHE_LINE_SIZE )
4670 +
4671 +#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
4672 +#define KORINA_BAR1 0x18800001 /* 1 MB IO */
4673 +#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Acacia
4674 + internal Registers */
4675 +#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
4676 +
4677 +#define KORINA_CNFG4 KORINA_BAR0
4678 +#define KORINA_CNFG5 KORINA_BAR1
4679 +#define KORINA_CNFG6 KORINA_BAR2
4680 +#define KORINA_CNFG7 KORINA_BAR3
4681 +
4682 +#define KORINA_SUBSYS_VENDOR_ID 0
4683 +#define KORINA_SUBSYSTEM_ID 0
4684 +#define KORINA_CNFG8 0
4685 +#define KORINA_CNFG9 0
4686 +#define KORINA_CNFG10 0
4687 +#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
4688 + KORINA_SUBSYSTEM_ID)
4689 +#define KORINA_INT_LINE 1
4690 +#define KORINA_INT_PIN 1
4691 +#define KORINA_MIN_GNT 8
4692 +#define KORINA_MAX_LAT 0x38
4693 +#define KORINA_CNFG12 0
4694 +#define KORINA_CNFG13 0
4695 +#define KORINA_CNFG14 0
4696 +#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
4697 + (KORINA_MIN_GNT<<16) | \
4698 + (KORINA_INT_PIN<<8) | \
4699 + KORINA_INT_LINE)
4700 +#define KORINA_RETRY_LIMIT 0x80
4701 +#define KORINA_TRDY_LIMIT 0x80
4702 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
4703 + KORINA_TRDY_LIMIT)
4704 +#define PCI_PBAxC_R 0x0
4705 +#define PCI_PBAxC_RL 0x1
4706 +#define PCI_PBAxC_RM 0x2
4707 +#define SIZE_SHFT 2
4708 +
4709 +#ifdef __MIPSEB__
4710 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
4711 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
4712 + PCIPBAC_pp_m | \
4713 + (SIZE_32MB<<SIZE_SHFT) | \
4714 + PCIPBAC_p_m)
4715 +#else
4716 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | \
4717 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
4718 + PCIPBAC_pp_m | \
4719 + (SIZE_32MB<<SIZE_SHFT) | \
4720 + PCIPBAC_p_m)
4721 +#endif
4722 +
4723 +#if 0
4724 +
4725 +#define KORINA_PBA0C ( PCIPBAC_sb_m | PCIPBAC_pp_m | \
4726 + ((PCI_PBAxC_R &0x3) << PCIPBAC_mr_b) | \
4727 + (SIZE_128MB<<SIZE_SHFT))
4728 +#endif
4729 +#define KORINA_CNFG17 KORINA_PBA0C
4730 +#define KORINA_PBA0M 0x0
4731 +#define KORINA_CNFG18 KORINA_PBA0M
4732 +
4733 +#ifdef __MIPSEB__
4734 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
4735 + PCIPBAC_msi_m)
4736 +#else
4737 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
4738 + PCIPBAC_msi_m)
4739 +
4740 +#endif
4741 +
4742 +#define KORINA_CNFG19 KORINA_PBA1C
4743 +#define KORINA_PBA1M 0x0
4744 +#define KORINA_CNFG20 KORINA_PBA1M
4745 +
4746 +#ifdef __MIPSEB__
4747 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
4748 + PCIPBAC_msi_m)
4749 +#else
4750 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
4751 + PCIPBAC_msi_m)
4752 +
4753 +#endif
4754 +#define KORINA_CNFG21 KORINA_PBA2C
4755 +#define KORINA_PBA2M 0x18000000
4756 +#define KORINA_CNFG22 KORINA_PBA2M
4757 +#define KORINA_PBA3C 0
4758 +#define KORINA_CNFG23 KORINA_PBA3C
4759 +#define KORINA_PBA3M 0
4760 +#define KORINA_CNFG24 KORINA_PBA3M
4761 +
4762 +
4763 +
4764 +#define PCITC_DTIMER_VAL 8
4765 +#define PCITC_RTIMER_VAL 0x10
4766 +
4767 +
4768 +#endif /* _PCIKORINA_H */
4769 +
4770 +
4771 +
4772 +
4773 +
4774 +
4775 +
4776 +
4777 +
4778 +
4779 +
4780 +
4781 +
4782 +
4783 +
4784 +
4785 +
4786 diff -urN linux.old/include/asm-mips/rc32434/pci_regs.h linux.dev/include/asm-mips/rc32434/pci_regs.h
4787 --- linux.old/include/asm-mips/rc32434/pci_regs.h 1970-01-01 01:00:00.000000000 +0100
4788 +++ linux.dev/include/asm-mips/rc32434/pci_regs.h 2006-07-29 19:31:51.000000000 +0200
4789 @@ -0,0 +1,8 @@
4790 +/* Override the default address space for this arch
4791 +*/
4792 +
4793 +#include <linux/pci_regs.h>
4794 +
4795 +//#undef PCI_BASE_ADDRESS_SPACE
4796 +//#define PCI_BASE_ADDRESS_SPACE PCI_BASE_ADDRESS_SPACE_MEMORY
4797 +
4798 diff -urN linux.old/include/asm-mips/rc32434/rb.h linux.dev/include/asm-mips/rc32434/rb.h
4799 --- linux.old/include/asm-mips/rc32434/rb.h 1970-01-01 01:00:00.000000000 +0100
4800 +++ linux.dev/include/asm-mips/rc32434/rb.h 2006-07-29 19:31:51.000000000 +0200
4801 @@ -0,0 +1,69 @@
4802 +#ifndef __MIPS_RB_H__
4803 +#define __MIPS_RB_H__
4804 +#include <linux/genhd.h>
4805 +
4806 +#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000))
4807 +#define DEV0BASE 0x010000
4808 +#define DEV0MASK 0x010004
4809 +#define DEV0C 0x010008
4810 +#define DEV0TC 0x01000C
4811 +#define DEV1BASE 0x010010
4812 +#define DEV1MASK 0x010014
4813 +#define DEV1C 0x010018
4814 +#define DEV1TC 0x01001C
4815 +#define DEV2BASE 0x010020
4816 +#define DEV2MASK 0x010024
4817 +#define DEV2C 0x010028
4818 +#define DEV2TC 0x01002C
4819 +#define DEV3BASE 0x010030
4820 +#define DEV3MASK 0x010034
4821 +#define DEV3C 0x010038
4822 +#define DEV3TC 0x01003C
4823 +#define BTCS 0x010040
4824 +#define BTCOMPARE 0x010044
4825 +#define GPIOFUNC 0x050000
4826 +#define GPIOCFG 0x050004
4827 +#define GPIOD 0x050008
4828 +#define GPIOILEVEL 0x05000C
4829 +#define GPIOISTAT 0x050010
4830 +#define GPIONMIEN 0x050014
4831 +#define IMASK6 0x038038
4832 +
4833 +#define LO_WPX (1 << 0)
4834 +#define LO_ALE (1 << 1)
4835 +#define LO_CLE (1 << 2)
4836 +#define LO_CEX (1 << 3)
4837 +#define LO_FOFF (1 << 5)
4838 +#define LO_SPICS (1 << 6)
4839 +#define LO_ULED (1 << 7)
4840 +
4841 +typedef enum {
4842 + FUNC = 0x00,
4843 + CFG = 0x04,
4844 + DATA = 0x08,
4845 + ILEVEL = 0x0c,
4846 + ISTAT = 0x10,
4847 + NMIEN = 0x14
4848 +} gpio_func;
4849 +
4850 +extern void changeLatchU5(unsigned char orMask, unsigned char nandMask);
4851 +extern unsigned get434Reg(unsigned regOffs);
4852 +extern void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val);
4853 +extern void gpio_set(gpio_func func, u32 mask, u32 value);
4854 +extern u32 gpio_get(gpio_func func);
4855 +
4856 +#define get434Reg(x) (*(volatile unsigned *) (IDT434_REG_BASE + (x)))
4857 +
4858 +struct korina_device {
4859 + char *name;
4860 + unsigned char mac[6];
4861 + struct net_device *dev;
4862 +};
4863 +
4864 +struct cf_device {
4865 + int gpio_pin;
4866 + void *dev;
4867 + struct gendisk *gd;
4868 +};
4869 +
4870 +#endif
4871 diff -urN linux.old/include/asm-mips/rc32434/rc32434.h linux.dev/include/asm-mips/rc32434/rc32434.h
4872 --- linux.old/include/asm-mips/rc32434/rc32434.h 1970-01-01 01:00:00.000000000 +0100
4873 +++ linux.dev/include/asm-mips/rc32434/rc32434.h 2006-07-29 19:31:51.000000000 +0200
4874 @@ -0,0 +1,126 @@
4875 +/*
4876 + ***************************************************************************
4877 + * Definitions for IDT RC323434 CPU.
4878 + *
4879 + ****************************************************************************
4880 + * Kiran Rao
4881 + *
4882 + * Original form
4883 + ****************************************************************************
4884 + * P. Sadik Oct 08, 2003
4885 + *
4886 + * Started revision history
4887 + * Made IDT_BUS_FREQ a kernel configuration parameter
4888 + ****************************************************************************
4889 + * P. Sadik Oct 10, 2003
4890 + *
4891 + * Removed IDT_BUS_FREQ, since this parameter is no longer required. Instead
4892 + * idt_cpu_freq is used everywhere
4893 + ****************************************************************************
4894 + * P. Sadik Oct 20, 2003
4895 + *
4896 + * Removed RC32434_BASE_BAUD
4897 + ****************************************************************************
4898 +*/
4899 +#ifndef _RC32434_H_
4900 +#define _RC32434_H_
4901 +
4902 +#include <linux/config.h>
4903 +#include <linux/delay.h>
4904 +#include <asm/io.h>
4905 +#include <asm/rc32434/timer.h>
4906 +
4907 +#define RC32434_REG_BASE 0x18000000
4908 +
4909 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
4910 +#define timer ((volatile TIM_t) TIM0_VirtualAddress)
4911 +#define gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
4912 +
4913 +#define IDT_CLOCK_MULT 2
4914 +#define MIPS_CPU_TIMER_IRQ 7
4915 +/* Interrupt Controller */
4916 +#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
4917 +#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
4918 +#define IC_GROUP_OFFSET 0x0C
4919 +
4920 +#define NUM_INTR_GROUPS 5
4921 +/* 16550 UARTs */
4922 +
4923 +#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
4924 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
4925 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
4926 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
4927 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
4928 +
4929 +
4930 +#ifdef __MIPSEB__
4931 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
4932 +#else
4933 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
4934 +#endif
4935 +
4936 +#define RC32434_UART0_IRQ GROUP3_IRQ_BASE + 0
4937 +// #define EB434_UART1_IRQ GROUP4_IRQ_BASE + 11
4938 +
4939 +#define local_readl(addr) __raw_readl(addr)
4940 +#define local_writel(l,addr) __raw_writel(l,addr)
4941 +
4942 +/* cpu pipeline flush */
4943 +static inline void rc32434_sync(void)
4944 +{
4945 + __asm__ volatile ("sync");
4946 +}
4947 +
4948 +static inline void rc32434_sync_udelay(int us)
4949 +{
4950 + __asm__ volatile ("sync");
4951 + udelay(us);
4952 +}
4953 +
4954 +static inline void rc32434_sync_delay(int ms)
4955 +{
4956 + __asm__ volatile ("sync");
4957 + mdelay(ms);
4958 +}
4959 +
4960 +/*
4961 + * C access to CLZ and CLO instructions
4962 + * (count leading zeroes/ones).
4963 + */
4964 +static inline int rc32434_clz(unsigned long val)
4965 +{
4966 + int ret;
4967 + __asm__ volatile (
4968 + ".set\tnoreorder\n\t"
4969 + ".set\tnoat\n\t"
4970 + ".set\tmips32\n\t"
4971 + "clz\t%0,%1\n\t"
4972 + ".set\tmips0\n\t"
4973 + ".set\tat\n\t"
4974 + ".set\treorder"
4975 + : "=r" (ret)
4976 + : "r" (val));
4977 +
4978 + return ret;
4979 +}
4980 +static inline int rc32434_clo(unsigned long val)
4981 +{
4982 + int ret;
4983 + __asm__ volatile (
4984 + ".set\tnoreorder\n\t"
4985 + ".set\tnoat\n\t"
4986 + ".set\tmips32\n\t"
4987 + "clo\t%0,%1\n\t"
4988 + ".set\tmips0\n\t"
4989 + ".set\tat\n\t"
4990 + ".set\treorder"
4991 + : "=r" (ret)
4992 + : "r" (val));
4993 +
4994 + return ret;
4995 +}
4996 +
4997 +extern void cons_putc(char c);
4998 +extern void cons_puts(char *s);
4999 +
5000 +#endif /* _RC32434_H_ */
5001 diff -urN linux.old/include/asm-mips/rc32434/rst.h linux.dev/include/asm-mips/rc32434/rst.h
5002 --- linux.old/include/asm-mips/rc32434/rst.h 1970-01-01 01:00:00.000000000 +0100
5003 +++ linux.dev/include/asm-mips/rc32434/rst.h 2006-07-29 19:31:51.000000000 +0200
5004 @@ -0,0 +1,105 @@
5005 +#ifndef __IDT_RST_H__
5006 +#define __IDT_RST_H__
5007 +
5008 +/*******************************************************************************
5009 + *
5010 + * Copyright 2002 Integrated Device Technology, Inc.
5011 + * All rights reserved.
5012 + *
5013 + * Reset register definitions.
5014 + *
5015 + * File : $Id: rst.h,v 1.2 2002/06/06 18:34:05 astichte Exp $
5016 + *
5017 + * Author : Allen.Stichter@idt.com
5018 + * Date : 20020118
5019 + * Update :
5020 + * $Log: rst.h,v $
5021 + * Revision 1.2 2002/06/06 18:34:05 astichte
5022 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
5023 + *
5024 + * Revision 1.1 2002/05/29 17:33:24 sysarch
5025 + * jba File moved from vcode/include/idt/acacia
5026 + *
5027 + *
5028 + ******************************************************************************/
5029 +
5030 +#include <asm/rc32434/types.h>
5031 +
5032 +enum
5033 +{
5034 + RST0_PhysicalAddress = 0x18000000,
5035 + RST_PhysicalAddress = RST0_PhysicalAddress, // Default
5036 +
5037 + RST0_VirtualAddress = 0xb8000000,
5038 + RST_VirtualAddress = RST0_VirtualAddress, // Default
5039 +} ;
5040 +
5041 +typedef struct RST_s
5042 +{
5043 + U32 filler [0x0006] ;
5044 + U32 sysid ;
5045 + U32 filler2 [0x2000-8] ; // Pad out to offset 0x8000
5046 + U32 reset ;
5047 + U32 bcv ;
5048 + U32 cea ;
5049 +} volatile * RST_t ;
5050 +
5051 +enum
5052 +{
5053 + SYSID_rev_b = 0,
5054 + SYSID_rev_m = 0x000000ff,
5055 + SYSID_imp_b = 8,
5056 + SYSID_imp_m = 0x000fff00,
5057 + SYSID_vendor_b = 20,
5058 + SYSID_vendor_m = 0xfff00000,
5059 +
5060 + BCV_pll_b = 0,
5061 + BCV_pll_m = 0x0000000f,
5062 + BCV_pll_PLLBypass_v = 0x0, // PCLK=1*CLK.
5063 + BCV_pll_Mul3_v = 0x1, // PCLK=3*CLK.
5064 + BCV_pll_Mul4_v = 0x2, // PCLK=4*CLK.
5065 + BCV_pll_SlowMul5_v = 0x3, // PCLK=4*CLK.
5066 + BCV_pll_Mul5_v = 0x4, // PCLK=6*CLK.
5067 + BCV_pll_SlowMul6_v = 0x5, // PCLK=8*CLK.
5068 + BCV_pll_Mul6_v = 0x6, // PCLK=8*CLK.
5069 + BCV_pll_Mul8_v = 0x7, // PCLK=8*CLK.
5070 + BCV_pll_Mul10_v = 0x8, // PCLK=8*CLK.
5071 + BCV_pll_Res5_v = 0x9,
5072 + BCV_pll_Res6_v = 0xa,
5073 + BCV_pll_Res7_v = 0xb,
5074 + BCV_pll_Res8_v = 0xc,
5075 + BCV_pll_Res13_v = 0xd,
5076 + BCV_pll_Res14_v = 0xe,
5077 + BCV_pll_Res15_v = 0xf,
5078 + BCV_clkDiv_b = 4,
5079 + BCV_clkDiv_m = 0x00000030,
5080 + BCV_clkDiv_Div1_v = 0x0,
5081 + BCV_clkDiv_Div2_v = 0x1,
5082 + BCV_clkDiv_Div4_v = 0x2,
5083 + BCV_clkDiv_Res3_v = 0x3,
5084 + BCV_bigEndian_b = 6,
5085 + BCV_bigEndian_m = 0x00000040,
5086 + BCV_resetFast_b = 7,
5087 + BCV_resetFast_m = 0x00000080,
5088 + BCV_pciMode_b = 8,
5089 + BCV_pciMode_m = 0x00000100,
5090 + BCV_pciMode_disabled_v = 0, // PCI is disabled.
5091 + BCV_pciMode_tnr_v = 1, // satellite Target Not Ready.
5092 + BCV_pciMode_suspended_v = 2, // satellite with suspended CPU.
5093 + BCV_pciMode_external_v = 3, // host, external arbiter.
5094 + BCV_pciMode_fixed_v = 4, // host, fixed priority arbiter.
5095 + BCV_pciMode_roundRobin_v= 5, // host, round robin arbiter.
5096 + BCV_pciMode_res6_v = 6,
5097 + BCV_pciMode_res7_v = 7,
5098 + BCV_watchDisable_b = 11,
5099 + BCV_watchDisable_m = 0x00000800,
5100 + BCV_pllTest_b = 12,
5101 + BCV_pllTest_m = 0x00001000,
5102 + BCV_nvramInit_b = 13,
5103 + BCV_nvramInit_m = 0x00002000,
5104 + BCV_clksyncTstMd_b = 14,
5105 + BCV_clksyncTstMd_m = 0x00004000,
5106 + BCV_delayBypass_b = 15,
5107 + BCV_delayByPass_m = 0x00008000,
5108 +} ;
5109 +#endif // __IDT_RST_H__
5110 diff -urN linux.old/include/asm-mips/rc32434/spi.h linux.dev/include/asm-mips/rc32434/spi.h
5111 --- linux.old/include/asm-mips/rc32434/spi.h 1970-01-01 01:00:00.000000000 +0100
5112 +++ linux.dev/include/asm-mips/rc32434/spi.h 2006-07-29 19:31:51.000000000 +0200
5113 @@ -0,0 +1,100 @@
5114 +#ifndef __IDT_SPI_H__
5115 +#define __IDT_SPI_H__
5116 +
5117 +/*******************************************************************************
5118 + *
5119 + * Copyright 2002 Integrated Device Technology, Inc.
5120 + * All rights reserved.
5121 + *
5122 + * Serial Peripheral Interface register definitions.
5123 + *
5124 + * File : $Id: spi.h,v 1.2 2002/06/06 18:34:05 astichte Exp $
5125 + *
5126 + * Author : ryan.holmQVist@idt.com
5127 + * Date : 20011005
5128 + * Update :
5129 + * $Log: spi.h,v $
5130 + * Revision 1.2 2002/06/06 18:34:05 astichte
5131 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
5132 + *
5133 + * Revision 1.1 2002/05/29 17:33:25 sysarch
5134 + * jba File moved from vcode/include/idt/acacia
5135 + *
5136 + *
5137 + ******************************************************************************/
5138 +
5139 +#include <asm/rc32434/types.h>
5140 +
5141 +enum
5142 +{
5143 + SPI0_PhysicalAddress = 0x18070000,
5144 + SPI_PhysicalAddress = SPI0_PhysicalAddress,
5145 +
5146 + SPI0_VirtualAddress = 0xb8070000,
5147 + SPI_VirtualAddress = SPI0_VirtualAddress,
5148 +} ;
5149 +
5150 +typedef struct
5151 +{
5152 + U32 spcp ; // prescalar. 0=off, * spiClk = sysClk/(2*(spcp+1)*SPR)
5153 + U32 spc ; // spi control reg use SPC_
5154 + U32 sps ; // spi status reg use SPS_
5155 + U32 spd ; // spi data reg use SPD_
5156 + U32 siofunc ; // serial IO function use SIOFUNC_
5157 + U32 siocfg ; // serial IO config use SIOCFG_
5158 + U32 siod; // serial IO data use SIOD_
5159 +} volatile *SPI_t ;
5160 +
5161 +enum
5162 +{
5163 + SPCP_div_b = 0,
5164 + SPCP_div_m = 0x000000ff,
5165 + SPC_spr_b = 0,
5166 + SPC_spr_m = 0x00000003,
5167 + SPC_spr_div2_v = 0,
5168 + SPC_spr_div4_v = 1,
5169 + SPC_spr_div16_v = 2,
5170 + SPC_spr_div32_v = 3,
5171 + SPC_cpha_b = 2,
5172 + SPC_cpha_m = 0x00000004,
5173 + SPC_cpol_b = 3,
5174 + SPC_cpol_m = 0x00000008,
5175 + SPC_mstr_b = 4,
5176 + SPC_mstr_m = 0x00000010,
5177 + SPC_spe_b = 6,
5178 + SPC_spe_m = 0x00000040,
5179 + SPC_spie_b = 7,
5180 + SPC_spie_m = 0x00000080,
5181 +
5182 + SPS_modf_b = 4,
5183 + SPS_modf_m = 0x00000010,
5184 + SPS_wcol_b = 6,
5185 + SPS_wcol_m = 0x00000040,
5186 + SPS_spif_b = 7,
5187 + SPS_spif_m = 0x00000070,
5188 +
5189 + SPD_data_b = 0,
5190 + SPD_data_m = 0x000000ff,
5191 +
5192 + SIOFUNC_sdo_b = 0,
5193 + SIOFUNC_sdo_m = 0x00000001,
5194 + SIOFUNC_sdi_b = 1,
5195 + SIOFUNC_sdi_m = 0x00000002,
5196 + SIOFUNC_sck_b = 2,
5197 + SIOFUNC_sck_m = 0x00000004,
5198 +
5199 + SIOCFG_sdo_b = 0,
5200 + SIOCFG_sdo_m = 0x00000001,
5201 + SIOCFG_sdi_b = 1,
5202 + SIOCFG_sdi_m = 0x00000002,
5203 + SIOCFG_sck_b = 2,
5204 + SIOCFG_sck_m = 0x00000004,
5205 +
5206 + SIOD_sdo_b = 0,
5207 + SIOD_sdo_m = 0x00000001,
5208 + SIOD_sdi_b = 1,
5209 + SIOD_sdi_m = 0x00000002,
5210 + SIOD_sck_b = 2,
5211 + SIOD_sck_m = 0x00000004,
5212 +} ;
5213 +#endif // __IDT_SPI_H__
5214 diff -urN linux.old/include/asm-mips/rc32434/timer.h linux.dev/include/asm-mips/rc32434/timer.h
5215 --- linux.old/include/asm-mips/rc32434/timer.h 1970-01-01 01:00:00.000000000 +0100
5216 +++ linux.dev/include/asm-mips/rc32434/timer.h 2006-07-29 19:31:51.000000000 +0200
5217 @@ -0,0 +1,91 @@
5218 +/**************************************************************************
5219 + *
5220 + * BRIEF MODULE DESCRIPTION
5221 + * Definitions for timer registers
5222 + *
5223 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5224 + *
5225 + * This program is free software; you can redistribute it and/or modify it
5226 + * under the terms of the GNU General Public License as published by the
5227 + * Free Software Foundation; either version 2 of the License, or (at your
5228 + * option) any later version.
5229 + *
5230 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5231 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5232 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5233 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5234 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5235 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5236 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5237 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5238 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5239 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5240 + *
5241 + * You should have received a copy of the GNU General Public License along
5242 + * with this program; if not, write to the Free Software Foundation, Inc.,
5243 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5244 + *
5245 + *
5246 + **************************************************************************
5247 + * May 2004 rkt,neb.
5248 + *
5249 + * Initial Release
5250 + *
5251 + *
5252 + *
5253 + **************************************************************************
5254 + */
5255 +
5256 +#ifndef __IDT_TIM_H__
5257 +#define __IDT_TIM_H__
5258 +
5259 +enum
5260 +{
5261 + TIM0_PhysicalAddress = 0x18028000,
5262 + TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
5263 +
5264 + TIM0_VirtualAddress = 0xb8028000,
5265 + TIM_VirtualAddress = TIM0_VirtualAddress, // Default
5266 +} ;
5267 +
5268 +enum
5269 +{
5270 + TIM_Count = 3,
5271 +} ;
5272 +
5273 +struct TIM_CNTR_s
5274 +{
5275 + u32 count ;
5276 + u32 compare ;
5277 + u32 ctc ; //use CTC_
5278 +} ;
5279 +
5280 +typedef struct TIM_s
5281 +{
5282 + struct TIM_CNTR_s tim [TIM_Count] ;
5283 + u32 rcount ; //use RCOUNT_
5284 + u32 rcompare ; //use RCOMPARE_
5285 + u32 rtc ; //use RTC_
5286 +} volatile * TIM_t ;
5287 +
5288 +enum
5289 +{
5290 + CTC_en_b = 0,
5291 + CTC_en_m = 0x00000001,
5292 + CTC_to_b = 1,
5293 + CTC_to_m = 0x00000002,
5294 +
5295 + RCOUNT_count_b = 0,
5296 + RCOUNT_count_m = 0x0000ffff,
5297 + RCOMPARE_compare_b = 0,
5298 + RCOMPARE_compare_m = 0x0000ffff,
5299 + RTC_ce_b = 0,
5300 + RTC_ce_m = 0x00000001,
5301 + RTC_to_b = 1,
5302 + RTC_to_m = 0x00000002,
5303 + RTC_rqe_b = 2,
5304 + RTC_rqe_m = 0x00000004,
5305 +
5306 +} ;
5307 +#endif // __IDT_TIM_H__
5308 +
5309 diff -urN linux.old/include/asm-mips/rc32434/tim.h linux.dev/include/asm-mips/rc32434/tim.h
5310 --- linux.old/include/asm-mips/rc32434/tim.h 1970-01-01 01:00:00.000000000 +0100
5311 +++ linux.dev/include/asm-mips/rc32434/tim.h 2006-07-29 19:31:51.000000000 +0200
5312 @@ -0,0 +1,78 @@
5313 +#ifndef __IDT_TIM_H__
5314 +#define __IDT_TIM_H__
5315 +
5316 +/*******************************************************************************
5317 + *
5318 + * Copyright 2002 Integrated Device Technology, Inc.
5319 + * All rights reserved.
5320 + *
5321 + * Timer register definition.
5322 + *
5323 + * File : $Id: tim.h,v 1.2 2002/06/06 18:34:05 astichte Exp $
5324 + *
5325 + * Author : ryan.holmQVist@idt.com
5326 + * Date : 20011005
5327 + * Update :
5328 + * $Log: tim.h,v $
5329 + * Revision 1.2 2002/06/06 18:34:05 astichte
5330 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
5331 + *
5332 + * Revision 1.1 2002/05/29 17:33:25 sysarch
5333 + * jba File moved from vcode/include/idt/acacia
5334 + *
5335 + *
5336 + ******************************************************************************/
5337 +
5338 +
5339 +#include <asm/rc32434/types.h>
5340 +
5341 +enum
5342 +{
5343 + TIM0_PhysicalAddress = 0x18028000,
5344 + TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
5345 +
5346 + TIM0_VirtualAddress = 0xb8028000,
5347 + TIM_VirtualAddress = TIM0_VirtualAddress, // Default
5348 +} ;
5349 +
5350 +enum
5351 +{
5352 + TIM_Count = 3,
5353 +} ;
5354 +
5355 +struct TIM_CNTR_s
5356 +{
5357 + U32 count ;
5358 + U32 compare ;
5359 + U32 ctc ; //use CTC_
5360 +} ;
5361 +
5362 +typedef struct TIM_s
5363 +{
5364 + struct TIM_CNTR_s tim [TIM_Count] ;
5365 + U32 rcount ; //use RCOUNT_
5366 + U32 rcompare ; //use RCOMPARE_
5367 + U32 rtc ; //use RTC_
5368 +} volatile * TIM_t ;
5369 +
5370 +enum
5371 +{
5372 + CTC_en_b = 0,
5373 + CTC_en_m = 0x00000001,
5374 + CTC_to_b = 1,
5375 + CTC_to_m = 0x00000002,
5376 +
5377 + RCOUNT_count_b = 0,
5378 + RCOUNT_count_m = 0x0000ffff,
5379 + RCOMPARE_compare_b = 0,
5380 + RCOMPARE_compare_m = 0x0000ffff,
5381 + RTC_ce_b = 0,
5382 + RTC_ce_m = 0x00000001,
5383 + RTC_to_b = 1,
5384 + RTC_to_m = 0x00000002,
5385 + RTC_rqe_b = 2,
5386 + RTC_rqe_m = 0x00000004,
5387 +
5388 +} ;
5389 +#endif // __IDT_TIM_H__
5390 +
5391 diff -urN linux.old/include/asm-mips/rc32434/types.h linux.dev/include/asm-mips/rc32434/types.h
5392 --- linux.old/include/asm-mips/rc32434/types.h 1970-01-01 01:00:00.000000000 +0100
5393 +++ linux.dev/include/asm-mips/rc32434/types.h 2006-07-29 19:31:51.000000000 +0200
5394 @@ -0,0 +1,39 @@
5395 +#ifndef __IDT_TYPES_H__
5396 +#define __IDT_TYPES_H__
5397 +
5398 +/*******************************************************************************
5399 + *
5400 + * Copyright 2002 Integrated Device Technology, Inc.
5401 + * All rights reserved.
5402 + *
5403 + * Common typedefs used in IDT-generated code.
5404 + *
5405 + * File : $Id: types.h,v 1.1 2002/06/06 16:16:56 astichte Exp $
5406 + *
5407 + * Author : Allen.Stichter@idt.com
5408 + * Date : 20020606
5409 + * Update :
5410 + * $Log: types.h,v $
5411 + * Revision 1.1 2002/06/06 16:16:56 astichte
5412 + * Added
5413 + *
5414 + *
5415 + ******************************************************************************/
5416 +
5417 +typedef unsigned char U8 ;
5418 +typedef signed char S8 ;
5419 +
5420 +typedef unsigned short U16 ;
5421 +typedef signed short S16 ;
5422 +
5423 +typedef unsigned int U32 ;
5424 +typedef signed int S32 ;
5425 +
5426 +typedef unsigned long long U64 ;
5427 +typedef signed long long S64 ;
5428 +
5429 +#ifndef __cplusplus
5430 + typedef U32 bool ; // (false == 0), (true is != false)
5431 +#endif // __cplusplus
5432 +
5433 +#endif // __IDT_TYPES_H__
5434 diff -urN linux.old/include/asm-mips/rc32434/uart.h linux.dev/include/asm-mips/rc32434/uart.h
5435 --- linux.old/include/asm-mips/rc32434/uart.h 1970-01-01 01:00:00.000000000 +0100
5436 +++ linux.dev/include/asm-mips/rc32434/uart.h 2006-07-29 19:31:51.000000000 +0200
5437 @@ -0,0 +1,178 @@
5438 +#ifndef __IDT_UART_H__
5439 +#define __IDT_UART_H__
5440 +
5441 +/*******************************************************************************
5442 + *
5443 + * Copyright 2002 Integrated Device Technology, Inc.
5444 + * All rights reserved.
5445 + *
5446 + * UART register definitions.
5447 + *
5448 + * File : $Id: uart.h,v 1.3 2002/06/06 18:34:05 astichte Exp $
5449 + *
5450 + * Author : Allen.Stichter@idt.com
5451 + * Date : 20020118
5452 + * Update :
5453 + * $Log: uart.h,v $
5454 + * Revision 1.3 2002/06/06 18:34:05 astichte
5455 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
5456 + *
5457 + * Revision 1.2 2002/06/04 17:37:52 astichte
5458 + * Updated register definitions.
5459 + *
5460 + * Revision 1.1 2002/05/29 17:33:25 sysarch
5461 + * jba File moved from vcode/include/idt/acacia
5462 + *
5463 + *
5464 + ******************************************************************************/
5465 +
5466 +#include <asm/rc32434/types.h>
5467 +
5468 +enum
5469 +{
5470 + UART_PhysicalAddress = 0x18058000,
5471 + UART_PhysicalAddress = UART_PhysicalAddress, // Default
5472 +
5473 + UART_VirtualAddress = 0xb8058000,
5474 + UART_VirtualAddress = UART_VirtualAddress, // Default
5475 +} ;
5476 +
5477 +/*
5478 + * Register definitions are in bytes so we can handle endian problems.
5479 + */
5480 +
5481 +typedef struct UART_s
5482 +{
5483 + union
5484 + {
5485 + U32 const uartrb ; // 0x00 - DLAB=0, read.
5486 + U32 uartth ; // 0x00 - DLAB=0, write.
5487 + U32 uartdll ; // 0x00 - DLAB=1, read/write.
5488 + } ;
5489 +
5490 + union
5491 + {
5492 + U32 uartie ; // 0x04 - DLAB=0, read/write.
5493 + U32 uartdlh ; // 0x04 - DLAB=1, read/write.
5494 + } ;
5495 + union
5496 + {
5497 + U32 const uartii ; // 0x08 - DLAB=0, read.
5498 + U32 uartfc ; // 0x08 - DLAB=0, write.
5499 + } ;
5500 +
5501 + U32 uartlc ; // 0x0c
5502 + U32 uartmc ; // 0x10
5503 + U32 uartls ; // 0x14
5504 + U32 uartms ; // 0x18
5505 + U32 uarts ; // 0x1c
5506 +} volatile *UART_t ;
5507 +
5508 +// Reset registers.
5509 +typedef U32 volatile *UARTRR_t ;
5510 +
5511 +enum
5512 +{
5513 + UARTIE_rda_b = 0,
5514 + UARTIE_rda_m = 0x00000001,
5515 + UARTIE_the_b = 1,
5516 + UARTIE_the_m = 0x00000002,
5517 + UARTIE_rls_b = 2,
5518 + UARTIE_rls_m = 0x00000004,
5519 + UARTIE_ems_b = 3,
5520 + UARTIE_ems_m = 0x00000008,
5521 +
5522 + UARTII_pi_b = 0,
5523 + UARTII_pi_m = 0x00000001,
5524 + UARTII_iid_b = 1,
5525 + UARTII_iid_m = 0x0000000e,
5526 + UARTII_iid_ms_v = 0, // Modem stat-CTS,DSR,RI or DCD.
5527 + UARTII_iid_thre_v = 1, // Trans. Holding Reg. empty.
5528 + UARTII_iid_rda_v = 2, // Receive data available
5529 + UARTII_iid_rls_v = 3, // Overrun, parity, etc, error.
5530 + UARTII_iid_res4_v = 4, // reserved.
5531 + UARTII_iid_res5_v = 5, // reserved.
5532 + UARTII_iid_cto_v = 6, // Character timeout.
5533 + UARTII_iid_res7_v = 7, // reserved.
5534 +
5535 + UARTFC_en_b = 0,
5536 + UARTFC_en_m = 0x00000001,
5537 + UARTFC_rr_b = 1,
5538 + UARTFC_rr_m = 0x00000002,
5539 + UARTFC_tr_b = 2,
5540 + UARTFC_tr_m = 0x00000004,
5541 + UARTFC_dms_b = 3,
5542 + UARTFC_dms_m = 0x00000008,
5543 + UARTFC_rt_b = 6,
5544 + UARTFC_rt_m = 0x000000c0,
5545 + UARTFC_rt_1Byte_v = 0,
5546 + UARTFC_rt_4Byte_v = 1,
5547 + UARTFC_rt_8Byte_v = 2,
5548 + UARTFC_rt_14Byte_v = 3,
5549 +
5550 + UARTLC_wls_b = 0,
5551 + UARTLC_wls_m = 0x00000003,
5552 + UARTLC_wls_5Bits_v = 0,
5553 + UARTLC_wls_6Bits_v = 1,
5554 + UARTLC_wls_7Bits_v = 2,
5555 + UARTLC_wls_8Bits_v = 3,
5556 + UARTLC_stb_b = 2,
5557 + UARTLC_stb_m = 0x00000004,
5558 + UARTLC_pen_b = 3,
5559 + UARTLC_pen_m = 0x00000008,
5560 + UARTLC_eps_b = 4,
5561 + UARTLC_eps_m = 0x00000010,
5562 + UARTLC_sp_b = 5,
5563 + UARTLC_sp_m = 0x00000020,
5564 + UARTLC_sb_b = 6,
5565 + UARTLC_sb_m = 0x00000040,
5566 + UARTLC_dlab_b = 7,
5567 + UARTLC_dlab_m = 0x00000080,
5568 +
5569 + UARTMC_dtr_b = 0,
5570 + UARTMC_dtr_m = 0x00000001,
5571 + UARTMC_rts_b = 1,
5572 + UARTMC_rts_m = 0x00000002,
5573 + UARTMC_o1_b = 2,
5574 + UARTMC_o1_m = 0x00000004,
5575 + UARTMC_o2_b = 3,
5576 + UARTMC_o2_m = 0x00000008,
5577 + UARTMC_lp_b = 4,
5578 + UARTMC_lp_m = 0x00000010,
5579 +
5580 + UARTLS_dr_b = 0,
5581 + UARTLS_dr_m = 0x00000001,
5582 + UARTLS_oe_b = 1,
5583 + UARTLS_oe_m = 0x00000002,
5584 + UARTLS_pe_b = 2,
5585 + UARTLS_pe_m = 0x00000004,
5586 + UARTLS_fe_b = 3,
5587 + UARTLS_fe_m = 0x00000008,
5588 + UARTLS_bi_b = 4,
5589 + UARTLS_bi_m = 0x00000010,
5590 + UARTLS_thr_b = 5,
5591 + UARTLS_thr_m = 0x00000020,
5592 + UARTLS_te_b = 6,
5593 + UARTLS_te_m = 0x00000040,
5594 + UARTLS_rfe_b = 7,
5595 + UARTLS_rfe_m = 0x00000080,
5596 +
5597 + UARTMS_dcts_b = 0,
5598 + UARTMS_dcts_m = 0x00000001,
5599 + UARTMS_ddsr_b = 1,
5600 + UARTMS_ddsr_m = 0x00000002,
5601 + UARTMS_teri_b = 2,
5602 + UARTMS_teri_m = 0x00000004,
5603 + UARTMS_ddcd_b = 3,
5604 + UARTMS_ddcd_m = 0x00000008,
5605 + UARTMS_cts_b = 4,
5606 + UARTMS_cts_m = 0x00000010,
5607 + UARTMS_dsr_b = 5,
5608 + UARTMS_dsr_m = 0x00000020,
5609 + UARTMS_ri_b = 6,
5610 + UARTMS_ri_m = 0x00000040,
5611 + UARTMS_dcd_b = 7,
5612 + UARTMS_dcd_m = 0x00000080,
5613 +} ;
5614 +
5615 +#endif // __IDT_UART_H__
Staging tree of Mathias Kresin