target/linux/adm5120-2.6/files/arch/mips/pci/ops-adm5120.c

   1 /*
   2  *  $Id$
   3  *
   4  *  ADM5120 specific PCI operations
   5  *
   6  *  Copyright (C) ADMtek Incorporated.
   7  *  Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
   8  *  Copyright (C) 2007 Gabor Juhos <juhosg@freemail.hu>
   9  *  Copyright (C) 2007 OpenWrt.org
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version 2
  14  *  of the License, or (at your option) any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful,
  17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *  GNU General Public License for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License
  22  *  along with this program; if not, write to the
  23  *  Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
  24  *  Boston, MA  02110-1301, USA.
  25  *
  26  */
  27
  28 #include <linux/types.h>
  29 #include <linux/kernel.h>
  30 #include <linux/pci.h>
  31
  32 #include <asm/mach-adm5120/adm5120_defs.h>
  33
  34 #define DEBUG   0
  35 #if DEBUG
  36 #define DBG(f, ...) printk(f, ## __VA_ARGS__ )
  37 #else
  38 #define DBG(f, ...)
  39 #endif
  40
  41 #define PCI_ENABLE 0x80000000
  42
  43 static inline void write_cfgaddr(u32 addr)
  44 {
  45         *(volatile u32*)KSEG1ADDR(ADM5120_PCICFG_ADDR) = (addr | PCI_ENABLE);
  46 }
  47
  48 static inline void write_cfgdata(u32 data)
  49 {
  50         *(volatile u32*)KSEG1ADDR(ADM5120_PCICFG_DATA) = data;
  51
  52 }
  53
  54 static inline u32 read_cfgdata(void)
  55 {
  56         return (*(volatile u32*)KSEG1ADDR(ADM5120_PCICFG_DATA));
  57 }
  58
  59 static inline u32 mkaddr(struct pci_bus *bus, unsigned int devfn, int where)
  60 {
  61         return (((bus->number & 0xFF) << 16) | ((devfn & 0xFF) << 8) | \
  62                 (where & 0xFC));
  63 }
  64
  65 static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
  66                            int size, u32 *val)
  67 {
  68         u32 data;
  69
  70         write_cfgaddr(mkaddr(bus,devfn,where));
  71         data = read_cfgdata();
  72
  73         DBG("PCI: cfg_read  %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
  74                 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, data);
  75
  76         switch (size) {
  77         case 1:
  78                 if (where & 1)
  79                         data >>= 8;
  80                 if (where & 2)
  81                         data >>= 16;
  82                 data &= 0xFF;
  83                 break;
  84         case 2:
  85                 if (where & 2)
  86                         data >>= 16;
  87                 data &= 0xFFFF;
  88                 break;
  89         }
  90
  91         *val = data;
  92         DBG(", 0x%08X returned\n", data);
  93
  94         return PCIBIOS_SUCCESSFUL;
  95 }
  96
  97 static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
  98                             int size, u32 val)
  99 {
 100         u32 data;
 101         int s;
 102
 103         write_cfgaddr(mkaddr(bus,devfn,where));
 104         data = read_cfgdata();
 105
 106         DBG("PCI: cfg_write %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
 107                 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, data);
 108
 109         switch (size) {
 110         case 1:
 111                 s = ((where & 3) << 3);
 112                 data &= ~(0xFF << s);
 113                 data |= ((val & 0xFF) << s);
 114                 break;
 115         case 2:
 116                 s = ((where & 2) << 4);
 117                 data &= ~(0xFFFF << s);
 118                 data |= ((val & 0xFFFF) << s);
 119                 break;
 120         case 4:
 121                 data = val;
 122                 break;
 123         }
 124
 125         write_cfgdata(data);
 126         DBG(", 0x%08X written\n", data);
 127
 128         return PCIBIOS_SUCCESSFUL;
 129 }
 130
 131 struct pci_ops adm5120_pci_ops = {
 132         .read   = pci_config_read,
 133         .write  = pci_config_write,
 134 };