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atheros: indent fixes
[openwrt/staging/mkresin.git] / target / linux / atheros / patches-3.10 / 110-ar2313_ethernet.patch
1 --- a/drivers/net/ethernet/Kconfig
2 +++ b/drivers/net/ethernet/Kconfig
3 @@ -22,6 +22,7 @@ source "drivers/net/ethernet/adaptec/Kco
4 source "drivers/net/ethernet/aeroflex/Kconfig"
5 source "drivers/net/ethernet/alteon/Kconfig"
6 source "drivers/net/ethernet/amd/Kconfig"
7 +source "drivers/net/ethernet/ar231x/Kconfig"
8 source "drivers/net/ethernet/apple/Kconfig"
9 source "drivers/net/ethernet/atheros/Kconfig"
10 source "drivers/net/ethernet/cadence/Kconfig"
11 --- a/drivers/net/ethernet/Makefile
12 +++ b/drivers/net/ethernet/Makefile
13 @@ -9,6 +9,7 @@ obj-$(CONFIG_GRETH) += aeroflex/
14 obj-$(CONFIG_NET_VENDOR_ALTEON) += alteon/
15 obj-$(CONFIG_NET_VENDOR_AMD) += amd/
16 obj-$(CONFIG_NET_VENDOR_APPLE) += apple/
17 +obj-$(CONFIG_NET_VENDOR_AR231X) += ar231x/
18 obj-$(CONFIG_NET_VENDOR_ATHEROS) += atheros/
19 obj-$(CONFIG_NET_CADENCE) += cadence/
20 obj-$(CONFIG_NET_BFIN) += adi/
21 --- /dev/null
22 +++ b/drivers/net/ethernet/ar231x/Kconfig
23 @@ -0,0 +1,5 @@
24 +config NET_VENDOR_AR231X
25 + tristate "AR231X Ethernet support"
26 + depends on ATHEROS_AR231X
27 + help
28 + Support for the AR231x/531x ethernet controller
29 --- /dev/null
30 +++ b/drivers/net/ethernet/ar231x/Makefile
31 @@ -0,0 +1 @@
32 +obj-$(CONFIG_NET_VENDOR_AR231X) += ar231x.o
33 --- /dev/null
34 +++ b/drivers/net/ethernet/ar231x/ar231x.c
35 @@ -0,0 +1,1255 @@
36 +/*
37 + * ar231x.c: Linux driver for the Atheros AR231x Ethernet device.
38 + *
39 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
40 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
41 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
42 + *
43 + * Thanks to Atheros for providing hardware and documentation
44 + * enabling me to write this driver.
45 + *
46 + * This program is free software; you can redistribute it and/or modify
47 + * it under the terms of the GNU General Public License as published by
48 + * the Free Software Foundation; either version 2 of the License, or
49 + * (at your option) any later version.
50 + *
51 + * Additional credits:
52 + * This code is taken from John Taylor's Sibyte driver and then
53 + * modified for the AR2313.
54 + */
55 +
56 +#include <linux/module.h>
57 +#include <linux/version.h>
58 +#include <linux/types.h>
59 +#include <linux/errno.h>
60 +#include <linux/ioport.h>
61 +#include <linux/pci.h>
62 +#include <linux/netdevice.h>
63 +#include <linux/etherdevice.h>
64 +#include <linux/interrupt.h>
65 +#include <linux/hardirq.h>
66 +#include <linux/skbuff.h>
67 +#include <linux/init.h>
68 +#include <linux/delay.h>
69 +#include <linux/mm.h>
70 +#include <linux/highmem.h>
71 +#include <linux/sockios.h>
72 +#include <linux/pkt_sched.h>
73 +#include <linux/mii.h>
74 +#include <linux/phy.h>
75 +#include <linux/ethtool.h>
76 +#include <linux/ctype.h>
77 +#include <linux/platform_device.h>
78 +#include <linux/io.h>
79 +#include <linux/uaccess.h>
80 +
81 +#include <net/sock.h>
82 +#include <net/ip.h>
83 +
84 +#define AR2313_MTU 1692
85 +#define AR2313_PRIOS 1
86 +#define AR2313_QUEUES (2*AR2313_PRIOS)
87 +#define AR2313_DESCR_ENTRIES 64
88 +
89 +
90 +#ifndef min
91 +#define min(a,b) (((a)<(b))?(a):(b))
92 +#endif
93 +
94 +#ifndef SMP_CACHE_BYTES
95 +#define SMP_CACHE_BYTES L1_CACHE_BYTES
96 +#endif
97 +
98 +#define AR2313_MBOX_SET_BIT 0x8
99 +
100 +#include "ar231x.h"
101 +
102 +/**
103 + * New interrupt handler strategy:
104 + *
105 + * An old interrupt handler worked using the traditional method of
106 + * replacing an skbuff with a new one when a packet arrives. However
107 + * the rx rings do not need to contain a static number of buffer
108 + * descriptors, thus it makes sense to move the memory allocation out
109 + * of the main interrupt handler and do it in a bottom half handler
110 + * and only allocate new buffers when the number of buffers in the
111 + * ring is below a certain threshold. In order to avoid starving the
112 + * NIC under heavy load it is however necessary to force allocation
113 + * when hitting a minimum threshold. The strategy for alloction is as
114 + * follows:
115 + *
116 + * RX_LOW_BUF_THRES - allocate buffers in the bottom half
117 + * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
118 + * the buffers in the interrupt handler
119 + * RX_RING_THRES - maximum number of buffers in the rx ring
120 + *
121 + * One advantagous side effect of this allocation approach is that the
122 + * entire rx processing can be done without holding any spin lock
123 + * since the rx rings and registers are totally independent of the tx
124 + * ring and its registers. This of course includes the kmalloc's of
125 + * new skb's. Thus start_xmit can run in parallel with rx processing
126 + * and the memory allocation on SMP systems.
127 + *
128 + * Note that running the skb reallocation in a bottom half opens up
129 + * another can of races which needs to be handled properly. In
130 + * particular it can happen that the interrupt handler tries to run
131 + * the reallocation while the bottom half is either running on another
132 + * CPU or was interrupted on the same CPU. To get around this the
133 + * driver uses bitops to prevent the reallocation routines from being
134 + * reentered.
135 + *
136 + * TX handling can also be done without holding any spin lock, wheee
137 + * this is fun! since tx_csm is only written to by the interrupt
138 + * handler.
139 + */
140 +
141 +/**
142 + * Threshold values for RX buffer allocation - the low water marks for
143 + * when to start refilling the rings are set to 75% of the ring
144 + * sizes. It seems to make sense to refill the rings entirely from the
145 + * intrrupt handler once it gets below the panic threshold, that way
146 + * we don't risk that the refilling is moved to another CPU when the
147 + * one running the interrupt handler just got the slab code hot in its
148 + * cache.
149 + */
150 +#define RX_RING_SIZE AR2313_DESCR_ENTRIES
151 +#define RX_PANIC_THRES (RX_RING_SIZE/4)
152 +#define RX_LOW_THRES ((3*RX_RING_SIZE)/4)
153 +#define CRC_LEN 4
154 +#define RX_OFFSET 2
155 +
156 +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
157 +#define VLAN_HDR 4
158 +#else
159 +#define VLAN_HDR 0
160 +#endif
161 +
162 +#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + RX_OFFSET)
163 +
164 +#ifdef MODULE
165 +MODULE_LICENSE("GPL");
166 +MODULE_AUTHOR("Sameer Dekate <sdekate@arubanetworks.com>, Imre Kaloz <kaloz@openwrt.org>, Felix Fietkau <nbd@openwrt.org>");
167 +MODULE_DESCRIPTION("AR231x Ethernet driver");
168 +#endif
169 +
170 +#define virt_to_phys(x) ((u32)(x) & 0x1fffffff)
171 +
172 +/* prototypes */
173 +static void ar231x_halt(struct net_device *dev);
174 +static void rx_tasklet_func(unsigned long data);
175 +static void rx_tasklet_cleanup(struct net_device *dev);
176 +static void ar231x_multicast_list(struct net_device *dev);
177 +static void ar231x_tx_timeout(struct net_device *dev);
178 +
179 +static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum);
180 +static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value);
181 +static int ar231x_mdiobus_reset(struct mii_bus *bus);
182 +static int ar231x_mdiobus_probe (struct net_device *dev);
183 +static void ar231x_adjust_link(struct net_device *dev);
184 +
185 +#ifndef ERR
186 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
187 +#endif
188 +
189 +#ifdef CONFIG_NET_POLL_CONTROLLER
190 +static void
191 +ar231x_netpoll(struct net_device *dev)
192 +{
193 + unsigned long flags;
194 +
195 + local_irq_save(flags);
196 + ar231x_interrupt(dev->irq, dev);
197 + local_irq_restore(flags);
198 +}
199 +#endif
200 +
201 +static const struct net_device_ops ar231x_ops = {
202 + .ndo_open = ar231x_open,
203 + .ndo_stop = ar231x_close,
204 + .ndo_start_xmit = ar231x_start_xmit,
205 + .ndo_set_rx_mode = ar231x_multicast_list,
206 + .ndo_do_ioctl = ar231x_ioctl,
207 + .ndo_change_mtu = eth_change_mtu,
208 + .ndo_validate_addr = eth_validate_addr,
209 + .ndo_set_mac_address = eth_mac_addr,
210 + .ndo_tx_timeout = ar231x_tx_timeout,
211 +#ifdef CONFIG_NET_POLL_CONTROLLER
212 + .ndo_poll_controller = ar231x_netpoll,
213 +#endif
214 +};
215 +
216 +int ar231x_probe(struct platform_device *pdev)
217 +{
218 + struct net_device *dev;
219 + struct ar231x_private *sp;
220 + struct resource *res;
221 + unsigned long ar_eth_base;
222 + char buf[64];
223 +
224 + dev = alloc_etherdev(sizeof(struct ar231x_private));
225 +
226 + if (dev == NULL) {
227 + printk(KERN_ERR
228 + "ar231x: Unable to allocate net_device structure!\n");
229 + return -ENOMEM;
230 + }
231 +
232 + platform_set_drvdata(pdev, dev);
233 +
234 + sp = netdev_priv(dev);
235 + sp->dev = dev;
236 + sp->cfg = pdev->dev.platform_data;
237 +
238 + sprintf(buf, "eth%d_membase", pdev->id);
239 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf);
240 + if (!res)
241 + return -ENODEV;
242 +
243 + sp->link = 0;
244 + ar_eth_base = res->start;
245 +
246 + sprintf(buf, "eth%d_irq", pdev->id);
247 + dev->irq = platform_get_irq_byname(pdev, buf);
248 +
249 + spin_lock_init(&sp->lock);
250 +
251 + dev->features |= NETIF_F_HIGHDMA;
252 + dev->netdev_ops = &ar231x_ops;
253 +
254 + tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev);
255 + tasklet_disable(&sp->rx_tasklet);
256 +
257 + sp->eth_regs =
258 + ioremap_nocache(virt_to_phys(ar_eth_base), sizeof(*sp->eth_regs));
259 + if (!sp->eth_regs) {
260 + printk("Can't remap eth registers\n");
261 + return -ENXIO;
262 + }
263 +
264 + /**
265 + * When there's only one MAC, PHY regs are typically on ENET0,
266 + * even though the MAC might be on ENET1.
267 + * Needto remap PHY regs separately in this case
268 + */
269 + if (virt_to_phys(ar_eth_base) == virt_to_phys(sp->phy_regs))
270 + sp->phy_regs = sp->eth_regs;
271 + else {
272 + sp->phy_regs =
273 + ioremap_nocache(virt_to_phys(sp->cfg->phy_base),
274 + sizeof(*sp->phy_regs));
275 + if (!sp->phy_regs) {
276 + printk("Can't remap phy registers\n");
277 + return -ENXIO;
278 + }
279 + }
280 +
281 + sp->dma_regs =
282 + ioremap_nocache(virt_to_phys(ar_eth_base + 0x1000),
283 + sizeof(*sp->dma_regs));
284 + dev->base_addr = (unsigned int) sp->dma_regs;
285 + if (!sp->dma_regs) {
286 + printk("Can't remap DMA registers\n");
287 + return -ENXIO;
288 + }
289 +
290 + sp->int_regs = ioremap_nocache(virt_to_phys(sp->cfg->reset_base), 4);
291 + if (!sp->int_regs) {
292 + printk("Can't remap INTERRUPT registers\n");
293 + return -ENXIO;
294 + }
295 +
296 + strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1);
297 + sp->name[sizeof(sp->name) - 1] = '\0';
298 + memcpy(dev->dev_addr, sp->cfg->macaddr, 6);
299 +
300 + if (ar231x_init(dev)) {
301 + /* ar231x_init() calls ar231x_init_cleanup() on error */
302 + kfree(dev);
303 + return -ENODEV;
304 + }
305 +
306 + if (register_netdev(dev)) {
307 + printk("%s: register_netdev failed\n", __func__);
308 + return -1;
309 + }
310 +
311 + printk("%s: %s: %02x:%02x:%02x:%02x:%02x:%02x, irq %d\n",
312 + dev->name, sp->name,
313 + dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
314 + dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], dev->irq);
315 +
316 + sp->mii_bus = mdiobus_alloc();
317 + if (sp->mii_bus == NULL)
318 + return -1;
319 +
320 + sp->mii_bus->priv = dev;
321 + sp->mii_bus->read = ar231x_mdiobus_read;
322 + sp->mii_bus->write = ar231x_mdiobus_write;
323 + sp->mii_bus->reset = ar231x_mdiobus_reset;
324 + sp->mii_bus->name = "ar231x_eth_mii";
325 + snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
326 + sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL);
327 + *sp->mii_bus->irq = PHY_POLL;
328 +
329 + mdiobus_register(sp->mii_bus);
330 +
331 + if (ar231x_mdiobus_probe(dev) != 0) {
332 + printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
333 + rx_tasklet_cleanup(dev);
334 + ar231x_init_cleanup(dev);
335 + unregister_netdev(dev);
336 + kfree(dev);
337 + return -ENODEV;
338 + }
339 +
340 + /* start link poll timer */
341 + ar231x_setup_timer(dev);
342 +
343 + return 0;
344 +}
345 +
346 +
347 +static void ar231x_multicast_list(struct net_device *dev)
348 +{
349 + struct ar231x_private *sp = netdev_priv(dev);
350 + unsigned int filter;
351 +
352 + filter = sp->eth_regs->mac_control;
353 +
354 + if (dev->flags & IFF_PROMISC)
355 + filter |= MAC_CONTROL_PR;
356 + else
357 + filter &= ~MAC_CONTROL_PR;
358 + if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0))
359 + filter |= MAC_CONTROL_PM;
360 + else
361 + filter &= ~MAC_CONTROL_PM;
362 +
363 + sp->eth_regs->mac_control = filter;
364 +}
365 +
366 +static void rx_tasklet_cleanup(struct net_device *dev)
367 +{
368 + struct ar231x_private *sp = netdev_priv(dev);
369 +
370 + /**
371 + * Tasklet may be scheduled. Need to get it removed from the list
372 + * since we're about to free the struct.
373 + */
374 +
375 + sp->unloading = 1;
376 + tasklet_enable(&sp->rx_tasklet);
377 + tasklet_kill(&sp->rx_tasklet);
378 +}
379 +
380 +static int ar231x_remove(struct platform_device *pdev)
381 +{
382 + struct net_device *dev = platform_get_drvdata(pdev);
383 + struct ar231x_private *sp = netdev_priv(dev);
384 + rx_tasklet_cleanup(dev);
385 + ar231x_init_cleanup(dev);
386 + unregister_netdev(dev);
387 + mdiobus_unregister(sp->mii_bus);
388 + mdiobus_free(sp->mii_bus);
389 + kfree(dev);
390 + return 0;
391 +}
392 +
393 +
394 +/**
395 + * Restart the AR2313 ethernet controller.
396 + */
397 +static int ar231x_restart(struct net_device *dev)
398 +{
399 + /* disable interrupts */
400 + disable_irq(dev->irq);
401 +
402 + /* stop mac */
403 + ar231x_halt(dev);
404 +
405 + /* initialize */
406 + ar231x_init(dev);
407 +
408 + /* enable interrupts */
409 + enable_irq(dev->irq);
410 +
411 + return 0;
412 +}
413 +
414 +static struct platform_driver ar231x_driver = {
415 + .driver.name = "ar231x-eth",
416 + .probe = ar231x_probe,
417 + .remove = ar231x_remove,
418 +};
419 +
420 +module_platform_driver(ar231x_driver);
421 +
422 +static void ar231x_free_descriptors(struct net_device *dev)
423 +{
424 + struct ar231x_private *sp = netdev_priv(dev);
425 + if (sp->rx_ring != NULL) {
426 + kfree((void *) KSEG0ADDR(sp->rx_ring));
427 + sp->rx_ring = NULL;
428 + sp->tx_ring = NULL;
429 + }
430 +}
431 +
432 +
433 +static int ar231x_allocate_descriptors(struct net_device *dev)
434 +{
435 + struct ar231x_private *sp = netdev_priv(dev);
436 + int size;
437 + int j;
438 + ar231x_descr_t *space;
439 +
440 + if (sp->rx_ring != NULL) {
441 + printk("%s: already done.\n", __FUNCTION__);
442 + return 0;
443 + }
444 +
445 + size =
446 + (sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES));
447 + space = kmalloc(size, GFP_KERNEL);
448 + if (space == NULL)
449 + return 1;
450 +
451 + /* invalidate caches */
452 + dma_cache_inv((unsigned int) space, size);
453 +
454 + /* now convert pointer to KSEG1 */
455 + space = (ar231x_descr_t *) KSEG1ADDR(space);
456 +
457 + memset((void *) space, 0, size);
458 +
459 + sp->rx_ring = space;
460 + space += AR2313_DESCR_ENTRIES;
461 +
462 + sp->tx_ring = space;
463 + space += AR2313_DESCR_ENTRIES;
464 +
465 + /* Initialize the transmit Descriptors */
466 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
467 + ar231x_descr_t *td = &sp->tx_ring[j];
468 + td->status = 0;
469 + td->devcs = DMA_TX1_CHAINED;
470 + td->addr = 0;
471 + td->descr =
472 + virt_to_phys(&sp->
473 + tx_ring[(j + 1) & (AR2313_DESCR_ENTRIES - 1)]);
474 + }
475 +
476 + return 0;
477 +}
478 +
479 +
480 +/**
481 + * Generic cleanup handling data allocated during init. Used when the
482 + * module is unloaded or if an error occurs during initialization
483 + */
484 +static void ar231x_init_cleanup(struct net_device *dev)
485 +{
486 + struct ar231x_private *sp = netdev_priv(dev);
487 + struct sk_buff *skb;
488 + int j;
489 +
490 + ar231x_free_descriptors(dev);
491 +
492 + if (sp->eth_regs)
493 + iounmap((void *) sp->eth_regs);
494 + if (sp->dma_regs)
495 + iounmap((void *) sp->dma_regs);
496 +
497 + if (sp->rx_skb) {
498 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
499 + skb = sp->rx_skb[j];
500 + if (skb) {
501 + sp->rx_skb[j] = NULL;
502 + dev_kfree_skb(skb);
503 + }
504 + }
505 + kfree(sp->rx_skb);
506 + sp->rx_skb = NULL;
507 + }
508 +
509 + if (sp->tx_skb) {
510 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
511 + skb = sp->tx_skb[j];
512 + if (skb) {
513 + sp->tx_skb[j] = NULL;
514 + dev_kfree_skb(skb);
515 + }
516 + }
517 + kfree(sp->tx_skb);
518 + sp->tx_skb = NULL;
519 + }
520 +}
521 +
522 +static int ar231x_setup_timer(struct net_device *dev)
523 +{
524 + struct ar231x_private *sp = netdev_priv(dev);
525 +
526 + init_timer(&sp->link_timer);
527 +
528 + sp->link_timer.function = ar231x_link_timer_fn;
529 + sp->link_timer.data = (int) dev;
530 + sp->link_timer.expires = jiffies + HZ;
531 +
532 + add_timer(&sp->link_timer);
533 + return 0;
534 +}
535 +
536 +static void ar231x_link_timer_fn(unsigned long data)
537 +{
538 + struct net_device *dev = (struct net_device *) data;
539 + struct ar231x_private *sp = netdev_priv(dev);
540 +
541 + /**
542 + * See if the link status changed.
543 + * This was needed to make sure we set the PHY to the
544 + * autonegotiated value of half or full duplex.
545 + */
546 + ar231x_check_link(dev);
547 +
548 + /**
549 + * Loop faster when we don't have link.
550 + * This was needed to speed up the AP bootstrap time.
551 + */
552 + if (sp->link == 0)
553 + mod_timer(&sp->link_timer, jiffies + HZ / 2);
554 + else
555 + mod_timer(&sp->link_timer, jiffies + LINK_TIMER);
556 +}
557 +
558 +static void ar231x_check_link(struct net_device *dev)
559 +{
560 + struct ar231x_private *sp = netdev_priv(dev);
561 + u16 phy_data;
562 +
563 + phy_data = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR);
564 + if (sp->phy_data != phy_data) {
565 + if (phy_data & BMSR_LSTATUS) {
566 + /**
567 + * Link is present, ready link partner ability to
568 + * deterine duplexity.
569 + */
570 + int duplex = 0;
571 + u16 reg;
572 +
573 + sp->link = 1;
574 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMCR);
575 + if (reg & BMCR_ANENABLE) {
576 + /* auto neg enabled */
577 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_LPA);
578 + duplex = (reg & (LPA_100FULL | LPA_10FULL)) ? 1 : 0;
579 + } else {
580 + /* no auto neg, just read duplex config */
581 + duplex = (reg & BMCR_FULLDPLX) ? 1 : 0;
582 + }
583 +
584 + printk(KERN_INFO "%s: Configuring MAC for %s duplex\n",
585 + dev->name, (duplex) ? "full" : "half");
586 +
587 + if (duplex) {
588 + /* full duplex */
589 + sp->eth_regs->mac_control =
590 + ((sp->eth_regs->
591 + mac_control | MAC_CONTROL_F) & ~MAC_CONTROL_DRO);
592 + } else {
593 + /* half duplex */
594 + sp->eth_regs->mac_control =
595 + ((sp->eth_regs->
596 + mac_control | MAC_CONTROL_DRO) & ~MAC_CONTROL_F);
597 + }
598 + } else {
599 + /* no link */
600 + sp->link = 0;
601 + }
602 + sp->phy_data = phy_data;
603 + }
604 +}
605 +
606 +static int ar231x_reset_reg(struct net_device *dev)
607 +{
608 + struct ar231x_private *sp = netdev_priv(dev);
609 + unsigned int ethsal, ethsah;
610 + unsigned int flags;
611 +
612 + *sp->int_regs |= sp->cfg->reset_mac;
613 + mdelay(10);
614 + *sp->int_regs &= ~sp->cfg->reset_mac;
615 + mdelay(10);
616 + *sp->int_regs |= sp->cfg->reset_phy;
617 + mdelay(10);
618 + *sp->int_regs &= ~sp->cfg->reset_phy;
619 + mdelay(10);
620 +
621 + sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR);
622 + mdelay(10);
623 + sp->dma_regs->bus_mode =
624 + ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE);
625 +
626 + /* enable interrupts */
627 + sp->dma_regs->intr_ena = (DMA_STATUS_AIS |
628 + DMA_STATUS_NIS |
629 + DMA_STATUS_RI |
630 + DMA_STATUS_TI | DMA_STATUS_FBE);
631 + sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring);
632 + sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring);
633 + sp->dma_regs->control =
634 + (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF);
635 +
636 + sp->eth_regs->flow_control = (FLOW_CONTROL_FCE);
637 + sp->eth_regs->vlan_tag = (0x8100);
638 +
639 + /* Enable Ethernet Interface */
640 + flags = (MAC_CONTROL_TE | /* transmit enable */
641 + MAC_CONTROL_PM | /* pass mcast */
642 + MAC_CONTROL_F | /* full duplex */
643 + MAC_CONTROL_HBD); /* heart beat disabled */
644 +
645 + if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
646 + flags |= MAC_CONTROL_PR;
647 + }
648 + sp->eth_regs->mac_control = flags;
649 +
650 + /* Set all Ethernet station address registers to their initial values */
651 + ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
652 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF));
653 +
654 + ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
655 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
656 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
657 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF));
658 +
659 + sp->eth_regs->mac_addr[0] = ethsah;
660 + sp->eth_regs->mac_addr[1] = ethsal;
661 +
662 + mdelay(10);
663 +
664 + return 0;
665 +}
666 +
667 +
668 +static int ar231x_init(struct net_device *dev)
669 +{
670 + struct ar231x_private *sp = netdev_priv(dev);
671 + int ecode = 0;
672 +
673 + /* Allocate descriptors */
674 + if (ar231x_allocate_descriptors(dev)) {
675 + printk("%s: %s: ar231x_allocate_descriptors failed\n",
676 + dev->name, __FUNCTION__);
677 + ecode = -EAGAIN;
678 + goto init_error;
679 + }
680 +
681 + /* Get the memory for the skb rings */
682 + if (sp->rx_skb == NULL) {
683 + sp->rx_skb =
684 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
685 + GFP_KERNEL);
686 + if (!(sp->rx_skb)) {
687 + printk("%s: %s: rx_skb kmalloc failed\n",
688 + dev->name, __FUNCTION__);
689 + ecode = -EAGAIN;
690 + goto init_error;
691 + }
692 + }
693 + memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
694 +
695 + if (sp->tx_skb == NULL) {
696 + sp->tx_skb =
697 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
698 + GFP_KERNEL);
699 + if (!(sp->tx_skb)) {
700 + printk("%s: %s: tx_skb kmalloc failed\n",
701 + dev->name, __FUNCTION__);
702 + ecode = -EAGAIN;
703 + goto init_error;
704 + }
705 + }
706 + memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
707 +
708 + /**
709 + * Set tx_csm before we start receiving interrupts, otherwise
710 + * the interrupt handler might think it is supposed to process
711 + * tx ints before we are up and running, which may cause a null
712 + * pointer access in the int handler.
713 + */
714 + sp->rx_skbprd = 0;
715 + sp->cur_rx = 0;
716 + sp->tx_prd = 0;
717 + sp->tx_csm = 0;
718 +
719 + /* Zero the stats before starting the interface */
720 + memset(&dev->stats, 0, sizeof(dev->stats));
721 +
722 + /**
723 + * We load the ring here as there seem to be no way to tell the
724 + * firmware to wipe the ring without re-initializing it.
725 + */
726 + ar231x_load_rx_ring(dev, RX_RING_SIZE);
727 +
728 + /* Init hardware */
729 + ar231x_reset_reg(dev);
730 +
731 + /* Get the IRQ */
732 + ecode =
733 + request_irq(dev->irq, &ar231x_interrupt,
734 + IRQF_DISABLED,
735 + dev->name, dev);
736 + if (ecode) {
737 + printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n",
738 + dev->name, __FUNCTION__, dev->irq);
739 + goto init_error;
740 + }
741 +
742 +
743 + tasklet_enable(&sp->rx_tasklet);
744 +
745 + return 0;
746 +
747 +init_error:
748 + ar231x_init_cleanup(dev);
749 + return ecode;
750 +}
751 +
752 +/**
753 + * Load the rx ring.
754 + *
755 + * Loading rings is safe without holding the spin lock since this is
756 + * done only before the device is enabled, thus no interrupts are
757 + * generated and by the interrupt handler/tasklet handler.
758 + */
759 +static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs)
760 +{
761 + struct ar231x_private *sp = netdev_priv(dev);
762 + short i, idx;
763 +
764 + idx = sp->rx_skbprd;
765 +
766 + for (i = 0; i < nr_bufs; i++) {
767 + struct sk_buff *skb;
768 + ar231x_descr_t *rd;
769 +
770 + if (sp->rx_skb[idx])
771 + break;
772 +
773 + skb = netdev_alloc_skb_ip_align(dev, AR2313_BUFSIZE);
774 + if (!skb) {
775 + printk("\n\n\n\n %s: No memory in system\n\n\n\n",
776 + __FUNCTION__);
777 + break;
778 + }
779 +
780 + /* Make sure IP header starts on a fresh cache line */
781 + skb->dev = dev;
782 + sp->rx_skb[idx] = skb;
783 +
784 + rd = (ar231x_descr_t *) & sp->rx_ring[idx];
785 +
786 + /* initialize dma descriptor */
787 + rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
788 + DMA_RX1_CHAINED);
789 + rd->addr = virt_to_phys(skb->data);
790 + rd->descr =
791 + virt_to_phys(&sp->
792 + rx_ring[(idx + 1) & (AR2313_DESCR_ENTRIES - 1)]);
793 + rd->status = DMA_RX_OWN;
794 +
795 + idx = DSC_NEXT(idx);
796 + }
797 +
798 + if (i)
799 + sp->rx_skbprd = idx;
800 +
801 + return;
802 +}
803 +
804 +#define AR2313_MAX_PKTS_PER_CALL 64
805 +
806 +static int ar231x_rx_int(struct net_device *dev)
807 +{
808 + struct ar231x_private *sp = netdev_priv(dev);
809 + struct sk_buff *skb, *skb_new;
810 + ar231x_descr_t *rxdesc;
811 + unsigned int status;
812 + u32 idx;
813 + int pkts = 0;
814 + int rval;
815 +
816 + idx = sp->cur_rx;
817 +
818 + /* process at most the entire ring and then wait for another int */
819 + while (1) {
820 + rxdesc = &sp->rx_ring[idx];
821 + status = rxdesc->status;
822 +
823 + if (status & DMA_RX_OWN) {
824 + /* SiByte owns descriptor or descr not yet filled in */
825 + rval = 0;
826 + break;
827 + }
828 +
829 + if (++pkts > AR2313_MAX_PKTS_PER_CALL) {
830 + rval = 1;
831 + break;
832 + }
833 +
834 + if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) {
835 + dev->stats.rx_errors++;
836 + dev->stats.rx_dropped++;
837 +
838 + /* add statistics counters */
839 + if (status & DMA_RX_ERR_CRC)
840 + dev->stats.rx_crc_errors++;
841 + if (status & DMA_RX_ERR_COL)
842 + dev->stats.rx_over_errors++;
843 + if (status & DMA_RX_ERR_LENGTH)
844 + dev->stats.rx_length_errors++;
845 + if (status & DMA_RX_ERR_RUNT)
846 + dev->stats.rx_over_errors++;
847 + if (status & DMA_RX_ERR_DESC)
848 + dev->stats.rx_over_errors++;
849 +
850 + } else {
851 + /* alloc new buffer. */
852 + skb_new = netdev_alloc_skb_ip_align(dev, AR2313_BUFSIZE);
853 + if (skb_new != NULL) {
854 + skb = sp->rx_skb[idx];
855 + /* set skb */
856 + skb_put(skb,
857 + ((status >> DMA_RX_LEN_SHIFT) & 0x3fff) - CRC_LEN);
858 +
859 + dev->stats.rx_bytes += skb->len;
860 + skb->protocol = eth_type_trans(skb, dev);
861 + /* pass the packet to upper layers */
862 + netif_rx(skb);
863 +
864 + skb_new->dev = dev;
865 + /* reset descriptor's curr_addr */
866 + rxdesc->addr = virt_to_phys(skb_new->data);
867 +
868 + dev->stats.rx_packets++;
869 + sp->rx_skb[idx] = skb_new;
870 + } else {
871 + dev->stats.rx_dropped++;
872 + }
873 + }
874 +
875 + rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
876 + DMA_RX1_CHAINED);
877 + rxdesc->status = DMA_RX_OWN;
878 +
879 + idx = DSC_NEXT(idx);
880 + }
881 +
882 + sp->cur_rx = idx;
883 +
884 + return rval;
885 +}
886 +
887 +
888 +static void ar231x_tx_int(struct net_device *dev)
889 +{
890 + struct ar231x_private *sp = netdev_priv(dev);
891 + u32 idx;
892 + struct sk_buff *skb;
893 + ar231x_descr_t *txdesc;
894 + unsigned int status = 0;
895 +
896 + idx = sp->tx_csm;
897 +
898 + while (idx != sp->tx_prd) {
899 + txdesc = &sp->tx_ring[idx];
900 + status = txdesc->status;
901 +
902 + if (status & DMA_TX_OWN) {
903 + /* ar231x dma still owns descr */
904 + break;
905 + }
906 + /* done with this descriptor */
907 + dma_unmap_single(NULL, txdesc->addr,
908 + txdesc->devcs & DMA_TX1_BSIZE_MASK,
909 + DMA_TO_DEVICE);
910 + txdesc->status = 0;
911 +
912 + if (status & DMA_TX_ERROR) {
913 + dev->stats.tx_errors++;
914 + dev->stats.tx_dropped++;
915 + if (status & DMA_TX_ERR_UNDER)
916 + dev->stats.tx_fifo_errors++;
917 + if (status & DMA_TX_ERR_HB)
918 + dev->stats.tx_heartbeat_errors++;
919 + if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK))
920 + dev->stats.tx_carrier_errors++;
921 + if (status & (DMA_TX_ERR_LATE |
922 + DMA_TX_ERR_COL |
923 + DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER))
924 + dev->stats.tx_aborted_errors++;
925 + } else {
926 + /* transmit OK */
927 + dev->stats.tx_packets++;
928 + }
929 +
930 + skb = sp->tx_skb[idx];
931 + sp->tx_skb[idx] = NULL;
932 + idx = DSC_NEXT(idx);
933 + dev->stats.tx_bytes += skb->len;
934 + dev_kfree_skb_irq(skb);
935 + }
936 +
937 + sp->tx_csm = idx;
938 +
939 + return;
940 +}
941 +
942 +
943 +static void rx_tasklet_func(unsigned long data)
944 +{
945 + struct net_device *dev = (struct net_device *) data;
946 + struct ar231x_private *sp = netdev_priv(dev);
947 +
948 + if (sp->unloading)
949 + return;
950 +
951 + if (ar231x_rx_int(dev)) {
952 + tasklet_hi_schedule(&sp->rx_tasklet);
953 + } else {
954 + unsigned long flags;
955 + spin_lock_irqsave(&sp->lock, flags);
956 + sp->dma_regs->intr_ena |= DMA_STATUS_RI;
957 + spin_unlock_irqrestore(&sp->lock, flags);
958 + }
959 +}
960 +
961 +static void rx_schedule(struct net_device *dev)
962 +{
963 + struct ar231x_private *sp = netdev_priv(dev);
964 +
965 + sp->dma_regs->intr_ena &= ~DMA_STATUS_RI;
966 +
967 + tasklet_hi_schedule(&sp->rx_tasklet);
968 +}
969 +
970 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id)
971 +{
972 + struct net_device *dev = (struct net_device *) dev_id;
973 + struct ar231x_private *sp = netdev_priv(dev);
974 + unsigned int status, enabled;
975 +
976 + /* clear interrupt */
977 + /* Don't clear RI bit if currently disabled */
978 + status = sp->dma_regs->status;
979 + enabled = sp->dma_regs->intr_ena;
980 + sp->dma_regs->status = status & enabled;
981 +
982 + if (status & DMA_STATUS_NIS) {
983 + /* normal status */
984 + /**
985 + * Don't schedule rx processing if interrupt
986 + * is already disabled.
987 + */
988 + if (status & enabled & DMA_STATUS_RI) {
989 + /* receive interrupt */
990 + rx_schedule(dev);
991 + }
992 + if (status & DMA_STATUS_TI) {
993 + /* transmit interrupt */
994 + ar231x_tx_int(dev);
995 + }
996 + }
997 +
998 + /* abnormal status */
999 + if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS))
1000 + ar231x_restart(dev);
1001 +
1002 + return IRQ_HANDLED;
1003 +}
1004 +
1005 +
1006 +static int ar231x_open(struct net_device *dev)
1007 +{
1008 + struct ar231x_private *sp = netdev_priv(dev);
1009 + unsigned int ethsal, ethsah;
1010 +
1011 + /* reset the hardware, in case the MAC address changed */
1012 + ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
1013 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF));
1014 +
1015 + ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
1016 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
1017 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
1018 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF));
1019 +
1020 + sp->eth_regs->mac_addr[0] = ethsah;
1021 + sp->eth_regs->mac_addr[1] = ethsal;
1022 +
1023 + mdelay(10);
1024 +
1025 + dev->mtu = 1500;
1026 + netif_start_queue(dev);
1027 +
1028 + sp->eth_regs->mac_control |= MAC_CONTROL_RE;
1029 +
1030 + return 0;
1031 +}
1032 +
1033 +static void ar231x_tx_timeout(struct net_device *dev)
1034 +{
1035 + struct ar231x_private *sp = netdev_priv(dev);
1036 + unsigned long flags;
1037 +
1038 + spin_lock_irqsave(&sp->lock, flags);
1039 + ar231x_restart(dev);
1040 + spin_unlock_irqrestore(&sp->lock, flags);
1041 +}
1042 +
1043 +static void ar231x_halt(struct net_device *dev)
1044 +{
1045 + struct ar231x_private *sp = netdev_priv(dev);
1046 + int j;
1047 +
1048 + tasklet_disable(&sp->rx_tasklet);
1049 +
1050 + /* kill the MAC */
1051 + sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */
1052 + MAC_CONTROL_TE); /* disable Transmits */
1053 + /* stop dma */
1054 + sp->dma_regs->control = 0;
1055 + sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR;
1056 +
1057 + /* place phy and MAC in reset */
1058 + *sp->int_regs |= (sp->cfg->reset_mac | sp->cfg->reset_phy);
1059 +
1060 + /* free buffers on tx ring */
1061 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
1062 + struct sk_buff *skb;
1063 + ar231x_descr_t *txdesc;
1064 +
1065 + txdesc = &sp->tx_ring[j];
1066 + txdesc->descr = 0;
1067 +
1068 + skb = sp->tx_skb[j];
1069 + if (skb) {
1070 + dev_kfree_skb(skb);
1071 + sp->tx_skb[j] = NULL;
1072 + }
1073 + }
1074 +}
1075 +
1076 +/**
1077 + * close should do nothing. Here's why. It's called when
1078 + * 'ifconfig bond0 down' is run. If it calls free_irq then
1079 + * the irq is gone forever ! When bond0 is made 'up' again,
1080 + * the ar231x_open () does not call request_irq (). Worse,
1081 + * the call to ar231x_halt() generates a WDOG reset due to
1082 + * the write to 'sp->int_regs' and the box reboots.
1083 + * Commenting this out is good since it allows the
1084 + * system to resume when bond0 is made up again.
1085 + */
1086 +static int ar231x_close(struct net_device *dev)
1087 +{
1088 +#if 0
1089 + /* Disable interrupts */
1090 + disable_irq(dev->irq);
1091 +
1092 + /**
1093 + * Without (or before) releasing irq and stopping hardware, this
1094 + * is an absolute non-sense, by the way. It will be reset instantly
1095 + * by the first irq.
1096 + */
1097 + netif_stop_queue(dev);
1098 +
1099 + /* stop the MAC and DMA engines */
1100 + ar231x_halt(dev);
1101 +
1102 + /* release the interrupt */
1103 + free_irq(dev->irq, dev);
1104 +
1105 +#endif
1106 + return 0;
1107 +}
1108 +
1109 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev)
1110 +{
1111 + struct ar231x_private *sp = netdev_priv(dev);
1112 + ar231x_descr_t *td;
1113 + u32 idx;
1114 +
1115 + idx = sp->tx_prd;
1116 + td = &sp->tx_ring[idx];
1117 +
1118 + if (td->status & DMA_TX_OWN) {
1119 + /* free skbuf and lie to the caller that we sent it out */
1120 + dev->stats.tx_dropped++;
1121 + dev_kfree_skb(skb);
1122 +
1123 + /* restart transmitter in case locked */
1124 + sp->dma_regs->xmt_poll = 0;
1125 + return 0;
1126 + }
1127 +
1128 + /* Setup the transmit descriptor. */
1129 + td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) |
1130 + (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED));
1131 + td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
1132 + td->status = DMA_TX_OWN;
1133 +
1134 + /* kick transmitter last */
1135 + sp->dma_regs->xmt_poll = 0;
1136 +
1137 + sp->tx_skb[idx] = skb;
1138 + idx = DSC_NEXT(idx);
1139 + sp->tx_prd = idx;
1140 +
1141 + return 0;
1142 +}
1143 +
1144 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1145 +{
1146 + struct ar231x_private *sp = netdev_priv(dev);
1147 + int ret;
1148 +
1149 + switch (cmd) {
1150 + case SIOCETHTOOL:
1151 + spin_lock_irq(&sp->lock);
1152 + ret = phy_ethtool_ioctl(sp->phy_dev, (void *) ifr->ifr_data);
1153 + spin_unlock_irq(&sp->lock);
1154 + return ret;
1155 +
1156 + case SIOCSIFHWADDR:
1157 + if (copy_from_user
1158 + (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
1159 + return -EFAULT;
1160 + return 0;
1161 +
1162 + case SIOCGIFHWADDR:
1163 + if (copy_to_user
1164 + (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
1165 + return -EFAULT;
1166 + return 0;
1167 +
1168 + case SIOCGMIIPHY:
1169 + case SIOCGMIIREG:
1170 + case SIOCSMIIREG:
1171 + return phy_mii_ioctl(sp->phy_dev, ifr, cmd);
1172 +
1173 + default:
1174 + break;
1175 + }
1176 +
1177 + return -EOPNOTSUPP;
1178 +}
1179 +
1180 +static void ar231x_adjust_link(struct net_device *dev)
1181 +{
1182 + struct ar231x_private *sp = netdev_priv(dev);
1183 + unsigned int mc;
1184 +
1185 + if (!sp->phy_dev->link)
1186 + return;
1187 +
1188 + if (sp->phy_dev->duplex != sp->oldduplex) {
1189 + mc = readl(&sp->eth_regs->mac_control);
1190 + mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO);
1191 + if (sp->phy_dev->duplex)
1192 + mc |= MAC_CONTROL_F;
1193 + else
1194 + mc |= MAC_CONTROL_DRO;
1195 + writel(mc, &sp->eth_regs->mac_control);
1196 + sp->oldduplex = sp->phy_dev->duplex;
1197 + }
1198 +}
1199 +
1200 +#define MII_ADDR(phy, reg) \
1201 + ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT))
1202 +
1203 +static int
1204 +ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1205 +{
1206 + struct net_device *const dev = bus->priv;
1207 + struct ar231x_private *sp = netdev_priv(dev);
1208 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1209 +
1210 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum);
1211 + while (ethernet->mii_addr & MII_ADDR_BUSY);
1212 + return ethernet->mii_data >> MII_DATA_SHIFT;
1213 +}
1214 +
1215 +static int
1216 +ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value)
1217 +{
1218 + struct net_device *const dev = bus->priv;
1219 + struct ar231x_private *sp = netdev_priv(dev);
1220 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1221 +
1222 + while (ethernet->mii_addr & MII_ADDR_BUSY);
1223 + ethernet->mii_data = value << MII_DATA_SHIFT;
1224 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE;
1225 +
1226 + return 0;
1227 +}
1228 +
1229 +static int ar231x_mdiobus_reset(struct mii_bus *bus)
1230 +{
1231 + struct net_device *const dev = bus->priv;
1232 +
1233 + ar231x_reset_reg(dev);
1234 +
1235 + return 0;
1236 +}
1237 +
1238 +static int ar231x_mdiobus_probe (struct net_device *dev)
1239 +{
1240 + struct ar231x_private *const sp = netdev_priv(dev);
1241 + struct phy_device *phydev = NULL;
1242 + int phy_addr;
1243 +
1244 + /* find the first (lowest address) PHY on the current MAC's MII bus */
1245 + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
1246 + if (sp->mii_bus->phy_map[phy_addr]) {
1247 + phydev = sp->mii_bus->phy_map[phy_addr];
1248 + sp->phy = phy_addr;
1249 + break; /* break out with first one found */
1250 + }
1251 +
1252 + if (!phydev) {
1253 + printk (KERN_ERR "ar231x: %s: no PHY found\n", dev->name);
1254 + return -1;
1255 + }
1256 +
1257 + /* now we are supposed to have a proper phydev, to attach to... */
1258 + BUG_ON(!phydev);
1259 + BUG_ON(phydev->attached_dev);
1260 +
1261 + phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link, 0,
1262 + PHY_INTERFACE_MODE_MII);
1263 +
1264 + if (IS_ERR(phydev)) {
1265 + printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
1266 + return PTR_ERR(phydev);
1267 + }
1268 +
1269 + /* mask with MAC supported features */
1270 + phydev->supported &= (SUPPORTED_10baseT_Half
1271 + | SUPPORTED_10baseT_Full
1272 + | SUPPORTED_100baseT_Half
1273 + | SUPPORTED_100baseT_Full
1274 + | SUPPORTED_Autoneg
1275 + /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
1276 + | SUPPORTED_MII
1277 + | SUPPORTED_TP);
1278 +
1279 + phydev->advertising = phydev->supported;
1280 +
1281 + sp->oldduplex = -1;
1282 + sp->phy_dev = phydev;
1283 +
1284 + printk(KERN_INFO "%s: attached PHY driver [%s] "
1285 + "(mii_bus:phy_addr=%s)\n",
1286 + dev->name, phydev->drv->name, dev_name(&phydev->dev));
1287 +
1288 + return 0;
1289 +}
1290 +
1291 --- /dev/null
1292 +++ b/drivers/net/ethernet/ar231x/ar231x.h
1293 @@ -0,0 +1,288 @@
1294 +/*
1295 + * ar231x.h: Linux driver for the Atheros AR231x Ethernet device.
1296 + *
1297 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
1298 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1299 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1300 + *
1301 + * Thanks to Atheros for providing hardware and documentation
1302 + * enabling me to write this driver.
1303 + *
1304 + * This program is free software; you can redistribute it and/or modify
1305 + * it under the terms of the GNU General Public License as published by
1306 + * the Free Software Foundation; either version 2 of the License, or
1307 + * (at your option) any later version.
1308 + */
1309 +
1310 +#ifndef _AR2313_H_
1311 +#define _AR2313_H_
1312 +
1313 +#include <linux/interrupt.h>
1314 +#include <generated/autoconf.h>
1315 +#include <linux/bitops.h>
1316 +#include <ar231x_platform.h>
1317 +
1318 +/* probe link timer - 5 secs */
1319 +#define LINK_TIMER (5*HZ)
1320 +
1321 +#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
1322 +#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
1323 +#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0)
1324 +
1325 +#define AR2313_TX_TIMEOUT (HZ/4)
1326 +
1327 +/* Rings */
1328 +#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc))
1329 +#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))
1330 +
1331 +#define AR2313_MBGET 2
1332 +#define AR2313_MBSET 3
1333 +#define AR2313_PCI_RECONFIG 4
1334 +#define AR2313_PCI_DUMP 5
1335 +#define AR2313_TEST_PANIC 6
1336 +#define AR2313_TEST_NULLPTR 7
1337 +#define AR2313_READ_DATA 8
1338 +#define AR2313_WRITE_DATA 9
1339 +#define AR2313_GET_VERSION 10
1340 +#define AR2313_TEST_HANG 11
1341 +#define AR2313_SYNC 12
1342 +
1343 +#define DMA_RX_ERR_CRC BIT(1)
1344 +#define DMA_RX_ERR_DRIB BIT(2)
1345 +#define DMA_RX_ERR_MII BIT(3)
1346 +#define DMA_RX_EV2 BIT(5)
1347 +#define DMA_RX_ERR_COL BIT(6)
1348 +#define DMA_RX_LONG BIT(7)
1349 +#define DMA_RX_LS BIT(8) /* last descriptor */
1350 +#define DMA_RX_FS BIT(9) /* first descriptor */
1351 +#define DMA_RX_MF BIT(10) /* multicast frame */
1352 +#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */
1353 +#define DMA_RX_ERR_LENGTH BIT(12) /* length error */
1354 +#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */
1355 +#define DMA_RX_ERROR BIT(15) /* error summary */
1356 +#define DMA_RX_LEN_MASK 0x3fff0000
1357 +#define DMA_RX_LEN_SHIFT 16
1358 +#define DMA_RX_FILT BIT(30)
1359 +#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */
1360 +
1361 +#define DMA_RX1_BSIZE_MASK 0x000007ff
1362 +#define DMA_RX1_BSIZE_SHIFT 0
1363 +#define DMA_RX1_CHAINED BIT(24)
1364 +#define DMA_RX1_RER BIT(25)
1365 +
1366 +#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */
1367 +#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */
1368 +#define DMA_TX_COL_MASK 0x78
1369 +#define DMA_TX_COL_SHIFT 3
1370 +#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */
1371 +#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */
1372 +#define DMA_TX_ERR_LATE BIT(9) /* late collision */
1373 +#define DMA_TX_ERR_LINK BIT(10) /* no carrier */
1374 +#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */
1375 +#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */
1376 +#define DMA_TX_ERROR BIT(15) /* frame aborted */
1377 +#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */
1378 +
1379 +#define DMA_TX1_BSIZE_MASK 0x000007ff
1380 +#define DMA_TX1_BSIZE_SHIFT 0
1381 +#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */
1382 +#define DMA_TX1_TER BIT(25) /* transmit end of ring */
1383 +#define DMA_TX1_FS BIT(29) /* first segment */
1384 +#define DMA_TX1_LS BIT(30) /* last segment */
1385 +#define DMA_TX1_IC BIT(31) /* interrupt on completion */
1386 +
1387 +#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
1388 +
1389 +#define MAC_CONTROL_RE BIT(2) /* receive enable */
1390 +#define MAC_CONTROL_TE BIT(3) /* transmit enable */
1391 +#define MAC_CONTROL_DC BIT(5) /* Deferral check */
1392 +#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */
1393 +#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */
1394 +#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */
1395 +#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */
1396 +#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */
1397 +#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */
1398 +#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */
1399 +#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */
1400 +#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */
1401 +#define MAC_CONTROL_PR BIT(18) /* promiscuous mode (valid frames only) */
1402 +#define MAC_CONTROL_PM BIT(19) /* pass multicast */
1403 +#define MAC_CONTROL_F BIT(20) /* full-duplex */
1404 +#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */
1405 +#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */
1406 +#define MAC_CONTROL_BLE BIT(30) /* big endian mode */
1407 +#define MAC_CONTROL_RA BIT(31) /* receive all (valid and invalid frames) */
1408 +
1409 +#define MII_ADDR_BUSY BIT(0)
1410 +#define MII_ADDR_WRITE BIT(1)
1411 +#define MII_ADDR_REG_SHIFT 6
1412 +#define MII_ADDR_PHY_SHIFT 11
1413 +#define MII_DATA_SHIFT 0
1414 +
1415 +#define FLOW_CONTROL_FCE BIT(1)
1416 +
1417 +#define DMA_BUS_MODE_SWR BIT(0) /* software reset */
1418 +#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */
1419 +#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
1420 +#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */
1421 +
1422 +#define DMA_STATUS_TI BIT(0) /* transmit interrupt */
1423 +#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */
1424 +#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */
1425 +#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */
1426 +#define DMA_STATUS_UNF BIT(5) /* transmit underflow */
1427 +#define DMA_STATUS_RI BIT(6) /* receive interrupt */
1428 +#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */
1429 +#define DMA_STATUS_RPS BIT(8) /* receive process stopped */
1430 +#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */
1431 +#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */
1432 +#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */
1433 +#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */
1434 +#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */
1435 +#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
1436 +#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
1437 +#define DMA_STATUS_EB_SHIFT 23 /* error bits */
1438 +
1439 +#define DMA_CONTROL_SR BIT(1) /* start receive */
1440 +#define DMA_CONTROL_ST BIT(13) /* start transmit */
1441 +#define DMA_CONTROL_SF BIT(21) /* store and forward */
1442 +
1443 +
1444 +typedef struct {
1445 + volatile unsigned int status; /* OWN, Device control and status. */
1446 + volatile unsigned int devcs; /* pkt Control bits + Length */
1447 + volatile unsigned int addr; /* Current Address. */
1448 + volatile unsigned int descr; /* Next descriptor in chain. */
1449 +} ar231x_descr_t;
1450 +
1451 +
1452 +
1453 +/**
1454 + * New Combo structure for Both Eth0 AND eth1
1455 + */
1456 +typedef struct {
1457 + volatile unsigned int mac_control; /* 0x00 */
1458 + volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */
1459 + volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
1460 + volatile unsigned int mii_addr; /* 0x14 */
1461 + volatile unsigned int mii_data; /* 0x18 */
1462 + volatile unsigned int flow_control; /* 0x1c */
1463 + volatile unsigned int vlan_tag; /* 0x20 */
1464 + volatile unsigned int pad[7]; /* 0x24 - 0x3c */
1465 + volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
1466 +
1467 +} ETHERNET_STRUCT;
1468 +
1469 +/********************************************************************
1470 + * Interrupt controller
1471 + ********************************************************************/
1472 +
1473 +typedef struct {
1474 + volatile unsigned int wdog_control; /* 0x08 */
1475 + volatile unsigned int wdog_timer; /* 0x0c */
1476 + volatile unsigned int misc_status; /* 0x10 */
1477 + volatile unsigned int misc_mask; /* 0x14 */
1478 + volatile unsigned int global_status; /* 0x18 */
1479 + volatile unsigned int reserved; /* 0x1c */
1480 + volatile unsigned int reset_control; /* 0x20 */
1481 +} INTERRUPT;
1482 +
1483 +/********************************************************************
1484 + * DMA controller
1485 + ********************************************************************/
1486 +typedef struct {
1487 + volatile unsigned int bus_mode; /* 0x00 (CSR0) */
1488 + volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
1489 + volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
1490 + volatile unsigned int rcv_base; /* 0x0c (CSR3) */
1491 + volatile unsigned int xmt_base; /* 0x10 (CSR4) */
1492 + volatile unsigned int status; /* 0x14 (CSR5) */
1493 + volatile unsigned int control; /* 0x18 (CSR6) */
1494 + volatile unsigned int intr_ena; /* 0x1c (CSR7) */
1495 + volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
1496 + volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
1497 + volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
1498 + volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
1499 +} DMA;
1500 +
1501 +/**
1502 + * Struct private for the Sibyte.
1503 + *
1504 + * Elements are grouped so variables used by the tx handling goes
1505 + * together, and will go into the same cache lines etc. in order to
1506 + * avoid cache line contention between the rx and tx handling on SMP.
1507 + *
1508 + * Frequently accessed variables are put at the beginning of the
1509 + * struct to help the compiler generate better/shorter code.
1510 + */
1511 +struct ar231x_private {
1512 + struct net_device *dev;
1513 + int version;
1514 + u32 mb[2];
1515 +
1516 + volatile ETHERNET_STRUCT *phy_regs;
1517 + volatile ETHERNET_STRUCT *eth_regs;
1518 + volatile DMA *dma_regs;
1519 + volatile u32 *int_regs;
1520 + struct ar231x_eth *cfg;
1521 +
1522 + spinlock_t lock; /* Serialise access to device */
1523 +
1524 + /* RX and TX descriptors, must be adjacent */
1525 + ar231x_descr_t *rx_ring;
1526 + ar231x_descr_t *tx_ring;
1527 +
1528 +
1529 + struct sk_buff **rx_skb;
1530 + struct sk_buff **tx_skb;
1531 +
1532 + /* RX elements */
1533 + u32 rx_skbprd;
1534 + u32 cur_rx;
1535 +
1536 + /* TX elements */
1537 + u32 tx_prd;
1538 + u32 tx_csm;
1539 +
1540 + /* Misc elements */
1541 + char name[48];
1542 + struct {
1543 + u32 address;
1544 + u32 length;
1545 + char *mapping;
1546 + } desc;
1547 +
1548 +
1549 + struct timer_list link_timer;
1550 + unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
1551 + unsigned short mac;
1552 + unsigned short link; /* 0 - link down, 1 - link up */
1553 + u16 phy_data;
1554 +
1555 + struct tasklet_struct rx_tasklet;
1556 + int unloading;
1557 +
1558 + struct phy_device *phy_dev;
1559 + struct mii_bus *mii_bus;
1560 + int oldduplex;
1561 +};
1562 +
1563 +
1564 +/* Prototypes */
1565 +static int ar231x_init(struct net_device *dev);
1566 +#ifdef TX_TIMEOUT
1567 +static void ar231x_tx_timeout(struct net_device *dev);
1568 +#endif
1569 +static int ar231x_restart(struct net_device *dev);
1570 +static void ar231x_load_rx_ring(struct net_device *dev, int bufs);
1571 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id);
1572 +static int ar231x_open(struct net_device *dev);
1573 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev);
1574 +static int ar231x_close(struct net_device *dev);
1575 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr,
1576 + int cmd);
1577 +static void ar231x_init_cleanup(struct net_device *dev);
1578 +static int ar231x_setup_timer(struct net_device *dev);
1579 +static void ar231x_link_timer_fn(unsigned long data);
1580 +static void ar231x_check_link(struct net_device *dev);
1581 +#endif /* _AR2313_H_ */
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