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atheros: v3.18: remap flash for boardconfig parsing
[openwrt/staging/mkresin.git] / target / linux / atheros / patches-3.18 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -96,6 +96,19 @@ config AR7
4 Support for the Texas Instruments AR7 System-on-a-Chip
5 family: TNETD7100, 7200 and 7300.
6
7 +config ATH25
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config ATH79
21 bool "Atheros AR71XX/AR724X/AR913X based boards"
22 select ARCH_REQUIRE_GPIOLIB
23 @@ -834,6 +847,7 @@ config MIPS_PARAVIRT
24
25 endchoice
26
27 +source "arch/mips/ath25/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -2,6 +2,7 @@
34
35 platforms += alchemy
36 platforms += ar7
37 +platforms += ath25
38 platforms += ath79
39 platforms += bcm47xx
40 platforms += bcm63xx
41 --- /dev/null
42 +++ b/arch/mips/ath25/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR531X/AR231X WiSoC
46 +#
47 +platform-$(CONFIG_ATH25) += ath25/
48 +cflags-$(CONFIG_ATH25) += -I$(srctree)/arch/mips/include/asm/mach-ath25
49 +load-$(CONFIG_ATH25) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ath25/Kconfig
52 @@ -0,0 +1,9 @@
53 +config SOC_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATH25
56 + default y
57 +
58 +config SOC_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATH25
61 + default y
62 --- /dev/null
63 +++ b/arch/mips/ath25/Makefile
64 @@ -0,0 +1,13 @@
65 +#
66 +# This file is subject to the terms and conditions of the GNU General Public
67 +# License. See the file "COPYING" in the main directory of this archive
68 +# for more details.
69 +#
70 +# Copyright (C) 2006 FON Technology, SL.
71 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
72 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
73 +#
74 +
75 +obj-y += board.o prom.o devices.o
76 +obj-$(CONFIG_SOC_AR5312) += ar5312.o
77 +obj-$(CONFIG_SOC_AR2315) += ar2315.o
78 --- /dev/null
79 +++ b/arch/mips/ath25/board.c
80 @@ -0,0 +1,244 @@
81 +/*
82 + * This file is subject to the terms and conditions of the GNU General Public
83 + * License. See the file "COPYING" in the main directory of this archive
84 + * for more details.
85 + *
86 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
87 + * Copyright (C) 2006 FON Technology, SL.
88 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
89 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
90 + */
91 +
92 +#include <generated/autoconf.h>
93 +#include <linux/init.h>
94 +#include <linux/module.h>
95 +#include <linux/types.h>
96 +#include <linux/string.h>
97 +#include <linux/platform_device.h>
98 +#include <linux/kernel.h>
99 +#include <linux/random.h>
100 +#include <linux/etherdevice.h>
101 +#include <linux/irq.h>
102 +#include <linux/io.h>
103 +#include <asm/irq_cpu.h>
104 +#include <asm/reboot.h>
105 +#include <asm/bootinfo.h>
106 +#include <asm/time.h>
107 +
108 +#include <ath25_platform.h>
109 +#include "devices.h"
110 +#include "ar5312.h"
111 +#include "ar2315.h"
112 +
113 +void (*ath25_irq_dispatch)(void);
114 +
115 +static inline bool check_radio_magic(const void __iomem *addr)
116 +{
117 + addr += 0x7a; /* offset for flash magic */
118 + return (__raw_readb(addr) == 0x5a) && (__raw_readb(addr + 1) == 0xa5);
119 +}
120 +
121 +static inline bool check_notempty(const void __iomem *addr)
122 +{
123 + return __raw_readl(addr) != 0xffffffff;
124 +}
125 +
126 +static inline bool check_board_data(const void __iomem *addr, bool broken)
127 +{
128 + /* config magic found */
129 + if (__raw_readl(addr) == ATH25_BD_MAGIC)
130 + return true;
131 +
132 + if (!broken)
133 + return false;
134 +
135 + /* broken board data detected, use radio data to find the
136 + * offset, user will fix this */
137 +
138 + if (check_radio_magic(addr + 0x1000))
139 + return true;
140 + if (check_radio_magic(addr + 0xf8))
141 + return true;
142 +
143 + return false;
144 +}
145 +
146 +static const void __iomem * __init find_board_config(const void __iomem *limit,
147 + const bool broken)
148 +{
149 + const void __iomem *addr;
150 + const void __iomem *begin = limit - 0x1000;
151 + const void __iomem *end = limit - 0x30000;
152 +
153 + for (addr = begin; addr >= end; addr -= 0x1000)
154 + if (check_board_data(addr, broken))
155 + return addr;
156 +
157 + return NULL;
158 +}
159 +
160 +static const void __iomem * __init find_radio_config(const void __iomem *limit,
161 + const void __iomem *bcfg)
162 +{
163 + const void __iomem *rcfg, *begin, *end;
164 +
165 + /*
166 + * Now find the start of Radio Configuration data, using heuristics:
167 + * Search forward from Board Configuration data by 0x1000 bytes
168 + * at a time until we find non-0xffffffff.
169 + */
170 + begin = bcfg + 0x1000;
171 + end = limit;
172 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
173 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
174 + return rcfg;
175 +
176 + /* AR2316 relocates radio config to new location */
177 + begin = bcfg + 0xf8;
178 + end = limit - 0x1000 + 0xf8;
179 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
180 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
181 + return rcfg;
182 +
183 + return NULL;
184 +}
185 +
186 +/*
187 + * NB: Search region size could be larger than the actual flash size,
188 + * but this shouldn't be a problem here, because the flash
189 + * will simply be mapped multiple times.
190 + */
191 +int __init ath25_find_config(phys_addr_t base, unsigned long size)
192 +{
193 + const void __iomem *flash_base, *flash_limit;
194 + struct ath25_boarddata *config;
195 + unsigned int rcfg_size;
196 + int broken_boarddata = 0;
197 + const void __iomem *bcfg, *rcfg;
198 + u8 *board_data;
199 + u8 *radio_data;
200 + u8 *mac_addr;
201 + u32 offset;
202 +
203 + flash_base = ioremap_nocache(base, size);
204 + flash_limit = flash_base + size;
205 +
206 + ath25_board.config = NULL;
207 + ath25_board.radio = NULL;
208 +
209 + /* Copy the board and radio data to RAM, because accessing the mapped
210 + * memory of the flash directly after booting is not safe */
211 +
212 + /* Try to find valid board and radio data */
213 + bcfg = find_board_config(flash_limit, false);
214 +
215 + /* If that fails, try to at least find valid radio data */
216 + if (!bcfg) {
217 + bcfg = find_board_config(flash_limit, true);
218 + broken_boarddata = 1;
219 + }
220 +
221 + if (!bcfg) {
222 + pr_warn("WARNING: No board configuration data found!\n");
223 + goto error;
224 + }
225 +
226 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
227 + ath25_board.config = (struct ath25_boarddata *)board_data;
228 + memcpy_fromio(board_data, bcfg, 0x100);
229 + if (broken_boarddata) {
230 + pr_warn("WARNING: broken board data detected\n");
231 + config = ath25_board.config;
232 + if (is_zero_ether_addr(config->enet0_mac)) {
233 + pr_info("Fixing up empty mac addresses\n");
234 + config->reset_config_gpio = 0xffff;
235 + config->sys_led_gpio = 0xffff;
236 + random_ether_addr(config->wlan0_mac);
237 + config->wlan0_mac[0] &= ~0x06;
238 + random_ether_addr(config->enet0_mac);
239 + random_ether_addr(config->enet1_mac);
240 + }
241 + }
242 +
243 + /* Radio config starts 0x100 bytes after board config, regardless
244 + * of what the physical layout on the flash chip looks like */
245 +
246 + rcfg = find_radio_config(flash_limit, bcfg);
247 + if (!rcfg) {
248 + pr_warn("WARNING: Could not find Radio Configuration data\n");
249 + goto error;
250 + }
251 +
252 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
253 + ath25_board.radio = radio_data;
254 + offset = radio_data - board_data;
255 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
256 + offset);
257 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
258 + memcpy_fromio(radio_data, rcfg, rcfg_size);
259 +
260 + mac_addr = &radio_data[0x1d * 2];
261 + if (is_broadcast_ether_addr(mac_addr)) {
262 + pr_info("Radio MAC is blank; using board-data\n");
263 + ether_addr_copy(mac_addr, ath25_board.config->wlan0_mac);
264 + }
265 +
266 + iounmap(flash_base);
267 +
268 + return 0;
269 +
270 +error:
271 + iounmap(flash_base);
272 + return -ENODEV;
273 +}
274 +
275 +static void ath25_halt(void)
276 +{
277 + local_irq_disable();
278 + while (1)
279 + ;
280 +}
281 +
282 +void __init plat_mem_setup(void)
283 +{
284 + _machine_halt = ath25_halt;
285 + pm_power_off = ath25_halt;
286 +
287 + if (is_ar5312())
288 + ar5312_plat_mem_setup();
289 + else
290 + ar2315_plat_mem_setup();
291 +
292 + /* Disable data watchpoints */
293 + write_c0_watchlo0(0);
294 +}
295 +
296 +asmlinkage void plat_irq_dispatch(void)
297 +{
298 + ath25_irq_dispatch();
299 +}
300 +
301 +void __init plat_time_init(void)
302 +{
303 + if (is_ar5312())
304 + ar5312_plat_time_init();
305 + else
306 + ar2315_plat_time_init();
307 +}
308 +
309 +unsigned int __cpuinit get_c0_compare_int(void)
310 +{
311 + return CP0_LEGACY_COMPARE_IRQ;
312 +}
313 +
314 +void __init arch_init_irq(void)
315 +{
316 + clear_c0_status(ST0_IM);
317 + mips_cpu_irq_init();
318 +
319 + /* Initialize interrupt controllers */
320 + if (is_ar5312())
321 + ar5312_arch_init_irq();
322 + else
323 + ar2315_arch_init_irq();
324 +}
325 --- /dev/null
326 +++ b/arch/mips/ath25/prom.c
327 @@ -0,0 +1,26 @@
328 +/*
329 + * This file is subject to the terms and conditions of the GNU General Public
330 + * License. See the file "COPYING" in the main directory of this archive
331 + * for more details.
332 + *
333 + * Copyright MontaVista Software Inc
334 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
335 + * Copyright (C) 2006 FON Technology, SL.
336 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
337 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
338 + */
339 +
340 +/*
341 + * Prom setup file for ar231x
342 + */
343 +
344 +#include <linux/init.h>
345 +#include <asm/bootinfo.h>
346 +
347 +void __init prom_init(void)
348 +{
349 +}
350 +
351 +void __init prom_free_prom_memory(void)
352 +{
353 +}
354 --- /dev/null
355 +++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h
356 @@ -0,0 +1,84 @@
357 +#ifndef __ASM_MACH_ATH25_PLATFORM_H
358 +#define __ASM_MACH_ATH25_PLATFORM_H
359 +
360 +#include <linux/etherdevice.h>
361 +
362 +/*
363 + * This is board-specific data that is stored in a "fixed" location in flash.
364 + * It is shared across operating systems, so it should not be changed lightly.
365 + * The main reason we need it is in order to extract the ethernet MAC
366 + * address(es).
367 + */
368 +struct ath25_boarddata {
369 + u32 magic; /* board data is valid */
370 +#define ATH25_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
371 + u16 cksum; /* checksum (starting with BD_REV 2) */
372 + u16 rev; /* revision of this struct */
373 +#define BD_REV 4
374 + char board_name[64]; /* Name of board */
375 + u16 major; /* Board major number */
376 + u16 minor; /* Board minor number */
377 + u32 flags; /* Board configuration */
378 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
379 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
380 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
381 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
382 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
383 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
384 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
385 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
386 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
387 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
388 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
389 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
390 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
391 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
392 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
393 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
394 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
395 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
396 + u16 reset_config_gpio; /* Reset factory GPIO pin */
397 + u16 sys_led_gpio; /* System LED GPIO pin */
398 +
399 + u32 cpu_freq; /* CPU core frequency in Hz */
400 + u32 sys_freq; /* System frequency in Hz */
401 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
402 +
403 + u8 wlan0_mac[ETH_ALEN];
404 + u8 enet0_mac[ETH_ALEN];
405 + u8 enet1_mac[ETH_ALEN];
406 +
407 + u16 pci_id; /* Pseudo PCIID for common code */
408 + u16 mem_cap; /* cap bank1 in MB */
409 +
410 + /* version 3 */
411 + u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
412 +};
413 +
414 +#define BOARD_CONFIG_BUFSZ 0x1000
415 +
416 +/*
417 + * Platform device information for the Wireless MAC
418 + */
419 +struct ar231x_board_config {
420 + u16 devid;
421 +
422 + /* board config data */
423 + struct ath25_boarddata *config;
424 +
425 + /* radio calibration data */
426 + const char *radio;
427 +};
428 +
429 +/*
430 + * Platform device information for the Ethernet MAC
431 + */
432 +struct ar231x_eth {
433 + void (*reset_set)(u32);
434 + void (*reset_clear)(u32);
435 + u32 reset_mac;
436 + u32 reset_phy;
437 + char *macaddr;
438 +};
439 +
440 +#endif /* __ASM_MACH_ATH25_PLATFORM_H */
441 --- /dev/null
442 +++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
443 @@ -0,0 +1,64 @@
444 +/*
445 + * Atheros AR231x/AR531x SoC specific CPU feature overrides
446 + *
447 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
448 + *
449 + * This file was derived from: include/asm-mips/cpu-features.h
450 + * Copyright (C) 2003, 2004 Ralf Baechle
451 + * Copyright (C) 2004 Maciej W. Rozycki
452 + *
453 + * This program is free software; you can redistribute it and/or modify it
454 + * under the terms of the GNU General Public License version 2 as published
455 + * by the Free Software Foundation.
456 + *
457 + */
458 +#ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
459 +#define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
460 +
461 +/*
462 + * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
463 + */
464 +#define cpu_has_tlb 1
465 +#define cpu_has_4kex 1
466 +#define cpu_has_3k_cache 0
467 +#define cpu_has_4k_cache 1
468 +#define cpu_has_tx39_cache 0
469 +#define cpu_has_sb1_cache 0
470 +#define cpu_has_fpu 0
471 +#define cpu_has_32fpr 0
472 +#define cpu_has_counter 1
473 +#define cpu_has_ejtag 1
474 +
475 +#if !defined(CONFIG_SOC_AR5312)
476 +# define cpu_has_llsc 1
477 +#else
478 +/*
479 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
480 + * ll/sc instructions.
481 + */
482 +# define cpu_has_llsc 0
483 +#endif
484 +
485 +#define cpu_has_mips16 0
486 +#define cpu_has_mdmx 0
487 +#define cpu_has_mips3d 0
488 +#define cpu_has_smartmips 0
489 +
490 +#define cpu_has_mips32r1 1
491 +
492 +#if !defined(CONFIG_SOC_AR5312)
493 +# define cpu_has_mips32r2 1
494 +#endif
495 +
496 +#define cpu_has_mips64r1 0
497 +#define cpu_has_mips64r2 0
498 +
499 +#define cpu_has_dsp 0
500 +#define cpu_has_mipsmt 0
501 +
502 +#define cpu_has_64bits 0
503 +#define cpu_has_64bit_zero_reg 0
504 +#define cpu_has_64bit_gp_regs 0
505 +#define cpu_has_64bit_addresses 0
506 +
507 +#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */
508 --- /dev/null
509 +++ b/arch/mips/include/asm/mach-ath25/dma-coherence.h
510 @@ -0,0 +1,82 @@
511 +/*
512 + * This file is subject to the terms and conditions of the GNU General Public
513 + * License. See the file "COPYING" in the main directory of this archive
514 + * for more details.
515 + *
516 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
517 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
518 + *
519 + */
520 +#ifndef __ASM_MACH_ATH25_DMA_COHERENCE_H
521 +#define __ASM_MACH_ATH25_DMA_COHERENCE_H
522 +
523 +#include <linux/device.h>
524 +
525 +/*
526 + * We need some arbitrary non-zero value to be programmed to the BAR1 register
527 + * of PCI host controller to enable DMA. The same value should be used as the
528 + * offset to calculate the physical address of DMA buffer for PCI devices.
529 + */
530 +#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
531 +
532 +static inline dma_addr_t ath25_dev_offset(struct device *dev)
533 +{
534 +#ifdef CONFIG_PCI
535 + extern struct bus_type pci_bus_type;
536 +
537 + if (dev && dev->bus == &pci_bus_type)
538 + return AR2315_PCI_HOST_SDRAM_BASEADDR;
539 +#endif
540 + return 0;
541 +}
542 +
543 +static inline dma_addr_t
544 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
545 +{
546 + return virt_to_phys(addr) + ath25_dev_offset(dev);
547 +}
548 +
549 +static inline dma_addr_t
550 +plat_map_dma_mem_page(struct device *dev, struct page *page)
551 +{
552 + return page_to_phys(page) + ath25_dev_offset(dev);
553 +}
554 +
555 +static inline unsigned long
556 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
557 +{
558 + return dma_addr - ath25_dev_offset(dev);
559 +}
560 +
561 +static inline void
562 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
563 + enum dma_data_direction direction)
564 +{
565 +}
566 +
567 +static inline int plat_dma_supported(struct device *dev, u64 mask)
568 +{
569 + return 1;
570 +}
571 +
572 +static inline void plat_extra_sync_for_device(struct device *dev)
573 +{
574 +}
575 +
576 +static inline int plat_dma_mapping_error(struct device *dev,
577 + dma_addr_t dma_addr)
578 +{
579 + return 0;
580 +}
581 +
582 +static inline int plat_device_is_coherent(struct device *dev)
583 +{
584 +#ifdef CONFIG_DMA_COHERENT
585 + return 1;
586 +#endif
587 +#ifdef CONFIG_DMA_NONCOHERENT
588 + return 0;
589 +#endif
590 +}
591 +
592 +#endif /* __ASM_MACH_ATH25_DMA_COHERENCE_H */
593 --- /dev/null
594 +++ b/arch/mips/include/asm/mach-ath25/gpio.h
595 @@ -0,0 +1,16 @@
596 +#ifndef __ASM_MACH_ATH25_GPIO_H
597 +#define __ASM_MACH_ATH25_GPIO_H
598 +
599 +#include <asm-generic/gpio.h>
600 +
601 +#define gpio_get_value __gpio_get_value
602 +#define gpio_set_value __gpio_set_value
603 +#define gpio_cansleep __gpio_cansleep
604 +#define gpio_to_irq __gpio_to_irq
605 +
606 +static inline int irq_to_gpio(unsigned irq)
607 +{
608 + return -EINVAL;
609 +}
610 +
611 +#endif /* __ASM_MACH_ATH25_GPIO_H */
612 --- /dev/null
613 +++ b/arch/mips/include/asm/mach-ath25/war.h
614 @@ -0,0 +1,25 @@
615 +/*
616 + * This file is subject to the terms and conditions of the GNU General Public
617 + * License. See the file "COPYING" in the main directory of this archive
618 + * for more details.
619 + *
620 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
621 + */
622 +#ifndef __ASM_MACH_ATH25_WAR_H
623 +#define __ASM_MACH_ATH25_WAR_H
624 +
625 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
626 +#define R4600_V1_HIT_CACHEOP_WAR 0
627 +#define R4600_V2_HIT_CACHEOP_WAR 0
628 +#define R5432_CP0_INTERRUPT_WAR 0
629 +#define BCM1250_M3_WAR 0
630 +#define SIBYTE_1956_WAR 0
631 +#define MIPS4K_ICACHE_REFILL_WAR 0
632 +#define MIPS_CACHE_SYNC_WAR 0
633 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
634 +#define RM9000_CDEX_SMP_WAR 0
635 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
636 +#define R10000_LLSC_WAR 0
637 +#define MIPS34K_MISSED_ITLB_WAR 0
638 +
639 +#endif /* __ASM_MACH_ATH25_WAR_H */
640 --- /dev/null
641 +++ b/arch/mips/ath25/ar2315_regs.h
642 @@ -0,0 +1,481 @@
643 +/*
644 + * Register definitions for AR2315+
645 + *
646 + * This file is subject to the terms and conditions of the GNU General Public
647 + * License. See the file "COPYING" in the main directory of this archive
648 + * for more details.
649 + *
650 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
651 + * Copyright (C) 2006 FON Technology, SL.
652 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
653 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
654 + */
655 +
656 +#ifndef __ASM_MACH_ATH25_AR2315_REGS_H
657 +#define __ASM_MACH_ATH25_AR2315_REGS_H
658 +
659 +/*
660 + * IRQs
661 + */
662 +#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
663 +#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
664 +#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
665 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
666 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
667 +
668 +/*
669 + * Miscellaneous interrupts, which share IP2.
670 + */
671 +#define AR2315_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+0)
672 +#define AR2315_MISC_IRQ_I2C_RSVD (AR231X_MISC_IRQ_BASE+1)
673 +#define AR2315_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+2)
674 +#define AR2315_MISC_IRQ_AHB (AR231X_MISC_IRQ_BASE+3)
675 +#define AR2315_MISC_IRQ_APB (AR231X_MISC_IRQ_BASE+4)
676 +#define AR2315_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+5)
677 +#define AR2315_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+6)
678 +#define AR2315_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+7)
679 +#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+8)
680 +#define AR2315_MISC_IRQ_COUNT 9
681 +
682 +/*
683 + * Address map
684 + */
685 +#define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */
686 +#define AR2315_SPI_READ_SIZE 0x01000000
687 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
688 +#define AR2315_PCI 0x10100000 /* PCI MMR */
689 +#define AR2315_PCI_SIZE 0x00001000
690 +#define AR2315_SDRAMCTL_BASE 0x10300000 /* SDRAM MMR */
691 +#define AR2315_SDRAMCTL_SIZE 0x00000020
692 +#define AR2315_LOCAL_BASE 0x10400000 /* Local bus MMR */
693 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
694 +#define AR2315_RST_BASE 0x11000000 /* Reset control MMR */
695 +#define AR2315_RST_SIZE 0x00000100
696 +#define AR2315_UART0 0x11100000 /* UART MMR */
697 +#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
698 +#define AR2315_PCIEXT 0x80000000 /* pci external */
699 +#define AR2315_PCIEXT_SZ 0x40000000
700 +
701 +/* MII registers offset inside Ethernet MMR region */
702 +#define AR2315_ENET0_MII (AR2315_ENET0 + 0x14)
703 +
704 +/*
705 + * Cold reset register
706 + */
707 +#define AR2315_COLD_RESET 0x0000
708 +
709 +#define AR2315_RESET_COLD_AHB 0x00000001
710 +#define AR2315_RESET_COLD_APB 0x00000002
711 +#define AR2315_RESET_COLD_CPU 0x00000004
712 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
713 +#define AR2315_RESET_SYSTEM \
714 + (RESET_COLD_CPU |\
715 + RESET_COLD_APB |\
716 + RESET_COLD_AHB) /* full system */
717 +#define AR2317_RESET_SYSTEM 0x00000010
718 +
719 +/*
720 + * Reset register
721 + */
722 +#define AR2315_RESET 0x0004
723 +
724 +/* warm reset WLAN0 MAC */
725 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
726 +/* warm reset WLAN0 BaseBand */
727 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
728 +/* warm reset MPEG-TS */
729 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
730 +/* warm reset PCI ahb/dma */
731 +#define AR2315_RESET_PCIDMA 0x00000008
732 +/* warm reset memory controller */
733 +#define AR2315_RESET_MEMCTL 0x00000010
734 +/* warm reset local bus */
735 +#define AR2315_RESET_LOCAL 0x00000020
736 +/* warm reset I2C bus */
737 +#define AR2315_RESET_I2C_RSVD 0x00000040
738 +/* warm reset SPI interface */
739 +#define AR2315_RESET_SPI 0x00000080
740 +/* warm reset UART0 */
741 +#define AR2315_RESET_UART0 0x00000100
742 +/* warm reset IR interface */
743 +#define AR2315_RESET_IR_RSVD 0x00000200
744 +/* cold reset ENET0 phy */
745 +#define AR2315_RESET_EPHY0 0x00000400
746 +/* cold reset ENET0 mac */
747 +#define AR2315_RESET_ENET0 0x00000800
748 +
749 +/*
750 + * AHB master arbitration control
751 + */
752 +#define AR2315_AHB_ARB_CTL 0x0008
753 +
754 +/* CPU, default */
755 +#define AR2315_ARB_CPU 0x00000001
756 +/* WLAN */
757 +#define AR2315_ARB_WLAN 0x00000002
758 +/* MPEG-TS */
759 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
760 +/* LOCAL */
761 +#define AR2315_ARB_LOCAL 0x00000008
762 +/* PCI */
763 +#define AR2315_ARB_PCI 0x00000010
764 +/* Ethernet */
765 +#define AR2315_ARB_ETHERNET 0x00000020
766 +/* retry policy, debug only */
767 +#define AR2315_ARB_RETRY 0x00000100
768 +
769 +/*
770 + * Config Register
771 + */
772 +#define AR2315_ENDIAN_CTL 0x000c
773 +
774 +/* EC - AHB bridge endianess */
775 +#define AR2315_CONFIG_AHB 0x00000001
776 +/* WLAN byteswap */
777 +#define AR2315_CONFIG_WLAN 0x00000002
778 +/* MPEG-TS byteswap */
779 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
780 +/* PCI byteswap */
781 +#define AR2315_CONFIG_PCI 0x00000008
782 +/* Memory controller endianess */
783 +#define AR2315_CONFIG_MEMCTL 0x00000010
784 +/* Local bus byteswap */
785 +#define AR2315_CONFIG_LOCAL 0x00000020
786 +/* Ethernet byteswap */
787 +#define AR2315_CONFIG_ETHERNET 0x00000040
788 +
789 +/* CPU write buffer merge */
790 +#define AR2315_CONFIG_MERGE 0x00000200
791 +/* CPU big endian */
792 +#define AR2315_CONFIG_CPU 0x00000400
793 +#define AR2315_CONFIG_PCIAHB 0x00000800
794 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
795 +/* SPI byteswap */
796 +#define AR2315_CONFIG_SPI 0x00008000
797 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
798 +#define AR2315_CONFIG_CPU_PCI 0x00020000
799 +#define AR2315_CONFIG_CPU_MMR 0x00040000
800 +#define AR2315_CONFIG_BIG 0x00000400
801 +
802 +/*
803 + * NMI control
804 + */
805 +#define AR2315_NMI_CTL 0x0010
806 +
807 +#define AR2315_NMI_EN 1
808 +
809 +/*
810 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0).
811 + */
812 +#define AR2315_SREV 0x0014
813 +
814 +#define AR2315_REV_MAJ 0x00f0
815 +#define AR2315_REV_MAJ_S 4
816 +#define AR2315_REV_MIN 0x000f
817 +#define AR2315_REV_MIN_S 0
818 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
819 +
820 +/*
821 + * Interface Enable
822 + */
823 +#define AR2315_IF_CTL 0x0018
824 +
825 +#define AR2315_IF_MASK 0x00000007
826 +#define AR2315_IF_DISABLED 0
827 +#define AR2315_IF_PCI 1
828 +#define AR2315_IF_TS_LOCAL 2
829 +/* only for emulation with separate pins */
830 +#define AR2315_IF_ALL 3
831 +#define AR2315_IF_LOCAL_HOST 0x00000008
832 +#define AR2315_IF_PCI_HOST 0x00000010
833 +#define AR2315_IF_PCI_INTR 0x00000020
834 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
835 +#define AR2315_IF_PCI_CLK_INPUT 0
836 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
837 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
838 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
839 +#define AR2315_IF_PCI_CLK_SHIFT 16
840 +
841 +/*
842 + * APB Interrupt control
843 + */
844 +
845 +#define AR2315_ISR 0x0020
846 +#define AR2315_IMR 0x0024
847 +#define AR2315_GISR 0x0028
848 +
849 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
850 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
851 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
852 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
853 +#define AR2315_ISR_APB 0x0010 /* APB error */
854 +#define AR2315_ISR_TIMER 0x0020 /* timer */
855 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
856 +#define AR2315_ISR_WD 0x0080 /* watchdog */
857 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
858 +
859 +#define AR2315_GISR_MISC 0x0001
860 +#define AR2315_GISR_WLAN0 0x0002
861 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
862 +#define AR2315_GISR_LOCALPCI 0x0008
863 +#define AR2315_GISR_WMACPOLL 0x0010
864 +#define AR2315_GISR_TIMER 0x0020
865 +#define AR2315_GISR_ETHERNET 0x0040
866 +
867 +/*
868 + * Timers
869 + */
870 +#define AR2315_TIMER 0x0030
871 +#define AR2315_RELOAD 0x0034
872 +
873 +#define AR2315_WD 0x0038
874 +#define AR2315_WDC 0x003c
875 +
876 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
877 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
878 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
879 +
880 +/*
881 + * CPU Performance Counters
882 + */
883 +#define AR2315_PERFCNT0 0x0048
884 +#define AR2315_PERFCNT1 0x004c
885 +
886 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
887 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
888 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
889 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
890 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
891 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
892 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
893 +
894 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
895 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
896 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
897 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
898 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
899 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
900 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
901 +
902 +/*
903 + * AHB Error Reporting.
904 + */
905 +#define AR2315_AHB_ERR0 0x0050 /* error */
906 +#define AR2315_AHB_ERR1 0x0054 /* haddr */
907 +#define AR2315_AHB_ERR2 0x0058 /* hwdata */
908 +#define AR2315_AHB_ERR3 0x005c /* hrdata */
909 +#define AR2315_AHB_ERR4 0x0060 /* status */
910 +
911 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
912 + /* write 1 to clear all bits in ERR0 */
913 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
914 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
915 +
916 +#define AR2315_PROCERR_HMAST 0x0000000f
917 +#define AR2315_PROCERR_HMAST_DFLT 0
918 +#define AR2315_PROCERR_HMAST_WMAC 1
919 +#define AR2315_PROCERR_HMAST_ENET 2
920 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
921 +#define AR2315_PROCERR_HMAST_LOCAL 4
922 +#define AR2315_PROCERR_HMAST_CPU 5
923 +#define AR2315_PROCERR_HMAST_PCITGT 6
924 +
925 +#define AR2315_PROCERR_HMAST_S 0
926 +#define AR2315_PROCERR_HWRITE 0x00000010
927 +#define AR2315_PROCERR_HSIZE 0x00000060
928 +#define AR2315_PROCERR_HSIZE_S 5
929 +#define AR2315_PROCERR_HTRANS 0x00000180
930 +#define AR2315_PROCERR_HTRANS_S 7
931 +#define AR2315_PROCERR_HBURST 0x00000e00
932 +#define AR2315_PROCERR_HBURST_S 9
933 +
934 +/*
935 + * Clock Control
936 + */
937 +#define AR2315_PLLC_CTL 0x0064
938 +#define AR2315_PLLV_CTL 0x0068
939 +#define AR2315_CPUCLK 0x006c
940 +#define AR2315_AMBACLK 0x0070
941 +#define AR2315_SYNCCLK 0x0074
942 +#define AR2315_DSL_SLEEP_CTL 0x0080
943 +#define AR2315_DSL_SLEEP_DUR 0x0084
944 +
945 +/* PLLc Control fields */
946 +#define PLLC_REF_DIV_M 0x00000003
947 +#define PLLC_REF_DIV_S 0
948 +#define PLLC_FDBACK_DIV_M 0x0000007C
949 +#define PLLC_FDBACK_DIV_S 2
950 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
951 +#define PLLC_ADD_FDBACK_DIV_S 7
952 +#define PLLC_CLKC_DIV_M 0x0001c000
953 +#define PLLC_CLKC_DIV_S 14
954 +#define PLLC_CLKM_DIV_M 0x00700000
955 +#define PLLC_CLKM_DIV_S 20
956 +
957 +/* CPU CLK Control fields */
958 +#define CPUCLK_CLK_SEL_M 0x00000003
959 +#define CPUCLK_CLK_SEL_S 0
960 +#define CPUCLK_CLK_DIV_M 0x0000000c
961 +#define CPUCLK_CLK_DIV_S 2
962 +
963 +/* AMBA CLK Control fields */
964 +#define AMBACLK_CLK_SEL_M 0x00000003
965 +#define AMBACLK_CLK_SEL_S 0
966 +#define AMBACLK_CLK_DIV_M 0x0000000c
967 +#define AMBACLK_CLK_DIV_S 2
968 +
969 +/* GPIO MMR base address */
970 +#define AR2315_GPIO 0x0088
971 +
972 +#define AR2315_RESET_GPIO 5
973 +
974 +/*
975 + * PCI Clock Control
976 + */
977 +#define AR2315_PCICLK 0x00a4
978 +
979 +#define AR2315_PCICLK_INPUT_M 0x3
980 +#define AR2315_PCICLK_INPUT_S 0
981 +
982 +#define AR2315_PCICLK_PLLC_CLKM 0
983 +#define AR2315_PCICLK_PLLC_CLKM1 1
984 +#define AR2315_PCICLK_PLLC_CLKC 2
985 +#define AR2315_PCICLK_REF_CLK 3
986 +
987 +#define AR2315_PCICLK_DIV_M 0xc
988 +#define AR2315_PCICLK_DIV_S 2
989 +
990 +#define AR2315_PCICLK_IN_FREQ 0
991 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
992 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
993 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
994 +
995 +/*
996 + * Observation Control Register
997 + */
998 +#define AR2315_OCR 0x00b0
999 +
1000 +#define OCR_GPIO0_IRIN 0x0040
1001 +#define OCR_GPIO1_IROUT 0x0080
1002 +#define OCR_GPIO3_RXCLR 0x0200
1003 +
1004 +/*
1005 + * General Clock Control
1006 + */
1007 +#define AR2315_MISCCLK 0x00b4
1008 +
1009 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1010 +#define MISCCLK_PROCREFCLK 0x00000002
1011 +
1012 +/*
1013 + * SDRAM Controller
1014 + * - No read or write buffers are included.
1015 + */
1016 +#define AR2315_MEM_CFG 0x0000
1017 +#define AR2315_MEM_CTRL 0x000c
1018 +#define AR2315_MEM_REF 0x0010
1019 +
1020 +#define SDRAM_DATA_WIDTH_M 0x00006000
1021 +#define SDRAM_DATA_WIDTH_S 13
1022 +
1023 +#define SDRAM_COL_WIDTH_M 0x00001E00
1024 +#define SDRAM_COL_WIDTH_S 9
1025 +
1026 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1027 +#define SDRAM_ROW_WIDTH_S 5
1028 +
1029 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1030 +#define SDRAM_BANKADDR_BITS_S 3
1031 +
1032 +/*
1033 + * Local Bus Interface Registers
1034 + */
1035 +#define AR2315_LB_CONFIG 0x0000
1036 +
1037 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1038 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1039 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1040 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1041 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1042 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1043 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1044 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1045 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1046 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1047 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1048 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1049 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1050 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1051 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1052 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1053 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1054 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1055 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1056 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1057 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1058 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1059 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1060 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1061 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1062 +
1063 +#define AR2315_LB_CLKSEL 0x0004
1064 +
1065 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1066 +
1067 +#define AR2315_LB_1MS 0x0008
1068 +
1069 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1070 +
1071 +#define AR2315_LB_MISCCFG 0x000c
1072 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1073 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1074 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1075 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1076 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1077 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1078 +#define AR2315_LBM_TIMEOUT_SHFT 7
1079 +#define AR2315_LBM_PORTMUX 0x07000000
1080 +
1081 +#define AR2315_LB_RXTSOFF 0x0010
1082 +
1083 +#define AR2315_LB_TX_CHAIN_EN 0x0100
1084 +
1085 +#define AR2315_LB_TXEN_0 0x01
1086 +#define AR2315_LB_TXEN_1 0x02
1087 +#define AR2315_LB_TXEN_2 0x04
1088 +#define AR2315_LB_TXEN_3 0x08
1089 +
1090 +#define AR2315_LB_TX_CHAIN_DIS 0x0104
1091 +#define AR2315_LB_TX_DESC_PTR 0x0200
1092 +
1093 +#define AR2315_LB_RX_CHAIN_EN 0x0400
1094 +
1095 +#define AR2315_LB_RXEN 0x01
1096 +
1097 +#define AR2315_LB_RX_CHAIN_DIS 0x0404
1098 +#define AR2315_LB_RX_DESC_PTR 0x0408
1099 +
1100 +#define AR2315_LB_INT_STATUS 0x0500
1101 +
1102 +#define AR2315_INT_TX_DESC 0x0001
1103 +#define AR2315_INT_TX_OK 0x0002
1104 +#define AR2315_INT_TX_ERR 0x0004
1105 +#define AR2315_INT_TX_EOF 0x0008
1106 +#define AR2315_INT_RX_DESC 0x0010
1107 +#define AR2315_INT_RX_OK 0x0020
1108 +#define AR2315_INT_RX_ERR 0x0040
1109 +#define AR2315_INT_RX_EOF 0x0080
1110 +#define AR2315_INT_TX_TRUNC 0x0100
1111 +#define AR2315_INT_TX_STARVE 0x0200
1112 +#define AR2315_INT_LB_TIMEOUT 0x0400
1113 +#define AR2315_INT_LB_ERR 0x0800
1114 +#define AR2315_INT_MBOX_WR 0x1000
1115 +#define AR2315_INT_MBOX_RD 0x2000
1116 +
1117 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1118 +#define AR2315_LB_INT_MASK 0x0504
1119 +
1120 +#define AR2315_LB_INT_EN 0x0508
1121 +#define AR2315_LB_MBOX 0x0600
1122 +
1123 +#endif /* __ASM_MACH_ATH25_AR2315_REGS_H */
1124 --- /dev/null
1125 +++ b/arch/mips/ath25/ar5312_regs.h
1126 @@ -0,0 +1,228 @@
1127 +/*
1128 + * This file is subject to the terms and conditions of the GNU General Public
1129 + * License. See the file "COPYING" in the main directory of this archive
1130 + * for more details.
1131 + *
1132 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1133 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1134 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1135 + */
1136 +
1137 +#ifndef __ASM_MACH_ATH25_AR5312_REGS_H
1138 +#define __ASM_MACH_ATH25_AR5312_REGS_H
1139 +
1140 +#include <asm/addrspace.h>
1141 +
1142 +/*
1143 + * IRQs
1144 + */
1145 +#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
1146 +#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
1147 +#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
1148 +#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
1149 +#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
1150 +
1151 +/*
1152 + * Miscellaneous interrupts, which share IP6.
1153 + */
1154 +#define AR5312_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+0)
1155 +#define AR5312_MISC_IRQ_AHB_PROC (AR231X_MISC_IRQ_BASE+1)
1156 +#define AR5312_MISC_IRQ_AHB_DMA (AR231X_MISC_IRQ_BASE+2)
1157 +#define AR5312_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+3)
1158 +#define AR5312_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+4)
1159 +#define AR5312_MISC_IRQ_UART0_DMA (AR231X_MISC_IRQ_BASE+5)
1160 +#define AR5312_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+6)
1161 +#define AR5312_MISC_IRQ_LOCAL (AR231X_MISC_IRQ_BASE+7)
1162 +#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+8)
1163 +#define AR5312_MISC_IRQ_COUNT 9
1164 +
1165 +/*
1166 + * Address Map
1167 + *
1168 + * The AR5312 supports 2 enet MACS, even though many reference boards only
1169 + * actually use 1 of them (i.e. Only MAC 0 is actually connected to an enet
1170 + * PHY or PHY switch. The AR2312 supports 1 enet MAC.
1171 + */
1172 +#define AR5312_WLAN0 0x18000000
1173 +#define AR5312_WLAN1 0x18500000
1174 +#define AR5312_ENET0 0x18100000
1175 +#define AR5312_ENET1 0x18200000
1176 +#define AR5312_SDRAMCTL_BASE 0x18300000
1177 +#define AR5312_SDRAMCTL_SIZE 0x00000010
1178 +#define AR5312_FLASHCTL_BASE 0x18400000
1179 +#define AR5312_FLASHCTL_SIZE 0x00000010
1180 +#define AR5312_UART0 0x1c000000 /* UART MMR */
1181 +#define AR5312_GPIO_BASE 0x1c002000
1182 +#define AR5312_RST_BASE 0x1c003000
1183 +#define AR5312_RST_SIZE 0x00000100
1184 +#define AR5312_FLASH_BASE 0x1e000000
1185 +#define AR5312_FLASH_SIZE 0x00800000
1186 +
1187 +/*
1188 + * Need these defines to determine true number of ethernet MACs
1189 + */
1190 +#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1191 +#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1192 +#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1193 +
1194 +/* MII registers offset inside Ethernet MMR region */
1195 +#define AR5312_ENET0_MII (AR5312_ENET0 + 0x14)
1196 +#define AR5312_ENET1_MII (AR5312_ENET1 + 0x14)
1197 +
1198 +/* Reset/Timer Block Address Map */
1199 +#define AR5312_TIMER 0x0000 /* countdown timer */
1200 +#define AR5312_RELOAD 0x0004 /* timer reload value */
1201 +#define AR5312_WD_CTRL 0x0008 /* watchdog cntrl */
1202 +#define AR5312_WD_TIMER 0x000c /* watchdog timer */
1203 +#define AR5312_ISR 0x0010 /* Intr Status Reg */
1204 +#define AR5312_IMR 0x0014 /* Intr Mask Reg */
1205 +#define AR5312_RESET 0x0020
1206 +#define AR5312_CLOCKCTL1 0x0064
1207 +#define AR5312_SCRATCH 0x006c
1208 +#define AR5312_PROCADDR 0x0070
1209 +#define AR5312_PROC1 0x0074
1210 +#define AR5312_DMAADDR 0x0078
1211 +#define AR5312_DMA1 0x007c
1212 +#define AR5312_ENABLE 0x0080 /* interface enb */
1213 +#define AR5312_REV 0x0090 /* revision */
1214 +
1215 +/* AR5312_WD_CTRL register bit field definitions */
1216 +#define AR5312_WD_CTRL_IGNORE_EXPIRATION 0x0000
1217 +#define AR5312_WD_CTRL_NMI 0x0001
1218 +#define AR5312_WD_CTRL_RESET 0x0002
1219 +
1220 +/* AR5312_ISR register bit field definitions */
1221 +#define AR5312_ISR_TIMER 0x0001
1222 +#define AR5312_ISR_AHBPROC 0x0002
1223 +#define AR5312_ISR_AHBDMA 0x0004
1224 +#define AR5312_ISR_GPIO 0x0008
1225 +#define AR5312_ISR_UART0 0x0010
1226 +#define AR5312_ISR_UART0DMA 0x0020
1227 +#define AR5312_ISR_WD 0x0040
1228 +#define AR5312_ISR_LOCAL 0x0080
1229 +
1230 +/* AR5312_RESET register bit field definitions */
1231 +#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
1232 +#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
1233 +#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1234 +#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1235 +#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1236 +#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1237 +#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1238 +#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1239 +#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1240 +#define AR5312_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1241 +#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1242 +#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1243 +#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1244 +#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the processor */
1245 +#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1246 +#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1247 +#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1248 +#define AR5312_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1249 +
1250 +#define AR5312_RESET_WMAC0_BITS \
1251 + (AR5312_RESET_WLAN0 |\
1252 + AR5312_RESET_WARM_WLAN0_MAC |\
1253 + AR5312_RESET_WARM_WLAN0_BB)
1254 +
1255 +#define AR5312_RESET_WMAC1_BITS \
1256 + (AR5312_RESET_WLAN1 |\
1257 + AR5312_RESET_WARM_WLAN1_MAC |\
1258 + AR5312_RESET_WARM_WLAN1_BB)
1259 +
1260 +/* AR5312_CLOCKCTL1 register bit field definitions */
1261 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1262 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1263 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1264 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1265 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1266 +
1267 +/* Valid for AR5312 and AR2312 */
1268 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1269 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1270 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1271 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1272 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1273 +
1274 +/* Valid for AR2313 */
1275 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1276 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1277 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1278 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1279 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1280 +
1281 +/* AR5312_ENABLE register bit field definitions */
1282 +#define AR5312_ENABLE_WLAN0 0x0001
1283 +#define AR5312_ENABLE_ENET0 0x0002
1284 +#define AR5312_ENABLE_ENET1 0x0004
1285 +#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1286 +#define AR5312_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1287 +#define AR5312_ENABLE_WLAN1 \
1288 + (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
1289 + AR5312_ENABLE_WLAN1_DMA)
1290 +
1291 +/* AR5312_REV register bit field definitions */
1292 +#define AR5312_REV_WMAC_MAJ 0xf000
1293 +#define AR5312_REV_WMAC_MAJ_S 12
1294 +#define AR5312_REV_WMAC_MIN 0x0f00
1295 +#define AR5312_REV_WMAC_MIN_S 8
1296 +#define AR5312_REV_MAJ 0x00f0
1297 +#define AR5312_REV_MAJ_S 4
1298 +#define AR5312_REV_MIN 0x000f
1299 +#define AR5312_REV_MIN_S 0
1300 +#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
1301 +
1302 +/* Major revision numbers, bits 7..4 of Revision ID register */
1303 +#define AR5312_REV_MAJ_AR5312 0x4
1304 +#define AR5312_REV_MAJ_AR2313 0x5
1305 +
1306 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1307 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1308 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1309 +
1310 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1311 +#define AR5312_FLASHCTL0 0x0000
1312 +#define AR5312_FLASHCTL1 0x0004
1313 +#define AR5312_FLASHCTL2 0x0008
1314 +
1315 +/* AR5312_FLASHCTL register bit field definitions */
1316 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1317 +#define FLASHCTL_IDCY_S 0
1318 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1319 +#define FLASHCTL_WST1_S 5
1320 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1321 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1322 +#define FLASHCTL_WST2_S 11
1323 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1324 +#define FLASHCTL_AC_S 16
1325 +#define FLASHCTL_AC_128K 0x00000000
1326 +#define FLASHCTL_AC_256K 0x00010000
1327 +#define FLASHCTL_AC_512K 0x00020000
1328 +#define FLASHCTL_AC_1M 0x00030000
1329 +#define FLASHCTL_AC_2M 0x00040000
1330 +#define FLASHCTL_AC_4M 0x00050000
1331 +#define FLASHCTL_AC_8M 0x00060000
1332 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1333 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1334 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1335 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1336 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1337 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1338 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1339 +#define FLASHCTL_MW8 0x00000000 /* Memory width x8 */
1340 +#define FLASHCTL_MW16 0x10000000 /* Memory width x16 */
1341 +#define FLASHCTL_MW32 0x20000000 /* Memory width x32 (not supported) */
1342 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1343 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1344 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1345 +
1346 +/* ARM SDRAM Controller -- just enough to determine memory size */
1347 +#define AR5312_MEM_CFG1 0x0004
1348 +
1349 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1350 +#define MEM_CFG1_AC0_S 8
1351 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1352 +#define MEM_CFG1_AC1_S 12
1353 +
1354 +#endif /* __ASM_MACH_ATH25_AR5312_REGS_H */
1355 --- /dev/null
1356 +++ b/arch/mips/ath25/ar5312.c
1357 @@ -0,0 +1,478 @@
1358 +/*
1359 + * This file is subject to the terms and conditions of the GNU General Public
1360 + * License. See the file "COPYING" in the main directory of this archive
1361 + * for more details.
1362 + *
1363 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1364 + * Copyright (C) 2006 FON Technology, SL.
1365 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1366 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1367 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1368 + */
1369 +
1370 +/*
1371 + * Platform devices for Atheros SoCs
1372 + */
1373 +
1374 +#include <generated/autoconf.h>
1375 +#include <linux/init.h>
1376 +#include <linux/module.h>
1377 +#include <linux/types.h>
1378 +#include <linux/string.h>
1379 +#include <linux/mtd/physmap.h>
1380 +#include <linux/platform_device.h>
1381 +#include <linux/kernel.h>
1382 +#include <linux/reboot.h>
1383 +#include <linux/leds.h>
1384 +#include <linux/gpio.h>
1385 +#include <asm/bootinfo.h>
1386 +#include <asm/reboot.h>
1387 +#include <asm/time.h>
1388 +#include <linux/irq.h>
1389 +#include <linux/io.h>
1390 +
1391 +#include <ath25_platform.h>
1392 +
1393 +#include "devices.h"
1394 +#include "ar5312.h"
1395 +#include "ar5312_regs.h"
1396 +
1397 +static void __iomem *ar5312_rst_base;
1398 +
1399 +static inline u32 ar5312_rst_reg_read(u32 reg)
1400 +{
1401 + return __raw_readl(ar5312_rst_base + reg);
1402 +}
1403 +
1404 +static inline void ar5312_rst_reg_write(u32 reg, u32 val)
1405 +{
1406 + __raw_writel(val, ar5312_rst_base + reg);
1407 +}
1408 +
1409 +static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val)
1410 +{
1411 + u32 ret = ar5312_rst_reg_read(reg);
1412 +
1413 + ret &= ~mask;
1414 + ret |= val;
1415 + ar5312_rst_reg_write(reg, ret);
1416 +}
1417 +
1418 +static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id)
1419 +{
1420 + u32 proc1 = ar5312_rst_reg_read(AR5312_PROC1);
1421 + u32 proc_addr = ar5312_rst_reg_read(AR5312_PROCADDR); /* clears error */
1422 + u32 dma1 = ar5312_rst_reg_read(AR5312_DMA1);
1423 + u32 dma_addr = ar5312_rst_reg_read(AR5312_DMAADDR); /* clears error */
1424 +
1425 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1426 + proc_addr, proc1, dma_addr, dma1);
1427 +
1428 + machine_restart("AHB error"); /* Catastrophic failure */
1429 + return IRQ_HANDLED;
1430 +}
1431 +
1432 +static struct irqaction ar5312_ahb_err_interrupt = {
1433 + .handler = ar5312_ahb_err_handler,
1434 + .name = "ar5312-ahb-error",
1435 +};
1436 +
1437 +static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1438 +{
1439 + unsigned int ar231x_misc_intrs = ar5312_rst_reg_read(AR5312_ISR) &
1440 + ar5312_rst_reg_read(AR5312_IMR);
1441 +
1442 + if (ar231x_misc_intrs & AR5312_ISR_TIMER) {
1443 + generic_handle_irq(AR5312_MISC_IRQ_TIMER);
1444 + (void)ar5312_rst_reg_read(AR5312_TIMER);
1445 + } else if (ar231x_misc_intrs & AR5312_ISR_AHBPROC)
1446 + generic_handle_irq(AR5312_MISC_IRQ_AHB_PROC);
1447 + else if ((ar231x_misc_intrs & AR5312_ISR_UART0))
1448 + generic_handle_irq(AR5312_MISC_IRQ_UART0);
1449 + else if (ar231x_misc_intrs & AR5312_ISR_WD)
1450 + generic_handle_irq(AR5312_MISC_IRQ_WATCHDOG);
1451 + else
1452 + spurious_interrupt();
1453 +}
1454 +
1455 +/* Enable the specified AR5312_MISC_IRQ interrupt */
1456 +static void ar5312_misc_irq_unmask(struct irq_data *d)
1457 +{
1458 + unsigned int imr;
1459 +
1460 + imr = ar5312_rst_reg_read(AR5312_IMR);
1461 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
1462 + ar5312_rst_reg_write(AR5312_IMR, imr);
1463 +}
1464 +
1465 +/* Disable the specified AR5312_MISC_IRQ interrupt */
1466 +static void ar5312_misc_irq_mask(struct irq_data *d)
1467 +{
1468 + unsigned int imr;
1469 +
1470 + imr = ar5312_rst_reg_read(AR5312_IMR);
1471 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
1472 + ar5312_rst_reg_write(AR5312_IMR, imr);
1473 + ar5312_rst_reg_read(AR5312_IMR); /* flush write buffer */
1474 +}
1475 +
1476 +static struct irq_chip ar5312_misc_irq_chip = {
1477 + .name = "ar5312-misc",
1478 + .irq_unmask = ar5312_misc_irq_unmask,
1479 + .irq_mask = ar5312_misc_irq_mask,
1480 +};
1481 +
1482 +static void ar5312_irq_dispatch(void)
1483 +{
1484 + int pending = read_c0_status() & read_c0_cause();
1485 +
1486 + if (pending & CAUSEF_IP2)
1487 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1488 + else if (pending & CAUSEF_IP3)
1489 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1490 + else if (pending & CAUSEF_IP4)
1491 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1492 + else if (pending & CAUSEF_IP5)
1493 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1494 + else if (pending & CAUSEF_IP6)
1495 + do_IRQ(AR5312_IRQ_MISC_INTRS);
1496 + else if (pending & CAUSEF_IP7)
1497 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
1498 + else
1499 + spurious_interrupt();
1500 +}
1501 +
1502 +void __init ar5312_arch_init_irq(void)
1503 +{
1504 + int i;
1505 +
1506 + ath25_irq_dispatch = ar5312_irq_dispatch;
1507 + for (i = 0; i < AR5312_MISC_IRQ_COUNT; i++) {
1508 + int irq = AR231X_MISC_IRQ_BASE + i;
1509 +
1510 + irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
1511 + handle_level_irq);
1512 + }
1513 + setup_irq(AR5312_MISC_IRQ_AHB_PROC, &ar5312_ahb_err_interrupt);
1514 + irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
1515 +}
1516 +
1517 +static void ar5312_device_reset_set(u32 mask)
1518 +{
1519 + u32 val;
1520 +
1521 + val = ar5312_rst_reg_read(AR5312_RESET);
1522 + ar5312_rst_reg_write(AR5312_RESET, val | mask);
1523 +}
1524 +
1525 +static void ar5312_device_reset_clear(u32 mask)
1526 +{
1527 + u32 val;
1528 +
1529 + val = ar5312_rst_reg_read(AR5312_RESET);
1530 + ar5312_rst_reg_write(AR5312_RESET, val & ~mask);
1531 +}
1532 +
1533 +static struct physmap_flash_data ar5312_flash_data = {
1534 + .width = 2,
1535 +};
1536 +
1537 +static struct resource ar5312_flash_resource = {
1538 + .start = AR5312_FLASH_BASE,
1539 + .end = AR5312_FLASH_BASE + AR5312_FLASH_SIZE - 1,
1540 + .flags = IORESOURCE_MEM,
1541 +};
1542 +
1543 +static struct ar231x_eth ar5312_eth0_data = {
1544 + .reset_set = ar5312_device_reset_set,
1545 + .reset_clear = ar5312_device_reset_clear,
1546 + .reset_mac = AR5312_RESET_ENET0,
1547 + .reset_phy = AR5312_RESET_EPHY0,
1548 +};
1549 +
1550 +static struct ar231x_eth ar5312_eth1_data = {
1551 + .reset_set = ar5312_device_reset_set,
1552 + .reset_clear = ar5312_device_reset_clear,
1553 + .reset_mac = AR5312_RESET_ENET1,
1554 + .reset_phy = AR5312_RESET_EPHY1,
1555 +};
1556 +
1557 +static struct platform_device ar5312_physmap_flash = {
1558 + .name = "physmap-flash",
1559 + .id = 0,
1560 + .dev.platform_data = &ar5312_flash_data,
1561 + .resource = &ar5312_flash_resource,
1562 + .num_resources = 1,
1563 +};
1564 +
1565 +#ifdef CONFIG_LEDS_GPIO
1566 +static struct gpio_led ar5312_leds[] = {
1567 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1568 +};
1569 +
1570 +static const struct gpio_led_platform_data ar5312_led_data = {
1571 + .num_leds = ARRAY_SIZE(ar5312_leds),
1572 + .leds = (void *)ar5312_leds,
1573 +};
1574 +
1575 +static struct platform_device ar5312_gpio_leds = {
1576 + .name = "leds-gpio",
1577 + .id = -1,
1578 + .dev.platform_data = (void *)&ar5312_led_data,
1579 +};
1580 +#endif
1581 +
1582 +static void __init ar5312_flash_init(void)
1583 +{
1584 + void __iomem *flashctl_base;
1585 + u32 ctl;
1586 +
1587 + flashctl_base = ioremap_nocache(AR5312_FLASHCTL_BASE,
1588 + AR5312_FLASHCTL_SIZE);
1589 +
1590 + ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL0);
1591 + ctl &= FLASHCTL_MW;
1592 +
1593 + /* fixup flash width */
1594 + switch (ctl) {
1595 + case FLASHCTL_MW16:
1596 + ar5312_flash_data.width = 2;
1597 + break;
1598 + case FLASHCTL_MW8:
1599 + default:
1600 + ar5312_flash_data.width = 1;
1601 + break;
1602 + }
1603 +
1604 + /*
1605 + * Configure flash bank 0.
1606 + * Assume 8M window size. Flash will be aliased if it's smaller
1607 + */
1608 + ctl = FLASHCTL_E |
1609 + FLASHCTL_AC_8M |
1610 + FLASHCTL_RBLE |
1611 + (0x01 << FLASHCTL_IDCY_S) |
1612 + (0x07 << FLASHCTL_WST1_S) |
1613 + (0x07 << FLASHCTL_WST2_S) |
1614 + ctl;
1615 +
1616 + __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL0);
1617 +
1618 + /* Disable other flash banks */
1619 + ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL1);
1620 + ctl &= ~(FLASHCTL_E | FLASHCTL_AC);
1621 + __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL1);
1622 + ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL2);
1623 + ctl &= ~(FLASHCTL_E | FLASHCTL_AC);
1624 + __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL2);
1625 +
1626 + iounmap(flashctl_base);
1627 +}
1628 +
1629 +void __init ar5312_init_devices(void)
1630 +{
1631 + struct ath25_boarddata *config;
1632 + u8 *c;
1633 +
1634 + ar5312_flash_init();
1635 +
1636 + /* Locate board/radio config data */
1637 + ath25_find_config(AR5312_FLASH_BASE, AR5312_FLASH_SIZE);
1638 + config = ath25_board.config;
1639 +
1640 + /* AR2313 has CPU minor rev. 10 */
1641 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1642 + ath25_soc = ATH25_SOC_AR2313;
1643 +
1644 + /* AR2312 shares the same Silicon ID as AR5312 */
1645 + else if (config->flags & BD_ISCASPER)
1646 + ath25_soc = ATH25_SOC_AR2312;
1647 +
1648 + /* Everything else is probably AR5312 or compatible */
1649 + else
1650 + ath25_soc = ATH25_SOC_AR5312;
1651 +
1652 + platform_device_register(&ar5312_physmap_flash);
1653 +
1654 +#ifdef CONFIG_LEDS_GPIO
1655 + ar5312_leds[0].gpio = config->sys_led_gpio;
1656 + platform_device_register(&ar5312_gpio_leds);
1657 +#endif
1658 +
1659 + /* Fix up MAC addresses if necessary */
1660 + if (is_broadcast_ether_addr(config->enet0_mac))
1661 + ether_addr_copy(config->enet0_mac, config->enet1_mac);
1662 +
1663 + /* If ENET0 and ENET1 have the same mac address,
1664 + * increment the one from ENET1 */
1665 + if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) {
1666 + c = config->enet1_mac + 5;
1667 + while ((c >= config->enet1_mac) && !(++(*c)))
1668 + c--;
1669 + }
1670 +
1671 + switch (ath25_soc) {
1672 + case ATH25_SOC_AR5312:
1673 + ar5312_eth0_data.macaddr = config->enet0_mac;
1674 + ath25_add_ethernet(0, AR5312_ENET0, "eth0_mii",
1675 + AR5312_ENET0_MII, AR5312_IRQ_ENET0_INTRS,
1676 + &ar5312_eth0_data);
1677 +
1678 + ar5312_eth1_data.macaddr = config->enet1_mac;
1679 + ath25_add_ethernet(1, AR5312_ENET1, "eth1_mii",
1680 + AR5312_ENET1_MII, AR5312_IRQ_ENET1_INTRS,
1681 + &ar5312_eth1_data);
1682 +
1683 + if (!ath25_board.radio)
1684 + return;
1685 +
1686 + if (!(config->flags & BD_WLAN0))
1687 + break;
1688 +
1689 + ath25_add_wmac(0, AR5312_WLAN0, AR5312_IRQ_WLAN0_INTRS);
1690 + break;
1691 + /*
1692 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1693 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1694 + */
1695 + case ATH25_SOC_AR2312:
1696 + case ATH25_SOC_AR2313:
1697 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1698 + ar5312_eth1_data.macaddr = config->enet0_mac;
1699 + ath25_add_ethernet(1, AR5312_ENET1, "eth0_mii",
1700 + AR5312_ENET0_MII, AR5312_IRQ_ENET1_INTRS,
1701 + &ar5312_eth1_data);
1702 +
1703 + if (!ath25_board.radio)
1704 + return;
1705 + break;
1706 + default:
1707 + break;
1708 + }
1709 +
1710 + if (config->flags & BD_WLAN1)
1711 + ath25_add_wmac(1, AR5312_WLAN1, AR5312_IRQ_WLAN1_INTRS);
1712 +}
1713 +
1714 +static void ar5312_restart(char *command)
1715 +{
1716 + /* reset the system */
1717 + local_irq_disable();
1718 + while (1)
1719 + ar5312_rst_reg_write(AR5312_RESET, AR5312_RESET_SYSTEM);
1720 +}
1721 +
1722 +/*
1723 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1724 + * to determine the predevisor value.
1725 + */
1726 +static unsigned clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
1727 +
1728 +static unsigned __init ar5312_cpu_frequency(void)
1729 +{
1730 + unsigned int scratch;
1731 + unsigned int predivide_mask, predivide_shift;
1732 + unsigned int multiplier_mask, multiplier_shift;
1733 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
1734 + unsigned int doubler_mask;
1735 + u16 devid;
1736 +
1737 + /* Trust the bootrom's idea of cpu frequency. */
1738 + scratch = ar5312_rst_reg_read(AR5312_SCRATCH);
1739 + if (scratch)
1740 + return scratch;
1741 +
1742 + devid = ar5312_rst_reg_read(AR5312_REV);
1743 + devid &= AR5312_REV_MAJ;
1744 + devid >>= AR5312_REV_MAJ_S;
1745 + if (devid == AR5312_REV_MAJ_AR2313) {
1746 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
1747 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
1748 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
1749 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
1750 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
1751 + } else { /* AR5312 and AR2312 */
1752 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
1753 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
1754 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
1755 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
1756 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
1757 + }
1758 +
1759 + /*
1760 + * Clocking is derived from a fixed 40MHz input clock.
1761 + *
1762 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
1763 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
1764 + * flash, Timer, Watchdog Timer)
1765 + *
1766 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
1767 + *
1768 + * So, for example, with a PLL multiplier of 5, we have
1769 + *
1770 + * cpu_freq = 200MHz
1771 + * sys_freq = 50MHz
1772 + * cnt_freq = 100MHz
1773 + *
1774 + * We compute the CPU frequency, based on PLL settings.
1775 + */
1776 +
1777 + clock_ctl1 = ar5312_rst_reg_read(AR5312_CLOCKCTL1);
1778 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
1779 + predivisor = clockctl1_predivide_table[predivide_select];
1780 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
1781 +
1782 + if (clock_ctl1 & doubler_mask)
1783 + multiplier = multiplier << 1;
1784 +
1785 + return (40000000 / predivisor) * multiplier;
1786 +}
1787 +
1788 +static inline unsigned ar5312_sys_frequency(void)
1789 +{
1790 + return ar5312_cpu_frequency() / 4;
1791 +}
1792 +
1793 +void __init ar5312_plat_time_init(void)
1794 +{
1795 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
1796 +}
1797 +
1798 +void __init ar5312_plat_mem_setup(void)
1799 +{
1800 + void __iomem *sdram_base;
1801 + u32 memsize, memcfg, bank0AC, bank1AC;
1802 + u32 devid;
1803 +
1804 + /* Detect memory size */
1805 + sdram_base = ioremap_nocache(AR5312_SDRAMCTL_BASE,
1806 + AR5312_SDRAMCTL_SIZE);
1807 + memcfg = __raw_readl(sdram_base + AR5312_MEM_CFG1);
1808 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
1809 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
1810 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
1811 + (bank1AC ? (1 << (bank1AC+1)) : 0);
1812 + memsize <<= 20;
1813 + add_memory_region(0, memsize, BOOT_MEM_RAM);
1814 + iounmap(sdram_base);
1815 +
1816 + ar5312_rst_base = ioremap_nocache(AR5312_RST_BASE, AR5312_RST_SIZE);
1817 +
1818 + devid = ar5312_rst_reg_read(AR5312_REV);
1819 + devid >>= AR5312_REV_WMAC_MIN_S;
1820 + devid &= AR5312_REV_CHIP;
1821 + ath25_board.devid = (u16)devid;
1822 +
1823 + /* Clear any lingering AHB errors */
1824 + ar5312_rst_reg_read(AR5312_PROCADDR);
1825 + ar5312_rst_reg_read(AR5312_DMAADDR);
1826 + ar5312_rst_reg_write(AR5312_WD_CTRL, AR5312_WD_CTRL_IGNORE_EXPIRATION);
1827 +
1828 + _machine_restart = ar5312_restart;
1829 +}
1830 +
1831 +void __init ar5312_arch_init(void)
1832 +{
1833 + ath25_serial_setup(AR5312_UART0, AR5312_MISC_IRQ_UART0,
1834 + ar5312_sys_frequency());
1835 +}
1836 --- /dev/null
1837 +++ b/arch/mips/ath25/ar2315.c
1838 @@ -0,0 +1,418 @@
1839 +/*
1840 + * This file is subject to the terms and conditions of the GNU General Public
1841 + * License. See the file "COPYING" in the main directory of this archive
1842 + * for more details.
1843 + *
1844 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1845 + * Copyright (C) 2006 FON Technology, SL.
1846 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1847 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1848 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1849 + */
1850 +
1851 +/*
1852 + * Platform devices for Atheros SoCs
1853 + */
1854 +
1855 +#include <generated/autoconf.h>
1856 +#include <linux/init.h>
1857 +#include <linux/module.h>
1858 +#include <linux/types.h>
1859 +#include <linux/string.h>
1860 +#include <linux/platform_device.h>
1861 +#include <linux/kernel.h>
1862 +#include <linux/reboot.h>
1863 +#include <linux/delay.h>
1864 +#include <linux/leds.h>
1865 +#include <linux/gpio.h>
1866 +#include <asm/bootinfo.h>
1867 +#include <asm/reboot.h>
1868 +#include <asm/time.h>
1869 +#include <linux/irq.h>
1870 +#include <linux/io.h>
1871 +
1872 +#include <ath25_platform.h>
1873 +
1874 +#include "devices.h"
1875 +#include "ar2315.h"
1876 +#include "ar2315_regs.h"
1877 +
1878 +static void __iomem *ar2315_rst_base;
1879 +
1880 +static inline u32 ar2315_rst_reg_read(u32 reg)
1881 +{
1882 + return __raw_readl(ar2315_rst_base + reg);
1883 +}
1884 +
1885 +static inline void ar2315_rst_reg_write(u32 reg, u32 val)
1886 +{
1887 + __raw_writel(val, ar2315_rst_base + reg);
1888 +}
1889 +
1890 +static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val)
1891 +{
1892 + u32 ret = ar2315_rst_reg_read(reg);
1893 +
1894 + ret &= ~mask;
1895 + ret |= val;
1896 + ar2315_rst_reg_write(reg, ret);
1897 +}
1898 +
1899 +static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
1900 +{
1901 + ar2315_rst_reg_write(AR2315_AHB_ERR0, AHB_ERROR_DET);
1902 + ar2315_rst_reg_read(AR2315_AHB_ERR1);
1903 +
1904 + pr_emerg("AHB fatal error\n");
1905 + machine_restart("AHB error"); /* Catastrophic failure */
1906 +
1907 + return IRQ_HANDLED;
1908 +}
1909 +
1910 +static struct irqaction ar2315_ahb_err_interrupt = {
1911 + .handler = ar2315_ahb_err_handler,
1912 + .name = "ar2315-ahb-error",
1913 +};
1914 +
1915 +static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1916 +{
1917 + unsigned int misc_intr = ar2315_rst_reg_read(AR2315_ISR) &
1918 + ar2315_rst_reg_read(AR2315_IMR);
1919 +
1920 + if (misc_intr & AR2315_ISR_SPI)
1921 + generic_handle_irq(AR2315_MISC_IRQ_SPI);
1922 + else if (misc_intr & AR2315_ISR_TIMER)
1923 + generic_handle_irq(AR2315_MISC_IRQ_TIMER);
1924 + else if (misc_intr & AR2315_ISR_AHB)
1925 + generic_handle_irq(AR2315_MISC_IRQ_AHB);
1926 + else if (misc_intr & AR2315_ISR_GPIO) {
1927 + ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO);
1928 + generic_handle_irq(AR2315_MISC_IRQ_GPIO);
1929 + } else if (misc_intr & AR2315_ISR_UART0)
1930 + generic_handle_irq(AR2315_MISC_IRQ_UART0);
1931 + else if (misc_intr & AR2315_ISR_WD) {
1932 + ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD);
1933 + generic_handle_irq(AR2315_MISC_IRQ_WATCHDOG);
1934 + } else
1935 + spurious_interrupt();
1936 +}
1937 +
1938 +static void ar2315_misc_irq_unmask(struct irq_data *d)
1939 +{
1940 + unsigned int imr;
1941 +
1942 + imr = ar2315_rst_reg_read(AR2315_IMR);
1943 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
1944 + ar2315_rst_reg_write(AR2315_IMR, imr);
1945 +}
1946 +
1947 +static void ar2315_misc_irq_mask(struct irq_data *d)
1948 +{
1949 + unsigned int imr;
1950 +
1951 + imr = ar2315_rst_reg_read(AR2315_IMR);
1952 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
1953 + ar2315_rst_reg_write(AR2315_IMR, imr);
1954 +}
1955 +
1956 +static struct irq_chip ar2315_misc_irq_chip = {
1957 + .name = "ar2315-misc",
1958 + .irq_unmask = ar2315_misc_irq_unmask,
1959 + .irq_mask = ar2315_misc_irq_mask,
1960 +};
1961 +
1962 +/*
1963 + * Called when an interrupt is received, this function
1964 + * determines exactly which interrupt it was, and it
1965 + * invokes the appropriate handler.
1966 + *
1967 + * Implicitly, we also define interrupt priority by
1968 + * choosing which to dispatch first.
1969 + */
1970 +static void ar2315_irq_dispatch(void)
1971 +{
1972 + int pending = read_c0_status() & read_c0_cause();
1973 +
1974 + if (pending & CAUSEF_IP3)
1975 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
1976 + else if (pending & CAUSEF_IP4)
1977 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
1978 + else if (pending & CAUSEF_IP2)
1979 + do_IRQ(AR2315_IRQ_MISC_INTRS);
1980 + else if (pending & CAUSEF_IP7)
1981 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
1982 + else
1983 + spurious_interrupt();
1984 +}
1985 +
1986 +void __init ar2315_arch_init_irq(void)
1987 +{
1988 + int i;
1989 +
1990 + ath25_irq_dispatch = ar2315_irq_dispatch;
1991 + for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
1992 + int irq = AR231X_MISC_IRQ_BASE + i;
1993 +
1994 + irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
1995 + handle_level_irq);
1996 + }
1997 + setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_err_interrupt);
1998 + irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
1999 +}
2000 +
2001 +static void ar2315_device_reset_set(u32 mask)
2002 +{
2003 + u32 val;
2004 +
2005 + val = ar2315_rst_reg_read(AR2315_RESET);
2006 + ar2315_rst_reg_write(AR2315_RESET, val | mask);
2007 +}
2008 +
2009 +static void ar2315_device_reset_clear(u32 mask)
2010 +{
2011 + u32 val;
2012 +
2013 + val = ar2315_rst_reg_read(AR2315_RESET);
2014 + ar2315_rst_reg_write(AR2315_RESET, val & ~mask);
2015 +}
2016 +
2017 +static struct ar231x_eth ar2315_eth_data = {
2018 + .reset_set = ar2315_device_reset_set,
2019 + .reset_clear = ar2315_device_reset_clear,
2020 + .reset_mac = AR2315_RESET_ENET0,
2021 + .reset_phy = AR2315_RESET_EPHY0,
2022 +};
2023 +
2024 +static struct resource ar2315_spiflash_res[] = {
2025 + {
2026 + .name = "spiflash_read",
2027 + .flags = IORESOURCE_MEM,
2028 + .start = AR2315_SPI_READ_BASE,
2029 + .end = AR2315_SPI_READ_BASE + AR2315_SPI_READ_SIZE - 1,
2030 + },
2031 + {
2032 + .name = "spiflash_mmr",
2033 + .flags = IORESOURCE_MEM,
2034 + .start = AR2315_SPI_MMR,
2035 + .end = AR2315_SPI_MMR + 12 - 1,
2036 + },
2037 +};
2038 +
2039 +static struct platform_device ar2315_spiflash = {
2040 + .id = 0,
2041 + .name = "ar2315-spiflash",
2042 + .resource = ar2315_spiflash_res,
2043 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2044 +};
2045 +
2046 +static struct resource ar2315_wdt_res[] = {
2047 + {
2048 + .flags = IORESOURCE_MEM,
2049 + .start = AR2315_RST_BASE + AR2315_WD,
2050 + .end = AR2315_RST_BASE + AR2315_WD + 8 - 1,
2051 + },
2052 + {
2053 + .flags = IORESOURCE_IRQ,
2054 + .start = AR2315_MISC_IRQ_WATCHDOG,
2055 + .end = AR2315_MISC_IRQ_WATCHDOG,
2056 + }
2057 +};
2058 +
2059 +static struct platform_device ar2315_wdt = {
2060 + .id = 0,
2061 + .name = "ar2315-wdt",
2062 + .resource = ar2315_wdt_res,
2063 + .num_resources = ARRAY_SIZE(ar2315_wdt_res)
2064 +};
2065 +
2066 +#ifdef CONFIG_LEDS_GPIO
2067 +static struct gpio_led ar2315_leds[6];
2068 +static struct gpio_led_platform_data ar2315_led_data = {
2069 + .leds = (void *)ar2315_leds,
2070 +};
2071 +
2072 +static struct platform_device ar2315_gpio_leds = {
2073 + .name = "leds-gpio",
2074 + .id = -1,
2075 + .dev = {
2076 + .platform_data = (void *)&ar2315_led_data,
2077 + }
2078 +};
2079 +
2080 +static void __init ar2315_init_gpio_leds(void)
2081 +{
2082 + static char led_names[6][6];
2083 + int i, led = 0;
2084 +
2085 + ar2315_led_data.num_leds = 0;
2086 + for (i = 1; i < 8; i++) {
2087 + if ((i == AR2315_RESET_GPIO) ||
2088 + (i == ath25_board.config->reset_config_gpio))
2089 + continue;
2090 +
2091 + if (i == ath25_board.config->sys_led_gpio)
2092 + strcpy(led_names[led], "wlan");
2093 + else
2094 + sprintf(led_names[led], "gpio%d", i);
2095 +
2096 + ar2315_leds[led].name = led_names[led];
2097 + ar2315_leds[led].gpio = i;
2098 + ar2315_leds[led].active_low = 0;
2099 + led++;
2100 + }
2101 + ar2315_led_data.num_leds = led;
2102 + platform_device_register(&ar2315_gpio_leds);
2103 +}
2104 +#else
2105 +static inline void ar2315_init_gpio_leds(void)
2106 +{
2107 +}
2108 +#endif
2109 +
2110 +void __init ar2315_init_devices(void)
2111 +{
2112 + /* Find board configuration */
2113 + ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE);
2114 + ar2315_eth_data.macaddr = ath25_board.config->enet0_mac;
2115 +
2116 + ar2315_init_gpio_leds();
2117 + platform_device_register(&ar2315_wdt);
2118 + platform_device_register(&ar2315_spiflash);
2119 + ath25_add_ethernet(0, AR2315_ENET0, "eth0_mii", AR2315_ENET0_MII,
2120 + AR2315_IRQ_ENET0_INTRS, &ar2315_eth_data);
2121 + ath25_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2122 +}
2123 +
2124 +static void ar2315_restart(char *command)
2125 +{
2126 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
2127 +
2128 + local_irq_disable();
2129 +
2130 + /* try reset the system via reset control */
2131 + ar2315_rst_reg_write(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
2132 +
2133 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
2134 + * a workaround. Give it some time to attempt a gpio based hardware
2135 + * reset (atheros reference design workaround) */
2136 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2137 + mdelay(100);
2138 +
2139 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2140 + * workaround. Attempt to jump to the mips reset location -
2141 + * the boot loader itself might be able to recover the system */
2142 + mips_reset_vec();
2143 +}
2144 +
2145 +/*
2146 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2147 + * to determine the predevisor value.
2148 + */
2149 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2150 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2151 +
2152 +static unsigned __init ar2315_sys_clk(u32 clock_ctl)
2153 +{
2154 + unsigned int pllc_ctrl, cpu_div;
2155 + unsigned int pllc_out, refdiv, fdiv, divby2;
2156 + unsigned int clk_div;
2157 +
2158 + pllc_ctrl = ar2315_rst_reg_read(AR2315_PLLC_CTL);
2159 + refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2160 + refdiv = clockctl1_predivide_table[refdiv];
2161 + fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2162 + divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2163 + divby2 += 1;
2164 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2165 +
2166 + /* clkm input selected */
2167 + switch (clock_ctl & CPUCLK_CLK_SEL_M) {
2168 + case 0:
2169 + case 1:
2170 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
2171 + PLLC_CLKM_DIV_S];
2172 + break;
2173 + case 2:
2174 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
2175 + PLLC_CLKC_DIV_S];
2176 + break;
2177 + default:
2178 + pllc_out = 40000000;
2179 + clk_div = 1;
2180 + break;
2181 + }
2182 +
2183 + cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2184 + cpu_div = cpu_div * 2 ?: 1;
2185 +
2186 + return pllc_out / (clk_div * cpu_div);
2187 +}
2188 +
2189 +static inline unsigned ar2315_cpu_frequency(void)
2190 +{
2191 + return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_CPUCLK));
2192 +}
2193 +
2194 +static inline unsigned ar2315_apb_frequency(void)
2195 +{
2196 + return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_AMBACLK));
2197 +}
2198 +
2199 +void __init ar2315_plat_time_init(void)
2200 +{
2201 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2202 +}
2203 +
2204 +void __init ar2315_plat_mem_setup(void)
2205 +{
2206 + void __iomem *sdram_base;
2207 + u32 memsize, memcfg;
2208 + u32 devid;
2209 + u32 config;
2210 +
2211 + sdram_base = ioremap_nocache(AR2315_SDRAMCTL_BASE,
2212 + AR2315_SDRAMCTL_SIZE);
2213 + memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG);
2214 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2215 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2216 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2217 + memsize <<= 3;
2218 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2219 + iounmap(sdram_base);
2220 +
2221 + ar2315_rst_base = ioremap_nocache(AR2315_RST_BASE, AR2315_RST_SIZE);
2222 +
2223 + /* Detect the hardware based on the device ID */
2224 + devid = ar2315_rst_reg_read(AR2315_SREV) & AR2315_REV_CHIP;
2225 + switch (devid) {
2226 + case 0x91: /* Need to check */
2227 + ath25_soc = ATH25_SOC_AR2318;
2228 + break;
2229 + case 0x90:
2230 + ath25_soc = ATH25_SOC_AR2317;
2231 + break;
2232 + case 0x87:
2233 + ath25_soc = ATH25_SOC_AR2316;
2234 + break;
2235 + case 0x86:
2236 + default:
2237 + ath25_soc = ATH25_SOC_AR2315;
2238 + break;
2239 + }
2240 + ath25_board.devid = devid;
2241 +
2242 + /* Clear any lingering AHB errors */
2243 + config = read_c0_config();
2244 + write_c0_config(config & ~0x3);
2245 + ar2315_rst_reg_write(AR2315_AHB_ERR0, AHB_ERROR_DET);
2246 + ar2315_rst_reg_read(AR2315_AHB_ERR1);
2247 + ar2315_rst_reg_write(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2248 +
2249 + _machine_restart = ar2315_restart;
2250 +}
2251 +
2252 +void __init ar2315_arch_init(void)
2253 +{
2254 + ath25_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
2255 + ar2315_apb_frequency());
2256 +}
2257 --- /dev/null
2258 +++ b/arch/mips/ath25/ar2315.h
2259 @@ -0,0 +1,36 @@
2260 +#ifndef __AR2315_H
2261 +#define __AR2315_H
2262 +
2263 +#ifdef CONFIG_SOC_AR2315
2264 +
2265 +void ar2315_arch_init_irq(void);
2266 +void ar2315_init_devices(void);
2267 +void ar2315_plat_time_init(void);
2268 +void ar2315_plat_mem_setup(void);
2269 +void ar2315_arch_init(void);
2270 +
2271 +#else
2272 +
2273 +static inline void ar2315_arch_init_irq(void)
2274 +{
2275 +}
2276 +
2277 +static inline void ar2315_init_devices(void)
2278 +{
2279 +}
2280 +
2281 +static inline void ar2315_plat_time_init(void)
2282 +{
2283 +}
2284 +
2285 +static inline void ar2315_plat_mem_setup(void)
2286 +{
2287 +}
2288 +
2289 +static inline void ar2315_arch_init(void)
2290 +{
2291 +}
2292 +
2293 +#endif
2294 +
2295 +#endif
2296 --- /dev/null
2297 +++ b/arch/mips/ath25/ar5312.h
2298 @@ -0,0 +1,36 @@
2299 +#ifndef __AR5312_H
2300 +#define __AR5312_H
2301 +
2302 +#ifdef CONFIG_SOC_AR5312
2303 +
2304 +void ar5312_arch_init_irq(void);
2305 +void ar5312_init_devices(void);
2306 +void ar5312_plat_time_init(void);
2307 +void ar5312_plat_mem_setup(void);
2308 +void ar5312_arch_init(void);
2309 +
2310 +#else
2311 +
2312 +static inline void ar5312_arch_init_irq(void)
2313 +{
2314 +}
2315 +
2316 +static inline void ar5312_init_devices(void)
2317 +{
2318 +}
2319 +
2320 +static inline void ar5312_plat_time_init(void)
2321 +{
2322 +}
2323 +
2324 +static inline void ar5312_plat_mem_setup(void)
2325 +{
2326 +}
2327 +
2328 +static inline void ar5312_arch_init(void)
2329 +{
2330 +}
2331 +
2332 +#endif
2333 +
2334 +#endif
2335 --- /dev/null
2336 +++ b/arch/mips/ath25/devices.h
2337 @@ -0,0 +1,44 @@
2338 +#ifndef __ATH25_DEVICES_H
2339 +#define __ATH25_DEVICES_H
2340 +
2341 +#define AR231X_MISC_IRQ_BASE 0x20
2342 +#define AR231X_GPIO_IRQ_BASE 0x30
2343 +
2344 +#define AR231X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */
2345 +
2346 +enum ath25_soc_type {
2347 + /* handled by ar5312.c */
2348 + ATH25_SOC_AR2312,
2349 + ATH25_SOC_AR2313,
2350 + ATH25_SOC_AR5312,
2351 +
2352 + /* handled by ar2315.c */
2353 + ATH25_SOC_AR2315,
2354 + ATH25_SOC_AR2316,
2355 + ATH25_SOC_AR2317,
2356 + ATH25_SOC_AR2318,
2357 +
2358 + ATH25_SOC_UNKNOWN
2359 +};
2360 +
2361 +extern enum ath25_soc_type ath25_soc;
2362 +extern struct ar231x_board_config ath25_board;
2363 +extern void (*ath25_irq_dispatch)(void);
2364 +
2365 +int ath25_find_config(phys_addr_t offset, unsigned long size);
2366 +int ath25_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2367 + int irq, void *pdata);
2368 +void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
2369 +int ath25_add_wmac(int nr, u32 base, int irq);
2370 +
2371 +static inline bool is_ar2315(void)
2372 +{
2373 + return (current_cpu_data.cputype == CPU_4KEC);
2374 +}
2375 +
2376 +static inline bool is_ar5312(void)
2377 +{
2378 + return !is_ar2315();
2379 +}
2380 +
2381 +#endif
2382 --- /dev/null
2383 +++ b/arch/mips/ath25/devices.c
2384 @@ -0,0 +1,191 @@
2385 +#include <linux/kernel.h>
2386 +#include <linux/init.h>
2387 +#include <linux/serial.h>
2388 +#include <linux/serial_core.h>
2389 +#include <linux/serial_8250.h>
2390 +#include <linux/platform_device.h>
2391 +#include <asm/bootinfo.h>
2392 +
2393 +#include <ath25_platform.h>
2394 +#include "devices.h"
2395 +#include "ar5312.h"
2396 +#include "ar2315.h"
2397 +
2398 +struct ar231x_board_config ath25_board;
2399 +enum ath25_soc_type ath25_soc = ATH25_SOC_UNKNOWN;
2400 +
2401 +static struct resource ath25_eth0_res[] = {
2402 + {
2403 + .name = "eth0_membase",
2404 + .flags = IORESOURCE_MEM,
2405 + },
2406 + {
2407 + .name = "eth0_mii",
2408 + .flags = IORESOURCE_MEM,
2409 + },
2410 + {
2411 + .name = "eth0_irq",
2412 + .flags = IORESOURCE_IRQ,
2413 + }
2414 +};
2415 +
2416 +static struct resource ath25_eth1_res[] = {
2417 + {
2418 + .name = "eth1_membase",
2419 + .flags = IORESOURCE_MEM,
2420 + },
2421 + {
2422 + .name = "eth1_mii",
2423 + .flags = IORESOURCE_MEM,
2424 + },
2425 + {
2426 + .name = "eth1_irq",
2427 + .flags = IORESOURCE_IRQ,
2428 + }
2429 +};
2430 +
2431 +static struct platform_device ath25_eth[] = {
2432 + {
2433 + .id = 0,
2434 + .name = "ar231x-eth",
2435 + .resource = ath25_eth0_res,
2436 + .num_resources = ARRAY_SIZE(ath25_eth0_res)
2437 + },
2438 + {
2439 + .id = 1,
2440 + .name = "ar231x-eth",
2441 + .resource = ath25_eth1_res,
2442 + .num_resources = ARRAY_SIZE(ath25_eth1_res)
2443 + }
2444 +};
2445 +
2446 +static struct resource ath25_wmac0_res[] = {
2447 + {
2448 + .name = "wmac0_membase",
2449 + .flags = IORESOURCE_MEM,
2450 + },
2451 + {
2452 + .name = "wmac0_irq",
2453 + .flags = IORESOURCE_IRQ,
2454 + }
2455 +};
2456 +
2457 +static struct resource ath25_wmac1_res[] = {
2458 + {
2459 + .name = "wmac1_membase",
2460 + .flags = IORESOURCE_MEM,
2461 + },
2462 + {
2463 + .name = "wmac1_irq",
2464 + .flags = IORESOURCE_IRQ,
2465 + }
2466 +};
2467 +
2468 +static struct platform_device ath25_wmac[] = {
2469 + {
2470 + .id = 0,
2471 + .name = "ar231x-wmac",
2472 + .resource = ath25_wmac0_res,
2473 + .num_resources = ARRAY_SIZE(ath25_wmac0_res),
2474 + .dev.platform_data = &ath25_board,
2475 + },
2476 + {
2477 + .id = 1,
2478 + .name = "ar231x-wmac",
2479 + .resource = ath25_wmac1_res,
2480 + .num_resources = ARRAY_SIZE(ath25_wmac1_res),
2481 + .dev.platform_data = &ath25_board,
2482 + },
2483 +};
2484 +
2485 +static const char * const soc_type_strings[] = {
2486 + [ATH25_SOC_AR5312] = "Atheros AR5312",
2487 + [ATH25_SOC_AR2312] = "Atheros AR2312",
2488 + [ATH25_SOC_AR2313] = "Atheros AR2313",
2489 + [ATH25_SOC_AR2315] = "Atheros AR2315",
2490 + [ATH25_SOC_AR2316] = "Atheros AR2316",
2491 + [ATH25_SOC_AR2317] = "Atheros AR2317",
2492 + [ATH25_SOC_AR2318] = "Atheros AR2318",
2493 + [ATH25_SOC_UNKNOWN] = "Atheros (unknown)",
2494 +};
2495 +
2496 +const char *get_system_type(void)
2497 +{
2498 + if ((ath25_soc >= ARRAY_SIZE(soc_type_strings)) ||
2499 + !soc_type_strings[ath25_soc])
2500 + return soc_type_strings[ATH25_SOC_UNKNOWN];
2501 + return soc_type_strings[ath25_soc];
2502 +}
2503 +
2504 +int __init ath25_add_ethernet(int nr, u32 base, const char *mii_name,
2505 + u32 mii_base, int irq, void *pdata)
2506 +{
2507 + struct resource *res;
2508 +
2509 + ath25_eth[nr].dev.platform_data = pdata;
2510 + res = &ath25_eth[nr].resource[0];
2511 + res->start = base;
2512 + res->end = base + 0x2000 - 1;
2513 + res++;
2514 + res->name = mii_name;
2515 + res->start = mii_base;
2516 + res->end = mii_base + 8 - 1;
2517 + res++;
2518 + res->start = irq;
2519 + res->end = irq;
2520 + return platform_device_register(&ath25_eth[nr]);
2521 +}
2522 +
2523 +void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
2524 +{
2525 + struct uart_port s;
2526 +
2527 + memset(&s, 0, sizeof(s));
2528 +
2529 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
2530 + s.iotype = UPIO_MEM32;
2531 + s.irq = irq;
2532 + s.regshift = 2;
2533 + s.mapbase = mapbase;
2534 + s.uartclk = uartclk;
2535 +
2536 + early_serial_setup(&s);
2537 +}
2538 +
2539 +int __init ath25_add_wmac(int nr, u32 base, int irq)
2540 +{
2541 + struct resource *res;
2542 +
2543 + ath25_wmac[nr].dev.platform_data = &ath25_board;
2544 + res = &ath25_wmac[nr].resource[0];
2545 + res->start = base;
2546 + res->end = base + 0x10000 - 1;
2547 + res++;
2548 + res->start = irq;
2549 + res->end = irq;
2550 + return platform_device_register(&ath25_wmac[nr]);
2551 +}
2552 +
2553 +static int __init ath25_register_devices(void)
2554 +{
2555 + if (is_ar5312())
2556 + ar5312_init_devices();
2557 + else
2558 + ar2315_init_devices();
2559 +
2560 + return 0;
2561 +}
2562 +
2563 +device_initcall(ath25_register_devices);
2564 +
2565 +static int __init ath25_arch_init(void)
2566 +{
2567 + if (is_ar5312())
2568 + ar5312_arch_init();
2569 + else
2570 + ar2315_arch_init();
2571 +
2572 + return 0;
2573 +}
2574 +
2575 +arch_initcall(ath25_arch_init);
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