1 #ifndef LINUX_SSB_CHIPCO_H_
2 #define LINUX_SSB_CHIPCO_H_
4 /* SonicsSiliconBackplane CHIPCOMMON core hardware definitions
6 * The chipcommon core provides chip identification, SB control,
7 * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
8 * gpio interface, extbus, and support for serial and parallel flashes.
10 * Copyright 2005, Broadcom Corporation
11 * Copyright 2006, Michael Buesch <mb@bu3sch.de>
13 * Licensed under the GPL version 2. See COPYING for details.
16 /** ChipCommon core registers. **/
18 #define SSB_CHIPCO_CHIPID 0x0000
19 #define SSB_CHIPCO_IDMASK 0x0000FFFF
20 #define SSB_CHIPCO_REVMASK 0x000F0000
21 #define SSB_CHIPCO_REVSHIFT 16
22 #define SSB_CHIPCO_PACKMASK 0x00F00000
23 #define SSB_CHIPCO_PACKSHIFT 20
24 #define SSB_CHIPCO_NRCORESMASK 0x0F000000
25 #define SSB_CHIPCO_NRCORESSHIFT 24
26 #define SSB_CHIPCO_CAP 0x0004 /* Capabilities */
27 #define SSB_CHIPCO_CAP_NRUART 0x00000003 /* # of UARTs */
28 #define SSB_CHIPCO_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
29 #define SSB_CHIPCO_CAP_UARTCLK 0x00000018 /* UART clock select */
30 #define SSB_CHIPCO_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */
31 #define SSB_CHIPCO_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
32 #define SSB_CHIPCO_CAP_EXTBUS 0x000000C0 /* External buses present */
33 #define SSB_CHIPCO_CAP_FLASHT 0x00000700 /* Flash Type */
34 #define SSB_CHIPCO_FLASHT_NONE 0x00000000 /* No flash */
35 #define SSB_CHIPCO_FLASHT_STSER 0x00000100 /* ST serial flash */
36 #define SSB_CHIPCO_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
37 #define SSB_CHIPCO_FLASHT_PARA 0x00000700 /* Parallel flash */
38 #define SSB_CHIPCO_CAP_PLLT 0x00038000 /* PLL Type */
39 #define SSB_PLLTYPE_NONE 0x00000000
40 #define SSB_PLLTYPE_1 0x00010000 /* 48Mhz base, 3 dividers */
41 #define SSB_PLLTYPE_2 0x00020000 /* 48Mhz, 4 dividers */
42 #define SSB_PLLTYPE_3 0x00030000 /* 25Mhz, 2 dividers */
43 #define SSB_PLLTYPE_4 0x00008000 /* 48Mhz, 4 dividers */
44 #define SSB_PLLTYPE_5 0x00018000 /* 25Mhz, 4 dividers */
45 #define SSB_PLLTYPE_6 0x00028000 /* 100/200 or 120/240 only */
46 #define SSB_PLLTYPE_7 0x00038000 /* 25Mhz, 4 dividers */
47 #define SSB_CHIPCO_CAP_PCTL 0x00040000 /* Power Control */
48 #define SSB_CHIPCO_CAP_OTPS 0x00380000 /* OTP size */
49 #define SSB_CHIPCO_CAP_OTPS_SHIFT 19
50 #define SSB_CHIPCO_CAP_OTPS_BASE 5
51 #define SSB_CHIPCO_CAP_JTAGM 0x00400000 /* JTAG master present */
52 #define SSB_CHIPCO_CAP_BROM 0x00800000 /* Internal boot ROM active */
53 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
54 #define SSB_CHIPCO_CORECTL 0x0008
55 #define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
56 #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
57 #define SSB_CHIPCO_BIST 0x000C
58 #define SSB_CHIPCO_OTPS 0x0010 /* OTP status */
59 #define SSB_CHIPCO_OTPS_PROGFAIL 0x80000000
60 #define SSB_CHIPCO_OTPS_PROTECT 0x00000007
61 #define SSB_CHIPCO_OTPS_HW_PROTECT 0x00000001
62 #define SSB_CHIPCO_OTPS_SW_PROTECT 0x00000002
63 #define SSB_CHIPCO_OTPS_CID_PROTECT 0x00000004
64 #define SSB_CHIPCO_OTPC 0x0014 /* OTP control */
65 #define SSB_CHIPCO_OTPC_RECWAIT 0xFF000000
66 #define SSB_CHIPCO_OTPC_PROGWAIT 0x00FFFF00
67 #define SSB_CHIPCO_OTPC_PRW_SHIFT 8
68 #define SSB_CHIPCO_OTPC_MAXFAIL 0x00000038
69 #define SSB_CHIPCO_OTPC_VSEL 0x00000006
70 #define SSB_CHIPCO_OTPC_SELVL 0x00000001
71 #define SSB_CHIPCO_OTPP 0x0018 /* OTP prog */
72 #define SSB_CHIPCO_OTPP_COL 0x000000FF
73 #define SSB_CHIPCO_OTPP_ROW 0x0000FF00
74 #define SSB_CHIPCO_OTPP_ROW_SHIFT 8
75 #define SSB_CHIPCO_OTPP_READERR 0x10000000
76 #define SSB_CHIPCO_OTPP_VALUE 0x20000000
77 #define SSB_CHIPCO_OTPP_READ 0x40000000
78 #define SSB_CHIPCO_OTPP_START 0x80000000
79 #define SSB_CHIPCO_OTPP_BUSY 0x80000000
80 #define SSB_CHIPCO_IRQSTAT 0x0020
81 #define SSB_CHIPCO_IRQMASK 0x0024
82 #define SSB_CHIPCO_IRQ_GPIO 0x00000001 /* gpio intr */
83 #define SSB_CHIPCO_IRQ_EXT 0x00000002 /* ro: ext intr pin (corerev >= 3) */
84 #define SSB_CHIPCO_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */
85 #define SSB_CHIPCO_CHIPCTL 0x0028 /* Rev >= 11 only */
86 #define SSB_CHIPCO_CHIPSTAT 0x002C /* Rev >= 11 only */
87 #define SSB_CHIPCO_JCMD 0x0030 /* Rev >= 10 only */
88 #define SSB_CHIPCO_JCMD_START 0x80000000
89 #define SSB_CHIPCO_JCMD_BUSY 0x80000000
90 #define SSB_CHIPCO_JCMD_PAUSE 0x40000000
91 #define SSB_CHIPCO_JCMD0_ACC_MASK 0x0000F000
92 #define SSB_CHIPCO_JCMD0_ACC_IRDR 0x00000000
93 #define SSB_CHIPCO_JCMD0_ACC_DR 0x00001000
94 #define SSB_CHIPCO_JCMD0_ACC_IR 0x00002000
95 #define SSB_CHIPCO_JCMD0_ACC_RESET 0x00003000
96 #define SSB_CHIPCO_JCMD0_ACC_IRPDR 0x00004000
97 #define SSB_CHIPCO_JCMD0_ACC_PDR 0x00005000
98 #define SSB_CHIPCO_JCMD0_IRW_MASK 0x00000F00
99 #define SSB_CHIPCO_JCMD_ACC_MASK 0x000F0000 /* Changes for corerev 11 */
100 #define SSB_CHIPCO_JCMD_ACC_IRDR 0x00000000
101 #define SSB_CHIPCO_JCMD_ACC_DR 0x00010000
102 #define SSB_CHIPCO_JCMD_ACC_IR 0x00020000
103 #define SSB_CHIPCO_JCMD_ACC_RESET 0x00030000
104 #define SSB_CHIPCO_JCMD_ACC_IRPDR 0x00040000
105 #define SSB_CHIPCO_JCMD_ACC_PDR 0x00050000
106 #define SSB_CHIPCO_JCMD_IRW_MASK 0x00001F00
107 #define SSB_CHIPCO_JCMD_IRW_SHIFT 8
108 #define SSB_CHIPCO_JCMD_DRW_MASK 0x0000003F
109 #define SSB_CHIPCO_JIR 0x0034 /* Rev >= 10 only */
110 #define SSB_CHIPCO_JDR 0x0038 /* Rev >= 10 only */
111 #define SSB_CHIPCO_JCTL 0x003C /* Rev >= 10 only */
112 #define SSB_CHIPCO_JCTL_FORCE_CLK 4 /* Force clock */
113 #define SSB_CHIPCO_JCTL_EXT_EN 2 /* Enable external targets */
114 #define SSB_CHIPCO_JCTL_EN 1 /* Enable Jtag master */
115 #define SSB_CHIPCO_FLASHCTL 0x0040
116 #define SSB_CHIPCO_FLASHCTL_START 0x80000000
117 #define SSB_CHIPCO_FLASHCTL_BUSY SSB_CHIPCO_FLASHCTL_START
118 #define SSB_CHIPCO_FLASHADDR 0x0044
119 #define SSB_CHIPCO_FLASHDATA 0x0048
120 #define SSB_CHIPCO_BCAST_ADDR 0x0050
121 #define SSB_CHIPCO_BCAST_DATA 0x0054
122 #define SSB_CHIPCO_GPIOIN 0x0060
123 #define SSB_CHIPCO_GPIOOUT 0x0064
124 #define SSB_CHIPCO_GPIOOUTEN 0x0068
125 #define SSB_CHIPCO_GPIOCTL 0x006C
126 #define SSB_CHIPCO_GPIOPOL 0x0070
127 #define SSB_CHIPCO_GPIOIRQ 0x0074
128 #define SSB_CHIPCO_WATCHDOG 0x0080
129 #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
130 #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16
131 #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
132 #define SSB_CHIPCO_CLOCK_N 0x0090
133 #define SSB_CHIPCO_CLOCK_SB 0x0094
134 #define SSB_CHIPCO_CLOCK_PCI 0x0098
135 #define SSB_CHIPCO_CLOCK_M2 0x009C
136 #define SSB_CHIPCO_CLOCK_MIPS 0x00A0
137 #define SSB_CHIPCO_CLKDIV 0x00A4 /* Rev >= 3 only */
138 #define SSB_CHIPCO_CLKDIV_SFLASH 0x0F000000
139 #define SSB_CHIPCO_CLKDIV_SFLASH_SHIFT 24
140 #define SSB_CHIPCO_CLKDIV_OTP 0x000F0000
141 #define SSB_CHIPCO_CLKDIV_OTP_SHIFT 16
142 #define SSB_CHIPCO_CLKDIV_JTAG 0x00000F00
143 #define SSB_CHIPCO_CLKDIV_JTAG_SHIFT 8
144 #define SSB_CHIPCO_CLKDIV_UART 0x000000FF
145 #define SSB_CHIPCO_PLLONDELAY 0x00B0 /* Rev >= 4 only */
146 #define SSB_CHIPCO_FREFSELDELAY 0x00B4 /* Rev >= 4 only */
147 #define SSB_CHIPCO_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */
148 #define SSB_CHIPCO_SLOWCLKCTL_SRC 0x00000007 /* slow clock source mask */
149 #define SSB_CHIPCO_SLOWCLKCTL_SRC_LPO 0x00000000 /* source of slow clock is LPO */
150 #define SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL 0x00000001 /* source of slow clock is crystal */
151 #define SSB_CHIPCO_SLOECLKCTL_SRC_PCI 0x00000002 /* source of slow clock is PCI */
152 #define SSB_CHIPCO_SLOWCLKCTL_LPOFREQ 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
153 #define SSB_CHIPCO_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
154 #define SSB_CHIPCO_SLOWCLKCTL_FSLOW 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
155 #define SSB_CHIPCO_SLOWCLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
156 #define SSB_CHIPCO_SLOWCLKCTL_ENXTAL 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
157 #define SSB_CHIPCO_SLOWCLKCTL_XTALPU 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
158 #define SSB_CHIPCO_SLOWCLKCTL_CLKDIV 0xFFFF0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
159 #define SSB_CHIPCO_SLOWCLKCTL_CLKDIV_SHIFT 16
160 #define SSB_CHIPCO_SYSCLKCTL 0x00C0 /* Rev >= 3 only */
161 #define SSB_CHIPCO_SYSCLKCTL_IDLPEN 0x00000001 /* ILPen: Enable Idle Low Power */
162 #define SSB_CHIPCO_SYSCLKCTL_ALPEN 0x00000002 /* ALPen: Enable Active Low Power */
163 #define SSB_CHIPCO_SYSCLKCTL_PLLEN 0x00000004 /* ForcePLLOn */
164 #define SSB_CHIPCO_SYSCLKCTL_FORCEALP 0x00000008 /* Force ALP (or HT if ALPen is not set */
165 #define SSB_CHIPCO_SYSCLKCTL_FORCEHT 0x00000010 /* Force HT */
166 #define SSB_CHIPCO_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */
167 #define SSB_CHIPCO_SYSCLKCTL_CLKDIV_SHIFT 16
168 #define SSB_CHIPCO_CLKSTSTR 0x00C4 /* Rev >= 3 only */
169 #define SSB_CHIPCO_PCMCIA_CFG 0x0100
170 #define SSB_CHIPCO_PCMCIA_MEMWAIT 0x0104
171 #define SSB_CHIPCO_PCMCIA_ATTRWAIT 0x0108
172 #define SSB_CHIPCO_PCMCIA_IOWAIT 0x010C
173 #define SSB_CHIPCO_IDE_CFG 0x0110
174 #define SSB_CHIPCO_IDE_MEMWAIT 0x0114
175 #define SSB_CHIPCO_IDE_ATTRWAIT 0x0118
176 #define SSB_CHIPCO_IDE_IOWAIT 0x011C
177 #define SSB_CHIPCO_PROG_CFG 0x0120
178 #define SSB_CHIPCO_PROG_WAITCNT 0x0124
179 #define SSB_CHIPCO_FLASH_CFG 0x0128
180 #define SSB_CHIPCO_FLASH_WAITCNT 0x012C
181 #define SSB_CHIPCO_UART0_DATA 0x0300
182 #define SSB_CHIPCO_UART0_IMR 0x0304
183 #define SSB_CHIPCO_UART0_FCR 0x0308
184 #define SSB_CHIPCO_UART0_LCR 0x030C
185 #define SSB_CHIPCO_UART0_MCR 0x0310
186 #define SSB_CHIPCO_UART0_LSR 0x0314
187 #define SSB_CHIPCO_UART0_MSR 0x0318
188 #define SSB_CHIPCO_UART0_SCRATCH 0x031C
189 #define SSB_CHIPCO_UART1_DATA 0x0400
190 #define SSB_CHIPCO_UART1_IMR 0x0404
191 #define SSB_CHIPCO_UART1_FCR 0x0408
192 #define SSB_CHIPCO_UART1_LCR 0x040C
193 #define SSB_CHIPCO_UART1_MCR 0x0410
194 #define SSB_CHIPCO_UART1_LSR 0x0414
195 #define SSB_CHIPCO_UART1_MSR 0x0418
196 #define SSB_CHIPCO_UART1_SCRATCH 0x041C
200 /** Clockcontrol masks and values **/
202 /* SSB_CHIPCO_CLOCK_N */
203 #define SSB_CHIPCO_CLK_N1 0x0000003F /* n1 control */
204 #define SSB_CHIPCO_CLK_N2 0x00003F00 /* n2 control */
205 #define SSB_CHIPCO_CLK_N2_SHIFT 8
206 #define SSB_CHIPCO_CLK_PLLC 0x000F0000 /* pll control */
207 #define SSB_CHIPCO_CLK_PLLC_SHIFT 16
209 /* SSB_CHIPCO_CLOCK_SB/PCI/UART */
210 #define SSB_CHIPCO_CLK_M1 0x0000003F /* m1 control */
211 #define SSB_CHIPCO_CLK_M2 0x00003F00 /* m2 control */
212 #define SSB_CHIPCO_CLK_M2_SHIFT 8
213 #define SSB_CHIPCO_CLK_M3 0x003F0000 /* m3 control */
214 #define SSB_CHIPCO_CLK_M3_SHIFT 16
215 #define SSB_CHIPCO_CLK_MC 0x1F000000 /* mux control */
216 #define SSB_CHIPCO_CLK_MC_SHIFT 24
218 /* N3M Clock control magic field values */
219 #define SSB_CHIPCO_CLK_F6_2 0x02 /* A factor of 2 in */
220 #define SSB_CHIPCO_CLK_F6_3 0x03 /* 6-bit fields like */
221 #define SSB_CHIPCO_CLK_F6_4 0x05 /* N1, M1 or M3 */
222 #define SSB_CHIPCO_CLK_F6_5 0x09
223 #define SSB_CHIPCO_CLK_F6_6 0x11
224 #define SSB_CHIPCO_CLK_F6_7 0x21
226 #define SSB_CHIPCO_CLK_F5_BIAS 5 /* 5-bit fields get this added */
228 #define SSB_CHIPCO_CLK_MC_BYPASS 0x08
229 #define SSB_CHIPCO_CLK_MC_M1 0x04
230 #define SSB_CHIPCO_CLK_MC_M1M2 0x02
231 #define SSB_CHIPCO_CLK_MC_M1M2M3 0x01
232 #define SSB_CHIPCO_CLK_MC_M1M3 0x11
234 /* Type 2 Clock control magic field values */
235 #define SSB_CHIPCO_CLK_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
236 #define SSB_CHIPCO_CLK_T2M2_BIAS 3 /* m2 bias */
238 #define SSB_CHIPCO_CLK_T2MC_M1BYP 1
239 #define SSB_CHIPCO_CLK_T2MC_M2BYP 2
240 #define SSB_CHIPCO_CLK_T2MC_M3BYP 4
242 /* Type 6 Clock control magic field values */
243 #define SSB_CHIPCO_CLK_T6_MMASK 1 /* bits of interest in m */
244 #define SSB_CHIPCO_CLK_T6_M0 120000000 /* sb clock for m = 0 */
245 #define SSB_CHIPCO_CLK_T6_M1 100000000 /* sb clock for m = 1 */
246 #define SSB_CHIPCO_CLK_SB2MIPS_T6(sb) (2 * (sb))
248 /* Common clock base */
249 #define SSB_CHIPCO_CLK_BASE1 24000000 /* Half the clock freq */
250 #define SSB_CHIPCO_CLK_BASE2 12500000 /* Alternate crystal on some PLL's */
252 /* Clock control values for 200Mhz in 5350 */
253 #define SSB_CHIPCO_CLK_5350_N 0x0311
254 #define SSB_CHIPCO_CLK_5350_M 0x04020009
257 /** Bits in the config registers **/
259 #define SSB_CHIPCO_CFG_EN 0x0001 /* Enable */
260 #define SSB_CHIPCO_CFG_EXTM 0x000E /* Extif Mode */
261 #define SSB_CHIPCO_CFG_EXTM_ASYNC 0x0002 /* Async/Parallel flash */
262 #define SSB_CHIPCO_CFG_EXTM_SYNC 0x0004 /* Synchronous */
263 #define SSB_CHIPCO_CFG_EXTM_PCMCIA 0x0008 /* PCMCIA */
264 #define SSB_CHIPCO_CFG_EXTM_IDE 0x000A /* IDE */
265 #define SSB_CHIPCO_CFG_DS16 0x0010 /* Data size, 0=8bit, 1=16bit */
266 #define SSB_CHIPCO_CFG_CLKDIV 0x0060 /* Sync: Clock divisor */
267 #define SSB_CHIPCO_CFG_CLKEN 0x0080 /* Sync: Clock enable */
268 #define SSB_CHIPCO_CFG_BSTRO 0x0100 /* Sync: Size/Bytestrobe */
271 /** Flash-specific control/status values */
273 /* flashcontrol opcodes for ST flashes */
274 #define SSB_CHIPCO_FLASHCTL_ST_WREN 0x0006 /* Write Enable */
275 #define SSB_CHIPCO_FLASHCTL_ST_WRDIS 0x0004 /* Write Disable */
276 #define SSB_CHIPCO_FLASHCTL_ST_RDSR 0x0105 /* Read Status Register */
277 #define SSB_CHIPCO_FLASHCTL_ST_WRSR 0x0101 /* Write Status Register */
278 #define SSB_CHIPCO_FLASHCTL_ST_READ 0x0303 /* Read Data Bytes */
279 #define SSB_CHIPCO_FLASHCTL_ST_PP 0x0302 /* Page Program */
280 #define SSB_CHIPCO_FLASHCTL_ST_SE 0x02D8 /* Sector Erase */
281 #define SSB_CHIPCO_FLASHCTL_ST_BE 0x00C7 /* Bulk Erase */
282 #define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */
283 #define SSB_CHIPCO_FLASHCTL_ST_RSIG 0x03AB /* Read Electronic Signature */
285 /* Status register bits for ST flashes */
286 #define SSB_CHIPCO_FLASHSTA_ST_WIP 0x01 /* Write In Progress */
287 #define SSB_CHIPCO_FLASHSTA_ST_WEL 0x02 /* Write Enable Latch */
288 #define SSB_CHIPCO_FLASHSTA_ST_BP 0x1C /* Block Protect */
289 #define SSB_CHIPCO_FLASHSTA_ST_BP_SHIFT 2
290 #define SSB_CHIPCO_FLASHSTA_ST_SRWD 0x80 /* Status Register Write Disable */
292 /* flashcontrol opcodes for Atmel flashes */
293 #define SSB_CHIPCO_FLASHCTL_AT_READ 0x07E8
294 #define SSB_CHIPCO_FLASHCTL_AT_PAGE_READ 0x07D2
295 #define SSB_CHIPCO_FLASHCTL_AT_BUF1_READ /* FIXME */
296 #define SSB_CHIPCO_FLASHCTL_AT_BUF2_READ /* FIXME */
297 #define SSB_CHIPCO_FLASHCTL_AT_STATUS 0x01D7
298 #define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRITE 0x0384
299 #define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRITE 0x0387
300 #define SSB_CHIPCO_FLASHCTL_AT_BUF1_ERASE_PRGM 0x0283 /* Erase program */
301 #define SSB_CHIPCO_FLASHCTL_AT_BUF2_ERASE_PRGM 0x0286 /* Erase program */
302 #define SSB_CHIPCO_FLASHCTL_AT_BUF1_PROGRAM 0x0288
303 #define SSB_CHIPCO_FLASHCTL_AT_BUF2_PROGRAM 0x0289
304 #define SSB_CHIPCO_FLASHCTL_AT_PAGE_ERASE 0x0281
305 #define SSB_CHIPCO_FLASHCTL_AT_BLOCK_ERASE 0x0250
306 #define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRER_PRGM 0x0382 /* Write erase program */
307 #define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRER_PRGM 0x0385 /* Write erase program */
308 #define SSB_CHIPCO_FLASHCTL_AT_BUF1_LOAD 0x0253
309 #define SSB_CHIPCO_FLASHCTL_AT_BUF2_LOAD 0x0255
310 #define SSB_CHIPCO_FLASHCTL_AT_BUF1_COMPARE 0x0260
311 #define SSB_CHIPCO_FLASHCTL_AT_BUF2_COMPARE 0x0261
312 #define SSB_CHIPCO_FLASHCTL_AT_BUF1_REPROGRAM 0x0258
313 #define SSB_CHIPCO_FLASHCTL_AT_BUF2_REPROGRAM 0x0259
315 /* Status register bits for Atmel flashes */
316 #define SSB_CHIPCO_FLASHSTA_AT_READY 0x80
317 #define SSB_CHIPCO_FLASHSTA_AT_MISMATCH 0x40
318 #define SSB_CHIPCO_FLASHSTA_AT_ID 0x38
319 #define SSB_CHIPCO_FLASHSTA_AT_ID_SHIFT 3
325 #define SSB_CHIPCO_OTP_HW_REGION SSB_CHIPCO_OTPS_HW_PROTECT
326 #define SSB_CHIPCO_OTP_SW_REGION SSB_CHIPCO_OTPS_SW_PROTECT
327 #define SSB_CHIPCO_OTP_CID_REGION SSB_CHIPCO_OTPS_CID_PROTECT
329 /* OTP regions (Byte offsets from otp size) */
330 #define SSB_CHIPCO_OTP_SWLIM_OFF (-8)
331 #define SSB_CHIPCO_OTP_CIDBASE_OFF 0
332 #define SSB_CHIPCO_OTP_CIDLIM_OFF 8
334 /* Predefined OTP words (Word offset from otp size) */
335 #define SSB_CHIPCO_OTP_BOUNDARY_OFF (-4)
336 #define SSB_CHIPCO_OTP_HWSIGN_OFF (-3)
337 #define SSB_CHIPCO_OTP_SWSIGN_OFF (-2)
338 #define SSB_CHIPCO_OTP_CIDSIGN_OFF (-1)
340 #define SSB_CHIPCO_OTP_CID_OFF 0
341 #define SSB_CHIPCO_OTP_PKG_OFF 1
342 #define SSB_CHIPCO_OTP_FID_OFF 2
343 #define SSB_CHIPCO_OTP_RSV_OFF 3
344 #define SSB_CHIPCO_OTP_LIM_OFF 4
346 #define SSB_CHIPCO_OTP_SIGNATURE 0x578A
347 #define SSB_CHIPCO_OTP_MAGIC 0x4E56
351 struct ssb_serial_port
;
353 struct ssb_chipcommon
{
354 struct ssb_device
*dev
;
356 /* Fast Powerup Delay constant */
357 u16 fast_pwrup_delay
;
360 extern void ssb_chipcommon_init(struct ssb_chipcommon
*cc
);
362 #include <linux/pm.h>
363 extern void ssb_chipco_suspend(struct ssb_chipcommon
*cc
, pm_message_t state
);
364 extern void ssb_chipco_resume(struct ssb_chipcommon
*cc
);
366 extern void ssb_chipco_get_clockcpu(struct ssb_chipcommon
*cc
,
367 u32
*plltype
, u32
*n
, u32
*m
);
368 extern void ssb_chipco_get_clockcontrol(struct ssb_chipcommon
*cc
,
369 u32
*plltype
, u32
*n
, u32
*m
);
370 extern void ssb_chipco_timing_init(struct ssb_chipcommon
*cc
,
371 unsigned long ns_per_cycle
);
379 extern void ssb_chipco_set_clockmode(struct ssb_chipcommon
*cc
,
380 enum ssb_clkmode mode
);
382 extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon
*cc
,
385 u32
ssb_chipco_gpio_in(struct ssb_chipcommon
*cc
, u32 mask
);
387 void ssb_chipco_gpio_out(struct ssb_chipcommon
*cc
, u32 mask
, u32 value
);
389 void ssb_chipco_gpio_outen(struct ssb_chipcommon
*cc
, u32 mask
, u32 value
);
391 #ifdef CONFIG_SSB_SERIAL
392 extern int ssb_chipco_serial_init(struct ssb_chipcommon
*cc
,
393 struct ssb_serial_port
*ports
);
394 #endif /* CONFIG_SSB_SERIAL */
396 #endif /* LINUX_SSB_CHIPCO_H_ */
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