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generic: 5.15: copy config and patch from 5.10
[openwrt/staging/mkresin.git] / target / linux / generic / backport-5.15 / 754-net-next-net-dsa-qca8k-convert-to-GENMASK_FIELD_PREP_FIELD_GET.patch
1 From 90ae68bfc2ffcb54a4ba4f64edbeb84a80cbb57c Mon Sep 17 00:00:00 2001
2 From: Ansuel Smith <ansuelsmth@gmail.com>
3 Date: Mon, 22 Nov 2021 16:23:41 +0100
4 Subject: net: dsa: qca8k: convert to GENMASK/FIELD_PREP/FIELD_GET
5
6 Convert and try to standardize bit fields using
7 GENMASK/FIELD_PREP/FIELD_GET macros. Rework some logic to support the
8 standard macro and tidy things up. No functional change intended.
9
10 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
11 Signed-off-by: David S. Miller <davem@davemloft.net>
12 ---
13 drivers/net/dsa/qca8k.c | 98 +++++++++++++++----------------
14 drivers/net/dsa/qca8k.h | 153 ++++++++++++++++++++++++++----------------------
15 2 files changed, 130 insertions(+), 121 deletions(-)
16
17 --- a/drivers/net/dsa/qca8k.c
18 +++ b/drivers/net/dsa/qca8k.c
19 @@ -9,6 +9,7 @@
20 #include <linux/module.h>
21 #include <linux/phy.h>
22 #include <linux/netdevice.h>
23 +#include <linux/bitfield.h>
24 #include <net/dsa.h>
25 #include <linux/of_net.h>
26 #include <linux/of_mdio.h>
27 @@ -319,18 +320,18 @@ qca8k_fdb_read(struct qca8k_priv *priv,
28 }
29
30 /* vid - 83:72 */
31 - fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M;
32 + fdb->vid = FIELD_GET(QCA8K_ATU_VID_MASK, reg[2]);
33 /* aging - 67:64 */
34 - fdb->aging = reg[2] & QCA8K_ATU_STATUS_M;
35 + fdb->aging = FIELD_GET(QCA8K_ATU_STATUS_MASK, reg[2]);
36 /* portmask - 54:48 */
37 - fdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M;
38 + fdb->port_mask = FIELD_GET(QCA8K_ATU_PORT_MASK, reg[1]);
39 /* mac - 47:0 */
40 - fdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff;
41 - fdb->mac[1] = reg[1] & 0xff;
42 - fdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff;
43 - fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff;
44 - fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff;
45 - fdb->mac[5] = reg[0] & 0xff;
46 + fdb->mac[0] = FIELD_GET(QCA8K_ATU_ADDR0_MASK, reg[1]);
47 + fdb->mac[1] = FIELD_GET(QCA8K_ATU_ADDR1_MASK, reg[1]);
48 + fdb->mac[2] = FIELD_GET(QCA8K_ATU_ADDR2_MASK, reg[0]);
49 + fdb->mac[3] = FIELD_GET(QCA8K_ATU_ADDR3_MASK, reg[0]);
50 + fdb->mac[4] = FIELD_GET(QCA8K_ATU_ADDR4_MASK, reg[0]);
51 + fdb->mac[5] = FIELD_GET(QCA8K_ATU_ADDR5_MASK, reg[0]);
52
53 return 0;
54 }
55 @@ -343,18 +344,18 @@ qca8k_fdb_write(struct qca8k_priv *priv,
56 int i;
57
58 /* vid - 83:72 */
59 - reg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S;
60 + reg[2] = FIELD_PREP(QCA8K_ATU_VID_MASK, vid);
61 /* aging - 67:64 */
62 - reg[2] |= aging & QCA8K_ATU_STATUS_M;
63 + reg[2] |= FIELD_PREP(QCA8K_ATU_STATUS_MASK, aging);
64 /* portmask - 54:48 */
65 - reg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S;
66 + reg[1] = FIELD_PREP(QCA8K_ATU_PORT_MASK, port_mask);
67 /* mac - 47:0 */
68 - reg[1] |= mac[0] << QCA8K_ATU_ADDR0_S;
69 - reg[1] |= mac[1];
70 - reg[0] |= mac[2] << QCA8K_ATU_ADDR2_S;
71 - reg[0] |= mac[3] << QCA8K_ATU_ADDR3_S;
72 - reg[0] |= mac[4] << QCA8K_ATU_ADDR4_S;
73 - reg[0] |= mac[5];
74 + reg[1] |= FIELD_PREP(QCA8K_ATU_ADDR0_MASK, mac[0]);
75 + reg[1] |= FIELD_PREP(QCA8K_ATU_ADDR1_MASK, mac[1]);
76 + reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR2_MASK, mac[2]);
77 + reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR3_MASK, mac[3]);
78 + reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR4_MASK, mac[4]);
79 + reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR5_MASK, mac[5]);
80
81 /* load the array into the ARL table */
82 for (i = 0; i < 3; i++)
83 @@ -372,7 +373,7 @@ qca8k_fdb_access(struct qca8k_priv *priv
84 reg |= cmd;
85 if (port >= 0) {
86 reg |= QCA8K_ATU_FUNC_PORT_EN;
87 - reg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S;
88 + reg |= FIELD_PREP(QCA8K_ATU_FUNC_PORT_MASK, port);
89 }
90
91 /* Write the function register triggering the table access */
92 @@ -454,7 +455,7 @@ qca8k_vlan_access(struct qca8k_priv *pri
93 /* Set the command and VLAN index */
94 reg = QCA8K_VTU_FUNC1_BUSY;
95 reg |= cmd;
96 - reg |= vid << QCA8K_VTU_FUNC1_VID_S;
97 + reg |= FIELD_PREP(QCA8K_VTU_FUNC1_VID_MASK, vid);
98
99 /* Write the function register triggering the table access */
100 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);
101 @@ -500,13 +501,11 @@ qca8k_vlan_add(struct qca8k_priv *priv,
102 if (ret < 0)
103 goto out;
104 reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN;
105 - reg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port));
106 + reg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port);
107 if (untagged)
108 - reg |= QCA8K_VTU_FUNC0_EG_MODE_UNTAG <<
109 - QCA8K_VTU_FUNC0_EG_MODE_S(port);
110 + reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(port);
111 else
112 - reg |= QCA8K_VTU_FUNC0_EG_MODE_TAG <<
113 - QCA8K_VTU_FUNC0_EG_MODE_S(port);
114 + reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(port);
115
116 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
117 if (ret)
118 @@ -534,15 +533,13 @@ qca8k_vlan_del(struct qca8k_priv *priv,
119 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);
120 if (ret < 0)
121 goto out;
122 - reg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port));
123 - reg |= QCA8K_VTU_FUNC0_EG_MODE_NOT <<
124 - QCA8K_VTU_FUNC0_EG_MODE_S(port);
125 + reg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port);
126 + reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(port);
127
128 /* Check if we're the last member to be removed */
129 del = true;
130 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
131 - mask = QCA8K_VTU_FUNC0_EG_MODE_NOT;
132 - mask <<= QCA8K_VTU_FUNC0_EG_MODE_S(i);
133 + mask = QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(i);
134
135 if ((reg & mask) != mask) {
136 del = false;
137 @@ -1014,7 +1011,7 @@ qca8k_parse_port_config(struct qca8k_pri
138 mode == PHY_INTERFACE_MODE_RGMII_TXID)
139 delay = 1;
140
141 - if (delay > QCA8K_MAX_DELAY) {
142 + if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, delay)) {
143 dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
144 delay = 3;
145 }
146 @@ -1030,7 +1027,7 @@ qca8k_parse_port_config(struct qca8k_pri
147 mode == PHY_INTERFACE_MODE_RGMII_RXID)
148 delay = 2;
149
150 - if (delay > QCA8K_MAX_DELAY) {
151 + if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, delay)) {
152 dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
153 delay = 3;
154 }
155 @@ -1141,8 +1138,8 @@ qca8k_setup(struct dsa_switch *ds)
156 /* Enable QCA header mode on all cpu ports */
157 if (dsa_is_cpu_port(ds, i)) {
158 ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(i),
159 - QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
160 - QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
161 + FIELD_PREP(QCA8K_PORT_HDR_CTRL_TX_MASK, QCA8K_PORT_HDR_CTRL_ALL) |
162 + FIELD_PREP(QCA8K_PORT_HDR_CTRL_RX_MASK, QCA8K_PORT_HDR_CTRL_ALL));
163 if (ret) {
164 dev_err(priv->dev, "failed enabling QCA header mode");
165 return ret;
166 @@ -1159,10 +1156,10 @@ qca8k_setup(struct dsa_switch *ds)
167 * for igmp, unknown, multicast and broadcast packet
168 */
169 ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
170 - BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
171 - BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
172 - BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
173 - BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
174 + FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK, BIT(cpu_port)) |
175 + FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK, BIT(cpu_port)) |
176 + FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK, BIT(cpu_port)) |
177 + FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK, BIT(cpu_port)));
178 if (ret)
179 return ret;
180
181 @@ -1180,8 +1177,6 @@ qca8k_setup(struct dsa_switch *ds)
182
183 /* Individual user ports get connected to CPU port only */
184 if (dsa_is_user_port(ds, i)) {
185 - int shift = 16 * (i % 2);
186 -
187 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
188 QCA8K_PORT_LOOKUP_MEMBER,
189 BIT(cpu_port));
190 @@ -1198,8 +1193,8 @@ qca8k_setup(struct dsa_switch *ds)
191 * default egress vid
192 */
193 ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
194 - 0xfff << shift,
195 - QCA8K_PORT_VID_DEF << shift);
196 + QCA8K_EGREES_VLAN_PORT_MASK(i),
197 + QCA8K_EGREES_VLAN_PORT(i, QCA8K_PORT_VID_DEF));
198 if (ret)
199 return ret;
200
201 @@ -1246,7 +1241,7 @@ qca8k_setup(struct dsa_switch *ds)
202 QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
203 QCA8K_PORT_HOL_CTRL1_WRED_EN;
204 qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i),
205 - QCA8K_PORT_HOL_CTRL1_ING_BUF |
206 + QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK |
207 QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
208 QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
209 QCA8K_PORT_HOL_CTRL1_WRED_EN,
210 @@ -1269,8 +1264,8 @@ qca8k_setup(struct dsa_switch *ds)
211 mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) |
212 QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496);
213 qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH,
214 - QCA8K_GLOBAL_FC_GOL_XON_THRES_S |
215 - QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S,
216 + QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK |
217 + QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK,
218 mask);
219 }
220
221 @@ -1918,11 +1913,11 @@ qca8k_port_vlan_filtering(struct dsa_swi
222
223 if (vlan_filtering) {
224 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
225 - QCA8K_PORT_LOOKUP_VLAN_MODE,
226 + QCA8K_PORT_LOOKUP_VLAN_MODE_MASK,
227 QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE);
228 } else {
229 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
230 - QCA8K_PORT_LOOKUP_VLAN_MODE,
231 + QCA8K_PORT_LOOKUP_VLAN_MODE_MASK,
232 QCA8K_PORT_LOOKUP_VLAN_MODE_NONE);
233 }
234
235 @@ -1953,11 +1948,9 @@ qca8k_port_vlan_add(struct dsa_switch *d
236 dev_err(priv->dev, "Failed to add VLAN to port %d (%d)", port, ret);
237
238 if (pvid) {
239 - int shift = 16 * (port % 2);
240 -
241 qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
242 - 0xfff << shift,
243 - vlan->vid_end << shift);
244 + QCA8K_EGREES_VLAN_PORT_MASK(port),
245 + QCA8K_EGREES_VLAN_PORT(port, vlan->vid_end));
246 qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
247 QCA8K_PORT_VLAN_CVID(vlan->vid_end) |
248 QCA8K_PORT_VLAN_SVID(vlan->vid_end));
249 @@ -2050,7 +2043,7 @@ static int qca8k_read_switch_id(struct q
250 if (ret < 0)
251 return -ENODEV;
252
253 - id = QCA8K_MASK_CTRL_DEVICE_ID(val & QCA8K_MASK_CTRL_DEVICE_ID_MASK);
254 + id = QCA8K_MASK_CTRL_DEVICE_ID(val);
255 if (id != data->id) {
256 dev_err(priv->dev, "Switch id detected %x but expected %x", id, data->id);
257 return -ENODEV;
258 @@ -2059,7 +2052,7 @@ static int qca8k_read_switch_id(struct q
259 priv->switch_id = id;
260
261 /* Save revision to communicate to the internal PHY driver */
262 - priv->switch_revision = (val & QCA8K_MASK_CTRL_REV_ID_MASK);
263 + priv->switch_revision = QCA8K_MASK_CTRL_REV_ID(val);
264
265 return 0;
266 }
267 --- a/drivers/net/dsa/qca8k.h
268 +++ b/drivers/net/dsa/qca8k.h
269 @@ -30,9 +30,9 @@
270 /* Global control registers */
271 #define QCA8K_REG_MASK_CTRL 0x000
272 #define QCA8K_MASK_CTRL_REV_ID_MASK GENMASK(7, 0)
273 -#define QCA8K_MASK_CTRL_REV_ID(x) ((x) >> 0)
274 +#define QCA8K_MASK_CTRL_REV_ID(x) FIELD_GET(QCA8K_MASK_CTRL_REV_ID_MASK, x)
275 #define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8)
276 -#define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8)
277 +#define QCA8K_MASK_CTRL_DEVICE_ID(x) FIELD_GET(QCA8K_MASK_CTRL_DEVICE_ID_MASK, x)
278 #define QCA8K_REG_PORT0_PAD_CTRL 0x004
279 #define QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN BIT(31)
280 #define QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE BIT(19)
281 @@ -41,12 +41,11 @@
282 #define QCA8K_REG_PORT6_PAD_CTRL 0x00c
283 #define QCA8K_PORT_PAD_RGMII_EN BIT(26)
284 #define QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK GENMASK(23, 22)
285 -#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) ((x) << 22)
286 +#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) FIELD_PREP(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, x)
287 #define QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK GENMASK(21, 20)
288 -#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) ((x) << 20)
289 +#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) FIELD_PREP(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, x)
290 #define QCA8K_PORT_PAD_RGMII_TX_DELAY_EN BIT(25)
291 #define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24)
292 -#define QCA8K_MAX_DELAY 3
293 #define QCA8K_PORT_PAD_SGMII_EN BIT(7)
294 #define QCA8K_REG_PWS 0x010
295 #define QCA8K_PWS_POWER_ON_SEL BIT(31)
296 @@ -68,10 +67,12 @@
297 #define QCA8K_MDIO_MASTER_READ BIT(27)
298 #define QCA8K_MDIO_MASTER_WRITE 0
299 #define QCA8K_MDIO_MASTER_SUP_PRE BIT(26)
300 -#define QCA8K_MDIO_MASTER_PHY_ADDR(x) ((x) << 21)
301 -#define QCA8K_MDIO_MASTER_REG_ADDR(x) ((x) << 16)
302 -#define QCA8K_MDIO_MASTER_DATA(x) (x)
303 +#define QCA8K_MDIO_MASTER_PHY_ADDR_MASK GENMASK(25, 21)
304 +#define QCA8K_MDIO_MASTER_PHY_ADDR(x) FIELD_PREP(QCA8K_MDIO_MASTER_PHY_ADDR_MASK, x)
305 +#define QCA8K_MDIO_MASTER_REG_ADDR_MASK GENMASK(20, 16)
306 +#define QCA8K_MDIO_MASTER_REG_ADDR(x) FIELD_PREP(QCA8K_MDIO_MASTER_REG_ADDR_MASK, x)
307 #define QCA8K_MDIO_MASTER_DATA_MASK GENMASK(15, 0)
308 +#define QCA8K_MDIO_MASTER_DATA(x) FIELD_PREP(QCA8K_MDIO_MASTER_DATA_MASK, x)
309 #define QCA8K_MDIO_MASTER_MAX_PORTS 5
310 #define QCA8K_MDIO_MASTER_MAX_REG 32
311 #define QCA8K_GOL_MAC_ADDR0 0x60
312 @@ -93,9 +94,7 @@
313 #define QCA8K_PORT_STATUS_FLOW_AUTO BIT(12)
314 #define QCA8K_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4))
315 #define QCA8K_PORT_HDR_CTRL_RX_MASK GENMASK(3, 2)
316 -#define QCA8K_PORT_HDR_CTRL_RX_S 2
317 #define QCA8K_PORT_HDR_CTRL_TX_MASK GENMASK(1, 0)
318 -#define QCA8K_PORT_HDR_CTRL_TX_S 0
319 #define QCA8K_PORT_HDR_CTRL_ALL 2
320 #define QCA8K_PORT_HDR_CTRL_MGMT 1
321 #define QCA8K_PORT_HDR_CTRL_NONE 0
322 @@ -105,10 +104,11 @@
323 #define QCA8K_SGMII_EN_TX BIT(3)
324 #define QCA8K_SGMII_EN_SD BIT(4)
325 #define QCA8K_SGMII_CLK125M_DELAY BIT(7)
326 -#define QCA8K_SGMII_MODE_CTRL_MASK (BIT(22) | BIT(23))
327 -#define QCA8K_SGMII_MODE_CTRL_BASEX (0 << 22)
328 -#define QCA8K_SGMII_MODE_CTRL_PHY (1 << 22)
329 -#define QCA8K_SGMII_MODE_CTRL_MAC (2 << 22)
330 +#define QCA8K_SGMII_MODE_CTRL_MASK GENMASK(23, 22)
331 +#define QCA8K_SGMII_MODE_CTRL(x) FIELD_PREP(QCA8K_SGMII_MODE_CTRL_MASK, x)
332 +#define QCA8K_SGMII_MODE_CTRL_BASEX QCA8K_SGMII_MODE_CTRL(0x0)
333 +#define QCA8K_SGMII_MODE_CTRL_PHY QCA8K_SGMII_MODE_CTRL(0x1)
334 +#define QCA8K_SGMII_MODE_CTRL_MAC QCA8K_SGMII_MODE_CTRL(0x2)
335
336 /* MAC_PWR_SEL registers */
337 #define QCA8K_REG_MAC_PWR_SEL 0x0e4
338 @@ -121,100 +121,115 @@
339
340 /* ACL registers */
341 #define QCA8K_REG_PORT_VLAN_CTRL0(_i) (0x420 + (_i * 8))
342 -#define QCA8K_PORT_VLAN_CVID(x) (x << 16)
343 -#define QCA8K_PORT_VLAN_SVID(x) x
344 +#define QCA8K_PORT_VLAN_CVID_MASK GENMASK(27, 16)
345 +#define QCA8K_PORT_VLAN_CVID(x) FIELD_PREP(QCA8K_PORT_VLAN_CVID_MASK, x)
346 +#define QCA8K_PORT_VLAN_SVID_MASK GENMASK(11, 0)
347 +#define QCA8K_PORT_VLAN_SVID(x) FIELD_PREP(QCA8K_PORT_VLAN_SVID_MASK, x)
348 #define QCA8K_REG_PORT_VLAN_CTRL1(_i) (0x424 + (_i * 8))
349 #define QCA8K_REG_IPV4_PRI_BASE_ADDR 0x470
350 #define QCA8K_REG_IPV4_PRI_ADDR_MASK 0x474
351
352 /* Lookup registers */
353 #define QCA8K_REG_ATU_DATA0 0x600
354 -#define QCA8K_ATU_ADDR2_S 24
355 -#define QCA8K_ATU_ADDR3_S 16
356 -#define QCA8K_ATU_ADDR4_S 8
357 +#define QCA8K_ATU_ADDR2_MASK GENMASK(31, 24)
358 +#define QCA8K_ATU_ADDR3_MASK GENMASK(23, 16)
359 +#define QCA8K_ATU_ADDR4_MASK GENMASK(15, 8)
360 +#define QCA8K_ATU_ADDR5_MASK GENMASK(7, 0)
361 #define QCA8K_REG_ATU_DATA1 0x604
362 -#define QCA8K_ATU_PORT_M 0x7f
363 -#define QCA8K_ATU_PORT_S 16
364 -#define QCA8K_ATU_ADDR0_S 8
365 +#define QCA8K_ATU_PORT_MASK GENMASK(22, 16)
366 +#define QCA8K_ATU_ADDR0_MASK GENMASK(15, 8)
367 +#define QCA8K_ATU_ADDR1_MASK GENMASK(7, 0)
368 #define QCA8K_REG_ATU_DATA2 0x608
369 -#define QCA8K_ATU_VID_M 0xfff
370 -#define QCA8K_ATU_VID_S 8
371 -#define QCA8K_ATU_STATUS_M 0xf
372 +#define QCA8K_ATU_VID_MASK GENMASK(19, 8)
373 +#define QCA8K_ATU_STATUS_MASK GENMASK(3, 0)
374 #define QCA8K_ATU_STATUS_STATIC 0xf
375 #define QCA8K_REG_ATU_FUNC 0x60c
376 #define QCA8K_ATU_FUNC_BUSY BIT(31)
377 #define QCA8K_ATU_FUNC_PORT_EN BIT(14)
378 #define QCA8K_ATU_FUNC_MULTI_EN BIT(13)
379 #define QCA8K_ATU_FUNC_FULL BIT(12)
380 -#define QCA8K_ATU_FUNC_PORT_M 0xf
381 -#define QCA8K_ATU_FUNC_PORT_S 8
382 +#define QCA8K_ATU_FUNC_PORT_MASK GENMASK(11, 8)
383 #define QCA8K_REG_VTU_FUNC0 0x610
384 #define QCA8K_VTU_FUNC0_VALID BIT(20)
385 #define QCA8K_VTU_FUNC0_IVL_EN BIT(19)
386 -#define QCA8K_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
387 -#define QCA8K_VTU_FUNC0_EG_MODE_MASK 3
388 -#define QCA8K_VTU_FUNC0_EG_MODE_UNMOD 0
389 -#define QCA8K_VTU_FUNC0_EG_MODE_UNTAG 1
390 -#define QCA8K_VTU_FUNC0_EG_MODE_TAG 2
391 -#define QCA8K_VTU_FUNC0_EG_MODE_NOT 3
392 +/* QCA8K_VTU_FUNC0_EG_MODE_MASK GENMASK(17, 4)
393 + * It does contain VLAN_MODE for each port [5:4] for port0,
394 + * [7:6] for port1 ... [17:16] for port6. Use virtual port
395 + * define to handle this.
396 + */
397 +#define QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i) (4 + (_i) * 2)
398 +#define QCA8K_VTU_FUNC0_EG_MODE_MASK GENMASK(1, 0)
399 +#define QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(_i) (GENMASK(1, 0) << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
400 +#define QCA8K_VTU_FUNC0_EG_MODE_UNMOD FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x0)
401 +#define QCA8K_VTU_FUNC0_EG_MODE_PORT_UNMOD(_i) (QCA8K_VTU_FUNC0_EG_MODE_UNMOD << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
402 +#define QCA8K_VTU_FUNC0_EG_MODE_UNTAG FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x1)
403 +#define QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(_i) (QCA8K_VTU_FUNC0_EG_MODE_UNTAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
404 +#define QCA8K_VTU_FUNC0_EG_MODE_TAG FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x2)
405 +#define QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(_i) (QCA8K_VTU_FUNC0_EG_MODE_TAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
406 +#define QCA8K_VTU_FUNC0_EG_MODE_NOT FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x3)
407 +#define QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(_i) (QCA8K_VTU_FUNC0_EG_MODE_NOT << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
408 #define QCA8K_REG_VTU_FUNC1 0x614
409 #define QCA8K_VTU_FUNC1_BUSY BIT(31)
410 -#define QCA8K_VTU_FUNC1_VID_S 16
411 +#define QCA8K_VTU_FUNC1_VID_MASK GENMASK(27, 16)
412 #define QCA8K_VTU_FUNC1_FULL BIT(4)
413 #define QCA8K_REG_GLOBAL_FW_CTRL0 0x620
414 #define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10)
415 #define QCA8K_REG_GLOBAL_FW_CTRL1 0x624
416 -#define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S 24
417 -#define QCA8K_GLOBAL_FW_CTRL1_BC_DP_S 16
418 -#define QCA8K_GLOBAL_FW_CTRL1_MC_DP_S 8
419 -#define QCA8K_GLOBAL_FW_CTRL1_UC_DP_S 0
420 +#define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK GENMASK(30, 24)
421 +#define QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK GENMASK(22, 16)
422 +#define QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK GENMASK(14, 8)
423 +#define QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK GENMASK(6, 0)
424 #define QCA8K_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc)
425 #define QCA8K_PORT_LOOKUP_MEMBER GENMASK(6, 0)
426 -#define QCA8K_PORT_LOOKUP_VLAN_MODE GENMASK(9, 8)
427 -#define QCA8K_PORT_LOOKUP_VLAN_MODE_NONE (0 << 8)
428 -#define QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK (1 << 8)
429 -#define QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK (2 << 8)
430 -#define QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE (3 << 8)
431 +#define QCA8K_PORT_LOOKUP_VLAN_MODE_MASK GENMASK(9, 8)
432 +#define QCA8K_PORT_LOOKUP_VLAN_MODE(x) FIELD_PREP(QCA8K_PORT_LOOKUP_VLAN_MODE_MASK, x)
433 +#define QCA8K_PORT_LOOKUP_VLAN_MODE_NONE QCA8K_PORT_LOOKUP_VLAN_MODE(0x0)
434 +#define QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK QCA8K_PORT_LOOKUP_VLAN_MODE(0x1)
435 +#define QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK QCA8K_PORT_LOOKUP_VLAN_MODE(0x2)
436 +#define QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE QCA8K_PORT_LOOKUP_VLAN_MODE(0x3)
437 #define QCA8K_PORT_LOOKUP_STATE_MASK GENMASK(18, 16)
438 -#define QCA8K_PORT_LOOKUP_STATE_DISABLED (0 << 16)
439 -#define QCA8K_PORT_LOOKUP_STATE_BLOCKING (1 << 16)
440 -#define QCA8K_PORT_LOOKUP_STATE_LISTENING (2 << 16)
441 -#define QCA8K_PORT_LOOKUP_STATE_LEARNING (3 << 16)
442 -#define QCA8K_PORT_LOOKUP_STATE_FORWARD (4 << 16)
443 -#define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16)
444 +#define QCA8K_PORT_LOOKUP_STATE(x) FIELD_PREP(QCA8K_PORT_LOOKUP_STATE_MASK, x)
445 +#define QCA8K_PORT_LOOKUP_STATE_DISABLED QCA8K_PORT_LOOKUP_STATE(0x0)
446 +#define QCA8K_PORT_LOOKUP_STATE_BLOCKING QCA8K_PORT_LOOKUP_STATE(0x1)
447 +#define QCA8K_PORT_LOOKUP_STATE_LISTENING QCA8K_PORT_LOOKUP_STATE(0x2)
448 +#define QCA8K_PORT_LOOKUP_STATE_LEARNING QCA8K_PORT_LOOKUP_STATE(0x3)
449 +#define QCA8K_PORT_LOOKUP_STATE_FORWARD QCA8K_PORT_LOOKUP_STATE(0x4)
450 #define QCA8K_PORT_LOOKUP_LEARN BIT(20)
451
452 #define QCA8K_REG_GLOBAL_FC_THRESH 0x800
453 -#define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) ((x) << 16)
454 -#define QCA8K_GLOBAL_FC_GOL_XON_THRES_S GENMASK(24, 16)
455 -#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) ((x) << 0)
456 -#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S GENMASK(8, 0)
457 +#define QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK GENMASK(24, 16)
458 +#define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) FIELD_PREP(QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK, x)
459 +#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK GENMASK(8, 0)
460 +#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) FIELD_PREP(QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK, x)
461
462 #define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8)
463 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF GENMASK(3, 0)
464 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) ((x) << 0)
465 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF GENMASK(7, 4)
466 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) ((x) << 4)
467 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF GENMASK(11, 8)
468 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) ((x) << 8)
469 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF GENMASK(15, 12)
470 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) ((x) << 12)
471 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF GENMASK(19, 16)
472 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) ((x) << 16)
473 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF GENMASK(23, 20)
474 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) ((x) << 20)
475 -#define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF GENMASK(29, 24)
476 -#define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) ((x) << 24)
477 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK GENMASK(3, 0)
478 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK, x)
479 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK GENMASK(7, 4)
480 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK, x)
481 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK GENMASK(11, 8)
482 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK, x)
483 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK GENMASK(15, 12)
484 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK, x)
485 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK GENMASK(19, 16)
486 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK, x)
487 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK GENMASK(23, 20)
488 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK, x)
489 +#define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK GENMASK(29, 24)
490 +#define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK, x)
491
492 #define QCA8K_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
493 -#define QCA8K_PORT_HOL_CTRL1_ING_BUF GENMASK(3, 0)
494 -#define QCA8K_PORT_HOL_CTRL1_ING(x) ((x) << 0)
495 +#define QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK GENMASK(3, 0)
496 +#define QCA8K_PORT_HOL_CTRL1_ING(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK, x)
497 #define QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN BIT(6)
498 #define QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN BIT(7)
499 #define QCA8K_PORT_HOL_CTRL1_WRED_EN BIT(8)
500 #define QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
501
502 /* Pkt edit registers */
503 +#define QCA8K_EGREES_VLAN_PORT_SHIFT(_i) (16 * ((_i) % 2))
504 +#define QCA8K_EGREES_VLAN_PORT_MASK(_i) (GENMASK(11, 0) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i))
505 +#define QCA8K_EGREES_VLAN_PORT(_i, x) ((x) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i))
506 #define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2)))
507
508 /* L3 registers */
Staging tree of Mathias Kresin