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generic ar8xxx: increase VLAN table for AR83x7
[openwrt/staging/mkresin.git] / target / linux / generic / files / drivers / net / phy / ar8216.h
1 /*
2 * ar8216.h: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #ifndef __AR8216_H
18 #define __AR8216_H
19
20 #define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
21
22 #define AR8XXX_CAP_GIGE BIT(0)
23 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
24
25 #define AR8XXX_NUM_PHYS 5
26 #define AR8216_PORT_CPU 0
27 #define AR8216_NUM_PORTS 6
28 #define AR8216_NUM_VLANS 16
29 #define AR7240SW_NUM_PORTS 5
30 #define AR8316_NUM_VLANS 4096
31
32 /* size of the vlan table */
33 #define AR8X16_MAX_VLANS 128
34 #define AR83X7_MAX_VLANS 4096
35 #define AR8XXX_MAX_VLANS AR83X7_MAX_VLANS
36
37 #define AR8X16_PROBE_RETRIES 10
38 #define AR8X16_MAX_PORTS 8
39
40 #define AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS 7
41 #define AR8XXX_DEFAULT_ARL_AGE_TIME 300
42
43 /* Atheros specific MII registers */
44 #define MII_ATH_MMD_ADDR 0x0d
45 #define MII_ATH_MMD_DATA 0x0e
46 #define MII_ATH_DBG_ADDR 0x1d
47 #define MII_ATH_DBG_DATA 0x1e
48
49 #define AR8216_REG_CTRL 0x0000
50 #define AR8216_CTRL_REVISION BITS(0, 8)
51 #define AR8216_CTRL_REVISION_S 0
52 #define AR8216_CTRL_VERSION BITS(8, 8)
53 #define AR8216_CTRL_VERSION_S 8
54 #define AR8216_CTRL_RESET BIT(31)
55
56 #define AR8216_REG_FLOOD_MASK 0x002C
57 #define AR8216_FM_UNI_DEST_PORTS BITS(0, 6)
58 #define AR8216_FM_MULTI_DEST_PORTS BITS(16, 6)
59 #define AR8229_FLOOD_MASK_MC_DP(_p) BIT(16 + (_p))
60 #define AR8229_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p))
61 #define AR8236_FM_CPU_BROADCAST_EN BIT(26)
62 #define AR8236_FM_CPU_BCAST_FWD_EN BIT(25)
63
64 #define AR8216_REG_GLOBAL_CTRL 0x0030
65 #define AR8216_GCTRL_MTU BITS(0, 11)
66 #define AR8236_GCTRL_MTU BITS(0, 14)
67 #define AR8316_GCTRL_MTU BITS(0, 14)
68
69 #define AR8216_REG_VTU 0x0040
70 #define AR8216_VTU_OP BITS(0, 3)
71 #define AR8216_VTU_OP_NOOP 0x0
72 #define AR8216_VTU_OP_FLUSH 0x1
73 #define AR8216_VTU_OP_LOAD 0x2
74 #define AR8216_VTU_OP_PURGE 0x3
75 #define AR8216_VTU_OP_REMOVE_PORT 0x4
76 #define AR8216_VTU_ACTIVE BIT(3)
77 #define AR8216_VTU_FULL BIT(4)
78 #define AR8216_VTU_PORT BITS(8, 4)
79 #define AR8216_VTU_PORT_S 8
80 #define AR8216_VTU_VID BITS(16, 12)
81 #define AR8216_VTU_VID_S 16
82 #define AR8216_VTU_PRIO BITS(28, 3)
83 #define AR8216_VTU_PRIO_S 28
84 #define AR8216_VTU_PRIO_EN BIT(31)
85
86 #define AR8216_REG_VTU_DATA 0x0044
87 #define AR8216_VTUDATA_MEMBER BITS(0, 10)
88 #define AR8236_VTUDATA_MEMBER BITS(0, 7)
89 #define AR8216_VTUDATA_VALID BIT(11)
90
91 #define AR8216_REG_ATU_FUNC0 0x0050
92 #define AR8216_ATU_OP BITS(0, 3)
93 #define AR8216_ATU_OP_NOOP 0x0
94 #define AR8216_ATU_OP_FLUSH 0x1
95 #define AR8216_ATU_OP_LOAD 0x2
96 #define AR8216_ATU_OP_PURGE 0x3
97 #define AR8216_ATU_OP_FLUSH_UNLOCKED 0x4
98 #define AR8216_ATU_OP_FLUSH_PORT 0x5
99 #define AR8216_ATU_OP_GET_NEXT 0x6
100 #define AR8216_ATU_ACTIVE BIT(3)
101 #define AR8216_ATU_PORT_NUM BITS(8, 4)
102 #define AR8216_ATU_PORT_NUM_S 8
103 #define AR8216_ATU_FULL_VIO BIT(12)
104 #define AR8216_ATU_ADDR5 BITS(16, 8)
105 #define AR8216_ATU_ADDR5_S 16
106 #define AR8216_ATU_ADDR4 BITS(24, 8)
107 #define AR8216_ATU_ADDR4_S 24
108
109 #define AR8216_REG_ATU_FUNC1 0x0054
110 #define AR8216_ATU_ADDR3 BITS(0, 8)
111 #define AR8216_ATU_ADDR3_S 0
112 #define AR8216_ATU_ADDR2 BITS(8, 8)
113 #define AR8216_ATU_ADDR2_S 8
114 #define AR8216_ATU_ADDR1 BITS(16, 8)
115 #define AR8216_ATU_ADDR1_S 16
116 #define AR8216_ATU_ADDR0 BITS(24, 8)
117 #define AR8216_ATU_ADDR0_S 24
118
119 #define AR8216_REG_ATU_FUNC2 0x0058
120 #define AR8216_ATU_PORTS BITS(0, 6)
121 #define AR8216_ATU_PORTS_S 0
122 #define AR8216_ATU_PORT0 BIT(0)
123 #define AR8216_ATU_PORT1 BIT(1)
124 #define AR8216_ATU_PORT2 BIT(2)
125 #define AR8216_ATU_PORT3 BIT(3)
126 #define AR8216_ATU_PORT4 BIT(4)
127 #define AR8216_ATU_PORT5 BIT(5)
128 #define AR8216_ATU_STATUS BITS(16, 4)
129 #define AR8216_ATU_STATUS_S 16
130
131 #define AR8216_REG_ATU_CTRL 0x005C
132 #define AR8216_ATU_CTRL_AGE_EN BIT(17)
133 #define AR8216_ATU_CTRL_AGE_TIME BITS(0, 16)
134 #define AR8216_ATU_CTRL_AGE_TIME_S 0
135 #define AR8236_ATU_CTRL_RES BIT(20)
136 #define AR8216_ATU_CTRL_LEARN_CHANGE BIT(18)
137 #define AR8216_ATU_CTRL_RESERVED BIT(19)
138 #define AR8216_ATU_CTRL_ARP_EN BIT(20)
139
140 #define AR8216_REG_TAG_PRIORITY 0x0070
141
142 #define AR8216_REG_SERVICE_TAG 0x0074
143 #define AR8216_SERVICE_TAG_M BITS(0, 16)
144
145 #define AR8216_REG_MIB_FUNC 0x0080
146 #define AR8216_MIB_TIMER BITS(0, 16)
147 #define AR8216_MIB_AT_HALF_EN BIT(16)
148 #define AR8216_MIB_BUSY BIT(17)
149 #define AR8216_MIB_FUNC BITS(24, 3)
150 #define AR8216_MIB_FUNC_S 24
151 #define AR8216_MIB_FUNC_NO_OP 0x0
152 #define AR8216_MIB_FUNC_FLUSH 0x1
153 #define AR8216_MIB_FUNC_CAPTURE 0x3
154 #define AR8236_MIB_EN BIT(30)
155
156 #define AR8216_REG_GLOBAL_CPUPORT 0x0078
157 #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT BITS(4, 4)
158 #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S 4
159 #define AR8216_GLOBAL_CPUPORT_EN BIT(8)
160
161 #define AR8216_REG_MDIO_CTRL 0x98
162 #define AR8216_MDIO_CTRL_DATA_M BITS(0, 16)
163 #define AR8216_MDIO_CTRL_REG_ADDR_S 16
164 #define AR8216_MDIO_CTRL_PHY_ADDR_S 21
165 #define AR8216_MDIO_CTRL_CMD_WRITE 0
166 #define AR8216_MDIO_CTRL_CMD_READ BIT(27)
167 #define AR8216_MDIO_CTRL_MASTER_EN BIT(30)
168 #define AR8216_MDIO_CTRL_BUSY BIT(31)
169
170 #define AR8216_PORT_OFFSET(_i) (0x0100 * (_i + 1))
171 #define AR8216_REG_PORT_STATUS(_i) (AR8216_PORT_OFFSET(_i) + 0x0000)
172 #define AR8216_PORT_STATUS_SPEED BITS(0,2)
173 #define AR8216_PORT_STATUS_SPEED_S 0
174 #define AR8216_PORT_STATUS_TXMAC BIT(2)
175 #define AR8216_PORT_STATUS_RXMAC BIT(3)
176 #define AR8216_PORT_STATUS_TXFLOW BIT(4)
177 #define AR8216_PORT_STATUS_RXFLOW BIT(5)
178 #define AR8216_PORT_STATUS_DUPLEX BIT(6)
179 #define AR8216_PORT_STATUS_LINK_UP BIT(8)
180 #define AR8216_PORT_STATUS_LINK_AUTO BIT(9)
181 #define AR8216_PORT_STATUS_LINK_PAUSE BIT(10)
182 #define AR8216_PORT_STATUS_FLOW_CONTROL BIT(12)
183
184 #define AR8216_REG_PORT_CTRL(_i) (AR8216_PORT_OFFSET(_i) + 0x0004)
185
186 /* port forwarding state */
187 #define AR8216_PORT_CTRL_STATE BITS(0, 3)
188 #define AR8216_PORT_CTRL_STATE_S 0
189
190 #define AR8216_PORT_CTRL_LEARN_LOCK BIT(7)
191
192 /* egress 802.1q mode */
193 #define AR8216_PORT_CTRL_VLAN_MODE BITS(8, 2)
194 #define AR8216_PORT_CTRL_VLAN_MODE_S 8
195
196 #define AR8216_PORT_CTRL_IGMP_SNOOP BIT(10)
197 #define AR8216_PORT_CTRL_HEADER BIT(11)
198 #define AR8216_PORT_CTRL_MAC_LOOP BIT(12)
199 #define AR8216_PORT_CTRL_SINGLE_VLAN BIT(13)
200 #define AR8216_PORT_CTRL_LEARN BIT(14)
201 #define AR8216_PORT_CTRL_MIRROR_TX BIT(16)
202 #define AR8216_PORT_CTRL_MIRROR_RX BIT(17)
203
204 #define AR8216_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET(_i) + 0x0008)
205
206 #define AR8216_PORT_VLAN_DEFAULT_ID BITS(0, 12)
207 #define AR8216_PORT_VLAN_DEFAULT_ID_S 0
208
209 #define AR8216_PORT_VLAN_DEST_PORTS BITS(16, 9)
210 #define AR8216_PORT_VLAN_DEST_PORTS_S 16
211
212 /* bit0 added to the priority field of egress frames */
213 #define AR8216_PORT_VLAN_TX_PRIO BIT(27)
214
215 /* port default priority */
216 #define AR8216_PORT_VLAN_PRIORITY BITS(28, 2)
217 #define AR8216_PORT_VLAN_PRIORITY_S 28
218
219 /* ingress 802.1q mode */
220 #define AR8216_PORT_VLAN_MODE BITS(30, 2)
221 #define AR8216_PORT_VLAN_MODE_S 30
222
223 #define AR8216_REG_PORT_RATE(_i) (AR8216_PORT_OFFSET(_i) + 0x000c)
224 #define AR8216_REG_PORT_PRIO(_i) (AR8216_PORT_OFFSET(_i) + 0x0010)
225
226 #define AR8216_STATS_RXBROAD 0x00
227 #define AR8216_STATS_RXPAUSE 0x04
228 #define AR8216_STATS_RXMULTI 0x08
229 #define AR8216_STATS_RXFCSERR 0x0c
230 #define AR8216_STATS_RXALIGNERR 0x10
231 #define AR8216_STATS_RXRUNT 0x14
232 #define AR8216_STATS_RXFRAGMENT 0x18
233 #define AR8216_STATS_RX64BYTE 0x1c
234 #define AR8216_STATS_RX128BYTE 0x20
235 #define AR8216_STATS_RX256BYTE 0x24
236 #define AR8216_STATS_RX512BYTE 0x28
237 #define AR8216_STATS_RX1024BYTE 0x2c
238 #define AR8216_STATS_RXMAXBYTE 0x30
239 #define AR8216_STATS_RXTOOLONG 0x34
240 #define AR8216_STATS_RXGOODBYTE 0x38
241 #define AR8216_STATS_RXBADBYTE 0x40
242 #define AR8216_STATS_RXOVERFLOW 0x48
243 #define AR8216_STATS_FILTERED 0x4c
244 #define AR8216_STATS_TXBROAD 0x50
245 #define AR8216_STATS_TXPAUSE 0x54
246 #define AR8216_STATS_TXMULTI 0x58
247 #define AR8216_STATS_TXUNDERRUN 0x5c
248 #define AR8216_STATS_TX64BYTE 0x60
249 #define AR8216_STATS_TX128BYTE 0x64
250 #define AR8216_STATS_TX256BYTE 0x68
251 #define AR8216_STATS_TX512BYTE 0x6c
252 #define AR8216_STATS_TX1024BYTE 0x70
253 #define AR8216_STATS_TXMAXBYTE 0x74
254 #define AR8216_STATS_TXOVERSIZE 0x78
255 #define AR8216_STATS_TXBYTE 0x7c
256 #define AR8216_STATS_TXCOLLISION 0x84
257 #define AR8216_STATS_TXABORTCOL 0x88
258 #define AR8216_STATS_TXMULTICOL 0x8c
259 #define AR8216_STATS_TXSINGLECOL 0x90
260 #define AR8216_STATS_TXEXCDEFER 0x94
261 #define AR8216_STATS_TXDEFER 0x98
262 #define AR8216_STATS_TXLATECOL 0x9c
263
264 #define AR8216_MIB_RXB_ID 14 /* RxGoodByte */
265 #define AR8216_MIB_TXB_ID 29 /* TxByte */
266
267 #define AR8229_REG_OPER_MODE0 0x04
268 #define AR8229_OPER_MODE0_MAC_GMII_EN BIT(6)
269 #define AR8229_OPER_MODE0_PHY_MII_EN BIT(10)
270
271 #define AR8229_REG_OPER_MODE1 0x08
272 #define AR8229_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
273
274 #define AR8229_REG_QM_CTRL 0x3c
275 #define AR8229_QM_CTRL_ARP_EN BIT(15)
276
277 #define AR8236_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET((_i)) + 0x0008)
278 #define AR8236_PORT_VLAN_DEFAULT_ID BITS(16, 12)
279 #define AR8236_PORT_VLAN_DEFAULT_ID_S 16
280 #define AR8236_PORT_VLAN_PRIORITY BITS(29, 3)
281 #define AR8236_PORT_VLAN_PRIORITY_S 28
282
283 #define AR8236_REG_PORT_VLAN2(_i) (AR8216_PORT_OFFSET((_i)) + 0x000c)
284 #define AR8236_PORT_VLAN2_MEMBER BITS(16, 7)
285 #define AR8236_PORT_VLAN2_MEMBER_S 16
286 #define AR8236_PORT_VLAN2_TX_PRIO BIT(23)
287 #define AR8236_PORT_VLAN2_VLAN_MODE BITS(30, 2)
288 #define AR8236_PORT_VLAN2_VLAN_MODE_S 30
289
290 #define AR8236_STATS_RXBROAD 0x00
291 #define AR8236_STATS_RXPAUSE 0x04
292 #define AR8236_STATS_RXMULTI 0x08
293 #define AR8236_STATS_RXFCSERR 0x0c
294 #define AR8236_STATS_RXALIGNERR 0x10
295 #define AR8236_STATS_RXRUNT 0x14
296 #define AR8236_STATS_RXFRAGMENT 0x18
297 #define AR8236_STATS_RX64BYTE 0x1c
298 #define AR8236_STATS_RX128BYTE 0x20
299 #define AR8236_STATS_RX256BYTE 0x24
300 #define AR8236_STATS_RX512BYTE 0x28
301 #define AR8236_STATS_RX1024BYTE 0x2c
302 #define AR8236_STATS_RX1518BYTE 0x30
303 #define AR8236_STATS_RXMAXBYTE 0x34
304 #define AR8236_STATS_RXTOOLONG 0x38
305 #define AR8236_STATS_RXGOODBYTE 0x3c
306 #define AR8236_STATS_RXBADBYTE 0x44
307 #define AR8236_STATS_RXOVERFLOW 0x4c
308 #define AR8236_STATS_FILTERED 0x50
309 #define AR8236_STATS_TXBROAD 0x54
310 #define AR8236_STATS_TXPAUSE 0x58
311 #define AR8236_STATS_TXMULTI 0x5c
312 #define AR8236_STATS_TXUNDERRUN 0x60
313 #define AR8236_STATS_TX64BYTE 0x64
314 #define AR8236_STATS_TX128BYTE 0x68
315 #define AR8236_STATS_TX256BYTE 0x6c
316 #define AR8236_STATS_TX512BYTE 0x70
317 #define AR8236_STATS_TX1024BYTE 0x74
318 #define AR8236_STATS_TX1518BYTE 0x78
319 #define AR8236_STATS_TXMAXBYTE 0x7c
320 #define AR8236_STATS_TXOVERSIZE 0x80
321 #define AR8236_STATS_TXBYTE 0x84
322 #define AR8236_STATS_TXCOLLISION 0x8c
323 #define AR8236_STATS_TXABORTCOL 0x90
324 #define AR8236_STATS_TXMULTICOL 0x94
325 #define AR8236_STATS_TXSINGLECOL 0x98
326 #define AR8236_STATS_TXEXCDEFER 0x9c
327 #define AR8236_STATS_TXDEFER 0xa0
328 #define AR8236_STATS_TXLATECOL 0xa4
329
330 #define AR8236_MIB_RXB_ID 15 /* RxGoodByte */
331 #define AR8236_MIB_TXB_ID 31 /* TxByte */
332
333 #define AR8316_REG_POSTRIP 0x0008
334 #define AR8316_POSTRIP_MAC0_GMII_EN BIT(0)
335 #define AR8316_POSTRIP_MAC0_RGMII_EN BIT(1)
336 #define AR8316_POSTRIP_PHY4_GMII_EN BIT(2)
337 #define AR8316_POSTRIP_PHY4_RGMII_EN BIT(3)
338 #define AR8316_POSTRIP_MAC0_MAC_MODE BIT(4)
339 #define AR8316_POSTRIP_RTL_MODE BIT(5)
340 #define AR8316_POSTRIP_RGMII_RXCLK_DELAY_EN BIT(6)
341 #define AR8316_POSTRIP_RGMII_TXCLK_DELAY_EN BIT(7)
342 #define AR8316_POSTRIP_SERDES_EN BIT(8)
343 #define AR8316_POSTRIP_SEL_ANA_RST BIT(9)
344 #define AR8316_POSTRIP_GATE_25M_EN BIT(10)
345 #define AR8316_POSTRIP_SEL_CLK25M BIT(11)
346 #define AR8316_POSTRIP_HIB_PULSE_HW BIT(12)
347 #define AR8316_POSTRIP_DBG_MODE_I BIT(13)
348 #define AR8316_POSTRIP_MAC5_MAC_MODE BIT(14)
349 #define AR8316_POSTRIP_MAC5_PHY_MODE BIT(15)
350 #define AR8316_POSTRIP_POWER_DOWN_HW BIT(16)
351 #define AR8316_POSTRIP_LPW_STATE_EN BIT(17)
352 #define AR8316_POSTRIP_MAN_EN BIT(18)
353 #define AR8316_POSTRIP_PHY_PLL_ON BIT(19)
354 #define AR8316_POSTRIP_LPW_EXIT BIT(20)
355 #define AR8316_POSTRIP_TXDELAY_S0 BIT(21)
356 #define AR8316_POSTRIP_TXDELAY_S1 BIT(22)
357 #define AR8316_POSTRIP_RXDELAY_S0 BIT(23)
358 #define AR8316_POSTRIP_LED_OPEN_EN BIT(24)
359 #define AR8316_POSTRIP_SPI_EN BIT(25)
360 #define AR8316_POSTRIP_RXDELAY_S1 BIT(26)
361 #define AR8316_POSTRIP_POWER_ON_SEL BIT(31)
362
363 /* port speed */
364 enum {
365 AR8216_PORT_SPEED_10M = 0,
366 AR8216_PORT_SPEED_100M = 1,
367 AR8216_PORT_SPEED_1000M = 2,
368 AR8216_PORT_SPEED_ERR = 3,
369 };
370
371 /* ingress 802.1q mode */
372 enum {
373 AR8216_IN_PORT_ONLY = 0,
374 AR8216_IN_PORT_FALLBACK = 1,
375 AR8216_IN_VLAN_ONLY = 2,
376 AR8216_IN_SECURE = 3
377 };
378
379 /* egress 802.1q mode */
380 enum {
381 AR8216_OUT_KEEP = 0,
382 AR8216_OUT_STRIP_VLAN = 1,
383 AR8216_OUT_ADD_VLAN = 2
384 };
385
386 /* port forwarding state */
387 enum {
388 AR8216_PORT_STATE_DISABLED = 0,
389 AR8216_PORT_STATE_BLOCK = 1,
390 AR8216_PORT_STATE_LISTEN = 2,
391 AR8216_PORT_STATE_LEARN = 3,
392 AR8216_PORT_STATE_FORWARD = 4
393 };
394
395 /* mib counter type */
396 enum {
397 AR8XXX_MIB_BASIC = 0,
398 AR8XXX_MIB_EXTENDED = 1
399 };
400
401 enum {
402 AR8XXX_VER_AR8216 = 0x01,
403 AR8XXX_VER_AR8236 = 0x03,
404 AR8XXX_VER_AR8316 = 0x10,
405 AR8XXX_VER_AR8327 = 0x12,
406 AR8XXX_VER_AR8337 = 0x13,
407 };
408
409 #define AR8XXX_NUM_ARL_RECORDS 100
410
411 enum arl_op {
412 AR8XXX_ARL_INITIALIZE,
413 AR8XXX_ARL_GET_NEXT
414 };
415
416 struct arl_entry {
417 u16 portmap;
418 u8 mac[6];
419 };
420
421 struct ar8xxx_priv;
422
423 struct ar8xxx_mib_desc {
424 unsigned int size;
425 unsigned int offset;
426 const char *name;
427 u8 type;
428 };
429
430 struct ar8xxx_chip {
431 unsigned long caps;
432 bool config_at_probe;
433 bool mii_lo_first;
434
435 /* parameters to calculate REG_PORT_STATS_BASE */
436 unsigned reg_port_stats_start;
437 unsigned reg_port_stats_length;
438
439 unsigned reg_arl_ctrl;
440
441 int (*hw_init)(struct ar8xxx_priv *priv);
442 void (*cleanup)(struct ar8xxx_priv *priv);
443
444 const char *name;
445 int vlans;
446 int ports;
447 const struct switch_dev_ops *swops;
448
449 void (*init_globals)(struct ar8xxx_priv *priv);
450 void (*init_port)(struct ar8xxx_priv *priv, int port);
451 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
452 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
453 u32 (*read_port_eee_status)(struct ar8xxx_priv *priv, int port);
454 int (*atu_flush)(struct ar8xxx_priv *priv);
455 int (*atu_flush_port)(struct ar8xxx_priv *priv, int port);
456 void (*vtu_flush)(struct ar8xxx_priv *priv);
457 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
458 void (*phy_fixup)(struct ar8xxx_priv *priv, int phy);
459 void (*set_mirror_regs)(struct ar8xxx_priv *priv);
460 void (*get_arl_entry)(struct ar8xxx_priv *priv, struct arl_entry *a,
461 u32 *status, enum arl_op op);
462 int (*sw_hw_apply)(struct switch_dev *dev);
463 void (*phy_rgmii_set)(struct ar8xxx_priv *priv, struct phy_device *phydev);
464 int (*phy_read)(struct ar8xxx_priv *priv, int addr, int regnum);
465 int (*phy_write)(struct ar8xxx_priv *priv, int addr, int regnum, u16 val);
466
467 const struct ar8xxx_mib_desc *mib_decs;
468 unsigned num_mibs;
469 unsigned mib_func;
470 int mib_rxb_id;
471 int mib_txb_id;
472 };
473
474 struct ar8xxx_priv {
475 struct switch_dev dev;
476 struct mii_bus *mii_bus;
477 struct mii_bus *sw_mii_bus;
478 struct phy_device *phy;
479 struct device *pdev;
480
481 int (*get_port_link)(unsigned port);
482
483 const struct net_device_ops *ndo_old;
484 struct net_device_ops ndo;
485 struct mutex reg_mutex;
486 u8 chip_ver;
487 u8 chip_rev;
488 const struct ar8xxx_chip *chip;
489 void *chip_data;
490 bool initialized;
491 bool port4_phy;
492 char buf[2048];
493 struct arl_entry arl_table[AR8XXX_NUM_ARL_RECORDS];
494 char arl_buf[AR8XXX_NUM_ARL_RECORDS * 32 + 256];
495 bool link_up[AR8X16_MAX_PORTS];
496
497 bool init;
498
499 struct mutex mib_lock;
500 struct delayed_work mib_work;
501 u64 *mib_stats;
502 u32 mib_poll_interval;
503 u8 mib_type;
504
505 struct list_head list;
506 unsigned int use_count;
507
508 /* all fields below are cleared on reset */
509 bool vlan;
510
511 u16 vlan_id[AR8XXX_MAX_VLANS];
512 u8 vlan_table[AR8XXX_MAX_VLANS];
513 u8 vlan_tagged;
514 u16 pvid[AR8X16_MAX_PORTS];
515 int arl_age_time;
516
517 /* mirroring */
518 bool mirror_rx;
519 bool mirror_tx;
520 int source_port;
521 int monitor_port;
522 u8 port_vlan_prio[AR8X16_MAX_PORTS];
523 };
524
525 u32
526 ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum);
527 void
528 ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val);
529 u32
530 ar8xxx_read(struct ar8xxx_priv *priv, int reg);
531 void
532 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val);
533 u32
534 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
535
536 void
537 ar8xxx_phy_dbg_read(struct ar8xxx_priv *priv, int phy_addr,
538 u16 dbg_addr, u16 *dbg_data);
539 void
540 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
541 u16 dbg_addr, u16 dbg_data);
542 void
543 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data);
544 u16
545 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg);
546 void
547 ar8xxx_phy_init(struct ar8xxx_priv *priv);
548 int
549 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
550 struct switch_val *val);
551 int
552 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
553 struct switch_val *val);
554 int
555 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
556 const struct switch_attr *attr,
557 struct switch_val *val);
558 int
559 ar8xxx_sw_set_mib_poll_interval(struct switch_dev *dev,
560 const struct switch_attr *attr,
561 struct switch_val *val);
562 int
563 ar8xxx_sw_get_mib_poll_interval(struct switch_dev *dev,
564 const struct switch_attr *attr,
565 struct switch_val *val);
566 int
567 ar8xxx_sw_set_mib_type(struct switch_dev *dev,
568 const struct switch_attr *attr,
569 struct switch_val *val);
570 int
571 ar8xxx_sw_get_mib_type(struct switch_dev *dev,
572 const struct switch_attr *attr,
573 struct switch_val *val);
574 int
575 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
576 const struct switch_attr *attr,
577 struct switch_val *val);
578 int
579 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
580 const struct switch_attr *attr,
581 struct switch_val *val);
582 int
583 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
584 const struct switch_attr *attr,
585 struct switch_val *val);
586 int
587 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
588 const struct switch_attr *attr,
589 struct switch_val *val);
590 int
591 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
592 const struct switch_attr *attr,
593 struct switch_val *val);
594 int
595 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
596 const struct switch_attr *attr,
597 struct switch_val *val);
598 int
599 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
600 const struct switch_attr *attr,
601 struct switch_val *val);
602 int
603 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
604 const struct switch_attr *attr,
605 struct switch_val *val);
606 int
607 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan);
608 int
609 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan);
610 int
611 ar8xxx_sw_hw_apply(struct switch_dev *dev);
612 int
613 ar8xxx_sw_reset_switch(struct switch_dev *dev);
614 int
615 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
616 struct switch_port_link *link);
617 int
618 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
619 const struct switch_attr *attr,
620 struct switch_val *val);
621 int
622 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
623 const struct switch_attr *attr,
624 struct switch_val *val);
625 int
626 ar8xxx_sw_get_arl_age_time(struct switch_dev *dev,
627 const struct switch_attr *attr,
628 struct switch_val *val);
629 int
630 ar8xxx_sw_set_arl_age_time(struct switch_dev *dev,
631 const struct switch_attr *attr,
632 struct switch_val *val);
633 int
634 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
635 const struct switch_attr *attr,
636 struct switch_val *val);
637 int
638 ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev,
639 const struct switch_attr *attr,
640 struct switch_val *val);
641 int
642 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,
643 const struct switch_attr *attr,
644 struct switch_val *val);
645 int
646 ar8xxx_sw_get_port_stats(struct switch_dev *dev, int port,
647 struct switch_port_stats *stats);
648 int
649 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
650
651 static inline struct ar8xxx_priv *
652 swdev_to_ar8xxx(struct switch_dev *swdev)
653 {
654 return container_of(swdev, struct ar8xxx_priv, dev);
655 }
656
657 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
658 {
659 return priv->chip->caps & AR8XXX_CAP_GIGE;
660 }
661
662 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
663 {
664 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
665 }
666
667 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
668 {
669 return priv->chip_ver == AR8XXX_VER_AR8216;
670 }
671
672 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
673 {
674 return priv->chip_ver == AR8XXX_VER_AR8236;
675 }
676
677 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
678 {
679 return priv->chip_ver == AR8XXX_VER_AR8316;
680 }
681
682 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
683 {
684 return priv->chip_ver == AR8XXX_VER_AR8327;
685 }
686
687 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
688 {
689 return priv->chip_ver == AR8XXX_VER_AR8337;
690 }
691
692 static inline void
693 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
694 {
695 ar8xxx_rmw(priv, reg, 0, val);
696 }
697
698 static inline void
699 ar8xxx_reg_clear(struct ar8xxx_priv *priv, int reg, u32 val)
700 {
701 ar8xxx_rmw(priv, reg, val, 0);
702 }
703
704 static inline void
705 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
706 {
707 regaddr >>= 1;
708 *r1 = regaddr & 0x1e;
709
710 regaddr >>= 5;
711 *r2 = regaddr & 0x7;
712
713 regaddr >>= 3;
714 *page = regaddr & 0x1ff;
715 }
716
717 static inline void
718 wait_for_page_switch(void)
719 {
720 udelay(5);
721 }
722
723 #endif
Staging tree of Mathias Kresin