target/linux/generic/pending-5.15/851-0002-phy-marvell-phy-mvebu-a3700-comphy-Add-native-kernel.patch

   1 From 9d276da259cce20b2ed7a868b6e6a6a205f7bb04 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
   3 Date: Thu, 23 Sep 2021 19:20:13 +0200
   4 Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Add native kernel
   5  implementation
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 Remove old RPC implementation and add a new native kernel implementation.
  11
  12 The old implementation uses ARM SMC API to issue RPC calls to ARM Trusted
  13 Firmware which provides real implementation of PHY configuration.
  14
  15 But older versions of ARM Trusted Firmware do not provide this PHY
  16 configuration functionality, simply returning: operation not supported; or
  17 worse, some versions provide the configuration functionality incorrectly.
  18
  19 For example the firmware shipped in ESPRESSObin board has this older
  20 version of ARM Trusted Firmware and therefore SATA, USB 3.0 and PCIe
  21 functionality do not work with newer versions of Linux kernel.
  22
  23 Due to the above reasons, the following commits were introduced into Linux,
  24 to workaround these issues by ignoring -EOPNOTSUPP error code from
  25 phy-mvebu-a3700-comphy driver function phy_power_on():
  26
  27 commit 45aefe3d2251 ("ata: ahci: mvebu: Make SATA PHY optional for Armada
  28 3720")
  29 commit 3241929b67d2 ("usb: host: xhci: mvebu: make USB 3.0 PHY optional for
  30 Armada 3720")
  31 commit b0c6ae0f8948 ("PCI: aardvark: Fix initialization with old Marvell's
  32 Arm Trusted Firmware")
  33
  34 Replace this RPC implementation with proper native kernel implementation,
  35 which is independent on the firmware. Never return -EOPNOTSUPP for proper
  36 arguments.
  37
  38 This should solve multiple issues with real-world boards, where it is not
  39 possible or really inconvenient to change the firmware. Let's eliminate
  40 these issues.
  41
  42 This implementation is ported directly from Armada 3720 comphy driver found
  43 in newest version of ARM Trusted Firmware source code, but with various
  44 fixes of register names, some added comments, some refactoring due to the
  45 original code not conforming to kernel standards. Also PCIe mode poweroff
  46 support was added here, and PHY reset support. These changes are also going
  47 to be sent to ARM Trusted Firmware.
  48
  49 Signed-off-by: Pali Rohár <pali@kernel.org>
  50 Acked-by: Miquel Raynal <miquel.raynal@bootlin.com>
  51 [ Pali did the porting from ATF.
  52   I (Marek) then fixed some register names, some various other things,
  53   added some comments and refactored the code to kernel standards. Also
  54   fixed PHY poweroff and added PHY reset. ]
  55 Signed-off-by: Marek Behún <kabel@kernel.org>
  56 ---
  57  drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 1351 ++++++++++++++++--
  58  1 file changed, 1234 insertions(+), 117 deletions(-)
  59
  60 --- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
  61 +++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
  62 @@ -5,12 +5,16 @@
  63   * Authors:
  64   *   Evan Wang <xswang@marvell.com>
  65   *   Miquèl Raynal <miquel.raynal@bootlin.com>
  66 + *   Pali Rohár <pali@kernel.org>
  67 + *   Marek Behún <kabel@kernel.org>
  68   *
  69   * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
  70 - * SMC call initial support done by Grzegorz Jaszczyk.
  71 + * Comphy code from ARM Trusted Firmware ported by Pali Rohár <pali@kernel.org>
  72 + * and Marek Behún <kabel@kernel.org>.
  73   */
  74
  75 -#include <linux/arm-smccc.h>
  76 +#include <linux/bitfield.h>
  77 +#include <linux/clk.h>
  78  #include <linux/io.h>
  79  #include <linux/iopoll.h>
  80  #include <linux/mfd/syscon.h>
  81 @@ -18,103 +22,1147 @@
  82  #include <linux/phy.h>
  83  #include <linux/phy/phy.h>
  84  #include <linux/platform_device.h>
  85 +#include <linux/spinlock.h>
  86
  87 -#define MVEBU_A3700_COMPHY_LANES               3
  88 +#define PLL_SET_DELAY_US               600
  89 +#define COMPHY_PLL_SLEEP               1000
  90 +#define COMPHY_PLL_TIMEOUT             150000
  91 +
  92 +/* Comphy lane2 indirect access register offset */
  93 +#define COMPHY_LANE2_INDIR_ADDR                0x0
  94 +#define COMPHY_LANE2_INDIR_DATA                0x4
  95 +
  96 +/* SATA and USB3 PHY offset compared to SATA PHY */
  97 +#define COMPHY_LANE2_REGS_BASE         0x200
  98 +
  99 +/*
 100 + * When accessing common PHY lane registers directly, we need to shift by 1,
 101 + * since the registers are 16-bit.
 102 + */
 103 +#define COMPHY_LANE_REG_DIRECT(reg)    (((reg) & 0x7FF) << 1)
 104 +
 105 +/* COMPHY registers */
 106 +#define COMPHY_POWER_PLL_CTRL          0x01
 107 +#define PU_IVREF_BIT                   BIT(15)
 108 +#define PU_PLL_BIT                     BIT(14)
 109 +#define PU_RX_BIT                      BIT(13)
 110 +#define PU_TX_BIT                      BIT(12)
 111 +#define PU_TX_INTP_BIT                 BIT(11)
 112 +#define PU_DFE_BIT                     BIT(10)
 113 +#define RESET_DTL_RX_BIT               BIT(9)
 114 +#define PLL_LOCK_BIT                   BIT(8)
 115 +#define REF_FREF_SEL_MASK              GENMASK(4, 0)
 116 +#define REF_FREF_SEL_SERDES_25MHZ      FIELD_PREP(REF_FREF_SEL_MASK, 0x1)
 117 +#define REF_FREF_SEL_SERDES_40MHZ      FIELD_PREP(REF_FREF_SEL_MASK, 0x3)
 118 +#define REF_FREF_SEL_SERDES_50MHZ      FIELD_PREP(REF_FREF_SEL_MASK, 0x4)
 119 +#define REF_FREF_SEL_PCIE_USB3_25MHZ   FIELD_PREP(REF_FREF_SEL_MASK, 0x2)
 120 +#define REF_FREF_SEL_PCIE_USB3_40MHZ   FIELD_PREP(REF_FREF_SEL_MASK, 0x3)
 121 +#define COMPHY_MODE_MASK               GENMASK(7, 5)
 122 +#define COMPHY_MODE_SATA               FIELD_PREP(COMPHY_MODE_MASK, 0x0)
 123 +#define COMPHY_MODE_PCIE               FIELD_PREP(COMPHY_MODE_MASK, 0x3)
 124 +#define COMPHY_MODE_SERDES             FIELD_PREP(COMPHY_MODE_MASK, 0x4)
 125 +#define COMPHY_MODE_USB3               FIELD_PREP(COMPHY_MODE_MASK, 0x5)
 126 +
 127 +#define COMPHY_KVCO_CAL_CTRL           0x02
 128 +#define USE_MAX_PLL_RATE_BIT           BIT(12)
 129 +#define SPEED_PLL_MASK                 GENMASK(7, 2)
 130 +#define SPEED_PLL_VALUE_16             FIELD_PREP(SPEED_PLL_MASK, 0x10)
 131 +
 132 +#define COMPHY_DIG_LOOPBACK_EN         0x23
 133 +#define SEL_DATA_WIDTH_MASK            GENMASK(11, 10)
 134 +#define DATA_WIDTH_10BIT               FIELD_PREP(SEL_DATA_WIDTH_MASK, 0x0)
 135 +#define DATA_WIDTH_20BIT               FIELD_PREP(SEL_DATA_WIDTH_MASK, 0x1)
 136 +#define DATA_WIDTH_40BIT               FIELD_PREP(SEL_DATA_WIDTH_MASK, 0x2)
 137 +#define PLL_READY_TX_BIT               BIT(4)
 138 +
 139 +#define COMPHY_SYNC_PATTERN            0x24
 140 +#define TXD_INVERT_BIT                 BIT(10)
 141 +#define RXD_INVERT_BIT                 BIT(11)
 142 +
 143 +#define COMPHY_SYNC_MASK_GEN           0x25
 144 +#define PHY_GEN_MAX_MASK               GENMASK(11, 10)
 145 +#define PHY_GEN_MAX_USB3_5G            FIELD_PREP(PHY_GEN_MAX_MASK, 0x1)
 146 +
 147 +#define COMPHY_ISOLATION_CTRL          0x26
 148 +#define PHY_ISOLATE_MODE               BIT(15)
 149 +
 150 +#define COMPHY_GEN2_SET2               0x3e
 151 +#define GS2_TX_SSC_AMP_MASK            GENMASK(15, 9)
 152 +#define GS2_TX_SSC_AMP_4128            FIELD_PREP(GS2_TX_SSC_AMP_MASK, 0x20)
 153 +#define GS2_VREG_RXTX_MAS_ISET_MASK    GENMASK(8, 7)
 154 +#define GS2_VREG_RXTX_MAS_ISET_60U     FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\
 155 +                                                  0x0)
 156 +#define GS2_VREG_RXTX_MAS_ISET_80U     FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\
 157 +                                                  0x1)
 158 +#define GS2_VREG_RXTX_MAS_ISET_100U    FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\
 159 +                                                  0x2)
 160 +#define GS2_VREG_RXTX_MAS_ISET_120U    FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\
 161 +                                                  0x3)
 162 +#define GS2_RSVD_6_0_MASK              GENMASK(6, 0)
 163 +
 164 +#define COMPHY_GEN3_SET2               0x3f
 165 +
 166 +#define COMPHY_IDLE_SYNC_EN            0x48
 167 +#define IDLE_SYNC_EN                   BIT(12)
 168 +
 169 +#define COMPHY_MISC_CTRL0              0x4F
 170 +#define CLK100M_125M_EN                        BIT(4)
 171 +#define TXDCLK_2X_SEL                  BIT(6)
 172 +#define CLK500M_EN                     BIT(7)
 173 +#define PHY_REF_CLK_SEL                        BIT(10)
 174 +
 175 +#define COMPHY_SFT_RESET               0x52
 176 +#define SFT_RST                                BIT(9)
 177 +#define SFT_RST_NO_REG                 BIT(10)
 178 +
 179 +#define COMPHY_MISC_CTRL1              0x73
 180 +#define SEL_BITS_PCIE_FORCE            BIT(15)
 181 +
 182 +#define COMPHY_GEN2_SET3               0x112
 183 +#define GS3_FFE_CAP_SEL_MASK           GENMASK(3, 0)
 184 +#define GS3_FFE_CAP_SEL_VALUE          FIELD_PREP(GS3_FFE_CAP_SEL_MASK, 0xF)
 185 +
 186 +/* PIPE registers */
 187 +#define COMPHY_PIPE_LANE_CFG0          0x180
 188 +#define PRD_TXDEEMPH0_MASK             BIT(0)
 189 +#define PRD_TXMARGIN_MASK              GENMASK(3, 1)
 190 +#define PRD_TXSWING_MASK               BIT(4)
 191 +#define CFG_TX_ALIGN_POS_MASK          GENMASK(8, 5)
 192 +
 193 +#define COMPHY_PIPE_LANE_CFG1          0x181
 194 +#define PRD_TXDEEMPH1_MASK             BIT(15)
 195 +#define USE_MAX_PLL_RATE_EN            BIT(9)
 196 +#define TX_DET_RX_MODE                 BIT(6)
 197 +#define GEN2_TX_DATA_DLY_MASK          GENMASK(4, 3)
 198 +#define GEN2_TX_DATA_DLY_DEFT          FIELD_PREP(GEN2_TX_DATA_DLY_MASK, 2)
 199 +#define TX_ELEC_IDLE_MODE_EN           BIT(0)
 200 +
 201 +#define COMPHY_PIPE_LANE_STAT1         0x183
 202 +#define TXDCLK_PCLK_EN                 BIT(0)
 203 +
 204 +#define COMPHY_PIPE_LANE_CFG4          0x188
 205 +#define SPREAD_SPECTRUM_CLK_EN         BIT(7)
 206 +
 207 +#define COMPHY_PIPE_RST_CLK_CTRL       0x1C1
 208 +#define PIPE_SOFT_RESET                        BIT(0)
 209 +#define PIPE_REG_RESET                 BIT(1)
 210 +#define MODE_CORE_CLK_FREQ_SEL         BIT(9)
 211 +#define MODE_PIPE_WIDTH_32             BIT(3)
 212 +#define MODE_REFDIV_MASK               GENMASK(5, 4)
 213 +#define MODE_REFDIV_BY_4               FIELD_PREP(MODE_REFDIV_MASK, 0x2)
 214 +
 215 +#define COMPHY_PIPE_TEST_MODE_CTRL     0x1C2
 216 +#define MODE_MARGIN_OVERRIDE           BIT(2)
 217 +
 218 +#define COMPHY_PIPE_CLK_SRC_LO         0x1C3
 219 +#define MODE_CLK_SRC                   BIT(0)
 220 +#define BUNDLE_PERIOD_SEL              BIT(1)
 221 +#define BUNDLE_PERIOD_SCALE_MASK       GENMASK(3, 2)
 222 +#define BUNDLE_SAMPLE_CTRL             BIT(4)
 223 +#define PLL_READY_DLY_MASK             GENMASK(7, 5)
 224 +#define CFG_SEL_20B                    BIT(15)
 225 +
 226 +#define COMPHY_PIPE_PWR_MGM_TIM1       0x1D0
 227 +#define CFG_PM_OSCCLK_WAIT_MASK                GENMASK(15, 12)
 228 +#define CFG_PM_RXDEN_WAIT_MASK         GENMASK(11, 8)
 229 +#define CFG_PM_RXDEN_WAIT_1_UNIT       FIELD_PREP(CFG_PM_RXDEN_WAIT_MASK, 0x1)
 230 +#define CFG_PM_RXDLOZ_WAIT_MASK                GENMASK(7, 0)
 231 +#define CFG_PM_RXDLOZ_WAIT_7_UNIT      FIELD_PREP(CFG_PM_RXDLOZ_WAIT_MASK, 0x7)
 232 +#define CFG_PM_RXDLOZ_WAIT_12_UNIT     FIELD_PREP(CFG_PM_RXDLOZ_WAIT_MASK, 0xC)
 233 +
 234 +/*
 235 + * This register is not from PHY lane register space. It only exists in the
 236 + * indirect register space, before the actual PHY lane 2 registers. So the
 237 + * offset is absolute, not relative to COMPHY_LANE2_REGS_BASE.
 238 + * It is used only for SATA PHY initialization.
 239 + */
 240 +#define COMPHY_RESERVED_REG            0x0E
 241 +#define PHYCTRL_FRM_PIN_BIT            BIT(13)
 242
 243 -/* COMPHY Fast SMC function identifiers */
 244 -#define COMPHY_SIP_POWER_ON                    0x82000001
 245 -#define COMPHY_SIP_POWER_OFF                   0x82000002
 246 -#define COMPHY_SIP_PLL_LOCK                    0x82000003
 247 -
 248 -#define COMPHY_FW_MODE_SATA                    0x1
 249 -#define COMPHY_FW_MODE_SGMII                   0x2
 250 -#define COMPHY_FW_MODE_2500BASEX               0x3
 251 -#define COMPHY_FW_MODE_USB3H                   0x4
 252 -#define COMPHY_FW_MODE_USB3D                   0x5
 253 -#define COMPHY_FW_MODE_PCIE                    0x6
 254 -#define COMPHY_FW_MODE_USB3                    0xa
 255 -
 256 -#define COMPHY_FW_SPEED_1_25G                  0 /* SGMII 1G */
 257 -#define COMPHY_FW_SPEED_2_5G                   1
 258 -#define COMPHY_FW_SPEED_3_125G                 2 /* 2500BASE-X */
 259 -#define COMPHY_FW_SPEED_5G                     3
 260 -#define COMPHY_FW_SPEED_MAX                    0x3F
 261 -
 262 -#define COMPHY_FW_MODE(mode)                   ((mode) << 12)
 263 -#define COMPHY_FW_NET(mode, idx, speed)                (COMPHY_FW_MODE(mode) | \
 264 -                                                ((idx) << 8) | \
 265 -                                                ((speed) << 2))
 266 -#define COMPHY_FW_PCIE(mode, speed, width)     (COMPHY_FW_NET(mode, 0, speed) | \
 267 -                                                ((width) << 18))
 268 +/* South Bridge PHY Configuration Registers */
 269 +#define COMPHY_PHY_REG(lane, reg)      (((1 - (lane)) * 0x28) + ((reg) & 0x3f))
 270 +
 271 +/*
 272 + * lane0: USB3/GbE1 PHY Configuration 1
 273 + * lane1: PCIe/GbE0 PHY Configuration 1
 274 + * (used only by SGMII code)
 275 + */
 276 +#define COMPHY_PHY_CFG1                        0x0
 277 +#define PIN_PU_IVREF_BIT               BIT(1)
 278 +#define PIN_RESET_CORE_BIT             BIT(11)
 279 +#define PIN_RESET_COMPHY_BIT           BIT(12)
 280 +#define PIN_PU_PLL_BIT                 BIT(16)
 281 +#define PIN_PU_RX_BIT                  BIT(17)
 282 +#define PIN_PU_TX_BIT                  BIT(18)
 283 +#define PIN_TX_IDLE_BIT                        BIT(19)
 284 +#define GEN_RX_SEL_MASK                        GENMASK(25, 22)
 285 +#define GEN_RX_SEL_VALUE(val)          FIELD_PREP(GEN_RX_SEL_MASK, (val))
 286 +#define GEN_TX_SEL_MASK                        GENMASK(29, 26)
 287 +#define GEN_TX_SEL_VALUE(val)          FIELD_PREP(GEN_TX_SEL_MASK, (val))
 288 +#define SERDES_SPEED_1_25_G            0x6
 289 +#define SERDES_SPEED_3_125_G           0x8
 290 +#define PHY_RX_INIT_BIT                        BIT(30)
 291 +
 292 +/*
 293 + * lane0: USB3/GbE1 PHY Status 1
 294 + * lane1: PCIe/GbE0 PHY Status 1
 295 + * (used only by SGMII code)
 296 + */
 297 +#define COMPHY_PHY_STAT1               0x18
 298 +#define PHY_RX_INIT_DONE_BIT           BIT(0)
 299 +#define PHY_PLL_READY_RX_BIT           BIT(2)
 300 +#define PHY_PLL_READY_TX_BIT           BIT(3)
 301 +
 302 +/* PHY Selector */
 303 +#define COMPHY_SELECTOR_PHY_REG                        0xFC
 304 +/* bit0: 0: Lane1 is GbE0; 1: Lane1 is PCIe */
 305 +#define COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT      BIT(0)
 306 +/* bit4: 0: Lane0 is GbE1; 1: Lane0 is USB3 */
 307 +#define COMPHY_SELECTOR_USB3_GBE1_SEL_BIT      BIT(4)
 308 +/* bit8: 0: Lane0 is USB3 instead of GbE1, Lane2 is SATA; 1: Lane2 is USB3 */
 309 +#define COMPHY_SELECTOR_USB3_PHY_SEL_BIT       BIT(8)
 310
 311  struct mvebu_a3700_comphy_conf {
 312         unsigned int lane;
 313         enum phy_mode mode;
 314         int submode;
 315 -       u32 fw_mode;
 316  };
 317
 318 -#define MVEBU_A3700_COMPHY_CONF(_lane, _mode, _smode, _fw)             \
 319 +#define MVEBU_A3700_COMPHY_CONF(_lane, _mode, _smode)                  \
 320         {                                                               \
 321                 .lane = _lane,                                          \
 322                 .mode = _mode,                                          \
 323                 .submode = _smode,                                      \
 324 -               .fw_mode = _fw,                                         \
 325         }
 326
 327 -#define MVEBU_A3700_COMPHY_CONF_GEN(_lane, _mode, _fw) \
 328 -       MVEBU_A3700_COMPHY_CONF(_lane, _mode, PHY_INTERFACE_MODE_NA, _fw)
 329 +#define MVEBU_A3700_COMPHY_CONF_GEN(_lane, _mode) \
 330 +       MVEBU_A3700_COMPHY_CONF(_lane, _mode, PHY_INTERFACE_MODE_NA)
 331
 332 -#define MVEBU_A3700_COMPHY_CONF_ETH(_lane, _smode, _fw) \
 333 -       MVEBU_A3700_COMPHY_CONF(_lane, PHY_MODE_ETHERNET, _smode, _fw)
 334 +#define MVEBU_A3700_COMPHY_CONF_ETH(_lane, _smode) \
 335 +       MVEBU_A3700_COMPHY_CONF(_lane, PHY_MODE_ETHERNET, _smode)
 336
 337  static const struct mvebu_a3700_comphy_conf mvebu_a3700_comphy_modes[] = {
 338         /* lane 0 */
 339 -       MVEBU_A3700_COMPHY_CONF_GEN(0, PHY_MODE_USB_HOST_SS,
 340 -                                   COMPHY_FW_MODE_USB3H),
 341 -       MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII,
 342 -                                   COMPHY_FW_MODE_SGMII),
 343 -       MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX,
 344 -                                   COMPHY_FW_MODE_2500BASEX),
 345 +       MVEBU_A3700_COMPHY_CONF_GEN(0, PHY_MODE_USB_HOST_SS),
 346 +       MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII),
 347 +       MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_1000BASEX),
 348 +       MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX),
 349         /* lane 1 */
 350 -       MVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),
 351 -       MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII,
 352 -                                   COMPHY_FW_MODE_SGMII),
 353 -       MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX,
 354 -                                   COMPHY_FW_MODE_2500BASEX),
 355 +       MVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE),
 356 +       MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII),
 357 +       MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_1000BASEX),
 358 +       MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX),
 359         /* lane 2 */
 360 -       MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
 361 -       MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_USB_HOST_SS,
 362 -                                   COMPHY_FW_MODE_USB3H),
 363 +       MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA),
 364 +       MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_USB_HOST_SS),
 365 +};
 366 +
 367 +struct mvebu_a3700_comphy_priv {
 368 +       void __iomem *comphy_regs;
 369 +       void __iomem *lane0_phy_regs; /* USB3 and GbE1 */
 370 +       void __iomem *lane1_phy_regs; /* PCIe and GbE0 */
 371 +       void __iomem *lane2_phy_indirect; /* SATA and USB3 */
 372 +       spinlock_t lock; /* for PHY selector access */
 373 +       bool xtal_is_40m;
 374  };
 375
 376  struct mvebu_a3700_comphy_lane {
 377 +       struct mvebu_a3700_comphy_priv *priv;
 378         struct device *dev;
 379         unsigned int id;
 380         enum phy_mode mode;
 381         int submode;
 382 +       bool invert_tx;
 383 +       bool invert_rx;
 384 +       bool needs_reset;
 385 +};
 386 +
 387 +struct gbe_phy_init_data_fix {
 388 +       u16 addr;
 389 +       u16 value;
 390 +};
 391 +
 392 +/* Changes to 40M1G25 mode data required for running 40M3G125 init mode */
 393 +static struct gbe_phy_init_data_fix gbe_phy_init_fix[] = {
 394 +       { 0x005, 0x07CC }, { 0x015, 0x0000 }, { 0x01B, 0x0000 },
 395 +       { 0x01D, 0x0000 }, { 0x01E, 0x0000 }, { 0x01F, 0x0000 },
 396 +       { 0x020, 0x0000 }, { 0x021, 0x0030 }, { 0x026, 0x0888 },
 397 +       { 0x04D, 0x0152 }, { 0x04F, 0xA020 }, { 0x050, 0x07CC },
 398 +       { 0x053, 0xE9CA }, { 0x055, 0xBD97 }, { 0x071, 0x3015 },
 399 +       { 0x076, 0x03AA }, { 0x07C, 0x0FDF }, { 0x0C2, 0x3030 },
 400 +       { 0x0C3, 0x8000 }, { 0x0E2, 0x5550 }, { 0x0E3, 0x12A4 },
 401 +       { 0x0E4, 0x7D00 }, { 0x0E6, 0x0C83 }, { 0x101, 0xFCC0 },
 402 +       { 0x104, 0x0C10 }
 403  };
 404
 405 -static int mvebu_a3700_comphy_smc(unsigned long function, unsigned long lane,
 406 -                                 unsigned long mode)
 407 +/* 40M1G25 mode init data */
 408 +static u16 gbe_phy_init[512] = {
 409 +       /* 0       1       2       3       4       5       6       7 */
 410 +       /*-----------------------------------------------------------*/
 411 +       /* 8       9       A       B       C       D       E       F */
 412 +       0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */
 413 +       0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */
 414 +       0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */
 415 +       0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */
 416 +       0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */
 417 +       0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */
 418 +       0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
 419 +       0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */
 420 +       0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */
 421 +       0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */
 422 +       0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */
 423 +       0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */
 424 +       0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */
 425 +       0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */
 426 +       0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */
 427 +       0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */
 428 +       0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */
 429 +       0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */
 430 +       0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */
 431 +       0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */
 432 +       0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */
 433 +       0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */
 434 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */
 435 +       0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */
 436 +       0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */
 437 +       0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */
 438 +       0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */
 439 +       0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */
 440 +       0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */
 441 +       0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */
 442 +       0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */
 443 +       0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */
 444 +       0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */
 445 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */
 446 +       0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */
 447 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */
 448 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */
 449 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */
 450 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */
 451 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */
 452 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */
 453 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */
 454 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */
 455 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */
 456 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */
 457 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */
 458 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */
 459 +       0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */
 460 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */
 461 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */
 462 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */
 463 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */
 464 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */
 465 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */
 466 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */
 467 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */
 468 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */
 469 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */
 470 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */
 471 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */
 472 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */
 473 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */
 474 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */
 475 +       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000  /*1F8 */
 476 +};
 477 +
 478 +static inline void comphy_reg_set(void __iomem *addr, u32 data, u32 mask)
 479  {
 480 -       struct arm_smccc_res res;
 481 -       s32 ret;
 482 +       u32 val;
 483
 484 -       arm_smccc_smc(function, lane, mode, 0, 0, 0, 0, 0, &res);
 485 -       ret = res.a0;
 486 +       val = readl(addr);
 487 +       val = (val & ~mask) | (data & mask);
 488 +       writel(val, addr);
 489 +}
 490
 491 -       switch (ret) {
 492 -       case SMCCC_RET_SUCCESS:
 493 -               return 0;
 494 -       case SMCCC_RET_NOT_SUPPORTED:
 495 -               return -EOPNOTSUPP;
 496 +static inline void comphy_reg_set16(void __iomem *addr, u16 data, u16 mask)
 497 +{
 498 +       u16 val;
 499 +
 500 +       val = readw(addr);
 501 +       val = (val & ~mask) | (data & mask);
 502 +       writew(val, addr);
 503 +}
 504 +
 505 +/* Used for accessing lane 2 registers (SATA/USB3 PHY) */
 506 +static void comphy_set_indirect(struct mvebu_a3700_comphy_priv *priv,
 507 +                               u32 offset, u16 data, u16 mask)
 508 +{
 509 +       writel(offset,
 510 +              priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_ADDR);
 511 +       comphy_reg_set(priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_DATA,
 512 +                      data, mask);
 513 +}
 514 +
 515 +static void comphy_lane_reg_set(struct mvebu_a3700_comphy_lane *lane,
 516 +                               u16 reg, u16 data, u16 mask)
 517 +{
 518 +       if (lane->id == 2) {
 519 +               /* lane 2 PHY registers are accessed indirectly */
 520 +               comphy_set_indirect(lane->priv,
 521 +                                   reg + COMPHY_LANE2_REGS_BASE,
 522 +                                   data, mask);
 523 +       } else {
 524 +               void __iomem *base = lane->id == 1 ?
 525 +                                    lane->priv->lane1_phy_regs :
 526 +                                    lane->priv->lane0_phy_regs;
 527 +
 528 +               comphy_reg_set16(base + COMPHY_LANE_REG_DIRECT(reg),
 529 +                                data, mask);
 530 +       }
 531 +}
 532 +
 533 +static int comphy_lane_reg_poll(struct mvebu_a3700_comphy_lane *lane,
 534 +                               u16 reg, u16 bits,
 535 +                               ulong sleep_us, ulong timeout_us)
 536 +{
 537 +       int ret;
 538 +
 539 +       if (lane->id == 2) {
 540 +               u32 data;
 541 +
 542 +               /* lane 2 PHY registers are accessed indirectly */
 543 +               writel(reg + COMPHY_LANE2_REGS_BASE,
 544 +                      lane->priv->lane2_phy_indirect +
 545 +                      COMPHY_LANE2_INDIR_ADDR);
 546 +
 547 +               ret = readl_poll_timeout(lane->priv->lane2_phy_indirect +
 548 +                                        COMPHY_LANE2_INDIR_DATA,
 549 +                                        data, (data & bits) == bits,
 550 +                                        sleep_us, timeout_us);
 551 +       } else {
 552 +               void __iomem *base = lane->id == 1 ?
 553 +                                    lane->priv->lane1_phy_regs :
 554 +                                    lane->priv->lane0_phy_regs;
 555 +               u16 data;
 556 +
 557 +               ret = readw_poll_timeout(base + COMPHY_LANE_REG_DIRECT(reg),
 558 +                                        data, (data & bits) == bits,
 559 +                                        sleep_us, timeout_us);
 560 +       }
 561 +
 562 +       return ret;
 563 +}
 564 +
 565 +static void comphy_periph_reg_set(struct mvebu_a3700_comphy_lane *lane,
 566 +                                 u8 reg, u32 data, u32 mask)
 567 +{
 568 +       comphy_reg_set(lane->priv->comphy_regs + COMPHY_PHY_REG(lane->id, reg),
 569 +                      data, mask);
 570 +}
 571 +
 572 +static int comphy_periph_reg_poll(struct mvebu_a3700_comphy_lane *lane,
 573 +                                 u8 reg, u32 bits,
 574 +                                 ulong sleep_us, ulong timeout_us)
 575 +{
 576 +       u32 data;
 577 +
 578 +       return readl_poll_timeout(lane->priv->comphy_regs +
 579 +                                 COMPHY_PHY_REG(lane->id, reg),
 580 +                                 data, (data & bits) == bits,
 581 +                                 sleep_us, timeout_us);
 582 +}
 583 +
 584 +/* PHY selector configures with corresponding modes */
 585 +static int
 586 +mvebu_a3700_comphy_set_phy_selector(struct mvebu_a3700_comphy_lane *lane)
 587 +{
 588 +       u32 old, new, clr = 0, set = 0;
 589 +       unsigned long flags;
 590 +
 591 +       switch (lane->mode) {
 592 +       case PHY_MODE_SATA:
 593 +               /* SATA must be in Lane2 */
 594 +               if (lane->id == 2)
 595 +                       clr = COMPHY_SELECTOR_USB3_PHY_SEL_BIT;
 596 +               else
 597 +                       goto error;
 598 +               break;
 599 +
 600 +       case PHY_MODE_ETHERNET:
 601 +               if (lane->id == 0)
 602 +                       clr = COMPHY_SELECTOR_USB3_GBE1_SEL_BIT;
 603 +               else if (lane->id == 1)
 604 +                       clr = COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT;
 605 +               else
 606 +                       goto error;
 607 +               break;
 608 +
 609 +       case PHY_MODE_USB_HOST_SS:
 610 +               if (lane->id == 2)
 611 +                       set = COMPHY_SELECTOR_USB3_PHY_SEL_BIT;
 612 +               else if (lane->id == 0)
 613 +                       set = COMPHY_SELECTOR_USB3_GBE1_SEL_BIT;
 614 +               else
 615 +                       goto error;
 616 +               break;
 617 +
 618 +       case PHY_MODE_PCIE:
 619 +               /* PCIE must be in Lane1 */
 620 +               if (lane->id == 1)
 621 +                       set = COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT;
 622 +               else
 623 +                       goto error;
 624 +               break;
 625 +
 626 +       default:
 627 +               goto error;
 628 +       }
 629 +
 630 +       spin_lock_irqsave(&lane->priv->lock, flags);
 631 +
 632 +       old = readl(lane->priv->comphy_regs + COMPHY_SELECTOR_PHY_REG);
 633 +       new = (old & ~clr) | set;
 634 +       writel(new, lane->priv->comphy_regs + COMPHY_SELECTOR_PHY_REG);
 635 +
 636 +       spin_unlock_irqrestore(&lane->priv->lock, flags);
 637 +
 638 +       dev_dbg(lane->dev,
 639 +               "COMPHY[%d] mode[%d] changed PHY selector 0x%08x -> 0x%08x\n",
 640 +               lane->id, lane->mode, old, new);
 641 +
 642 +       return 0;
 643 +error:
 644 +       dev_err(lane->dev, "COMPHY[%d] mode[%d] is invalid\n", lane->id,
 645 +               lane->mode);
 646 +       return -EINVAL;
 647 +}
 648 +
 649 +static int
 650 +mvebu_a3700_comphy_sata_power_on(struct mvebu_a3700_comphy_lane *lane)
 651 +{
 652 +       u32 mask, data, ref_clk;
 653 +       int ret;
 654 +
 655 +       /* Configure phy selector for SATA */
 656 +       ret = mvebu_a3700_comphy_set_phy_selector(lane);
 657 +       if (ret)
 658 +               return ret;
 659 +
 660 +       /* Clear phy isolation mode to make it work in normal mode */
 661 +       comphy_lane_reg_set(lane, COMPHY_ISOLATION_CTRL,
 662 +                           0x0, PHY_ISOLATE_MODE);
 663 +
 664 +       /* 0. Check the Polarity invert bits */
 665 +       data = 0x0;
 666 +       if (lane->invert_tx)
 667 +               data |= TXD_INVERT_BIT;
 668 +       if (lane->invert_rx)
 669 +               data |= RXD_INVERT_BIT;
 670 +       mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
 671 +       comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);
 672 +
 673 +       /* 1. Select 40-bit data width */
 674 +       comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN,
 675 +                           DATA_WIDTH_40BIT, SEL_DATA_WIDTH_MASK);
 676 +
 677 +       /* 2. Select reference clock(25M) and PHY mode (SATA) */
 678 +       if (lane->priv->xtal_is_40m)
 679 +               ref_clk = REF_FREF_SEL_SERDES_40MHZ;
 680 +       else
 681 +               ref_clk = REF_FREF_SEL_SERDES_25MHZ;
 682 +
 683 +       data = ref_clk | COMPHY_MODE_SATA;
 684 +       mask = REF_FREF_SEL_MASK | COMPHY_MODE_MASK;
 685 +       comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
 686 +
 687 +       /* 3. Use maximum PLL rate (no power save) */
 688 +       comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL,
 689 +                           USE_MAX_PLL_RATE_BIT, USE_MAX_PLL_RATE_BIT);
 690 +
 691 +       /* 4. Reset reserved bit */
 692 +       comphy_set_indirect(lane->priv, COMPHY_RESERVED_REG,
 693 +                           0x0, PHYCTRL_FRM_PIN_BIT);
 694 +
 695 +       /* 5. Set vendor-specific configuration (It is done in sata driver) */
 696 +       /* XXX: in U-Boot below sequence was executed in this place, in Linux
 697 +        * not.  Now it is done only in U-Boot before this comphy
 698 +        * initialization - tests shows that it works ok, but in case of any
 699 +        * future problem it is left for reference.
 700 +        *   reg_set(MVEBU_REGS_BASE + 0xe00a0, 0, 0xffffffff);
 701 +        *   reg_set(MVEBU_REGS_BASE + 0xe00a4, BIT(6), BIT(6));
 702 +        */
 703 +
 704 +       /* Wait for > 55 us to allow PLL be enabled */
 705 +       udelay(PLL_SET_DELAY_US);
 706 +
 707 +       /* Polling status */
 708 +       ret = comphy_lane_reg_poll(lane, COMPHY_DIG_LOOPBACK_EN,
 709 +                                  PLL_READY_TX_BIT, COMPHY_PLL_SLEEP,
 710 +                                  COMPHY_PLL_TIMEOUT);
 711 +       if (ret) {
 712 +               dev_err(lane->dev, "Failed to lock SATA PLL\n");
 713 +               return ret;
 714 +       }
 715 +
 716 +       return 0;
 717 +}
 718 +
 719 +static void comphy_gbe_phy_init(struct mvebu_a3700_comphy_lane *lane,
 720 +                               bool is_1gbps)
 721 +{
 722 +       int addr, fix_idx;
 723 +       u16 val;
 724 +
 725 +       fix_idx = 0;
 726 +       for (addr = 0; addr < 512; addr++) {
 727 +               /*
 728 +                * All PHY register values are defined in full for 3.125Gbps
 729 +                * SERDES speed. The values required for 1.25 Gbps are almost
 730 +                * the same and only few registers should be "fixed" in
 731 +                * comparison to 3.125 Gbps values. These register values are
 732 +                * stored in "gbe_phy_init_fix" array.
 733 +                */
 734 +               if (!is_1gbps && gbe_phy_init_fix[fix_idx].addr == addr) {
 735 +                       /* Use new value */
 736 +                       val = gbe_phy_init_fix[fix_idx].value;
 737 +                       if (fix_idx < ARRAY_SIZE(gbe_phy_init_fix))
 738 +                               fix_idx++;
 739 +               } else {
 740 +                       val = gbe_phy_init[addr];
 741 +               }
 742 +
 743 +               comphy_lane_reg_set(lane, addr, val, 0xFFFF);
 744 +       }
 745 +}
 746 +
 747 +static int
 748 +mvebu_a3700_comphy_ethernet_power_on(struct mvebu_a3700_comphy_lane *lane)
 749 +{
 750 +       u32 mask, data, speed_sel;
 751 +       int ret;
 752 +
 753 +       /* Set selector */
 754 +       ret = mvebu_a3700_comphy_set_phy_selector(lane);
 755 +       if (ret)
 756 +               return ret;
 757 +
 758 +       /*
 759 +        * 1. Reset PHY by setting PHY input port PIN_RESET=1.
 760 +        * 2. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep
 761 +        *    PHY TXP/TXN output to idle state during PHY initialization
 762 +        * 3. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0.
 763 +        */
 764 +       data = PIN_PU_IVREF_BIT | PIN_TX_IDLE_BIT | PIN_RESET_COMPHY_BIT;
 765 +       mask = data | PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT |
 766 +              PIN_PU_TX_BIT | PHY_RX_INIT_BIT;
 767 +       comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
 768 +
 769 +       /* 4. Release reset to the PHY by setting PIN_RESET=0. */
 770 +       data = 0x0;
 771 +       mask = PIN_RESET_COMPHY_BIT;
 772 +       comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
 773 +
 774 +       /*
 775 +        * 5. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide COMPHY
 776 +        * bit rate
 777 +        */
 778 +       switch (lane->submode) {
 779 +       case PHY_INTERFACE_MODE_SGMII:
 780 +       case PHY_INTERFACE_MODE_1000BASEX:
 781 +               /* SGMII 1G, SerDes speed 1.25G */
 782 +               speed_sel = SERDES_SPEED_1_25_G;
 783 +               break;
 784 +       case PHY_INTERFACE_MODE_2500BASEX:
 785 +               /* 2500Base-X, SerDes speed 3.125G */
 786 +               speed_sel = SERDES_SPEED_3_125_G;
 787 +               break;
 788         default:
 789 +               /* Other rates are not supported */
 790 +               dev_err(lane->dev,
 791 +                       "unsupported phy speed %d on comphy lane%d\n",
 792 +                       lane->submode, lane->id);
 793                 return -EINVAL;
 794         }
 795 +       data = GEN_RX_SEL_VALUE(speed_sel) | GEN_TX_SEL_VALUE(speed_sel);
 796 +       mask = GEN_RX_SEL_MASK | GEN_TX_SEL_MASK;
 797 +       comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
 798 +
 799 +       /*
 800 +        * 6. Wait 10mS for bandgap and reference clocks to stabilize; then
 801 +        * start SW programming.
 802 +        */
 803 +       mdelay(10);
 804 +
 805 +       /* 7. Program COMPHY register PHY_MODE */
 806 +       data = COMPHY_MODE_SERDES;
 807 +       mask = COMPHY_MODE_MASK;
 808 +       comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
 809 +
 810 +       /*
 811 +        * 8. Set COMPHY register REFCLK_SEL to select the correct REFCLK
 812 +        * source
 813 +        */
 814 +       data = 0x0;
 815 +       mask = PHY_REF_CLK_SEL;
 816 +       comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask);
 817 +
 818 +       /*
 819 +        * 9. Set correct reference clock frequency in COMPHY register
 820 +        * REF_FREF_SEL.
 821 +        */
 822 +       if (lane->priv->xtal_is_40m)
 823 +               data = REF_FREF_SEL_SERDES_50MHZ;
 824 +       else
 825 +               data = REF_FREF_SEL_SERDES_25MHZ;
 826 +
 827 +       mask = REF_FREF_SEL_MASK;
 828 +       comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
 829 +
 830 +       /* 10. Program COMPHY register PHY_GEN_MAX[1:0]
 831 +        * This step is mentioned in the flow received from verification team.
 832 +        * However the PHY_GEN_MAX value is only meaningful for other interfaces
 833 +        * (not SERDES). For instance, it selects SATA speed 1.5/3/6 Gbps or
 834 +        * PCIe speed 2.5/5 Gbps
 835 +        */
 836 +
 837 +       /*
 838 +        * 11. Program COMPHY register SEL_BITS to set correct parallel data
 839 +        * bus width
 840 +        */
 841 +       data = DATA_WIDTH_10BIT;
 842 +       mask = SEL_DATA_WIDTH_MASK;
 843 +       comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, data, mask);
 844 +
 845 +       /*
 846 +        * 12. As long as DFE function needs to be enabled in any mode,
 847 +        * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F
 848 +        * for real chip during COMPHY power on.
 849 +        * The step 14 exists (and empty) in the original initialization flow
 850 +        * obtained from the verification team. According to the functional
 851 +        * specification DFE_UPDATE_EN already has the default value 0x3F
 852 +        */
 853 +
 854 +       /*
 855 +        * 13. Program COMPHY GEN registers.
 856 +        * These registers should be programmed based on the lab testing result
 857 +        * to achieve optimal performance. Please contact the CEA group to get
 858 +        * the related GEN table during real chip bring-up. We only required to
 859 +        * run though the entire registers programming flow defined by
 860 +        * "comphy_gbe_phy_init" when the REF clock is 40 MHz. For REF clock
 861 +        * 25 MHz the default values stored in PHY registers are OK.
 862 +        */
 863 +       dev_dbg(lane->dev, "Running C-DPI phy init %s mode\n",
 864 +               lane->submode == PHY_INTERFACE_MODE_2500BASEX ? "2G5" : "1G");
 865 +       if (lane->priv->xtal_is_40m)
 866 +               comphy_gbe_phy_init(lane,
 867 +                                   lane->submode != PHY_INTERFACE_MODE_2500BASEX);
 868 +
 869 +       /*
 870 +        * 14. [Simulation Only] should not be used for real chip.
 871 +        * By pass power up calibration by programming EXT_FORCE_CAL_DONE
 872 +        * (R02h[9]) to 1 to shorten COMPHY simulation time.
 873 +        */
 874 +
 875 +       /*
 876 +        * 15. [Simulation Only: should not be used for real chip]
 877 +        * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX training
 878 +        * simulation time.
 879 +        */
 880 +
 881 +       /*
 882 +        * 16. Check the PHY Polarity invert bit
 883 +        */
 884 +       data = 0x0;
 885 +       if (lane->invert_tx)
 886 +               data |= TXD_INVERT_BIT;
 887 +       if (lane->invert_rx)
 888 +               data |= RXD_INVERT_BIT;
 889 +       mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
 890 +       comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);
 891 +
 892 +       /*
 893 +        * 17. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to
 894 +        * start PHY power up sequence. All the PHY register programming should
 895 +        * be done before PIN_PU_PLL=1. There should be no register programming
 896 +        * for normal PHY operation from this point.
 897 +        */
 898 +       data = PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT;
 899 +       mask = data;
 900 +       comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
 901 +
 902 +       /*
 903 +        * 18. Wait for PHY power up sequence to finish by checking output ports
 904 +        * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1.
 905 +        */
 906 +       ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1,
 907 +                                    PHY_PLL_READY_TX_BIT |
 908 +                                    PHY_PLL_READY_RX_BIT,
 909 +                                    COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT);
 910 +       if (ret) {
 911 +               dev_err(lane->dev, "Failed to lock PLL for SERDES PHY %d\n",
 912 +                       lane->id);
 913 +               return ret;
 914 +       }
 915 +
 916 +       /*
 917 +        * 19. Set COMPHY input port PIN_TX_IDLE=0
 918 +        */
 919 +       comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, 0x0, PIN_TX_IDLE_BIT);
 920 +
 921 +       /*
 922 +        * 20. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To
 923 +        * start RX initialization. PIN_RX_INIT_DONE will be cleared to 0 by the
 924 +        * PHY After RX initialization is done, PIN_RX_INIT_DONE will be set to
 925 +        * 1 by COMPHY Set PIN_RX_INIT=0 after PIN_RX_INIT_DONE= 1. Please
 926 +        * refer to RX initialization part for details.
 927 +        */
 928 +       comphy_periph_reg_set(lane, COMPHY_PHY_CFG1,
 929 +                             PHY_RX_INIT_BIT, PHY_RX_INIT_BIT);
 930 +
 931 +       ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1,
 932 +                                    PHY_PLL_READY_TX_BIT |
 933 +                                    PHY_PLL_READY_RX_BIT,
 934 +                                    COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT);
 935 +       if (ret) {
 936 +               dev_err(lane->dev, "Failed to lock PLL for SERDES PHY %d\n",
 937 +                       lane->id);
 938 +               return ret;
 939 +       }
 940 +
 941 +       ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1,
 942 +                                    PHY_RX_INIT_DONE_BIT,
 943 +                                    COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT);
 944 +       if (ret) {
 945 +               dev_err(lane->dev, "Failed to init RX of SERDES PHY %d\n",
 946 +                       lane->id);
 947 +               return ret;
 948 +       }
 949 +
 950 +       return 0;
 951  }
 952
 953 -static int mvebu_a3700_comphy_get_fw_mode(int lane,
 954 +static int
 955 +mvebu_a3700_comphy_usb3_power_on(struct mvebu_a3700_comphy_lane *lane)
 956 +{
 957 +       u32 mask, data, cfg, ref_clk;
 958 +       int ret;
 959 +
 960 +       /* Set phy seclector */
 961 +       ret = mvebu_a3700_comphy_set_phy_selector(lane);
 962 +       if (ret)
 963 +               return ret;
 964 +
 965 +       /*
 966 +        * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The
 967 +        * register belong to UTMI module, so it is set in UTMI phy driver.
 968 +        */
 969 +
 970 +       /*
 971 +        * 1. Set PRD_TXDEEMPH (3.5db de-emph)
 972 +        */
 973 +       data = PRD_TXDEEMPH0_MASK;
 974 +       mask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK |
 975 +              CFG_TX_ALIGN_POS_MASK;
 976 +       comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG0, data, mask);
 977 +
 978 +       /*
 979 +        * 2. Set BIT0: enable transmitter in high impedance mode
 980 +        *    Set BIT[3:4]: delay 2 clock cycles for HiZ off latency
 981 +        *    Set BIT6: Tx detect Rx at HiZ mode
 982 +        *    Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db
 983 +        *            together with bit 0 of COMPHY_PIPE_LANE_CFG0 register
 984 +        */
 985 +       data = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN;
 986 +       mask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK |
 987 +              TX_ELEC_IDLE_MODE_EN;
 988 +       comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1, data, mask);
 989 +
 990 +       /*
 991 +        * 3. Set Spread Spectrum Clock Enabled
 992 +        */
 993 +       comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG4,
 994 +                           SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN);
 995 +
 996 +       /*
 997 +        * 4. Set Override Margining Controls From the MAC:
 998 +        *    Use margining signals from lane configuration
 999 +        */
1000 +       comphy_lane_reg_set(lane, COMPHY_PIPE_TEST_MODE_CTRL,
1001 +                           MODE_MARGIN_OVERRIDE, 0xFFFF);
1002 +
1003 +       /*
1004 +        * 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles
1005 +        *    set Mode Clock Source = PCLK is generated from REFCLK
1006 +        */
1007 +       data = 0x0;
1008 +       mask = MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE_MASK |
1009 +              BUNDLE_SAMPLE_CTRL | PLL_READY_DLY_MASK;
1010 +       comphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO, data, mask);
1011 +
1012 +       /*
1013 +        * 6. Set G2 Spread Spectrum Clock Amplitude at 4K
1014 +        */
1015 +       comphy_lane_reg_set(lane, COMPHY_GEN2_SET2,
1016 +                           GS2_TX_SSC_AMP_4128, GS2_TX_SSC_AMP_MASK);
1017 +
1018 +       /*
1019 +        * 7. Unset G3 Spread Spectrum Clock Amplitude
1020 +        *    set G3 TX and RX Register Master Current Select
1021 +        */
1022 +       data = GS2_VREG_RXTX_MAS_ISET_60U;
1023 +       mask = GS2_TX_SSC_AMP_MASK | GS2_VREG_RXTX_MAS_ISET_MASK |
1024 +              GS2_RSVD_6_0_MASK;
1025 +       comphy_lane_reg_set(lane, COMPHY_GEN3_SET2, data, mask);
1026 +
1027 +       /*
1028 +        * 8. Check crystal jumper setting and program the Power and PLL Control
1029 +        * accordingly Change RX wait
1030 +        */
1031 +       if (lane->priv->xtal_is_40m) {
1032 +               ref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ;
1033 +               cfg = CFG_PM_RXDLOZ_WAIT_12_UNIT;
1034 +       } else {
1035 +               ref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ;
1036 +               cfg = CFG_PM_RXDLOZ_WAIT_7_UNIT;
1037 +       }
1038 +
1039 +       data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |
1040 +              PU_TX_INTP_BIT | PU_DFE_BIT | COMPHY_MODE_USB3 | ref_clk;
1041 +       mask = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |
1042 +              PU_TX_INTP_BIT | PU_DFE_BIT | PLL_LOCK_BIT | COMPHY_MODE_MASK |
1043 +              REF_FREF_SEL_MASK;
1044 +       comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
1045 +
1046 +       data = CFG_PM_RXDEN_WAIT_1_UNIT | cfg;
1047 +       mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK |
1048 +              CFG_PM_RXDLOZ_WAIT_MASK;
1049 +       comphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask);
1050 +
1051 +       /*
1052 +        * 9. Enable idle sync
1053 +        */
1054 +       comphy_lane_reg_set(lane, COMPHY_IDLE_SYNC_EN,
1055 +                           IDLE_SYNC_EN, IDLE_SYNC_EN);
1056 +
1057 +       /*
1058 +        * 10. Enable the output of 500M clock
1059 +        */
1060 +       comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, CLK500M_EN, CLK500M_EN);
1061 +
1062 +       /*
1063 +        * 11. Set 20-bit data width
1064 +        */
1065 +       comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN,
1066 +                           DATA_WIDTH_20BIT, 0xFFFF);
1067 +
1068 +       /*
1069 +        * 12. Override Speed_PLL value and use MAC PLL
1070 +        */
1071 +       data = SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT;
1072 +       mask = 0xFFFF;
1073 +       comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, data, mask);
1074 +
1075 +       /*
1076 +        * 13. Check the Polarity invert bit
1077 +        */
1078 +       data = 0x0;
1079 +       if (lane->invert_tx)
1080 +               data |= TXD_INVERT_BIT;
1081 +       if (lane->invert_rx)
1082 +               data |= RXD_INVERT_BIT;
1083 +       mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
1084 +       comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);
1085 +
1086 +       /*
1087 +        * 14. Set max speed generation to USB3.0 5Gbps
1088 +        */
1089 +       comphy_lane_reg_set(lane, COMPHY_SYNC_MASK_GEN,
1090 +                           PHY_GEN_MAX_USB3_5G, PHY_GEN_MAX_MASK);
1091 +
1092 +       /*
1093 +        * 15. Set capacitor value for FFE gain peaking to 0xF
1094 +        */
1095 +       comphy_lane_reg_set(lane, COMPHY_GEN2_SET3,
1096 +                           GS3_FFE_CAP_SEL_VALUE, GS3_FFE_CAP_SEL_MASK);
1097 +
1098 +       /*
1099 +        * 16. Release SW reset
1100 +        */
1101 +       data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4;
1102 +       mask = 0xFFFF;
1103 +       comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask);
1104 +
1105 +       /* Wait for > 55 us to allow PCLK be enabled */
1106 +       udelay(PLL_SET_DELAY_US);
1107 +
1108 +       ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN,
1109 +                                  COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT);
1110 +       if (ret) {
1111 +               dev_err(lane->dev, "Failed to lock USB3 PLL\n");
1112 +               return ret;
1113 +       }
1114 +
1115 +       return 0;
1116 +}
1117 +
1118 +static int
1119 +mvebu_a3700_comphy_pcie_power_on(struct mvebu_a3700_comphy_lane *lane)
1120 +{
1121 +       u32 mask, data, ref_clk;
1122 +       int ret;
1123 +
1124 +       /* Configure phy selector for PCIe */
1125 +       ret = mvebu_a3700_comphy_set_phy_selector(lane);
1126 +       if (ret)
1127 +               return ret;
1128 +
1129 +       /* 1. Enable max PLL. */
1130 +       comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1,
1131 +                           USE_MAX_PLL_RATE_EN, USE_MAX_PLL_RATE_EN);
1132 +
1133 +       /* 2. Select 20 bit SERDES interface. */
1134 +       comphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO,
1135 +                           CFG_SEL_20B, CFG_SEL_20B);
1136 +
1137 +       /* 3. Force to use reg setting for PCIe mode */
1138 +       comphy_lane_reg_set(lane, COMPHY_MISC_CTRL1,
1139 +                           SEL_BITS_PCIE_FORCE, SEL_BITS_PCIE_FORCE);
1140 +
1141 +       /* 4. Change RX wait */
1142 +       data = CFG_PM_RXDEN_WAIT_1_UNIT | CFG_PM_RXDLOZ_WAIT_12_UNIT;
1143 +       mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK |
1144 +              CFG_PM_RXDLOZ_WAIT_MASK;
1145 +       comphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask);
1146 +
1147 +       /* 5. Enable idle sync */
1148 +       comphy_lane_reg_set(lane, COMPHY_IDLE_SYNC_EN,
1149 +                           IDLE_SYNC_EN, IDLE_SYNC_EN);
1150 +
1151 +       /* 6. Enable the output of 100M/125M/500M clock */
1152 +       data = CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN;
1153 +       mask = data;
1154 +       comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask);
1155 +
1156 +       /*
1157 +        * 7. Enable TX, PCIE global register, 0xd0074814, it is done in
1158 +        * PCI-E driver
1159 +        */
1160 +
1161 +       /*
1162 +        * 8. Check crystal jumper setting and program the Power and PLL
1163 +        * Control accordingly
1164 +        */
1165 +
1166 +       if (lane->priv->xtal_is_40m)
1167 +               ref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ;
1168 +       else
1169 +               ref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ;
1170 +
1171 +       data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |
1172 +              PU_TX_INTP_BIT | PU_DFE_BIT | COMPHY_MODE_PCIE | ref_clk;
1173 +       mask = 0xFFFF;
1174 +       comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);
1175 +
1176 +       /* 9. Override Speed_PLL value and use MAC PLL */
1177 +       comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL,
1178 +                           SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT,
1179 +                           0xFFFF);
1180 +
1181 +       /* 10. Check the Polarity invert bit */
1182 +       data = 0x0;
1183 +       if (lane->invert_tx)
1184 +               data |= TXD_INVERT_BIT;
1185 +       if (lane->invert_rx)
1186 +               data |= RXD_INVERT_BIT;
1187 +       mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
1188 +       comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);
1189 +
1190 +       /* 11. Release SW reset */
1191 +       data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32;
1192 +       mask = data | PIPE_SOFT_RESET | MODE_REFDIV_MASK;
1193 +       comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask);
1194 +
1195 +       /* Wait for > 55 us to allow PCLK be enabled */
1196 +       udelay(PLL_SET_DELAY_US);
1197 +
1198 +       ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN,
1199 +                                  COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT);
1200 +       if (ret) {
1201 +               dev_err(lane->dev, "Failed to lock PCIE PLL\n");
1202 +               return ret;
1203 +       }
1204 +
1205 +       return 0;
1206 +}
1207 +
1208 +static void
1209 +mvebu_a3700_comphy_usb3_power_off(struct mvebu_a3700_comphy_lane *lane)
1210 +{
1211 +       /*
1212 +        * Currently the USB3 MAC sets the USB3 PHY to low state, so we do not
1213 +        * need to power off USB3 PHY again.
1214 +        */
1215 +}
1216 +
1217 +static void
1218 +mvebu_a3700_comphy_sata_power_off(struct mvebu_a3700_comphy_lane *lane)
1219 +{
1220 +       /* Set phy isolation mode */
1221 +       comphy_lane_reg_set(lane, COMPHY_ISOLATION_CTRL,
1222 +                           PHY_ISOLATE_MODE, PHY_ISOLATE_MODE);
1223 +
1224 +       /* Power off PLL, Tx, Rx */
1225 +       comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL,
1226 +                           0x0, PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT);
1227 +}
1228 +
1229 +static void
1230 +mvebu_a3700_comphy_ethernet_power_off(struct mvebu_a3700_comphy_lane *lane)
1231 +{
1232 +       u32 mask, data;
1233 +
1234 +       data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT | PIN_PU_IVREF_BIT |
1235 +              PHY_RX_INIT_BIT;
1236 +       mask = data;
1237 +       comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
1238 +}
1239 +
1240 +static void
1241 +mvebu_a3700_comphy_pcie_power_off(struct mvebu_a3700_comphy_lane *lane)
1242 +{
1243 +       /* Power off PLL, Tx, Rx */
1244 +       comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL,
1245 +                           0x0, PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT);
1246 +}
1247 +
1248 +static int mvebu_a3700_comphy_reset(struct phy *phy)
1249 +{
1250 +       struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
1251 +       u16 mask, data;
1252 +
1253 +       dev_dbg(lane->dev, "resetting lane %d\n", lane->id);
1254 +
1255 +       /* COMPHY reset for internal logic */
1256 +       comphy_lane_reg_set(lane, COMPHY_SFT_RESET,
1257 +                           SFT_RST_NO_REG, SFT_RST_NO_REG);
1258 +
1259 +       /* COMPHY register reset (cleared automatically) */
1260 +       comphy_lane_reg_set(lane, COMPHY_SFT_RESET, SFT_RST, SFT_RST);
1261 +
1262 +       /* PIPE soft and register reset */
1263 +       data = PIPE_SOFT_RESET | PIPE_REG_RESET;
1264 +       mask = data;
1265 +       comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask);
1266 +
1267 +       /* Release PIPE register reset */
1268 +       comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL,
1269 +                           0x0, PIPE_REG_RESET);
1270 +
1271 +       /* Reset SB configuration register (only for lanes 0 and 1) */
1272 +       if (lane->id == 0 || lane->id == 1) {
1273 +               u32 mask, data;
1274 +
1275 +               data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT |
1276 +                      PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT;
1277 +               mask = data | PIN_PU_IVREF_BIT | PIN_TX_IDLE_BIT;
1278 +               comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);
1279 +       }
1280 +
1281 +       return 0;
1282 +}
1283 +
1284 +static bool mvebu_a3700_comphy_check_mode(int lane,
1285                                           enum phy_mode mode,
1286                                           int submode)
1287  {
1288 @@ -122,7 +1170,7 @@ static int mvebu_a3700_comphy_get_fw_mod
1289
1290         /* Unused PHY mux value is 0x0 */
1291         if (mode == PHY_MODE_INVALID)
1292 -               return -EINVAL;
1293 +               return false;
1294
1295         for (i = 0; i < n; i++) {
1296                 if (mvebu_a3700_comphy_modes[i].lane == lane &&
1297 @@ -132,27 +1180,30 @@ static int mvebu_a3700_comphy_get_fw_mod
1298         }
1299
1300         if (i == n)
1301 -               return -EINVAL;
1302 +               return false;
1303
1304 -       return mvebu_a3700_comphy_modes[i].fw_mode;
1305 +       return true;
1306  }
1307
1308  static int mvebu_a3700_comphy_set_mode(struct phy *phy, enum phy_mode mode,
1309                                        int submode)
1310  {
1311         struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
1312 -       int fw_mode;
1313 -
1314 -       if (submode == PHY_INTERFACE_MODE_1000BASEX)
1315 -               submode = PHY_INTERFACE_MODE_SGMII;
1316
1317 -       fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, mode,
1318 -                                                submode);
1319 -       if (fw_mode < 0) {
1320 +       if (!mvebu_a3700_comphy_check_mode(lane->id, mode, submode)) {
1321                 dev_err(lane->dev, "invalid COMPHY mode\n");
1322 -               return fw_mode;
1323 +               return -EINVAL;
1324         }
1325
1326 +       /* Mode cannot be changed while the PHY is powered on */
1327 +       if (phy->power_count &&
1328 +           (lane->mode != mode || lane->submode != submode))
1329 +               return -EBUSY;
1330 +
1331 +       /* If changing mode, ensure reset is called */
1332 +       if (lane->mode != PHY_MODE_INVALID && lane->mode != mode)
1333 +               lane->needs_reset = true;
1334 +
1335         /* Just remember the mode, ->power_on() will do the real setup */
1336         lane->mode = mode;
1337         lane->submode = submode;
1338 @@ -163,76 +1214,68 @@ static int mvebu_a3700_comphy_set_mode(s
1339  static int mvebu_a3700_comphy_power_on(struct phy *phy)
1340  {
1341         struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
1342 -       u32 fw_param;
1343 -       int fw_mode;
1344 -       int fw_port;
1345         int ret;
1346
1347 -       fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id,
1348 -                                                lane->mode, lane->submode);
1349 -       if (fw_mode < 0) {
1350 +       if (!mvebu_a3700_comphy_check_mode(lane->id, lane->mode,
1351 +                                          lane->submode)) {
1352                 dev_err(lane->dev, "invalid COMPHY mode\n");
1353 -               return fw_mode;
1354 +               return -EINVAL;
1355 +       }
1356 +
1357 +       if (lane->needs_reset) {
1358 +               ret = mvebu_a3700_comphy_reset(phy);
1359 +               if (ret)
1360 +                       return ret;
1361 +
1362 +               lane->needs_reset = false;
1363         }
1364
1365         switch (lane->mode) {
1366         case PHY_MODE_USB_HOST_SS:
1367                 dev_dbg(lane->dev, "set lane %d to USB3 host mode\n", lane->id);
1368 -               fw_param = COMPHY_FW_MODE(fw_mode);
1369 -               break;
1370 +               return mvebu_a3700_comphy_usb3_power_on(lane);
1371         case PHY_MODE_SATA:
1372                 dev_dbg(lane->dev, "set lane %d to SATA mode\n", lane->id);
1373 -               fw_param = COMPHY_FW_MODE(fw_mode);
1374 -               break;
1375 +               return mvebu_a3700_comphy_sata_power_on(lane);
1376         case PHY_MODE_ETHERNET:
1377 -               fw_port = (lane->id == 0) ? 1 : 0;
1378 -               switch (lane->submode) {
1379 -               case PHY_INTERFACE_MODE_SGMII:
1380 -                       dev_dbg(lane->dev, "set lane %d to SGMII mode\n",
1381 -                               lane->id);
1382 -                       fw_param = COMPHY_FW_NET(fw_mode, fw_port,
1383 -                                                COMPHY_FW_SPEED_1_25G);
1384 -                       break;
1385 -               case PHY_INTERFACE_MODE_2500BASEX:
1386 -                       dev_dbg(lane->dev, "set lane %d to 2500BASEX mode\n",
1387 -                               lane->id);
1388 -                       fw_param = COMPHY_FW_NET(fw_mode, fw_port,
1389 -                                                COMPHY_FW_SPEED_3_125G);
1390 -                       break;
1391 -               default:
1392 -                       dev_err(lane->dev, "unsupported PHY submode (%d)\n",
1393 -                               lane->submode);
1394 -                       return -ENOTSUPP;
1395 -               }
1396 -               break;
1397 +               dev_dbg(lane->dev, "set lane %d to Ethernet mode\n", lane->id);
1398 +               return mvebu_a3700_comphy_ethernet_power_on(lane);
1399         case PHY_MODE_PCIE:
1400                 dev_dbg(lane->dev, "set lane %d to PCIe mode\n", lane->id);
1401 -               fw_param = COMPHY_FW_PCIE(fw_mode, COMPHY_FW_SPEED_5G,
1402 -                                         phy->attrs.bus_width);
1403 -               break;
1404 +               return mvebu_a3700_comphy_pcie_power_on(lane);
1405         default:
1406                 dev_err(lane->dev, "unsupported PHY mode (%d)\n", lane->mode);
1407 -               return -ENOTSUPP;
1408 +               return -EOPNOTSUPP;
1409         }
1410 -
1411 -       ret = mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_ON, lane->id, fw_param);
1412 -       if (ret == -EOPNOTSUPP)
1413 -               dev_err(lane->dev,
1414 -                       "unsupported SMC call, try updating your firmware\n");
1415 -
1416 -       return ret;
1417  }
1418
1419  static int mvebu_a3700_comphy_power_off(struct phy *phy)
1420  {
1421         struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
1422
1423 -       return mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_OFF, lane->id, 0);
1424 +       switch (lane->mode) {
1425 +       case PHY_MODE_USB_HOST_SS:
1426 +               mvebu_a3700_comphy_usb3_power_off(lane);
1427 +               return 0;
1428 +       case PHY_MODE_SATA:
1429 +               mvebu_a3700_comphy_sata_power_off(lane);
1430 +               return 0;
1431 +       case PHY_MODE_ETHERNET:
1432 +               mvebu_a3700_comphy_ethernet_power_off(lane);
1433 +               return 0;
1434 +       case PHY_MODE_PCIE:
1435 +               mvebu_a3700_comphy_pcie_power_off(lane);
1436 +               return 0;
1437 +       default:
1438 +               dev_err(lane->dev, "invalid COMPHY mode\n");
1439 +               return -EINVAL;
1440 +       }
1441  }
1442
1443  static const struct phy_ops mvebu_a3700_comphy_ops = {
1444         .power_on       = mvebu_a3700_comphy_power_on,
1445         .power_off      = mvebu_a3700_comphy_power_off,
1446 +       .reset          = mvebu_a3700_comphy_reset,
1447         .set_mode       = mvebu_a3700_comphy_set_mode,
1448         .owner          = THIS_MODULE,
1449  };
1450 @@ -256,13 +1299,75 @@ static struct phy *mvebu_a3700_comphy_xl
1451                 return ERR_PTR(-EINVAL);
1452         }
1453
1454 +       lane->invert_tx = args->args[1] & BIT(0);
1455 +       lane->invert_rx = args->args[1] & BIT(1);
1456 +
1457         return phy;
1458  }
1459
1460  static int mvebu_a3700_comphy_probe(struct platform_device *pdev)
1461  {
1462 +       struct mvebu_a3700_comphy_priv *priv;
1463         struct phy_provider *provider;
1464         struct device_node *child;
1465 +       struct resource *res;
1466 +       struct clk *clk;
1467 +       int ret;
1468 +
1469 +       priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1470 +       if (!priv)
1471 +               return -ENOMEM;
1472 +
1473 +       spin_lock_init(&priv->lock);
1474 +
1475 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "comphy");
1476 +       priv->comphy_regs = devm_ioremap_resource(&pdev->dev, res);
1477 +       if (IS_ERR(priv->comphy_regs))
1478 +               return PTR_ERR(priv->comphy_regs);
1479 +
1480 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1481 +                                          "lane1_pcie_gbe");
1482 +       priv->lane1_phy_regs = devm_ioremap_resource(&pdev->dev, res);
1483 +       if (IS_ERR(priv->lane1_phy_regs))
1484 +               return PTR_ERR(priv->lane1_phy_regs);
1485 +
1486 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1487 +                                          "lane0_usb3_gbe");
1488 +       priv->lane0_phy_regs = devm_ioremap_resource(&pdev->dev, res);
1489 +       if (IS_ERR(priv->lane0_phy_regs))
1490 +               return PTR_ERR(priv->lane0_phy_regs);
1491 +
1492 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1493 +                                          "lane2_sata_usb3");
1494 +       priv->lane2_phy_indirect = devm_ioremap_resource(&pdev->dev, res);
1495 +       if (IS_ERR(priv->lane2_phy_indirect))
1496 +               return PTR_ERR(priv->lane2_phy_indirect);
1497 +
1498 +       /*
1499 +        * Driver needs to know if reference xtal clock is 40MHz or 25MHz.
1500 +        * Old DT bindings do not have xtal clk present. So do not fail here
1501 +        * and expects that default 25MHz reference clock is used.
1502 +        */
1503 +       clk = clk_get(&pdev->dev, "xtal");
1504 +       if (IS_ERR(clk)) {
1505 +               if (PTR_ERR(clk) == -EPROBE_DEFER)
1506 +                       return -EPROBE_DEFER;
1507 +               dev_warn(&pdev->dev, "missing 'xtal' clk (%ld)\n",
1508 +                        PTR_ERR(clk));
1509 +       } else {
1510 +               ret = clk_prepare_enable(clk);
1511 +               if (ret) {
1512 +                       dev_warn(&pdev->dev, "enabling xtal clk failed (%d)\n",
1513 +                                ret);
1514 +               } else {
1515 +                       if (clk_get_rate(clk) == 40000000)
1516 +                               priv->xtal_is_40m = true;
1517 +                       clk_disable_unprepare(clk);
1518 +               }
1519 +               clk_put(clk);
1520 +       }
1521 +
1522 +       dev_set_drvdata(&pdev->dev, priv);
1523
1524         for_each_available_child_of_node(pdev->dev.of_node, child) {
1525                 struct mvebu_a3700_comphy_lane *lane;
1526 @@ -277,7 +1382,7 @@ static int mvebu_a3700_comphy_probe(stru
1527                         continue;
1528                 }
1529
1530 -               if (lane_id >= MVEBU_A3700_COMPHY_LANES) {
1531 +               if (lane_id >= 3) {
1532                         dev_err(&pdev->dev, "invalid 'reg' property\n");
1533                         continue;
1534                 }
1535 @@ -295,11 +1400,21 @@ static int mvebu_a3700_comphy_probe(stru
1536                         return PTR_ERR(phy);
1537                 }
1538
1539 +               lane->priv = priv;
1540                 lane->dev = &pdev->dev;
1541                 lane->mode = PHY_MODE_INVALID;
1542                 lane->submode = PHY_INTERFACE_MODE_NA;
1543                 lane->id = lane_id;
1544 +               lane->invert_tx = false;
1545 +               lane->invert_rx = false;
1546                 phy_set_drvdata(phy, lane);
1547 +
1548 +               /*
1549 +                * To avoid relying on the bootloader/firmware configuration,
1550 +                * power off all comphys.
1551 +                */
1552 +               mvebu_a3700_comphy_reset(phy);
1553 +               lane->needs_reset = false;
1554         }
1555
1556         provider = devm_of_phy_provider_register(&pdev->dev,
1557 @@ -323,5 +1438,7 @@ static struct platform_driver mvebu_a370
1558  module_platform_driver(mvebu_a3700_comphy_driver);
1559
1560  MODULE_AUTHOR("Miquèl Raynal <miquel.raynal@bootlin.com>");
1561 +MODULE_AUTHOR("Pali Rohár <pali@kernel.org>");
1562 +MODULE_AUTHOR("Marek Behún <kabel@kernel.org>");
1563  MODULE_DESCRIPTION("Common PHY driver for A3700");
1564  MODULE_LICENSE("GPL v2");