target/linux/ipq40xx/patches-4.14/072-qcom-ipq4019-add-cpu-operating-points-for-cpufreq-su.patch

   1 From 544af73985cd14b450bb8e8a6c22b89a555ac729 Mon Sep 17 00:00:00 2001
   2 From: Matthew McClintock <mmcclint@codeaurora.org>
   3 Date: Mon, 23 Jul 2018 09:10:35 +0200
   4 Subject: [PATCH 6/8] qcom: ipq4019: add cpu operating points for cpufreq
   5  support
   6
   7 This adds some operating points for cpu frequeny scaling
   8
   9 Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
  10 Signed-off-by: John Crispin <john@phrozen.org>
  11 ---
  12  arch/arm/boot/dts/qcom-ipq4019.dtsi | 34 ++++++++++++++++++++++++++--------
  13  1 file changed, 30 insertions(+), 8 deletions(-)
  14
  15 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
  16 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
  17 @@ -41,14 +41,7 @@
  18                         reg = <0x0>;
  19                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  20                         clock-frequency = <0>;
  21 -                       operating-points = <
  22 -                               /* kHz  uV (fixed) */
  23 -                               48000   1100000
  24 -                               200000  1100000
  25 -                               500000  1100000
  26 -                               666000  1100000
  27 -                       >;
  28 -                       clock-latency = <256000>;
  29 +                       operating-points-v2 = <&cpu0_opp_table>;
  30                 };
  31
  32                 cpu@1 {
  33 @@ -61,6 +54,7 @@
  34                         reg = <0x1>;
  35                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  36                         clock-frequency = <0>;
  37 +                       operating-points-v2 = <&cpu0_opp_table>;
  38                 };
  39
  40                 cpu@2 {
  41 @@ -73,6 +67,7 @@
  42                         reg = <0x2>;
  43                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  44                         clock-frequency = <0>;
  45 +                       operating-points-v2 = <&cpu0_opp_table>;
  46                 };
  47
  48                 cpu@3 {
  49 @@ -85,6 +80,7 @@
  50                         reg = <0x3>;
  51                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  52                         clock-frequency = <0>;
  53 +                       operating-points-v2 = <&cpu0_opp_table>;
  54                 };
  55
  56                 L2: l2-cache {
  57 @@ -94,6 +90,32 @@
  58                 };
  59         };
  60
  61 +       cpu0_opp_table: opp_table0 {
  62 +               compatible = "operating-points-v2";
  63 +               opp-shared;
  64 +
  65 +               opp-48000000 {
  66 +                       opp-hz = /bits/ 64 <48000000>;
  67 +                       clock-latency-ns = <256000>;
  68 +                       opp-microvolt = <1100000>;
  69 +               };
  70 +               opp-200000000 {
  71 +                       opp-hz = /bits/ 64 <200000000>;
  72 +                       clock-latency-ns = <256000>;
  73 +                       opp-microvolt = <1100000>;
  74 +               };
  75 +               opp-500000000 {
  76 +                       opp-hz = /bits/ 64 <500000000>;
  77 +                       clock-latency-ns = <256000>;
  78 +                       opp-microvolt = <1100000>;
  79 +               };
  80 +               opp-716000000 {
  81 +                       opp-hz = /bits/ 64 <716000000>;
  82 +                       clock-latency-ns = <256000>;
  83 +                       opp-microvolt = <1100000>;
  84 +               };
  85 +       };
  86 +
  87         pmu {
  88                 compatible = "arm,cortex-a7-pmu";
  89                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |