ipq806x: 5:15: refresh config
[openwrt/staging/mkresin.git] / target / linux / ipq806x / patches-5.15 / 104-7-drivers-thermal-tsens-Drop-unused-define-for-msm8960.patch
1 From 5716a61239c6ac9ceb137e825e93c3aea06c4634 Mon Sep 17 00:00:00 2001
2 From: Ansuel Smith <ansuelsmth@gmail.com>
3 Date: Fri, 19 Mar 2021 00:48:23 +0100
4 Subject: [PATCH 07/10] drivers: thermal: tsens: Drop unused define for msm8960
5
6 Drop unused define for msm8960 replaced by generic api and reg_field.
7
8 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
9 Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org>
10 ---
11 drivers/thermal/qcom/tsens-8960.c | 24 +-----------------------
12 1 file changed, 1 insertion(+), 23 deletions(-)
13
14 --- a/drivers/thermal/qcom/tsens-8960.c
15 +++ b/drivers/thermal/qcom/tsens-8960.c
16 @@ -10,8 +10,6 @@
17 #include <linux/thermal.h>
18 #include "tsens.h"
19
20 -#define CAL_MDEGC 30000
21 -
22 #define CONFIG_ADDR 0x3640
23 #define CONFIG_ADDR_8660 0x3620
24 /* CONFIG_ADDR bitmasks */
25 @@ -21,39 +19,19 @@
26 #define CONFIG_SHIFT_8660 28
27 #define CONFIG_MASK_8660 (3 << CONFIG_SHIFT_8660)
28
29 -#define STATUS_CNTL_ADDR_8064 0x3660
30 #define CNTL_ADDR 0x3620
31 /* CNTL_ADDR bitmasks */
32 #define EN BIT(0)
33 #define SW_RST BIT(1)
34 -#define SENSOR0_EN BIT(3)
35 +
36 #define MEASURE_PERIOD BIT(18)
37 #define SLP_CLK_ENA BIT(26)
38 #define SLP_CLK_ENA_8660 BIT(24)
39 #define SENSOR0_SHIFT 3
40
41 -/* INT_STATUS_ADDR bitmasks */
42 -#define MIN_STATUS_MASK BIT(0)
43 -#define LOWER_STATUS_CLR BIT(1)
44 -#define UPPER_STATUS_CLR BIT(2)
45 -#define MAX_STATUS_MASK BIT(3)
46 -
47 #define THRESHOLD_ADDR 0x3624
48 -/* THRESHOLD_ADDR bitmasks */
49 -#define THRESHOLD_MAX_LIMIT_SHIFT 24
50 -#define THRESHOLD_MIN_LIMIT_SHIFT 16
51 -#define THRESHOLD_UPPER_LIMIT_SHIFT 8
52 -#define THRESHOLD_LOWER_LIMIT_SHIFT 0
53 -
54 -/* Initial temperature threshold values */
55 -#define LOWER_LIMIT_TH 0x50
56 -#define UPPER_LIMIT_TH 0xdf
57 -#define MIN_LIMIT_TH 0x0
58 -#define MAX_LIMIT_TH 0xff
59
60 #define INT_STATUS_ADDR 0x363c
61 -#define TRDY_MASK BIT(7)
62 -#define TIMEOUT_US 100
63
64 #define S0_STATUS_OFF 0x3628
65 #define S1_STATUS_OFF 0x362c