target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9.dtsi

   1 #include <dt-bindings/gpio/gpio.h>
   2 #include <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
   3
   4 / {
   5         #address-cells = <1>;
   6         #size-cells = <1>;
   7         compatible = "lantiq,xway", "lantiq,vr9";
   8
   9         aliases {
  10                 serial0 = &asc1;
  11         };
  12
  13         chosen {
  14                 stdout-path = "serial0:115200n8";
  15         };
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 cpu@0 {
  22                         compatible = "mips,mips34Kc";
  23                         reg = <0>;
  24                 };
  25         };
  26
  27         cputemp {
  28                 compatible = "lantiq,cputemp";
  29         };
  30
  31         reboot {
  32                 compatible = "syscon-reboot";
  33
  34                 regmap = <&rcu0>;
  35                 offset = <0x10>;
  36                 mask = <0xe0000000>;
  37         };
  38
  39         biu@1f800000 {
  40                 #address-cells = <1>;
  41                 #size-cells = <1>;
  42                 compatible = "lantiq,biu", "simple-bus";
  43                 reg = <0x1f800000 0x800000>;
  44                 ranges = <0x0 0x1f800000 0x7fffff>;
  45
  46                 icu0: icu@80200 {
  47                         #interrupt-cells = <1>;
  48                         interrupt-controller;
  49                         compatible = "lantiq,icu";
  50                         reg = <0x80200 0xc8     /* icu0 */
  51                                0x80300 0xc8>;   /* icu1 */
  52                 };
  53
  54                 watchdog@803f0 {
  55                         compatible = "lantiq,xrx100-wdt", "lantiq,xrx100-wdt";
  56                         reg = <0x803f0 0x10>;
  57
  58                         regmap = <&rcu0>;
  59                 };
  60         };
  61
  62         sram@1f000000 {
  63                 #address-cells = <1>;
  64                 #size-cells = <1>;
  65                 compatible = "lantiq,sram", "simple-bus";
  66                 reg = <0x1f000000 0x800000>;
  67                 ranges = <0x0 0x1f000000 0x7fffff>;
  68
  69                 eiu0: eiu@101000 {
  70                         #interrupt-cells = <1>;
  71                         interrupt-controller;
  72                         compatible = "lantiq,eiu-xway";
  73                         reg = <0x101000 0x1000>;
  74                         interrupt-parent = <&icu0>;
  75                         lantiq,eiu-irqs = <166 135 66 40 41 42>;
  76                 };
  77
  78                 pmu0: pmu@102000 {
  79                         compatible = "lantiq,pmu-xway";
  80                         reg = <0x102000 0x1000>;
  81                 };
  82
  83                 cgu0: cgu@103000 {
  84                         compatible = "lantiq,cgu-xway";
  85                         reg = <0x103000 0x1000>;
  86                 };
  87
  88                 dcdc@106a00 {
  89                         compatible = "lantiq,dcdc-xrx200";
  90                         reg = <0x106a00 0x200>;
  91                 };
  92
  93                 vmmc: vmmc@107000 {
  94                         status = "disabled";
  95                         compatible = "lantiq,vmmc-xway";
  96                         reg = <0x107000 0x300>;
  97                         interrupt-parent = <&icu0>;
  98                         interrupts = <150 151 152 153 154 155>;
  99                 };
 100
 101                 pcie0_phy: phy@106800 {
 102                         compatible = "lantiq,vrx200-pcie-phy";
 103                         reg = <0x106800 0x100>;
 104                         lantiq,rcu = <&rcu0>;
 105                         lantiq,rcu-endian-offset = <0x4c>;
 106                         lantiq,rcu-big-endian-mask = <0x80>; /* bit 7 */
 107                         big-endian;
 108                         resets = <&reset0 12 24>, <&reset0 22 22>;
 109                         reset-names = "phy", "pcie";
 110                         #phy-cells = <1>;
 111                 };
 112
 113                 rcu0: rcu@203000 {
 114                         #address-cells = <1>;
 115                         #size-cells = <1>;
 116                         compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon";
 117                         reg = <0x203000 0x100>;
 118                         ranges = <0x0 0x203000 0x100>;
 119                         big-endian;
 120
 121                         gphy0: gphy@20 {
 122                                 compatible = "lantiq,xrx200-gphy";
 123                                 reg = <0x20 0x4>;
 124
 125                                 resets = <&reset0 31 30>, <&reset1 7 7>;
 126                                 reset-names = "gphy", "gphy2";
 127                         };
 128
 129                         gphy1: gphy@68 {
 130                                 compatible = "lantiq,xrx200-gphy";
 131                                 reg = <0x68 0x4>;
 132
 133                                 resets = <&reset0 29 28>, <&reset1 6 6>;
 134                                 reset-names = "gphy", "gphy2";
 135                         };
 136
 137                         reset0: reset-controller@10 {
 138                                 compatible = "lantiq,xrx200-reset";
 139                                 reg = <0x10 4>, <0x14 4>;
 140
 141                                 #reset-cells = <2>;
 142                         };
 143
 144                         reset1: reset-controller@48 {
 145                                 compatible = "lantiq,xrx200-reset";
 146                                 reg = <0x48 4>, <0x24 4>;
 147
 148                                 #reset-cells = <2>;
 149                         };
 150
 151                         usb_phy0: usb2-phy@18 {
 152                                 compatible = "lantiq,xrx200-usb2-phy";
 153                                 reg = <0x18 4>, <0x38 4>;
 154                                 status = "disabled";
 155
 156                                 resets = <&reset1 4 4>, <&reset0 4 4>;
 157                                 reset-names = "phy", "ctrl";
 158                                 #phy-cells = <0>;
 159                         };
 160
 161                         usb_phy1: usb2-phy@34 {
 162                                 compatible = "lantiq,xrx200-usb2-phy";
 163                                 reg = <0x34 4>, <0x3c 4>;
 164                                 status = "disabled";
 165
 166                                 resets = <&reset1 5 5>, <&reset0 4 4>;
 167                                 reset-names = "phy", "ctrl";
 168                                 #phy-cells = <0>;
 169                         };
 170                 };
 171         };
 172
 173         fpi@10000000 {
 174                 compatible = "lantiq,xrx200-fpi", "simple-bus";
 175                 ranges = <0x0 0x10000000 0xf000000>;
 176                 reg =   <0x1f400000 0x1000>,
 177                         <0x10000000 0xf000000>;
 178                 regmap = <&rcu0>;
 179                 offset-endianness = <0x4c>;
 180                 #address-cells = <1>;
 181                 #size-cells = <1>;
 182
 183                 localbus: localbus@0 {
 184                         #address-cells = <2>;
 185                         #size-cells = <1>;
 186                         ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
 187                                 1 0 0x4000000 0x4000010>; /* addsel1 */
 188                         compatible = "lantiq,localbus", "simple-bus";
 189                 };
 190
 191                 gptu@e100a00 {
 192                         compatible = "lantiq,gptu-xway";
 193                         reg = <0xe100a00 0x100>;
 194                         interrupt-parent = <&icu0>;
 195                         interrupts = <126 127 128 129 130 131>;
 196                 };
 197
 198                 usif: usif@da00000 {
 199                         compatible = "lantiq,usif";
 200                         reg = <0xda00000 0x1000000>;
 201                         interrupt-parent = <&icu0>;
 202                         interrupts = <29 125 107 108 109 110>;
 203                         status = "disabled";
 204                 };
 205
 206                 spi: spi@e100800 {
 207                         compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi";
 208                         reg = <0xe100800 0x100>;
 209                         interrupt-parent = <&icu0>;
 210                         interrupts = <22 23 24>;
 211                         interrupt-names = "spi_rx", "spi_tx", "spi_err",
 212                                         "spi_frm";
 213                         #address-cells = <1>;
 214                         #size-cells = <0>;
 215                         pinctrl-names = "default";
 216                         pinctrl-0 = <&spi_pins>, <&spi_cs4_pins>;
 217                         status = "disabled";
 218                 };
 219
 220                 gpio: pinmux@e100b10 {
 221                         compatible = "lantiq,xrx200-pinctrl";
 222                         #gpio-cells = <2>;
 223                         gpio-controller;
 224                         reg = <0xe100b10 0xa0>;
 225
 226                         gphy0_led0_pins: gphy0-led0 {
 227                                 lantiq,groups = "gphy0 led0";
 228                                 lantiq,function = "gphy";
 229                                 lantiq,open-drain = <0>;
 230                                 lantiq,pull = <2>;
 231                                 lantiq,output = <1>;
 232                         };
 233
 234                         gphy0_led1_pins: gphy0-led1 {
 235                                 lantiq,groups = "gphy0 led1";
 236                                 lantiq,function = "gphy";
 237                                 lantiq,open-drain = <0>;
 238                                 lantiq,pull = <2>;
 239                                 lantiq,output = <1>;
 240                         };
 241
 242                         gphy0_led2_pins: gphy0-led2 {
 243                                 lantiq,groups = "gphy0 led2";
 244                                 lantiq,function = "gphy";
 245                                 lantiq,open-drain = <0>;
 246                                 lantiq,pull = <2>;
 247                                 lantiq,output = <1>;
 248                         };
 249
 250                         gphy1_led0_pins: gphy1-led0 {
 251                                 lantiq,groups = "gphy1 led0";
 252                                 lantiq,function = "gphy";
 253                                 lantiq,open-drain = <0>;
 254                                 lantiq,pull = <2>;
 255                                 lantiq,output = <1>;
 256                         };
 257
 258                         gphy1_led1_pins: gphy1-led1 {
 259                                 lantiq,groups = "gphy1 led1";
 260                                 lantiq,function = "gphy";
 261                                 lantiq,open-drain = <0>;
 262                                 lantiq,pull = <2>;
 263                                 lantiq,output = <1>;
 264                         };
 265
 266                         gphy1_led2_pins: gphy1-led2 {
 267                                 lantiq,groups = "gphy1 led2";
 268                                 lantiq,function = "gphy";
 269                                 lantiq,open-drain = <0>;
 270                                 lantiq,pull = <2>;
 271                                 lantiq,output = <1>;
 272                         };
 273
 274                         mdio_pins: mdio {
 275                                 mux {
 276                                         lantiq,groups = "mdio";
 277                                         lantiq,function = "mdio";
 278                                 };
 279                         };
 280
 281                         nand_pins: nand {
 282                                 mux-0 {
 283                                         lantiq,groups = "nand cle", "nand ale",
 284                                                         "nand rd";
 285                                         lantiq,function = "ebu";
 286                                         lantiq,output = <1>;
 287                                         lantiq,open-drain = <0>;
 288                                         lantiq,pull = <0>;
 289                                 };
 290                                 mux-1 {
 291                                         lantiq,groups = "nand rdy";
 292                                         lantiq,function = "ebu";
 293                                         lantiq,output = <0>;
 294                                         lantiq,pull = <2>;
 295                                 };
 296                         };
 297
 298                         nand_cs1_pins: nand-cs1 {
 299                                 mux {
 300                                         lantiq,groups = "nand cs1";
 301                                         lantiq,function = "ebu";
 302                                         lantiq,open-drain = <0>;
 303                                         lantiq,pull = <0>;
 304                                 };
 305                         };
 306
 307                         pci_gnt1_pins: pci-gnt1 {
 308                                 lantiq,groups = "gnt1";
 309                                 lantiq,function = "pci";
 310                                 lantiq,output = <1>;
 311                                 lantiq,open-drain = <0>;
 312                                 lantiq,pull = <0>;
 313                         };
 314
 315                         pci_req1_pins: pci-req1 {
 316                                 lantiq,groups = "req1";
 317                                 lantiq,function = "pci";
 318                                 lantiq,output = <0>;
 319                                 lantiq,open-drain = <1>;
 320                                 lantiq,pull = <2>;
 321                         };
 322
 323                         spi_pins: spi {
 324                                 mux-0 {
 325                                         lantiq,groups = "spi_di";
 326                                         lantiq,function = "spi";
 327                                 };
 328                                 mux-1 {
 329                                         lantiq,groups = "spi_do", "spi_clk";
 330                                         lantiq,function = "spi";
 331                                         lantiq,output = <1>;
 332                                 };
 333                         };
 334
 335                         spi_cs4_pins: spi-cs4 {
 336                                 mux {
 337                                         lantiq,groups = "spi_cs4";
 338                                         lantiq,function = "spi";
 339                                         lantiq,output = <1>;
 340                                 };
 341                         };
 342
 343                         stp_pins: stp {
 344                                 lantiq,groups = "stp";
 345                                 lantiq,function = "stp";
 346                                 lantiq,pull = <0>;
 347                                 lantiq,open-drain = <0>;
 348                                 lantiq,output = <1>;
 349                         };
 350                 };
 351
 352                 stp: stp@e100bb0 {
 353                         status = "disabled";
 354                         compatible = "lantiq,gpio-stp-xway";
 355                         reg = <0xe100bb0 0x40>;
 356                         #gpio-cells = <2>;
 357                         gpio-controller;
 358
 359                         pinctrl-0 = <&stp_pins>;
 360                         pinctrl-names = "default";
 361
 362                         lantiq,shadow = <0xffffff>;
 363                         lantiq,groups = <0x7>;
 364                         lantiq,dsl = <0x0>;
 365                         lantiq,phy1 = <0x0>;
 366                         lantiq,phy2 = <0x0>;
 367                 };
 368
 369                 asc1: serial@e100c00 {
 370                         compatible = "lantiq,asc";
 371                         reg = <0xe100c00 0x400>;
 372                         interrupt-parent = <&icu0>;
 373                         interrupts = <112 113 114>;
 374                 };
 375
 376                 deu@e103100 {
 377                         compatible = "lantiq,deu-xrx200";
 378                         reg = <0xe103100 0xf00>;
 379                 };
 380
 381                 dma0: dma@e104100 {
 382                         compatible = "lantiq,dma-xway";
 383                         reg = <0xe104100 0x800>;
 384                 };
 385
 386                 ebu0: ebu@e105300 {
 387                         compatible = "lantiq,ebu-xway";
 388                         reg = <0xe105300 0x100>;
 389                 };
 390
 391                 usb0: usb@e101000 {
 392                         status = "disabled";
 393                         compatible = "lantiq,xrx200-usb";
 394                         reg = <0xe101000 0x1000
 395                                 0xe120000 0x3f000>;
 396                         interrupt-parent = <&icu0>;
 397                         interrupts = <62 91>;
 398                         dr_mode = "host";
 399                         phys = <&usb_phy0>;
 400                         phy-names = "usb2-phy";
 401                 };
 402
 403                 usb1: usb@e106000 {
 404                         status = "disabled";
 405                         compatible = "lantiq,xrx200-usb";
 406                         reg = <0xe106000 0x1000>;
 407                         interrupt-parent = <&icu0>;
 408                         interrupts = <91>;
 409                         dr_mode = "host";
 410                         phys = <&usb_phy1>;
 411                         phy-names = "usb2-phy";
 412                 };
 413
 414                 eth0: eth@e108000 {
 415                         #address-cells = <1>;
 416                         #size-cells = <0>;
 417                         compatible = "lantiq,xrx200-net";
 418                         reg = < 0xe108000 0x3000 /* switch */
 419                                 0xe10b100 0x70 /* mdio */
 420                                 0xe10b1d8 0x30 /* mii */
 421                                 0xe10b308 0x30 /* pmac */
 422                         >;
 423                         interrupt-parent = <&icu0>;
 424                         interrupts = <75 73 72>;
 425                         resets = <&reset0 21 16>, <&reset0 8 8>;
 426                         reset-names = "switch", "ppe";
 427                         lantiq,phys = <&gphy0>, <&gphy1>;
 428                         pinctrl-0 = <&mdio_pins>;
 429                         pinctrl-names = "default";
 430                 };
 431
 432                 mei@e116000 {
 433                         compatible = "lantiq,mei-xrx200";
 434                         reg = <0xe116000 0x9c>;
 435                         interrupt-parent = <&icu0>;
 436                         interrupts = <63>;
 437                 };
 438
 439                 ppe@e234000 {
 440                         compatible = "lantiq,ppe-xrx200";
 441                         reg = <0xe234000 0x3ffd>;
 442                         interrupt-parent = <&icu0>;
 443                         interrupts = <96>;
 444                         resets = <&reset0 3 3>, <&reset0 11 11>, <&reset0 23 23>;
 445                         reset-names = "dsp", "dfe", "tc";
 446                 };
 447
 448                 pcie0: pcie@d900000 {
 449                         compatible = "lantiq,pcie-xrx200";
 450
 451                         #interrupt-cells = <1>;
 452                         #size-cells = <2>;
 453                         #address-cells = <3>;
 454
 455                         reg = <0xd900000 0x1000>;
 456
 457                         interrupt-parent = <&icu0>;
 458                         interrupts = <161 144>;
 459
 460                         phys = <&pcie0_phy LANTIQ_PCIE_PHY_MODE_36MHZ>;
 461                         phy-names = "pcie";
 462
 463                         resets = <&reset0 22 22>;
 464
 465                         lantiq,rcu = <&rcu0>;
 466
 467                         device_type = "pci";
 468
 469                         gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>;
 470                 };
 471
 472                 pci0: pci@e105400 {
 473                         status = "disabled";
 474
 475                         #address-cells = <3>;
 476                         #size-cells = <2>;
 477                         #interrupt-cells = <1>;
 478                         compatible = "lantiq,pci-xway";
 479                         bus-range = <0x0 0x0>;
 480                         ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000   /* pci memory */
 481                                 0x1000000 0 0x00000000 0xae00000 0 0x200000>; /* io space */
 482                         reg = <0x7000000 0x8000         /* config space */
 483                                 0xe105400 0x400>;       /* pci bridge */
 484                         lantiq,bus-clock = <33333333>;
 485                         interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 486                         interrupt-map = <0x7000 0 0 1 &icu0 30 1>; /* slot 14, irq 30 */
 487                         req-mask = <0x1>; /* GNT1 */
 488                 };
 489         };
 490
 491         vdsl {
 492                 compatible = "lantiq,vdsl-vrx200";
 493         };
 494 };