target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9.dtsi

   1 #include <dt-bindings/gpio/gpio.h>
   2
   3 / {
   4         #address-cells = <1>;
   5         #size-cells = <1>;
   6         compatible = "lantiq,xway", "lantiq,vr9";
   7
   8         aliases {
   9                 serial0 = &asc1;
  10         };
  11
  12         chosen {
  13                 stdout-path = "serial0:115200n8";
  14         };
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         compatible = "mips,mips34Kc";
  22                         reg = <0>;
  23                 };
  24         };
  25
  26         cputemp {
  27                 compatible = "lantiq,cputemp";
  28         };
  29
  30         reboot {
  31                 compatible = "syscon-reboot";
  32
  33                 regmap = <&rcu0>;
  34                 offset = <0x10>;
  35                 mask = <0xe0000000>;
  36         };
  37
  38         biu@1f800000 {
  39                 #address-cells = <1>;
  40                 #size-cells = <1>;
  41                 compatible = "lantiq,biu", "simple-bus";
  42                 reg = <0x1f800000 0x800000>;
  43                 ranges = <0x0 0x1f800000 0x7fffff>;
  44
  45                 icu0: icu@80200 {
  46                         #interrupt-cells = <1>;
  47                         interrupt-controller;
  48                         compatible = "lantiq,icu";
  49                         reg = <0x80200 0x28
  50                                 0x80228 0x28
  51                                 0x80250 0x28
  52                                 0x80278 0x28
  53                                 0x802a0 0x28>;
  54                 };
  55
  56                 watchdog@803f0 {
  57                         compatible = "lantiq,xrx100-wdt", "lantiq,xrx100-wdt";
  58                         reg = <0x803f0 0x10>;
  59
  60                         regmap = <&rcu0>;
  61                 };
  62         };
  63
  64         sram@1f000000 {
  65                 #address-cells = <1>;
  66                 #size-cells = <1>;
  67                 compatible = "lantiq,sram", "simple-bus";
  68                 reg = <0x1f000000 0x800000>;
  69                 ranges = <0x0 0x1f000000 0x7fffff>;
  70
  71                 eiu0: eiu@101000 {
  72                         #interrupt-cells = <1>;
  73                         interrupt-controller;
  74                         compatible = "lantiq,eiu-xway";
  75                         reg = <0x101000 0x1000>;
  76                         interrupt-parent = <&icu0>;
  77                         lantiq,eiu-irqs = <166 135 66 40 41 42>;
  78                 };
  79
  80                 pmu0: pmu@102000 {
  81                         compatible = "lantiq,pmu-xway";
  82                         reg = <0x102000 0x1000>;
  83                 };
  84
  85                 cgu0: cgu@103000 {
  86                         compatible = "lantiq,cgu-xway";
  87                         reg = <0x103000 0x1000>;
  88                 };
  89
  90                 dcdc@106a00 {
  91                         compatible = "lantiq,dcdc-xrx200";
  92                         reg = <0x106a00 0x200>;
  93                 };
  94
  95                 vmmc: vmmc@107000 {
  96                         status = "disabled";
  97                         compatible = "lantiq,vmmc-xway";
  98                         reg = <0x107000 0x300>;
  99                         interrupt-parent = <&icu0>;
 100                         interrupts = <150 151 152 153 154 155>;
 101                 };
 102
 103                 rcu0: rcu@203000 {
 104                         #address-cells = <1>;
 105                         #size-cells = <1>;
 106                         compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon";
 107                         reg = <0x203000 0x100>;
 108                         ranges = <0x0 0x203000 0x100>;
 109                         big-endian;
 110
 111                         gphy0: gphy@20 {
 112                                 compatible = "lantiq,xrx200-gphy";
 113                                 reg = <0x20 0x4>;
 114
 115                                 resets = <&reset0 31 30>, <&reset1 7 7>;
 116                                 reset-names = "gphy", "gphy2";
 117                         };
 118
 119                         gphy1: gphy@68 {
 120                                 compatible = "lantiq,xrx200-gphy";
 121                                 reg = <0x68 0x4>;
 122
 123                                 resets = <&reset0 29 28>, <&reset1 6 6>;
 124                                 reset-names = "gphy", "gphy2";
 125                         };
 126
 127                         reset0: reset-controller@10 {
 128                                 compatible = "lantiq,xrx200-reset";
 129                                 reg = <0x10 4>, <0x14 4>;
 130
 131                                 #reset-cells = <2>;
 132                         };
 133
 134                         reset1: reset-controller@48 {
 135                                 compatible = "lantiq,xrx200-reset";
 136                                 reg = <0x48 4>, <0x24 4>;
 137
 138                                 #reset-cells = <2>;
 139                         };
 140
 141                         usb_phy0: usb2-phy@18 {
 142                                 compatible = "lantiq,xrx200-usb2-phy";
 143                                 reg = <0x18 4>, <0x38 4>;
 144                                 status = "disabled";
 145
 146                                 resets = <&reset1 4 4>, <&reset0 4 4>;
 147                                 reset-names = "phy", "ctrl";
 148                                 #phy-cells = <0>;
 149                         };
 150
 151                         usb_phy1: usb2-phy@34 {
 152                                 compatible = "lantiq,xrx200-usb2-phy";
 153                                 reg = <0x34 4>, <0x3c 4>;
 154                                 status = "disabled";
 155
 156                                 resets = <&reset1 5 5>, <&reset0 4 4>;
 157                                 reset-names = "phy", "ctrl";
 158                                 #phy-cells = <0>;
 159                         };
 160                 };
 161         };
 162
 163         fpi@10000000 {
 164                 compatible = "lantiq,xrx200-fpi", "simple-bus";
 165                 ranges = <0x0 0x10000000 0xf000000>;
 166                 reg =   <0x1f400000 0x1000>,
 167                         <0x10000000 0xf000000>;
 168                 regmap = <&rcu0>;
 169                 offset-endianness = <0x4c>;
 170                 #address-cells = <1>;
 171                 #size-cells = <1>;
 172
 173                 localbus: localbus@0 {
 174                         #address-cells = <2>;
 175                         #size-cells = <1>;
 176                         ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
 177                                 1 0 0x4000000 0x4000010>; /* addsel1 */
 178                         compatible = "lantiq,localbus", "simple-bus";
 179                 };
 180
 181                 gptu@e100a00 {
 182                         compatible = "lantiq,gptu-xway";
 183                         reg = <0xe100a00 0x100>;
 184                         interrupt-parent = <&icu0>;
 185                         interrupts = <126 127 128 129 130 131>;
 186                 };
 187
 188                 usif: usif@da00000 {
 189                         compatible = "lantiq,usif";
 190                         reg = <0xda00000 0x1000000>;
 191                         interrupt-parent = <&icu0>;
 192                         interrupts = <29 125 107 108 109 110>;
 193                         status = "disabled";
 194                 };
 195
 196                 spi: spi@e100800 {
 197                         compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi";
 198                         reg = <0xe100800 0x100>;
 199                         interrupt-parent = <&icu0>;
 200                         interrupts = <22 23 24>;
 201                         interrupt-names = "spi_rx", "spi_tx", "spi_err",
 202                                         "spi_frm";
 203                         #address-cells = <1>;
 204                         #size-cells = <0>;
 205                         pinctrl-names = "default";
 206                         pinctrl-0 = <&spi_pins>, <&spi_cs4_pins>;
 207                         status = "disabled";
 208                 };
 209
 210                 gpio: pinmux@e100b10 {
 211                         compatible = "lantiq,xrx200-pinctrl";
 212                         #gpio-cells = <2>;
 213                         gpio-controller;
 214                         reg = <0xe100b10 0xa0>;
 215
 216                         gphy0_led0_pins: gphy0-led0 {
 217                                 lantiq,groups = "gphy0 led0";
 218                                 lantiq,function = "gphy";
 219                                 lantiq,open-drain = <0>;
 220                                 lantiq,pull = <2>;
 221                                 lantiq,output = <1>;
 222                         };
 223
 224                         gphy0_led1_pins: gphy0-led1 {
 225                                 lantiq,groups = "gphy0 led1";
 226                                 lantiq,function = "gphy";
 227                                 lantiq,open-drain = <0>;
 228                                 lantiq,pull = <2>;
 229                                 lantiq,output = <1>;
 230                         };
 231
 232                         gphy0_led2_pins: gphy0-led2 {
 233                                 lantiq,groups = "gphy0 led2";
 234                                 lantiq,function = "gphy";
 235                                 lantiq,open-drain = <0>;
 236                                 lantiq,pull = <2>;
 237                                 lantiq,output = <1>;
 238                         };
 239
 240                         gphy1_led0_pins: gphy1-led0 {
 241                                 lantiq,groups = "gphy1 led0";
 242                                 lantiq,function = "gphy";
 243                                 lantiq,open-drain = <0>;
 244                                 lantiq,pull = <2>;
 245                                 lantiq,output = <1>;
 246                         };
 247
 248                         gphy1_led1_pins: gphy1-led1 {
 249                                 lantiq,groups = "gphy1 led1";
 250                                 lantiq,function = "gphy";
 251                                 lantiq,open-drain = <0>;
 252                                 lantiq,pull = <2>;
 253                                 lantiq,output = <1>;
 254                         };
 255
 256                         gphy1_led2_pins: gphy1-led2 {
 257                                 lantiq,groups = "gphy1 led2";
 258                                 lantiq,function = "gphy";
 259                                 lantiq,open-drain = <0>;
 260                                 lantiq,pull = <2>;
 261                                 lantiq,output = <1>;
 262                         };
 263
 264                         mdio_pins: mdio {
 265                                 mux {
 266                                         lantiq,groups = "mdio";
 267                                         lantiq,function = "mdio";
 268                                 };
 269                         };
 270
 271                         nand_pins: nand {
 272                                 mux-0 {
 273                                         lantiq,groups = "nand cle", "nand ale",
 274                                                         "nand rd";
 275                                         lantiq,function = "ebu";
 276                                         lantiq,output = <1>;
 277                                         lantiq,open-drain = <0>;
 278                                         lantiq,pull = <0>;
 279                                 };
 280                                 mux-1 {
 281                                         lantiq,groups = "nand rdy";
 282                                         lantiq,function = "ebu";
 283                                         lantiq,output = <0>;
 284                                         lantiq,pull = <2>;
 285                                 };
 286                         };
 287
 288                         nand_cs1_pins: nand-cs1 {
 289                                 mux {
 290                                         lantiq,groups = "nand cs1";
 291                                         lantiq,function = "ebu";
 292                                         lantiq,open-drain = <0>;
 293                                         lantiq,pull = <0>;
 294                                 };
 295                         };
 296
 297                         pci_gnt1_pins: pci-gnt1 {
 298                                 lantiq,groups = "gnt1";
 299                                 lantiq,function = "pci";
 300                                 lantiq,output = <1>;
 301                                 lantiq,open-drain = <0>;
 302                                 lantiq,pull = <0>;
 303                         };
 304
 305                         pci_req1_pins: pci-req1 {
 306                                 lantiq,groups = "req1";
 307                                 lantiq,function = "pci";
 308                                 lantiq,output = <0>;
 309                                 lantiq,open-drain = <1>;
 310                                 lantiq,pull = <2>;
 311                         };
 312
 313                         spi_pins: spi {
 314                                 mux-0 {
 315                                         lantiq,groups = "spi_di";
 316                                         lantiq,function = "spi";
 317                                 };
 318                                 mux-1 {
 319                                         lantiq,groups = "spi_do", "spi_clk";
 320                                         lantiq,function = "spi";
 321                                         lantiq,output = <1>;
 322                                 };
 323                         };
 324
 325                         spi_cs4_pins: spi-cs4 {
 326                                 mux {
 327                                         lantiq,groups = "spi_cs4";
 328                                         lantiq,function = "spi";
 329                                         lantiq,output = <1>;
 330                                 };
 331                         };
 332
 333                         stp_pins: stp {
 334                                 lantiq,groups = "stp";
 335                                 lantiq,function = "stp";
 336                                 lantiq,pull = <0>;
 337                                 lantiq,open-drain = <0>;
 338                                 lantiq,output = <1>;
 339                         };
 340                 };
 341
 342                 stp: stp@e100bb0 {
 343                         status = "disabled";
 344                         compatible = "lantiq,gpio-stp-xway";
 345                         reg = <0xe100bb0 0x40>;
 346                         #gpio-cells = <2>;
 347                         gpio-controller;
 348
 349                         pinctrl-0 = <&stp_pins>;
 350                         pinctrl-names = "default";
 351
 352                         lantiq,shadow = <0xffffff>;
 353                         lantiq,groups = <0x7>;
 354                         lantiq,dsl = <0x0>;
 355                         lantiq,phy1 = <0x0>;
 356                         lantiq,phy2 = <0x0>;
 357                 };
 358
 359                 asc1: serial@e100c00 {
 360                         compatible = "lantiq,asc";
 361                         reg = <0xe100c00 0x400>;
 362                         interrupt-parent = <&icu0>;
 363                         interrupts = <112 113 114>;
 364                 };
 365
 366                 deu@e103100 {
 367                         compatible = "lantiq,deu-xrx200";
 368                         reg = <0xe103100 0xf00>;
 369                 };
 370
 371                 dma0: dma@e104100 {
 372                         compatible = "lantiq,dma-xway";
 373                         reg = <0xe104100 0x800>;
 374                 };
 375
 376                 ebu0: ebu@e105300 {
 377                         compatible = "lantiq,ebu-xway";
 378                         reg = <0xe105300 0x100>;
 379                 };
 380
 381                 usb0: usb@e101000 {
 382                         status = "disabled";
 383                         compatible = "lantiq,xrx200-usb";
 384                         reg = <0xe101000 0x1000
 385                                 0xe120000 0x3f000>;
 386                         interrupt-parent = <&icu0>;
 387                         interrupts = <62 91>;
 388                         dr_mode = "host";
 389                         phys = <&usb_phy0>;
 390                         phy-names = "usb2-phy";
 391                 };
 392
 393                 usb1: usb@e106000 {
 394                         status = "disabled";
 395                         compatible = "lantiq,xrx200-usb";
 396                         reg = <0xe106000 0x1000>;
 397                         interrupt-parent = <&icu0>;
 398                         interrupts = <91>;
 399                         dr_mode = "host";
 400                         phys = <&usb_phy1>;
 401                         phy-names = "usb2-phy";
 402                 };
 403
 404                 eth0: eth@e108000 {
 405                         #address-cells = <1>;
 406                         #size-cells = <0>;
 407                         compatible = "lantiq,xrx200-net";
 408                         reg = < 0xe108000 0x3000 /* switch */
 409                                 0xe10b100 0x70 /* mdio */
 410                                 0xe10b1d8 0x30 /* mii */
 411                                 0xe10b308 0x30 /* pmac */
 412                         >;
 413                         interrupt-parent = <&icu0>;
 414                         interrupts = <75 73 72>;
 415                         resets = <&reset0 21 16>, <&reset0 8 8>;
 416                         reset-names = "switch", "ppe";
 417                         lantiq,phys = <&gphy0>, <&gphy1>;
 418                         pinctrl-0 = <&mdio_pins>;
 419                         pinctrl-names = "default";
 420                 };
 421
 422                 mei@e116000 {
 423                         compatible = "lantiq,mei-xrx200";
 424                         reg = <0xe116000 0x9c>;
 425                         interrupt-parent = <&icu0>;
 426                         interrupts = <63>;
 427                 };
 428
 429                 ppe@e234000 {
 430                         compatible = "lantiq,ppe-xrx200";
 431                         reg = <0xe234000 0x3ffd>;
 432                         interrupt-parent = <&icu0>;
 433                         interrupts = <96>;
 434                         resets = <&reset0 3 3>, <&reset0 11 11>, <&reset0 23 23>;
 435                         reset-names = "dsp", "dfe", "tc";
 436                 };
 437
 438                 pcie0: pcie@d900000 {
 439                         compatible = "lantiq,pcie-xrx200";
 440
 441                         #interrupt-cells = <1>;
 442                         #size-cells = <2>;
 443                         #address-cells = <3>;
 444
 445                         reg = <0xd900000 0x1000>;
 446
 447                         interrupt-parent = <&icu0>;
 448                         interrupts = <161 144>;
 449
 450                         device_type = "pci";
 451
 452                         gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>;
 453                 };
 454
 455                 pci0: pci@e105400 {
 456                         status = "disabled";
 457
 458                         #address-cells = <3>;
 459                         #size-cells = <2>;
 460                         #interrupt-cells = <1>;
 461                         compatible = "lantiq,pci-xway";
 462                         bus-range = <0x0 0x0>;
 463                         ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000   /* pci memory */
 464                                 0x1000000 0 0x00000000 0xae00000 0 0x200000>; /* io space */
 465                         reg = <0x7000000 0x8000         /* config space */
 466                                 0xe105400 0x400>;       /* pci bridge */
 467                         lantiq,bus-clock = <33333333>;
 468                         interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 469                         interrupt-map = <0x7000 0 0 1 &icu0 30 1>; /* slot 14, irq 30 */
 470                         req-mask = <0x1>; /* GNT1 */
 471                 };
 472         };
 473
 474         vdsl {
 475                 compatible = "lantiq,vdsl-vrx200";
 476         };
 477 };