target/linux/lantiq/patches-5.4/0028-NET-lantiq-various-etop-fixes.patch

   1 From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Tue, 9 Sep 2014 22:45:34 +0200
   4 Subject: [PATCH 28/36] NET: lantiq: various etop fixes
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  drivers/net/ethernet/lantiq_etop.c |  555 +++++++++++++++++++++++++-----------
   9  1 file changed, 389 insertions(+), 166 deletions(-)
  10
  11 --- a/drivers/net/ethernet/lantiq_etop.c
  12 +++ b/drivers/net/ethernet/lantiq_etop.c
  13 @@ -1,7 +1,7 @@
  14  // SPDX-License-Identifier: GPL-2.0-only
  15  /*
  16   *
  17 - *   Copyright (C) 2011 John Crispin <blogic@openwrt.org>
  18 + *   Copyright (C) 2011-12 John Crispin <blogic@openwrt.org>
  19   */
  20
  21  #include <linux/kernel.h>
  22 @@ -20,11 +20,16 @@
  23  #include <linux/mm.h>
  24  #include <linux/platform_device.h>
  25  #include <linux/ethtool.h>
  26 +#include <linux/if_vlan.h>
  27  #include <linux/init.h>
  28  #include <linux/delay.h>
  29  #include <linux/io.h>
  30  #include <linux/dma-mapping.h>
  31  #include <linux/module.h>
  32 +#include <linux/clk.h>
  33 +#include <linux/of_net.h>
  34 +#include <linux/of_irq.h>
  35 +#include <linux/of_platform.h>
  36
  37  #include <asm/checksum.h>
  38
  39 @@ -32,7 +37,7 @@
  40  #include <xway_dma.h>
  41  #include <lantiq_platform.h>
  42
  43 -#define LTQ_ETOP_MDIO          0x11804
  44 +#define LTQ_ETOP_MDIO_ACC      0x11804
  45  #define MDIO_REQUEST           0x80000000
  46  #define MDIO_READ              0x40000000
  47  #define MDIO_ADDR_MASK         0x1f
  48 @@ -41,44 +46,91 @@
  49  #define MDIO_REG_OFFSET                0x10
  50  #define MDIO_VAL_MASK          0xffff
  51
  52 -#define PPE32_CGEN             0x800
  53 -#define LQ_PPE32_ENET_MAC_CFG  0x1840
  54 +#define LTQ_ETOP_MDIO_CFG       0x11800
  55 +#define MDIO_CFG_MASK           0x6
  56 +
  57 +#define LTQ_ETOP_CFG            0x11808
  58 +#define LTQ_ETOP_IGPLEN         0x11820
  59 +#define LTQ_ETOP_MAC_CFG       0x11840
  60
  61  #define LTQ_ETOP_ENETS0                0x11850
  62  #define LTQ_ETOP_MAC_DA0       0x1186C
  63  #define LTQ_ETOP_MAC_DA1       0x11870
  64 -#define LTQ_ETOP_CFG           0x16020
  65 -#define LTQ_ETOP_IGPLEN                0x16080
  66 +
  67 +#define MAC_CFG_MASK           0xfff
  68 +#define MAC_CFG_CGEN           (1 << 11)
  69 +#define MAC_CFG_DUPLEX         (1 << 2)
  70 +#define MAC_CFG_SPEED          (1 << 1)
  71 +#define MAC_CFG_LINK           (1 << 0)
  72
  73  #define MAX_DMA_CHAN           0x8
  74  #define MAX_DMA_CRC_LEN                0x4
  75  #define MAX_DMA_DATA_LEN       0x600
  76
  77  #define ETOP_FTCU              BIT(28)
  78 -#define ETOP_MII_MASK          0xf
  79 -#define ETOP_MII_NORMAL                0xd
  80 -#define ETOP_MII_REVERSE       0xe
  81  #define ETOP_PLEN_UNDER                0x40
  82 -#define ETOP_CGEN              0x800
  83 +#define ETOP_CFG_MII0          0x01
  84
  85 -/* use 2 static channels for TX/RX */
  86 -#define LTQ_ETOP_TX_CHANNEL    1
  87 -#define LTQ_ETOP_RX_CHANNEL    6
  88 -#define IS_TX(x)               (x == LTQ_ETOP_TX_CHANNEL)
  89 -#define IS_RX(x)               (x == LTQ_ETOP_RX_CHANNEL)
  90 +#define ETOP_CFG_MASK           0xfff
  91 +#define ETOP_CFG_FEN0          (1 << 8)
  92 +#define ETOP_CFG_SEN0          (1 << 6)
  93 +#define ETOP_CFG_OFF1          (1 << 3)
  94 +#define ETOP_CFG_REMII0                (1 << 1)
  95 +#define ETOP_CFG_OFF0          (1 << 0)
  96 +
  97 +#define LTQ_GBIT_MDIO_CTL      0xCC
  98 +#define LTQ_GBIT_MDIO_DATA     0xd0
  99 +#define LTQ_GBIT_GCTL0         0x68
 100 +#define LTQ_GBIT_PMAC_HD_CTL   0x8c
 101 +#define LTQ_GBIT_P0_CTL                0x4
 102 +#define LTQ_GBIT_PMAC_RX_IPG   0xa8
 103 +#define LTQ_GBIT_RGMII_CTL     0x78
 104 +
 105 +#define PMAC_HD_CTL_AS         (1 << 19)
 106 +#define PMAC_HD_CTL_RXSH       (1 << 22)
 107 +
 108 +/* Switch Enable (0=disable, 1=enable) */
 109 +#define GCTL0_SE               0x80000000
 110 +/* Disable MDIO auto polling (0=disable, 1=enable) */
 111 +#define PX_CTL_DMDIO           0x00400000
 112 +
 113 +/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */
 114 +#define MDC_CLOCK_MASK         0xff000000
 115 +#define MDC_CLOCK_OFFSET       24
 116 +
 117 +/* register information for the gbit's MDIO bus */
 118 +#define MDIO_XR9_REQUEST       0x00008000
 119 +#define MDIO_XR9_READ          0x00000800
 120 +#define MDIO_XR9_WRITE         0x00000400
 121 +#define MDIO_XR9_REG_MASK      0x1f
 122 +#define MDIO_XR9_ADDR_MASK     0x1f
 123 +#define MDIO_XR9_RD_MASK       0xffff
 124 +#define MDIO_XR9_REG_OFFSET    0
 125 +#define MDIO_XR9_ADDR_OFFSET   5
 126 +#define MDIO_XR9_WR_OFFSET     16
 127
 128 +#define LTQ_DMA_ETOP   ((of_machine_is_compatible("lantiq,ase")) ? \
 129 +                       (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))
 130 +
 131 +/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
 132  #define ltq_etop_r32(x)                ltq_r32(ltq_etop_membase + (x))
 133  #define ltq_etop_w32(x, y)     ltq_w32(x, ltq_etop_membase + (y))
 134  #define ltq_etop_w32_mask(x, y, z)     \
 135                 ltq_w32_mask(x, y, ltq_etop_membase + (z))
 136
 137 -#define DRV_VERSION    "1.0"
 138 +#define ltq_gbit_r32(x)                ltq_r32(ltq_gbit_membase + (x))
 139 +#define ltq_gbit_w32(x, y)     ltq_w32(x, ltq_gbit_membase + (y))
 140 +#define ltq_gbit_w32_mask(x, y, z)     \
 141 +               ltq_w32_mask(x, y, ltq_gbit_membase + (z))
 142 +
 143 +#define DRV_VERSION    "1.2"
 144
 145  static void __iomem *ltq_etop_membase;
 146 +static void __iomem *ltq_gbit_membase;
 147
 148  struct ltq_etop_chan {
 149 -       int idx;
 150         int tx_free;
 151 +       int irq;
 152         struct net_device *netdev;
 153         struct napi_struct napi;
 154         struct ltq_dma_channel dma;
 155 @@ -88,23 +140,36 @@ struct ltq_etop_chan {
 156  struct ltq_etop_priv {
 157         struct net_device *netdev;
 158         struct platform_device *pdev;
 159 -       struct ltq_eth_data *pldata;
 160         struct resource *res;
 161
 162         struct mii_bus *mii_bus;
 163
 164 -       struct ltq_etop_chan ch[MAX_DMA_CHAN];
 165 -       int tx_free[MAX_DMA_CHAN >> 1];
 166 +       struct ltq_etop_chan txch;
 167 +       struct ltq_etop_chan rxch;
 168
 169 -       spinlock_t lock;
 170 +       int tx_irq;
 171 +       int rx_irq;
 172 +
 173 +       unsigned char mac[6];
 174 +       int mii_mode;
 175 +
 176 +       spinlock_t lock;
 177 +
 178 +       struct clk *clk_ppe;
 179 +       struct clk *clk_switch;
 180 +       struct clk *clk_ephy;
 181 +       struct clk *clk_ephycgu;
 182  };
 183
 184 +static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
 185 +                               int phy_reg, u16 phy_data);
 186 +
 187  static int
 188  ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
 189  {
 190         struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
 191
 192 -       ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
 193 +       ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN);
 194         if (!ch->skb[ch->dma.desc])
 195                 return -ENOMEM;
 196         ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(&priv->pdev->dev,
 197 @@ -139,8 +204,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan
 198         spin_unlock_irqrestore(&priv->lock, flags);
 199
 200         skb_put(skb, len);
 201 +       skb->dev = ch->netdev;
 202         skb->protocol = eth_type_trans(skb, ch->netdev);
 203         netif_receive_skb(skb);
 204 +       ch->netdev->stats.rx_packets++;
 205 +       ch->netdev->stats.rx_bytes += len;
 206  }
 207
 208  static int
 209 @@ -148,7 +216,9 @@ ltq_etop_poll_rx(struct napi_struct *nap
 210  {
 211         struct ltq_etop_chan *ch = container_of(napi,
 212                                 struct ltq_etop_chan, napi);
 213 +       struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
 214         int work_done = 0;
 215 +       unsigned long flags;
 216
 217         while (work_done < budget) {
 218                 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
 219 @@ -160,7 +230,9 @@ ltq_etop_poll_rx(struct napi_struct *nap
 220         }
 221         if (work_done < budget) {
 222                 napi_complete_done(&ch->napi, work_done);
 223 +               spin_lock_irqsave(&priv->lock, flags);
 224                 ltq_dma_ack_irq(&ch->dma);
 225 +               spin_unlock_irqrestore(&priv->lock, flags);
 226         }
 227         return work_done;
 228  }
 229 @@ -172,12 +244,14 @@ ltq_etop_poll_tx(struct napi_struct *nap
 230                 container_of(napi, struct ltq_etop_chan, napi);
 231         struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
 232         struct netdev_queue *txq =
 233 -               netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
 234 +               netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1);
 235         unsigned long flags;
 236
 237         spin_lock_irqsave(&priv->lock, flags);
 238         while ((ch->dma.desc_base[ch->tx_free].ctl &
 239                         (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
 240 +               ch->netdev->stats.tx_packets++;
 241 +               ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len;
 242                 dev_kfree_skb_any(ch->skb[ch->tx_free]);
 243                 ch->skb[ch->tx_free] = NULL;
 244                 memset(&ch->dma.desc_base[ch->tx_free], 0,
 245 @@ -190,7 +264,9 @@ ltq_etop_poll_tx(struct napi_struct *nap
 246         if (netif_tx_queue_stopped(txq))
 247                 netif_tx_start_queue(txq);
 248         napi_complete(&ch->napi);
 249 +       spin_lock_irqsave(&priv->lock, flags);
 250         ltq_dma_ack_irq(&ch->dma);
 251 +       spin_unlock_irqrestore(&priv->lock, flags);
 252         return 1;
 253  }
 254
 255 @@ -198,9 +274,10 @@ static irqreturn_t
 256  ltq_etop_dma_irq(int irq, void *_priv)
 257  {
 258         struct ltq_etop_priv *priv = _priv;
 259 -       int ch = irq - LTQ_DMA_CH0_INT;
 260 -
 261 -       napi_schedule(&priv->ch[ch].napi);
 262 +       if (irq == priv->txch.dma.irq)
 263 +               napi_schedule(&priv->txch.napi);
 264 +       else
 265 +               napi_schedule(&priv->rxch.napi);
 266         return IRQ_HANDLED;
 267  }
 268
 269 @@ -212,7 +289,7 @@ ltq_etop_free_channel(struct net_device
 270         ltq_dma_free(&ch->dma);
 271         if (ch->dma.irq)
 272                 free_irq(ch->dma.irq, priv);
 273 -       if (IS_RX(ch->idx)) {
 274 +       if (ch == &priv->txch) {
 275                 int desc;
 276                 for (desc = 0; desc < LTQ_DESC_NUM; desc++)
 277                         dev_kfree_skb_any(ch->skb[ch->dma.desc]);
 278 @@ -223,66 +300,135 @@ static void
 279  ltq_etop_hw_exit(struct net_device *dev)
 280  {
 281         struct ltq_etop_priv *priv = netdev_priv(dev);
 282 -       int i;
 283
 284 -       ltq_pmu_disable(PMU_PPE);
 285 -       for (i = 0; i < MAX_DMA_CHAN; i++)
 286 -               if (IS_TX(i) || IS_RX(i))
 287 -                       ltq_etop_free_channel(dev, &priv->ch[i]);
 288 +       clk_disable(priv->clk_ppe);
 289 +
 290 +       if (of_machine_is_compatible("lantiq,ar9"))
 291 +               clk_disable(priv->clk_switch);
 292 +
 293 +       if (of_machine_is_compatible("lantiq,ase")) {
 294 +               clk_disable(priv->clk_ephy);
 295 +               clk_disable(priv->clk_ephycgu);
 296 +       }
 297 +
 298 +       ltq_etop_free_channel(dev, &priv->txch);
 299 +       ltq_etop_free_channel(dev, &priv->rxch);
 300 +}
 301 +
 302 +static void
 303 +ltq_etop_gbit_init(struct net_device *dev)
 304 +{
 305 +       struct ltq_etop_priv *priv = netdev_priv(dev);
 306 +
 307 +       clk_enable(priv->clk_switch);
 308 +
 309 +       /* enable gbit port0 on the SoC */
 310 +       ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL);
 311 +
 312 +       ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
 313 +       /* disable MDIO auto polling mode */
 314 +       ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
 315 +       /* set 1522 packet size */
 316 +       ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);
 317 +       /* disable pmac & dmac headers */
 318 +       ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,
 319 +               LTQ_GBIT_PMAC_HD_CTL);
 320 +       /* Due to traffic halt when burst length 8,
 321 +               replace default IPG value with 0x3B */
 322 +       ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
 323 +       /* set mdc clock to 2.5 MHz */
 324 +       ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET,
 325 +               LTQ_GBIT_RGMII_CTL);
 326  }
 327
 328  static int
 329  ltq_etop_hw_init(struct net_device *dev)
 330  {
 331         struct ltq_etop_priv *priv = netdev_priv(dev);
 332 -       int i;
 333 +       int mii_mode = priv->mii_mode;
 334
 335 -       ltq_pmu_enable(PMU_PPE);
 336 +       clk_enable(priv->clk_ppe);
 337
 338 -       switch (priv->pldata->mii_mode) {
 339 +       if (of_machine_is_compatible("lantiq,ar9")) {
 340 +               ltq_etop_gbit_init(dev);
 341 +               /* force the etops link to the gbit to MII */
 342 +               mii_mode = PHY_INTERFACE_MODE_MII;
 343 +       }
 344 +       ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG);
 345 +       ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX |
 346 +                       MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG);
 347 +
 348 +       switch (mii_mode) {
 349         case PHY_INTERFACE_MODE_RMII:
 350 -               ltq_etop_w32_mask(ETOP_MII_MASK,
 351 -                       ETOP_MII_REVERSE, LTQ_ETOP_CFG);
 352 +               ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 |
 353 +                       ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
 354                 break;
 355
 356         case PHY_INTERFACE_MODE_MII:
 357 -               ltq_etop_w32_mask(ETOP_MII_MASK,
 358 -                       ETOP_MII_NORMAL, LTQ_ETOP_CFG);
 359 +               ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 |
 360 +                       ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
 361                 break;
 362
 363         default:
 364 +               if (of_machine_is_compatible("lantiq,ase")) {
 365 +                       clk_enable(priv->clk_ephy);
 366 +                       /* disable external MII */
 367 +                       ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
 368 +                       /* enable clock for internal PHY */
 369 +                       clk_enable(priv->clk_ephycgu);
 370 +                       /* we need to write this magic to the internal phy to
 371 +                          make it work */
 372 +                       ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
 373 +                       pr_info("Selected EPHY mode\n");
 374 +                       break;
 375 +               }
 376                 netdev_err(dev, "unknown mii mode %d\n",
 377 -                       priv->pldata->mii_mode);
 378 +                       mii_mode);
 379                 return -ENOTSUPP;
 380         }
 381
 382 -       /* enable crc generation */
 383 -       ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
 384 +       return 0;
 385 +}
 386 +
 387 +static int
 388 +ltq_etop_dma_init(struct net_device *dev)
 389 +{
 390 +       struct ltq_etop_priv *priv = netdev_priv(dev);
 391 +       int tx = priv->tx_irq - LTQ_DMA_ETOP;
 392 +       int rx = priv->rx_irq - LTQ_DMA_ETOP;
 393 +       int err;
 394
 395         ltq_dma_init_port(DMA_PORT_ETOP);
 396
 397 -       for (i = 0; i < MAX_DMA_CHAN; i++) {
 398 -               int irq = LTQ_DMA_CH0_INT + i;
 399 -               struct ltq_etop_chan *ch = &priv->ch[i];
 400 -
 401 -               ch->idx = ch->dma.nr = i;
 402 -               ch->dma.dev = &priv->pdev->dev;
 403 -
 404 -               if (IS_TX(i)) {
 405 -                       ltq_dma_alloc_tx(&ch->dma);
 406 -                       request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
 407 -               } else if (IS_RX(i)) {
 408 -                       ltq_dma_alloc_rx(&ch->dma);
 409 -                       for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
 410 -                                       ch->dma.desc++)
 411 -                               if (ltq_etop_alloc_skb(ch))
 412 -                                       return -ENOMEM;
 413 -                       ch->dma.desc = 0;
 414 -                       request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
 415 +       priv->txch.dma.nr = tx;
 416 +       priv->txch.dma.dev = &priv->pdev->dev;
 417 +       ltq_dma_alloc_tx(&priv->txch.dma);
 418 +       err = request_irq(priv->tx_irq, ltq_etop_dma_irq, 0, "eth_tx", priv);
 419 +       if (err) {
 420 +               netdev_err(dev, "failed to allocate tx irq\n");
 421 +               goto err_out;
 422 +       }
 423 +       priv->txch.dma.irq = priv->tx_irq;
 424 +
 425 +       priv->rxch.dma.nr = rx;
 426 +       priv->rxch.dma.dev = &priv->pdev->dev;
 427 +       ltq_dma_alloc_rx(&priv->rxch.dma);
 428 +       for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM;
 429 +                       priv->rxch.dma.desc++) {
 430 +               if (ltq_etop_alloc_skb(&priv->rxch)) {
 431 +                       netdev_err(dev, "failed to allocate skbs\n");
 432 +                       err = -ENOMEM;
 433 +                       goto err_out;
 434                 }
 435 -               ch->dma.irq = irq;
 436         }
 437 -       return 0;
 438 +       priv->rxch.dma.desc = 0;
 439 +       err = request_irq(priv->rx_irq, ltq_etop_dma_irq, 0, "eth_rx", priv);
 440 +       if (err)
 441 +               netdev_err(dev, "failed to allocate rx irq\n");
 442 +       else
 443 +               priv->rxch.dma.irq = priv->rx_irq;
 444 +err_out:
 445 +       return err;
 446  }
 447
 448  static void
 449 @@ -301,6 +447,39 @@ static const struct ethtool_ops ltq_etop
 450  };
 451
 452  static int
 453 +ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,
 454 +               int phy_reg, u16 phy_data)
 455 +{
 456 +       u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |
 457 +               (phy_data << MDIO_XR9_WR_OFFSET) |
 458 +               ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
 459 +               ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
 460 +
 461 +       while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
 462 +               ;
 463 +       ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
 464 +       while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
 465 +               ;
 466 +       return 0;
 467 +}
 468 +
 469 +static int
 470 +ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)
 471 +{
 472 +       u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |
 473 +               ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
 474 +               ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
 475 +
 476 +       while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
 477 +               ;
 478 +       ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
 479 +       while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
 480 +               ;
 481 +       val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;
 482 +       return val;
 483 +}
 484 +
 485 +static int
 486  ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
 487  {
 488         u32 val = MDIO_REQUEST |
 489 @@ -308,9 +487,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in
 490                 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
 491                 phy_data;
 492
 493 -       while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
 494 +       while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
 495                 ;
 496 -       ltq_etop_w32(val, LTQ_ETOP_MDIO);
 497 +       ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
 498         return 0;
 499  }
 500
 501 @@ -321,12 +500,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in
 502                 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
 503                 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
 504
 505 -       while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
 506 +       while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
 507                 ;
 508 -       ltq_etop_w32(val, LTQ_ETOP_MDIO);
 509 -       while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
 510 +       ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
 511 +       while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
 512                 ;
 513 -       val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
 514 +       val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK;
 515         return val;
 516  }
 517
 518 @@ -342,7 +521,10 @@ ltq_etop_mdio_probe(struct net_device *d
 519         struct ltq_etop_priv *priv = netdev_priv(dev);
 520         struct phy_device *phydev;
 521
 522 -       phydev = phy_find_first(priv->mii_bus);
 523 +       if (of_machine_is_compatible("lantiq,ase"))
 524 +               phydev = mdiobus_get_phy(priv->mii_bus, 8);
 525 +       else
 526 +               phydev = mdiobus_get_phy(priv->mii_bus, 0);
 527
 528         if (!phydev) {
 529                 netdev_err(dev, "no PHY found\n");
 530 @@ -350,14 +532,17 @@ ltq_etop_mdio_probe(struct net_device *d
 531         }
 532
 533         phydev = phy_connect(dev, phydev_name(phydev),
 534 -                            &ltq_etop_mdio_link, priv->pldata->mii_mode);
 535 +                            &ltq_etop_mdio_link, priv->mii_mode);
 536
 537         if (IS_ERR(phydev)) {
 538                 netdev_err(dev, "Could not attach to PHY\n");
 539                 return PTR_ERR(phydev);
 540         }
 541
 542 -       phy_set_max_speed(phydev, SPEED_100);
 543 +       if (of_machine_is_compatible("lantiq,ar9"))
 544 +               phy_set_max_speed(phydev, SPEED_1000);
 545 +       else
 546 +               phy_set_max_speed(phydev, SPEED_100);
 547
 548         phy_attached_info(phydev);
 549
 550 @@ -378,8 +563,13 @@ ltq_etop_mdio_init(struct net_device *de
 551         }
 552
 553         priv->mii_bus->priv = dev;
 554 -       priv->mii_bus->read = ltq_etop_mdio_rd;
 555 -       priv->mii_bus->write = ltq_etop_mdio_wr;
 556 +       if (of_machine_is_compatible("lantiq,ar9")) {
 557 +               priv->mii_bus->read = ltq_etop_mdio_rd_xr9;
 558 +               priv->mii_bus->write = ltq_etop_mdio_wr_xr9;
 559 +       } else {
 560 +               priv->mii_bus->read = ltq_etop_mdio_rd;
 561 +               priv->mii_bus->write = ltq_etop_mdio_wr;
 562 +       }
 563         priv->mii_bus->name = "ltq_mii";
 564         snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
 565                 priv->pdev->name, priv->pdev->id);
 566 @@ -416,18 +606,21 @@ static int
 567  ltq_etop_open(struct net_device *dev)
 568  {
 569         struct ltq_etop_priv *priv = netdev_priv(dev);
 570 -       int i;
 571 +       unsigned long flags;
 572
 573 -       for (i = 0; i < MAX_DMA_CHAN; i++) {
 574 -               struct ltq_etop_chan *ch = &priv->ch[i];
 575 +       napi_enable(&priv->txch.napi);
 576 +       napi_enable(&priv->rxch.napi);
 577 +
 578 +       spin_lock_irqsave(&priv->lock, flags);
 579 +       ltq_dma_open(&priv->txch.dma);
 580 +       ltq_dma_enable_irq(&priv->txch.dma);
 581 +       ltq_dma_open(&priv->rxch.dma);
 582 +       ltq_dma_enable_irq(&priv->rxch.dma);
 583 +       spin_unlock_irqrestore(&priv->lock, flags);
 584 +
 585 +       if (dev->phydev)
 586 +               phy_start(dev->phydev);
 587
 588 -               if (!IS_TX(i) && (!IS_RX(i)))
 589 -                       continue;
 590 -               ltq_dma_open(&ch->dma);
 591 -               ltq_dma_enable_irq(&ch->dma);
 592 -               napi_enable(&ch->napi);
 593 -       }
 594 -       phy_start(dev->phydev);
 595         netif_tx_start_all_queues(dev);
 596         return 0;
 597  }
 598 @@ -436,18 +629,19 @@ static int
 599  ltq_etop_stop(struct net_device *dev)
 600  {
 601         struct ltq_etop_priv *priv = netdev_priv(dev);
 602 -       int i;
 603 +       unsigned long flags;
 604
 605         netif_tx_stop_all_queues(dev);
 606 -       phy_stop(dev->phydev);
 607 -       for (i = 0; i < MAX_DMA_CHAN; i++) {
 608 -               struct ltq_etop_chan *ch = &priv->ch[i];
 609 -
 610 -               if (!IS_RX(i) && !IS_TX(i))
 611 -                       continue;
 612 -               napi_disable(&ch->napi);
 613 -               ltq_dma_close(&ch->dma);
 614 -       }
 615 +       if (dev->phydev)
 616 +               phy_stop(dev->phydev);
 617 +       napi_disable(&priv->txch.napi);
 618 +       napi_disable(&priv->rxch.napi);
 619 +
 620 +       spin_lock_irqsave(&priv->lock, flags);
 621 +       ltq_dma_close(&priv->txch.dma);
 622 +       ltq_dma_close(&priv->rxch.dma);
 623 +       spin_unlock_irqrestore(&priv->lock, flags);
 624 +
 625         return 0;
 626  }
 627
 628 @@ -457,16 +651,16 @@ ltq_etop_tx(struct sk_buff *skb, struct
 629         int queue = skb_get_queue_mapping(skb);
 630         struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
 631         struct ltq_etop_priv *priv = netdev_priv(dev);
 632 -       struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
 633 -       struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
 634 -       int len;
 635 +       struct ltq_dma_desc *desc =
 636 +               &priv->txch.dma.desc_base[priv->txch.dma.desc];
 637         unsigned long flags;
 638         u32 byte_offset;
 639 +       int len;
 640
 641         len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
 642
 643 -       if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
 644 -               dev_kfree_skb_any(skb);
 645 +       if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) ||
 646 +                       priv->txch.skb[priv->txch.dma.desc]) {
 647                 netdev_err(dev, "tx ring full\n");
 648                 netif_tx_stop_queue(txq);
 649                 return NETDEV_TX_BUSY;
 650 @@ -474,7 +668,7 @@ ltq_etop_tx(struct sk_buff *skb, struct
 651
 652         /* dma needs to start on a 16 byte aligned address */
 653         byte_offset = CPHYSADDR(skb->data) % 16;
 654 -       ch->skb[ch->dma.desc] = skb;
 655 +       priv->txch.skb[priv->txch.dma.desc] = skb;
 656
 657         netif_trans_update(dev);
 658
 659 @@ -484,11 +678,11 @@ ltq_etop_tx(struct sk_buff *skb, struct
 660         wmb();
 661         desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
 662                 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
 663 -       ch->dma.desc++;
 664 -       ch->dma.desc %= LTQ_DESC_NUM;
 665 +       priv->txch.dma.desc++;
 666 +       priv->txch.dma.desc %= LTQ_DESC_NUM;
 667         spin_unlock_irqrestore(&priv->lock, flags);
 668
 669 -       if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
 670 +       if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN)
 671                 netif_tx_stop_queue(txq);
 672
 673         return NETDEV_TX_OK;
 674 @@ -499,11 +693,14 @@ ltq_etop_change_mtu(struct net_device *d
 675  {
 676         struct ltq_etop_priv *priv = netdev_priv(dev);
 677         unsigned long flags;
 678 +       int max;
 679
 680         dev->mtu = new_mtu;
 681
 682 +       max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN;
 683 +
 684         spin_lock_irqsave(&priv->lock, flags);
 685 -       ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN);
 686 +       ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max, LTQ_ETOP_IGPLEN);
 687         spin_unlock_irqrestore(&priv->lock, flags);
 688
 689         return 0;
 690 @@ -563,6 +760,9 @@ ltq_etop_init(struct net_device *dev)
 691         if (err)
 692                 goto err_hw;
 693         ltq_etop_change_mtu(dev, 1500);
 694 +       err = ltq_etop_dma_init(dev);
 695 +       if (err)
 696 +               goto err_hw;
 697
 698         memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
 699         if (!is_valid_ether_addr(mac.sa_data)) {
 700 @@ -580,9 +780,10 @@ ltq_etop_init(struct net_device *dev)
 701                 dev->addr_assign_type = NET_ADDR_RANDOM;
 702
 703         ltq_etop_set_multicast_list(dev);
 704 -       err = ltq_etop_mdio_init(dev);
 705 -       if (err)
 706 -               goto err_netdev;
 707 +       if (!ltq_etop_mdio_init(dev))
 708 +               dev->ethtool_ops = &ltq_etop_ethtool_ops;
 709 +       else
 710 +               pr_warn("etop: mdio probe failed\n");;
 711         return 0;
 712
 713  err_netdev:
 714 @@ -602,6 +803,9 @@ ltq_etop_tx_timeout(struct net_device *d
 715         err = ltq_etop_hw_init(dev);
 716         if (err)
 717                 goto err_hw;
 718 +       err = ltq_etop_dma_init(dev);
 719 +       if (err)
 720 +               goto err_hw;
 721         netif_trans_update(dev);
 722         netif_wake_queue(dev);
 723         return;
 724 @@ -625,14 +829,19 @@ static const struct net_device_ops ltq_e
 725         .ndo_tx_timeout = ltq_etop_tx_timeout,
 726  };
 727
 728 -static int __init
 729 -ltq_etop_probe(struct platform_device *pdev)
 730 +static int ltq_etop_probe(struct platform_device *pdev)
 731  {
 732         struct net_device *dev;
 733         struct ltq_etop_priv *priv;
 734 -       struct resource *res;
 735 +       struct resource *res, *gbit_res, irqres[2];
 736 +       const u8 *mac;
 737         int err;
 738 -       int i;
 739 +
 740 +       err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2);
 741 +       if (err != 2) {
 742 +               dev_err(&pdev->dev, "failed to get etop irqs\n");
 743 +               return -EINVAL;
 744 +       }
 745
 746         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 747         if (!res) {
 748 @@ -658,31 +867,62 @@ ltq_etop_probe(struct platform_device *p
 749                 goto err_out;
 750         }
 751
 752 -       dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
 753 -       if (!dev) {
 754 -               err = -ENOMEM;
 755 -               goto err_out;
 756 +       if (of_machine_is_compatible("lantiq,ar9")) {
 757 +               gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 758 +               if (!gbit_res) {
 759 +                       dev_err(&pdev->dev, "failed to get gbit resource\n");
 760 +                       err = -ENOENT;
 761 +                       goto err_out;
 762 +               }
 763 +               ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev,
 764 +                       gbit_res->start, resource_size(gbit_res));
 765 +               if (!ltq_gbit_membase) {
 766 +                       dev_err(&pdev->dev, "failed to remap gigabit switch %d\n",
 767 +                               pdev->id);
 768 +                       err = -ENOMEM;
 769 +                       goto err_out;
 770 +               }
 771         }
 772 +
 773 +       dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
 774         strcpy(dev->name, "eth%d");
 775         dev->netdev_ops = &ltq_eth_netdev_ops;
 776 -       dev->ethtool_ops = &ltq_etop_ethtool_ops;
 777         priv = netdev_priv(dev);
 778         priv->res = res;
 779         priv->pdev = pdev;
 780 -       priv->pldata = dev_get_platdata(&pdev->dev);
 781         priv->netdev = dev;
 782 +       priv->tx_irq = irqres[0].start;
 783 +       priv->rx_irq = irqres[1].start;
 784 +       priv->mii_mode = of_get_phy_mode(pdev->dev.of_node);
 785 +
 786 +       mac = of_get_mac_address(pdev->dev.of_node);
 787 +       if (mac)
 788 +               memcpy(priv->mac, mac, ETH_ALEN);
 789 +
 790 +       priv->clk_ppe = clk_get(&pdev->dev, NULL);
 791 +       if (IS_ERR(priv->clk_ppe))
 792 +               return PTR_ERR(priv->clk_ppe);
 793 +       if (of_machine_is_compatible("lantiq,ar9")) {
 794 +               priv->clk_switch = clk_get(&pdev->dev, "switch");
 795 +               if (IS_ERR(priv->clk_switch))
 796 +                       return PTR_ERR(priv->clk_switch);
 797 +       }
 798 +       if (of_machine_is_compatible("lantiq,ase")) {
 799 +               priv->clk_ephy = clk_get(&pdev->dev, "ephy");
 800 +               if (IS_ERR(priv->clk_ephy))
 801 +                       return PTR_ERR(priv->clk_ephy);
 802 +               priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
 803 +               if (IS_ERR(priv->clk_ephycgu))
 804 +                       return PTR_ERR(priv->clk_ephycgu);
 805 +       }
 806 +
 807         spin_lock_init(&priv->lock);
 808         SET_NETDEV_DEV(dev, &pdev->dev);
 809
 810 -       for (i = 0; i < MAX_DMA_CHAN; i++) {
 811 -               if (IS_TX(i))
 812 -                       netif_napi_add(dev, &priv->ch[i].napi,
 813 -                               ltq_etop_poll_tx, 8);
 814 -               else if (IS_RX(i))
 815 -                       netif_napi_add(dev, &priv->ch[i].napi,
 816 -                               ltq_etop_poll_rx, 32);
 817 -               priv->ch[i].netdev = dev;
 818 -       }
 819 +       netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);
 820 +       netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);
 821 +       priv->txch.netdev = dev;
 822 +       priv->rxch.netdev = dev;
 823
 824         err = register_netdev(dev);
 825         if (err)
 826 @@ -711,31 +951,22 @@ ltq_etop_remove(struct platform_device *
 827         return 0;
 828  }
 829
 830 +static const struct of_device_id ltq_etop_match[] = {
 831 +       { .compatible = "lantiq,etop-xway" },
 832 +       {},
 833 +};
 834 +MODULE_DEVICE_TABLE(of, ltq_etop_match);
 835 +
 836  static struct platform_driver ltq_mii_driver = {
 837 +       .probe = ltq_etop_probe,
 838         .remove = ltq_etop_remove,
 839         .driver = {
 840                 .name = "ltq_etop",
 841 +               .of_match_table = ltq_etop_match,
 842         },
 843  };
 844
 845 -int __init
 846 -init_ltq_etop(void)
 847 -{
 848 -       int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
 849 -
 850 -       if (ret)
 851 -               pr_err("ltq_etop: Error registering platform driver!");
 852 -       return ret;
 853 -}
 854 -
 855 -static void __exit
 856 -exit_ltq_etop(void)
 857 -{
 858 -       platform_driver_unregister(&ltq_mii_driver);
 859 -}
 860 -
 861 -module_init(init_ltq_etop);
 862 -module_exit(exit_ltq_etop);
 863 +module_platform_driver(ltq_mii_driver);
 864
 865  MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 866  MODULE_DESCRIPTION("Lantiq SoC ETOP");