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kernel: bump 4.9 to 4.9.63
[openwrt/staging/mkresin.git] / target / linux / layerscape / patches-4.9 / 817-usb-support-layerscape.patch
1 From b14460ee524a34d3b94b44032b52155c4cd708e5 Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Wed, 27 Sep 2017 10:34:07 +0800
4 Subject: [PATCH] usb: support layerscape
5
6 This is a integrated patch for layerscape usb support.
7
8 Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
9 Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
10 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
11 Signed-off-by: Changming Huang <jerry.huang@nxp.com>
12 Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
13 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com>
14 Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
15 Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
16 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
17 ---
18 drivers/net/usb/r8152.c | 4 +
19 drivers/usb/common/common.c | 50 ++++++
20 drivers/usb/core/hub.c | 8 +
21 drivers/usb/dwc3/core.c | 235 ++++++++++++++++++++++++++-
22 drivers/usb/dwc3/core.h | 46 +++++-
23 drivers/usb/dwc3/host.c | 15 +-
24 drivers/usb/gadget/udc/fsl_udc_core.c | 46 +++---
25 drivers/usb/gadget/udc/fsl_usb2_udc.h | 16 +-
26 drivers/usb/host/Kconfig | 2 +-
27 drivers/usb/host/ehci-fsl.c | 289 +++++++++++++++++++++++++++++++---
28 drivers/usb/host/ehci-fsl.h | 3 +
29 drivers/usb/host/ehci-hub.c | 2 +
30 drivers/usb/host/ehci.h | 5 +
31 drivers/usb/host/fsl-mph-dr-of.c | 12 ++
32 drivers/usb/phy/phy-fsl-usb.c | 59 +++++--
33 drivers/usb/phy/phy-fsl-usb.h | 8 +
34 include/linux/usb.h | 1 +
35 include/linux/usb/of.h | 2 +
36 18 files changed, 730 insertions(+), 73 deletions(-)
37
38 --- a/drivers/net/usb/r8152.c
39 +++ b/drivers/net/usb/r8152.c
40 @@ -1812,6 +1812,10 @@ static int rx_bottom(struct r8152 *tp, i
41 unsigned int pkt_len;
42 struct sk_buff *skb;
43
44 + /* limite the skb numbers for rx_queue */
45 + if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
46 + break;
47 +
48 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
49 if (pkt_len < ETH_ZLEN)
50 break;
51 --- a/drivers/usb/common/common.c
52 +++ b/drivers/usb/common/common.c
53 @@ -105,6 +105,56 @@ static const char *const usb_dr_modes[]
54 [USB_DR_MODE_OTG] = "otg",
55 };
56
57 +/**
58 + * of_usb_get_dr_mode - Get dual role mode for given device_node
59 + * @np: Pointer to the given device_node
60 + *
61 + * The function gets phy interface string from property 'dr_mode',
62 + * and returns the correspondig enum usb_dr_mode
63 + */
64 +enum usb_dr_mode of_usb_get_dr_mode(struct device_node *np)
65 +{
66 + const char *dr_mode;
67 + int err, i;
68 +
69 + err = of_property_read_string(np, "dr_mode", &dr_mode);
70 + if (err < 0)
71 + return USB_DR_MODE_UNKNOWN;
72 +
73 + for (i = 0; i < ARRAY_SIZE(usb_dr_modes); i++)
74 + if (!strcmp(dr_mode, usb_dr_modes[i]))
75 + return i;
76 +
77 + return USB_DR_MODE_UNKNOWN;
78 +}
79 +EXPORT_SYMBOL_GPL(of_usb_get_dr_mode);
80 +
81 +/**
82 + * of_usb_get_maximum_speed - Get maximum requested speed for a given USB
83 + * controller.
84 + * @np: Pointer to the given device_node
85 + *
86 + * The function gets the maximum speed string from property "maximum-speed",
87 + * and returns the corresponding enum usb_device_speed.
88 + */
89 +enum usb_device_speed of_usb_get_maximum_speed(struct device_node *np)
90 +{
91 + const char *maximum_speed;
92 + int err;
93 + int i;
94 +
95 + err = of_property_read_string(np, "maximum-speed", &maximum_speed);
96 + if (err < 0)
97 + return USB_SPEED_UNKNOWN;
98 +
99 + for (i = 0; i < ARRAY_SIZE(speed_names); i++)
100 + if (strcmp(maximum_speed, speed_names[i]) == 0)
101 + return i;
102 +
103 + return USB_SPEED_UNKNOWN;
104 +}
105 +EXPORT_SYMBOL_GPL(of_usb_get_maximum_speed);
106 +
107 static enum usb_dr_mode usb_get_dr_mode_from_string(const char *str)
108 {
109 int ret;
110 --- a/drivers/usb/core/hub.c
111 +++ b/drivers/usb/core/hub.c
112 @@ -4415,6 +4415,14 @@ hub_port_init(struct usb_hub *hub, struc
113 else
114 speed = usb_speed_string(udev->speed);
115
116 +#if !defined(CONFIG_FSL_USB2_OTG) && !defined(CONFIG_FSL_USB2_OTG_MODULE)
117 +if (udev->speed != USB_SPEED_SUPER)
118 + dev_info(&udev->dev,
119 + "%s %s USB device number %d using %s\n",
120 + (udev->config) ? "reset" : "new", speed,
121 + devnum, udev->bus->controller->driver->name);
122 +#endif
123 +
124 if (udev->speed < USB_SPEED_SUPER)
125 dev_info(&udev->dev,
126 "%s %s USB device number %d using %s\n",
127 --- a/drivers/usb/dwc3/core.c
128 +++ b/drivers/usb/dwc3/core.c
129 @@ -58,6 +58,7 @@ static int dwc3_get_dr_mode(struct dwc3
130 enum usb_dr_mode mode;
131 struct device *dev = dwc->dev;
132 unsigned int hw_mode;
133 + struct device_node *node = dev->of_node;
134
135 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
136 dwc->dr_mode = USB_DR_MODE_OTG;
137 @@ -83,6 +84,24 @@ static int dwc3_get_dr_mode(struct dwc3
138 mode = USB_DR_MODE_HOST;
139 break;
140 default:
141 + /* Adjust Frame Length */
142 + if (dwc->configure_gfladj)
143 + dwc3_writel(dwc->regs, DWC3_GFLADJ, GFLADJ_30MHZ_REG_SEL |
144 + GFLADJ_30MHZ(GFLADJ_30MHZ_DEFAULT));
145 +
146 + /* Change burst beat and outstanding pipelined transfers requests */
147 + dwc3_writel(dwc->regs, DWC3_GSBUSCFG0,
148 + (dwc3_readl(dwc->regs, DWC3_GSBUSCFG0) & ~0xff) | 0xf);
149 + dwc3_writel(dwc->regs, DWC3_GSBUSCFG1,
150 + dwc3_readl(dwc->regs, DWC3_GSBUSCFG1) | 0xf00);
151 +
152 + /* Enable Snooping */
153 + if (node && of_dma_is_coherent(node)) {
154 + dwc3_writel(dwc->regs, DWC3_GSBUSCFG0,
155 + dwc3_readl(dwc->regs, DWC3_GSBUSCFG0) | 0x22220000);
156 + dev_dbg(dev, "enabled snooping for usb\n");
157 + }
158 +
159 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
160 mode = USB_DR_MODE_HOST;
161 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
162 @@ -213,8 +232,9 @@ static void dwc3_frame_length_adjustment
163
164 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
165 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
166 - if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
167 - "request value same as default, ignoring\n")) {
168 + if (dft == dwc->fladj) {
169 + dev_warn(dwc->dev, "request value same as default, ignoring\n");
170 + } else {
171 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
172 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
173 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
174 @@ -579,6 +599,99 @@ static int dwc3_phy_setup(struct dwc3 *d
175 return 0;
176 }
177
178 +/* set global soc bus configuration registers */
179 +static void dwc3_set_soc_bus_cfg(struct dwc3 *dwc)
180 +{
181 + struct device *dev = dwc->dev;
182 + u32 *vals;
183 + u32 cfg;
184 + int ntype;
185 + int ret;
186 + int i;
187 +
188 + cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
189 +
190 + /*
191 + * Handle property "snps,incr-burst-type-adjustment".
192 + * Get the number of value from this property:
193 + * result <= 0, means this property is not supported.
194 + * result = 1, means INCRx burst mode supported.
195 + * result > 1, means undefined length burst mode supported.
196 + */
197 + ntype = device_property_read_u32_array(dev,
198 + "snps,incr-burst-type-adjustment", NULL, 0);
199 + if (ntype > 0) {
200 + vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
201 + if (!vals) {
202 + dev_err(dev, "Error to get memory\n");
203 + return;
204 + }
205 + /* Get INCR burst type, and parse it */
206 + ret = device_property_read_u32_array(dev,
207 + "snps,incr-burst-type-adjustment", vals, ntype);
208 + if (ret) {
209 + dev_err(dev, "Error to get property\n");
210 + return;
211 + }
212 + *(dwc->incrx_type + 1) = vals[0];
213 + if (ntype > 1) {
214 + *dwc->incrx_type = 1;
215 + for (i = 1; i < ntype; i++) {
216 + if (vals[i] > *(dwc->incrx_type + 1))
217 + *(dwc->incrx_type + 1) = vals[i];
218 + }
219 + } else
220 + *dwc->incrx_type = 0;
221 +
222 + /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
223 + cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
224 + if (*dwc->incrx_type)
225 + cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
226 + switch (*(dwc->incrx_type + 1)) {
227 + case 256:
228 + cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
229 + break;
230 + case 128:
231 + cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
232 + break;
233 + case 64:
234 + cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
235 + break;
236 + case 32:
237 + cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
238 + break;
239 + case 16:
240 + cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
241 + break;
242 + case 8:
243 + cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
244 + break;
245 + case 4:
246 + cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
247 + break;
248 + case 1:
249 + break;
250 + default:
251 + dev_err(dev, "Invalid property\n");
252 + break;
253 + }
254 + }
255 +
256 + /* Handle usb snooping */
257 + if (dwc->dma_snooping_quirk) {
258 + cfg &= ~DWC3_GSBUSCFG0_SNP_MASK;
259 + cfg |= (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DATARD_SHIFT) |
260 + (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DESCRD_SHIFT) |
261 + (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DATAWR_SHIFT) |
262 + (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DESCWR_SHIFT);
263 + }
264 +
265 + dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
266 +
267 +}
268 +
269 +
270 +
271 static void dwc3_core_exit(struct dwc3 *dwc)
272 {
273 dwc3_event_buffers_cleanup(dwc);
274 @@ -721,6 +834,8 @@ static int dwc3_core_init(struct dwc3 *d
275 if (ret)
276 goto err1;
277
278 + dwc3_set_soc_bus_cfg(dwc);
279 +
280 /* Adjust Frame Length */
281 dwc3_frame_length_adjustment(dwc);
282
283 @@ -919,11 +1034,109 @@ static void dwc3_core_exit_mode(struct d
284 }
285 }
286
287 +static void dwc3_get_properties(struct dwc3 *dwc)
288 +{
289 + struct device *dev = dwc->dev;
290 + struct device_node *node = dev->of_node;
291 + u8 lpm_nyet_threshold;
292 + u8 tx_de_emphasis;
293 + u8 hird_threshold;
294 +
295 + /* default to highest possible threshold */
296 + lpm_nyet_threshold = 0xff;
297 +
298 + /* default to -3.5dB de-emphasis */
299 + tx_de_emphasis = 1;
300 +
301 + /*
302 + * default to assert utmi_sleep_n and use maximum allowed HIRD
303 + * threshold value of 0b1100
304 + */
305 + hird_threshold = 12;
306 +
307 + dwc->maximum_speed = usb_get_maximum_speed(dev);
308 + dwc->dr_mode = usb_get_dr_mode(dev);
309 + dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
310 +
311 + dwc->sysdev_is_parent = device_property_read_bool(dev,
312 + "linux,sysdev_is_parent");
313 + if (dwc->sysdev_is_parent)
314 + dwc->sysdev = dwc->dev->parent;
315 + else
316 + dwc->sysdev = dwc->dev;
317 +
318 + dwc->has_lpm_erratum = device_property_read_bool(dev,
319 + "snps,has-lpm-erratum");
320 + device_property_read_u8(dev, "snps,lpm-nyet-threshold",
321 + &lpm_nyet_threshold);
322 + dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
323 + "snps,is-utmi-l1-suspend");
324 + device_property_read_u8(dev, "snps,hird-threshold",
325 + &hird_threshold);
326 + dwc->usb3_lpm_capable = device_property_read_bool(dev,
327 + "snps,usb3_lpm_capable");
328 +
329 + dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
330 +
331 + dwc->configure_gfladj =
332 + of_property_read_bool(node, "configure-gfladj");
333 + dwc->dr_mode = usb_get_dr_mode(dev);
334 +
335 + dwc->disable_scramble_quirk = device_property_read_bool(dev,
336 + "snps,disable_scramble_quirk");
337 + dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
338 + "snps,u2exit_lfps_quirk");
339 + dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
340 + "snps,u2ss_inp3_quirk");
341 + dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
342 + "snps,req_p1p2p3_quirk");
343 + dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
344 + "snps,del_p1p2p3_quirk");
345 + dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
346 + "snps,del_phy_power_chg_quirk");
347 + dwc->lfps_filter_quirk = device_property_read_bool(dev,
348 + "snps,lfps_filter_quirk");
349 + dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
350 + "snps,rx_detect_poll_quirk");
351 + dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
352 + "snps,dis_u3_susphy_quirk");
353 + dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
354 + "snps,dis_u2_susphy_quirk");
355 + dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
356 + "snps,dis_enblslpm_quirk");
357 + dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
358 + "snps,dis_rxdet_inp3_quirk");
359 + dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
360 + "snps,dis-u2-freeclk-exists-quirk");
361 + dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
362 + "snps,dis-del-phy-power-chg-quirk");
363 + dwc->dma_snooping_quirk = device_property_read_bool(dev,
364 + "snps,dma-snooping");
365 +
366 + dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
367 + "snps,tx_de_emphasis_quirk");
368 + device_property_read_u8(dev, "snps,tx_de_emphasis",
369 + &tx_de_emphasis);
370 + device_property_read_string(dev, "snps,hsphy_interface",
371 + &dwc->hsphy_interface);
372 + device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
373 + &dwc->fladj);
374 +
375 + dwc->lpm_nyet_threshold = lpm_nyet_threshold;
376 + dwc->tx_de_emphasis = tx_de_emphasis;
377 +
378 + dwc->hird_threshold = hird_threshold
379 + | (dwc->is_utmi_l1_suspend << 4);
380 +
381 + dwc->imod_interval = 0;
382 +}
383 +
384 #define DWC3_ALIGN_MASK (16 - 1)
385
386 static int dwc3_probe(struct platform_device *pdev)
387 {
388 struct device *dev = &pdev->dev;
389 + struct device_node *node = dev->of_node;
390 struct resource *res;
391 struct dwc3 *dwc;
392 u8 lpm_nyet_threshold;
393 @@ -955,6 +1168,11 @@ static int dwc3_probe(struct platform_de
394 dwc->xhci_resources[0].flags = res->flags;
395 dwc->xhci_resources[0].name = res->name;
396
397 + if (node) {
398 + dwc->configure_gfladj =
399 + of_property_read_bool(node, "configure-gfladj");
400 + }
401 +
402 res->start += DWC3_GLOBALS_REGS_START;
403
404 /*
405 @@ -997,6 +1215,12 @@ static int dwc3_probe(struct platform_de
406 dwc->usb3_lpm_capable = device_property_read_bool(dev,
407 "snps,usb3_lpm_capable");
408
409 + dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
410 +
411 + dwc->configure_gfladj =
412 + of_property_read_bool(node, "configure-gfladj");
413 + dwc->dr_mode = of_usb_get_dr_mode(node);
414 +
415 dwc->disable_scramble_quirk = device_property_read_bool(dev,
416 "snps,disable_scramble_quirk");
417 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
418 @@ -1041,6 +1265,8 @@ static int dwc3_probe(struct platform_de
419 dwc->hird_threshold = hird_threshold
420 | (dwc->is_utmi_l1_suspend << 4);
421
422 + dwc3_get_properties(dwc);
423 +
424 platform_set_drvdata(pdev, dwc);
425 dwc3_cache_hwparams(dwc);
426
427 @@ -1064,6 +1290,11 @@ static int dwc3_probe(struct platform_de
428 if (ret < 0)
429 goto err1;
430
431 + /* Adjust Frame Length */
432 + if (dwc->configure_gfladj)
433 + dwc3_writel(dwc->regs, DWC3_GFLADJ, GFLADJ_30MHZ_REG_SEL |
434 + GFLADJ_30MHZ(GFLADJ_30MHZ_DEFAULT));
435 +
436 pm_runtime_forbid(dev);
437
438 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
439 --- a/drivers/usb/dwc3/core.h
440 +++ b/drivers/usb/dwc3/core.h
441 @@ -26,6 +26,7 @@
442 #include <linux/dma-mapping.h>
443 #include <linux/mm.h>
444 #include <linux/debugfs.h>
445 +#include <linux/of_address.h>
446
447 #include <linux/usb/ch9.h>
448 #include <linux/usb/gadget.h>
449 @@ -154,6 +155,32 @@
450
451 /* Bit fields */
452
453 +/* Global SoC Bus Configuration Register 0 */
454 +#define AXI3_CACHE_TYPE_AW 0x8 /* write allocate */
455 +#define AXI3_CACHE_TYPE_AR 0x4 /* read allocate */
456 +#define AXI3_CACHE_TYPE_SNP 0x2 /* cacheable */
457 +#define AXI3_CACHE_TYPE_BUF 0x1 /* bufferable */
458 +#define DWC3_GSBUSCFG0_DATARD_SHIFT 28
459 +#define DWC3_GSBUSCFG0_DESCRD_SHIFT 24
460 +#define DWC3_GSBUSCFG0_DATAWR_SHIFT 20
461 +#define DWC3_GSBUSCFG0_DESCWR_SHIFT 16
462 +#define DWC3_GSBUSCFG0_SNP_MASK 0xffff0000
463 +#define DWC3_GSBUSCFG0_DATABIGEND (1 << 11)
464 +#define DWC3_GSBUSCFG0_DESCBIGEND (1 << 10)
465 +#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
466 +#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
467 +#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
468 +#define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */
469 +#define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */
470 +#define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */
471 +#define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */
472 +#define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */
473 +#define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
474 +
475 +/* Global SoC Bus Configuration Register 1 */
476 +#define DWC3_GSBUSCFG1_1KPAGEENA (1 << 12) /* 1K page boundary enable */
477 +#define DWC3_GSBUSCFG1_PTRANSLIMIT_MASK 0xf00
478 +
479 /* Global Debug Queue/FIFO Space Available Register */
480 #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
481 #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
482 @@ -180,7 +207,6 @@
483 #define DWC3_GCTL_CLK_PIPE (1)
484 #define DWC3_GCTL_CLK_PIPEHALF (2)
485 #define DWC3_GCTL_CLK_MASK (3)
486 -
487 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
488 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
489 #define DWC3_GCTL_PRTCAP_HOST 1
490 @@ -289,6 +315,10 @@
491 /* Global Frame Length Adjustment Register */
492 #define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7)
493 #define DWC3_GFLADJ_30MHZ_MASK 0x3f
494 +#define GFLADJ_30MHZ_REG_SEL (1 << 7)
495 +#define GFLADJ_30MHZ(n) ((n) & 0x3f)
496 +#define GFLADJ_30MHZ_DEFAULT 0x20
497 +
498
499 /* Global User Control Register 2 */
500 #define DWC3_GUCTL2_RST_ACTBITLATER (1 << 14)
501 @@ -753,6 +783,7 @@ struct dwc3_scratchpad_array {
502 * @regs: base address for our registers
503 * @regs_size: address space size
504 * @fladj: frame length adjustment
505 + * @incrx_type: INCR burst type adjustment
506 * @irq_gadget: peripheral controller's IRQ number
507 * @nr_scratch: number of scratch buffers
508 * @u1u2: only used on revisions <1.83a for workaround
509 @@ -847,6 +878,7 @@ struct dwc3 {
510 spinlock_t lock;
511
512 struct device *dev;
513 + struct device *sysdev;
514
515 struct platform_device *xhci;
516 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
517 @@ -872,6 +904,12 @@ struct dwc3 {
518 enum usb_phy_interface hsphy_mode;
519
520 u32 fladj;
521 + /*
522 + * For INCR burst type.
523 + * First field: for undefined length INCR burst type enable.
524 + * Second field: for INCRx burst type enable
525 + */
526 + u32 incrx_type[2];
527 u32 irq_gadget;
528 u32 nr_scratch;
529 u32 u1u2;
530 @@ -948,9 +986,12 @@ struct dwc3 {
531 unsigned ep0_bounced:1;
532 unsigned ep0_expect_in:1;
533 unsigned has_hibernation:1;
534 + unsigned sysdev_is_parent:1;
535 unsigned has_lpm_erratum:1;
536 unsigned is_utmi_l1_suspend:1;
537 unsigned is_fpga:1;
538 + unsigned needs_fifo_resize:1;
539 + unsigned configure_gfladj:1;
540 unsigned pending_events:1;
541 unsigned pullups_connected:1;
542 unsigned setup_packet_pending:1;
543 @@ -971,9 +1012,12 @@ struct dwc3 {
544 unsigned dis_rxdet_inp3_quirk:1;
545 unsigned dis_u2_freeclk_exists_quirk:1;
546 unsigned dis_del_phy_power_chg_quirk:1;
547 + unsigned dma_snooping_quirk:1;
548
549 unsigned tx_de_emphasis_quirk:1;
550 unsigned tx_de_emphasis:2;
551 +
552 + u16 imod_interval;
553 };
554
555 /* -------------------------------------------------------------------------- */
556 --- a/drivers/usb/dwc3/host.c
557 +++ b/drivers/usb/dwc3/host.c
558 @@ -17,6 +17,8 @@
559
560 #include <linux/platform_device.h>
561
562 +#include <linux/of_device.h>
563 +
564 #include "core.h"
565
566 int dwc3_host_init(struct dwc3 *dwc)
567 @@ -73,12 +75,21 @@ int dwc3_host_init(struct dwc3 *dwc)
568 return -ENOMEM;
569 }
570
571 - dma_set_coherent_mask(&xhci->dev, dwc->dev->coherent_dma_mask);
572 + if (IS_ENABLED(CONFIG_OF) && dwc->dev->of_node)
573 + of_dma_configure(&xhci->dev, dwc->dev->of_node);
574 + else
575 + dma_set_coherent_mask(&xhci->dev, dwc->dev->coherent_dma_mask);
576
577 - xhci->dev.parent = dwc->dev;
578 + xhci->dev.parent = dwc->dev;
579 xhci->dev.dma_mask = dwc->dev->dma_mask;
580 xhci->dev.dma_parms = dwc->dev->dma_parms;
581
582 + /* set DMA operations */
583 + if (dwc->dev->of_node && of_dma_is_coherent(dwc->dev->of_node)) {
584 + xhci->dev.archdata.dma_ops = dwc->dev->archdata.dma_ops;
585 + dev_dbg(dwc->dev, "set dma_ops for usb\n");
586 + }
587 +
588 dwc->xhci = xhci;
589
590 ret = platform_device_add_resources(xhci, dwc->xhci_resources,
591 --- a/drivers/usb/gadget/udc/fsl_udc_core.c
592 +++ b/drivers/usb/gadget/udc/fsl_udc_core.c
593 @@ -198,7 +198,11 @@ __acquires(ep->udc->lock)
594
595 spin_unlock(&ep->udc->lock);
596
597 - usb_gadget_giveback_request(&ep->ep, &req->req);
598 + /* this complete() should a func implemented by gadget layer,
599 + * eg fsg->bulk_in_complete()
600 + */
601 + if (req->req.complete)
602 + usb_gadget_giveback_request(&ep->ep, &req->req);
603
604 spin_lock(&ep->udc->lock);
605 ep->stopped = stopped;
606 @@ -245,10 +249,10 @@ static int dr_controller_setup(struct fs
607 if (udc->pdata->have_sysif_regs) {
608 if (udc->pdata->controller_ver) {
609 /* controller version 1.6 or above */
610 - ctrl = __raw_readl(&usb_sys_regs->control);
611 + ctrl = ioread32be(&usb_sys_regs->control);
612 ctrl &= ~USB_CTRL_UTMI_PHY_EN;
613 ctrl |= USB_CTRL_USB_EN;
614 - __raw_writel(ctrl, &usb_sys_regs->control);
615 + iowrite32be(ctrl, &usb_sys_regs->control);
616 }
617 }
618 portctrl |= PORTSCX_PTS_ULPI;
619 @@ -257,13 +261,14 @@ static int dr_controller_setup(struct fs
620 portctrl |= PORTSCX_PTW_16BIT;
621 /* fall through */
622 case FSL_USB2_PHY_UTMI:
623 + case FSL_USB2_PHY_UTMI_DUAL:
624 if (udc->pdata->have_sysif_regs) {
625 if (udc->pdata->controller_ver) {
626 /* controller version 1.6 or above */
627 - ctrl = __raw_readl(&usb_sys_regs->control);
628 + ctrl = ioread32be(&usb_sys_regs->control);
629 ctrl |= (USB_CTRL_UTMI_PHY_EN |
630 USB_CTRL_USB_EN);
631 - __raw_writel(ctrl, &usb_sys_regs->control);
632 + iowrite32be(ctrl, &usb_sys_regs->control);
633 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI
634 PHY CLK to become stable - 10ms*/
635 }
636 @@ -329,22 +334,22 @@ static int dr_controller_setup(struct fs
637 /* Config control enable i/o output, cpu endian register */
638 #ifndef CONFIG_ARCH_MXC
639 if (udc->pdata->have_sysif_regs) {
640 - ctrl = __raw_readl(&usb_sys_regs->control);
641 + ctrl = ioread32be(&usb_sys_regs->control);
642 ctrl |= USB_CTRL_IOENB;
643 - __raw_writel(ctrl, &usb_sys_regs->control);
644 + iowrite32be(ctrl, &usb_sys_regs->control);
645 }
646 #endif
647
648 -#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
649 +#if !defined(CONFIG_NOT_COHERENT_CACHE)
650 /* Turn on cache snooping hardware, since some PowerPC platforms
651 * wholly rely on hardware to deal with cache coherent. */
652
653 if (udc->pdata->have_sysif_regs) {
654 /* Setup Snooping for all the 4GB space */
655 tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
656 - __raw_writel(tmp, &usb_sys_regs->snoop1);
657 + iowrite32be(tmp, &usb_sys_regs->snoop1);
658 tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
659 - __raw_writel(tmp, &usb_sys_regs->snoop2);
660 + iowrite32be(tmp, &usb_sys_regs->snoop2);
661 }
662 #endif
663
664 @@ -1057,7 +1062,7 @@ static int fsl_ep_fifo_status(struct usb
665 struct ep_queue_head *qh;
666
667 ep = container_of(_ep, struct fsl_ep, ep);
668 - if (!_ep || (!ep->ep.desc && ep_index(ep) != 0))
669 + if (!_ep || !ep->ep.desc || (ep_index(ep) == 0))
670 return -ENODEV;
671
672 udc = (struct fsl_udc *)ep->udc;
673 @@ -1599,14 +1604,13 @@ static int process_ep_req(struct fsl_udc
674 struct fsl_req *curr_req)
675 {
676 struct ep_td_struct *curr_td;
677 - int td_complete, actual, remaining_length, j, tmp;
678 + int actual, remaining_length, j, tmp;
679 int status = 0;
680 int errors = 0;
681 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
682 int direction = pipe % 2;
683
684 curr_td = curr_req->head;
685 - td_complete = 0;
686 actual = curr_req->req.length;
687
688 for (j = 0; j < curr_req->dtd_count; j++) {
689 @@ -1651,11 +1655,9 @@ static int process_ep_req(struct fsl_udc
690 status = -EPROTO;
691 break;
692 } else {
693 - td_complete++;
694 break;
695 }
696 } else {
697 - td_complete++;
698 VDBG("dTD transmitted successful");
699 }
700
701 @@ -1698,7 +1700,7 @@ static void dtd_complete_irq(struct fsl_
702 curr_ep = get_ep_by_pipe(udc, i);
703
704 /* If the ep is configured */
705 - if (curr_ep->name == NULL) {
706 + if (strncmp(curr_ep->name, "ep", 2)) {
707 WARNING("Invalid EP?");
708 continue;
709 }
710 @@ -2420,10 +2422,12 @@ static int fsl_udc_probe(struct platform
711 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
712 #endif
713
714 +#ifdef CONFIG_ARCH_MXC
715 /* Initialize USB clocks */
716 ret = fsl_udc_clk_init(pdev);
717 if (ret < 0)
718 goto err_iounmap_noclk;
719 +#endif
720
721 /* Read Device Controller Capability Parameters register */
722 dccparams = fsl_readl(&dr_regs->dccparams);
723 @@ -2463,9 +2467,11 @@ static int fsl_udc_probe(struct platform
724 dr_controller_setup(udc_controller);
725 }
726
727 +#ifdef CONFIG_ARCH_MXC
728 ret = fsl_udc_clk_finalize(pdev);
729 if (ret)
730 goto err_free_irq;
731 +#endif
732
733 /* Setup gadget structure */
734 udc_controller->gadget.ops = &fsl_gadget_ops;
735 @@ -2478,6 +2484,7 @@ static int fsl_udc_probe(struct platform
736 /* Setup gadget.dev and register with kernel */
737 dev_set_name(&udc_controller->gadget.dev, "gadget");
738 udc_controller->gadget.dev.of_node = pdev->dev.of_node;
739 + set_dma_ops(&udc_controller->gadget.dev, pdev->dev.archdata.dma_ops);
740
741 if (!IS_ERR_OR_NULL(udc_controller->transceiver))
742 udc_controller->gadget.is_otg = 1;
743 @@ -2529,7 +2536,9 @@ err_free_irq:
744 err_iounmap:
745 if (pdata->exit)
746 pdata->exit(pdev);
747 +#ifdef CONFIG_ARCH_MXC
748 fsl_udc_clk_release();
749 +#endif
750 err_iounmap_noclk:
751 iounmap(dr_regs);
752 err_release_mem_region:
753 @@ -2557,8 +2566,9 @@ static int fsl_udc_remove(struct platfor
754 udc_controller->done = &done;
755 usb_del_gadget_udc(&udc_controller->gadget);
756
757 +#ifdef CONFIG_ARCH_MXC
758 fsl_udc_clk_release();
759 -
760 +#endif
761 /* DR has been stopped in usb_gadget_unregister_driver() */
762 remove_proc_file();
763
764 @@ -2570,7 +2580,7 @@ static int fsl_udc_remove(struct platfor
765 dma_pool_destroy(udc_controller->td_pool);
766 free_irq(udc_controller->irq, udc_controller);
767 iounmap(dr_regs);
768 - if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
769 + if (res && (pdata->operating_mode == FSL_USB2_DR_DEVICE))
770 release_mem_region(res->start, resource_size(res));
771
772 /* free udc --wait for the release() finished */
773 --- a/drivers/usb/gadget/udc/fsl_usb2_udc.h
774 +++ b/drivers/usb/gadget/udc/fsl_usb2_udc.h
775 @@ -20,6 +20,10 @@
776 #define USB_MAX_CTRL_PAYLOAD 64
777 #define USB_DR_SYS_OFFSET 0x400
778
779 +#ifdef CONFIG_SOC_LS1021A
780 +#undef CONFIG_ARCH_MXC
781 +#endif
782 +
783 /* USB DR device mode registers (Little Endian) */
784 struct usb_dr_device {
785 /* Capability register */
786 @@ -597,18 +601,6 @@ struct platform_device;
787 int fsl_udc_clk_init(struct platform_device *pdev);
788 int fsl_udc_clk_finalize(struct platform_device *pdev);
789 void fsl_udc_clk_release(void);
790 -#else
791 -static inline int fsl_udc_clk_init(struct platform_device *pdev)
792 -{
793 - return 0;
794 -}
795 -static inline int fsl_udc_clk_finalize(struct platform_device *pdev)
796 -{
797 - return 0;
798 -}
799 -static inline void fsl_udc_clk_release(void)
800 -{
801 -}
802 #endif
803
804 #endif
805 --- a/drivers/usb/host/Kconfig
806 +++ b/drivers/usb/host/Kconfig
807 @@ -165,7 +165,7 @@ config XPS_USB_HCD_XILINX
808
809 config USB_EHCI_FSL
810 tristate "Support for Freescale PPC on-chip EHCI USB controller"
811 - depends on FSL_SOC
812 + depends on USB_EHCI_HCD
813 select USB_EHCI_ROOT_HUB_TT
814 ---help---
815 Variation of ARC USB block used in some Freescale chips.
816 --- a/drivers/usb/host/ehci-fsl.c
817 +++ b/drivers/usb/host/ehci-fsl.c
818 @@ -37,13 +37,141 @@
819 #include <linux/fsl_devices.h>
820 #include <linux/of_platform.h>
821
822 +#ifdef CONFIG_PPC
823 +#include <asm/fsl_pm.h>
824 +#include <linux/suspend.h>
825 +#endif
826 +
827 #include "ehci.h"
828 #include "ehci-fsl.h"
829
830 +#define FSL_USB_PHY_ADDR 0xffe214000
831 +
832 +struct ccsr_usb_port_ctrl {
833 + u32 ctrl;
834 + u32 drvvbuscfg;
835 + u32 pwrfltcfg;
836 + u32 sts;
837 + u8 res_14[0xc];
838 + u32 bistcfg;
839 + u32 biststs;
840 + u32 abistcfg;
841 + u32 abiststs;
842 + u8 res_30[0x10];
843 + u32 xcvrprg;
844 + u32 anaprg;
845 + u32 anadrv;
846 + u32 anasts;
847 +};
848 +
849 +struct ccsr_usb_phy {
850 + u32 id;
851 + struct ccsr_usb_port_ctrl port1;
852 + u8 res_50[0xc];
853 + u32 tvr;
854 + u32 pllprg[4];
855 + u8 res_70[0x4];
856 + u32 anaccfg;
857 + u32 dbg;
858 + u8 res_7c[0x4];
859 + struct ccsr_usb_port_ctrl port2;
860 + u8 res_dc[0x334];
861 +};
862 +
863 #define DRIVER_DESC "Freescale EHCI Host controller driver"
864 #define DRV_NAME "ehci-fsl"
865
866 static struct hc_driver __read_mostly fsl_ehci_hc_driver;
867 +struct ehci_fsl {
868 + /* store current hcd state for otg;
869 + * have_hcd is true when host drv al already part of otg framework,
870 + * otherwise false;
871 + * hcd_add is true when otg framework wants to add host
872 + * drv as part of otg;flase when it wants to remove it
873 + */
874 +unsigned have_hcd:1;
875 +unsigned hcd_add:1;
876 +};
877 +
878 +static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
879 +{
880 +struct ehci_hcd *ehci = hcd_to_ehci(hcd);
881 +
882 +return container_of(ehci, struct ehci_fsl, ehci);
883 +}
884 +
885 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
886 +static void do_change_hcd(struct work_struct *work)
887 +{
888 +struct ehci_hcd *ehci = container_of(work, struct ehci_hcd,
889 + change_hcd_work);
890 +struct usb_hcd *hcd = ehci_to_hcd(ehci);
891 +struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
892 +void __iomem *non_ehci = hcd->regs;
893 +int retval;
894 +
895 + if (ehci_fsl->hcd_add && !ehci_fsl->have_hcd) {
896 + writel(USBMODE_CM_HOST, non_ehci + FSL_SOC_USB_USBMODE);
897 + /* host, gadget and otg share same int line */
898 + retval = usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
899 + if (retval == 0)
900 + ehci_fsl->have_hcd = 1;
901 + } else if (!ehci_fsl->hcd_add && ehci_fsl->have_hcd) {
902 + usb_remove_hcd(hcd);
903 + ehci_fsl->have_hcd = 0;
904 + }
905 +}
906 +#endif
907 +
908 +struct ehci_fsl {
909 + struct ehci_hcd ehci;
910 +
911 +#ifdef CONFIG_PM
912 +struct ehci_regs saved_regs;
913 +struct ccsr_usb_phy saved_phy_regs;
914 +/* Saved USB PHY settings, need to restore after deep sleep. */
915 +u32 usb_ctrl;
916 +#endif
917 + /*
918 + * store current hcd state for otg;
919 + * have_hcd is true when host drv al already part of otg framework,
920 + * otherwise false;
921 + * hcd_add is true when otg framework wants to add host
922 + * drv as part of otg;flase when it wants to remove it
923 + */
924 +unsigned have_hcd:1;
925 +unsigned hcd_add:1;
926 +};
927 +
928 +static strut ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
929 +{
930 +struct ehci_hcd *ehci = hcd_to_ehci(hcd);
931 +
932 +return container_of(ehci, struct ehci_fsl, ehci);
933 +}
934 +
935 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
936 +static void do_change_hcd(struct work_struct *work)
937 +{
938 +struct ehci_hcd *ehci = container_of(work, struct ehci_hcd,
939 +change_hcd_work);
940 +struct usb_hcd *hcd = ehci_to_hcd(ehci);
941 +struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
942 +void __iomem *non_ehci = hcd->regs;
943 +int retval;
944 +
945 +if (ehci_fsl->hcd_add && !ehci_fsl->have_hcd) {
946 +writel(USBMODE_CM_HOST, non_ehci + FSL_SOC_USB_USBMODE);
947 +/* host, gadget and otg share same int line */
948 +retval = usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
949 +if (retval == 0)
950 +ehci_fsl->have_hcd = 1;
951 +} else if (!ehci_fsl->hcd_add && ehci_fsl->have_hcd) {
952 + usb_remove_hcd(hcd);
953 +ehci_fsl->have_hcd = 0;
954 +}
955 +}
956 +#endif
957
958 /* configure so an HC device and id are always provided */
959 /* always called with process context; sleeping is OK */
960 @@ -131,6 +259,12 @@ static int fsl_ehci_drv_probe(struct pla
961 clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
962 CONTROL_REGISTER_W1C_MASK, 0x4);
963
964 + /* Set USB_EN bit to select ULPI phy for USB controller version 2.5 */
965 + if (pdata->controller_ver == FSL_USB_VER_2_5 &&
966 + pdata->phy_mode == FSL_USB2_PHY_ULPI)
967 + iowrite32be(USB_CTRL_USB_EN, hcd->regs + FSL_SOC_USB_CTRL);
968 +
969 +
970 /*
971 * Enable UTMI phy and program PTS field in UTMI mode before asserting
972 * controller reset for USB Controller version 2.5
973 @@ -143,16 +277,20 @@ static int fsl_ehci_drv_probe(struct pla
974
975 /* Don't need to set host mode here. It will be done by tdi_reset() */
976
977 - retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
978 + retval = usb_add_hcd(hcd, irq, IRQF_SHARED | IRQF_NO_SUSPEND);
979 if (retval != 0)
980 goto err2;
981 device_wakeup_enable(hcd->self.controller);
982
983 -#ifdef CONFIG_USB_OTG
984 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
985 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
986 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
987 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
988
989 hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2);
990 +
991 + INIT_WORK(&ehci->change_hcd_work, do_change_hcd);
992 +
993 dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n",
994 hcd, ehci, hcd->usb_phy);
995
996 @@ -168,6 +306,11 @@ static int fsl_ehci_drv_probe(struct pla
997 retval = -ENODEV;
998 goto err2;
999 }
1000 +
1001 + ehci_fsl->have_hcd = 1;
1002 + } else {
1003 + dev_err(&pdev->dev, "wrong operating mode\n");
1004 + return -ENODEV;
1005 }
1006 #endif
1007 return retval;
1008 @@ -181,6 +324,18 @@ static int fsl_ehci_drv_probe(struct pla
1009 return retval;
1010 }
1011
1012 +static bool usb_phy_clk_valid(struct usb_hcd *hcd,
1013 + enum fsl_usb2_phy_modes phy_mode)
1014 +{
1015 + void __iomem *non_ehci = hcd->regs;
1016 + bool ret = true;
1017 +
1018 + if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID))
1019 + ret = false;
1020 +
1021 + return ret;
1022 +}
1023 +
1024 static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
1025 enum fsl_usb2_phy_modes phy_mode,
1026 unsigned int port_offset)
1027 @@ -219,6 +374,21 @@ static int ehci_fsl_setup_phy(struct usb
1028 /* fall through */
1029 case FSL_USB2_PHY_UTMI:
1030 case FSL_USB2_PHY_UTMI_DUAL:
1031 + if (pdata->has_fsl_erratum_a006918) {
1032 + pr_warn("fsl-ehci: USB PHY clock invalid\n");
1033 + return -EINVAL;
1034 + }
1035 +
1036 + /* PHY_CLK_VALID bit is de-featured from all controller
1037 + * versions below 2.4 and is to be checked only for
1038 + * internal UTMI phy
1039 + */
1040 + if (pdata->controller_ver > FSL_USB_VER_2_4 &&
1041 + pdata->have_sysif_regs && !usb_phy_clk_valid(hcd)) {
1042 + pr_err("fsl-ehci: USB PHY clock invalid\n");
1043 + return -EINVAL;
1044 + }
1045 +
1046 if (pdata->have_sysif_regs && pdata->controller_ver) {
1047 /* controller version 1.6 or above */
1048 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
1049 @@ -292,14 +462,9 @@ static int ehci_fsl_usb_setup(struct ehc
1050 return -EINVAL;
1051
1052 if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
1053 - unsigned int chip, rev, svr;
1054 -
1055 - svr = mfspr(SPRN_SVR);
1056 - chip = svr >> 16;
1057 - rev = (svr >> 4) & 0xf;
1058
1059 /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
1060 - if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
1061 + if (pdata->has_fsl_erratum_14 == 1)
1062 ehci->has_fsl_port_bug = 1;
1063
1064 if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
1065 @@ -379,16 +544,57 @@ static int ehci_fsl_setup(struct usb_hcd
1066 return retval;
1067 }
1068
1069 -struct ehci_fsl {
1070 - struct ehci_hcd ehci;
1071
1072 #ifdef CONFIG_PM
1073 - /* Saved USB PHY settings, need to restore after deep sleep. */
1074 - u32 usb_ctrl;
1075 -#endif
1076 -};
1077 +void __iomem *phy_reg;
1078
1079 -#ifdef CONFIG_PM
1080 +#ifdef CONFIG_PPC
1081 +/* save usb registers */
1082 +static int ehci_fsl_save_context(struct usb_hcd *hcd)
1083 +{
1084 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1085 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1086 + void __iomem *non_ehci = hcd->regs;
1087 + struct device *dev = hcd->self.controller;
1088 + struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
1089 +
1090 + if (pdata->phy_mode == FSL_USB2_PHY_UTMI_DUAL) {
1091 + phy_reg = ioremap(FSL_USB_PHY_ADDR,
1092 + sizeof(struct ccsr_usb_phy));
1093 + _memcpy_fromio((void *)&ehci_fsl->saved_phy_regs, phy_reg,
1094 + sizeof(struct ccsr_usb_phy));
1095 + }
1096 +
1097 + _memcpy_fromio((void *)&ehci_fsl->saved_regs, ehci->regs,
1098 + sizeof(struct ehci_regs));
1099 + ehci_fsl->usb_ctrl = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
1100 +
1101 + return 0;
1102 +}
1103 +
1104 +/*Restore usb registers */
1105 +static int ehci_fsl_restore_context(struct usb_hcd *hcd)
1106 +{
1107 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1108 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1109 + void __iomem *non_ehci = hcd->regs;
1110 + struct device *dev = hcd->self.controller;
1111 + struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
1112 +
1113 + if (pdata->phy_mode == FSL_USB2_PHY_UTMI_DUAL) {
1114 + if (phy_reg)
1115 + _memcpy_toio(phy_reg,
1116 + (void *)&ehci_fsl->saved_phy_regs,
1117 + sizeof(struct ccsr_usb_phy));
1118 + }
1119 +
1120 + _memcpy_toio(ehci->regs, (void *)&ehci_fsl->saved_regs,
1121 + sizeof(struct ehci_regs));
1122 + iowrite32be(ehci_fsl->usb_ctrl, non_ehci + FSL_SOC_USB_CTRL);
1123 +
1124 + return 0;
1125 +}
1126 +#endif
1127
1128 #ifdef CONFIG_PPC_MPC512x
1129 static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
1130 @@ -535,26 +741,43 @@ static inline int ehci_fsl_mpc512x_drv_r
1131 }
1132 #endif /* CONFIG_PPC_MPC512x */
1133
1134 -static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
1135 -{
1136 - struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1137 -
1138 - return container_of(ehci, struct ehci_fsl, ehci);
1139 -}
1140 -
1141 static int ehci_fsl_drv_suspend(struct device *dev)
1142 {
1143 struct usb_hcd *hcd = dev_get_drvdata(dev);
1144 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1145 void __iomem *non_ehci = hcd->regs;
1146 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1147 + struct usb_bus host = hcd->self;
1148 +#endif
1149 +
1150 +#ifdef CONFIG_PPC
1151 +suspend_state_t pm_state;
1152 +pm_state = pm_suspend_state();
1153 +
1154 +if (pm_state == PM_SUSPEND_MEM)
1155 + ehci_fsl_save_context(hcd);
1156 +#endif
1157
1158 if (of_device_is_compatible(dev->parent->of_node,
1159 "fsl,mpc5121-usb2-dr")) {
1160 return ehci_fsl_mpc512x_drv_suspend(dev);
1161 }
1162
1163 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1164 + if (host.is_otg) {
1165 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1166 +
1167 + /* remove hcd */
1168 + ehci_fsl->hcd_add = 0;
1169 + schedule_work(&ehci->change_hcd_work);
1170 + host.is_otg = 0;
1171 + return 0;
1172 + }
1173 +#endif
1174 +
1175 ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
1176 device_may_wakeup(dev));
1177 +
1178 if (!fsl_deep_sleep())
1179 return 0;
1180
1181 @@ -568,12 +791,34 @@ static int ehci_fsl_drv_resume(struct de
1182 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1183 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1184 void __iomem *non_ehci = hcd->regs;
1185 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1186 + struct usb_bus host = hcd->self;
1187 +#endif
1188 +
1189 +#ifdef CONFIG_PPC
1190 +suspend_state_t pm_state;
1191 +pm_state = pm_suspend_state();
1192 +
1193 +if (pm_state == PM_SUSPEND_MEM)
1194 + ehci_fsl_restore_context(hcd);
1195 +#endif
1196
1197 if (of_device_is_compatible(dev->parent->of_node,
1198 "fsl,mpc5121-usb2-dr")) {
1199 return ehci_fsl_mpc512x_drv_resume(dev);
1200 }
1201
1202 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1203 + if (host.is_otg) {
1204 + /* add hcd */
1205 + ehci_fsl->hcd_add = 1;
1206 + schedule_work(&ehci->change_hcd_work);
1207 + usb_hcd_resume_root_hub(hcd);
1208 + host.is_otg = 0;
1209 + return 0;
1210 + }
1211 +#endif
1212 +
1213 ehci_prepare_ports_for_controller_resume(ehci);
1214 if (!fsl_deep_sleep())
1215 return 0;
1216 --- a/drivers/usb/host/ehci-fsl.h
1217 +++ b/drivers/usb/host/ehci-fsl.h
1218 @@ -63,4 +63,7 @@
1219 #define UTMI_PHY_EN (1<<9)
1220 #define ULPI_PHY_CLK_SEL (1<<10)
1221 #define PHY_CLK_VALID (1<<17)
1222 +
1223 +/* Retry count for checking UTMI PHY CLK validity */
1224 +#define UTMI_PHY_CLK_VALID_CHK_RETRY 5
1225 #endif /* _EHCI_FSL_H */
1226 --- a/drivers/usb/host/ehci-hub.c
1227 +++ b/drivers/usb/host/ehci-hub.c
1228 @@ -305,6 +305,8 @@ static int ehci_bus_suspend (struct usb_
1229 USB_PORT_STAT_HIGH_SPEED)
1230 fs_idle_delay = true;
1231 ehci_writel(ehci, t2, reg);
1232 + if (ehci_has_fsl_susp_errata(ehci))
1233 + usleep_range(10000, 20000);
1234 changed = 1;
1235 }
1236 }
1237 --- a/drivers/usb/host/ehci.h
1238 +++ b/drivers/usb/host/ehci.h
1239 @@ -180,6 +180,9 @@ struct ehci_hcd { /* one per controlle
1240 unsigned periodic_count; /* periodic activity count */
1241 unsigned uframe_periodic_max; /* max periodic time per uframe */
1242
1243 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1244 + struct work_struct change_hcd_work;
1245 +#endif
1246
1247 /* list of itds & sitds completed while now_frame was still active */
1248 struct list_head cached_itd_list;
1249 @@ -706,8 +709,10 @@ ehci_port_speed(struct ehci_hcd *ehci, u
1250 * incoming packets get corrupted in HS mode
1251 */
1252 #define ehci_has_fsl_hs_errata(e) ((e)->has_fsl_hs_errata)
1253 +#define ehci_has_fsl_susp_errata(e) ((e)->has_fsl_susp_errata)
1254 #else
1255 #define ehci_has_fsl_hs_errata(e) (0)
1256 +#define ehci_has_fsl_susp_errata(e) (0)
1257 #endif
1258
1259 /*
1260 --- a/drivers/usb/host/fsl-mph-dr-of.c
1261 +++ b/drivers/usb/host/fsl-mph-dr-of.c
1262 @@ -226,6 +226,18 @@ static int fsl_usb2_mph_dr_of_probe(stru
1263 of_property_read_bool(np, "fsl,usb-erratum-a007792");
1264 pdata->has_fsl_erratum_a005275 =
1265 of_property_read_bool(np, "fsl,usb-erratum-a005275");
1266 + pdata->has_fsl_erratum_a005697 =
1267 + of_property_read_bool(np, "fsl,usb_erratum-a005697");
1268 + if (of_get_property(np, "fsl,erratum_a006918", NULL))
1269 + pdata->has_fsl_erratum_a006918 = 1;
1270 + else
1271 + pdata->has_fsl_erratum_a006918 = 0;
1272 +
1273 + if (of_get_property(np, "fsl,usb_erratum_14", NULL))
1274 + pdata->has_fsl_erratum_14 = 1;
1275 + else
1276 + pdata->has_fsl_erratum_14 = 0;
1277 +
1278
1279 /*
1280 * Determine whether phy_clk_valid needs to be checked
1281 --- a/drivers/usb/phy/phy-fsl-usb.c
1282 +++ b/drivers/usb/phy/phy-fsl-usb.c
1283 @@ -1,5 +1,5 @@
1284 /*
1285 - * Copyright (C) 2007,2008 Freescale semiconductor, Inc.
1286 + * Copyright 2007,2008 Freescale Semiconductor, Inc.
1287 *
1288 * Author: Li Yang <LeoLi@freescale.com>
1289 * Jerry Huang <Chang-Ming.Huang@freescale.com>
1290 @@ -463,6 +463,7 @@ void otg_reset_controller(void)
1291 int fsl_otg_start_host(struct otg_fsm *fsm, int on)
1292 {
1293 struct usb_otg *otg = fsm->otg;
1294 + struct usb_bus *host = otg->host;
1295 struct device *dev;
1296 struct fsl_otg *otg_dev =
1297 container_of(otg->usb_phy, struct fsl_otg, phy);
1298 @@ -486,6 +487,7 @@ int fsl_otg_start_host(struct otg_fsm *f
1299 otg_reset_controller();
1300 VDBG("host on......\n");
1301 if (dev->driver->pm && dev->driver->pm->resume) {
1302 + host->is_otg = 1;
1303 retval = dev->driver->pm->resume(dev);
1304 if (fsm->id) {
1305 /* default-b */
1306 @@ -510,8 +512,11 @@ int fsl_otg_start_host(struct otg_fsm *f
1307 else {
1308 VDBG("host off......\n");
1309 if (dev && dev->driver) {
1310 - if (dev->driver->pm && dev->driver->pm->suspend)
1311 + if (dev->driver->pm &&
1312 + dev->driver->pm->suspend) {
1313 + host->is_otg = 1;
1314 retval = dev->driver->pm->suspend(dev);
1315 + }
1316 if (fsm->id)
1317 /* default-b */
1318 fsl_otg_drv_vbus(fsm, 0);
1319 @@ -539,8 +544,17 @@ int fsl_otg_start_gadget(struct otg_fsm
1320 dev = otg->gadget->dev.parent;
1321
1322 if (on) {
1323 - if (dev->driver->resume)
1324 + /* Delay gadget resume to synchronize between host and gadget
1325 + * drivers. Upon role-reversal host drv is shutdown by kernel
1326 + * worker thread. By the time host drv shuts down, controller
1327 + * gets programmed for gadget role. Shutting host drv after
1328 + * this results in controller getting reset, and it stops
1329 + * responding to otg events
1330 + */
1331 + if (dev->driver->resume) {
1332 + msleep(1000);
1333 dev->driver->resume(dev);
1334 + }
1335 } else {
1336 if (dev->driver->suspend)
1337 dev->driver->suspend(dev, otg_suspend_state);
1338 @@ -672,6 +686,10 @@ static void fsl_otg_event(struct work_st
1339 fsl_otg_start_host(fsm, 0);
1340 otg_drv_vbus(fsm, 0);
1341 fsl_otg_start_gadget(fsm, 1);
1342 + } else {
1343 + fsl_otg_start_gadget(fsm, 0);
1344 + otg_drv_vbus(fsm, 1);
1345 + fsl_otg_start_host(fsm, 1);
1346 }
1347 }
1348
1349 @@ -724,6 +742,7 @@ irqreturn_t fsl_otg_isr(int irq, void *d
1350 {
1351 struct otg_fsm *fsm = &((struct fsl_otg *)dev_id)->fsm;
1352 struct usb_otg *otg = ((struct fsl_otg *)dev_id)->phy.otg;
1353 + struct fsl_otg *otg_dev = dev_id;
1354 u32 otg_int_src, otg_sc;
1355
1356 otg_sc = fsl_readl(&usb_dr_regs->otgsc);
1357 @@ -753,18 +772,8 @@ irqreturn_t fsl_otg_isr(int irq, void *d
1358 otg->gadget->is_a_peripheral = !fsm->id;
1359 VDBG("ID int (ID is %d)\n", fsm->id);
1360
1361 - if (fsm->id) { /* switch to gadget */
1362 - schedule_delayed_work(
1363 - &((struct fsl_otg *)dev_id)->otg_event,
1364 - 100);
1365 - } else { /* switch to host */
1366 - cancel_delayed_work(&
1367 - ((struct fsl_otg *)dev_id)->
1368 - otg_event);
1369 - fsl_otg_start_gadget(fsm, 0);
1370 - otg_drv_vbus(fsm, 1);
1371 - fsl_otg_start_host(fsm, 1);
1372 - }
1373 + schedule_delayed_work(&otg_dev->otg_event, 100);
1374 +
1375 return IRQ_HANDLED;
1376 }
1377 }
1378 @@ -923,12 +932,32 @@ int usb_otg_start(struct platform_device
1379 temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW);
1380 switch (pdata->phy_mode) {
1381 case FSL_USB2_PHY_ULPI:
1382 + if (pdata->controller_ver) {
1383 + /* controller version 1.6 or above */
1384 + setbits32(&p_otg->dr_mem_map->control,
1385 + USB_CTRL_ULPI_PHY_CLK_SEL);
1386 + /*
1387 + * Due to controller issue of PHY_CLK_VALID in ULPI
1388 + * mode, we set USB_CTRL_USB_EN before checking
1389 + * PHY_CLK_VALID, otherwise PHY_CLK_VALID doesn't work.
1390 + */
1391 + clrsetbits_be32(&p_otg->dr_mem_map->control,
1392 + USB_CTRL_UTMI_PHY_EN, USB_CTRL_IOENB);
1393 + }
1394 temp |= PORTSC_PTS_ULPI;
1395 break;
1396 case FSL_USB2_PHY_UTMI_WIDE:
1397 temp |= PORTSC_PTW_16BIT;
1398 /* fall through */
1399 case FSL_USB2_PHY_UTMI:
1400 + if (pdata->controller_ver) {
1401 + /* controller version 1.6 or above */
1402 + setbits32(&p_otg->dr_mem_map->control,
1403 + USB_CTRL_UTMI_PHY_EN);
1404 + /* Delay for UTMI PHY CLK to become stable - 10ms */
1405 + mdelay(FSL_UTMI_PHY_DLY);
1406 + }
1407 + setbits32(&p_otg->dr_mem_map->control, USB_CTRL_UTMI_PHY_EN);
1408 temp |= PORTSC_PTS_UTMI;
1409 /* fall through */
1410 default:
1411 --- a/drivers/usb/phy/phy-fsl-usb.h
1412 +++ b/drivers/usb/phy/phy-fsl-usb.h
1413 @@ -199,6 +199,14 @@
1414 /* control Register Bit Masks */
1415 #define USB_CTRL_IOENB (0x1<<2)
1416 #define USB_CTRL_ULPI_INT0EN (0x1<<0)
1417 +#define USB_CTRL_WU_INT_EN (0x1<<1)
1418 +#define USB_CTRL_LINE_STATE_FILTER__EN (0x1<<3)
1419 +#define USB_CTRL_KEEP_OTG_ON (0x1<<4)
1420 +#define USB_CTRL_OTG_PORT (0x1<<5)
1421 +#define USB_CTRL_PLL_RESET (0x1<<8)
1422 +#define USB_CTRL_UTMI_PHY_EN (0x1<<9)
1423 +#define USB_CTRL_ULPI_PHY_CLK_SEL (0x1<<10)
1424 +#define USB_CTRL_PHY_CLK_VALID (0x1<<17)
1425
1426 /* BCSR5 */
1427 #define BCSR5_INT_USB (0x02)
1428 --- a/include/linux/usb.h
1429 +++ b/include/linux/usb.h
1430 @@ -362,6 +362,7 @@ struct usb_bus {
1431 * for control transfers?
1432 */
1433 u8 otg_port; /* 0, or number of OTG/HNP port */
1434 + unsigned is_otg:1; /* true when host is also otg */
1435 unsigned is_b_host:1; /* true during some HNP roleswitches */
1436 unsigned b_hnp_enable:1; /* OTG: did A-Host enable HNP? */
1437 unsigned no_stop_on_short:1; /*
1438 --- a/include/linux/usb/of.h
1439 +++ b/include/linux/usb/of.h
1440 @@ -11,6 +11,8 @@
1441 #include <linux/usb/otg.h>
1442 #include <linux/usb/phy.h>
1443
1444 +enum usb_dr_mode of_usb_get_dr_mode(struct device_node *np);
1445 +
1446 #if IS_ENABLED(CONFIG_OF)
1447 enum usb_dr_mode of_usb_get_dr_mode_by_phy(struct device_node *np, int arg0);
1448 bool of_usb_host_tpl_support(struct device_node *np);
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