ipq806x: add support for GL.iNet GL-B1300
[openwrt/staging/mkresin.git] / target / linux / mediatek / files / arch / arm / boot / dts / mt7623n-bananapi-bpi-r2.dts
1 /*
2 * Copyright 2017 Sean Wang <sean.wang@mediatek.com>
3 *
4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 */
6
7 /dts-v1/;
8 #include <dt-bindings/input/input.h>
9 #include "_mt7623.dtsi"
10 #include "mt6323.dtsi"
11
12 / {
13 model = "Bananapi BPI-R2";
14 compatible = "bananapi,bpi-r2", "mediatek,mt7623";
15
16 aliases {
17 serial2 = &uart2;
18 };
19
20 chosen {
21 stdout-path = "serial2:115200n8";
22 };
23
24 cpus {
25 cpu@0 {
26 proc-supply = <&mt6323_vproc_reg>;
27 };
28
29 cpu@1 {
30 proc-supply = <&mt6323_vproc_reg>;
31 };
32
33 cpu@2 {
34 proc-supply = <&mt6323_vproc_reg>;
35 };
36
37 cpu@3 {
38 proc-supply = <&mt6323_vproc_reg>;
39 };
40 };
41
42 gpio_keys {
43 compatible = "gpio-keys";
44 pinctrl-names = "default";
45 pinctrl-0 = <&key_pins_a>;
46
47 factory {
48 label = "factory";
49 linux,code = <BTN_0>;
50 gpios = <&pio 256 GPIO_ACTIVE_LOW>;
51 };
52
53 wps {
54 label = "wps";
55 linux,code = <KEY_WPS_BUTTON>;
56 gpios = <&pio 257 GPIO_ACTIVE_HIGH>;
57 };
58 };
59
60 leds {
61 compatible = "gpio-leds";
62 pinctrl-names = "default";
63 pinctrl-0 = <&led_pins_a>;
64
65 red {
66 label = "bpi-r2:pio:red";
67 gpios = <&pio 239 GPIO_ACTIVE_HIGH>;
68 default-state = "off";
69 };
70
71 green {
72 label = "bpi-r2:pio:green";
73 gpios = <&pio 240 GPIO_ACTIVE_HIGH>;
74 default-state = "off";
75 };
76
77 blue {
78 label = "bpi-r2:pio:blue";
79 gpios = <&pio 241 GPIO_ACTIVE_HIGH>;
80 default-state = "off";
81 };
82 };
83
84 memory@80000000 {
85 reg = <0 0x80000000 0 0x40000000>;
86 };
87 };
88
89 &cir {
90 pinctrl-names = "default";
91 pinctrl-0 = <&cir_pins_a>;
92 status = "okay";
93 };
94
95 &crypto {
96 status = "okay";
97 };
98
99 &eth {
100 status = "okay";
101 gmac0: mac@0 {
102 compatible = "mediatek,eth-mac";
103 reg = <0>;
104 phy-mode = "trgmii";
105 fixed-link {
106 speed = <1000>;
107 full-duplex;
108 pause;
109 };
110 };
111
112 mdio: mdio-bus {
113 #address-cells = <1>;
114 #size-cells = <0>;
115 switch@0 {
116 compatible = "mediatek,mt7530";
117 #address-cells = <1>;
118 #size-cells = <0>;
119 reg = <0>;
120
121 pinctrl-names = "default";
122 reset-gpios = <&pio 33 0>;
123 core-supply = <&mt6323_vpa_reg>;
124 io-supply = <&mt6323_vemc3v3_reg>;
125
126 ports {
127 #address-cells = <1>;
128 #size-cells = <0>;
129 reg = <0>;
130 port@0 {
131 reg = <0>;
132 label = "wan";
133 };
134
135 port@1 {
136 reg = <1>;
137 label = "lan0";
138 };
139
140 port@2 {
141 reg = <2>;
142 label = "lan1";
143 };
144
145 port@3 {
146 reg = <3>;
147 label = "lan2";
148 };
149
150 port@4 {
151 reg = <4>;
152 label = "lan3";
153 };
154
155 port@6 {
156 reg = <6>;
157 label = "cpu";
158 ethernet = <&gmac0>;
159 phy-mode = "trgmii";
160 fixed-link {
161 speed = <1000>;
162 full-duplex;
163 };
164 };
165 };
166 };
167 };
168 };
169
170 &i2c0 {
171 pinctrl-names = "default";
172 pinctrl-0 = <&i2c0_pins_a>;
173 status = "okay";
174 };
175
176 &i2c1 {
177 pinctrl-names = "default";
178 pinctrl-0 = <&i2c1_pins_a>;
179 status = "okay";
180 };
181
182 &pio {
183 cir_pins_a:cir@0 {
184 pins_cir {
185 pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
186 bias-disable;
187 };
188 };
189
190 i2c0_pins_a: i2c@0 {
191 pins_i2c0 {
192 pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
193 <MT7623_PIN_76_SCL0_FUNC_SCL0>;
194 bias-disable;
195 };
196 };
197
198 i2c1_pins_a: i2c@1 {
199 pin_i2c1 {
200 pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
201 <MT7623_PIN_58_SCL1_FUNC_SCL1>;
202 bias-disable;
203 };
204 };
205
206 i2s0_pins_a: i2s@0 {
207 pin_i2s0 {
208 pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
209 <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
210 <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
211 <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
212 <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
213 drive-strength = <MTK_DRIVE_12mA>;
214 bias-pull-down;
215 };
216 };
217
218 i2s1_pins_a: i2s@1 {
219 pin_i2s1 {
220 pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
221 <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
222 <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
223 <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
224 <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
225 drive-strength = <MTK_DRIVE_12mA>;
226 bias-pull-down;
227 };
228 };
229
230 key_pins_a: keys@0 {
231 pins_keys {
232 pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
233 <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ;
234 input-enable;
235 };
236 };
237
238 led_pins_a: leds@0 {
239 pins_leds {
240 pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>,
241 <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>,
242 <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>;
243 };
244 };
245
246 mmc0_pins_default: mmc0default {
247 pins_cmd_dat {
248 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
249 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
250 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
251 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
252 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
253 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
254 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
255 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
256 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
257 input-enable;
258 bias-pull-up;
259 };
260
261 pins_clk {
262 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
263 bias-pull-down;
264 };
265
266 pins_rst {
267 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
268 bias-pull-up;
269 };
270 };
271
272 mmc0_pins_uhs: mmc0 {
273 pins_cmd_dat {
274 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
275 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
276 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
277 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
278 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
279 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
280 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
281 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
282 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
283 input-enable;
284 drive-strength = <MTK_DRIVE_2mA>;
285 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
286 };
287
288 pins_clk {
289 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
290 drive-strength = <MTK_DRIVE_2mA>;
291 bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
292 };
293
294 pins_rst {
295 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
296 bias-pull-up;
297 };
298 };
299
300 mmc1_pins_default: mmc1default {
301 pins_cmd_dat {
302 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
303 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
304 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
305 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
306 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
307 input-enable;
308 drive-strength = <MTK_DRIVE_4mA>;
309 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
310 };
311
312 pins_clk {
313 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
314 bias-pull-down;
315 drive-strength = <MTK_DRIVE_4mA>;
316 };
317 };
318
319 mmc1_pins_uhs: mmc1 {
320 pins_cmd_dat {
321 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
322 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
323 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
324 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
325 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
326 input-enable;
327 drive-strength = <MTK_DRIVE_4mA>;
328 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
329 };
330
331 pins_clk {
332 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
333 drive-strength = <MTK_DRIVE_4mA>;
334 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
335 };
336 };
337
338 spi0_pins_a: spi@0 {
339 pins_spi {
340 pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
341 <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
342 <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
343 <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
344 bias-disable;
345 };
346 };
347
348 pwm_pins_a: pwm@0 {
349 pins_pwm {
350 pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
351 <MT7623_PIN_204_PWM1_FUNC_PWM1>,
352 <MT7623_PIN_205_PWM2_FUNC_PWM2>,
353 <MT7623_PIN_206_PWM3_FUNC_PWM3>,
354 <MT7623_PIN_207_PWM4_FUNC_PWM4>;
355 };
356 };
357
358 uart0_pins_a: uart@0 {
359 pins_dat {
360 pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
361 <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
362 };
363 };
364
365 uart1_pins_a: uart@1 {
366 pins_dat {
367 pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
368 <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
369 };
370 };
371 };
372
373 &pwm {
374 pinctrl-names = "default";
375 pinctrl-0 = <&pwm_pins_a>;
376 status = "okay";
377 };
378
379 &pwrap {
380 mt6323 {
381 mt6323led: led {
382 compatible = "mediatek,mt6323-led";
383 #address-cells = <1>;
384 #size-cells = <0>;
385
386 led@0 {
387 reg = <0>;
388 label = "bpi-r2:isink:green";
389 default-state = "off";
390 };
391 led@1 {
392 reg = <1>;
393 label = "bpi-r2:isink:red";
394 default-state = "off";
395 };
396 led@2 {
397 reg = <2>;
398 label = "bpi-r2:isink:blue";
399 default-state = "off";
400 };
401 };
402 };
403 };
404
405 &spi0 {
406 pinctrl-names = "default";
407 pinctrl-0 = <&spi0_pins_a>;
408 status = "okay";
409 };
410
411 &uart0 {
412 pinctrl-names = "default";
413 pinctrl-0 = <&uart0_pins_a>;
414 status = "disabled";
415 };
416
417 &u3phy1 {
418 status = "okay";
419 };
420
421 &u3phy2 {
422 status = "okay";
423 };
424
425 &uart1 {
426 pinctrl-names = "default";
427 pinctrl-0 = <&uart1_pins_a>;
428 status = "disabled";
429 };
430
431 &uart2 {
432 status = "okay";
433 };
434
435 &usb1 {
436 vusb33-supply = <&mt6323_vusb_reg>;
437 status = "okay";
438 };
439
440 &usb2 {
441 vusb33-supply = <&mt6323_vusb_reg>;
442 status = "okay";
443 };