target/linux/ramips/files/arch/mips/ralink/rt305x/rt305x.c

   1 /*
   2  * Ralink RT305x SoC specific setup
   3  *
   4  * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  * Parts of this file are based on Ralink's 2.6.21 BSP
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License version 2 as published
  11  * by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17
  18 #include <asm/mipsregs.h>
  19
  20 #include <asm/mach-ralink/common.h>
  21 #include <asm/mach-ralink/ramips_gpio.h>
  22 #include <asm/mach-ralink/rt305x.h>
  23 #include <asm/mach-ralink/rt305x_regs.h>
  24
  25 void __iomem * rt305x_sysc_base;
  26 void __iomem * rt305x_memc_base;
  27 enum rt305x_soc_type rt305x_soc;
  28
  29 void __init ramips_soc_prom_init(void)
  30 {
  31         void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
  32         const char *name = "unknown";
  33         u32 n0;
  34         u32 n1;
  35         u32 id;
  36
  37         n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
  38         n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
  39
  40         if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) {
  41                 unsigned long icache_sets;
  42
  43                 icache_sets = (read_c0_config1() >> 22) & 7;
  44                 if (icache_sets == 1) {
  45                         rt305x_soc = RT305X_SOC_RT3050;
  46                         name = "RT3050";
  47                 } else {
  48                         rt305x_soc = RT305X_SOC_RT3052;
  49                         name = "RT3052";
  50                 }
  51         } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
  52                 rt305x_soc = RT305X_SOC_RT3350;
  53                 name = "RT3350";
  54         } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
  55                 rt305x_soc = RT305X_SOC_RT3352;
  56                 name = "RT3352";
  57         } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
  58                 rt305x_soc = RT305X_SOC_RT5350;
  59                 name = "RT5350";
  60         } else {
  61                 panic("rt305x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
  62         }
  63
  64         id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
  65
  66         snprintf(ramips_sys_type, RAMIPS_SYS_TYPE_LEN,
  67                 "Ralink %s id:%u rev:%u",
  68                 name,
  69                 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
  70                 (id & CHIP_ID_REV_MASK));
  71
  72         ramips_mem_base = RT305X_SDRAM_BASE;
  73
  74         if (soc_is_rt305x() || soc_is_rt3350() || soc_is_rt5350()) {
  75                 ramips_mem_size_min = RT305X_MEM_SIZE_MIN;
  76                 ramips_mem_size_max = RT305X_MEM_SIZE_MAX;
  77         } else if (soc_is_rt3352()) {
  78                 ramips_mem_size_min = RT3352_MEM_SIZE_MIN;
  79                 ramips_mem_size_max = RT3352_MEM_SIZE_MAX;
  80         } else {
  81                 BUG();
  82         }
  83 }
  84
  85 static struct ramips_gpio_chip rt305x_gpio_chips[] = {
  86         {
  87                 .chip = {
  88                         .label  = "RT305X-GPIO0",
  89                         .base   = 0,
  90                         .ngpio  = 24,
  91                 },
  92                 .regs = {
  93                         [RAMIPS_GPIO_REG_INT]   = 0x00,
  94                         [RAMIPS_GPIO_REG_EDGE]  = 0x04,
  95                         [RAMIPS_GPIO_REG_RENA]  = 0x08,
  96                         [RAMIPS_GPIO_REG_FENA]  = 0x0c,
  97                         [RAMIPS_GPIO_REG_DATA]  = 0x20,
  98                         [RAMIPS_GPIO_REG_DIR]   = 0x24,
  99                         [RAMIPS_GPIO_REG_POL]   = 0x28,
 100                         [RAMIPS_GPIO_REG_SET]   = 0x2c,
 101                         [RAMIPS_GPIO_REG_RESET] = 0x30,
 102                         [RAMIPS_GPIO_REG_TOGGLE] = 0x34,
 103                 },
 104                 .map_base = RT305X_PIO_BASE,
 105                 .map_size = RT305X_PIO_SIZE,
 106         },
 107         {
 108                 .chip = {
 109                         .label  = "RT305X-GPIO1",
 110                         .base   = 24,
 111                         .ngpio  = 16,
 112                 },
 113                 .regs = {
 114                         [RAMIPS_GPIO_REG_INT]   = 0x38,
 115                         [RAMIPS_GPIO_REG_EDGE]  = 0x3c,
 116                         [RAMIPS_GPIO_REG_RENA]  = 0x40,
 117                         [RAMIPS_GPIO_REG_FENA]  = 0x44,
 118                         [RAMIPS_GPIO_REG_DATA]  = 0x48,
 119                         [RAMIPS_GPIO_REG_DIR]   = 0x4c,
 120                         [RAMIPS_GPIO_REG_POL]   = 0x50,
 121                         [RAMIPS_GPIO_REG_SET]   = 0x54,
 122                         [RAMIPS_GPIO_REG_RESET] = 0x58,
 123                         [RAMIPS_GPIO_REG_TOGGLE] = 0x5c,
 124                 },
 125                 .map_base = RT305X_PIO_BASE,
 126                 .map_size = RT305X_PIO_SIZE,
 127         },
 128         {
 129                 .chip = {
 130                         .label  = "RT305X-GPIO2",
 131                         .base   = 40,
 132                         .ngpio  = 12,
 133                 },
 134                 .regs = {
 135                         [RAMIPS_GPIO_REG_INT]   = 0x60,
 136                         [RAMIPS_GPIO_REG_EDGE]  = 0x64,
 137                         [RAMIPS_GPIO_REG_RENA]  = 0x68,
 138                         [RAMIPS_GPIO_REG_FENA]  = 0x6c,
 139                         [RAMIPS_GPIO_REG_DATA]  = 0x70,
 140                         [RAMIPS_GPIO_REG_DIR]   = 0x74,
 141                         [RAMIPS_GPIO_REG_POL]   = 0x78,
 142                         [RAMIPS_GPIO_REG_SET]   = 0x7c,
 143                         [RAMIPS_GPIO_REG_RESET] = 0x80,
 144                         [RAMIPS_GPIO_REG_TOGGLE] = 0x84,
 145                 },
 146                 .map_base = RT305X_PIO_BASE,
 147                 .map_size = RT305X_PIO_SIZE,
 148         },
 149 };
 150
 151 static struct ramips_gpio_data rt305x_gpio_data = {
 152         .chips = rt305x_gpio_chips,
 153         .num_chips = ARRAY_SIZE(rt305x_gpio_chips),
 154 };
 155
 156 static void rt305x_gpio_reserve(int first, int last)
 157 {
 158         for (; first <= last; first++)
 159                 gpio_request(first, "reserved");
 160 }
 161
 162 void __init rt305x_gpio_init(u32 mode)
 163 {
 164         u32 t;
 165
 166         rt305x_sysc_wr(mode, SYSC_REG_GPIO_MODE);
 167
 168         ramips_gpio_init(&rt305x_gpio_data);
 169         if ((mode & RT305X_GPIO_MODE_I2C) == 0)
 170                 rt305x_gpio_reserve(RT305X_GPIO_I2C_SD, RT305X_GPIO_I2C_SCLK);
 171
 172         if ((mode & RT305X_GPIO_MODE_SPI) == 0)
 173                 rt305x_gpio_reserve(RT305X_GPIO_SPI_EN, RT305X_GPIO_SPI_CLK);
 174
 175         t = mode >> RT305X_GPIO_MODE_UART0_SHIFT;
 176         t &= RT305X_GPIO_MODE_UART0_MASK;
 177         switch (t) {
 178         case RT305X_GPIO_MODE_UARTF:
 179         case RT305X_GPIO_MODE_PCM_UARTF:
 180         case RT305X_GPIO_MODE_PCM_I2S:
 181         case RT305X_GPIO_MODE_I2S_UARTF:
 182                 rt305x_gpio_reserve(RT305X_GPIO_7, RT305X_GPIO_14);
 183                 break;
 184         case RT305X_GPIO_MODE_PCM_GPIO:
 185                 rt305x_gpio_reserve(RT305X_GPIO_10, RT305X_GPIO_14);
 186                 break;
 187         case RT305X_GPIO_MODE_GPIO_UARTF:
 188         case RT305X_GPIO_MODE_GPIO_I2S:
 189                 rt305x_gpio_reserve(RT305X_GPIO_7, RT305X_GPIO_10);
 190                 break;
 191         }
 192
 193         if ((mode & RT305X_GPIO_MODE_UART1) == 0)
 194                 rt305x_gpio_reserve(RT305X_GPIO_UART1_TXD,
 195                                     RT305X_GPIO_UART1_RXD);
 196
 197         if ((mode & RT305X_GPIO_MODE_JTAG) == 0)
 198                 rt305x_gpio_reserve(RT305X_GPIO_JTAG_TDO, RT305X_GPIO_JTAG_TDI);
 199
 200         if ((mode & RT305X_GPIO_MODE_MDIO) == 0)
 201                 rt305x_gpio_reserve(RT305X_GPIO_MDIO_MDC,
 202                                     RT305X_GPIO_MDIO_MDIO);
 203
 204         if ((mode & RT305X_GPIO_MODE_SDRAM) == 0)
 205                 rt305x_gpio_reserve(RT305X_GPIO_SDRAM_MD16,
 206                                     RT305X_GPIO_SDRAM_MD31);
 207
 208         if ((mode & RT305X_GPIO_MODE_RGMII) == 0)
 209                 rt305x_gpio_reserve(RT305X_GPIO_GE0_TXD0,
 210                                     RT305X_GPIO_GE0_RXCLK);
 211 }