target/linux/ramips/patches-4.3/0021-arch-mips-ralink-add-mt7688-detection.patch

   1 From 14ef339843c24bf449d0f6d8bc176368c331c2c8 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 7 Dec 2015 17:29:00 +0100
   4 Subject: [PATCH 21/53] arch: mips: ralink: add mt7688 detection
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/include/asm/mach-ralink/mt7620.h      |    1 +
   9  arch/mips/include/asm/mach-ralink/ralink_regs.h |    1 +
  10  arch/mips/ralink/mt7620.c                       |   21 ++++++++++++++++-----
  11  3 files changed, 18 insertions(+), 5 deletions(-)
  12
  13 diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
  14 index 0ef882b..455d406 100644
  15 --- a/arch/mips/include/asm/mach-ralink/mt7620.h
  16 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
  17 @@ -17,6 +17,7 @@
  18
  19  #define SYSC_REG_CHIP_NAME0            0x00
  20  #define SYSC_REG_CHIP_NAME1            0x04
  21 +#define SYSC_REG_EFUSE_CFG             0x08
  22  #define SYSC_REG_CHIP_REV              0x0c
  23  #define SYSC_REG_SYSTEM_CONFIG0                0x10
  24  #define SYSC_REG_SYSTEM_CONFIG1                0x14
  25 diff --git a/arch/mips/include/asm/mach-ralink/ralink_regs.h b/arch/mips/include/asm/mach-ralink/ralink_regs.h
  26 index 8fcbd0f..69fbcec 100644
  27 --- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
  28 +++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
  29 @@ -24,6 +24,7 @@ enum ralink_soc_type {
  30         MT762X_SOC_MT7620N,
  31         MT762X_SOC_MT7621AT,
  32         MT762X_SOC_MT7628AN,
  33 +       MT762X_SOC_MT7688,
  34  };
  35  extern enum ralink_soc_type ralink_soc;
  36
  37 diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
  38 index 41b4a3e..6975ed8 100644
  39 --- a/arch/mips/ralink/mt7620.c
  40 +++ b/arch/mips/ralink/mt7620.c
  41 @@ -46,6 +46,9 @@ enum mt762x_soc_type mt762x_soc;
  42  #define CLKCFG_FFRAC_MASK      0x001f
  43  #define CLKCFG_FFRAC_USB_VAL   0x0003
  44
  45 +/* EFUSE bits */
  46 +#define EFUSE_MT7688           0x100000
  47 +
  48  /* does the board have sdram or ddram */
  49  static int dram_type;
  50
  51 @@ -407,7 +410,7 @@ void __init ralink_clk_init(void)
  52  #define RINT(x)                ((x) / 1000000)
  53  #define RFRAC(x)       (((x) / 1000) % 1000)
  54
  55 -       if (mt762x_soc == MT762X_SOC_MT7628AN) {
  56 +       if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688) {
  57                 if (xtal_rate == MHZ(40))
  58                         cpu_rate = MHZ(580);
  59                 else
  60 @@ -451,7 +454,8 @@ void __init ralink_clk_init(void)
  61         ralink_clk_add("10000c00.uartlite", periph_rate);
  62         ralink_clk_add("10180000.wmac", xtal_rate);
  63
  64 -       if (IS_ENABLED(CONFIG_USB)) {
  65 +       if (IS_ENABLED(CONFIG_USB) &&
  66 +               (mt762x_soc == MT762X_SOC_MT7620A || mt762x_soc == MT762X_SOC_MT7620N)) {
  67                 /*
  68                  * When the CPU goes into sleep mode, the BUS clock will be too low for
  69                  * USB to function properly
  70 @@ -548,8 +552,15 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
  71                         soc_info->compatible = "ralink,mt7620n-soc";
  72                 }
  73         } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
  74 -               mt762x_soc = MT762X_SOC_MT7628AN;
  75 -               name = "MT7628AN";
  76 +               u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG);
  77 +
  78 +               if (efuse & EFUSE_MT7688) {
  79 +                       mt762x_soc = MT762X_SOC_MT7688;
  80 +                       name = "MT7688";
  81 +               } else {
  82 +                       mt762x_soc = MT762X_SOC_MT7628AN;
  83 +                       name = "MT7628AN";
  84 +               }
  85                 soc_info->compatible = "ralink,mt7628an-soc";
  86         } else {
  87                 panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
  88 @@ -582,7 +593,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
  89         pr_info("Digital PMU set to %s control\n",
  90                 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
  91
  92 -       if (mt762x_soc == MT762X_SOC_MT7628AN)
  93 +       if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688)
  94                 rt2880_pinmux_data = mt7628an_pinmux_data;
  95         else
  96                 rt2880_pinmux_data = mt7620a_pinmux_data;
  97 --
  98 1.7.10.4
  99