projects / openwrt / staging / mkresin.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Upgrade to Linux 2.6.19
[openwrt/staging/mkresin.git] / target / linux / rb532-2.6 / patches / 100-rb5xx_support.patch
1 diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig
2 --- linux.old/arch/mips/Kconfig 2006-11-29 22:57:37.000000000 +0100
3 +++ linux.dev/arch/mips/Kconfig 2006-12-14 04:09:50.000000000 +0100
4 @@ -728,6 +728,19 @@
5 select SYS_SUPPORTS_BIG_ENDIAN
6 select TOSHIBA_BOARDS
7
8 +config MIKROTIK_RB500
9 + bool "Support for RB5xx boards"
10 + select HW_HAS_PCI
11 + select IRQ_CPU
12 + select SYS_HAS_CPU_MIPS32_R1
13 + select SYS_SUPPORTS_LITTLE_ENDIAN
14 + select SYS_SUPPORTS_32BIT_KERNEL
15 + select SWAP_IO_SPACE
16 + select DMA_NONCOHERENT
17 + help
18 + Support the Mikrotik(tm) Routerboard 500 series,
19 + such as the RB532.
20 +
21 config TOSHIBA_RBTX4927
22 bool "Toshiba TBTX49[23]7 board"
23 select DMA_NONCOHERENT
24 @@ -1015,7 +1028,7 @@
25
26 config MIPS_L1_CACHE_SHIFT
27 int
28 - default "4" if MACH_DECSTATION
29 + default "4" if MACH_DECSTATION || MIKROTIK_RB500
30 default "7" if SGI_IP27
31 default "5"
32
33 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
34 --- linux.old/arch/mips/Makefile 2006-12-14 03:13:55.000000000 +0100
35 +++ linux.dev/arch/mips/Makefile 2006-12-14 04:09:50.000000000 +0100
36 @@ -586,6 +586,13 @@
37 load-$(CONFIG_TOSHIBA_JMR3927) += 0xffffffff80050000
38
39 #
40 +# Routerboard 532 board
41 +#
42 +core-$(CONFIG_MIKROTIK_RB500) += arch/mips/rb500/
43 +cflags-$(CONFIG_MIKROTIK_RB500) += -Iinclude/asm-mips/rc32434
44 +load-$(CONFIG_MIKROTIK_RB500) += 0xffffffff80101000
45 +
46 +#
47 # Toshiba RBTX4927 board or
48 # Toshiba RBTX4937 board
49 #
50 diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
51 --- linux.old/arch/mips/mm/tlbex.c 2006-11-29 22:57:37.000000000 +0100
52 +++ linux.dev/arch/mips/mm/tlbex.c 2006-12-14 04:09:50.000000000 +0100
53 @@ -874,7 +874,6 @@
54 case CPU_R10000:
55 case CPU_R12000:
56 case CPU_R14000:
57 - case CPU_4KC:
58 case CPU_SB1:
59 case CPU_SB1A:
60 case CPU_4KSC:
61 @@ -902,6 +901,7 @@
62 tlbw(p);
63 break;
64
65 + case CPU_4KC:
66 case CPU_4KEC:
67 case CPU_24K:
68 case CPU_34K:
69 diff -urN linux.old/arch/mips/pci/fixup-rb500.c linux.dev/arch/mips/pci/fixup-rb500.c
70 --- linux.old/arch/mips/pci/fixup-rb500.c 1970-01-01 01:00:00.000000000 +0100
71 +++ linux.dev/arch/mips/pci/fixup-rb500.c 2006-12-14 04:09:50.000000000 +0100
72 @@ -0,0 +1,49 @@
73 +/*
74 + * Copyright 2001 MontaVista Software Inc.
75 + * Author: MontaVista Software, Inc.
76 + * stevel@mvista.com or source@mvista.com
77 + *
78 + * This program is free software; you can redistribute it and/or modify it
79 + * under the terms of the GNU General Public License as published by the
80 + * Free Software Foundation; either version 2 of the License, or (at your
81 + * option) any later version.
82 + *
83 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
84 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
85 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
86 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
87 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
88 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
89 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
90 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
91 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
92 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
93 + *
94 + * You should have received a copy of the GNU General Public License along
95 + * with this program; if not, write to the Free Software Foundation, Inc.,
96 + * 675 Mass Ave, Cambridge, MA 02139, USA.
97 + */
98 +
99 +#include <linux/autoconf.h>
100 +#include <linux/types.h>
101 +#include <linux/pci.h>
102 +#include <linux/kernel.h>
103 +#include <linux/init.h>
104 +
105 +#include <asm/rc32434/rc32434.h>
106 +
107 +static int __devinitdata irq_map[2][12] = {
108 + { 0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1 },
109 + { 0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3 }
110 +};
111 +
112 +int __devinit pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
113 +{
114 + int irq = 0;
115 +
116 + if (dev->bus->number < 2 && PCI_SLOT(dev->devfn) < 12) {
117 + irq = irq_map[dev->bus->number][PCI_SLOT(dev->devfn)];
118 + }
119 + return irq + GROUP4_IRQ_BASE + 4;
120 +}
121 +
122 diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
123 --- linux.old/arch/mips/pci/Makefile 2006-11-29 22:57:37.000000000 +0100
124 +++ linux.dev/arch/mips/pci/Makefile 2006-12-14 04:09:50.000000000 +0100
125 @@ -53,3 +53,4 @@
126 obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
127 obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
128 obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
129 +obj-$(CONFIG_MIKROTIK_RB500) += pci-rc32434.o ops-rc32434.o fixup-rb500.o
130 diff -urN linux.old/arch/mips/pci/ops-rc32434.c linux.dev/arch/mips/pci/ops-rc32434.c
131 --- linux.old/arch/mips/pci/ops-rc32434.c 1970-01-01 01:00:00.000000000 +0100
132 +++ linux.dev/arch/mips/pci/ops-rc32434.c 2006-12-14 04:09:50.000000000 +0100
133 @@ -0,0 +1,195 @@
134 +/**************************************************************************
135 + *
136 + * BRIEF MODULE DESCRIPTION
137 + * pci_ops for IDT EB434 board
138 + *
139 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
140 + *
141 + * This program is free software; you can redistribute it and/or modify it
142 + * under the terms of the GNU General Public License as published by the
143 + * Free Software Foundation; either version 2 of the License, or (at your
144 + * option) any later version.
145 + *
146 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
147 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
148 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
149 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
150 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
151 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
152 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
153 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
154 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
155 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
156 + *
157 + * You should have received a copy of the GNU General Public License along
158 + * with this program; if not, write to the Free Software Foundation, Inc.,
159 + * 675 Mass Ave, Cambridge, MA 02139, USA.
160 + *
161 + *
162 + **************************************************************************
163 + * May 2004 rkt, neb
164 + *
165 + * Initial Release
166 + *
167 + *
168 + *
169 + **************************************************************************
170 + */
171 +
172 +#include <linux/autoconf.h>
173 +#include <linux/init.h>
174 +#include <linux/pci.h>
175 +#include <linux/types.h>
176 +#include <linux/delay.h>
177 +
178 +#include <asm/cpu.h>
179 +#include <asm/io.h>
180 +
181 +#include <asm/rc32434/rc32434.h>
182 +#include <asm/rc32434/pci.h>
183 +
184 +#define PCI_ACCESS_READ 0
185 +#define PCI_ACCESS_WRITE 1
186 +
187 +
188 +#define PCI_CFG_SET(bus,slot,func,off) \
189 + (rc32434_pci->pcicfga = (0x80000000 | \
190 + ((bus) << 16) | ((slot)<<11) | \
191 + ((func)<<8) | (off)))
192 +
193 +static inline int config_access(unsigned char access_type, struct pci_bus *bus,
194 + unsigned int devfn, unsigned char where,
195 + u32 * data)
196 +{
197 + unsigned int slot = PCI_SLOT(devfn);
198 + u8 func = PCI_FUNC(devfn);
199 +
200 + /* Setup address */
201 + PCI_CFG_SET(bus->number, slot, func, where);
202 + rc32434_sync();
203 +
204 + if (access_type == PCI_ACCESS_WRITE)
205 + rc32434_pci->pcicfgd = *data;
206 + else
207 + *data = rc32434_pci->pcicfgd;
208 +
209 + rc32434_sync();
210 +
211 + return 0;
212 +}
213 +
214 +
215 +/*
216 + * We can't address 8 and 16 bit words directly. Instead we have to
217 + * read/write a 32bit word and mask/modify the data we actually want.
218 + */
219 +static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
220 + int where, u8 * val)
221 +{
222 + u32 data;
223 + int ret;
224 +
225 + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
226 + *val = (data >> ((where & 3) << 3)) & 0xff;
227 + return ret;
228 +}
229 +
230 +static int read_config_word(struct pci_bus *bus, unsigned int devfn,
231 + int where, u16 * val)
232 +{
233 + u32 data;
234 + int ret;
235 +
236 + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
237 + *val = (data >> ((where & 3) << 3)) & 0xffff;
238 + return ret;
239 +}
240 +
241 +static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
242 + int where, u32 * val)
243 +{
244 + int ret;
245 +
246 + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
247 + return ret;
248 +}
249 +
250 +static int
251 +write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
252 + u8 val)
253 +{
254 + u32 data = 0;
255 +
256 + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
257 + return -1;
258 +
259 + data = (data & ~(0xff << ((where & 3) << 3))) |
260 + (val << ((where & 3) << 3));
261 +
262 + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
263 + return -1;
264 +
265 + return PCIBIOS_SUCCESSFUL;
266 +}
267 +
268 +
269 +static int
270 +write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
271 + u16 val)
272 +{
273 + u32 data = 0;
274 +
275 + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
276 + return -1;
277 +
278 + data = (data & ~(0xffff << ((where & 3) << 3))) |
279 + (val << ((where & 3) << 3));
280 +
281 + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
282 + return -1;
283 +
284 +
285 + return PCIBIOS_SUCCESSFUL;
286 +}
287 +
288 +
289 +static int
290 +write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
291 + u32 val)
292 +{
293 + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
294 + return -1;
295 +
296 + return PCIBIOS_SUCCESSFUL;
297 +}
298 +
299 +static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
300 + int where, int size, u32 * val)
301 +{
302 + switch (size) {
303 + case 1:
304 + return read_config_byte(bus, devfn, where, (u8 *) val);
305 + case 2:
306 + return read_config_word(bus, devfn, where, (u16 *) val);
307 + default:
308 + return read_config_dword(bus, devfn, where, val);
309 + }
310 +}
311 +
312 +static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
313 + int where, int size, u32 val)
314 +{
315 + switch (size) {
316 + case 1:
317 + return write_config_byte(bus, devfn, where, (u8) val);
318 + case 2:
319 + return write_config_word(bus, devfn, where, (u16) val);
320 + default:
321 + return write_config_dword(bus, devfn, where, val);
322 + }
323 +}
324 +
325 +struct pci_ops rc32434_pci_ops = {
326 + .read = pci_config_read,
327 + .write = pci_config_write,
328 +};
329 diff -urN linux.old/arch/mips/pci/pci-rc32434.c linux.dev/arch/mips/pci/pci-rc32434.c
330 --- linux.old/arch/mips/pci/pci-rc32434.c 1970-01-01 01:00:00.000000000 +0100
331 +++ linux.dev/arch/mips/pci/pci-rc32434.c 2006-12-14 04:09:50.000000000 +0100
332 @@ -0,0 +1,234 @@
333 +/**************************************************************************
334 + *
335 + * BRIEF MODULE DESCRIPTION
336 + * PCI initialization for IDT EB434 board
337 + *
338 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
339 + *
340 + * This program is free software; you can redistribute it and/or modify it
341 + * under the terms of the GNU General Public License as published by the
342 + * Free Software Foundation; either version 2 of the License, or (at your
343 + * option) any later version.
344 + *
345 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
346 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
347 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
348 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
349 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
350 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
351 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
352 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
353 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
354 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
355 + *
356 + * You should have received a copy of the GNU General Public License along
357 + * with this program; if not, write to the Free Software Foundation, Inc.,
358 + * 675 Mass Ave, Cambridge, MA 02139, USA.
359 + *
360 + *
361 + **************************************************************************
362 + * May 2004 rkt, neb
363 + *
364 + * Initial Release
365 + *
366 + *
367 + *
368 + **************************************************************************
369 + */
370 +
371 +#include <linux/autoconf.h>
372 +#include <linux/types.h>
373 +#include <linux/pci.h>
374 +#include <linux/kernel.h>
375 +#include <linux/init.h>
376 +
377 +#include <asm/rc32434/rc32434.h>
378 +#include <asm/rc32434/pci.h>
379 +
380 +#define PCI_ACCESS_READ 0
381 +#define PCI_ACCESS_WRITE 1
382 +
383 +/* define an unsigned array for the PCI registers */
384 +unsigned int korinaCnfgRegs[25] = {
385 + KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4,
386 + KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8,
387 + KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
388 + KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
389 + KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
390 + KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
391 +};
392 +static struct resource rc32434_res_pci_mem1;
393 +static struct resource rc32434_res_pci_mem2;
394 +
395 +static struct resource rc32434_res_pci_mem1 = {
396 + .name = "PCI MEM1",
397 + .start = 0x50000000,
398 + .end = 0x5FFFFFFF,
399 + .flags = IORESOURCE_MEM,
400 + .parent = &rc32434_res_pci_mem1,
401 + .sibling = NULL,
402 + .child = &rc32434_res_pci_mem2
403 +};
404 +
405 +static struct resource rc32434_res_pci_mem2 = {
406 + .name = "PCI Mem2",
407 + .start = 0x60000000,
408 + .end = 0x6FFFFFFF,
409 + .flags = IORESOURCE_MEM,
410 + .parent = &rc32434_res_pci_mem1,
411 + .sibling = NULL,
412 + .child = NULL
413 +};
414 +
415 +static struct resource rc32434_res_pci_io1 = {
416 + .name = "PCI I/O1",
417 + .start = 0x18800000,
418 + .end = 0x188FFFFF,
419 + .flags = IORESOURCE_IO,
420 +};
421 +
422 +extern struct pci_ops rc32434_pci_ops;
423 +
424 +#define PCI_MEM1_START PCI_ADDR_START
425 +#define PCI_MEM1_END PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1
426 +#define PCI_MEM2_START PCI_ADDR_START + CPUTOPCI_MEM_WIN
427 +#define PCI_MEM2_END PCI_ADDR_START + ( 2* CPUTOPCI_MEM_WIN) - 1
428 +#define PCI_IO1_START PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN)
429 +#define PCI_IO1_END PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN -1
430 +#define PCI_IO2_START PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN
431 +#define PCI_IO2_END PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) -1
432 +
433 +
434 +struct pci_controller rc32434_controller2;
435 +
436 +struct pci_controller rc32434_controller = {
437 + .pci_ops = &rc32434_pci_ops,
438 + .mem_resource = &rc32434_res_pci_mem1,
439 + .io_resource = &rc32434_res_pci_io1,
440 + .mem_offset = 0,
441 + .io_offset = 0,
442 +
443 +};
444 +
445 +#ifdef __MIPSEB__
446 +#define PCI_ENDIAN_FLAG PCILBAC_sb_m
447 +#else
448 +#define PCI_ENDIAN_FLAG 0
449 +#endif
450 +
451 +static int __init rc32434_pcibridge_init(void)
452 +{
453 + unsigned int pcicValue, pcicData = 0;
454 + unsigned int dummyRead, pciCntlVal;
455 + int loopCount;
456 + unsigned int pciConfigAddr;
457 +
458 + pcicValue = rc32434_pci->pcic;
459 + pcicValue = (pcicValue >> PCIM_SHFT) & PCIM_BIT_LEN;
460 + if (!((pcicValue == PCIM_H_EA) ||
461 + (pcicValue == PCIM_H_IA_FIX) ||
462 + (pcicValue == PCIM_H_IA_RR))) {
463 + printk("PCI init error!!!\n");
464 + /* Not in Host Mode, return ERROR */
465 + return -1;
466 + }
467 + /* Enables the Idle Grant mode, Arbiter Parking */
468 + pcicData |=(PCIC_igm_m|PCIC_eap_m|PCIC_en_m);
469 + rc32434_pci->pcic = pcicData; /* Enable the PCI bus Interface */
470 + /* Zero out the PCI status & PCI Status Mask */
471 + for(;;)
472 + {
473 + pcicData = rc32434_pci->pcis;
474 + if (!(pcicData & PCIS_rip_m))
475 + break;
476 + }
477 +
478 + rc32434_pci->pcis = 0;
479 + rc32434_pci->pcism = 0xFFFFFFFF;
480 + /* Zero out the PCI decoupled registers */
481 + rc32434_pci->pcidac=0; /* disable PCI decoupled accesses at initialization */
482 + rc32434_pci->pcidas=0; /* clear the status */
483 + rc32434_pci->pcidasm=0x0000007F; /* Mask all the interrupts */
484 + /* Mask PCI Messaging Interrupts */
485 + rc32434_pci_msg->pciiic = 0;
486 + rc32434_pci_msg->pciiim = 0xFFFFFFFF;
487 + rc32434_pci_msg->pciioic = 0;
488 + rc32434_pci_msg->pciioim = 0;
489 +
490 +
491 + /* Setup PCILB0 as Memory Window */
492 + rc32434_pci->pcilba[0].a = (unsigned int) (PCI_ADDR_START);
493 +
494 + /* setup the PCI map address as same as the local address */
495 +
496 + rc32434_pci->pcilba[0].m = (unsigned int) (PCI_ADDR_START);
497 +
498 +
499 + /* Setup PCILBA1 as MEM */
500 + rc32434_pci->pcilba[0].c = ( ((SIZE_256MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG);
501 + dummyRead = rc32434_pci->pcilba[0].c; /* flush the CPU write Buffers */
502 + rc32434_pci->pcilba[1].a = 0x60000000;
503 + rc32434_pci->pcilba[1].m = 0x60000000;
504 +
505 + /* setup PCILBA2 as IO Window*/
506 + rc32434_pci->pcilba[1].c = (((SIZE_256MB & 0x1f) << PCILBAC_size_b )| PCI_ENDIAN_FLAG);
507 + dummyRead = rc32434_pci->pcilba[1].c; /* flush the CPU write Buffers */
508 + rc32434_pci->pcilba[2].a = 0x18C00000;
509 + rc32434_pci->pcilba[2].m = 0x18FFFFFF;
510 +
511 + /* setup PCILBA2 as IO Window*/
512 + rc32434_pci->pcilba[2].c = (((SIZE_4MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG );
513 + dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */
514 +
515 + /* Setup PCILBA3 as IO Window */
516 + rc32434_pci->pcilba[3].a = 0x18800000;
517 + rc32434_pci->pcilba[3].m = 0x18800000;
518 + rc32434_pci->pcilba[3].c = ( (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m) | PCI_ENDIAN_FLAG);
519 + dummyRead = rc32434_pci->pcilba[3].c; /* flush the CPU write Buffers */
520 +
521 + pciConfigAddr=(unsigned int)(0x80000004);
522 + for(loopCount=0;loopCount<24;loopCount++){
523 + rc32434_pci->pcicfga=pciConfigAddr;
524 + dummyRead=rc32434_pci->pcicfga;
525 + rc32434_pci->pcicfgd = korinaCnfgRegs[loopCount];
526 + dummyRead=rc32434_pci->pcicfgd;
527 + pciConfigAddr += 4;
528 + }
529 + rc32434_pci->pcitc = (unsigned int)((PCITC_RTIMER_VAL&0xff) << PCITC_rtimer_b)
530 + | ((PCITC_DTIMER_VAL&0xff) << PCITC_dtimer_b);
531 +
532 + pciCntlVal=rc32434_pci->pcic;
533 + pciCntlVal &=~(PCIC_tnr_m);
534 + rc32434_pci->pcic = pciCntlVal;
535 + pciCntlVal=rc32434_pci->pcic;
536 + return 0;
537 +}
538 +
539 +/* Do platform specific device initialization at pci_enable_device() time */
540 +int pcibios_plat_dev_init(struct pci_dev *dev)
541 +{
542 + if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) {
543 + /* disable prefetched memory range */
544 + pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
545 + pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
546 +
547 + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
548 + }
549 + return 0;
550 +}
551 +
552 +static int __init rc32434_pci_init(void)
553 +{
554 + printk("PCI: Initializing PCI\n");
555 +
556 + ioport_resource.start = rc32434_res_pci_io1.start;
557 + ioport_resource.end = rc32434_res_pci_io1.end;
558 +
559 + rc32434_pcibridge_init();
560 +
561 + register_pci_controller(&rc32434_controller);
562 + rc32434_sync();
563 +}
564 +
565 +arch_initcall(rc32434_pci_init);
566 +
567 diff -urN linux.old/arch/mips/rb500/devices.c linux.dev/arch/mips/rb500/devices.c
568 --- linux.old/arch/mips/rb500/devices.c 1970-01-01 01:00:00.000000000 +0100
569 +++ linux.dev/arch/mips/rb500/devices.c 2006-12-14 04:09:50.000000000 +0100
570 @@ -0,0 +1,214 @@
571 +/*
572 + * RouterBoard 500 Platform devices
573 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
574 + *
575 + * This program is free software; you can redistribute it and/or modify
576 + * it under the terms of the GNU General Public License as published by
577 + * the Free Software Foundation; either version 2 of the License, or
578 + * (at your option) any later version.
579 + *
580 + * This program is distributed in the hope that it will be useful,
581 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
582 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
583 + * GNU General Public License for more details.
584 + *
585 + * $Id$
586 + */
587 +#include <linux/kernel.h>
588 +#include <linux/init.h>
589 +#include <linux/module.h>
590 +#include <linux/ctype.h>
591 +#include <linux/string.h>
592 +#include <linux/platform_device.h>
593 +#include <asm/unaligned.h>
594 +#include <asm/io.h>
595 +
596 +#include <asm/rc32434/rc32434.h>
597 +#include <asm/rc32434/dma.h>
598 +#include <asm/rc32434/dma_v.h>
599 +#include <asm/rc32434/eth.h>
600 +#include <asm/rc32434/rb.h>
601 +
602 +#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
603 +#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
604 +#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
605 +#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
606 +
607 +#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
608 +#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
609 +
610 +static struct resource korina_dev0_res[] = {
611 + {
612 + .name = "korina_regs",
613 + .start = ETH0_PhysicalAddress,
614 + .end = ETH0_PhysicalAddress + sizeof(ETH_t),
615 + .flags = IORESOURCE_MEM,
616 + },
617 + {
618 + .name = "korina_rx",
619 + .start = ETH0_DMA_RX_IRQ,
620 + .end = ETH0_DMA_RX_IRQ,
621 + .flags = IORESOURCE_IRQ
622 + },
623 + {
624 + .name = "korina_tx",
625 + .start = ETH0_DMA_TX_IRQ,
626 + .end = ETH0_DMA_TX_IRQ,
627 + .flags = IORESOURCE_IRQ
628 + },
629 + {
630 + .name = "korina_ovr",
631 + .start = ETH0_RX_OVR_IRQ,
632 + .end = ETH0_RX_OVR_IRQ,
633 + .flags = IORESOURCE_IRQ
634 + },
635 + {
636 + .name = "korina_und",
637 + .start = ETH0_TX_UND_IRQ,
638 + .end = ETH0_TX_UND_IRQ,
639 + .flags = IORESOURCE_IRQ
640 + },
641 + {
642 + .name = "korina_dma_rx",
643 + .start = ETH0_RX_DMA_ADDR,
644 + .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
645 + .flags = IORESOURCE_MEM,
646 + },
647 + {
648 + .name = "korina_dma_tx",
649 + .start = ETH0_TX_DMA_ADDR,
650 + .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
651 + .flags = IORESOURCE_MEM,
652 + }
653 +};
654 +
655 +static struct korina_device korina_dev0_data = {
656 + .name = "korina0",
657 + .mac = { 0xde, 0xca, 0xff, 0xc0, 0xff, 0xee }
658 +};
659 +
660 +static struct platform_device korina_dev0 = {
661 + .id = 0,
662 + .name = "korina",
663 + .dev.platform_data = &korina_dev0_data,
664 + .resource = korina_dev0_res,
665 + .num_resources = ARRAY_SIZE(korina_dev0_res),
666 +};
667 +
668 +
669 +#define CF_GPIO_NUM 13
670 +
671 +static struct resource cf_slot0_res[] = {
672 + {
673 + .name = "cf_membase",
674 + .flags = IORESOURCE_MEM
675 + },
676 + {
677 + .name = "cf_irq",
678 + .start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */
679 + .end = (8 + 4 * 32 + CF_GPIO_NUM),
680 + .flags = IORESOURCE_IRQ
681 + }
682 +};
683 +
684 +static struct cf_device cf_slot0_data = {
685 + .gpio_pin = 13
686 +};
687 +
688 +static struct platform_device cf_slot0 = {
689 + .id = 0,
690 + .name = "rb500-cf",
691 + .dev.platform_data = &cf_slot0_data,
692 + .resource = cf_slot0_res,
693 + .num_resources = ARRAY_SIZE(cf_slot0_res),
694 +};
695 +
696 +/* Resources and device for NAND. There is no data needed and no irqs, so just define the memory used. */
697 +static struct resource nand_slot0_res[] = {
698 + {
699 + .name = "nand_membase",
700 + .flags = IORESOURCE_MEM
701 + }
702 +};
703 +
704 +static struct platform_device nand_slot0 = {
705 + .id = 0,
706 + .name = "rb500-nand",
707 + .resource = nand_slot0_res,
708 + .num_resources = ARRAY_SIZE(nand_slot0_res),
709 +};
710 +
711 +
712 +static struct platform_device *rb500_devs[] = {
713 + &korina_dev0,
714 + &nand_slot0,
715 + &cf_slot0
716 +};
717 +
718 +static void __init parse_mac_addr(char* macstr)
719 +{
720 + int i, j;
721 + unsigned char result, value;
722 +
723 + for (i=0; i<6; i++) {
724 + result = 0;
725 + if (i != 5 && *(macstr+2) != ':') {
726 + return;
727 + }
728 + for (j=0; j<2; j++) {
729 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
730 + toupper(*macstr)-'A'+10) < 16) {
731 + result = result*16 + value;
732 + macstr++;
733 + }
734 + else return;
735 + }
736 +
737 + macstr++;
738 + korina_dev0_data.mac[i] = result;
739 + }
740 +}
741 +
742 +
743 +/* DEVICE CONTROLLER 1 */
744 +#define CFG_DC_DEV1 (void*)0xb8010010
745 +#define CFG_DC_DEV2 (void*)0xb8010020
746 +#define CFG_DC_DEVBASE 0x0
747 +#define CFG_DC_DEVMASK 0x4
748 +#define CFG_DC_DEVC 0x8
749 +#define CFG_DC_DEVTC 0xC
750 +
751 +
752 +static int __init plat_setup_devices(void)
753 +{
754 + /* Look for the CF card reader */
755 + if (!readl(CFG_DC_DEV1 + CFG_DC_DEVMASK))
756 + rb500_devs[1] = NULL;
757 + else {
758 + cf_slot0_res[0].start = readl(CFG_DC_DEV1 + CFG_DC_DEVBASE);
759 + cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
760 + }
761 +
762 + /* There is always a NAND device */
763 + nand_slot0_res[0].start = readl( CFG_DC_DEV2 + CFG_DC_DEVBASE);
764 + nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
765 +
766 + return platform_add_devices(rb500_devs, ARRAY_SIZE(rb500_devs));
767 +}
768 +
769 +static int __init setup_kmac(char *s)
770 +{
771 + printk("korina mac = %s\n",s);
772 + parse_mac_addr(s);
773 + return 0;
774 +}
775 +
776 +__setup("kmac=", setup_kmac);
777 +arch_initcall(plat_setup_devices);
778 +
779 +
780 +#if defined(CONFIG_MTD_BLOCK2MTD) && defined(CONFIG_BLK_DEV_CF_MIPS)
781 +extern void block2mtd_setup(char *initstr);
782 +extern void mount_devfs_fs(void);
783 +
784 +#endif
785 diff -urN linux.old/arch/mips/rb500/early_serial.c linux.dev/arch/mips/rb500/early_serial.c
786 --- linux.old/arch/mips/rb500/early_serial.c 1970-01-01 01:00:00.000000000 +0100
787 +++ linux.dev/arch/mips/rb500/early_serial.c 2006-12-14 04:09:50.000000000 +0100
788 @@ -0,0 +1,199 @@
789 +/**************************************************************************
790 + *
791 + * BRIEF MODULE DESCRIPTION
792 + * EB434 specific polling driver for 16550 UART.
793 + *
794 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
795 + *
796 + * This program is free software; you can redistribute it and/or modify it
797 + * under the terms of the GNU General Public License as published by the
798 + * Free Software Foundation; either version 2 of the License, or (at your
799 + * option) any later version.
800 + *
801 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
802 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
803 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
804 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
805 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
806 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
807 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
808 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
809 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
810 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
811 + *
812 + * You should have received a copy of the GNU General Public License along
813 + * with this program; if not, write to the Free Software Foundation, Inc.,
814 + * 675 Mass Ave, Cambridge, MA 02139, USA.
815 + *
816 + *
817 + **************************************************************************
818 + * Copyright (C) 2000 by Lineo, Inc.
819 + * Written by Quinn Jensen (jensenq@lineo.com)
820 + **************************************************************************
821 + * P. Sadik Oct 20, 2003
822 + *
823 + * DIVISOR is made a function of idt_cpu_freq
824 + **************************************************************************
825 + * P. Sadik Oct 30, 2003
826 + *
827 + * added reset_cons_port
828 + **************************************************************************
829 + */
830 +
831 +#include <linux/serial_reg.h>
832 +
833 +/* turn this on to watch the debug protocol echoed on the console port */
834 +#define DEBUG_REMOTE_DEBUG
835 +
836 +#define CONS_BAUD 115200
837 +
838 +extern unsigned int idt_cpu_freq;
839 +
840 +#define EXT_FREQ 24000000
841 +#define INT_FREQ idt_cpu_freq
842 +
843 +#define EXT_PORT 0xb9800000u
844 +#define EXT_SHIFT 0
845 +
846 +#ifdef __MIPSEB__
847 +#define INT_PORT 0xb8058003u
848 +#else
849 +#define INT_PORT 0xb8058000u
850 +#endif
851 +#define INT_SHIFT 2
852 +
853 +#define INT_FCR UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14
854 +#define EXT_FCR UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT
855 +
856 +typedef struct
857 +{
858 + volatile unsigned char *base;
859 + unsigned int shift;
860 + unsigned int freq;
861 + unsigned int fcr;
862 +} ser_port;
863 +
864 +ser_port ports[2] =
865 +{
866 + { (volatile unsigned char *)INT_PORT, INT_SHIFT, 0, INT_FCR},
867 + { (volatile unsigned char *)EXT_PORT, EXT_SHIFT, EXT_FREQ, EXT_FCR}
868 +};
869 +
870 +#define CONS_PORT 0
871 +
872 +void cons_putc(char c);
873 +int port_getc(int port);
874 +void port_putc(int port, char c);
875 +
876 +int cons_getc(void)
877 +{
878 + return port_getc(CONS_PORT);
879 +}
880 +
881 +void cons_putc(char c)
882 +{
883 + port_putc(CONS_PORT, c);
884 +}
885 +
886 +void cons_puts(char *s)
887 +{
888 + while(*s) {
889 + if(*s == '\n') cons_putc('\r');
890 + cons_putc(*s);
891 + s++;
892 + }
893 +}
894 +
895 +void cons_do_putn(int n)
896 +{
897 + if(n) {
898 + cons_do_putn(n / 10);
899 + cons_putc(n % 10 + '0');
900 + }
901 +}
902 +
903 +void cons_putn(int n)
904 +{
905 + if(n < 0) {
906 + cons_putc('-');
907 + n = -n;
908 + }
909 +
910 + if (n == 0) {
911 + cons_putc('0');
912 + } else {
913 + cons_do_putn(n);
914 + }
915 +}
916 +
917 +int port_getc(int p)
918 +{
919 + volatile unsigned char *port = ports[p].base;
920 + int s = ports[p].shift;
921 + int c;
922 +
923 + while((*(port + (UART_LSR << s)) & UART_LSR_DR) == 0) {
924 + continue;
925 + }
926 +
927 + c = *(port + (UART_RX << s));
928 +
929 + return c;
930 +}
931 +
932 +int port_getc_ready(int p)
933 +{
934 + volatile unsigned char *port = ports[p].base;
935 + int s = ports[p].shift;
936 +
937 + return *(port + (UART_LSR << s)) & UART_LSR_DR;
938 +}
939 +
940 +#define OK_TO_XMT (UART_LSR_TEMT | UART_LSR_THRE)
941 +
942 +void port_putc(int p, char c)
943 +{
944 + volatile unsigned char *port = ports[p].base;
945 + int s = ports[p].shift;
946 + volatile unsigned char *lsr = port + (UART_LSR << s);
947 +
948 + while((*lsr & OK_TO_XMT) != OK_TO_XMT) {
949 + continue;
950 + }
951 +
952 + *(port + (UART_TX << s)) = c;
953 +}
954 +
955 +void reset_cons_port(void)
956 +{
957 + volatile unsigned char *port = ports[CONS_PORT].base;
958 + unsigned int s = ports[CONS_PORT].shift;
959 + unsigned int DIVISOR;
960 +
961 + if (ports[CONS_PORT].freq)
962 + DIVISOR = (ports[CONS_PORT].freq / 16 / CONS_BAUD);
963 + else
964 + DIVISOR = (idt_cpu_freq / 16 / CONS_BAUD);
965 +
966 + /* reset the port */
967 + *(port + (UART_CSR << s)) = 0;
968 +
969 + /* clear and enable the FIFOs */
970 + *(port + (UART_FCR << s)) = ports[CONS_PORT].fcr;
971 +
972 + /* set the baud rate */
973 + *(port + (UART_LCR << s)) = UART_LCR_DLAB; /* enable DLL, DLM registers */
974 +
975 + *(port + (UART_DLL << s)) = DIVISOR;
976 + *(port + (UART_DLM << s)) = DIVISOR >> 8;
977 + /* set the line control stuff and disable DLL, DLM regs */
978 +
979 + *(port + (UART_LCR << s)) = UART_LCR_STOP | /* 2 stop bits */
980 + UART_LCR_WLEN8; /* 8 bit word length */
981 +
982 + /* leave interrupts off */
983 + *(port + (UART_IER << s)) = 0;
984 +
985 + /* the modem controls don't leave the chip on this port, so leave them alone */
986 + *(port + (UART_MCR << s)) = 0;
987 +}
988 diff -urN linux.old/arch/mips/rb500/irq.c linux.dev/arch/mips/rb500/irq.c
989 --- linux.old/arch/mips/rb500/irq.c 1970-01-01 01:00:00.000000000 +0100
990 +++ linux.dev/arch/mips/rb500/irq.c 2006-12-14 04:14:16.000000000 +0100
991 @@ -0,0 +1,264 @@
992 +/*
993 + * BRIEF MODULE DESCRIPTION
994 + * RC32434 interrupt routines.
995 + *
996 + * Copyright 2002 MontaVista Software Inc.
997 + * Author: MontaVista Software, Inc.
998 + * stevel@mvista.com or source@mvista.com
999 + *
1000 + * This program is free software; you can redistribute it and/or modify it
1001 + * under the terms of the GNU General Public License as published by the
1002 + * Free Software Foundation; either version 2 of the License, or (at your
1003 + * option) any later version.
1004 + *
1005 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1006 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1007 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1008 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1009 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1010 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1011 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1012 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1013 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1014 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1015 + *
1016 + * You should have received a copy of the GNU General Public License along
1017 + * with this program; if not, write to the Free Software Foundation, Inc.,
1018 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1019 + */
1020 +
1021 +#include <linux/errno.h>
1022 +#include <linux/init.h>
1023 +#include <linux/kernel_stat.h>
1024 +#include <linux/module.h>
1025 +#include <linux/signal.h>
1026 +#include <linux/sched.h>
1027 +#include <linux/types.h>
1028 +#include <linux/interrupt.h>
1029 +#include <linux/ioport.h>
1030 +#include <linux/timex.h>
1031 +#include <linux/slab.h>
1032 +#include <linux/random.h>
1033 +#include <linux/delay.h>
1034 +
1035 +#include <asm/bitops.h>
1036 +#include <asm/bootinfo.h>
1037 +#include <asm/io.h>
1038 +#include <asm/irq.h>
1039 +#include <asm/time.h>
1040 +#include <asm/mipsregs.h>
1041 +#include <asm/system.h>
1042 +#include <asm/rc32434/rc32434.h>
1043 +#include <asm/rc32434/gpio.h>
1044 +
1045 +extern void set_debug_traps(void);
1046 +extern irq_cpustat_t irq_stat [NR_CPUS];
1047 +unsigned int local_bh_count[NR_CPUS];
1048 +unsigned int local_irq_count[NR_CPUS];
1049 +
1050 +static unsigned int startup_irq(unsigned int irq);
1051 +static void rb500_end_irq(unsigned int irq_nr);
1052 +static void mask_and_ack_irq(unsigned int irq_nr);
1053 +static void rb500_enable_irq(unsigned int irq_nr);
1054 +static void rb500_disable_irq(unsigned int irq_nr);
1055 +
1056 +extern void __init init_generic_irq(void);
1057 +
1058 +typedef struct {
1059 + u32 mask; /* mask of valid bits in pending/mask registers */
1060 + volatile u32 *base_addr;
1061 +} intr_group_t;
1062 +
1063 +#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
1064 +
1065 +#if (NR_IRQS < RC32434_NR_IRQS)
1066 +#error Too little irqs defined. Did you override <asm/irq.h> ?
1067 +#endif
1068 +
1069 +static const intr_group_t intr_group[NUM_INTR_GROUPS] = {
1070 + { 0x0000efff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET) },
1071 + { 0x00001fff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET) },
1072 + { 0x00000007, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET) },
1073 + { 0x0003ffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET) },
1074 + { 0xffffffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET) }
1075 +};
1076 +
1077 +#define READ_PEND(base) (*(base))
1078 +#define READ_MASK(base) (*(base + 2))
1079 +#define WRITE_MASK(base, val) (*(base + 2) = (val))
1080 +
1081 +static inline int irq_to_group(unsigned int irq_nr)
1082 +{
1083 + return ((irq_nr - GROUP0_IRQ_BASE) >> 5);
1084 +}
1085 +
1086 +static inline int group_to_ip(unsigned int group)
1087 +{
1088 + return group + 2;
1089 +}
1090 +
1091 +static inline void enable_local_irq(unsigned int ip)
1092 +{
1093 + int ipnum = 0x100 << ip;
1094 + clear_c0_cause(ipnum);
1095 + set_c0_status(ipnum);
1096 +}
1097 +
1098 +static inline void disable_local_irq(unsigned int ip)
1099 +{
1100 + int ipnum = 0x100 << ip;
1101 + clear_c0_status(ipnum);
1102 +}
1103 +
1104 +static inline void ack_local_irq(unsigned int ip)
1105 +{
1106 + int ipnum = 0x100 << ip;
1107 + clear_c0_cause(ipnum);
1108 +}
1109 +
1110 +static void rb500_enable_irq(unsigned int irq_nr)
1111 +{
1112 + int ip = irq_nr - GROUP0_IRQ_BASE;
1113 + unsigned int group, intr_bit;
1114 + volatile unsigned int *addr;
1115 +
1116 +
1117 + if (ip < 0)
1118 + enable_local_irq(irq_nr);
1119 + else {
1120 + group = ip >> 5;
1121 +
1122 + ip &= (1<<5)-1;
1123 + intr_bit = 1 << ip;
1124 +
1125 + enable_local_irq(group_to_ip(group));
1126 +
1127 + addr = intr_group[group].base_addr;
1128 + WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
1129 + }
1130 +}
1131 +
1132 +static void rb500_disable_irq(unsigned int irq_nr)
1133 +{
1134 + int ip = irq_nr - GROUP0_IRQ_BASE;
1135 + unsigned int group, intr_bit, mask;
1136 + volatile unsigned int *addr;
1137 +
1138 + if (ip < 0) {
1139 + disable_local_irq(irq_nr);
1140 + }else{
1141 + group = ip >> 5;
1142 +
1143 + ip &= (1<<5) -1;
1144 + intr_bit = 1 << ip;
1145 + addr = intr_group[group].base_addr;
1146 + mask = READ_MASK(addr);
1147 + mask |= intr_bit;
1148 + WRITE_MASK(addr,mask);
1149 +
1150 + /*
1151 + * if there are no more interrupts enabled in this
1152 + * group, disable corresponding IP
1153 + */
1154 + if (mask == intr_group[group].mask)
1155 + disable_local_irq(group_to_ip(group));
1156 + }
1157 +}
1158 +
1159 +static unsigned int startup_irq(unsigned int irq_nr)
1160 +{
1161 + rb500_enable_irq(irq_nr);
1162 + return 0;
1163 +}
1164 +
1165 +static void shutdown_irq(unsigned int irq_nr)
1166 +{
1167 + rb500_disable_irq(irq_nr);
1168 + return;
1169 +}
1170 +
1171 +static void mask_and_ack_irq(unsigned int irq_nr)
1172 +{
1173 + rb500_disable_irq(irq_nr);
1174 + ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
1175 +}
1176 +
1177 +static void rb500_end_irq(unsigned int irq_nr)
1178 +{
1179 +
1180 + int ip = irq_nr - GROUP0_IRQ_BASE;
1181 + unsigned int intr_bit, group;
1182 + volatile unsigned int *addr;
1183 +
1184 + if ((irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
1185 + printk("warning: end_irq %d did not enable (%x)\n",
1186 + irq_nr, irq_desc[irq_nr].status);
1187 + return;
1188 + }
1189 +
1190 + if (ip < 0) {
1191 + enable_local_irq(irq_nr);
1192 + } else {
1193 + group = ip >> 5;
1194 +
1195 + ip &= (1 << 5) - 1;
1196 + intr_bit = 1 << ip;
1197 +
1198 + if (irq_nr >= GROUP4_IRQ_BASE && irq_nr <= (GROUP4_IRQ_BASE + 13)) {
1199 + gpio->gpioistat = gpio->gpioistat & ~intr_bit;
1200 + }
1201 +
1202 + enable_local_irq(group_to_ip(group));
1203 +
1204 + addr = intr_group[group].base_addr;
1205 + WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
1206 + }
1207 +}
1208 +
1209 +static struct hw_interrupt_type rc32434_irq_type = {
1210 + .typename = "RB500",
1211 + .startup = startup_irq,
1212 + .shutdown = shutdown_irq,
1213 + .enable = rb500_enable_irq,
1214 + .disable = rb500_disable_irq,
1215 + .ack = mask_and_ack_irq,
1216 + .end = rb500_end_irq,
1217 +};
1218 +
1219 +
1220 +void __init arch_init_irq(void)
1221 +{
1222 + int i;
1223 +
1224 + printk("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
1225 + memset(irq_desc, 0, sizeof(irq_desc));
1226 +
1227 + for (i = 0; i < RC32434_NR_IRQS; i++) {
1228 + irq_desc[i].status = IRQ_DISABLED;
1229 + irq_desc[i].action = NULL;
1230 + irq_desc[i].depth = 1;
1231 + irq_desc[i].chip = &rc32434_irq_type;
1232 + spin_lock_init(&irq_desc[i].lock);
1233 + }
1234 +}
1235 +
1236 +/* Main Interrupt dispatcher */
1237 +asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
1238 +{
1239 + unsigned int ip, pend, group;
1240 + volatile unsigned int *addr;
1241 + unsigned int cp0_cause = read_c0_cause() & read_c0_status();
1242 +
1243 + if (cp0_cause & CAUSEF_IP7) {
1244 + ll_timer_interrupt(7);
1245 + } else if ((ip = (cp0_cause & 0x7c00))) {
1246 + group = 21 - rc32434_clz(ip);
1247 +
1248 + addr = intr_group[group].base_addr;
1249 +
1250 + pend = READ_PEND(addr);
1251 + pend &= ~READ_MASK(addr); // only unmasked interrupts
1252 + pend = 39 - rc32434_clz(pend);
1253 + do_IRQ((group << 5) + pend);
1254 + }
1255 +}
1256 diff -urN linux.old/arch/mips/rb500/Makefile linux.dev/arch/mips/rb500/Makefile
1257 --- linux.old/arch/mips/rb500/Makefile 1970-01-01 01:00:00.000000000 +0100
1258 +++ linux.dev/arch/mips/rb500/Makefile 2006-12-14 04:09:50.000000000 +0100
1259 @@ -0,0 +1,5 @@
1260 +#
1261 +# Makefile for the RB500 board specific parts of the kernel
1262 +#
1263 +
1264 +obj-y += irq.o time.o setup.o serial.o early_serial.o prom.o misc.o devices.o
1265 diff -urN linux.old/arch/mips/rb500/misc.c linux.dev/arch/mips/rb500/misc.c
1266 --- linux.old/arch/mips/rb500/misc.c 1970-01-01 01:00:00.000000000 +0100
1267 +++ linux.dev/arch/mips/rb500/misc.c 2006-12-14 04:09:50.000000000 +0100
1268 @@ -0,0 +1,56 @@
1269 +#include <linux/module.h>
1270 +#include <linux/kernel.h> /* printk() */
1271 +#include <linux/types.h> /* size_t */
1272 +#include <linux/pci.h>
1273 +#include <linux/spinlock.h>
1274 +#include <asm/rc32434/rb.h>
1275 +
1276 +#define GPIO_BADDR 0xb8050000
1277 +
1278 +
1279 +static volatile unsigned char *devCtl3Base = 0;
1280 +static unsigned char latchU5State = 0;
1281 +static spinlock_t clu5Lock = SPIN_LOCK_UNLOCKED;
1282 +
1283 +void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val) {
1284 + unsigned flags, data;
1285 + unsigned i = 0;
1286 + spin_lock_irqsave(&clu5Lock, flags);
1287 + data = *(volatile unsigned *) (IDT434_REG_BASE + regOffs);
1288 + for (i = 0; i != len; ++i) {
1289 + if (val & (1 << i)) data |= (1 << (i + bit));
1290 + else data &= ~(1 << (i + bit));
1291 + }
1292 + *(volatile unsigned *) (IDT434_REG_BASE + regOffs) = data;
1293 + spin_unlock_irqrestore(&clu5Lock, flags);
1294 +}
1295 +
1296 +void changeLatchU5(unsigned char orMask, unsigned char nandMask) {
1297 + unsigned flags;
1298 + spin_lock_irqsave(&clu5Lock, flags);
1299 + latchU5State = (latchU5State | orMask) & ~nandMask;
1300 + if( !devCtl3Base) devCtl3Base = (volatile unsigned char *)
1301 + KSEG1ADDR(*(volatile unsigned *) KSEG1ADDR(0x18010030));
1302 + *devCtl3Base = latchU5State;
1303 + spin_unlock_irqrestore(&clu5Lock, flags);
1304 +}
1305 +
1306 +u32 gpio_get(gpio_func func)
1307 +{
1308 + return readl((void *) GPIO_BADDR + func);
1309 +}
1310 +
1311 +void gpio_set(gpio_func func, u32 mask, u32 value)
1312 +{
1313 + u32 val = readl((void *) GPIO_BADDR + func);
1314 +
1315 + val &= ~mask;
1316 + val |= value & mask;
1317 +
1318 + writel(val, (void *) GPIO_BADDR + func);
1319 +}
1320 +
1321 +EXPORT_SYMBOL(gpio_set);
1322 +EXPORT_SYMBOL(gpio_get);
1323 +EXPORT_SYMBOL(set434Reg);
1324 +EXPORT_SYMBOL(changeLatchU5);
1325 diff -urN linux.old/arch/mips/rb500/prom.c linux.dev/arch/mips/rb500/prom.c
1326 --- linux.old/arch/mips/rb500/prom.c 1970-01-01 01:00:00.000000000 +0100
1327 +++ linux.dev/arch/mips/rb500/prom.c 2006-12-14 05:15:05.000000000 +0100
1328 @@ -0,0 +1,181 @@
1329 +/*
1330 +* prom.c
1331 +**********************************************************************
1332 +* P . Sadik Oct 10, 2003
1333 +*
1334 +* Started change log
1335 +* idt_cpu_freq is make a kernel configuration parameter
1336 +* idt_cpu_freq is exported so that other modules can use it.
1337 +* Code cleanup
1338 +**********************************************************************
1339 +* P. Sadik Oct 20, 2003
1340 +*
1341 +* Removed NVRAM code from here, since they are already available under
1342 +* nvram directory.
1343 +* Added serial port initialisation.
1344 +**********************************************************************
1345 +**********************************************************************
1346 +* P. Sadik Oct 30, 2003
1347 +*
1348 +* Added reset_cons_port
1349 +**********************************************************************
1350 +
1351 + P.Christeas, 2005-2006
1352 + Port to 2.6, add 2.6 cmdline parsing
1353 +
1354 +*/
1355 +
1356 +#include <linux/autoconf.h>
1357 +#include <linux/init.h>
1358 +#include <linux/mm.h>
1359 +#include <linux/module.h>
1360 +#include <linux/string.h>
1361 +#include <linux/console.h>
1362 +#include <asm/bootinfo.h>
1363 +#include <linux/bootmem.h>
1364 +#include <linux/ioport.h>
1365 +#include <linux/blkdev.h>
1366 +#include <asm/rc32434/ddr.h>
1367 +
1368 +#define PROM_ENTRY(x) (0xbfc00000+((x)*8))
1369 +extern void __init setup_serial_port(void);
1370 +extern void cons_putc(char c);
1371 +extern void cons_puts(char *s);
1372 +
1373 +unsigned int idt_cpu_freq = 132000000;
1374 +EXPORT_SYMBOL(idt_cpu_freq);
1375 +unsigned int board_type = 500;
1376 +EXPORT_SYMBOL(board_type);
1377 +unsigned int gpio_bootup_state = 0;
1378 +EXPORT_SYMBOL(gpio_bootup_state);
1379 +
1380 +
1381 +char mips_mac_address[18] = "08:00:06:05:40:01";
1382 +EXPORT_SYMBOL(mips_mac_address);
1383 +
1384 +/* what to append to cmdline when button is [not] pressed */
1385 +#define GPIO_INIT_NOBUTTON ""
1386 +#define GPIO_INIT_BUTTON " 2"
1387 +
1388 +#ifdef CONFIG_MIKROTIK_RB500
1389 +unsigned soft_reboot = 0;
1390 +EXPORT_SYMBOL(soft_reboot);
1391 +#endif
1392 +
1393 +#define SR_NMI 0x00180000 /* NMI */
1394 +#define SERIAL_SPEED_ENTRY 0x00000001
1395 +
1396 +#ifdef CONFIG_REMOTE_DEBUG
1397 +extern int remote_debug;
1398 +#endif
1399 +
1400 +extern unsigned long mips_machgroup;
1401 +extern unsigned long mips_machtype;
1402 +
1403 +#define FREQ_TAG "HZ="
1404 +#define GPIO_TAG "gpio="
1405 +#define KMAC_TAG "kmac="
1406 +#define MEM_TAG "mem="
1407 +#define BOARD_TAG "board="
1408 +#define IGNORE_CMDLINE_MEM 1
1409 +#define DEBUG_DDR
1410 +
1411 +void parse_soft_settings(unsigned *ptr, unsigned size);
1412 +void parse_hard_settings(unsigned *ptr, unsigned size);
1413 +
1414 +void __init prom_setup_cmdline(void);
1415 +
1416 +#ifdef DEBUG_DDR
1417 +void cons_puthex4(u32 h){
1418 + h&=0x0f;
1419 + if (h>=10)
1420 + cons_putc((h-10)+'a');
1421 + else
1422 + cons_putc(h+'0');
1423 +}
1424 +
1425 +void cons_putreg32(u32 reg){
1426 + char c;
1427 + cons_putc('0');
1428 + cons_putc('x');
1429 + for (c=28;c>=0;c-=4)
1430 + cons_puthex4(reg>>c);
1431 +}
1432 +#endif
1433 +
1434 +void __init prom_init(void)
1435 +{
1436 + DDR_t ddr = (DDR_t) DDR_VirtualAddress; /* define the pointer to the DDR registers */
1437 + phys_t memsize = 0-ddr->ddrmask;
1438 +
1439 + /* this should be the very first message, even before serial is properly initialized */
1440 + prom_setup_cmdline();
1441 + setup_serial_port();
1442 +
1443 + mips_machgroup = MACH_GROUP_MIKROTIK;
1444 + soft_reboot = read_c0_status() & SR_NMI;
1445 + pm_power_off = NULL;
1446 +
1447 + /*
1448 + * give all RAM to boot allocator,
1449 + * except for the first 0x400 and the last 0x200 bytes
1450 + */
1451 + add_memory_region(ddr->ddrbase + 0x400, memsize - 0x600, BOOT_MEM_RAM);
1452 +}
1453 +
1454 +void prom_free_prom_memory(void)
1455 +{
1456 + /* FIXME: STUB */
1457 +}
1458 +
1459 +void __init prom_setup_cmdline(void){
1460 + char cmd_line[CL_SIZE];
1461 + char *cp;
1462 + int prom_argc;
1463 + char **prom_argv, **prom_envp;
1464 + int i;
1465 +
1466 + prom_argc = fw_arg0;
1467 + prom_argv = (char **) fw_arg1;
1468 + prom_envp = (char **) fw_arg2;
1469 +
1470 + cp=cmd_line;
1471 + /* Note: it is common that parameters start at argv[1] and not argv[0],
1472 + however, our elf loader starts at [0] */
1473 + for(i=0;i<prom_argc;i++){
1474 + if (strncmp(prom_argv[i], FREQ_TAG, sizeof(FREQ_TAG) - 1) == 0) {
1475 + idt_cpu_freq = simple_strtoul(prom_argv[i] + sizeof(FREQ_TAG) - 1, 0, 10);
1476 + continue;
1477 + }
1478 +#ifdef IGNORE_CMDLINE_MEM
1479 + /* parses out the "mem=xx" arg */
1480 + if (strncmp(prom_argv[i], MEM_TAG, sizeof(MEM_TAG) - 1) == 0) {
1481 + continue;
1482 + }
1483 +#endif
1484 + if (i>0) *(cp++) = ' ';
1485 + if (strncmp(prom_argv[i], BOARD_TAG, sizeof(BOARD_TAG) - 1) == 0) {
1486 + board_type = simple_strtoul(prom_argv[i] + sizeof(BOARD_TAG) - 1, 0, 10);
1487 + }
1488 + if (strncmp(prom_argv[i], GPIO_TAG, sizeof(GPIO_TAG) - 1) == 0) {
1489 + gpio_bootup_state = simple_strtoul(prom_argv[i] + sizeof(GPIO_TAG) - 1, 0, 10);
1490 + }
1491 + strcpy(cp,prom_argv[i]);
1492 + cp+=strlen(prom_argv[i]);
1493 + }
1494 +
1495 + i=strlen(arcs_cmdline);
1496 + if (i>0){
1497 + *(cp++) = ' ';
1498 + strcpy(cp,arcs_cmdline);
1499 + cp+=strlen(arcs_cmdline);
1500 + }
1501 + if (gpio_bootup_state&0x02)
1502 + strcpy(cp,GPIO_INIT_NOBUTTON);
1503 + else
1504 + strcpy(cp,GPIO_INIT_BUTTON);
1505 + cmd_line[CL_SIZE-1] = '\0';
1506 +
1507 + strcpy(arcs_cmdline,cmd_line);
1508 +}
1509 +
1510 diff -urN linux.old/arch/mips/rb500/serial.c linux.dev/arch/mips/rb500/serial.c
1511 --- linux.old/arch/mips/rb500/serial.c 1970-01-01 01:00:00.000000000 +0100
1512 +++ linux.dev/arch/mips/rb500/serial.c 2006-12-14 04:09:50.000000000 +0100
1513 @@ -0,0 +1,79 @@
1514 +/**************************************************************************
1515 + *
1516 + * BRIEF MODULE DESCRIPTION
1517 + * Serial port initialisation.
1518 + *
1519 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1520 + *
1521 + * This program is free software; you can redistribute it and/or modify it
1522 + * under the terms of the GNU General Public License as published by the
1523 + * Free Software Foundation; either version 2 of the License, or (at your
1524 + * option) any later version.
1525 + *
1526 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1527 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1528 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1529 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1530 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1531 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1532 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1533 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1534 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1535 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1536 + *
1537 + * You should have received a copy of the GNU General Public License along
1538 + * with this program; if not, write to the Free Software Foundation, Inc.,
1539 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1540 + *
1541 + *
1542 + **************************************************************************
1543 + * May 2004 rkt, neb
1544 + *
1545 + * Initial Release
1546 + *
1547 + *
1548 + *
1549 + **************************************************************************
1550 + */
1551 +
1552 +
1553 +#include <linux/autoconf.h>
1554 +#include <linux/init.h>
1555 +#include <linux/sched.h>
1556 +#include <linux/pci.h>
1557 +#include <linux/interrupt.h>
1558 +#include <linux/tty.h>
1559 +#include <linux/serial.h>
1560 +#include <linux/serial_core.h>
1561 +
1562 +#include <asm/time.h>
1563 +#include <asm/cpu.h>
1564 +#include <asm/bootinfo.h>
1565 +#include <asm/irq.h>
1566 +#include <asm/serial.h>
1567 +#include <asm/rc32434/rc32434.h>
1568 +
1569 +extern unsigned int idt_cpu_freq;
1570 +
1571 +static struct uart_port serial_req = {
1572 + .type = PORT_16550A,
1573 + .line = 0,
1574 + .irq = RC32434_UART0_IRQ,
1575 + .flags = STD_COM_FLAGS,
1576 + .iotype = UPIO_MEM,
1577 + .membase = (char *) KSEG1ADDR(RC32434_UART0_BASE),
1578 +// .fifosize = 14
1579 + .regshift = 2
1580 +};
1581 +
1582 +int __init setup_serial_port(void)
1583 +{
1584 + serial_req.uartclk = idt_cpu_freq;
1585 +
1586 + if (early_serial_setup(&serial_req)){
1587 + cons_puts("Serial setup failed!\n");
1588 + return -ENODEV;
1589 + }
1590 +
1591 + return(0);
1592 +}
1593 diff -urN linux.old/arch/mips/rb500/setup.c linux.dev/arch/mips/rb500/setup.c
1594 --- linux.old/arch/mips/rb500/setup.c 1970-01-01 01:00:00.000000000 +0100
1595 +++ linux.dev/arch/mips/rb500/setup.c 2006-12-14 04:51:12.000000000 +0100
1596 @@ -0,0 +1,81 @@
1597 +/*
1598 + * setup.c - boot time setup code
1599 + */
1600 +
1601 +#include <linux/init.h>
1602 +#include <linux/mm.h>
1603 +#include <linux/sched.h>
1604 +#include <linux/irq.h>
1605 +#include <linux/ioport.h>
1606 +#include <linux/pm.h>
1607 +#include <asm/bootinfo.h>
1608 +#include <asm/mipsregs.h>
1609 +#include <asm/pgtable.h>
1610 +#include <asm/reboot.h>
1611 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
1612 +#include <asm/time.h>
1613 +#include <asm/io.h>
1614 +#include <asm/rc32434/rc32434.h>
1615 +#include <asm/rc32434/pci.h>
1616 +
1617 +#ifdef CONFIG_PCI
1618 +extern void *rc32434_time_init(void);
1619 +extern int __init rc32434_pcibridge_init(void);
1620 +#endif
1621 +
1622 +#define epldMask ((volatile unsigned char *)0xB900000d)
1623 +
1624 +static void rb_machine_restart(char *command)
1625 +{
1626 + /* just jump to the reset vector */
1627 + * (volatile unsigned *) KSEG1ADDR(0x18008000) = 0x80000001;
1628 + ((void (*)(void))KSEG1ADDR(0x1FC00000u))();
1629 +}
1630 +
1631 +static void rb_machine_halt(void)
1632 +{
1633 + for(;;) continue;
1634 +}
1635 +
1636 +#ifdef CONFIG_CPU_HAS_WB
1637 +void (*__wbflush) (void);
1638 +
1639 +static void rb_write_buffer_flush(void)
1640 +{
1641 + __asm__ __volatile__
1642 + ("sync\n\t" "nop\n\t" "loop: bc0f loop\n\t" "nop\n\t");
1643 +}
1644 +#endif
1645 +
1646 +void __init plat_mem_setup(void)
1647 +{
1648 + unsigned int pciCntlVal;
1649 +
1650 + board_time_init = rc32434_time_init;
1651 +
1652 +#ifdef CONFIG_CPU_HAS_WB
1653 + __wbflush = rb_write_buffer_flush;
1654 +#endif
1655 + _machine_restart = rb_machine_restart;
1656 + _machine_halt = rb_machine_halt;
1657 + /*_machine_power_off = rb_machine_power_halt;*/
1658 + pm_power_off = rb_machine_halt;
1659 +
1660 + set_io_port_base(KSEG1);
1661 +
1662 + pciCntlVal=rc32434_pci->pcic;
1663 + pciCntlVal &= 0xFFFFFF7;
1664 + rc32434_pci->pcic = pciCntlVal;
1665 +
1666 +#ifdef CONFIG_PCI
1667 + /* Enable PCI interrupts in EPLD Mask register */
1668 + *epldMask = 0x0;
1669 + *(epldMask + 1) = 0x0;
1670 +#endif
1671 + write_c0_wired(0);
1672 +}
1673 +
1674 +const char *get_system_type(void)
1675 +{
1676 + return "MIPS RB500";
1677 +}
1678 diff -urN linux.old/arch/mips/rb500/time.c linux.dev/arch/mips/rb500/time.c
1679 --- linux.old/arch/mips/rb500/time.c 1970-01-01 01:00:00.000000000 +0100
1680 +++ linux.dev/arch/mips/rb500/time.c 2006-12-14 04:48:33.000000000 +0100
1681 @@ -0,0 +1,93 @@
1682 +/*
1683 +****************************************************************************
1684 +* Carsten Langgaard, carstenl@mips.com
1685 +* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1686 +*
1687 +***************************************************************************
1688 +*
1689 +* This program is free software; you can distribute it and/or modify it
1690 +* under the terms of the GNU General Public License (Version 2) as
1691 +* published by the Free Software Foundation.
1692 +*
1693 +* This program is distributed in the hope it will be useful, but WITHOUT
1694 +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1695 +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1696 +* for more details.
1697 +*
1698 +* You should have received a copy of the GNU General Public License along
1699 +* with this program; if not, write to the Free Software Foundation, Inc.,
1700 +* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1701 +*
1702 +****************************************************************************
1703 +*
1704 +* Setting up the clock on the MIPS boards.
1705 +*
1706 +****************************************************************************
1707 +* P. Sadik Oct 10, 2003
1708 +*
1709 +* Started change log.
1710 +* mips_counter_frequency is now calculated at run time, based on idt_cpu_freq.
1711 +* Code cleanup
1712 +****************************************************************************
1713 +*/
1714 +
1715 +#include <linux/autoconf.h>
1716 +#include <linux/init.h>
1717 +#include <linux/kernel_stat.h>
1718 +#include <linux/sched.h>
1719 +#include <linux/spinlock.h>
1720 +#include <linux/mc146818rtc.h>
1721 +#include <linux/irq.h>
1722 +#include <linux/timex.h>
1723 +
1724 +#include <asm/mipsregs.h>
1725 +#include <asm/ptrace.h>
1726 +#include <asm/debug.h>
1727 +#include <asm/rc32434/rc32434.h>
1728 +
1729 +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
1730 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
1731 +extern unsigned int mips_hpt_frequency;
1732 +extern unsigned int idt_cpu_freq;
1733 +
1734 +/*
1735 + * Figure out the r4k offset, the amount to increment the compare
1736 + * register for each time tick. There is no RTC available.
1737 + *
1738 + * The RC32434 counts at half the CPU *core* speed.
1739 + */
1740 +static unsigned long __init cal_r4koff(void)
1741 +{
1742 + mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
1743 + return (mips_hpt_frequency / HZ);
1744 +}
1745 +
1746 +
1747 +void __init rc32434_time_init(void)
1748 +{
1749 + unsigned int est_freq, flags;
1750 +
1751 + local_irq_save(flags);
1752 +
1753 + printk("calculating r4koff... ");
1754 + r4k_offset = cal_r4koff();
1755 + printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
1756 +
1757 + est_freq = 2*r4k_offset*HZ;
1758 + est_freq += 5000; /* round */
1759 + est_freq -= est_freq%10000;
1760 + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
1761 + (est_freq%1000000)*100/1000000);
1762 + local_irq_restore(flags);
1763 +}
1764 +
1765 +void __init plat_timer_setup(struct irqaction *irq)
1766 +{
1767 + /* we are using the cpu counter for timer interrupts */
1768 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1769 +
1770 + /* to generate the first timer interrupt */
1771 + r4k_cur = (read_c0_count() + r4k_offset);
1772 + write_c0_compare(r4k_cur);
1773 +}
1774 +
1775 diff -urN linux.old/drivers/mtd/devices/block2mtd.c linux.dev/drivers/mtd/devices/block2mtd.c
1776 --- linux.old/drivers/mtd/devices/block2mtd.c 2006-11-29 22:57:37.000000000 +0100
1777 +++ linux.dev/drivers/mtd/devices/block2mtd.c 2006-12-14 04:09:50.000000000 +0100
1778 @@ -26,7 +26,6 @@
1779 #define ERROR(fmt, args...) printk(KERN_ERR "block2mtd: " fmt "\n" , ## args)
1780 #define INFO(fmt, args...) printk(KERN_INFO "block2mtd: " fmt "\n" , ## args)
1781
1782 -
1783 /* Info for the block device */
1784 struct block2mtd_dev {
1785 struct list_head list;
1786 @@ -106,7 +105,7 @@
1787
1788 while (pages) {
1789 page = page_readahead(mapping, index);
1790 - if (!page)
1791 + if (!page || !page_address(page))
1792 return -ENOMEM;
1793 if (IS_ERR(page))
1794 return PTR_ERR(page);
1795 @@ -287,7 +286,7 @@
1796
1797
1798 /* FIXME: ensure that mtd->size % erase_size == 0 */
1799 -static struct block2mtd_dev *add_device(char *devname, int erase_size)
1800 +static struct block2mtd_dev *add_device(char *devname, int erase_size, char *alias)
1801 {
1802 struct block_device *bdev;
1803 struct block2mtd_dev *dev;
1804 @@ -330,14 +329,15 @@
1805
1806 /* Setup the MTD structure */
1807 /* make the name contain the block device in */
1808 - dev->mtd.name = kmalloc(sizeof("block2mtd: ") + strlen(devname),
1809 + dev->mtd.name = kmalloc(strlen((alias ?: devname)),
1810 GFP_KERNEL);
1811 if (!dev->mtd.name)
1812 goto devinit_err;
1813
1814 - sprintf(dev->mtd.name, "block2mtd: %s", devname);
1815 + strcpy(dev->mtd.name, (alias ?: devname));
1816
1817 dev->mtd.size = dev->blkdev->bd_inode->i_size & PAGE_MASK;
1818 + dev->mtd.size -= dev->mtd.size % erase_size;
1819 dev->mtd.erasesize = erase_size;
1820 dev->mtd.writesize = 1;
1821 dev->mtd.type = MTD_RAM;
1822 @@ -356,7 +356,7 @@
1823 }
1824 list_add(&dev->list, &blkmtd_device_list);
1825 INFO("mtd%d: [%s] erase_size = %dKiB [%d]", dev->mtd.index,
1826 - dev->mtd.name + strlen("blkmtd: "),
1827 + dev->mtd.name,
1828 dev->mtd.erasesize >> 10, dev->mtd.erasesize);
1829 return dev;
1830
1831 @@ -432,7 +432,7 @@
1832 {
1833 char buf[80 + 12]; /* 80 for device, 12 for erase size */
1834 char *str = buf;
1835 - char *token[2];
1836 + char *token[3];
1837 char *name;
1838 size_t erase_size = PAGE_SIZE;
1839 int i, ret;
1840 @@ -443,7 +443,7 @@
1841 strcpy(str, val);
1842 kill_final_newline(str);
1843
1844 - for (i = 0; i < 2; i++)
1845 + for (i = 0; i < 3; i++)
1846 token[i] = strsep(&str, ",");
1847
1848 if (str)
1849 @@ -464,13 +464,13 @@
1850 }
1851 }
1852
1853 - add_device(name, erase_size);
1854 + add_device(name, erase_size, token[2]);
1855
1856 return 0;
1857 }
1858
1859
1860 -static int block2mtd_setup(const char *val, struct kernel_param *kp)
1861 +int block2mtd_setup(const char *val, struct kernel_param *kp)
1862 {
1863 #ifdef MODULE
1864 return block2mtd_setup2(val);
1865 @@ -499,6 +499,7 @@
1866
1867 module_param_call(block2mtd, block2mtd_setup, NULL, NULL, 0200);
1868 MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=<dev>[,<erasesize>]\"");
1869 +EXPORT_SYMBOL(block2mtd_setup);
1870
1871 static int __init block2mtd_init(void)
1872 {
1873 diff -urN linux.old/drivers/pci/Makefile linux.dev/drivers/pci/Makefile
1874 --- linux.old/drivers/pci/Makefile 2006-11-29 22:57:37.000000000 +0100
1875 +++ linux.dev/drivers/pci/Makefile 2006-12-14 04:09:50.000000000 +0100
1876 @@ -16,6 +16,7 @@
1877
1878 # Build the PCI MSI interrupt support
1879 obj-$(CONFIG_PCI_MSI) += msi.o
1880 +obj-$(CONFIG_MIKROTIK_RB500) += setup-irq.o
1881
1882 # Build the Hypertransport interrupt support
1883 obj-$(CONFIG_HT_IRQ) += htirq.o
1884 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
1885 --- linux.old/include/asm-mips/bootinfo.h 2006-11-29 22:57:37.000000000 +0100
1886 +++ linux.dev/include/asm-mips/bootinfo.h 2006-12-14 04:09:50.000000000 +0100
1887 @@ -212,6 +212,8 @@
1888 #define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */
1889 #define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */
1890
1891 +#define MACH_GROUP_MIKROTIK 24 /* Mikrotik Boards */
1892 +
1893 #define CL_SIZE COMMAND_LINE_SIZE
1894
1895 const char *get_system_type(void);
1896 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
1897 --- linux.old/include/asm-mips/cpu.h 2006-11-29 22:57:37.000000000 +0100
1898 +++ linux.dev/include/asm-mips/cpu.h 2006-12-14 04:09:50.000000000 +0100
1899 @@ -200,7 +200,8 @@
1900 #define CPU_SB1A 62
1901 #define CPU_74K 63
1902 #define CPU_R14000 64
1903 -#define CPU_LAST 64
1904 +#define CPU_RC32300 65
1905 +#define CPU_LAST 65
1906
1907 /*
1908 * ISA Level encodings
1909 diff -urN linux.old/include/asm-mips/rc32434/crom.h linux.dev/include/asm-mips/rc32434/crom.h
1910 --- linux.old/include/asm-mips/rc32434/crom.h 1970-01-01 01:00:00.000000000 +0100
1911 +++ linux.dev/include/asm-mips/rc32434/crom.h 2006-12-14 04:09:50.000000000 +0100
1912 @@ -0,0 +1,98 @@
1913 +#ifndef __IDT_CROM_H__
1914 +#define __IDT_CROM_H__
1915 +
1916 +/*******************************************************************************
1917 + *
1918 + * Copyright 2002 Integrated Device Technology, Inc.
1919 + * All rights reserved.
1920 + *
1921 + * Configuration ROM register definitions.
1922 + *
1923 + * File : $Id: crom.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
1924 + *
1925 + * Author : Allen.Stichter@idt.com
1926 + * Date : 20020118
1927 + * Update :
1928 + * $Log: crom.h,v $
1929 + * Revision 1.2 2002/06/06 18:34:03 astichte
1930 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
1931 + *
1932 + * Revision 1.1 2002/05/29 17:33:21 sysarch
1933 + * jba File moved from vcode/include/idt/acacia
1934 + *
1935 + *
1936 + ******************************************************************************/
1937 +
1938 +#include <asm/rc32434/types.h>
1939 +
1940 +enum
1941 +{
1942 + CROM0_PhysicalAddress = 0x100b8000,
1943 + CROM_PhysicalAddress = CROM0_PhysicalAddress,
1944 +
1945 + CROM0_VirtualAddress = 0xb00b8000,
1946 + CROM_VirtualAddress = CROM0_VirtualAddress,
1947 +} ;
1948 +
1949 +typedef struct CROM_s
1950 +{
1951 + U32 cromw0 ; // use CROMW0_
1952 + U32 cromw1 ; // use CROMW1_
1953 + U32 cromw2 ; // use CROMW2_
1954 +} volatile * CROM_t ;
1955 +
1956 +enum
1957 +{
1958 + CROMW0_xloc_b = 0,
1959 + CROMW0_xloc_m = 0x0000003f,
1960 + CROMW0_yloc_b = 8,
1961 + CROMW0_yloc_m = 0x00003f00,
1962 + CROMW0_speed_b = 16,
1963 + CROMW0_speed_m = 0x01ff0000,
1964 + CROMW1_wafer_b = 0,
1965 + CROMW1_wafer_m = 0x0000001f,
1966 + CROMW1_lot_b = 8,
1967 + CROMW1_lot_m = 0x0fffff00,
1968 + CROMW1_fab_b = 28,
1969 + CROMW1_fab_m = 0xf0000000,
1970 + CROMW2_pci_b = 0,
1971 + CROMW2_pci_m = 0x00000001,
1972 + CROMW2_eth0_b = 1,
1973 + CROMW2_eth0_m = 0x00000002,
1974 + CROMW2_eth1_b = 2,
1975 + CROMW2_eth1_m = 0x00000004
1976 + CROMW2_i2c_b = 3,
1977 + CROMW2_i2c_m = 0x00000008,
1978 + CROMW2_rng_b = 4,
1979 + CROMW2_rng_m = 0x00000010,
1980 + CROMW2_se_b = 5,
1981 + CROMW2_se_m = 0x00000020,
1982 + CROMW2_des_b = 6,
1983 + CROMW2_des_m = 0x00000040,
1984 + CROMW2_tdes_b = 7,
1985 + CROMW2_tdes_m = 0x00000080,
1986 + CROMW2_a128_b = 8,
1987 + CROMW2_a128_m = 0x00000100,
1988 + CROMW2_a192_b = 9,
1989 + CROMW2_a192_m = 0x00000200,
1990 + CROMW2_a256_b = 10,
1991 + CROMW2_a256_m = 0x00000400,
1992 + CROMW2_md5_b = 11,
1993 + CROMW2_md5_m = 0x00000800,
1994 + CROMW2_s1_b = 12,
1995 + CROMW2_s1_m = 0x00001000,
1996 + CROMW2_s256_b = 13,
1997 + CROMW2_s256_m = 0x00002000,
1998 + CROMW2_pka_b = 14,
1999 + CROMW2_pka_m = 0x00004000,
2000 + CROMW2_exp_b = 15,
2001 + CROMW2_exp_m = 0x00018000,
2002 + CROMW2_exp_8192_v = 0,
2003 + CROMW2_exp_1536_v = 1,
2004 + CROMW2_exp_1024_v = 2,
2005 + CROMW2_exp_512_v = 3,
2006 + CROMW2_rocfg_b = 17,
2007 + CROMW2_rocfg_m = 0x000e0000,
2008 +} ;
2009 +
2010 +#endif // __IDT_CROM_H__
2011 diff -urN linux.old/include/asm-mips/rc32434/ddr.h linux.dev/include/asm-mips/rc32434/ddr.h
2012 --- linux.old/include/asm-mips/rc32434/ddr.h 1970-01-01 01:00:00.000000000 +0100
2013 +++ linux.dev/include/asm-mips/rc32434/ddr.h 2006-12-14 04:09:50.000000000 +0100
2014 @@ -0,0 +1,175 @@
2015 +#ifndef __IDT_DDR_H__
2016 +#define __IDT_DDR_H__
2017 +
2018 +/*******************************************************************************
2019 + *
2020 + * Copyright 2002 Integrated Device Technology, Inc.
2021 + * All rights reserved.
2022 + *
2023 + * DDR register definition.
2024 + *
2025 + * File : $Id: ddr.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
2026 + *
2027 + * Author : ryan.holmQVist@idt.com
2028 + * Date : 20011005
2029 + * Update :
2030 + * $Log: ddr.h,v $
2031 + * Revision 1.2 2002/06/06 18:34:03 astichte
2032 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2033 + *
2034 + * Revision 1.1 2002/05/29 17:33:21 sysarch
2035 + * jba File moved from vcode/include/idt/acacia
2036 + *
2037 + *
2038 + ******************************************************************************/
2039 +
2040 +#include <asm/rc32434/types.h>
2041 +
2042 +enum
2043 +{
2044 + DDR0_PhysicalAddress = 0x18018000,
2045 + DDR_PhysicalAddress = DDR0_PhysicalAddress, // Default
2046 +
2047 + DDR0_VirtualAddress = 0xb8018000,
2048 + DDR_VirtualAddress = DDR0_VirtualAddress, // Default
2049 +} ;
2050 +
2051 +typedef struct DDR_s
2052 +{
2053 + U32 ddrbase ;
2054 + U32 ddrmask ;
2055 + U32 res1;
2056 + U32 res2;
2057 + U32 ddrc ;
2058 + U32 ddrabase ;
2059 + U32 ddramask ;
2060 + U32 ddramap ;
2061 + U32 ddrcust;
2062 + U32 ddrrdc;
2063 + U32 ddrspare;
2064 +} volatile *DDR_t ;
2065 +
2066 +enum
2067 +{
2068 + DDR0BASE_baseaddr_b = 16,
2069 + DDR0BASE_baseaddr_m = 0xffff0000,
2070 +
2071 + DDR0MASK_mask_b = 16,
2072 + DDR0MASK_mask_m = 0xffff0000,
2073 +
2074 + DDR1BASE_baseaddr_b = 16,
2075 + DDR1BASE_baseaddr_m = 0xffff0000,
2076 +
2077 + DDR1MASK_mask_b = 16,
2078 + DDR1MASK_mask_m = 0xffff0000,
2079 +
2080 + DDRC_ata_b = 5,
2081 + DDRC_ata_m = 0x000000E0,
2082 + DDRC_dbw_b = 8,
2083 + DDRC_dbw_m = 0x00000100,
2084 + DDRC_wr_b = 9,
2085 + DDRC_wr_m = 0x00000600,
2086 + DDRC_ps_b = 11,
2087 + DDRC_ps_m = 0x00001800,
2088 + DDRC_dtype_b = 13,
2089 + DDRC_dtype_m = 0x0000e000,
2090 + DDRC_rfc_b = 16,
2091 + DDRC_rfc_m = 0x000f0000,
2092 + DDRC_rp_b = 20,
2093 + DDRC_rp_m = 0x00300000,
2094 + DDRC_ap_b = 22,
2095 + DDRC_ap_m = 0x00400000,
2096 + DDRC_rcd_b = 23,
2097 + DDRC_rcd_m = 0x01800000,
2098 + DDRC_cl_b = 25,
2099 + DDRC_cl_m = 0x06000000,
2100 + DDRC_dbm_b = 27,
2101 + DDRC_dbm_m = 0x08000000,
2102 + DDRC_sds_b = 28,
2103 + DDRC_sds_m = 0x10000000,
2104 + DDRC_atp_b = 29,
2105 + DDRC_atp_m = 0x60000000,
2106 + DDRC_re_b = 31,
2107 + DDRC_re_m = 0x80000000,
2108 +
2109 + DDRRDC_ces_b = 0,
2110 + DDRRDC_ces_m = 0x00000001,
2111 + DDRRDC_ace_b = 1,
2112 + DDRRDC_ace_m = 0x00000002,
2113 +
2114 + DDRABASE_baseaddr_b = 16,
2115 + DDRABASE_baseaddr_m = 0xffff0000,
2116 +
2117 + DDRAMASK_mask_b = 16,
2118 + DDRAMASK_mask_m = 0xffff0000,
2119 +
2120 + DDRAMAP_map_b = 16,
2121 + DDRAMAP_map_m = 0xffff0000,
2122 +
2123 + DDRCUST_cs_b = 0,
2124 + DDRCUST_cs_m = 0x00000003,
2125 + DDRCUST_we_b = 2,
2126 + DDRCUST_we_m = 0x00000004,
2127 + DDRCUST_ras_b = 3,
2128 + DDRCUST_ras_m = 0x00000008,
2129 + DDRCUST_cas_b = 4,
2130 + DDRCUST_cas_m = 0x00000010,
2131 + DDRCUST_cke_b = 5,
2132 + DDRCUST_cke_m = 0x00000020,
2133 + DDRCUST_ba_b = 6,
2134 + DDRCUST_ba_m = 0x000000c0,
2135 +
2136 + RCOUNT_rcount_b = 0,
2137 + RCOUNT_rcount_m = 0x0000ffff,
2138 +
2139 + RCOMPARE_rcompare_b = 0,
2140 + RCOMPARE_rcompare_m = 0x0000ffff,
2141 +
2142 + RTC_ce_b = 0,
2143 + RTC_ce_m = 0x00000001,
2144 + RTC_to_b = 1,
2145 + RTC_to_m = 0x00000002,
2146 + RTC_rqe_b = 2,
2147 + RTC_rqe_m = 0x00000004,
2148 +
2149 + DDRDQSC_dm_b = 0,
2150 + DDRDQSC_dm_m = 0x00000003,
2151 + DDRDQSC_dqsbs_b = 2,
2152 + DDRDQSC_dqsbs_m = 0x000000fc,
2153 + DDRDQSC_db_b = 8,
2154 + DDRDQSC_db_m = 0x00000100,
2155 + DDRDQSC_dbsp_b = 9,
2156 + DDRDQSC_dbsp_m = 0x01fffe00,
2157 + DDRDQSC_bdp_b = 25,
2158 + DDRDQSC_bdp_m = 0x7e000000,
2159 +
2160 + DDRDLLC_eao_b = 0,
2161 + DDRDLLC_eao_m = 0x00000001,
2162 + DDRDLLC_eo_b = 1,
2163 + DDRDLLC_eo_m = 0x0000003e,
2164 + DDRDLLC_fs_b = 6,
2165 + DDRDLLC_fs_m = 0x000000c0,
2166 + DDRDLLC_as_b = 8,
2167 + DDRDLLC_as_m = 0x00000700,
2168 + DDRDLLC_sp_b = 11,
2169 + DDRDLLC_sp_m = 0x001ff800,
2170 +
2171 + DDRDLLFC_men_b = 0,
2172 + DDRDLLFC_men_m = 0x00000001,
2173 + DDRDLLFC_aen_b = 1,
2174 + DDRDLLFC_aen_m = 0x00000002,
2175 + DDRDLLFC_ff_b = 2,
2176 + DDRDLLFC_ff_m = 0x00000004,
2177 +
2178 + DDRDLLTA_addr_b = 2,
2179 + DDRDLLTA_addr_m = 0xfffffffc,
2180 +
2181 + DDRDLLED_dbe_b = 0,
2182 + DDRDLLED_dbe_m = 0x00000001,
2183 + DDRDLLED_dte_b = 1,
2184 + DDRDLLED_dte_m = 0x00000002,
2185 +
2186 +
2187 +} ;
2188 +
2189 +#endif // __IDT_DDR_H__
2190 diff -urN linux.old/include/asm-mips/rc32434/dev.h linux.dev/include/asm-mips/rc32434/dev.h
2191 --- linux.old/include/asm-mips/rc32434/dev.h 1970-01-01 01:00:00.000000000 +0100
2192 +++ linux.dev/include/asm-mips/rc32434/dev.h 2006-12-14 04:09:50.000000000 +0100
2193 @@ -0,0 +1,134 @@
2194 +#ifndef __IDT_DEV_H__
2195 +#define __IDT_DEV_H__
2196 +
2197 +/*******************************************************************************
2198 + *
2199 + * Copyright 2002 Integrated Device Technology, Inc.
2200 + * All rights reserved.
2201 + *
2202 + * Device Controller register definition.
2203 + *
2204 + * File : $Id: dev.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
2205 + *
2206 + * Author : John.Ahrens@idt.com
2207 + * Date : 200112013
2208 + * Update :
2209 + * $Log: dev.h,v $
2210 + * Revision 1.2 2002/06/06 18:34:03 astichte
2211 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2212 + *
2213 + * Revision 1.1 2002/05/29 17:33:21 sysarch
2214 + * jba File moved from vcode/include/idt/acacia
2215 + *
2216 + *
2217 + ******************************************************************************/
2218 +
2219 +#include <asm/rc32434/types.h>
2220 +
2221 +enum
2222 +{
2223 + DEV0_PhysicalAddress = 0x18010000,
2224 + DEV_PhysicalAddress = DEV0_PhysicalAddress, // Default
2225 +
2226 + DEV0_VirtualAddress = 0xb8010000,
2227 + DEV_VirtualAddress = DEV0_VirtualAddress, // Default
2228 +} ;
2229 +
2230 +typedef struct DEVICE_s
2231 +{
2232 + U32 devbase ; // Device Base
2233 + U32 devmask ; // Device Mask
2234 + U32 devc ; // Device Control
2235 + U32 devtc ; // Device Timing Control
2236 +} volatile *DEVICE_t ;
2237 +
2238 +enum
2239 +{
2240 + DEV_Count = 3,
2241 +} ;
2242 +
2243 +typedef struct DEV_s
2244 +{
2245 + struct DEVICE_s dev [DEV_Count] ;
2246 + U32 btcs ; // Bus timeout control / status
2247 + U32 btcompare ; // Compare
2248 + U32 btaddr ; // Timeout address.
2249 + U32 devdacs ; // Decoupled access control.
2250 + U32 devdaa ; // Decoupled access address.
2251 + U32 devdad ; // Decoupled access address.
2252 + U32 devspare ; // spare.
2253 +} volatile *DEV_t ;
2254 +
2255 +enum
2256 +{
2257 + DEVBASE_baseaddr_b = 16,
2258 + DEVBASE_baseaddr_m = 0xffff0000,
2259 + DEVMASK_mask_b = 16,
2260 + DEVMASK_mask_m = 0xffff0000,
2261 +
2262 + DEVC_ds_b = 0,
2263 + DEVC_ds_m = 0x00000003,
2264 + DEVC_ds_8_v = 0, // 8-bit device.
2265 + DEVC_ds_16_v = 1, // reserved
2266 + DEVC_ds_res_v = 2, // reserved.
2267 + DEVC_ds_res2_v = 3, // reserved.
2268 + DEVC_be_b = 2,
2269 + DEVC_be_m = 0x00000004,
2270 + DEVC_wp_b = 3,
2271 + DEVC_wp_m = 0x00000008,
2272 + DEVC_csd_b = 4,
2273 + DEVC_csd_m = 0x000000f0,
2274 + DEVC_oed_b = 8,
2275 + DEVC_oed_m = 0x00000f00,
2276 + DEVC_bwd_b = 12,
2277 + DEVC_bwd_m = 0x0000f000,
2278 + DEVC_rws_b = 16,
2279 + DEVC_rws_m = 0x003f0000,
2280 + DEVC_wws_b = 22,
2281 + DEVC_wws_m = 0x0fc00000,
2282 + DEVC_bre_b = 28,
2283 + DEVC_bre_m = 0x10000000,
2284 + DEVC_bwe_b = 29,
2285 + DEVC_bwe_m = 0x20000000,
2286 + DEVC_wam_b = 30,
2287 + DEVC_wam_m = 0x40000000,
2288 +
2289 + DEVTC_prd_b = 0,
2290 + DEVTC_prd_m = 0x0000000f,
2291 + DEVTC_pwd_b = 4,
2292 + DEVTC_pwd_m = 0x000000f0,
2293 + DEVTC_wdh_b = 8,
2294 + DEVTC_wdh_m = 0x00000700,
2295 + DEVTC_csh_b = 11,
2296 + DEVTC_csh_m = 0x00001800,
2297 +
2298 + BTCS_tt_b = 0,
2299 + BTCS_tt_m = 0x00000001,
2300 + BTCS_tt_write = 0,
2301 + BTCS_tt_read = 1,
2302 + BTCS_bto_b = 1, // In btcs
2303 + BTCS_bto_m = 0x00000002, // In btcs
2304 + BTCS_bte_b = 2, // In btcs
2305 + BTCS_bte_m = 0x00000004, // In btcs
2306 +
2307 + BTCOMPARE_compare_b = 0, // In btcompare
2308 + BTCOMPARE_compare_m = 0x0000ffff, // In btcompare
2309 +
2310 + DEVDACS_op_b = 0, // In devdacs
2311 + DEVDACS_op_m = 0x00000001, // In devdacs
2312 + DEVDACS_op_write_v = 0,
2313 + DEVDACS_op_read_v = 1,
2314 + DEVDACS_size_b = 1, // In devdacs
2315 + DEVDACS_size_m = 0x00000006, // In devdacs
2316 + DEVDACS_size_byte_v = 0,
2317 + DEVDACS_size_halfword = 1,
2318 + DEVDACS_size_triplebyte = 2,
2319 + DEVDACS_size_word = 3,
2320 + DEVDACS_err_b = 3, // In devdacs
2321 + DEVDACS_err_m = 0x00000008, // In devdacs
2322 + DEVDACS_f_b = 4, // In devdacs
2323 + DEVDACS_f_m = 0x00000010, // In devdacs
2324 +} ;
2325 +
2326 +#endif //__IDT_DEV_H__
2327 +
2328 diff -urN linux.old/include/asm-mips/rc32434/dma.h linux.dev/include/asm-mips/rc32434/dma.h
2329 --- linux.old/include/asm-mips/rc32434/dma.h 1970-01-01 01:00:00.000000000 +0100
2330 +++ linux.dev/include/asm-mips/rc32434/dma.h 2006-12-14 04:09:50.000000000 +0100
2331 @@ -0,0 +1,202 @@
2332 +#ifndef __IDT_DMA_H__
2333 +#define __IDT_DMA_H__
2334 +
2335 +/*******************************************************************************
2336 + *
2337 + * Copyright 2002 Integrated Device Technology, Inc.
2338 + * All rights reserved.
2339 + *
2340 + * DMA register definition.
2341 + *
2342 + * File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
2343 + *
2344 + * Author : ryan.holmQVist@idt.com
2345 + * Date : 20011005
2346 + * Update :
2347 + * $Log: dma.h,v $
2348 + * Revision 1.3 2002/06/06 18:34:03 astichte
2349 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2350 + *
2351 + * Revision 1.2 2002/06/05 18:30:46 astichte
2352 + * Removed IDTField
2353 + *
2354 + * Revision 1.1 2002/05/29 17:33:21 sysarch
2355 + * jba File moved from vcode/include/idt/acacia
2356 + *
2357 + *
2358 + ******************************************************************************/
2359 +
2360 +#include <asm/rc32434/types.h>
2361 +enum
2362 +{
2363 + DMA0_PhysicalAddress = 0x18040000,
2364 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
2365 +
2366 + DMA0_VirtualAddress = 0xb8040000,
2367 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
2368 +} ;
2369 +
2370 +/*
2371 + * DMA descriptor (in physical memory).
2372 + */
2373 +
2374 +typedef struct DMAD_s
2375 +{
2376 + U32 control ; // Control. use DMAD_*
2377 + U32 ca ; // Current Address.
2378 + U32 devcs ; // Device control and status.
2379 + U32 link ; // Next descriptor in chain.
2380 +} volatile *DMAD_t ;
2381 +
2382 +enum
2383 +{
2384 + DMAD_size = sizeof (struct DMAD_s),
2385 + DMAD_count_b = 0, // in DMAD_t -> control
2386 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
2387 + DMAD_ds_b = 20, // in DMAD_t -> control
2388 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
2389 + DMAD_ds_ethRcv_v = 0,
2390 + DMAD_ds_ethXmt_v = 0,
2391 + DMAD_ds_memToFifo_v = 0,
2392 + DMAD_ds_fifoToMem_v = 0,
2393 + DMAD_ds_pciToMem_v = 0,
2394 + DMAD_ds_memToPci_v = 0,
2395 +
2396 + DMAD_devcmd_b = 22, // in DMAD_t -> control
2397 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
2398 + DMAD_devcmd_byte_v = 0, //memory-to-memory
2399 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
2400 + DMAD_devcmd_word_v = 2, //memory-to-memory
2401 + DMAD_devcmd_2words_v = 3, //memory-to-memory
2402 + DMAD_devcmd_4words_v = 4, //memory-to-memory
2403 + DMAD_devcmd_6words_v = 5, //memory-to-memory
2404 + DMAD_devcmd_8words_v = 6, //memory-to-memory
2405 + DMAD_devcmd_16words_v = 7, //memory-to-memory
2406 + DMAD_cof_b = 25, // chain on finished
2407 + DMAD_cof_m = 0x02000000, //
2408 + DMAD_cod_b = 26, // chain on done
2409 + DMAD_cod_m = 0x04000000, //
2410 + DMAD_iof_b = 27, // interrupt on finished
2411 + DMAD_iof_m = 0x08000000, //
2412 + DMAD_iod_b = 28, // interrupt on done
2413 + DMAD_iod_m = 0x10000000, //
2414 + DMAD_t_b = 29, // terminated
2415 + DMAD_t_m = 0x20000000, //
2416 + DMAD_d_b = 30, // done
2417 + DMAD_d_m = 0x40000000, //
2418 + DMAD_f_b = 31, // finished
2419 + DMAD_f_m = 0x80000000, //
2420 +} ;
2421 +
2422 +/*
2423 + * DMA register (within Internal Register Map).
2424 + */
2425 +
2426 +struct DMA_Chan_s
2427 +{
2428 + U32 dmac ; // Control.
2429 + U32 dmas ; // Status.
2430 + U32 dmasm ; // Mask.
2431 + U32 dmadptr ; // Descriptor pointer.
2432 + U32 dmandptr ; // Next descriptor pointer.
2433 +};
2434 +
2435 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
2436 +
2437 +//DMA_Channels use DMACH_count instead
2438 +
2439 +enum
2440 +{
2441 + DMAC_run_b = 0, //
2442 + DMAC_run_m = 0x00000001, //
2443 + DMAC_dm_b = 1, // done mask
2444 + DMAC_dm_m = 0x00000002, //
2445 + DMAC_mode_b = 2, //
2446 + DMAC_mode_m = 0x0000000c, //
2447 + DMAC_mode_auto_v = 0,
2448 + DMAC_mode_burst_v = 1,
2449 + DMAC_mode_transfer_v = 2, //usually used
2450 + DMAC_mode_reserved_v = 3,
2451 + DMAC_a_b = 4, //
2452 + DMAC_a_m = 0x00000010, //
2453 +
2454 + DMAS_f_b = 0, // finished (sticky)
2455 + DMAS_f_m = 0x00000001, //
2456 + DMAS_d_b = 1, // done (sticky)
2457 + DMAS_d_m = 0x00000002, //
2458 + DMAS_c_b = 2, // chain (sticky)
2459 + DMAS_c_m = 0x00000004, //
2460 + DMAS_e_b = 3, // error (sticky)
2461 + DMAS_e_m = 0x00000008, //
2462 + DMAS_h_b = 4, // halt (sticky)
2463 + DMAS_h_m = 0x00000010, //
2464 +
2465 + DMASM_f_b = 0, // finished (1=mask)
2466 + DMASM_f_m = 0x00000001, //
2467 + DMASM_d_b = 1, // done (1=mask)
2468 + DMASM_d_m = 0x00000002, //
2469 + DMASM_c_b = 2, // chain (1=mask)
2470 + DMASM_c_m = 0x00000004, //
2471 + DMASM_e_b = 3, // error (1=mask)
2472 + DMASM_e_m = 0x00000008, //
2473 + DMASM_h_b = 4, // halt (1=mask)
2474 + DMASM_h_m = 0x00000010, //
2475 +} ;
2476 +
2477 +/*
2478 + * DMA channel definitions
2479 + */
2480 +
2481 +enum
2482 +{
2483 + DMACH_ethRcv = 0,
2484 + DMACH_ethXmt = 1,
2485 + DMACH_memToFifo = 2,
2486 + DMACH_fifoToMem = 3,
2487 + DMACH_pciToMem = 4,
2488 + DMACH_memToPci = 5,
2489 +
2490 + DMACH_count //must be last
2491 +};
2492 +
2493 +
2494 +typedef struct DMAC_s
2495 +{
2496 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
2497 +} volatile *DMA_t ;
2498 +
2499 +
2500 +/*
2501 + * External DMA parameters
2502 +*/
2503 +#if 0
2504 +enum
2505 +{
2506 + DMADEVCMD_ts_b = 0, // ts field in devcmd
2507 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
2508 + DMADEVCMD_ts_byte_v = 0,
2509 + DMADEVCMD_ts_halfword_v = 1,
2510 + DMADEVCMD_ts_word_v = 2,
2511 + DMADEVCMD_ts_2word_v = 3,
2512 + DMADEVCMD_ts_4word_v = 4,
2513 + DMADEVCMD_ts_6word_v = 5,
2514 + DMADEVCMD_ts_8word_v = 6,
2515 + DMADEVCMD_ts_16word_v = 7
2516 +};
2517 +#endif
2518 +
2519 +#if 1 // aws - Compatibility.
2520 +# define EXTDMA_ts_b DMADEVCMD_ts_b
2521 +# define EXTDMA_ts_m DMADEVCMD_ts_m
2522 +# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
2523 +# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
2524 +# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
2525 +# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
2526 +# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
2527 +# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
2528 +# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
2529 +# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
2530 +#endif // aws - Compatibility.
2531 +
2532 +#endif // __IDT_DMA_H__
2533 +
2534 diff -urN linux.old/include/asm-mips/rc32434/dma_v.h linux.dev/include/asm-mips/rc32434/dma_v.h
2535 --- linux.old/include/asm-mips/rc32434/dma_v.h 1970-01-01 01:00:00.000000000 +0100
2536 +++ linux.dev/include/asm-mips/rc32434/dma_v.h 2006-12-14 04:09:50.000000000 +0100
2537 @@ -0,0 +1,73 @@
2538 +#ifndef __IDT_DMA_V_H__
2539 +#define __IDT_DMA_V_H__
2540 +
2541 +/*******************************************************************************
2542 + *
2543 + * Copyright 2002 Integrated Device Technology, Inc.
2544 + * All rights reserved.
2545 + *
2546 + * DMA register definition.
2547 + *
2548 + * File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
2549 + *
2550 + * Author : ryan.holmQVist@idt.com
2551 + * Date : 20011005
2552 + * Update :
2553 + * $Log: dma.h,v $
2554 + * Revision 1.3 2002/06/06 18:34:03 astichte
2555 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2556 + *
2557 + * Revision 1.2 2002/06/05 18:30:46 astichte
2558 + * Removed IDTField
2559 + *
2560 + * Revision 1.1 2002/05/29 17:33:21 sysarch
2561 + * jba File moved from vcode/include/idt/acacia
2562 + *
2563 + *
2564 + ******************************************************************************/
2565 +#include <asm/rc32434/types.h>
2566 +#include <asm/rc32434/dma.h>
2567 +#include <asm/rc32434/rc32434.h>
2568 +#define DMA_CHAN_OFFSET 0x14
2569 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
2570 +#define DMA_COUNT(count) \
2571 + ((count) & DMAD_count_m)
2572 +
2573 +#define DMA_HALT_TIMEOUT 500
2574 +
2575 +
2576 +static inline int rc32434_halt_dma(DMA_Chan_t ch)
2577 +{
2578 + int timeout=1;
2579 + if (local_readl(&ch->dmac) & DMAC_run_m) {
2580 + local_writel(0, &ch->dmac);
2581 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
2582 + if (local_readl(&ch->dmas) & DMAS_h_m) {
2583 + local_writel(0, &ch->dmas);
2584 + break;
2585 + }
2586 + }
2587 + }
2588 +
2589 + return timeout ? 0 : 1;
2590 +}
2591 +
2592 +static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
2593 +{
2594 + local_writel(0, &ch->dmandptr);
2595 + local_writel(dma_addr, &ch->dmadptr);
2596 +}
2597 +
2598 +static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
2599 +{
2600 + local_writel(dma_addr, &ch->dmandptr);
2601 +}
2602 +
2603 +#endif // __IDT_DMA_V_H__
2604 +
2605 +
2606 +
2607 +
2608 +
2609 +
2610 +
2611 diff -urN linux.old/include/asm-mips/rc32434/eth.h linux.dev/include/asm-mips/rc32434/eth.h
2612 --- linux.old/include/asm-mips/rc32434/eth.h 1970-01-01 01:00:00.000000000 +0100
2613 +++ linux.dev/include/asm-mips/rc32434/eth.h 2006-12-14 04:09:50.000000000 +0100
2614 @@ -0,0 +1,322 @@
2615 +#ifndef __IDT_ETH_H__
2616 +#define __IDT_ETH_H__
2617 +
2618 +/*******************************************************************************
2619 + *
2620 + * Copyright 2002 Integrated Device Technology, Inc.
2621 + * All rights reserved.
2622 + *
2623 + * Ethernet register definition.
2624 + *
2625 + * File : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
2626 + *
2627 + * Author : Allen.Stichter@idt.com
2628 + * Date : 20020605
2629 + * Update :
2630 + * $Log: eth.h,v $
2631 + * Revision 1.3 2002/06/06 18:34:04 astichte
2632 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2633 + *
2634 + * Revision 1.2 2002/06/05 18:19:46 astichte
2635 + * Added
2636 + *
2637 + * Revision 1.1 2002/05/29 17:33:22 sysarch
2638 + * jba File moved from vcode/include/idt/acacia
2639 + *
2640 + ******************************************************************************/
2641 +
2642 +#include <asm/rc32434/types.h>
2643 +
2644 +enum
2645 +{
2646 + ETH0_PhysicalAddress = 0x18060000,
2647 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
2648 +
2649 + ETH0_VirtualAddress = 0xb8060000,
2650 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
2651 +} ;
2652 +
2653 +typedef struct
2654 +{
2655 + U32 ethintfc ;
2656 + U32 ethfifott ;
2657 + U32 etharc ;
2658 + U32 ethhash0 ;
2659 + U32 ethhash1 ;
2660 + U32 ethu0 [4] ; // Reserved.
2661 + U32 ethpfs ;
2662 + U32 ethmcp ;
2663 + U32 eth_u1 [10] ; // Reserved.
2664 + U32 ethspare ;
2665 + U32 eth_u2 [42] ; // Reserved.
2666 + U32 ethsal0 ;
2667 + U32 ethsah0 ;
2668 + U32 ethsal1 ;
2669 + U32 ethsah1 ;
2670 + U32 ethsal2 ;
2671 + U32 ethsah2 ;
2672 + U32 ethsal3 ;
2673 + U32 ethsah3 ;
2674 + U32 ethrbc ;
2675 + U32 ethrpc ;
2676 + U32 ethrupc ;
2677 + U32 ethrfc ;
2678 + U32 ethtbc ;
2679 + U32 ethgpf ;
2680 + U32 eth_u9 [50] ; // Reserved.
2681 + U32 ethmac1 ;
2682 + U32 ethmac2 ;
2683 + U32 ethipgt ;
2684 + U32 ethipgr ;
2685 + U32 ethclrt ;
2686 + U32 ethmaxf ;
2687 + U32 eth_u10 ; // Reserved.
2688 + U32 ethmtest ;
2689 + U32 miimcfg ;
2690 + U32 miimcmd ;
2691 + U32 miimaddr ;
2692 + U32 miimwtd ;
2693 + U32 miimrdd ;
2694 + U32 miimind ;
2695 + U32 eth_u11 ; // Reserved.
2696 + U32 eth_u12 ; // Reserved.
2697 + U32 ethcfsa0 ;
2698 + U32 ethcfsa1 ;
2699 + U32 ethcfsa2 ;
2700 +} volatile *ETH_t;
2701 +
2702 +enum
2703 +{
2704 + ETHINTFC_en_b = 0,
2705 + ETHINTFC_en_m = 0x00000001,
2706 + ETHINTFC_its_b = 1,
2707 + ETHINTFC_its_m = 0x00000002,
2708 + ETHINTFC_rip_b = 2,
2709 + ETHINTFC_rip_m = 0x00000004,
2710 + ETHINTFC_jam_b = 3,
2711 + ETHINTFC_jam_m = 0x00000008,
2712 + ETHINTFC_ovr_b = 4,
2713 + ETHINTFC_ovr_m = 0x00000010,
2714 + ETHINTFC_und_b = 5,
2715 + ETHINTFC_und_m = 0x00000020,
2716 + ETHINTFC_iom_b = 6,
2717 + ETHINTFC_iom_m = 0x000000c0,
2718 +
2719 + ETHFIFOTT_tth_b = 0,
2720 + ETHFIFOTT_tth_m = 0x0000007f,
2721 +
2722 + ETHARC_pro_b = 0,
2723 + ETHARC_pro_m = 0x00000001,
2724 + ETHARC_am_b = 1,
2725 + ETHARC_am_m = 0x00000002,
2726 + ETHARC_afm_b = 2,
2727 + ETHARC_afm_m = 0x00000004,
2728 + ETHARC_ab_b = 3,
2729 + ETHARC_ab_m = 0x00000008,
2730 +
2731 + ETHSAL_byte5_b = 0,
2732 + ETHSAL_byte5_m = 0x000000ff,
2733 + ETHSAL_byte4_b = 8,
2734 + ETHSAL_byte4_m = 0x0000ff00,
2735 + ETHSAL_byte3_b = 16,
2736 + ETHSAL_byte3_m = 0x00ff0000,
2737 + ETHSAL_byte2_b = 24,
2738 + ETHSAL_byte2_m = 0xff000000,
2739 +
2740 + ETHSAH_byte1_b = 0,
2741 + ETHSAH_byte1_m = 0x000000ff,
2742 + ETHSAH_byte0_b = 8,
2743 + ETHSAH_byte0_m = 0x0000ff00,
2744 +
2745 + ETHGPF_ptv_b = 0,
2746 + ETHGPF_ptv_m = 0x0000ffff,
2747 +
2748 + ETHPFS_pfd_b = 0,
2749 + ETHPFS_pfd_m = 0x00000001,
2750 +
2751 + ETHCFSA0_cfsa4_b = 0,
2752 + ETHCFSA0_cfsa4_m = 0x000000ff,
2753 + ETHCFSA0_cfsa5_b = 8,
2754 + ETHCFSA0_cfsa5_m = 0x0000ff00,
2755 +
2756 + ETHCFSA1_cfsa2_b = 0,
2757 + ETHCFSA1_cfsa2_m = 0x000000ff,
2758 + ETHCFSA1_cfsa3_b = 8,
2759 + ETHCFSA1_cfsa3_m = 0x0000ff00,
2760 +
2761 + ETHCFSA2_cfsa0_b = 0,
2762 + ETHCFSA2_cfsa0_m = 0x000000ff,
2763 + ETHCFSA2_cfsa1_b = 8,
2764 + ETHCFSA2_cfsa1_m = 0x0000ff00,
2765 +
2766 + ETHMAC1_re_b = 0,
2767 + ETHMAC1_re_m = 0x00000001,
2768 + ETHMAC1_paf_b = 1,
2769 + ETHMAC1_paf_m = 0x00000002,
2770 + ETHMAC1_rfc_b = 2,
2771 + ETHMAC1_rfc_m = 0x00000004,
2772 + ETHMAC1_tfc_b = 3,
2773 + ETHMAC1_tfc_m = 0x00000008,
2774 + ETHMAC1_lb_b = 4,
2775 + ETHMAC1_lb_m = 0x00000010,
2776 + ETHMAC1_mr_b = 31,
2777 + ETHMAC1_mr_m = 0x80000000,
2778 +
2779 + ETHMAC2_fd_b = 0,
2780 + ETHMAC2_fd_m = 0x00000001,
2781 + ETHMAC2_flc_b = 1,
2782 + ETHMAC2_flc_m = 0x00000002,
2783 + ETHMAC2_hfe_b = 2,
2784 + ETHMAC2_hfe_m = 0x00000004,
2785 + ETHMAC2_dc_b = 3,
2786 + ETHMAC2_dc_m = 0x00000008,
2787 + ETHMAC2_cen_b = 4,
2788 + ETHMAC2_cen_m = 0x00000010,
2789 + ETHMAC2_pe_b = 5,
2790 + ETHMAC2_pe_m = 0x00000020,
2791 + ETHMAC2_vpe_b = 6,
2792 + ETHMAC2_vpe_m = 0x00000040,
2793 + ETHMAC2_ape_b = 7,
2794 + ETHMAC2_ape_m = 0x00000080,
2795 + ETHMAC2_ppe_b = 8,
2796 + ETHMAC2_ppe_m = 0x00000100,
2797 + ETHMAC2_lpe_b = 9,
2798 + ETHMAC2_lpe_m = 0x00000200,
2799 + ETHMAC2_nb_b = 12,
2800 + ETHMAC2_nb_m = 0x00001000,
2801 + ETHMAC2_bp_b = 13,
2802 + ETHMAC2_bp_m = 0x00002000,
2803 + ETHMAC2_ed_b = 14,
2804 + ETHMAC2_ed_m = 0x00004000,
2805 +
2806 + ETHIPGT_ipgt_b = 0,
2807 + ETHIPGT_ipgt_m = 0x0000007f,
2808 +
2809 + ETHIPGR_ipgr2_b = 0,
2810 + ETHIPGR_ipgr2_m = 0x0000007f,
2811 + ETHIPGR_ipgr1_b = 8,
2812 + ETHIPGR_ipgr1_m = 0x00007f00,
2813 +
2814 + ETHCLRT_maxret_b = 0,
2815 + ETHCLRT_maxret_m = 0x0000000f,
2816 + ETHCLRT_colwin_b = 8,
2817 + ETHCLRT_colwin_m = 0x00003f00,
2818 +
2819 + ETHMAXF_maxf_b = 0,
2820 + ETHMAXF_maxf_m = 0x0000ffff,
2821 +
2822 + ETHMTEST_tb_b = 2,
2823 + ETHMTEST_tb_m = 0x00000004,
2824 +
2825 + ETHMCP_div_b = 0,
2826 + ETHMCP_div_m = 0x000000ff,
2827 +
2828 + MIIMCFG_rsv_b = 0,
2829 + MIIMCFG_rsv_m = 0x0000000c,
2830 +
2831 + MIIMCMD_rd_b = 0,
2832 + MIIMCMD_rd_m = 0x00000001,
2833 + MIIMCMD_scn_b = 1,
2834 + MIIMCMD_scn_m = 0x00000002,
2835 +
2836 + MIIMADDR_regaddr_b = 0,
2837 + MIIMADDR_regaddr_m = 0x0000001f,
2838 + MIIMADDR_phyaddr_b = 8,
2839 + MIIMADDR_phyaddr_m = 0x00001f00,
2840 +
2841 + MIIMWTD_wdata_b = 0,
2842 + MIIMWTD_wdata_m = 0x0000ffff,
2843 +
2844 + MIIMRDD_rdata_b = 0,
2845 + MIIMRDD_rdata_m = 0x0000ffff,
2846 +
2847 + MIIMIND_bsy_b = 0,
2848 + MIIMIND_bsy_m = 0x00000001,
2849 + MIIMIND_scn_b = 1,
2850 + MIIMIND_scn_m = 0x00000002,
2851 + MIIMIND_nv_b = 2,
2852 + MIIMIND_nv_m = 0x00000004,
2853 +
2854 +} ;
2855 +
2856 +/*
2857 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
2858 + */
2859 +enum
2860 +{
2861 + ETHRX_fd_b = 0,
2862 + ETHRX_fd_m = 0x00000001,
2863 + ETHRX_ld_b = 1,
2864 + ETHRX_ld_m = 0x00000002,
2865 + ETHRX_rok_b = 2,
2866 + ETHRX_rok_m = 0x00000004,
2867 + ETHRX_fm_b = 3,
2868 + ETHRX_fm_m = 0x00000008,
2869 + ETHRX_mp_b = 4,
2870 + ETHRX_mp_m = 0x00000010,
2871 + ETHRX_bp_b = 5,
2872 + ETHRX_bp_m = 0x00000020,
2873 + ETHRX_vlt_b = 6,
2874 + ETHRX_vlt_m = 0x00000040,
2875 + ETHRX_cf_b = 7,
2876 + ETHRX_cf_m = 0x00000080,
2877 + ETHRX_ovr_b = 8,
2878 + ETHRX_ovr_m = 0x00000100,
2879 + ETHRX_crc_b = 9,
2880 + ETHRX_crc_m = 0x00000200,
2881 + ETHRX_cv_b = 10,
2882 + ETHRX_cv_m = 0x00000400,
2883 + ETHRX_db_b = 11,
2884 + ETHRX_db_m = 0x00000800,
2885 + ETHRX_le_b = 12,
2886 + ETHRX_le_m = 0x00001000,
2887 + ETHRX_lor_b = 13,
2888 + ETHRX_lor_m = 0x00002000,
2889 + ETHRX_ces_b = 14,
2890 + ETHRX_ces_m = 0x00004000,
2891 + ETHRX_length_b = 16,
2892 + ETHRX_length_m = 0xffff0000,
2893 +
2894 + ETHTX_fd_b = 0,
2895 + ETHTX_fd_m = 0x00000001,
2896 + ETHTX_ld_b = 1,
2897 + ETHTX_ld_m = 0x00000002,
2898 + ETHTX_oen_b = 2,
2899 + ETHTX_oen_m = 0x00000004,
2900 + ETHTX_pen_b = 3,
2901 + ETHTX_pen_m = 0x00000008,
2902 + ETHTX_cen_b = 4,
2903 + ETHTX_cen_m = 0x00000010,
2904 + ETHTX_hen_b = 5,
2905 + ETHTX_hen_m = 0x00000020,
2906 + ETHTX_tok_b = 6,
2907 + ETHTX_tok_m = 0x00000040,
2908 + ETHTX_mp_b = 7,
2909 + ETHTX_mp_m = 0x00000080,
2910 + ETHTX_bp_b = 8,
2911 + ETHTX_bp_m = 0x00000100,
2912 + ETHTX_und_b = 9,
2913 + ETHTX_und_m = 0x00000200,
2914 + ETHTX_of_b = 10,
2915 + ETHTX_of_m = 0x00000400,
2916 + ETHTX_ed_b = 11,
2917 + ETHTX_ed_m = 0x00000800,
2918 + ETHTX_ec_b = 12,
2919 + ETHTX_ec_m = 0x00001000,
2920 + ETHTX_lc_b = 13,
2921 + ETHTX_lc_m = 0x00002000,
2922 + ETHTX_td_b = 14,
2923 + ETHTX_td_m = 0x00004000,
2924 + ETHTX_crc_b = 15,
2925 + ETHTX_crc_m = 0x00008000,
2926 + ETHTX_le_b = 16,
2927 + ETHTX_le_m = 0x00010000,
2928 + ETHTX_cc_b = 17,
2929 + ETHTX_cc_m = 0x001E0000,
2930 +} ;
2931 +
2932 +#endif // __IDT_ETH_H__
2933 +
2934 +
2935 +
2936 +
2937 diff -urN linux.old/include/asm-mips/rc32434/eth_v.h linux.dev/include/asm-mips/rc32434/eth_v.h
2938 --- linux.old/include/asm-mips/rc32434/eth_v.h 1970-01-01 01:00:00.000000000 +0100
2939 +++ linux.dev/include/asm-mips/rc32434/eth_v.h 2006-12-14 04:09:50.000000000 +0100
2940 @@ -0,0 +1,64 @@
2941 +#ifndef __IDT_ETH_V_H__
2942 +#define __IDT_ETH_V_H__
2943 +
2944 +/*******************************************************************************
2945 + *
2946 + * Copyright 2002 Integrated Device Technology, Inc.
2947 + * All rights reserved.
2948 + *
2949 + * Ethernet register definition.
2950 + *
2951 + * File : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
2952 + *
2953 + * Author : Allen.Stichter@idt.com
2954 + * Date : 20020605
2955 + * Update :
2956 + * $Log: eth.h,v $
2957 + * Revision 1.3 2002/06/06 18:34:04 astichte
2958 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2959 + *
2960 + * Revision 1.2 2002/06/05 18:19:46 astichte
2961 + * Added
2962 + *
2963 + * Revision 1.1 2002/05/29 17:33:22 sysarch
2964 + * jba File moved from vcode/include/idt/acacia
2965 + *
2966 + ******************************************************************************/
2967 +
2968 +#include <asm/rc32434/types.h>
2969 +#include <asm/rc32434/eth.h>
2970 +
2971 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
2972 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
2973 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
2974 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
2975 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
2976 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
2977 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
2978 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
2979 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
2980 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
2981 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
2982 +
2983 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
2984 +
2985 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
2986 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
2987 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
2988 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
2989 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
2990 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
2991 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
2992 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
2993 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
2994 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
2995 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
2996 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
2997 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
2998 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
2999 +#endif // __IDT_ETH_V_H__
3000 +
3001 +
3002 +
3003 +
3004 +
3005 diff -urN linux.old/include/asm-mips/rc32434/gpio.h linux.dev/include/asm-mips/rc32434/gpio.h
3006 --- linux.old/include/asm-mips/rc32434/gpio.h 1970-01-01 01:00:00.000000000 +0100
3007 +++ linux.dev/include/asm-mips/rc32434/gpio.h 2006-12-14 04:09:50.000000000 +0100
3008 @@ -0,0 +1,182 @@
3009 +#ifndef __IDT_GPIO_H__
3010 +#define __IDT_GPIO_H__
3011 +
3012 +/*******************************************************************************
3013 + *
3014 + * Copyright 2002 Integrated Device Technology, Inc.
3015 + * All rights reserved.
3016 + *
3017 + * GPIO register definition.
3018 + *
3019 + * File : $Id: gpio.h,v 1.2 2002/06/06 18:34:04 astichte Exp $
3020 + *
3021 + * Author : ryan.holmQVist@idt.com
3022 + * Date : 20011005
3023 + * Update :
3024 + * $Log: gpio.h,v $
3025 + * Revision 1.2 2002/06/06 18:34:04 astichte
3026 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
3027 + *
3028 + * Revision 1.1 2002/05/29 17:33:22 sysarch
3029 + * jba File moved from vcode/include/idt/acacia
3030 + *
3031 + *
3032 + ******************************************************************************/
3033 +
3034 +#include <asm/rc32434/types.h>
3035 +enum
3036 +{
3037 + GPIO0_PhysicalAddress = 0x18050000,
3038 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
3039 +
3040 + GPIO0_VirtualAddress = 0xb8050000,
3041 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
3042 +} ;
3043 +
3044 +typedef struct
3045 +{
3046 + U32 gpiofunc; /* GPIO Function Register
3047 + * gpiofunc[x]==0 bit = gpio
3048 + * func[x]==1 bit = altfunc
3049 + */
3050 + U32 gpiocfg; /* GPIO Configuration Register
3051 + * gpiocfg[x]==0 bit = input
3052 + * gpiocfg[x]==1 bit = output
3053 + */
3054 + U32 gpiod; /* GPIO Data Register
3055 + * gpiod[x] read/write gpio pinX status
3056 + */
3057 + U32 gpioilevel; /* GPIO Interrupt Status Register
3058 + * interrupt level (see gpioistat)
3059 + */
3060 + U32 gpioistat; /* Gpio Interrupt Status Register
3061 + * istat[x] = (gpiod[x] == level[x])
3062 + * cleared in ISR (STICKY bits)
3063 + */
3064 + U32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
3065 +} volatile * GPIO_t ;
3066 +
3067 +typedef enum
3068 +{
3069 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
3070 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
3071 + GPIO_input_v = 0, // gpiocfg use pin as input.
3072 + GPIO_output_v = 1, // gpiocfg use pin as output.
3073 + GPIO_pin0_b = 0,
3074 + GPIO_pin0_m = 0x00000001,
3075 + GPIO_pin1_b = 1,
3076 + GPIO_pin1_m = 0x00000002,
3077 + GPIO_pin2_b = 2,
3078 + GPIO_pin2_m = 0x00000004,
3079 + GPIO_pin3_b = 3,
3080 + GPIO_pin3_m = 0x00000008,
3081 + GPIO_pin4_b = 4,
3082 + GPIO_pin4_m = 0x00000010,
3083 + GPIO_pin5_b = 5,
3084 + GPIO_pin5_m = 0x00000020,
3085 + GPIO_pin6_b = 6,
3086 + GPIO_pin6_m = 0x00000040,
3087 + GPIO_pin7_b = 7,
3088 + GPIO_pin7_m = 0x00000080,
3089 + GPIO_pin8_b = 8,
3090 + GPIO_pin8_m = 0x00000100,
3091 + GPIO_pin9_b = 9,
3092 + GPIO_pin9_m = 0x00000200,
3093 + GPIO_pin10_b = 10,
3094 + GPIO_pin10_m = 0x00000400,
3095 + GPIO_pin11_b = 11,
3096 + GPIO_pin11_m = 0x00000800,
3097 + GPIO_pin12_b = 12,
3098 + GPIO_pin12_m = 0x00001000,
3099 + GPIO_pin13_b = 13,
3100 + GPIO_pin13_m = 0x00002000,
3101 + GPIO_pin14_b = 14,
3102 + GPIO_pin14_m = 0x00004000,
3103 + GPIO_pin15_b = 15,
3104 + GPIO_pin15_m = 0x00008000,
3105 + GPIO_pin16_b = 16,
3106 + GPIO_pin16_m = 0x00010000,
3107 + GPIO_pin17_b = 17,
3108 + GPIO_pin17_m = 0x00020000,
3109 + GPIO_pin18_b = 18,
3110 + GPIO_pin18_m = 0x00040000,
3111 + GPIO_pin19_b = 19,
3112 + GPIO_pin19_m = 0x00080000,
3113 + GPIO_pin20_b = 20,
3114 + GPIO_pin20_m = 0x00100000,
3115 + GPIO_pin21_b = 21,
3116 + GPIO_pin21_m = 0x00200000,
3117 + GPIO_pin22_b = 22,
3118 + GPIO_pin22_m = 0x00400000,
3119 + GPIO_pin23_b = 23,
3120 + GPIO_pin23_m = 0x00800000,
3121 + GPIO_pin24_b = 24,
3122 + GPIO_pin24_m = 0x01000000,
3123 + GPIO_pin25_b = 25,
3124 + GPIO_pin25_m = 0x02000000,
3125 + GPIO_pin26_b = 26,
3126 + GPIO_pin26_m = 0x04000000,
3127 + GPIO_pin27_b = 27,
3128 + GPIO_pin27_m = 0x08000000,
3129 + GPIO_pin28_b = 28,
3130 + GPIO_pin28_m = 0x10000000,
3131 + GPIO_pin29_b = 29,
3132 + GPIO_pin29_m = 0x20000000,
3133 + GPIO_pin30_b = 30,
3134 + GPIO_pin30_m = 0x40000000,
3135 + GPIO_pin31_b = 31,
3136 + GPIO_pin31_m = 0x80000000,
3137 +
3138 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
3139 +
3140 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
3141 + GPIO_u0sout_m = GPIO_pin0_m,
3142 + GPIO_u0sout_cfg_v = GPIO_output_v,
3143 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
3144 + GPIO_u0sinp_m = GPIO_pin1_m,
3145 + GPIO_u0sinp_cfg_v = GPIO_input_v,
3146 + GPIO_u0rtsn_b = GPIO_pin2_b, // UART 0 req. to send.
3147 + GPIO_u0rtsn_m = GPIO_pin2_m,
3148 + GPIO_u0rtsn_cfg_v = GPIO_output_v,
3149 + GPIO_u0ctsn_b = GPIO_pin3_b, // UART 0 clear to send.
3150 + GPIO_u0ctsn_m = GPIO_pin3_m,
3151 + GPIO_u0ctsn_cfg_v = GPIO_input_v,
3152 + GPIO_maddr22_b = GPIO_pin4_b, // M&P bus bit 22.
3153 + GPIO_maddr22_m = GPIO_pin4_m,
3154 + GPIO_maddr22_cfg_v = GPIO_output_v,
3155 +
3156 + GPIO_maddr23_b = GPIO_pin5_b, // M&P bus bit 23.
3157 + GPIO_maddr23_m = GPIO_pin5_m,
3158 + GPIO_maddr23_cfg_v = GPIO_output_v,
3159 +
3160 + GPIO_maddr24_b = GPIO_pin6_b, // M&P bus bit 24.
3161 + GPIO_maddr24_m = GPIO_pin6_m,
3162 + GPIO_maddr24_cfg_v = GPIO_output_v,
3163 +
3164 + GPIO_maddr25_b = GPIO_pin7_b, // M&P bus bit 25.
3165 + GPIO_maddr25_m = GPIO_pin7_m,
3166 + GPIO_maddr25_cfg_v = GPIO_output_v,
3167 +
3168 + GPIO_cpu_b = GPIO_pin8_b, // M&P bus bit 25.
3169 + GPIO_cpu_m = GPIO_pin8_m,
3170 + GPIO_cpu_cfg_v = GPIO_output_v,
3171 + GPIO_afspare6_b = GPIO_pin9_b, // reserved.
3172 + GPIO_afspare6_m = GPIO_pin9_m,
3173 + GPIO_afspare6_cfg_v = GPIO_input_v,
3174 + GPIO_afspare4_b = GPIO_pin10_b, // reserved.
3175 + GPIO_afspare4_m = GPIO_pin10_m,
3176 + GPIO_afspare4_cfg_v = GPIO_input_v,
3177 + GPIO_afspare3_b = GPIO_pin11_b, // reserved.
3178 + GPIO_afspare3_m = GPIO_pin11_m,
3179 + GPIO_afspare3_cfg_v = GPIO_input_v,
3180 + GPIO_afspare2_b = GPIO_pin12_b, // reserved.
3181 + GPIO_afspare2_m = GPIO_pin12_m,
3182 + GPIO_afspare2_cfg_v = GPIO_input_v,
3183 + GPIO_pcimuintn_b = GPIO_pin13_b, // PCI messaging int.
3184 + GPIO_pcimuintn_m = GPIO_pin13_m,
3185 + GPIO_pcimuintn_cfg_v = GPIO_output_v,
3186 +
3187 +} GPIO_DEFS_t;
3188 +
3189 +#endif // __IDT_GPIO_H__
3190 +
3191 diff -urN linux.old/include/asm-mips/rc32434/i2c.h linux.dev/include/asm-mips/rc32434/i2c.h
3192 --- linux.old/include/asm-mips/rc32434/i2c.h 1970-01-01 01:00:00.000000000 +0100
3193 +++ linux.dev/include/asm-mips/rc32434/i2c.h 2006-12-14 04:09:50.000000000 +0100
3194 @@ -0,0 +1,147 @@
3195 +#ifndef __IDT_I2C_H__
3196 +#define __IDT_I2C_H__
3197 +
3198 +/*******************************************************************************
3199 + *
3200 + * Copyright 2002 Integrated Device Technology, Inc.
3201 + * All rights reserved.
3202 + *
3203 + * I2C register definitions.
3204 + *
3205 + * File : $Id: i2c.h,v 1.2 2002/06/06 18:34:04 astichte Exp $
3206 + *
3207 + * Author : Allen.Stichter@idt.com
3208 + * Date : 20020120
3209 + * Update :
3210 + * $Log: i2c.h,v $
3211 + * Revision 1.2 2002/06/06 18:34:04 astichte
3212 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
3213 + *
3214 + * Revision 1.1 2002/05/29 17:33:22 sysarch
3215 + * jba File moved from vcode/include/idt/acacia
3216 + *
3217 + *
3218 + ******************************************************************************/
3219 +
3220 +#include <asm/rc32434/types.h>
3221 +
3222 +enum
3223 +{
3224 + I2C0_PhysicalAddress = 0x18068000,
3225 + I2C_PhysicalAddress = I2C0_PhysicalAddress,
3226 +
3227 + I2C0_VirtualAddress = 0xb8068000,
3228 + I2C_VirtualAddress = I2C0_VirtualAddress,
3229 +} ;
3230 +
3231 +typedef struct
3232 +{
3233 + U32 i2cc ;
3234 + U32 i2cdi ;
3235 + U32 i2cdo ;
3236 + U32 i2ccp ; // I2C clk = ICLK / div / 8
3237 + U32 i2cmcmd ;
3238 + U32 i2cms ;
3239 + U32 i2cmsm ;
3240 + U32 i2css ;
3241 + U32 i2cssm ;
3242 + U32 i2csaddr ;
3243 + U32 i2csack ;
3244 +} volatile * I2C_t ;
3245 +enum
3246 +{
3247 + I2CC_men_b = 0, // In I2C-> i2cc
3248 + I2CC_men_m = 0x00000001,
3249 + I2CC_sen_b = 1, // In I2C-> i2cc
3250 + I2CC_sen_m = 0x00000002,
3251 + I2CC_iom_b = 2, // In I2C-> i2cc
3252 + I2CC_iom_m = 0x00000004,
3253 +
3254 + I2CDI_data_b = 0, // In I2C-> i2cdi
3255 + I2CDI_data_m = 0x000000ff,
3256 +
3257 + I2CDO_data_b = 0, // In I2C-> i2cdo
3258 + I2CDO_data_m = 0x000000ff,
3259 +
3260 + I2CCP_div_b = 0, // In I2C-> i2ccp
3261 + I2CCP_div_m = 0x0000ffff,
3262 +
3263 + I2CMCMD_cmd_b = 0, // In I2C-> i2cmcmd
3264 + I2CMCMD_cmd_m = 0x0000000f,
3265 + I2CMCMD_cmd_nop_v = 0,
3266 + I2CMCMD_cmd_start_v = 1,
3267 + I2CMCMD_cmd_stop_v = 2,
3268 + I2CMCMD_cmd_res3_v = 3,
3269 + I2CMCMD_cmd_rd_v = 4,
3270 + I2CMCMD_cmd_rdack_v = 5,
3271 + I2CMCMD_cmd_wd_v = 6,
3272 + I2CMCMD_cmd_wdack_v = 7,
3273 + I2CMCMD_cmd_res8_v = 8,
3274 + I2CMCMD_cmd_res9_v = 9,
3275 + I2CMCMD_cmd_res10_v = 10,
3276 + I2CMCMD_cmd_res11_v = 11,
3277 + I2CMCMD_cmd_res12_v = 12,
3278 + I2CMCMD_cmd_res13_v = 13,
3279 + I2CMCMD_cmd_res14_v = 14,
3280 + I2CMCMD_cmd_res15_v = 15,
3281 +
3282 + I2CMS_d_b = 0, // In I2C-> i2cms
3283 + I2CMS_d_m = 0x00000001,
3284 + I2CMS_na_b = 1, // In I2C-> i2cms
3285 + I2CMS_na_m = 0x00000002,
3286 + I2CMS_la_b = 2, // In I2C-> i2cms
3287 + I2CMS_la_m = 0x00000004,
3288 + I2CMS_err_b = 3, // In I2C-> i2cms
3289 + I2CMS_err_m = 0x00000008,
3290 +
3291 + I2CMSM_d_b = 0, // In I2C-> i2cmsm
3292 + I2CMSM_d_m = 0x00000001,
3293 + I2CMSM_na_b = 1, // In I2C-> i2cmsm
3294 + I2CMSM_na_m = 0x00000002,
3295 + I2CMSM_la_b = 2, // In I2C-> i2cmsm
3296 + I2CMSM_la_m = 0x00000004,
3297 + I2CMSM_err_b = 3, // In I2C-> i2cmsm
3298 + I2CMSM_err_m = 0x00000008,
3299 +
3300 + I2CSS_rr_b = 0, // In I2C-> i2css
3301 + I2CSS_rr_m = 0x00000001,
3302 + I2CSS_wr_b = 1, // In I2C-> i2css
3303 + I2CSS_wr_m = 0x00000002,
3304 + I2CSS_sa_b = 2, // In I2C-> i2css
3305 + I2CSS_sa_m = 0x00000004,
3306 + I2CSS_tf_b = 3, // In I2C-> i2css
3307 + I2CSS_tf_m = 0x00000008,
3308 + I2CSS_gc_b = 4, // In I2C-> i2css
3309 + I2CSS_gc_m = 0x00000010,
3310 + I2CSS_na_b = 5, // In I2C-> i2css
3311 + I2CSS_na_m = 0x00000020,
3312 + I2CSS_err_b = 6, // In I2C-> i2css
3313 + I2CSS_err_m = 0x00000040,
3314 +
3315 + I2CSSM_rr_b = 0, // In I2C-> i2cssm
3316 + I2CSSM_rr_m = 0x00000001,
3317 + I2CSSM_wr_b = 1, // In I2C-> i2cssm
3318 + I2CSSM_wr_m = 0x00000002,
3319 + I2CSSM_sa_b = 2, // In I2C-> i2cssm
3320 + I2CSSM_sa_m = 0x00000004,
3321 + I2CSSM_tf_b = 3, // In I2C-> i2cssm
3322 + I2CSSM_tf_m = 0x00000008,
3323 + I2CSSM_gc_b = 4, // In I2C-> i2cssm
3324 + I2CSSM_gc_m = 0x00000010,
3325 + I2CSSM_na_b = 5, // In I2C-> i2cssm
3326 + I2CSSM_na_m = 0x00000020,
3327 + I2CSSM_err_b = 6, // In I2C-> i2cssm
3328 + I2CSSM_err_m = 0x00000040,
3329 +
3330 + I2CSADDR_addr_b = 0, // In I2C-> i2csaddr
3331 + I2CSADDR_addr_m = 0x000003ff,
3332 + I2CSADDR_a_gc_b = 10, // In I2C-> i2csaddr
3333 + I2CSADDR_a_gc_m = 0x00000400,
3334 + I2CSADDR_a10_b = 11, // In I2C-> i2csaddr
3335 + I2CSADDR_a10_m = 0x00000800,
3336 +
3337 + I2CSACK_ack_b = 0, // In I2C-> i2csack
3338 + I2CSACK_ack_m = 0x00000001,
3339 +
3340 +} ;
3341 +#endif // __IDT_I2C_H__
3342 diff -urN linux.old/include/asm-mips/rc32434/integ.h linux.dev/include/asm-mips/rc32434/integ.h
3343 --- linux.old/include/asm-mips/rc32434/integ.h 1970-01-01 01:00:00.000000000 +0100
3344 +++ linux.dev/include/asm-mips/rc32434/integ.h 2006-12-14 04:09:50.000000000 +0100
3345 @@ -0,0 +1,78 @@
3346 +#ifndef __IDT_INTEG_H__
3347 +#define __IDT_INTEG_H__
3348 +
3349 +/*******************************************************************************
3350 + *
3351 + * Copyright 2002 Integrated Device Technology, Inc.
3352 + * All rights reserved.
3353 + *
3354 + * System Integrity register definition.
3355 + *
3356 + * File : $Id: integ.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
3357 + *
3358 + * Author : ryan.holmQVist@idt.com
3359 + * Date : 20011005
3360 + * Update :
3361 + * $Log: integ.h,v $
3362 + * Revision 1.3 2002/06/06 18:34:04 astichte
3363 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
3364 + *
3365 + * Revision 1.2 2002/06/05 18:32:33 astichte
3366 + * Removed IDTField
3367 + *
3368 + * Revision 1.1 2002/05/29 17:33:22 sysarch
3369 + * jba File moved from vcode/include/idt/acacia
3370 + *
3371 + ******************************************************************************/
3372 +
3373 +#include <asm/rc32434/types.h>
3374 +
3375 +enum
3376 +{
3377 + INTEG0_PhysicalAddress = 0x18030000,
3378 + INTEG_PhysicalAddress = INTEG0_PhysicalAddress, // Default
3379 +
3380 + INTEG0_VirtualAddress = 0xb8030000,
3381 + INTEG_VirtualAddress = INTEG0_VirtualAddress, // Default
3382 +} ;
3383 +
3384 +// if you are looing for CEA, try rst.h
3385 +typedef struct
3386 +{
3387 + U32 filler [0xc] ; // 0x30 bytes unused.
3388 + U32 errcs ; // sticky use ERRCS_
3389 + U32 wtcount ; // Watchdog timer count reg.
3390 + U32 wtcompare ; // Watchdog timer timeout value.
3391 + U32 wtc ; // Watchdog timer control. use WTC_
3392 +} volatile *INTEG_t ;
3393 +
3394 +enum
3395 +{
3396 + ERRCS_wto_b = 0, // In INTEG_t -> errcs
3397 + ERRCS_wto_m = 0x00000001,
3398 + ERRCS_wne_b = 1, // In INTEG_t -> errcs
3399 + ERRCS_wne_m = 0x00000002,
3400 + ERRCS_ucw_b = 2, // In INTEG_t -> errcs
3401 + ERRCS_ucw_m = 0x00000004,
3402 + ERRCS_ucr_b = 3, // In INTEG_t -> errcs
3403 + ERRCS_ucr_m = 0x00000008,
3404 + ERRCS_upw_b = 4, // In INTEG_t -> errcs
3405 + ERRCS_upw_m = 0x00000010,
3406 + ERRCS_upr_b = 5, // In INTEG_t -> errcs
3407 + ERRCS_upr_m = 0x00000020,
3408 + ERRCS_udw_b = 6, // In INTEG_t -> errcs
3409 + ERRCS_udw_m = 0x00000040,
3410 + ERRCS_udr_b = 7, // In INTEG_t -> errcs
3411 + ERRCS_udr_m = 0x00000080,
3412 + ERRCS_sae_b = 8, // In INTEG_t -> errcs
3413 + ERRCS_sae_m = 0x00000100,
3414 + ERRCS_wre_b = 9, // In INTEG_t -> errcs
3415 + ERRCS_wre_m = 0x00000200,
3416 +
3417 + WTC_en_b = 0, // In INTEG_t -> wtc
3418 + WTC_en_m = 0x00000001,
3419 + WTC_to_b = 1, // In INTEG_t -> wtc
3420 + WTC_to_m = 0x00000002,
3421 +} ;
3422 +
3423 +#endif // __IDT_INTEG_H__
3424 diff -urN linux.old/include/asm-mips/rc32434/int.h linux.dev/include/asm-mips/rc32434/int.h
3425 --- linux.old/include/asm-mips/rc32434/int.h 1970-01-01 01:00:00.000000000 +0100
3426 +++ linux.dev/include/asm-mips/rc32434/int.h 2006-12-14 04:09:50.000000000 +0100
3427 @@ -0,0 +1,167 @@
3428 +#ifndef __IDT_INT_H__
3429 +#define __IDT_INT_H__
3430 +
3431 +/*******************************************************************************
3432 + *
3433 + * Copyright 2002 Integrated Device Technology, Inc.
3434 + * All rights reserved.
3435 + *
3436 + * Interrupt Controller register definition.
3437 + *
3438 + * File : $Id: int.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
3439 + *
3440 + * Author : ryan.holmqvist@idt.com
3441 + * Date : 20011005
3442 + * Update :
3443 + * $Log: int.h,v $
3444 + * Revision 1.3 2002/06/06 18:34:04 astichte
3445 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
3446 + *
3447 + * Revision 1.2 2002/06/05 18:47:33 astichte
3448 + * Removed IDTField
3449 + *
3450 + * Revision 1.1 2002/05/29 17:33:22 sysarch
3451 + * jba File moved from vcode/include/idt/acacia
3452 + *
3453 + *
3454 + ******************************************************************************/
3455 +
3456 +#include <asm/rc32434/types.h>
3457 +
3458 +enum
3459 +{
3460 + INT0_PhysicalAddress = 0x18038000,
3461 + INT_PhysicalAddress = INT0_PhysicalAddress, // Default
3462 +
3463 + INT0_VirtualAddress = 0xb8038000,
3464 + INT_VirtualAddress = INT0_VirtualAddress, // Default
3465 +} ;
3466 +
3467 +struct INT_s
3468 +{
3469 + U32 ipend ; //Pending interrupts. use INT?_
3470 + U32 itest ; //Test bits. use INT?_
3471 + U32 imask ; //Interrupt disabled when set. use INT?_
3472 +} ;
3473 +
3474 +enum
3475 +{
3476 + IPEND2 = 0, // HW 2 interrupt to core. use INT2_
3477 + IPEND3 = 1, // HW 3 interrupt to core. use INT3_
3478 + IPEND4 = 2, // HW 4 interrupt to core. use INT4_
3479 + IPEND5 = 3, // HW 5 interrupt to core. use INT5_
3480 + IPEND6 = 4, // HW 6 interrupt to core. use INT6_
3481 +
3482 + IPEND_count, // must be last (used in loops)
3483 + IPEND_min = IPEND2 // min IPEND (used in loops)
3484 +};
3485 +
3486 +typedef struct INTC_s
3487 +{
3488 + struct INT_s i [IPEND_count] ;// use i[IPEND?] = INT?_
3489 + U32 nmips ; // use NMIPS_
3490 +} volatile *INT_t ;
3491 +
3492 +enum
3493 +{
3494 + INT2_timer0_b = 0,
3495 + INT2_timer0_m = 0x00000001,
3496 + INT2_timer1_b = 1,
3497 + INT2_timer1_m = 0x00000002,
3498 + INT2_timer2_b = 2,
3499 + INT2_timer2_m = 0x00000004,
3500 + INT2_refresh_b = 3,
3501 + INT2_refresh_m = 0x00000008,
3502 + INT2_watchdogTimeout_b = 4,
3503 + INT2_watchdogTimeout_m = 0x00000010,
3504 + INT2_undecodedCpuWrite_b = 5,
3505 + INT2_undecodedCpuWrite_m = 0x00000020,
3506 + INT2_undecodedCpuRead_b = 6,
3507 + INT2_undecodedCpuRead_m = 0x00000040,
3508 + INT2_undecodedPciWrite_b = 7,
3509 + INT2_undecodedPciWrite_m = 0x00000080,
3510 + INT2_undecodedPciRead_b = 8,
3511 + INT2_undecodedPciRead_m = 0x00000100,
3512 + INT2_undecodedDmaWrite_b = 9,
3513 + INT2_undecodedDmaWrite_m = 0x00000200,
3514 + INT2_undecodedDmaRead_b = 10,
3515 + INT2_undecodedDmaRead_m = 0x00000400,
3516 + INT2_ipBusSlaveAckError_b = 11,
3517 + INT2_ipBusSlaveAckError_m = 0x00000800,
3518 +
3519 + INT3_dmaChannel0_b = 0,
3520 + INT3_dmaChannel0_m = 0x00000001,
3521 + INT3_dmaChannel1_b = 1,
3522 + INT3_dmaChannel1_m = 0x00000002,
3523 + INT3_dmaChannel2_b = 2,
3524 + INT3_dmaChannel2_m = 0x00000004,
3525 + INT3_dmaChannel3_b = 3,
3526 + INT3_dmaChannel3_m = 0x00000008,
3527 + INT3_dmaChannel4_b = 4,
3528 + INT3_dmaChannel4_m = 0x00000010,
3529 + INT3_dmaChannel5_b = 5,
3530 + INT3_dmaChannel5_m = 0x00000020,
3531 +
3532 + INT5_uartGeneral0_b = 0,
3533 + INT5_uartGeneral0_m = 0x00000001,
3534 + INT5_uartTxrdy0_b = 1,
3535 + INT5_uartTxrdy0_m = 0x00000002,
3536 + INT5_uartRxrdy0_b = 2,
3537 + INT5_uartRxrdy0_m = 0x00000004,
3538 + INT5_pci_b = 3,
3539 + INT5_pci_m = 0x00000008,
3540 + INT5_pciDecoupled_b = 4,
3541 + INT5_pciDecoupled_m = 0x00000010,
3542 + INT5_spi_b = 5,
3543 + INT5_spi_m = 0x00000020,
3544 + INT5_deviceDecoupled_b = 6,
3545 + INT5_deviceDecoupled_m = 0x00000040,
3546 + INT5_i2cMaster_b = 7,
3547 + INT5_i2cMaster_m = 0x00000080,
3548 + INT5_i2cSlave_b = 8,
3549 + INT5_i2cSlave_m = 0x00000100,
3550 + INT5_ethOvr_b = 9,
3551 + INT5_ethOvr_m = 0x00000200,
3552 + INT5_ethUnd_b = 10,
3553 + INT5_ethUnd_m = 0x00000400,
3554 + INT5_ethPfd_b = 11,
3555 + INT5_ethPfd_m = 0x00000800,
3556 + INT5_nvram_b = 12,
3557 + INT5_nvram_m = 0x00001000,
3558 +
3559 + INT6_gpio0_b = 0,
3560 + INT6_gpio0_m = 0x00000001,
3561 + INT6_gpio1_b = 1,
3562 + INT6_gpio1_m = 0x00000002,
3563 + INT6_gpio2_b = 2,
3564 + INT6_gpio2_m = 0x00000004,
3565 + INT6_gpio3_b = 3,
3566 + INT6_gpio3_m = 0x00000008,
3567 + INT6_gpio4_b = 4,
3568 + INT6_gpio4_m = 0x00000010,
3569 + INT6_gpio5_b = 5,
3570 + INT6_gpio5_m = 0x00000020,
3571 + INT6_gpio6_b = 6,
3572 + INT6_gpio6_m = 0x00000040,
3573 + INT6_gpio7_b = 7,
3574 + INT6_gpio7_m = 0x00000080,
3575 + INT6_gpio8_b = 8,
3576 + INT6_gpio8_m = 0x00000100,
3577 + INT6_gpio9_b = 9,
3578 + INT6_gpio9_m = 0x00000200,
3579 + INT6_gpio10_b = 10,
3580 + INT6_gpio10_m = 0x00000400,
3581 + INT6_gpio11_b = 11,
3582 + INT6_gpio11_m = 0x00000800,
3583 + INT6_gpio12_b = 12,
3584 + INT6_gpio12_m = 0x00001000,
3585 + INT6_gpio13_b = 13,
3586 + INT6_gpio13_m = 0x00002000,
3587 +
3588 + NMIPS_gpio_b = 0,
3589 + NMIPS_gpio_m = 0x00000001,
3590 +} ;
3591 +
3592 +#endif // __IDT_INT_H__
3593 +
3594 +
3595 diff -urN linux.old/include/asm-mips/rc32434/iparb.h linux.dev/include/asm-mips/rc32434/iparb.h
3596 --- linux.old/include/asm-mips/rc32434/iparb.h 1970-01-01 01:00:00.000000000 +0100
3597 +++ linux.dev/include/asm-mips/rc32434/iparb.h 2006-12-14 04:09:50.000000000 +0100
3598 @@ -0,0 +1,95 @@
3599 +#ifndef __IDT_IPARB_H__
3600 +#define __IDT_IPARB_H__
3601 +
3602 +/*******************************************************************************
3603 + *
3604 + * Copyright 2002 Integrated Device Technology, Inc.
3605 + * All rights reserved.
3606 + *
3607 + * IP Arbiter register definitions.
3608 + *
3609 + * File : $Id: iparb.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
3610 + *
3611 + * Author : Allen.Stichter@idt.com
3612 + * Date : 20020120
3613 + * Update :
3614 + * $Log: iparb.h,v $
3615 + * Revision 1.3 2002/06/06 18:34:04 astichte
3616 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
3617 + *
3618 + * Revision 1.2 2002/06/05 19:01:42 astichte
3619 + * Removed IDTField
3620 + *
3621 + * Revision 1.1 2002/05/29 17:33:23 sysarch
3622 + * jba File moved from vcode/include/idt/acacia
3623 + *
3624 + ******************************************************************************/
3625 +
3626 +#include <asm/rc32434/types.h>
3627 +
3628 +enum
3629 +{
3630 + IPARB0_PhysicalAddress = 0x18048000,
3631 + IPARB_PhysicalAddress = IPARB0_PhysicalAddress, // Default
3632 +
3633 + IPARB0_VirtualAddress = 0xb8048000,
3634 + IPARB_VirtualAddress = IPARB0_VirtualAddress, // Default
3635 +} ;
3636 +
3637 +enum
3638 +{
3639 + IPABMXC_ethernetReceive = 0,
3640 + IPABMXC_ethernetTransmit = 1,
3641 + IPABMXC_memoryToHoldFifo = 2,
3642 + IPABMXC_holdFifoToMemory = 3,
3643 + IPABMXC_pciToMemory = 4,
3644 + IPABMXC_memoryToPci = 5,
3645 + IPABMXC_pciTarget = 6,
3646 + IPABMXC_pciTargetStart = 7,
3647 + IPABMXC_cpuToIpBus = 8,
3648 +
3649 + IPABMXC_Count, // Must be last in list !
3650 + IPABMXC_Min = IPABMXC_ethernetReceive,
3651 +
3652 + IPAPXC_PriorityCount = 4, // 3-highest, 0-lowest.
3653 +} ;
3654 +
3655 +typedef struct
3656 +{
3657 + U32 ipapc [IPAPXC_PriorityCount] ; // ipapc[IPAPXC_] = IPAPC_
3658 + U32 ipabmc [IPABMXC_Count] ; // ipabmc[IPABMXC_] = IPABMC_
3659 + U32 ipac ; // use IPAC_
3660 + U32 ipaitcc; // use IPAITCC_
3661 + U32 ipaspare ;
3662 +} volatile * IPARB_t ;
3663 +
3664 +enum
3665 +{
3666 + IPAC_dwm_b = 2,
3667 + IPAC_dwm_m = 0x00000004,
3668 + IPAC_drm_b = 3,
3669 + IPAC_drm_m = 0x00000008,
3670 + IPAC_msk_b = 4,
3671 + IPAC_msk_m = 0x00000010,
3672 +
3673 + IPAPC_ptc_b = 0,
3674 + IPAPC_ptc_m = 0x00003fff,
3675 + IPAPC_mf_b = 14,
3676 + IPAPC_mf_m = 0x00004000,
3677 + IPAPC_cptc_b = 16,
3678 + IPAPC_cptc_m = 0x3fff0000,
3679 +
3680 + IPAITCC_itcc = 0,
3681 + IPAITCC_itcc, = 0x000001ff,
3682 +
3683 + IPABMC_mtc_b = 0,
3684 + IPABMC_mtc_m = 0x00000fff,
3685 + IPABMC_p_b = 12,
3686 + IPABMC_p_m = 0x00003000,
3687 + IPABMC_msk_b = 14,
3688 + IPABMC_msk_m = 0x00004000,
3689 + IPABMC_cmtc_b = 16,
3690 + IPABMC_cmtc_m = 0x0fff0000,
3691 +};
3692 +
3693 +#endif // __IDT_IPARB_H__
3694 diff -urN linux.old/include/asm-mips/rc32434/irm.h linux.dev/include/asm-mips/rc32434/irm.h
3695 --- linux.old/include/asm-mips/rc32434/irm.h 1970-01-01 01:00:00.000000000 +0100
3696 +++ linux.dev/include/asm-mips/rc32434/irm.h 2006-12-14 04:09:50.000000000 +0100
3697 @@ -0,0 +1,55 @@
3698 +#ifndef __IDT_IRM_H__
3699 +#define __IDT_IRM_H__
3700 +
3701 +/*******************************************************************************
3702 + *
3703 + * Copyright 2002 Integrated Device Technology, Inc.
3704 + * All rights reserved.
3705 + *
3706 + * Internal Register Map
3707 + *
3708 + * File : $Id: irm.h,v 1.2 2002/06/05 14:51:06 astichte Exp $
3709 + *
3710 + * Author : Allen.Stichter@idt.com
3711 + * Date : 20020605
3712 + * Update :
3713 + * $Log: irm.h,v $
3714 + * Revision 1.2 2002/06/05 14:51:06 astichte
3715 + * *** empty log message ***
3716 + *
3717 + * Revision 1.1 2002/05/29 17:33:23 sysarch
3718 + * jba File moved from vcode/include/idt/acacia
3719 + *
3720 + ******************************************************************************/
3721 +
3722 +/*
3723 + * NOTE --
3724 + * This file is here for backwards compatibility.
3725 + * DO NOT USE !!!!
3726 + */
3727 +
3728 +typedef enum
3729 +{
3730 + IRM_Physical = 0x18000000, // Internal Reg. map physical.
3731 + RST_Offset = 0x00000000, // Includes sysid and RST.
3732 + DEV_Offset = 0x00010000, // Device Controller 0.
3733 + DDR_Offset = 0x00018000, // Double-Data-Rate mem. controller.
3734 + PMARB_Offset = 0x00020000, // PM bus arbiter.
3735 + TIM_Offset = 0x00028000, // Counter / timer.
3736 + INTEG_Offset = 0x00030000, // System Integrity.
3737 + INT_Offset = 0x00038000, // Interrupt controller.
3738 + DMA_Offset = 0x00040000, // DMA.
3739 + IPARB_Offset = 0x00044000, // IP bus arbiter.
3740 + GPIO_Offset = 0x00050000, // GPIO.
3741 + UART_Offset = 0x00058000, // UART
3742 + ETH_Offset = 0x00060000, // Ethernet 1.
3743 + I2C_Offset = 0x00068000, // I2C interface.
3744 + SPI_Offset = 0x00070000, // Serial Peripheral Interface.
3745 + NVRAM_Offset = 0x00078000, // NVRAM interface
3746 + AUTH_Offset = 0x0007c000, // Authorization unit
3747 + PCI_Offset = 0x00080000,
3748 + CROM_Offset = 0x000b8000, // Configuration ROM.
3749 + IRM_Size = 0x00200000, // Internal Reg. map size.
3750 +} IRM_Offset_t ;
3751 +
3752 +#endif // __IDT_IRM_H__
3753 diff -urN linux.old/include/asm-mips/rc32434/irq.h linux.dev/include/asm-mips/rc32434/irq.h
3754 --- linux.old/include/asm-mips/rc32434/irq.h 1970-01-01 01:00:00.000000000 +0100
3755 +++ linux.dev/include/asm-mips/rc32434/irq.h 2006-12-14 04:09:50.000000000 +0100
3756 @@ -0,0 +1,8 @@
3757 +#ifndef __ASM_MACH_MIPS_IRQ_H
3758 +#define __ASM_MACH_MIPS_IRQ_H
3759 +
3760 +#include <linux/autoconf.h>
3761 +
3762 +#define NR_IRQS 256
3763 +
3764 +#endif /* __ASM_MACH_MIPS_IRQ_H */
3765 diff -urN linux.old/include/asm-mips/rc32434/nvram.h linux.dev/include/asm-mips/rc32434/nvram.h
3766 --- linux.old/include/asm-mips/rc32434/nvram.h 1970-01-01 01:00:00.000000000 +0100
3767 +++ linux.dev/include/asm-mips/rc32434/nvram.h 2006-12-14 04:09:50.000000000 +0100
3768 @@ -0,0 +1,97 @@
3769 +#ifndef __IDT_NVRAM_H
3770 +#define __IDT_NVRAM_H
3771 +
3772 +/*******************************************************************************
3773 + *
3774 + * Copyright 2002 Integrated Device Technology, Inc.
3775 + * All rights reserved.
3776 + *
3777 + * IP Arbiter register definitions.
3778 + *
3779 + * File : $Id: nvram.h,v 1.3 2003/07/24 18:34:04 astichte Exp $
3780 + *
3781 + * Author : kiran.rao@idt.com
3782 + * Date : 20030724
3783 + * Update :
3784 + * $Log: nvram.h,v $
3785 + *
3786 + *
3787 + ******************************************************************************/
3788 +#include <asm/rc32434/tpes.h>
3789 +
3790 +
3791 +enum
3792 +{
3793 + NVRAM0_PhysicalAddress = 0xba000000,
3794 + NVRAM_PhysicalAddress = NVRAM0_PhysicalAddress, // Default
3795 +
3796 + NVRAM0_VirtualAddress = 0xba000000,
3797 + NVRAM_VirtualAddress = NVRAM0_VirtualAddress, // Default
3798 +} ;
3799 +
3800 +enum
3801 +{
3802 + NVRCMD_cmd_b = 0,
3803 + NVRCMD_cmd_m = 0x0000007f,
3804 +
3805 + NVRS_r_b = 0,
3806 + NVRS_r_m = 0x00000001,
3807 + NVRS_e_b = 1,
3808 + NVRS_e_m = 0x00000002,
3809 + NVRS_k_b = 2,
3810 + NVRS_k_m = 0x00000004,
3811 +
3812 + NVRSM_r_b = 0,
3813 + NVRSM_r_m = 0x00000001,
3814 + NVRSM_e_b = 1,
3815 + NVRSM_e_m = 0x00000002,
3816 + NVRSM_k_b = 2,
3817 + NVRSM_k_m = 0x00000004,
3818 +
3819 + NVRCFG0_pwidth_b = 0,
3820 + NVRCFG0_pwidth_m = 0x00000003,
3821 + NVRCFG0_nmax_b = 2,
3822 + NVRCFG0_nmax_m = 0x0000000C,
3823 + NVRCFG0_vppl_b = 4,
3824 + NVRCFG0_vppl_m = 0x000000f0,
3825 + NVRCFG0_vppm_b = 8,
3826 + NVRCFG0_vppm_m = 0x00000300,
3827 + NVRCFG0_dvpp_b = 10,
3828 + NVRCFG0_dvpp_m = 0x00000c00,
3829 + NVRCFG0_x_b = 12,
3830 + NVRCFG0_x_m = 0x00007000,
3831 +
3832 + NVRCFG1_t1tecc_b = 0,
3833 + NVRCFG1_t1tecc_m = 0x00000003,
3834 + NVRCFG1_t1mrcl_b = 2,
3835 + NVRCFG1_t1mrcl_m = 0x0000000c,
3836 + NVRCFG1_t1bias_b = 4,
3837 + NVRCFG1_t1bias_m = 0x00000030,
3838 + NVRCFG1_t2tecc_b = 6,
3839 + NVRCFG1_t2tecc_m = 0x000000c0,
3840 + NVRCFG1_t2mrcl_b = 8,
3841 + NVRCFG1_t2mrcl_m = 0x00000300,
3842 + NVRCFG1_t2bias_b = 10,
3843 + NVRCFG1_t2bias_m = 0x00000c00,
3844 + NVRCFG1_t3tecc_b = 12,
3845 + NVRCFG1_t3tecc_m = 0x00003000,
3846 + NVRCFG1_t3mrcl_b = 14,
3847 + NVRCFG1_t3mrcl_m = 0x0000c000,
3848 + NVRCFG1_t3bias_b = 16,
3849 + NVRCFG1_t3bias_m = 0x00030000,
3850 + NVRCFG1_t4tecc_b = 18,
3851 + NVRCFG1_t4tecc_m = 0x000c0000,
3852 + NVRCFG1_t4mrcl_b = 20,
3853 + NVRCFG1_t4mrcl_m = 0x00300000,
3854 + NVRCFG1_t4bias_b = 22,
3855 + NVRCFG1_t4bias_m = 0x00c00000,
3856 + NVRCFG1_t5tecc_b = 24,
3857 + NVRCFG1_t5tecc_m = 0x03000000,
3858 + NVRCFG1_t5mrcl_b = 26,
3859 + NVRCFG1_t5mrcl_m = 0x0c000000,
3860 + NVRCFG1_t5bias_b = 28,
3861 + NVRCFG1_t5bias_m = 0x30000000,
3862 +}
3863 +
3864 +#endif // __IDT_NVRAM_H__
3865 +
3866 diff -urN linux.old/include/asm-mips/rc32434/pci.h linux.dev/include/asm-mips/rc32434/pci.h
3867 --- linux.old/include/asm-mips/rc32434/pci.h 1970-01-01 01:00:00.000000000 +0100
3868 +++ linux.dev/include/asm-mips/rc32434/pci.h 2006-12-14 04:09:50.000000000 +0100
3869 @@ -0,0 +1,695 @@
3870 +/**************************************************************************
3871 + *
3872 + * BRIEF MODULE DESCRIPTION
3873 + * PCI register definitio
3874 + *
3875 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
3876 + *
3877 + * This program is free software; you can redistribute it and/or modify it
3878 + * under the terms of the GNU General Public License as published by the
3879 + * Free Software Foundation; either version 2 of the License, or (at your
3880 + * option) any later version.
3881 + *
3882 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3883 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3884 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3885 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3886 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3887 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3888 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3889 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3890 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3891 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3892 + *
3893 + * You should have received a copy of the GNU General Public License along
3894 + * with this program; if not, write to the Free Software Foundation, Inc.,
3895 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3896 + *
3897 + *
3898 + **************************************************************************
3899 + * May 2004 rkt, neb.
3900 + *
3901 + * Initial Release
3902 + *
3903 + *
3904 + *
3905 + **************************************************************************
3906 + */
3907 +
3908 +#ifndef __IDT_PCI_H__
3909 +#define __IDT_PCI_H__
3910 +
3911 +enum
3912 +{
3913 + PCI0_PhysicalAddress = 0x18080000,
3914 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
3915 +
3916 + PCI0_VirtualAddress = 0xB8080000,
3917 + PCI_VirtualAddress = PCI0_VirtualAddress,
3918 +} ;
3919 +
3920 +enum
3921 +{
3922 + PCI_LbaCount = 4, // Local base addresses.
3923 +} ;
3924 +
3925 +typedef struct
3926 +{
3927 + u32 a ; // Address.
3928 + u32 c ; // Control.
3929 + u32 m ; // mapping.
3930 +} PCI_Map_s ;
3931 +
3932 +typedef struct
3933 +{
3934 + u32 pcic ;
3935 + u32 pcis ;
3936 + u32 pcism ;
3937 + u32 pcicfga ;
3938 + u32 pcicfgd ;
3939 + PCI_Map_s pcilba [PCI_LbaCount] ;
3940 + u32 pcidac ;
3941 + u32 pcidas ;
3942 + u32 pcidasm ;
3943 + u32 pcidad ;
3944 + u32 pcidma8c ;
3945 + u32 pcidma9c ;
3946 + u32 pcitc ;
3947 +} volatile *PCI_t ;
3948 +
3949 +// PCI messaging unit.
3950 +enum
3951 +{
3952 + PCIM_Count = 2,
3953 +} ;
3954 +typedef struct
3955 +{
3956 + u32 pciim [PCIM_Count] ;
3957 + u32 pciom [PCIM_Count] ;
3958 + u32 pciid ;
3959 + u32 pciiic ;
3960 + u32 pciiim ;
3961 + u32 pciiod ;
3962 + u32 pciioic ;
3963 + u32 pciioim ;
3964 +} volatile *PCIM_t ;
3965 +
3966 +/*******************************************************************************
3967 + *
3968 + * PCI Control Register
3969 + *
3970 + ******************************************************************************/
3971 +enum
3972 +{
3973 + PCIC_en_b = 0,
3974 + PCIC_en_m = 0x00000001,
3975 + PCIC_tnr_b = 1,
3976 + PCIC_tnr_m = 0x00000002,
3977 + PCIC_sce_b = 2,
3978 + PCIC_sce_m = 0x00000004,
3979 + PCIC_ien_b = 3,
3980 + PCIC_ien_m = 0x00000008,
3981 + PCIC_aaa_b = 4,
3982 + PCIC_aaa_m = 0x00000010,
3983 + PCIC_eap_b = 5,
3984 + PCIC_eap_m = 0x00000020,
3985 + PCIC_pcim_b = 6,
3986 + PCIC_pcim_m = 0x000001c0,
3987 + PCIC_pcim_disabled_v = 0,
3988 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
3989 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
3990 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
3991 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
3992 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
3993 + PCIC_pcim_reserved6_v = 6,
3994 + PCIC_pcim_reserved7_v = 7,
3995 + PCIC_igm_b = 9,
3996 + PCIC_igm_m = 0x00000200,
3997 +} ;
3998 +
3999 +/*******************************************************************************
4000 + *
4001 + * PCI Status Register
4002 + *
4003 + ******************************************************************************/
4004 +enum {
4005 + PCIS_eed_b = 0,
4006 + PCIS_eed_m = 0x00000001,
4007 + PCIS_wr_b = 1,
4008 + PCIS_wr_m = 0x00000002,
4009 + PCIS_nmi_b = 2,
4010 + PCIS_nmi_m = 0x00000004,
4011 + PCIS_ii_b = 3,
4012 + PCIS_ii_m = 0x00000008,
4013 + PCIS_cwe_b = 4,
4014 + PCIS_cwe_m = 0x00000010,
4015 + PCIS_cre_b = 5,
4016 + PCIS_cre_m = 0x00000020,
4017 + PCIS_mdpe_b = 6,
4018 + PCIS_mdpe_m = 0x00000040,
4019 + PCIS_sta_b = 7,
4020 + PCIS_sta_m = 0x00000080,
4021 + PCIS_rta_b = 8,
4022 + PCIS_rta_m = 0x00000100,
4023 + PCIS_rma_b = 9,
4024 + PCIS_rma_m = 0x00000200,
4025 + PCIS_sse_b = 10,
4026 + PCIS_sse_m = 0x00000400,
4027 + PCIS_ose_b = 11,
4028 + PCIS_ose_m = 0x00000800,
4029 + PCIS_pe_b = 12,
4030 + PCIS_pe_m = 0x00001000,
4031 + PCIS_tae_b = 13,
4032 + PCIS_tae_m = 0x00002000,
4033 + PCIS_rle_b = 14,
4034 + PCIS_rle_m = 0x00004000,
4035 + PCIS_bme_b = 15,
4036 + PCIS_bme_m = 0x00008000,
4037 + PCIS_prd_b = 16,
4038 + PCIS_prd_m = 0x00010000,
4039 + PCIS_rip_b = 17,
4040 + PCIS_rip_m = 0x00020000,
4041 +} ;
4042 +
4043 +/*******************************************************************************
4044 + *
4045 + * PCI Status Mask Register
4046 + *
4047 + ******************************************************************************/
4048 +enum {
4049 + PCISM_eed_b = 0,
4050 + PCISM_eed_m = 0x00000001,
4051 + PCISM_wr_b = 1,
4052 + PCISM_wr_m = 0x00000002,
4053 + PCISM_nmi_b = 2,
4054 + PCISM_nmi_m = 0x00000004,
4055 + PCISM_ii_b = 3,
4056 + PCISM_ii_m = 0x00000008,
4057 + PCISM_cwe_b = 4,
4058 + PCISM_cwe_m = 0x00000010,
4059 + PCISM_cre_b = 5,
4060 + PCISM_cre_m = 0x00000020,
4061 + PCISM_mdpe_b = 6,
4062 + PCISM_mdpe_m = 0x00000040,
4063 + PCISM_sta_b = 7,
4064 + PCISM_sta_m = 0x00000080,
4065 + PCISM_rta_b = 8,
4066 + PCISM_rta_m = 0x00000100,
4067 + PCISM_rma_b = 9,
4068 + PCISM_rma_m = 0x00000200,
4069 + PCISM_sse_b = 10,
4070 + PCISM_sse_m = 0x00000400,
4071 + PCISM_ose_b = 11,
4072 + PCISM_ose_m = 0x00000800,
4073 + PCISM_pe_b = 12,
4074 + PCISM_pe_m = 0x00001000,
4075 + PCISM_tae_b = 13,
4076 + PCISM_tae_m = 0x00002000,
4077 + PCISM_rle_b = 14,
4078 + PCISM_rle_m = 0x00004000,
4079 + PCISM_bme_b = 15,
4080 + PCISM_bme_m = 0x00008000,
4081 + PCISM_prd_b = 16,
4082 + PCISM_prd_m = 0x00010000,
4083 + PCISM_rip_b = 17,
4084 + PCISM_rip_m = 0x00020000,
4085 +} ;
4086 +
4087 +/*******************************************************************************
4088 + *
4089 + * PCI Configuration Address Register
4090 + *
4091 + ******************************************************************************/
4092 +enum {
4093 + PCICFGA_reg_b = 2,
4094 + PCICFGA_reg_m = 0x000000fc,
4095 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
4096 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
4097 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
4098 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
4099 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
4100 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
4101 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
4102 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
4103 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
4104 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
4105 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
4106 + PCICFGA_reg_pba0m_v = 0x48>>2,
4107 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
4108 + PCICFGA_reg_pba1m_v = 0x50>>2,
4109 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
4110 + PCICFGA_reg_pba2m_v = 0x58>>2,
4111 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
4112 + PCICFGA_reg_pba3m_v = 0x60>>2,
4113 + PCICFGA_reg_pmgt_v = 0x64>>2,
4114 + PCICFGA_func_b = 8,
4115 + PCICFGA_func_m = 0x00000700,
4116 + PCICFGA_dev_b = 11,
4117 + PCICFGA_dev_m = 0x0000f800,
4118 + PCICFGA_dev_internal_v = 0,
4119 + PCICFGA_bus_b = 16,
4120 + PCICFGA_bus_m = 0x00ff0000,
4121 + PCICFGA_bus_type0_v = 0, //local bus
4122 + PCICFGA_en_b = 31, // read only
4123 + PCICFGA_en_m = 0x80000000,
4124 +} ;
4125 +
4126 +enum {
4127 + PCFGID_vendor_b = 0,
4128 + PCFGID_vendor_m = 0x0000ffff,
4129 + PCFGID_vendor_IDT_v = 0x111d,
4130 + PCFGID_device_b = 16,
4131 + PCFGID_device_m = 0xffff0000,
4132 + PCFGID_device_Korinade_v = 0x0214,
4133 +
4134 + PCFG04_command_ioena_b = 1,
4135 + PCFG04_command_ioena_m = 0x00000001,
4136 + PCFG04_command_memena_b = 2,
4137 + PCFG04_command_memena_m = 0x00000002,
4138 + PCFG04_command_bmena_b = 3,
4139 + PCFG04_command_bmena_m = 0x00000004,
4140 + PCFG04_command_mwinv_b = 5,
4141 + PCFG04_command_mwinv_m = 0x00000010,
4142 + PCFG04_command_parena_b = 7,
4143 + PCFG04_command_parena_m = 0x00000040,
4144 + PCFG04_command_serrena_b = 9,
4145 + PCFG04_command_serrena_m = 0x00000100,
4146 + PCFG04_command_fastbbena_b = 10,
4147 + PCFG04_command_fastbbena_m = 0x00000200,
4148 + PCFG04_status_b = 16,
4149 + PCFG04_status_m = 0xffff0000,
4150 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
4151 + PCFG04_status_66MHz_m = 0x00200000,
4152 + PCFG04_status_fbb_b = 23,
4153 + PCFG04_status_fbb_m = 0x00800000,
4154 + PCFG04_status_mdpe_b = 24,
4155 + PCFG04_status_mdpe_m = 0x01000000,
4156 + PCFG04_status_dst_b = 25,
4157 + PCFG04_status_dst_m = 0x06000000,
4158 + PCFG04_status_sta_b = 27,
4159 + PCFG04_status_sta_m = 0x08000000,
4160 + PCFG04_status_rta_b = 28,
4161 + PCFG04_status_rta_m = 0x10000000,
4162 + PCFG04_status_rma_b = 29,
4163 + PCFG04_status_rma_m = 0x20000000,
4164 + PCFG04_status_sse_b = 30,
4165 + PCFG04_status_sse_m = 0x40000000,
4166 + PCFG04_status_pe_b = 31,
4167 + PCFG04_status_pe_m = 0x40000000,
4168 +
4169 + PCFG08_revId_b = 0,
4170 + PCFG08_revId_m = 0x000000ff,
4171 + PCFG08_classCode_b = 0,
4172 + PCFG08_classCode_m = 0xffffff00,
4173 + PCFG08_classCode_bridge_v = 06,
4174 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
4175 + PCFG0C_cacheline_b = 0,
4176 + PCFG0C_cacheline_m = 0x000000ff,
4177 + PCFG0C_masterLatency_b = 8,
4178 + PCFG0C_masterLatency_m = 0x0000ff00,
4179 + PCFG0C_headerType_b = 16,
4180 + PCFG0C_headerType_m = 0x00ff0000,
4181 + PCFG0C_bist_b = 24,
4182 + PCFG0C_bist_m = 0xff000000,
4183 +
4184 + PCIPBA_msi_b = 0,
4185 + PCIPBA_msi_m = 0x00000001,
4186 + PCIPBA_p_b = 3,
4187 + PCIPBA_p_m = 0x00000004,
4188 + PCIPBA_baddr_b = 8,
4189 + PCIPBA_baddr_m = 0xffffff00,
4190 +
4191 + PCFGSS_vendorId_b = 0,
4192 + PCFGSS_vendorId_m = 0x0000ffff,
4193 + PCFGSS_id_b = 16,
4194 + PCFGSS_id_m = 0xffff0000,
4195 +
4196 + PCFG3C_interruptLine_b = 0,
4197 + PCFG3C_interruptLine_m = 0x000000ff,
4198 + PCFG3C_interruptPin_b = 8,
4199 + PCFG3C_interruptPin_m = 0x0000ff00,
4200 + PCFG3C_minGrant_b = 16,
4201 + PCFG3C_minGrant_m = 0x00ff0000,
4202 + PCFG3C_maxLat_b = 24,
4203 + PCFG3C_maxLat_m = 0xff000000,
4204 +
4205 + PCIPBAC_msi_b = 0,
4206 + PCIPBAC_msi_m = 0x00000001,
4207 + PCIPBAC_p_b = 1,
4208 + PCIPBAC_p_m = 0x00000002,
4209 + PCIPBAC_size_b = 2,
4210 + PCIPBAC_size_m = 0x0000007c,
4211 + PCIPBAC_sb_b = 7,
4212 + PCIPBAC_sb_m = 0x00000080,
4213 + PCIPBAC_pp_b = 8,
4214 + PCIPBAC_pp_m = 0x00000100,
4215 + PCIPBAC_mr_b = 9,
4216 + PCIPBAC_mr_m = 0x00000600,
4217 + PCIPBAC_mr_read_v =0, //no prefetching
4218 + PCIPBAC_mr_readLine_v =1,
4219 + PCIPBAC_mr_readMult_v =2,
4220 + PCIPBAC_mrl_b = 11,
4221 + PCIPBAC_mrl_m = 0x00000800,
4222 + PCIPBAC_mrm_b = 12,
4223 + PCIPBAC_mrm_m = 0x00001000,
4224 + PCIPBAC_trp_b = 13,
4225 + PCIPBAC_trp_m = 0x00002000,
4226 +
4227 + PCFG40_trdyTimeout_b = 0,
4228 + PCFG40_trdyTimeout_m = 0x000000ff,
4229 + PCFG40_retryLim_b = 8,
4230 + PCFG40_retryLim_m = 0x0000ff00,
4231 +};
4232 +
4233 +/*******************************************************************************
4234 + *
4235 + * PCI Local Base Address [0|1|2|3] Register
4236 + *
4237 + ******************************************************************************/
4238 +enum {
4239 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
4240 + PCILBA_baddr_m = 0xffffff00,
4241 +} ;
4242 +/*******************************************************************************
4243 + *
4244 + * PCI Local Base Address Control Register
4245 + *
4246 + ******************************************************************************/
4247 +enum {
4248 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
4249 + PCILBAC_msi_m = 0x00000001,
4250 + PCILBAC_msi_mem_v = 0,
4251 + PCILBAC_msi_io_v = 1,
4252 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
4253 + PCILBAC_size_m = 0x0000007c,
4254 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
4255 + PCILBAC_sb_m = 0x00000080,
4256 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
4257 + PCILBAC_rt_m = 0x00000100,
4258 + PCILBAC_rt_noprefetch_v = 0, // mem read
4259 + PCILBAC_rt_prefetch_v = 1, // mem readline
4260 +} ;
4261 +
4262 +/*******************************************************************************
4263 + *
4264 + * PCI Local Base Address [0|1|2|3] Mapping Register
4265 + *
4266 + ******************************************************************************/
4267 +enum {
4268 + PCILBAM_maddr_b = 8,
4269 + PCILBAM_maddr_m = 0xffffff00,
4270 +} ;
4271 +
4272 +/*******************************************************************************
4273 + *
4274 + * PCI Decoupled Access Control Register
4275 + *
4276 + ******************************************************************************/
4277 +enum {
4278 + PCIDAC_den_b = 0,
4279 + PCIDAC_den_m = 0x00000001,
4280 +} ;
4281 +
4282 +/*******************************************************************************
4283 + *
4284 + * PCI Decoupled Access Status Register
4285 + *
4286 + ******************************************************************************/
4287 +enum {
4288 + PCIDAS_d_b = 0,
4289 + PCIDAS_d_m = 0x00000001,
4290 + PCIDAS_b_b = 1,
4291 + PCIDAS_b_m = 0x00000002,
4292 + PCIDAS_e_b = 2,
4293 + PCIDAS_e_m = 0x00000004,
4294 + PCIDAS_ofe_b = 3,
4295 + PCIDAS_ofe_m = 0x00000008,
4296 + PCIDAS_off_b = 4,
4297 + PCIDAS_off_m = 0x00000010,
4298 + PCIDAS_ife_b = 5,
4299 + PCIDAS_ife_m = 0x00000020,
4300 + PCIDAS_iff_b = 6,
4301 + PCIDAS_iff_m = 0x00000040,
4302 +} ;
4303 +
4304 +/*******************************************************************************
4305 + *
4306 + * PCI DMA Channel 8 Configuration Register
4307 + *
4308 + ******************************************************************************/
4309 +enum
4310 +{
4311 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
4312 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
4313 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
4314 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
4315 +} ;
4316 +
4317 +/*******************************************************************************
4318 + *
4319 + * PCI DMA Channel 9 Configuration Register
4320 + *
4321 + ******************************************************************************/
4322 +enum
4323 +{
4324 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
4325 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
4326 +} ;
4327 +
4328 +/*******************************************************************************
4329 + *
4330 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
4331 + *
4332 + ******************************************************************************/
4333 +enum {
4334 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
4335 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
4336 + // These are for reads (DMA channel 8)
4337 + PCIDMAD_devcmd_mr_v = 0, //memory read
4338 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
4339 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
4340 + PCIDMAD_devcmd_ior_v = 3, //I/O read
4341 + // These are for writes (DMA channel 9)
4342 + PCIDMAD_devcmd_mw_v = 0, //memory write
4343 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
4344 + PCIDMAD_devcmd_iow_v = 3, //I/O write
4345 +
4346 + // Swap byte field applies to both DMA channel 8 and 9
4347 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
4348 + PCIDMAD_sb_m = 0x01000000, // swap byte field
4349 +} ;
4350 +
4351 +
4352 +/*******************************************************************************
4353 + *
4354 + * PCI Target Control Register
4355 + *
4356 + ******************************************************************************/
4357 +enum
4358 +{
4359 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
4360 + PCITC_rtimer_m = 0x000000ff,
4361 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
4362 + PCITC_dtimer_m = 0x0000ff00,
4363 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
4364 + PCITC_rdr_m = 0x00040000,
4365 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
4366 + PCITC_ddt_m = 0x00080000,
4367 +} ;
4368 +/*******************************************************************************
4369 + *
4370 + * PCI messaging unit [applies to both inbound and outbound registers ]
4371 + *
4372 + ******************************************************************************/
4373 +enum
4374 +{
4375 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
4376 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
4377 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
4378 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
4379 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
4380 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
4381 +};
4382 +
4383 +
4384 +
4385 +
4386 +
4387 +
4388 +#define PCI_MSG_VirtualAddress 0xB8088010
4389 +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
4390 +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
4391 +
4392 +#define PCIM_SHFT 0x6
4393 +#define PCIM_BIT_LEN 0x7
4394 +#define PCIM_H_EA 0x3
4395 +#define PCIM_H_IA_FIX 0x4
4396 +#define PCIM_H_IA_RR 0x5
4397 +#if 0
4398 +#define PCI_ADDR_START 0x13000000
4399 +#endif
4400 +
4401 +#define PCI_ADDR_START 0x50000000
4402 +
4403 +#define CPUTOPCI_MEM_WIN 0x02000000
4404 +#define CPUTOPCI_IO_WIN 0x00100000
4405 +#define PCILBA_SIZE_SHFT 2
4406 +#define PCILBA_SIZE_MASK 0x1F
4407 +#define SIZE_256MB 0x1C
4408 +#define SIZE_128MB 0x1B
4409 +#define SIZE_64MB 0x1A
4410 +#define SIZE_32MB 0x19
4411 +#define SIZE_16MB 0x18
4412 +#define SIZE_4MB 0x16
4413 +#define SIZE_2MB 0x15
4414 +#define SIZE_1MB 0x14
4415 +#define KORINA_CONFIG0_ADDR 0x80000000
4416 +#define KORINA_CONFIG1_ADDR 0x80000004
4417 +#define KORINA_CONFIG2_ADDR 0x80000008
4418 +#define KORINA_CONFIG3_ADDR 0x8000000C
4419 +#define KORINA_CONFIG4_ADDR 0x80000010
4420 +#define KORINA_CONFIG5_ADDR 0x80000014
4421 +#define KORINA_CONFIG6_ADDR 0x80000018
4422 +#define KORINA_CONFIG7_ADDR 0x8000001C
4423 +#define KORINA_CONFIG8_ADDR 0x80000020
4424 +#define KORINA_CONFIG9_ADDR 0x80000024
4425 +#define KORINA_CONFIG10_ADDR 0x80000028
4426 +#define KORINA_CONFIG11_ADDR 0x8000002C
4427 +#define KORINA_CONFIG12_ADDR 0x80000030
4428 +#define KORINA_CONFIG13_ADDR 0x80000034
4429 +#define KORINA_CONFIG14_ADDR 0x80000038
4430 +#define KORINA_CONFIG15_ADDR 0x8000003C
4431 +#define KORINA_CONFIG16_ADDR 0x80000040
4432 +#define KORINA_CONFIG17_ADDR 0x80000044
4433 +#define KORINA_CONFIG18_ADDR 0x80000048
4434 +#define KORINA_CONFIG19_ADDR 0x8000004C
4435 +#define KORINA_CONFIG20_ADDR 0x80000050
4436 +#define KORINA_CONFIG21_ADDR 0x80000054
4437 +#define KORINA_CONFIG22_ADDR 0x80000058
4438 +#define KORINA_CONFIG23_ADDR 0x8000005C
4439 +#define KORINA_CONFIG24_ADDR 0x80000060
4440 +#define KORINA_CONFIG25_ADDR 0x80000064
4441 +#define KORINA_CMD (PCFG04_command_ioena_m | \
4442 + PCFG04_command_memena_m | \
4443 + PCFG04_command_bmena_m | \
4444 + PCFG04_command_mwinv_m | \
4445 + PCFG04_command_parena_m | \
4446 + PCFG04_command_serrena_m )
4447 +
4448 +#define KORINA_STAT (PCFG04_status_mdpe_m | \
4449 + PCFG04_status_sta_m | \
4450 + PCFG04_status_rta_m | \
4451 + PCFG04_status_rma_m | \
4452 + PCFG04_status_sse_m | \
4453 + PCFG04_status_pe_m)
4454 +
4455 +#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
4456 +
4457 +#define KORINA_REVID 0
4458 +#define KORINA_CLASS_CODE 0
4459 +#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
4460 + KORINA_REVID)
4461 +
4462 +#define KORINA_CACHE_LINE_SIZE 4
4463 +#define KORINA_MASTER_LAT 0x3c
4464 +#define KORINA_HEADER_TYPE 0
4465 +#define KORINA_BIST 0
4466 +
4467 +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
4468 + (KORINA_HEADER_TYPE<<16) | \
4469 + (KORINA_MASTER_LAT<<8) | \
4470 + KORINA_CACHE_LINE_SIZE )
4471 +
4472 +#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
4473 +#define KORINA_BAR1 0x18800001 /* 1 MB IO */
4474 +#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
4475 + internal Registers */
4476 +#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
4477 +
4478 +#define KORINA_CNFG4 KORINA_BAR0
4479 +#define KORINA_CNFG5 KORINA_BAR1
4480 +#define KORINA_CNFG6 KORINA_BAR2
4481 +#define KORINA_CNFG7 KORINA_BAR3
4482 +
4483 +#define KORINA_SUBSYS_VENDOR_ID 0x011d
4484 +#define KORINA_SUBSYSTEM_ID 0x0214
4485 +#define KORINA_CNFG8 0
4486 +#define KORINA_CNFG9 0
4487 +#define KORINA_CNFG10 0
4488 +#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
4489 + KORINA_SUBSYSTEM_ID)
4490 +#define KORINA_INT_LINE 1
4491 +#define KORINA_INT_PIN 1
4492 +#define KORINA_MIN_GNT 8
4493 +#define KORINA_MAX_LAT 0x38
4494 +#define KORINA_CNFG12 0
4495 +#define KORINA_CNFG13 0
4496 +#define KORINA_CNFG14 0
4497 +#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
4498 + (KORINA_MIN_GNT<<16) | \
4499 + (KORINA_INT_PIN<<8) | \
4500 + KORINA_INT_LINE)
4501 +#define KORINA_RETRY_LIMIT 0x80
4502 +#define KORINA_TRDY_LIMIT 0x80
4503 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
4504 + KORINA_TRDY_LIMIT)
4505 +#define PCI_PBAxC_R 0x0
4506 +#define PCI_PBAxC_RL 0x1
4507 +#define PCI_PBAxC_RM 0x2
4508 +#define SIZE_SHFT 2
4509 +
4510 +#if defined(__MIPSEB__)
4511 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
4512 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
4513 + PCIPBAC_pp_m | \
4514 + (SIZE_128MB<<SIZE_SHFT) | \
4515 + PCIPBAC_p_m)
4516 +#else
4517 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | \
4518 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
4519 + PCIPBAC_pp_m | \
4520 + (SIZE_128MB<<SIZE_SHFT) | \
4521 + PCIPBAC_p_m)
4522 +#endif
4523 +#define KORINA_CNFG17 KORINA_PBA0C
4524 +#define KORINA_PBA0M 0x0
4525 +#define KORINA_CNFG18 KORINA_PBA0M
4526 +
4527 +#if defined(__MIPSEB__)
4528 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
4529 + PCIPBAC_msi_m)
4530 +#else
4531 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
4532 + PCIPBAC_msi_m)
4533 +#endif
4534 +#define KORINA_CNFG19 KORINA_PBA1C
4535 +#define KORINA_PBA1M 0x0
4536 +#define KORINA_CNFG20 KORINA_PBA1M
4537 +
4538 +#if defined(__MIPSEB__)
4539 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
4540 + PCIPBAC_msi_m)
4541 +#else
4542 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
4543 + PCIPBAC_msi_m)
4544 +#endif
4545 +#define KORINA_CNFG21 KORINA_PBA2C
4546 +#define KORINA_PBA2M 0x18000000
4547 +#define KORINA_CNFG22 KORINA_PBA2M
4548 +#define KORINA_PBA3C 0
4549 +#define KORINA_CNFG23 KORINA_PBA3C
4550 +#define KORINA_PBA3M 0
4551 +#define KORINA_CNFG24 KORINA_PBA3M
4552 +
4553 +
4554 +
4555 +#define PCITC_DTIMER_VAL 8
4556 +#define PCITC_RTIMER_VAL 0x10
4557 +
4558 +
4559 +
4560 +
4561 +#endif // __IDT_PCI_H__
4562 +
4563 +
4564 +
4565 diff -urN linux.old/include/asm-mips/rc32434/pcikorina.h linux.dev/include/asm-mips/rc32434/pcikorina.h
4566 --- linux.old/include/asm-mips/rc32434/pcikorina.h 1970-01-01 01:00:00.000000000 +0100
4567 +++ linux.dev/include/asm-mips/rc32434/pcikorina.h 2006-12-14 04:09:50.000000000 +0100
4568 @@ -0,0 +1,209 @@
4569 +/* $Id: pciacacia.h,v 1.5 2001/05/01 10:09:17 carstenl Exp $
4570 + *
4571 + * This file is subject to the terms and conditions of the GNU General Public
4572 + * License. See the file "COPYING" in the main directory of this archive
4573 + * for more details.
4574 + */
4575 +#ifndef _PCIKORINA_H
4576 +#define _PCIKORINA_H
4577 +
4578 +
4579 +#define PCI_MSG_VirtualAddress 0xB8088010
4580 +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
4581 +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
4582 +
4583 +#define PCIM_SHFT 0x6
4584 +#define PCIM_BIT_LEN 0x7
4585 +#define PCIM_H_EA 0x3
4586 +#define PCIM_H_IA_FIX 0x4
4587 +#define PCIM_H_IA_RR 0x5
4588 +#if 0
4589 +#define PCI_ADDR_START 0x13000000
4590 +#endif
4591 +
4592 +#define PCI_ADDR_START 0x50000000
4593 +
4594 +#define CPUTOPCI_MEM_WIN 0x02000000
4595 +#define CPUTOPCI_IO_WIN 0x00100000
4596 +#define PCILBA_SIZE_SHFT 2
4597 +#define PCILBA_SIZE_MASK 0x1F
4598 +#define SIZE_256MB 0x1C
4599 +#define SIZE_128MB 0x1B
4600 +#define SIZE_64MB 0x1A
4601 +#define SIZE_32MB 0x19
4602 +#define SIZE_16MB 0x18
4603 +#define SIZE_4MB 0x16
4604 +#define SIZE_2MB 0x15
4605 +#define SIZE_1MB 0x14
4606 +#define KORINA_CONFIG0_ADDR 0x80000000
4607 +#define KORINA_CONFIG1_ADDR 0x80000004
4608 +#define KORINA_CONFIG2_ADDR 0x80000008
4609 +#define KORINA_CONFIG3_ADDR 0x8000000C
4610 +#define KORINA_CONFIG4_ADDR 0x80000010
4611 +#define KORINA_CONFIG5_ADDR 0x80000014
4612 +#define KORINA_CONFIG6_ADDR 0x80000018
4613 +#define KORINA_CONFIG7_ADDR 0x8000001C
4614 +#define KORINA_CONFIG8_ADDR 0x80000020
4615 +#define KORINA_CONFIG9_ADDR 0x80000024
4616 +#define KORINA_CONFIG10_ADDR 0x80000028
4617 +#define KORINA_CONFIG11_ADDR 0x8000002C
4618 +#define KORINA_CONFIG12_ADDR 0x80000030
4619 +#define KORINA_CONFIG13_ADDR 0x80000034
4620 +#define KORINA_CONFIG14_ADDR 0x80000038
4621 +#define KORINA_CONFIG15_ADDR 0x8000003C
4622 +#define KORINA_CONFIG16_ADDR 0x80000040
4623 +#define KORINA_CONFIG17_ADDR 0x80000044
4624 +#define KORINA_CONFIG18_ADDR 0x80000048
4625 +#define KORINA_CONFIG19_ADDR 0x8000004C
4626 +#define KORINA_CONFIG20_ADDR 0x80000050
4627 +#define KORINA_CONFIG21_ADDR 0x80000054
4628 +#define KORINA_CONFIG22_ADDR 0x80000058
4629 +#define KORINA_CONFIG23_ADDR 0x8000005C
4630 +#define KORINA_CONFIG24_ADDR 0x80000060
4631 +#define KORINA_CONFIG25_ADDR 0x80000064
4632 +#define KORINA_CMD (PCFG04_command_ioena_m | \
4633 + PCFG04_command_memena_m | \
4634 + PCFG04_command_bmena_m | \
4635 + PCFG04_command_mwinv_m | \
4636 + PCFG04_command_parena_m | \
4637 + PCFG04_command_serrena_m )
4638 +
4639 +#define KORINA_STAT (PCFG04_status_mdpe_m | \
4640 + PCFG04_status_sta_m | \
4641 + PCFG04_status_rta_m | \
4642 + PCFG04_status_rma_m | \
4643 + PCFG04_status_sse_m | \
4644 + PCFG04_status_pe_m)
4645 +
4646 +#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
4647 +
4648 +#define KORINA_REVID 0
4649 +#define KORINA_CLASS_CODE 0
4650 +#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
4651 + KORINA_REVID)
4652 +
4653 +#define KORINA_CACHE_LINE_SIZE 4
4654 +#define KORINA_MASTER_LAT 0x3c
4655 +#define KORINA_HEADER_TYPE 0
4656 +#define KORINA_BIST 0
4657 +
4658 +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
4659 + (KORINA_HEADER_TYPE<<16) | \
4660 + (KORINA_MASTER_LAT<<8) | \
4661 + KORINA_CACHE_LINE_SIZE )
4662 +
4663 +#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
4664 +#define KORINA_BAR1 0x18800001 /* 1 MB IO */
4665 +#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Acacia
4666 + internal Registers */
4667 +#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
4668 +
4669 +#define KORINA_CNFG4 KORINA_BAR0
4670 +#define KORINA_CNFG5 KORINA_BAR1
4671 +#define KORINA_CNFG6 KORINA_BAR2
4672 +#define KORINA_CNFG7 KORINA_BAR3
4673 +
4674 +#define KORINA_SUBSYS_VENDOR_ID 0
4675 +#define KORINA_SUBSYSTEM_ID 0
4676 +#define KORINA_CNFG8 0
4677 +#define KORINA_CNFG9 0
4678 +#define KORINA_CNFG10 0
4679 +#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
4680 + KORINA_SUBSYSTEM_ID)
4681 +#define KORINA_INT_LINE 1
4682 +#define KORINA_INT_PIN 1
4683 +#define KORINA_MIN_GNT 8
4684 +#define KORINA_MAX_LAT 0x38
4685 +#define KORINA_CNFG12 0
4686 +#define KORINA_CNFG13 0
4687 +#define KORINA_CNFG14 0
4688 +#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
4689 + (KORINA_MIN_GNT<<16) | \
4690 + (KORINA_INT_PIN<<8) | \
4691 + KORINA_INT_LINE)
4692 +#define KORINA_RETRY_LIMIT 0x80
4693 +#define KORINA_TRDY_LIMIT 0x80
4694 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
4695 + KORINA_TRDY_LIMIT)
4696 +#define PCI_PBAxC_R 0x0
4697 +#define PCI_PBAxC_RL 0x1
4698 +#define PCI_PBAxC_RM 0x2
4699 +#define SIZE_SHFT 2
4700 +
4701 +#ifdef __MIPSEB__
4702 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
4703 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
4704 + PCIPBAC_pp_m | \
4705 + (SIZE_32MB<<SIZE_SHFT) | \
4706 + PCIPBAC_p_m)
4707 +#else
4708 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | \
4709 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
4710 + PCIPBAC_pp_m | \
4711 + (SIZE_32MB<<SIZE_SHFT) | \
4712 + PCIPBAC_p_m)
4713 +#endif
4714 +
4715 +#if 0
4716 +
4717 +#define KORINA_PBA0C ( PCIPBAC_sb_m | PCIPBAC_pp_m | \
4718 + ((PCI_PBAxC_R &0x3) << PCIPBAC_mr_b) | \
4719 + (SIZE_128MB<<SIZE_SHFT))
4720 +#endif
4721 +#define KORINA_CNFG17 KORINA_PBA0C
4722 +#define KORINA_PBA0M 0x0
4723 +#define KORINA_CNFG18 KORINA_PBA0M
4724 +
4725 +#ifdef __MIPSEB__
4726 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
4727 + PCIPBAC_msi_m)
4728 +#else
4729 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
4730 + PCIPBAC_msi_m)
4731 +
4732 +#endif
4733 +
4734 +#define KORINA_CNFG19 KORINA_PBA1C
4735 +#define KORINA_PBA1M 0x0
4736 +#define KORINA_CNFG20 KORINA_PBA1M
4737 +
4738 +#ifdef __MIPSEB__
4739 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
4740 + PCIPBAC_msi_m)
4741 +#else
4742 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
4743 + PCIPBAC_msi_m)
4744 +
4745 +#endif
4746 +#define KORINA_CNFG21 KORINA_PBA2C
4747 +#define KORINA_PBA2M 0x18000000
4748 +#define KORINA_CNFG22 KORINA_PBA2M
4749 +#define KORINA_PBA3C 0
4750 +#define KORINA_CNFG23 KORINA_PBA3C
4751 +#define KORINA_PBA3M 0
4752 +#define KORINA_CNFG24 KORINA_PBA3M
4753 +
4754 +
4755 +
4756 +#define PCITC_DTIMER_VAL 8
4757 +#define PCITC_RTIMER_VAL 0x10
4758 +
4759 +
4760 +#endif /* _PCIKORINA_H */
4761 +
4762 +
4763 +
4764 +
4765 +
4766 +
4767 +
4768 +
4769 +
4770 +
4771 +
4772 +
4773 +
4774 +
4775 +
4776 +
4777 +
4778 diff -urN linux.old/include/asm-mips/rc32434/pci_regs.h linux.dev/include/asm-mips/rc32434/pci_regs.h
4779 --- linux.old/include/asm-mips/rc32434/pci_regs.h 1970-01-01 01:00:00.000000000 +0100
4780 +++ linux.dev/include/asm-mips/rc32434/pci_regs.h 2006-12-14 04:09:50.000000000 +0100
4781 @@ -0,0 +1,8 @@
4782 +/* Override the default address space for this arch
4783 +*/
4784 +
4785 +#include <linux/pci_regs.h>
4786 +
4787 +//#undef PCI_BASE_ADDRESS_SPACE
4788 +//#define PCI_BASE_ADDRESS_SPACE PCI_BASE_ADDRESS_SPACE_MEMORY
4789 +
4790 diff -urN linux.old/include/asm-mips/rc32434/rb.h linux.dev/include/asm-mips/rc32434/rb.h
4791 --- linux.old/include/asm-mips/rc32434/rb.h 1970-01-01 01:00:00.000000000 +0100
4792 +++ linux.dev/include/asm-mips/rc32434/rb.h 2006-12-14 04:09:50.000000000 +0100
4793 @@ -0,0 +1,84 @@
4794 +/*
4795 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
4796 + *
4797 + * This program is free software; you can redistribute it and/or modify
4798 + * it under the terms of the GNU General Public License as published by
4799 + * the Free Software Foundation; either version 2 of the License, or
4800 + * (at your option) any later version.
4801 + *
4802 + * This program is distributed in the hope that it will be useful,
4803 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4804 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4805 + * GNU General Public License for more details.
4806 + *
4807 + * $Id$
4808 + */
4809 +#ifndef __MIPS_RB_H__
4810 +#define __MIPS_RB_H__
4811 +#include <linux/genhd.h>
4812 +
4813 +#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000))
4814 +#define DEV0BASE 0x010000
4815 +#define DEV0MASK 0x010004
4816 +#define DEV0C 0x010008
4817 +#define DEV0TC 0x01000C
4818 +#define DEV1BASE 0x010010
4819 +#define DEV1MASK 0x010014
4820 +#define DEV1C 0x010018
4821 +#define DEV1TC 0x01001C
4822 +#define DEV2BASE 0x010020
4823 +#define DEV2MASK 0x010024
4824 +#define DEV2C 0x010028
4825 +#define DEV2TC 0x01002C
4826 +#define DEV3BASE 0x010030
4827 +#define DEV3MASK 0x010034
4828 +#define DEV3C 0x010038
4829 +#define DEV3TC 0x01003C
4830 +#define BTCS 0x010040
4831 +#define BTCOMPARE 0x010044
4832 +#define GPIOFUNC 0x050000
4833 +#define GPIOCFG 0x050004
4834 +#define GPIOD 0x050008
4835 +#define GPIOILEVEL 0x05000C
4836 +#define GPIOISTAT 0x050010
4837 +#define GPIONMIEN 0x050014
4838 +#define IMASK6 0x038038
4839 +
4840 +#define LO_WPX (1 << 0)
4841 +#define LO_ALE (1 << 1)
4842 +#define LO_CLE (1 << 2)
4843 +#define LO_CEX (1 << 3)
4844 +#define LO_FOFF (1 << 5)
4845 +#define LO_SPICS (1 << 6)
4846 +#define LO_ULED (1 << 7)
4847 +
4848 +typedef enum {
4849 + FUNC = 0x00,
4850 + CFG = 0x04,
4851 + DATA = 0x08,
4852 + ILEVEL = 0x0c,
4853 + ISTAT = 0x10,
4854 + NMIEN = 0x14
4855 +} gpio_func;
4856 +
4857 +extern void changeLatchU5(unsigned char orMask, unsigned char nandMask);
4858 +extern unsigned get434Reg(unsigned regOffs);
4859 +extern void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val);
4860 +extern void gpio_set(gpio_func func, u32 mask, u32 value);
4861 +extern u32 gpio_get(gpio_func func);
4862 +
4863 +#define get434Reg(x) (*(volatile unsigned *) (IDT434_REG_BASE + (x)))
4864 +
4865 +struct korina_device {
4866 + char *name;
4867 + unsigned char mac[6];
4868 + struct net_device *dev;
4869 +};
4870 +
4871 +struct cf_device {
4872 + int gpio_pin;
4873 + void *dev;
4874 + struct gendisk *gd;
4875 +};
4876 +
4877 +#endif
4878 diff -urN linux.old/include/asm-mips/rc32434/rc32434.h linux.dev/include/asm-mips/rc32434/rc32434.h
4879 --- linux.old/include/asm-mips/rc32434/rc32434.h 1970-01-01 01:00:00.000000000 +0100
4880 +++ linux.dev/include/asm-mips/rc32434/rc32434.h 2006-12-14 04:09:50.000000000 +0100
4881 @@ -0,0 +1,126 @@
4882 +/*
4883 + ***************************************************************************
4884 + * Definitions for IDT RC323434 CPU.
4885 + *
4886 + ****************************************************************************
4887 + * Kiran Rao
4888 + *
4889 + * Original form
4890 + ****************************************************************************
4891 + * P. Sadik Oct 08, 2003
4892 + *
4893 + * Started revision history
4894 + * Made IDT_BUS_FREQ a kernel configuration parameter
4895 + ****************************************************************************
4896 + * P. Sadik Oct 10, 2003
4897 + *
4898 + * Removed IDT_BUS_FREQ, since this parameter is no longer required. Instead
4899 + * idt_cpu_freq is used everywhere
4900 + ****************************************************************************
4901 + * P. Sadik Oct 20, 2003
4902 + *
4903 + * Removed RC32434_BASE_BAUD
4904 + ****************************************************************************
4905 +*/
4906 +#ifndef _RC32434_H_
4907 +#define _RC32434_H_
4908 +
4909 +#include <linux/autoconf.h>
4910 +#include <linux/delay.h>
4911 +#include <asm/io.h>
4912 +#include <asm/rc32434/timer.h>
4913 +
4914 +#define RC32434_REG_BASE 0x18000000
4915 +
4916 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
4917 +#define timer ((volatile TIM_t) TIM0_VirtualAddress)
4918 +#define gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
4919 +
4920 +#define IDT_CLOCK_MULT 2
4921 +#define MIPS_CPU_TIMER_IRQ 7
4922 +/* Interrupt Controller */
4923 +#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
4924 +#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
4925 +#define IC_GROUP_OFFSET 0x0C
4926 +
4927 +#define NUM_INTR_GROUPS 5
4928 +/* 16550 UARTs */
4929 +
4930 +#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
4931 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
4932 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
4933 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
4934 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
4935 +
4936 +
4937 +#ifdef __MIPSEB__
4938 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
4939 +#else
4940 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
4941 +#endif
4942 +
4943 +#define RC32434_UART0_IRQ GROUP3_IRQ_BASE + 0
4944 +// #define EB434_UART1_IRQ GROUP4_IRQ_BASE + 11
4945 +
4946 +#define local_readl(addr) __raw_readl(addr)
4947 +#define local_writel(l,addr) __raw_writel(l,addr)
4948 +
4949 +/* cpu pipeline flush */
4950 +static inline void rc32434_sync(void)
4951 +{
4952 + __asm__ volatile ("sync");
4953 +}
4954 +
4955 +static inline void rc32434_sync_udelay(int us)
4956 +{
4957 + __asm__ volatile ("sync");
4958 + udelay(us);
4959 +}
4960 +
4961 +static inline void rc32434_sync_delay(int ms)
4962 +{
4963 + __asm__ volatile ("sync");
4964 + mdelay(ms);
4965 +}
4966 +
4967 +/*
4968 + * C access to CLZ and CLO instructions
4969 + * (count leading zeroes/ones).
4970 + */
4971 +static inline int rc32434_clz(unsigned long val)
4972 +{
4973 + int ret;
4974 + __asm__ volatile (
4975 + ".set\tnoreorder\n\t"
4976 + ".set\tnoat\n\t"
4977 + ".set\tmips32\n\t"
4978 + "clz\t%0,%1\n\t"
4979 + ".set\tmips0\n\t"
4980 + ".set\tat\n\t"
4981 + ".set\treorder"
4982 + : "=r" (ret)
4983 + : "r" (val));
4984 +
4985 + return ret;
4986 +}
4987 +static inline int rc32434_clo(unsigned long val)
4988 +{
4989 + int ret;
4990 + __asm__ volatile (
4991 + ".set\tnoreorder\n\t"
4992 + ".set\tnoat\n\t"
4993 + ".set\tmips32\n\t"
4994 + "clo\t%0,%1\n\t"
4995 + ".set\tmips0\n\t"
4996 + ".set\tat\n\t"
4997 + ".set\treorder"
4998 + : "=r" (ret)
4999 + : "r" (val));
5000 +
5001 + return ret;
5002 +}
5003 +
5004 +extern void cons_putc(char c);
5005 +extern void cons_puts(char *s);
5006 +
5007 +#endif /* _RC32434_H_ */
5008 diff -urN linux.old/include/asm-mips/rc32434/rst.h linux.dev/include/asm-mips/rc32434/rst.h
5009 --- linux.old/include/asm-mips/rc32434/rst.h 1970-01-01 01:00:00.000000000 +0100
5010 +++ linux.dev/include/asm-mips/rc32434/rst.h 2006-12-14 04:09:50.000000000 +0100
5011 @@ -0,0 +1,105 @@
5012 +#ifndef __IDT_RST_H__
5013 +#define __IDT_RST_H__
5014 +
5015 +/*******************************************************************************
5016 + *
5017 + * Copyright 2002 Integrated Device Technology, Inc.
5018 + * All rights reserved.
5019 + *
5020 + * Reset register definitions.
5021 + *
5022 + * File : $Id: rst.h,v 1.2 2002/06/06 18:34:05 astichte Exp $
5023 + *
5024 + * Author : Allen.Stichter@idt.com
5025 + * Date : 20020118
5026 + * Update :
5027 + * $Log: rst.h,v $
5028 + * Revision 1.2 2002/06/06 18:34:05 astichte
5029 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
5030 + *
5031 + * Revision 1.1 2002/05/29 17:33:24 sysarch
5032 + * jba File moved from vcode/include/idt/acacia
5033 + *
5034 + *
5035 + ******************************************************************************/
5036 +
5037 +#include <asm/rc32434/types.h>
5038 +
5039 +enum
5040 +{
5041 + RST0_PhysicalAddress = 0x18000000,
5042 + RST_PhysicalAddress = RST0_PhysicalAddress, // Default
5043 +
5044 + RST0_VirtualAddress = 0xb8000000,
5045 + RST_VirtualAddress = RST0_VirtualAddress, // Default
5046 +} ;
5047 +
5048 +typedef struct RST_s
5049 +{
5050 + U32 filler [0x0006] ;
5051 + U32 sysid ;
5052 + U32 filler2 [0x2000-8] ; // Pad out to offset 0x8000
5053 + U32 reset ;
5054 + U32 bcv ;
5055 + U32 cea ;
5056 +} volatile * RST_t ;
5057 +
5058 +enum
5059 +{
5060 + SYSID_rev_b = 0,
5061 + SYSID_rev_m = 0x000000ff,
5062 + SYSID_imp_b = 8,
5063 + SYSID_imp_m = 0x000fff00,
5064 + SYSID_vendor_b = 20,
5065 + SYSID_vendor_m = 0xfff00000,
5066 +
5067 + BCV_pll_b = 0,
5068 + BCV_pll_m = 0x0000000f,
5069 + BCV_pll_PLLBypass_v = 0x0, // PCLK=1*CLK.
5070 + BCV_pll_Mul3_v = 0x1, // PCLK=3*CLK.
5071 + BCV_pll_Mul4_v = 0x2, // PCLK=4*CLK.
5072 + BCV_pll_SlowMul5_v = 0x3, // PCLK=4*CLK.
5073 + BCV_pll_Mul5_v = 0x4, // PCLK=6*CLK.
5074 + BCV_pll_SlowMul6_v = 0x5, // PCLK=8*CLK.
5075 + BCV_pll_Mul6_v = 0x6, // PCLK=8*CLK.
5076 + BCV_pll_Mul8_v = 0x7, // PCLK=8*CLK.
5077 + BCV_pll_Mul10_v = 0x8, // PCLK=8*CLK.
5078 + BCV_pll_Res5_v = 0x9,
5079 + BCV_pll_Res6_v = 0xa,
5080 + BCV_pll_Res7_v = 0xb,
5081 + BCV_pll_Res8_v = 0xc,
5082 + BCV_pll_Res13_v = 0xd,
5083 + BCV_pll_Res14_v = 0xe,
5084 + BCV_pll_Res15_v = 0xf,
5085 + BCV_clkDiv_b = 4,
5086 + BCV_clkDiv_m = 0x00000030,
5087 + BCV_clkDiv_Div1_v = 0x0,
5088 + BCV_clkDiv_Div2_v = 0x1,
5089 + BCV_clkDiv_Div4_v = 0x2,
5090 + BCV_clkDiv_Res3_v = 0x3,
5091 + BCV_bigEndian_b = 6,
5092 + BCV_bigEndian_m = 0x00000040,
5093 + BCV_resetFast_b = 7,
5094 + BCV_resetFast_m = 0x00000080,
5095 + BCV_pciMode_b = 8,
5096 + BCV_pciMode_m = 0x00000100,
5097 + BCV_pciMode_disabled_v = 0, // PCI is disabled.
5098 + BCV_pciMode_tnr_v = 1, // satellite Target Not Ready.
5099 + BCV_pciMode_suspended_v = 2, // satellite with suspended CPU.
5100 + BCV_pciMode_external_v = 3, // host, external arbiter.
5101 + BCV_pciMode_fixed_v = 4, // host, fixed priority arbiter.
5102 + BCV_pciMode_roundRobin_v= 5, // host, round robin arbiter.
5103 + BCV_pciMode_res6_v = 6,
5104 + BCV_pciMode_res7_v = 7,
5105 + BCV_watchDisable_b = 11,
5106 + BCV_watchDisable_m = 0x00000800,
5107 + BCV_pllTest_b = 12,
5108 + BCV_pllTest_m = 0x00001000,
5109 + BCV_nvramInit_b = 13,
5110 + BCV_nvramInit_m = 0x00002000,
5111 + BCV_clksyncTstMd_b = 14,
5112 + BCV_clksyncTstMd_m = 0x00004000,
5113 + BCV_delayBypass_b = 15,
5114 + BCV_delayByPass_m = 0x00008000,
5115 +} ;
5116 +#endif // __IDT_RST_H__
5117 diff -urN linux.old/include/asm-mips/rc32434/spi.h linux.dev/include/asm-mips/rc32434/spi.h
5118 --- linux.old/include/asm-mips/rc32434/spi.h 1970-01-01 01:00:00.000000000 +0100
5119 +++ linux.dev/include/asm-mips/rc32434/spi.h 2006-12-14 04:09:50.000000000 +0100
5120 @@ -0,0 +1,100 @@
5121 +#ifndef __IDT_SPI_H__
5122 +#define __IDT_SPI_H__
5123 +
5124 +/*******************************************************************************
5125 + *
5126 + * Copyright 2002 Integrated Device Technology, Inc.
5127 + * All rights reserved.
5128 + *
5129 + * Serial Peripheral Interface register definitions.
5130 + *
5131 + * File : $Id: spi.h,v 1.2 2002/06/06 18:34:05 astichte Exp $
5132 + *
5133 + * Author : ryan.holmQVist@idt.com
5134 + * Date : 20011005
5135 + * Update :
5136 + * $Log: spi.h,v $
5137 + * Revision 1.2 2002/06/06 18:34:05 astichte
5138 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
5139 + *
5140 + * Revision 1.1 2002/05/29 17:33:25 sysarch
5141 + * jba File moved from vcode/include/idt/acacia
5142 + *
5143 + *
5144 + ******************************************************************************/
5145 +
5146 +#include <asm/rc32434/types.h>
5147 +
5148 +enum
5149 +{
5150 + SPI0_PhysicalAddress = 0x18070000,
5151 + SPI_PhysicalAddress = SPI0_PhysicalAddress,
5152 +
5153 + SPI0_VirtualAddress = 0xb8070000,
5154 + SPI_VirtualAddress = SPI0_VirtualAddress,
5155 +} ;
5156 +
5157 +typedef struct
5158 +{
5159 + U32 spcp ; // prescalar. 0=off, * spiClk = sysClk/(2*(spcp+1)*SPR)
5160 + U32 spc ; // spi control reg use SPC_
5161 + U32 sps ; // spi status reg use SPS_
5162 + U32 spd ; // spi data reg use SPD_
5163 + U32 siofunc ; // serial IO function use SIOFUNC_
5164 + U32 siocfg ; // serial IO config use SIOCFG_
5165 + U32 siod; // serial IO data use SIOD_
5166 +} volatile *SPI_t ;
5167 +
5168 +enum
5169 +{
5170 + SPCP_div_b = 0,
5171 + SPCP_div_m = 0x000000ff,
5172 + SPC_spr_b = 0,
5173 + SPC_spr_m = 0x00000003,
5174 + SPC_spr_div2_v = 0,
5175 + SPC_spr_div4_v = 1,
5176 + SPC_spr_div16_v = 2,
5177 + SPC_spr_div32_v = 3,
5178 + SPC_cpha_b = 2,
5179 + SPC_cpha_m = 0x00000004,
5180 + SPC_cpol_b = 3,
5181 + SPC_cpol_m = 0x00000008,
5182 + SPC_mstr_b = 4,
5183 + SPC_mstr_m = 0x00000010,
5184 + SPC_spe_b = 6,
5185 + SPC_spe_m = 0x00000040,
5186 + SPC_spie_b = 7,
5187 + SPC_spie_m = 0x00000080,
5188 +
5189 + SPS_modf_b = 4,
5190 + SPS_modf_m = 0x00000010,
5191 + SPS_wcol_b = 6,
5192 + SPS_wcol_m = 0x00000040,
5193 + SPS_spif_b = 7,
5194 + SPS_spif_m = 0x00000070,
5195 +
5196 + SPD_data_b = 0,
5197 + SPD_data_m = 0x000000ff,
5198 +
5199 + SIOFUNC_sdo_b = 0,
5200 + SIOFUNC_sdo_m = 0x00000001,
5201 + SIOFUNC_sdi_b = 1,
5202 + SIOFUNC_sdi_m = 0x00000002,
5203 + SIOFUNC_sck_b = 2,
5204 + SIOFUNC_sck_m = 0x00000004,
5205 +
5206 + SIOCFG_sdo_b = 0,
5207 + SIOCFG_sdo_m = 0x00000001,
5208 + SIOCFG_sdi_b = 1,
5209 + SIOCFG_sdi_m = 0x00000002,
5210 + SIOCFG_sck_b = 2,
5211 + SIOCFG_sck_m = 0x00000004,
5212 +
5213 + SIOD_sdo_b = 0,
5214 + SIOD_sdo_m = 0x00000001,
5215 + SIOD_sdi_b = 1,
5216 + SIOD_sdi_m = 0x00000002,
5217 + SIOD_sck_b = 2,
5218 + SIOD_sck_m = 0x00000004,
5219 +} ;
5220 +#endif // __IDT_SPI_H__
5221 diff -urN linux.old/include/asm-mips/rc32434/timer.h linux.dev/include/asm-mips/rc32434/timer.h
5222 --- linux.old/include/asm-mips/rc32434/timer.h 1970-01-01 01:00:00.000000000 +0100
5223 +++ linux.dev/include/asm-mips/rc32434/timer.h 2006-12-14 04:09:50.000000000 +0100
5224 @@ -0,0 +1,91 @@
5225 +/**************************************************************************
5226 + *
5227 + * BRIEF MODULE DESCRIPTION
5228 + * Definitions for timer registers
5229 + *
5230 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5231 + *
5232 + * This program is free software; you can redistribute it and/or modify it
5233 + * under the terms of the GNU General Public License as published by the
5234 + * Free Software Foundation; either version 2 of the License, or (at your
5235 + * option) any later version.
5236 + *
5237 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5238 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5239 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5240 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5241 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5242 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5243 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5244 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5245 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5246 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5247 + *
5248 + * You should have received a copy of the GNU General Public License along
5249 + * with this program; if not, write to the Free Software Foundation, Inc.,
5250 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5251 + *
5252 + *
5253 + **************************************************************************
5254 + * May 2004 rkt,neb.
5255 + *
5256 + * Initial Release
5257 + *
5258 + *
5259 + *
5260 + **************************************************************************
5261 + */
5262 +
5263 +#ifndef __IDT_TIM_H__
5264 +#define __IDT_TIM_H__
5265 +
5266 +enum
5267 +{
5268 + TIM0_PhysicalAddress = 0x18028000,
5269 + TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
5270 +
5271 + TIM0_VirtualAddress = 0xb8028000,
5272 + TIM_VirtualAddress = TIM0_VirtualAddress, // Default
5273 +} ;
5274 +
5275 +enum
5276 +{
5277 + TIM_Count = 3,
5278 +} ;
5279 +
5280 +struct TIM_CNTR_s
5281 +{
5282 + u32 count ;
5283 + u32 compare ;
5284 + u32 ctc ; //use CTC_
5285 +} ;
5286 +
5287 +typedef struct TIM_s
5288 +{
5289 + struct TIM_CNTR_s tim [TIM_Count] ;
5290 + u32 rcount ; //use RCOUNT_
5291 + u32 rcompare ; //use RCOMPARE_
5292 + u32 rtc ; //use RTC_
5293 +} volatile * TIM_t ;
5294 +
5295 +enum
5296 +{
5297 + CTC_en_b = 0,
5298 + CTC_en_m = 0x00000001,
5299 + CTC_to_b = 1,
5300 + CTC_to_m = 0x00000002,
5301 +
5302 + RCOUNT_count_b = 0,
5303 + RCOUNT_count_m = 0x0000ffff,
5304 + RCOMPARE_compare_b = 0,
5305 + RCOMPARE_compare_m = 0x0000ffff,
5306 + RTC_ce_b = 0,
5307 + RTC_ce_m = 0x00000001,
5308 + RTC_to_b = 1,
5309 + RTC_to_m = 0x00000002,
5310 + RTC_rqe_b = 2,
5311 + RTC_rqe_m = 0x00000004,
5312 +
5313 +} ;
5314 +#endif // __IDT_TIM_H__
5315 +
5316 diff -urN linux.old/include/asm-mips/rc32434/tim.h linux.dev/include/asm-mips/rc32434/tim.h
5317 --- linux.old/include/asm-mips/rc32434/tim.h 1970-01-01 01:00:00.000000000 +0100
5318 +++ linux.dev/include/asm-mips/rc32434/tim.h 2006-12-14 04:09:50.000000000 +0100
5319 @@ -0,0 +1,78 @@
5320 +#ifndef __IDT_TIM_H__
5321 +#define __IDT_TIM_H__
5322 +
5323 +/*******************************************************************************
5324 + *
5325 + * Copyright 2002 Integrated Device Technology, Inc.
5326 + * All rights reserved.
5327 + *
5328 + * Timer register definition.
5329 + *
5330 + * File : $Id: tim.h,v 1.2 2002/06/06 18:34:05 astichte Exp $
5331 + *
5332 + * Author : ryan.holmQVist@idt.com
5333 + * Date : 20011005
5334 + * Update :
5335 + * $Log: tim.h,v $
5336 + * Revision 1.2 2002/06/06 18:34:05 astichte
5337 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
5338 + *
5339 + * Revision 1.1 2002/05/29 17:33:25 sysarch
5340 + * jba File moved from vcode/include/idt/acacia
5341 + *
5342 + *
5343 + ******************************************************************************/
5344 +
5345 +
5346 +#include <asm/rc32434/types.h>
5347 +
5348 +enum
5349 +{
5350 + TIM0_PhysicalAddress = 0x18028000,
5351 + TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
5352 +
5353 + TIM0_VirtualAddress = 0xb8028000,
5354 + TIM_VirtualAddress = TIM0_VirtualAddress, // Default
5355 +} ;
5356 +
5357 +enum
5358 +{
5359 + TIM_Count = 3,
5360 +} ;
5361 +
5362 +struct TIM_CNTR_s
5363 +{
5364 + U32 count ;
5365 + U32 compare ;
5366 + U32 ctc ; //use CTC_
5367 +} ;
5368 +
5369 +typedef struct TIM_s
5370 +{
5371 + struct TIM_CNTR_s tim [TIM_Count] ;
5372 + U32 rcount ; //use RCOUNT_
5373 + U32 rcompare ; //use RCOMPARE_
5374 + U32 rtc ; //use RTC_
5375 +} volatile * TIM_t ;
5376 +
5377 +enum
5378 +{
5379 + CTC_en_b = 0,
5380 + CTC_en_m = 0x00000001,
5381 + CTC_to_b = 1,
5382 + CTC_to_m = 0x00000002,
5383 +
5384 + RCOUNT_count_b = 0,
5385 + RCOUNT_count_m = 0x0000ffff,
5386 + RCOMPARE_compare_b = 0,
5387 + RCOMPARE_compare_m = 0x0000ffff,
5388 + RTC_ce_b = 0,
5389 + RTC_ce_m = 0x00000001,
5390 + RTC_to_b = 1,
5391 + RTC_to_m = 0x00000002,
5392 + RTC_rqe_b = 2,
5393 + RTC_rqe_m = 0x00000004,
5394 +
5395 +} ;
5396 +#endif // __IDT_TIM_H__
5397 +
5398 diff -urN linux.old/include/asm-mips/rc32434/types.h linux.dev/include/asm-mips/rc32434/types.h
5399 --- linux.old/include/asm-mips/rc32434/types.h 1970-01-01 01:00:00.000000000 +0100
5400 +++ linux.dev/include/asm-mips/rc32434/types.h 2006-12-14 04:10:43.000000000 +0100
5401 @@ -0,0 +1,35 @@
5402 +#ifndef __IDT_TYPES_H__
5403 +#define __IDT_TYPES_H__
5404 +
5405 +/*******************************************************************************
5406 + *
5407 + * Copyright 2002 Integrated Device Technology, Inc.
5408 + * All rights reserved.
5409 + *
5410 + * Common typedefs used in IDT-generated code.
5411 + *
5412 + * File : $Id: types.h,v 1.1 2002/06/06 16:16:56 astichte Exp $
5413 + *
5414 + * Author : Allen.Stichter@idt.com
5415 + * Date : 20020606
5416 + * Update :
5417 + * $Log: types.h,v $
5418 + * Revision 1.1 2002/06/06 16:16:56 astichte
5419 + * Added
5420 + *
5421 + *
5422 + ******************************************************************************/
5423 +
5424 +typedef unsigned char U8 ;
5425 +typedef signed char S8 ;
5426 +
5427 +typedef unsigned short U16 ;
5428 +typedef signed short S16 ;
5429 +
5430 +typedef unsigned int U32 ;
5431 +typedef signed int S32 ;
5432 +
5433 +typedef unsigned long long U64 ;
5434 +typedef signed long long S64 ;
5435 +
5436 +#endif // __IDT_TYPES_H__
5437 diff -urN linux.old/include/asm-mips/rc32434/uart.h linux.dev/include/asm-mips/rc32434/uart.h
5438 --- linux.old/include/asm-mips/rc32434/uart.h 1970-01-01 01:00:00.000000000 +0100
5439 +++ linux.dev/include/asm-mips/rc32434/uart.h 2006-12-14 04:09:50.000000000 +0100
5440 @@ -0,0 +1,178 @@
5441 +#ifndef __IDT_UART_H__
5442 +#define __IDT_UART_H__
5443 +
5444 +/*******************************************************************************
5445 + *
5446 + * Copyright 2002 Integrated Device Technology, Inc.
5447 + * All rights reserved.
5448 + *
5449 + * UART register definitions.
5450 + *
5451 + * File : $Id: uart.h,v 1.3 2002/06/06 18:34:05 astichte Exp $
5452 + *
5453 + * Author : Allen.Stichter@idt.com
5454 + * Date : 20020118
5455 + * Update :
5456 + * $Log: uart.h,v $
5457 + * Revision 1.3 2002/06/06 18:34:05 astichte
5458 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
5459 + *
5460 + * Revision 1.2 2002/06/04 17:37:52 astichte
5461 + * Updated register definitions.
5462 + *
5463 + * Revision 1.1 2002/05/29 17:33:25 sysarch
5464 + * jba File moved from vcode/include/idt/acacia
5465 + *
5466 + *
5467 + ******************************************************************************/
5468 +
5469 +#include <asm/rc32434/types.h>
5470 +
5471 +enum
5472 +{
5473 + UART_PhysicalAddress = 0x18058000,
5474 + UART_PhysicalAddress = UART_PhysicalAddress, // Default
5475 +
5476 + UART_VirtualAddress = 0xb8058000,
5477 + UART_VirtualAddress = UART_VirtualAddress, // Default
5478 +} ;
5479 +
5480 +/*
5481 + * Register definitions are in bytes so we can handle endian problems.
5482 + */
5483 +
5484 +typedef struct UART_s
5485 +{
5486 + union
5487 + {
5488 + U32 const uartrb ; // 0x00 - DLAB=0, read.
5489 + U32 uartth ; // 0x00 - DLAB=0, write.
5490 + U32 uartdll ; // 0x00 - DLAB=1, read/write.
5491 + } ;
5492 +
5493 + union
5494 + {
5495 + U32 uartie ; // 0x04 - DLAB=0, read/write.
5496 + U32 uartdlh ; // 0x04 - DLAB=1, read/write.
5497 + } ;
5498 + union
5499 + {
5500 + U32 const uartii ; // 0x08 - DLAB=0, read.
5501 + U32 uartfc ; // 0x08 - DLAB=0, write.
5502 + } ;
5503 +
5504 + U32 uartlc ; // 0x0c
5505 + U32 uartmc ; // 0x10
5506 + U32 uartls ; // 0x14
5507 + U32 uartms ; // 0x18
5508 + U32 uarts ; // 0x1c
5509 +} volatile *UART_t ;
5510 +
5511 +// Reset registers.
5512 +typedef U32 volatile *UARTRR_t ;
5513 +
5514 +enum
5515 +{
5516 + UARTIE_rda_b = 0,
5517 + UARTIE_rda_m = 0x00000001,
5518 + UARTIE_the_b = 1,
5519 + UARTIE_the_m = 0x00000002,
5520 + UARTIE_rls_b = 2,
5521 + UARTIE_rls_m = 0x00000004,
5522 + UARTIE_ems_b = 3,
5523 + UARTIE_ems_m = 0x00000008,
5524 +
5525 + UARTII_pi_b = 0,
5526 + UARTII_pi_m = 0x00000001,
5527 + UARTII_iid_b = 1,
5528 + UARTII_iid_m = 0x0000000e,
5529 + UARTII_iid_ms_v = 0, // Modem stat-CTS,DSR,RI or DCD.
5530 + UARTII_iid_thre_v = 1, // Trans. Holding Reg. empty.
5531 + UARTII_iid_rda_v = 2, // Receive data available
5532 + UARTII_iid_rls_v = 3, // Overrun, parity, etc, error.
5533 + UARTII_iid_res4_v = 4, // reserved.
5534 + UARTII_iid_res5_v = 5, // reserved.
5535 + UARTII_iid_cto_v = 6, // Character timeout.
5536 + UARTII_iid_res7_v = 7, // reserved.
5537 +
5538 + UARTFC_en_b = 0,
5539 + UARTFC_en_m = 0x00000001,
5540 + UARTFC_rr_b = 1,
5541 + UARTFC_rr_m = 0x00000002,
5542 + UARTFC_tr_b = 2,
5543 + UARTFC_tr_m = 0x00000004,
5544 + UARTFC_dms_b = 3,
5545 + UARTFC_dms_m = 0x00000008,
5546 + UARTFC_rt_b = 6,
5547 + UARTFC_rt_m = 0x000000c0,
5548 + UARTFC_rt_1Byte_v = 0,
5549 + UARTFC_rt_4Byte_v = 1,
5550 + UARTFC_rt_8Byte_v = 2,
5551 + UARTFC_rt_14Byte_v = 3,
5552 +
5553 + UARTLC_wls_b = 0,
5554 + UARTLC_wls_m = 0x00000003,
5555 + UARTLC_wls_5Bits_v = 0,
5556 + UARTLC_wls_6Bits_v = 1,
5557 + UARTLC_wls_7Bits_v = 2,
5558 + UARTLC_wls_8Bits_v = 3,
5559 + UARTLC_stb_b = 2,
5560 + UARTLC_stb_m = 0x00000004,
5561 + UARTLC_pen_b = 3,
5562 + UARTLC_pen_m = 0x00000008,
5563 + UARTLC_eps_b = 4,
5564 + UARTLC_eps_m = 0x00000010,
5565 + UARTLC_sp_b = 5,
5566 + UARTLC_sp_m = 0x00000020,
5567 + UARTLC_sb_b = 6,
5568 + UARTLC_sb_m = 0x00000040,
5569 + UARTLC_dlab_b = 7,
5570 + UARTLC_dlab_m = 0x00000080,
5571 +
5572 + UARTMC_dtr_b = 0,
5573 + UARTMC_dtr_m = 0x00000001,
5574 + UARTMC_rts_b = 1,
5575 + UARTMC_rts_m = 0x00000002,
5576 + UARTMC_o1_b = 2,
5577 + UARTMC_o1_m = 0x00000004,
5578 + UARTMC_o2_b = 3,
5579 + UARTMC_o2_m = 0x00000008,
5580 + UARTMC_lp_b = 4,
5581 + UARTMC_lp_m = 0x00000010,
5582 +
5583 + UARTLS_dr_b = 0,
5584 + UARTLS_dr_m = 0x00000001,
5585 + UARTLS_oe_b = 1,
5586 + UARTLS_oe_m = 0x00000002,
5587 + UARTLS_pe_b = 2,
5588 + UARTLS_pe_m = 0x00000004,
5589 + UARTLS_fe_b = 3,
5590 + UARTLS_fe_m = 0x00000008,
5591 + UARTLS_bi_b = 4,
5592 + UARTLS_bi_m = 0x00000010,
5593 + UARTLS_thr_b = 5,
5594 + UARTLS_thr_m = 0x00000020,
5595 + UARTLS_te_b = 6,
5596 + UARTLS_te_m = 0x00000040,
5597 + UARTLS_rfe_b = 7,
5598 + UARTLS_rfe_m = 0x00000080,
5599 +
5600 + UARTMS_dcts_b = 0,
5601 + UARTMS_dcts_m = 0x00000001,
5602 + UARTMS_ddsr_b = 1,
5603 + UARTMS_ddsr_m = 0x00000002,
5604 + UARTMS_teri_b = 2,
5605 + UARTMS_teri_m = 0x00000004,
5606 + UARTMS_ddcd_b = 3,
5607 + UARTMS_ddcd_m = 0x00000008,
5608 + UARTMS_cts_b = 4,
5609 + UARTMS_cts_m = 0x00000010,
5610 + UARTMS_dsr_b = 5,
5611 + UARTMS_dsr_m = 0x00000020,
5612 + UARTMS_ri_b = 6,
5613 + UARTMS_ri_m = 0x00000040,
5614 + UARTMS_dcd_b = 7,
5615 + UARTMS_dcd_m = 0x00000080,
5616 +} ;
5617 +
5618 +#endif // __IDT_UART_H__
Staging tree of Mathias Kresin