Add support for the FriendlyARM NanoPi R2S.
Signed-off-by: David Bauer <mail@david-bauer.net>
HIDDEN:=1
endef
+
+# RK3328 boards
+
+define U-Boot/nanopi-r2s-rk3328
+ BUILD_SUBTARGET:=armv8
+ NAME:=NanoPi R2S
+ BUILD_DEVICES:= \
+ friendlyarm_nanopi-r2s
+ DEPENDS:=+PACKAGE_u-boot-nanopi-r2s-rk3328:arm-trusted-firmware-rockchip
+ PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip
+ ATF:=rk3328_bl31.elf
+ OF_PLATDATA:=$(1)
+endef
+
+
+# RK3399 boards
+
define U-Boot/rockpro64-rk3399
BUILD_SUBTARGET:=armv8
NAME:=RockPro64
pine64_rockpro64
DEPENDS:=+PACKAGE_u-boot-rockpro64-rk3399:arm-trusted-firmware-rockchip
PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip
+ ATF:=rk3399_bl31.elf
endef
UBOOT_TARGETS := \
- rockpro64-rk3399
+ rockpro64-rk3399 \
+ nanopi-r2s-rk3328
UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes
UBOOT_MAKE_FLAGS += \
- BL31=$(STAGING_DIR_IMAGE)/rk3399_bl31.elf
+ BL31=$(STAGING_DIR_IMAGE)/$(ATF)
define Build/Configure
$(call Build/Configure/U-Boot)
+ifneq ($(OF_PLATDATA),)
+ mkdir -p $(PKG_BUILD_DIR)/tpl/dts
+ mkdir -p $(PKG_BUILD_DIR)/include/generated
+
+ $(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-platdata.c $(PKG_BUILD_DIR)/tpl/dts/dt-platdata.c
+ $(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-structs-gen.h $(PKG_BUILD_DIR)/include/generated/dt-structs-gen.h
+endif
+
$(SED) 's#CONFIG_MKIMAGE_DTC_PATH=.*#CONFIG_MKIMAGE_DTC_PATH="$(PKG_BUILD_DIR)/scripts/dtc/dtc"#g' $(PKG_BUILD_DIR)/.config
echo 'CONFIG_IDENT_STRING=" OpenWrt"' >> $(PKG_BUILD_DIR)/.config
endef
--- /dev/null
+From 55273cf6079ddd3b006da69f0113c2c66c03f17e Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Tue, 14 Jul 2020 22:44:22 +0200
+Subject: [PATCH] spl: remove dtoc of-pdata generation
+
+Remove the dtoc of-pdata generation. This generation is dependant on
+libpython-dev. As OpenWrt does not ship with this dependency, use
+pre-generated pdata files and remove the generation from the
+build-process.
+
+This only affects RK3328 boards.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ scripts/Makefile.spl | 6 ------
+ 1 file changed, 6 deletions(-)
+
+--- a/scripts/Makefile.spl
++++ b/scripts/Makefile.spl
+@@ -320,12 +320,6 @@ PHONY += dts_dir
+ dts_dir:
+ $(shell [ -d $(obj)/dts ] || mkdir -p $(obj)/dts)
+
+-include/generated/dt-structs-gen.h: $(obj)/$(SPL_BIN).dtb dts_dir FORCE
+- $(call if_changed,dtoch)
+-
+-$(obj)/dts/dt-platdata.c: $(obj)/$(SPL_BIN).dtb dts_dir FORCE
+- $(call if_changed,dtocc)
+-
+ ifdef CONFIG_SAMSUNG
+ ifdef CONFIG_VAR_SIZE_SPL
+ VAR_SIZE_PARAM = --vs
--- /dev/null
+From 67f4c228c2bf515386cd54073104dc2e6eae85ea Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Fri, 10 Jul 2020 14:58:30 +0200
+Subject: [PATCH] rockchip: rk3328: Add support for FriendlyARM NanoPi R2S
+
+This adds support for the NanoPi R2S from FriendlyArm.
+
+Rockchip RK3328 SoC
+1GB DDR4 RAM
+Gigabit Ethernet (WAN)
+Gigabit Ethernet (USB3) (LAN)
+USB 2.0 Host Port
+MicroSD slot
+Reset button
+WAN - LAN - SYS LED
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ arch/arm/dts/Makefile | 1 +
+ arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi | 34 +++
+ arch/arm/dts/rk3328-nanopi-r2s.dts | 334 +++++++++++++++++++++
+ board/rockchip/evb_rk3328/MAINTAINERS | 7 +
+ configs/nanopi-r2s-rk3328_defconfig | 99 ++++++
+ 5 files changed, 475 insertions(+)
+ create mode 100644 arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
+ create mode 100644 arch/arm/dts/rk3328-nanopi-r2s.dts
+ create mode 100644 configs/nanopi-r2s-rk3328_defconfig
+
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -106,6 +106,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
+
+ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
+ rk3328-evb.dtb \
++ rk3328-nanopi-r2s.dtb \
+ rk3328-roc-cc.dtb \
+ rk3328-rock64.dtb \
+ rk3328-rock-pi-e.dtb
+--- /dev/null
++++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
+@@ -0,0 +1,34 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
++ * (C) Copyright 2020 David Bauer
++ */
++
++#include "rk3328-u-boot.dtsi"
++#include "rk3328-sdram-ddr4-666.dtsi"
++/ {
++ chosen {
++ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
++ };
++};
++
++&gpio0 {
++ u-boot,dm-spl;
++};
++
++&pinctrl {
++ u-boot,dm-spl;
++};
++
++&sdmmc0m1_gpio {
++ u-boot,dm-spl;
++};
++
++&pcfg_pull_up_4ma {
++ u-boot,dm-spl;
++};
++
++/* Need this and all the pinctrl/gpio stuff above to set pinmux */
++&vcc_sd {
++ u-boot,dm-spl;
++};
+--- /dev/null
++++ b/arch/arm/dts/rk3328-nanopi-r2s.dts
+@@ -0,0 +1,334 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
++ */
++
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/gpio/gpio.h>
++#include "rk3328.dtsi"
++
++/ {
++ model = "FriendlyARM NanoPi R2S";
++ compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
++
++ chosen {
++ stdout-path = "serial2:1500000n8";
++ };
++
++ gmac_clkin: external-gmac-clock {
++ compatible = "fixed-clock";
++ clock-frequency = <125000000>;
++ clock-output-names = "gmac_clkin";
++ #clock-cells = <0>;
++ };
++
++ vcc_sd: sdmmc-regulator {
++ compatible = "regulator-fixed";
++ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdmmc0m1_gpio>;
++ regulator-name = "vcc_sd";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc_io>;
++ };
++
++ vcc_sdio: sdmmcio-regulator {
++ compatible = "regulator-gpio";
++ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ states = <1800000 0x1
++ 3300000 0x0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdio_vcc_pin>;
++ regulator-always-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vcc_sdio";
++ regulator-settling-time-us = <5000>;
++ regulator-type = "voltage";
++ vin-supply = <&vcc_io>;
++ };
++
++ vcc_sys: vcc-sys {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_sys";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ pinctrl-names = "default";
++ pinctrl-0 = <&led_pins>;
++
++ sys {
++ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
++ label = "nanopi-r2s:red:sys";
++ };
++
++ lan {
++ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
++ label = "nanopi-r2s:green:lan";
++ };
++
++ wan {
++ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
++ label = "nanopi-r2s:green:wan";
++ };
++ };
++
++ gpio_keys {
++ compatible = "gpio-keys-polled";
++ poll-interval = <100>;
++
++ pinctrl-names = "default";
++ pinctrl-0 = <&button_pins>;
++
++ reset {
++ label = "Reset Button";
++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
++ linux,code = <KEY_RESTART>;
++ debounce-interval = <50>;
++ };
++ };
++};
++
++&cpu0 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu1 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu2 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu3 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&gmac2io {
++ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
++ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
++ clock_in_out = "input";
++ phy-supply = <&vcc_io>;
++ phy-handle = <&rtl8211e>;
++ phy-mode = "rgmii";
++ pinctrl-names = "default";
++ pinctrl-0 = <&rgmiim1_pins>;
++ snps,aal;
++ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
++ snps,reset-active-low;
++ snps,reset-delays-us = <0 10000 50000>;
++ tx_delay = <0x24>;
++ rx_delay = <0x18>;
++ status = "okay";
++
++ mdio {
++ compatible = "snps,dwmac-mdio";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ rtl8211e: ethernet-phy@0 {
++ reg = <0>;
++ };
++ };
++};
++
++&i2c1 {
++ status = "okay";
++
++ rk805: rk805@18 {
++ compatible = "rockchip,rk805";
++ reg = <0x18>;
++ interrupt-parent = <&gpio2>;
++ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
++ #clock-cells = <1>;
++ clock-output-names = "xin32k", "rk805-clkout2";
++ gpio-controller;
++ #gpio-cells = <2>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pmic_int_l>;
++ rockchip,system-power-controller;
++ wakeup-source;
++
++ vcc1-supply = <&vcc_sys>;
++ vcc2-supply = <&vcc_sys>;
++ vcc3-supply = <&vcc_sys>;
++ vcc4-supply = <&vcc_sys>;
++ vcc5-supply = <&vcc_io>;
++ vcc6-supply = <&vcc_sys>;
++
++ regulators {
++ vdd_logic: DCDC_REG1 {
++ regulator-name = "vdd_logic";
++ regulator-min-microvolt = <712500>;
++ regulator-max-microvolt = <1450000>;
++ regulator-ramp-delay = <12500>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1000000>;
++ };
++ };
++
++ vdd_arm: DCDC_REG2 {
++ regulator-name = "vdd_arm";
++ regulator-min-microvolt = <712500>;
++ regulator-max-microvolt = <1450000>;
++ regulator-ramp-delay = <12500>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <950000>;
++ };
++ };
++
++ vcc_ddr: DCDC_REG3 {
++ regulator-name = "vcc_ddr";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ };
++ };
++
++ vcc_io: DCDC_REG4 {
++ regulator-name = "vcc_io";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3300000>;
++ };
++ };
++
++ vcc_18: LDO_REG1 {
++ regulator-name = "vcc_18";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vcc18_emmc: LDO_REG2 {
++ regulator-name = "vcc18_emmc";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vdd_10: LDO_REG3 {
++ regulator-name = "vdd_10";
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <1000000>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1000000>;
++ };
++ };
++ };
++ };
++};
++
++&io_domains {
++ status = "okay";
++
++ vccio1-supply = <&vcc_io>;
++ vccio2-supply = <&vcc18_emmc>;
++ vccio3-supply = <&vcc_sdio>;
++ vccio4-supply = <&vcc_18>;
++ vccio5-supply = <&vcc_io>;
++ vccio6-supply = <&vcc_io>;
++ pmuio-supply = <&vcc_io>;
++};
++
++&pinctrl {
++ leds {
++ led_pins: led-pins {
++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>,
++ <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>,
++ <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ button {
++ button_pins: button-pins {
++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ pmic {
++ pmic_int_l: pmic-int-l {
++ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ sd {
++ sdio_vcc_pin: sdio-vcc-pin {
++ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++};
++
++&sdmmc {
++ bus-width = <4>;
++ cap-mmc-highspeed;
++ cap-sd-highspeed;
++ disable-wp;
++ max-frequency = <150000000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
++ vmmc-supply = <&vcc_sd>;
++ vqmmc-supply = <&vcc_sdio>;
++ status = "okay";
++};
++
++&tsadc {
++ rockchip,hw-tshut-mode = <0>;
++ rockchip,hw-tshut-polarity = <0>;
++ status = "okay";
++};
++
++&uart2 {
++ status = "okay";
++};
++
++&u2phy {
++ status = "okay";
++
++ u2phy_host: host-port {
++ status = "okay";
++ };
++};
++
++&usb_host0_ehci {
++ status = "okay";
++};
++
++&usb_host0_ohci {
++ status = "okay";
++};
+--- a/board/rockchip/evb_rk3328/MAINTAINERS
++++ b/board/rockchip/evb_rk3328/MAINTAINERS
+@@ -5,6 +5,13 @@ F: board/rockchip/evb_rk3328
+ F: include/configs/evb_rk3328.h
+ F: configs/evb-rk3328_defconfig
+
++NANOPI-R2S-RK3328
++M: David Bauer <mail@david-bauer.net>
++S: Maintained
++F: configs/nanopi-r2s-rk3328_defconfig
++F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
++F: arch/arm/dts/rk3328-nanopi-r2s.dts
++
+ ROC-RK3328-CC
+ M: Loic Devulder <ldevulder@suse.com>
+ M: Chen-Yu Tsai <wens@csie.org>
+--- /dev/null
++++ b/configs/nanopi-r2s-rk3328_defconfig
+@@ -0,0 +1,99 @@
++CONFIG_ARM=y
++CONFIG_ARCH_ROCKCHIP=y
++CONFIG_SYS_TEXT_BASE=0x00200000
++CONFIG_SPL_GPIO_SUPPORT=y
++CONFIG_ENV_OFFSET=0x3F8000
++CONFIG_ROCKCHIP_RK3328=y
++CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
++CONFIG_TPL_LIBCOMMON_SUPPORT=y
++CONFIG_TPL_LIBGENERIC_SUPPORT=y
++CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
++CONFIG_SPL_STACK_R_ADDR=0x600000
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_DEBUG_UART_BASE=0xFF130000
++CONFIG_DEBUG_UART_CLOCK=24000000
++CONFIG_SMBIOS_PRODUCT_NAME="nanopi_r2s_rk3328"
++CONFIG_DEBUG_UART=y
++CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
++# CONFIG_ANDROID_BOOT_IMAGE is not set
++CONFIG_FIT=y
++CONFIG_FIT_VERBOSE=y
++CONFIG_SPL_LOAD_FIT=y
++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb"
++CONFIG_MISC_INIT_R=y
++# CONFIG_DISPLAY_CPUINFO is not set
++CONFIG_DISPLAY_BOARDINFO_LATE=y
++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
++CONFIG_TPL_SYS_MALLOC_SIMPLE=y
++CONFIG_SPL_STACK_R=y
++CONFIG_SPL_I2C_SUPPORT=y
++CONFIG_SPL_POWER_SUPPORT=y
++CONFIG_SPL_ATF=y
++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
++CONFIG_CMD_BOOTZ=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_USB=y
++# CONFIG_CMD_SETEXPR is not set
++CONFIG_CMD_TIME=y
++CONFIG_SPL_OF_CONTROL=y
++CONFIG_TPL_OF_CONTROL=y
++CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2s"
++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
++CONFIG_TPL_OF_PLATDATA=y
++CONFIG_ENV_IS_IN_MMC=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_TPL_DM=y
++CONFIG_REGMAP=y
++CONFIG_SPL_REGMAP=y
++CONFIG_TPL_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_SPL_SYSCON=y
++CONFIG_TPL_SYSCON=y
++CONFIG_CLK=y
++CONFIG_SPL_CLK=y
++CONFIG_FASTBOOT_BUF_ADDR=0x800800
++CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
++CONFIG_ROCKCHIP_GPIO=y
++CONFIG_SYS_I2C_ROCKCHIP=y
++CONFIG_MMC_DW=y
++CONFIG_MMC_DW_ROCKCHIP=y
++CONFIG_SF_DEFAULT_SPEED=20000000
++CONFIG_DM_ETH=y
++CONFIG_ETH_DESIGNWARE=y
++CONFIG_GMAC_ROCKCHIP=y
++CONFIG_PINCTRL=y
++CONFIG_SPL_PINCTRL=y
++CONFIG_DM_PMIC=y
++CONFIG_PMIC_RK8XX=y
++CONFIG_SPL_DM_REGULATOR=y
++CONFIG_REGULATOR_PWM=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_SPL_DM_REGULATOR_FIXED=y
++CONFIG_REGULATOR_RK8XX=y
++CONFIG_PWM_ROCKCHIP=y
++CONFIG_RAM=y
++CONFIG_SPL_RAM=y
++CONFIG_TPL_RAM=y
++CONFIG_DM_RESET=y
++CONFIG_BAUDRATE=1500000
++CONFIG_DEBUG_UART_SHIFT=2
++CONFIG_SYSRESET=y
++# CONFIG_TPL_SYSRESET is not set
++CONFIG_USB=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_DWC3=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_GENERIC=y
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_OHCI_GENERIC=y
++CONFIG_USB_DWC2=y
++CONFIG_USB_DWC3=y
++# CONFIG_USB_DWC3_GADGET is not set
++CONFIG_USB_GADGET=y
++CONFIG_USB_GADGET_DWC2_OTG=y
++CONFIG_SPL_TINY_MEMSET=y
++CONFIG_TPL_TINY_MEMSET=y
++CONFIG_ERRNO_STR=y
++CONFIG_SMBIOS_MANUFACTURER="pine64"
--- /dev/null
+/*
+ * DO NOT MODIFY
+ *
+ * This file was generated by dtoc from a .dtb (device tree binary) file.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dt-structs.h>
+
+static const struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
+ .reg = {0xff100000, 0x1000},
+};
+U_BOOT_DEVICE(syscon_at_ff100000) = {
+ .name = "rockchip_rk3328_grf",
+ .platdata = &dtv_syscon_at_ff100000,
+ .platdata_size = sizeof(dtv_syscon_at_ff100000),
+};
+
+static const struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
+ .reg = {0xff440000, 0x1000},
+ .rockchip_grf = 0x3a,
+};
+U_BOOT_DEVICE(clock_controller_at_ff440000) = {
+ .name = "rockchip_rk3328_cru",
+ .platdata = &dtv_clock_controller_at_ff440000,
+ .platdata_size = sizeof(dtv_clock_controller_at_ff440000),
+};
+
+static const struct dtd_rockchip_rk3328_uart dtv_serial_at_ff130000 = {
+ .clock_frequency = 0x16e3600,
+ .clocks = {
+ {&dtv_clock_controller_at_ff440000, {40}},
+ {&dtv_clock_controller_at_ff440000, {212}},},
+ .dma_names = {"tx", "rx"},
+ .dmas = {0x10, 0x6, 0x10, 0x7},
+ .interrupts = {0x0, 0x39, 0x4},
+ .pinctrl_0 = 0x26,
+ .pinctrl_names = "default",
+ .reg = {0xff130000, 0x100},
+ .reg_io_width = 0x4,
+ .reg_shift = 0x2,
+};
+U_BOOT_DEVICE(serial_at_ff130000) = {
+ .name = "rockchip_rk3328_uart",
+ .platdata = &dtv_serial_at_ff130000,
+ .platdata_size = sizeof(dtv_serial_at_ff130000),
+};
+
+static const struct dtd_rockchip_rk3328_dw_mshc dtv_mmc_at_ff500000 = {
+ .bus_width = 0x4,
+ .cap_mmc_highspeed = true,
+ .cap_sd_highspeed = true,
+ .clocks = {
+ {&dtv_clock_controller_at_ff440000, {317}},
+ {&dtv_clock_controller_at_ff440000, {33}},
+ {&dtv_clock_controller_at_ff440000, {74}},
+ {&dtv_clock_controller_at_ff440000, {78}},},
+ .disable_wp = true,
+ .fifo_depth = 0x100,
+ .interrupts = {0x0, 0xc, 0x4},
+ .max_frequency = 0x8f0d180,
+ .pinctrl_0 = {0x47, 0x48, 0x49, 0x4a},
+ .pinctrl_names = "default",
+ .reg = {0xff500000, 0x4000},
+ .u_boot_spl_fifo_mode = true,
+ .vmmc_supply = 0x4b,
+ .vqmmc_supply = 0x1e,
+};
+U_BOOT_DEVICE(mmc_at_ff500000) = {
+ .name = "rockchip_rk3328_dw_mshc",
+ .platdata = &dtv_mmc_at_ff500000,
+ .platdata_size = sizeof(dtv_mmc_at_ff500000),
+};
+
+static const struct dtd_rockchip_rk3328_pinctrl dtv_pinctrl = {
+ .ranges = true,
+ .rockchip_grf = 0x3a,
+};
+U_BOOT_DEVICE(pinctrl) = {
+ .name = "rockchip_rk3328_pinctrl",
+ .platdata = &dtv_pinctrl,
+ .platdata_size = sizeof(dtv_pinctrl),
+};
+
+static const struct dtd_rockchip_gpio_bank dtv_gpio0_at_ff210000 = {
+ .clocks = {
+ {&dtv_clock_controller_at_ff440000, {200}},},
+ .gpio_controller = true,
+ .interrupt_controller = true,
+ .interrupts = {0x0, 0x33, 0x4},
+ .reg = {0xff210000, 0x100},
+};
+U_BOOT_DEVICE(gpio0_at_ff210000) = {
+ .name = "rockchip_gpio_bank",
+ .platdata = &dtv_gpio0_at_ff210000,
+ .platdata_size = sizeof(dtv_gpio0_at_ff210000),
+};
+
+static const struct dtd_regulator_fixed dtv_sdmmc_regulator = {
+ .gpio = {0x60, 0x1e, 0x1},
+ .pinctrl_0 = 0x61,
+ .pinctrl_names = "default",
+ .regulator_max_microvolt = 0x325aa0,
+ .regulator_min_microvolt = 0x325aa0,
+ .regulator_name = "vcc_sd",
+ .vin_supply = 0x1c,
+};
+U_BOOT_DEVICE(sdmmc_regulator) = {
+ .name = "regulator_fixed",
+ .platdata = &dtv_sdmmc_regulator,
+ .platdata_size = sizeof(dtv_sdmmc_regulator),
+};
+
+static const struct dtd_rockchip_rk3328_dmc dtv_dmc = {
+ .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
+ 0xff720000, 0x1000, 0xff798000, 0x1000},
+ .rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,
+ 0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,
+ 0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,
+ 0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,
+ 0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,
+ 0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,
+ 0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,
+ 0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,
+ 0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,
+ 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,
+ 0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
+ 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
+ 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
+ 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
+ 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
+ 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
+ 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
+ 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
+ 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
+ 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
+ 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
+ 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
+ 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
+ 0x77, 0x77, 0x79, 0x9},
+};
+U_BOOT_DEVICE(dmc) = {
+ .name = "rockchip_rk3328_dmc",
+ .platdata = &dtv_dmc,
+ .platdata_size = sizeof(dtv_dmc),
+};
+
--- /dev/null
+/*
+ * DO NOT MODIFY
+ *
+ * This file was generated by dtoc from a .dtb (device tree binary) file.
+ */
+
+#include <stdbool.h>
+#include <linux/libfdt.h>
+struct dtd_regulator_fixed {
+ fdt32_t gpio[3];
+ fdt32_t pinctrl_0;
+ const char * pinctrl_names;
+ fdt32_t regulator_max_microvolt;
+ fdt32_t regulator_min_microvolt;
+ const char * regulator_name;
+ fdt32_t vin_supply;
+};
+struct dtd_rockchip_gpio_bank {
+ struct phandle_1_arg clocks[1];
+ bool gpio_controller;
+ bool interrupt_controller;
+ fdt32_t interrupts[3];
+ fdt64_t reg[2];
+};
+struct dtd_rockchip_rk3328_cru {
+ fdt64_t reg[2];
+ fdt32_t rockchip_grf;
+};
+struct dtd_rockchip_rk3328_dmc {
+ fdt64_t reg[12];
+ fdt32_t rockchip_sdram_params[196];
+};
+struct dtd_rockchip_rk3328_dw_mshc {
+ fdt32_t bus_width;
+ bool cap_mmc_highspeed;
+ bool cap_sd_highspeed;
+ struct phandle_1_arg clocks[4];
+ bool disable_wp;
+ fdt32_t fifo_depth;
+ fdt32_t interrupts[3];
+ fdt32_t max_frequency;
+ fdt32_t pinctrl_0[4];
+ const char * pinctrl_names;
+ fdt64_t reg[2];
+ bool u_boot_spl_fifo_mode;
+ fdt32_t vmmc_supply;
+ fdt32_t vqmmc_supply;
+};
+struct dtd_rockchip_rk3328_grf {
+ fdt64_t reg[2];
+};
+struct dtd_rockchip_rk3328_pinctrl {
+ bool ranges;
+ fdt32_t rockchip_grf;
+};
+struct dtd_rockchip_rk3328_uart {
+ fdt32_t clock_frequency;
+ struct phandle_1_arg clocks[2];
+ const char * dma_names[2];
+ fdt32_t dmas[4];
+ fdt32_t interrupts[3];
+ fdt32_t pinctrl_0;
+ const char * pinctrl_names;
+ fdt64_t reg[2];
+ fdt32_t reg_io_width;
+ fdt32_t reg_shift;
+};
+#define dtd_syscon dtd_rockchip_rk3328_cru
+#define dtd_simple_mfd dtd_rockchip_rk3328_grf
+#define dtd_snps_dw_apb_uart dtd_rockchip_rk3328_uart
+#define dtd_rockchip_cru dtd_rockchip_rk3328_cru
+#define dtd_rockchip_rk3288_dw_mshc dtd_rockchip_rk3328_dw_mshc
projects / openwrt / staging / mkresin.git / commitdiff