PKG_FWCUTTER_SOURCE_URL:=http://bu3sch.de/b43/fwcutter/
PKG_FWCUTTER_MD5SUM:=3db2f4de85a459451f5b391cf67a8d44
+PKG_SRC_NAME:=b43-src
+PKG_SRC_VERSION:=2008-08-06
+
+PKG_SRC_SOURCE:=compat-wireless-$(PKG_SRC_VERSION).tar.bz2
+PKG_SRC_SOURCE_URL:=http://www.orbit-lab.org/kernel/compat-wireless-2.6/2008/08/
+PKG_SRC_MD5SUM:=9563ceeed86bca0859ad5f010623277c
+
define KernelPackage/b43
SUBMENU:=Wireless Drivers
TITLE:=Broadcom 43xx wireless support
define Build/Prepare
mkdir -p $(PKG_BUILD_DIR)
- $(CP) ./src/* $(PKG_BUILD_DIR)/
tar xjf "$(DL_DIR)/$(PKG_FWV4_SOURCE)" -C "$(PKG_BUILD_DIR)"
tar xjf "$(DL_DIR)/$(PKG_FWCUTTER_SOURCE)" -C "$(PKG_BUILD_DIR)"
+ tar xjf "$(DL_DIR)/$(PKG_SRC_SOURCE)" -C "$(PKG_BUILD_DIR)"
+ $(CP) $(PKG_BUILD_DIR)/compat-wireless-$(PKG_SRC_VERSION)/drivers/net/wireless/b43/* $(PKG_BUILD_DIR)/
$(Build/Patch)
$(if $(QUILT),touch $(PKG_BUILD_DIR)/.quilt_used)
endef
-Index: b43/main.c
-===================================================================
---- b43.orig/main.c 2008-02-15 22:39:48.000000000 +0100
-+++ b43/main.c 2008-02-15 22:45:38.000000000 +0100
-@@ -2939,7 +2942,7 @@ static int b43_op_set_key(struct ieee802
- u8 algorithm;
- u8 index;
- int err;
-- DECLARE_MAC_BUF(mac);
-+// DECLARE_MAC_BUF(mac);
-
- if (modparam_nohwcrypt)
- return -ENOSPC; /* User disabled HW-crypto */
-@@ -3019,10 +3022,12 @@ out_unlock:
- spin_unlock_irqrestore(&wl->irq_lock, flags);
- mutex_unlock(&wl->mutex);
- if (!err) {
-+#if 0
- b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
- "mac: %s\n",
- cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
- print_mac(mac, addr));
-+#endif
- }
- return err;
- }
--- /dev/null
+Index: b43/dma.c
+===================================================================
+--- b43.orig/dma.c 2008-07-27 13:56:25.000000000 +0200
++++ b43/dma.c 2008-07-27 14:02:26.000000000 +0200
+@@ -328,11 +328,11 @@ static inline
+ dma_addr_t dmaaddr;
+
+ if (tx) {
+- dmaaddr = ssb_dma_map_single(ring->dev->dev,
+- buf, len, DMA_TO_DEVICE);
++ dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
++ buf, len, DMA_TO_DEVICE);
+ } else {
+- dmaaddr = ssb_dma_map_single(ring->dev->dev,
+- buf, len, DMA_FROM_DEVICE);
++ dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
++ buf, len, DMA_FROM_DEVICE);
+ }
+
+ return dmaaddr;
+@@ -343,11 +343,11 @@ static inline
+ dma_addr_t addr, size_t len, int tx)
+ {
+ if (tx) {
+- ssb_dma_unmap_single(ring->dev->dev,
+- addr, len, DMA_TO_DEVICE);
++ dma_unmap_single(ring->dev->dev->dma_dev,
++ addr, len, DMA_TO_DEVICE);
+ } else {
+- ssb_dma_unmap_single(ring->dev->dev,
+- addr, len, DMA_FROM_DEVICE);
++ dma_unmap_single(ring->dev->dev->dma_dev,
++ addr, len, DMA_FROM_DEVICE);
+ }
+ }
+
+@@ -356,8 +356,8 @@ static inline
+ dma_addr_t addr, size_t len)
+ {
+ B43_WARN_ON(ring->tx);
+- ssb_dma_sync_single_for_cpu(ring->dev->dev,
+- addr, len, DMA_FROM_DEVICE);
++ dma_sync_single_for_cpu(ring->dev->dev->dma_dev,
++ addr, len, DMA_FROM_DEVICE);
+ }
+
+ static inline
+@@ -365,8 +365,8 @@ static inline
+ dma_addr_t addr, size_t len)
+ {
+ B43_WARN_ON(ring->tx);
+- ssb_dma_sync_single_for_device(ring->dev->dev,
+- addr, len, DMA_FROM_DEVICE);
++ dma_sync_single_for_device(ring->dev->dev->dma_dev,
++ addr, len, DMA_FROM_DEVICE);
+ }
+
+ static inline
+@@ -381,6 +381,7 @@ static inline
+
+ static int alloc_ringmemory(struct b43_dmaring *ring)
+ {
++ struct device *dma_dev = ring->dev->dev->dma_dev;
+ gfp_t flags = GFP_KERNEL;
+
+ /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
+@@ -391,14 +392,11 @@ static int alloc_ringmemory(struct b43_dmaring *ring)
+ * For unknown reasons - possibly a hardware error - the BCM4311 rev
+ * 02, which uses 64-bit DMA, needs the ring buffer in very low memory,
+ * which accounts for the GFP_DMA flag below.
+- *
+- * The flags here must match the flags in free_ringmemory below!
+ */
+ if (ring->type == B43_DMA_64BIT)
+ flags |= GFP_DMA;
+- ring->descbase = ssb_dma_alloc_consistent(ring->dev->dev,
+- B43_DMA_RINGMEMSIZE,
+- &(ring->dmabase), flags);
++ ring->descbase = dma_alloc_coherent(dma_dev, B43_DMA_RINGMEMSIZE,
++ &(ring->dmabase), flags);
+ if (!ring->descbase) {
+ b43err(ring->dev->wl, "DMA ringmemory allocation failed\n");
+ return -ENOMEM;
+@@ -410,13 +408,10 @@ static int alloc_ringmemory(struct b43_dmaring *ring)
+
+ static void free_ringmemory(struct b43_dmaring *ring)
+ {
+- gfp_t flags = GFP_KERNEL;
+-
+- if (ring->type == B43_DMA_64BIT)
+- flags |= GFP_DMA;
++ struct device *dma_dev = ring->dev->dev->dma_dev;
+
+- ssb_dma_free_consistent(ring->dev->dev, B43_DMA_RINGMEMSIZE,
+- ring->descbase, ring->dmabase, flags);
++ dma_free_coherent(dma_dev, B43_DMA_RINGMEMSIZE,
++ ring->descbase, ring->dmabase);
+ }
+
+ /* Reset the RX DMA channel */
+@@ -523,7 +518,7 @@ static bool b43_dma_mapping_error(struct b43_dmaring *ring,
+ dma_addr_t addr,
+ size_t buffersize, bool dma_to_device)
+ {
+- if (unlikely(ssb_dma_mapping_error(ring->dev->dev, addr)))
++ if (unlikely(dma_mapping_error(addr)))
+ return 1;
+
+ switch (ring->type) {
+@@ -849,10 +844,10 @@ struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
+ goto err_kfree_meta;
+
+ /* test for ability to dma to txhdr_cache */
+- dma_test = ssb_dma_map_single(dev->dev,
+- ring->txhdr_cache,
+- b43_txhdr_size(dev),
+- DMA_TO_DEVICE);
++ dma_test = dma_map_single(dev->dev->dma_dev,
++ ring->txhdr_cache,
++ b43_txhdr_size(dev),
++ DMA_TO_DEVICE);
+
+ if (b43_dma_mapping_error(ring, dma_test,
+ b43_txhdr_size(dev), 1)) {
+@@ -864,10 +859,10 @@ struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
+ if (!ring->txhdr_cache)
+ goto err_kfree_meta;
+
+- dma_test = ssb_dma_map_single(dev->dev,
+- ring->txhdr_cache,
+- b43_txhdr_size(dev),
+- DMA_TO_DEVICE);
++ dma_test = dma_map_single(dev->dev->dma_dev,
++ ring->txhdr_cache,
++ b43_txhdr_size(dev),
++ DMA_TO_DEVICE);
+
+ if (b43_dma_mapping_error(ring, dma_test,
+ b43_txhdr_size(dev), 1)) {
+@@ -878,9 +873,9 @@ struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
+ }
+ }
+
+- ssb_dma_unmap_single(dev->dev,
+- dma_test, b43_txhdr_size(dev),
+- DMA_TO_DEVICE);
++ dma_unmap_single(dev->dev->dma_dev,
++ dma_test, b43_txhdr_size(dev),
++ DMA_TO_DEVICE);
+ }
+
+ err = alloc_ringmemory(ring);
-config B43
- tristate "Broadcom 43xx wireless support (mac80211 stack)"
- depends on SSB_POSSIBLE && MAC80211 && WLAN_80211
- select SSB
- select FW_LOADER
- select HW_RANDOM
- ---help---
- b43 is a driver for the Broadcom 43xx series wireless devices.
-
- Check "lspci" for something like
- "Broadcom Corporation BCM43XX 802.11 Wireless LAN Controller"
- to determine whether you own such a device.
-
- This driver supports the new BCM43xx IEEE 802.11G devices, but not
- the old IEEE 802.11B devices. Old devices are supported by
- the b43legacy driver.
- Note that this has nothing to do with the standard that your AccessPoint
- supports (A, B, G or a combination).
- IEEE 802.11G devices can talk to IEEE 802.11B AccessPoints.
-
- It is safe to include both b43 and b43legacy as the underlying glue
- layer will automatically load the correct version for your device.
-
- This driver uses V4 firmware, which must be installed separately using
- b43-fwcutter.
-
- This driver can be built as a module (recommended) that will be called "b43".
- If unsure, say M.
-
-# Auto-select SSB PCI-HOST support, if possible
-config B43_PCI_AUTOSELECT
- bool
- depends on B43 && SSB_PCIHOST_POSSIBLE
- select SSB_PCIHOST
- default y
-
-# Auto-select SSB PCICORE driver, if possible
-config B43_PCICORE_AUTOSELECT
- bool
- depends on B43 && SSB_DRIVER_PCICORE_POSSIBLE
- select SSB_DRIVER_PCICORE
- default y
-
-config B43_PCMCIA
- bool "Broadcom 43xx PCMCIA device support (EXPERIMENTAL)"
- depends on B43 && SSB_PCMCIAHOST_POSSIBLE && EXPERIMENTAL
- select SSB_PCMCIAHOST
- ---help---
- Broadcom 43xx PCMCIA device support.
-
- Support for 16bit PCMCIA devices.
- Please note that most PC-CARD devices are _NOT_ 16bit PCMCIA
- devices, but 32bit CardBUS devices. CardBUS devices are supported
- out of the box by b43.
-
- With this config option you can drive b43 cards in
- CompactFlash formfactor in a PCMCIA adaptor.
- CF b43 cards can sometimes be found in handheld PCs.
-
- It's safe to select Y here, even if you don't have a B43 PCMCIA device.
-
- If unsure, say N.
-
-config B43_NPHY
- bool "Pre IEEE 802.11n support (BROKEN)"
- depends on B43 && EXPERIMENTAL
- ---help---
- Support for the IEEE 802.11n draft.
-
- THIS IS BROKEN AND DOES NOT WORK YET.
-
- SAY N.
-
-# This config option automatically enables b43 LEDS support,
-# if it's possible.
-config B43_LEDS
- bool
- depends on B43 && MAC80211_LEDS && (LEDS_CLASS = y || LEDS_CLASS = B43)
- default y
-
-# This config option automatically enables b43 RFKILL support,
-# if it's possible.
-config B43_RFKILL
- bool
- depends on B43 && (RFKILL = y || RFKILL = B43) && RFKILL_INPUT && (INPUT_POLLDEV = y || INPUT_POLLDEV = B43)
- default y
-
-config B43_DEBUG
- bool "Broadcom 43xx debugging"
- depends on B43
- ---help---
- Broadcom 43xx debugging messages.
-
- Say Y, if you want to find out why the driver does not
- work for you.
-b43-y += main.o
-b43-y += tables.o
-b43-$(CONFIG_B43_NPHY) += tables_nphy.o
-b43-y += phy.o
-b43-$(CONFIG_B43_NPHY) += nphy.o
-b43-y += sysfs.o
-b43-y += xmit.o
-b43-y += lo.o
-b43-y += wa.o
-b43-y += dma.o
-b43-$(CONFIG_B43_PIO) += pio.o
-b43-$(CONFIG_B43_RFKILL) += rfkill.o
-b43-$(CONFIG_B43_LEDS) += leds.o
-b43-$(CONFIG_B43_PCMCIA) += pcmcia.o
-b43-$(CONFIG_B43_DEBUG) += debugfs.o
-
-obj-$(CONFIG_B43) += b43.o
-#ifndef B43_H_
-#define B43_H_
-
-#include <linux/kernel.h>
-#include <linux/spinlock.h>
-#include <linux/interrupt.h>
-#include <linux/hw_random.h>
-#include <linux/ssb/ssb.h>
-#include <net/mac80211.h>
-
-#include "debugfs.h"
-#include "leds.h"
-#include "rfkill.h"
-#include "lo.h"
-#include "phy.h"
-
-
-/* The unique identifier of the firmware that's officially supported by
- * this driver version. */
-#define B43_SUPPORTED_FIRMWARE_ID "FW13"
-
-
-#ifdef CONFIG_B43_DEBUG
-# define B43_DEBUG 1
-#else
-# define B43_DEBUG 0
-#endif
-
-#define B43_RX_MAX_SSI 60
-
-/* MMIO offsets */
-#define B43_MMIO_DMA0_REASON 0x20
-#define B43_MMIO_DMA0_IRQ_MASK 0x24
-#define B43_MMIO_DMA1_REASON 0x28
-#define B43_MMIO_DMA1_IRQ_MASK 0x2C
-#define B43_MMIO_DMA2_REASON 0x30
-#define B43_MMIO_DMA2_IRQ_MASK 0x34
-#define B43_MMIO_DMA3_REASON 0x38
-#define B43_MMIO_DMA3_IRQ_MASK 0x3C
-#define B43_MMIO_DMA4_REASON 0x40
-#define B43_MMIO_DMA4_IRQ_MASK 0x44
-#define B43_MMIO_DMA5_REASON 0x48
-#define B43_MMIO_DMA5_IRQ_MASK 0x4C
-#define B43_MMIO_MACCTL 0x120 /* MAC control */
-#define B43_MMIO_MACCMD 0x124 /* MAC command */
-#define B43_MMIO_GEN_IRQ_REASON 0x128
-#define B43_MMIO_GEN_IRQ_MASK 0x12C
-#define B43_MMIO_RAM_CONTROL 0x130
-#define B43_MMIO_RAM_DATA 0x134
-#define B43_MMIO_PS_STATUS 0x140
-#define B43_MMIO_RADIO_HWENABLED_HI 0x158
-#define B43_MMIO_SHM_CONTROL 0x160
-#define B43_MMIO_SHM_DATA 0x164
-#define B43_MMIO_SHM_DATA_UNALIGNED 0x166
-#define B43_MMIO_XMITSTAT_0 0x170
-#define B43_MMIO_XMITSTAT_1 0x174
-#define B43_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
-#define B43_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
-#define B43_MMIO_TSF_CFP_REP 0x188
-#define B43_MMIO_TSF_CFP_START 0x18C
-#define B43_MMIO_TSF_CFP_MAXDUR 0x190
-
-/* 32-bit DMA */
-#define B43_MMIO_DMA32_BASE0 0x200
-#define B43_MMIO_DMA32_BASE1 0x220
-#define B43_MMIO_DMA32_BASE2 0x240
-#define B43_MMIO_DMA32_BASE3 0x260
-#define B43_MMIO_DMA32_BASE4 0x280
-#define B43_MMIO_DMA32_BASE5 0x2A0
-/* 64-bit DMA */
-#define B43_MMIO_DMA64_BASE0 0x200
-#define B43_MMIO_DMA64_BASE1 0x240
-#define B43_MMIO_DMA64_BASE2 0x280
-#define B43_MMIO_DMA64_BASE3 0x2C0
-#define B43_MMIO_DMA64_BASE4 0x300
-#define B43_MMIO_DMA64_BASE5 0x340
-
-/* PIO on core rev < 11 */
-#define B43_MMIO_PIO_BASE0 0x300
-#define B43_MMIO_PIO_BASE1 0x310
-#define B43_MMIO_PIO_BASE2 0x320
-#define B43_MMIO_PIO_BASE3 0x330
-#define B43_MMIO_PIO_BASE4 0x340
-#define B43_MMIO_PIO_BASE5 0x350
-#define B43_MMIO_PIO_BASE6 0x360
-#define B43_MMIO_PIO_BASE7 0x370
-/* PIO on core rev >= 11 */
-#define B43_MMIO_PIO11_BASE0 0x200
-#define B43_MMIO_PIO11_BASE1 0x240
-#define B43_MMIO_PIO11_BASE2 0x280
-#define B43_MMIO_PIO11_BASE3 0x2C0
-#define B43_MMIO_PIO11_BASE4 0x300
-#define B43_MMIO_PIO11_BASE5 0x340
-
-#define B43_MMIO_PHY_VER 0x3E0
-#define B43_MMIO_PHY_RADIO 0x3E2
-#define B43_MMIO_PHY0 0x3E6
-#define B43_MMIO_ANTENNA 0x3E8
-#define B43_MMIO_CHANNEL 0x3F0
-#define B43_MMIO_CHANNEL_EXT 0x3F4
-#define B43_MMIO_RADIO_CONTROL 0x3F6
-#define B43_MMIO_RADIO_DATA_HIGH 0x3F8
-#define B43_MMIO_RADIO_DATA_LOW 0x3FA
-#define B43_MMIO_PHY_CONTROL 0x3FC
-#define B43_MMIO_PHY_DATA 0x3FE
-#define B43_MMIO_MACFILTER_CONTROL 0x420
-#define B43_MMIO_MACFILTER_DATA 0x422
-#define B43_MMIO_RCMTA_COUNT 0x43C
-#define B43_MMIO_RADIO_HWENABLED_LO 0x49A
-#define B43_MMIO_GPIO_CONTROL 0x49C
-#define B43_MMIO_GPIO_MASK 0x49E
-#define B43_MMIO_TSF_CFP_START_LOW 0x604
-#define B43_MMIO_TSF_CFP_START_HIGH 0x606
-#define B43_MMIO_TSF_CFP_PRETBTT 0x612
-#define B43_MMIO_TSF_0 0x632 /* core rev < 3 only */
-#define B43_MMIO_TSF_1 0x634 /* core rev < 3 only */
-#define B43_MMIO_TSF_2 0x636 /* core rev < 3 only */
-#define B43_MMIO_TSF_3 0x638 /* core rev < 3 only */
-#define B43_MMIO_RNG 0x65A
-#define B43_MMIO_IFSCTL 0x688 /* Interframe space control */
-#define B43_MMIO_IFSCTL_USE_EDCF 0x0004
-#define B43_MMIO_POWERUP_DELAY 0x6A8
-
-/* SPROM boardflags_lo values */
-#define B43_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
-#define B43_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
-#define B43_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
-#define B43_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
-#define B43_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
-#define B43_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
-#define B43_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
-#define B43_BFL_ENETADM 0x0080 /* has ADMtek switch */
-#define B43_BFL_ENETVLAN 0x0100 /* can do vlan */
-#define B43_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
-#define B43_BFL_NOPCI 0x0400 /* leaves PCI floating */
-#define B43_BFL_FEM 0x0800 /* supports the Front End Module */
-#define B43_BFL_EXTLNA 0x1000 /* has an external LNA */
-#define B43_BFL_HGPA 0x2000 /* had high gain PA */
-#define B43_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
-#define B43_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
-
-/* GPIO register offset, in both ChipCommon and PCI core. */
-#define B43_GPIO_CONTROL 0x6c
-
-/* SHM Routing */
-enum {
- B43_SHM_UCODE, /* Microcode memory */
- B43_SHM_SHARED, /* Shared memory */
- B43_SHM_SCRATCH, /* Scratch memory */
- B43_SHM_HW, /* Internal hardware register */
- B43_SHM_RCMTA, /* Receive match transmitter address (rev >= 5 only) */
-};
-/* SHM Routing modifiers */
-#define B43_SHM_AUTOINC_R 0x0200 /* Auto-increment address on read */
-#define B43_SHM_AUTOINC_W 0x0100 /* Auto-increment address on write */
-#define B43_SHM_AUTOINC_RW (B43_SHM_AUTOINC_R | \
- B43_SHM_AUTOINC_W)
-
-/* Misc SHM_SHARED offsets */
-#define B43_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */
-#define B43_SHM_SH_PCTLWDPOS 0x0008
-#define B43_SHM_SH_RXPADOFF 0x0034 /* RX Padding data offset (PIO only) */
-#define B43_SHM_SH_PHYVER 0x0050 /* PHY version */
-#define B43_SHM_SH_PHYTYPE 0x0052 /* PHY type */
-#define B43_SHM_SH_ANTSWAP 0x005C /* Antenna swap threshold */
-#define B43_SHM_SH_HOSTFLO 0x005E /* Hostflags for ucode options (low) */
-#define B43_SHM_SH_HOSTFMI 0x0060 /* Hostflags for ucode options (middle) */
-#define B43_SHM_SH_HOSTFHI 0x0062 /* Hostflags for ucode options (high) */
-#define B43_SHM_SH_RFATT 0x0064 /* Current radio attenuation value */
-#define B43_SHM_SH_RADAR 0x0066 /* Radar register */
-#define B43_SHM_SH_PHYTXNOI 0x006E /* PHY noise directly after TX (lower 8bit only) */
-#define B43_SHM_SH_RFRXSP1 0x0072 /* RF RX SP Register 1 */
-#define B43_SHM_SH_CHAN 0x00A0 /* Current channel (low 8bit only) */
-#define B43_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5Ghz channel */
-#define B43_SHM_SH_BCMCFIFOID 0x0108 /* Last posted cookie to the bcast/mcast FIFO */
-/* SHM_SHARED TX FIFO variables */
-#define B43_SHM_SH_SIZE01 0x0098 /* TX FIFO size for FIFO 0 (low) and 1 (high) */
-#define B43_SHM_SH_SIZE23 0x009A /* TX FIFO size for FIFO 2 and 3 */
-#define B43_SHM_SH_SIZE45 0x009C /* TX FIFO size for FIFO 4 and 5 */
-#define B43_SHM_SH_SIZE67 0x009E /* TX FIFO size for FIFO 6 and 7 */
-/* SHM_SHARED background noise */
-#define B43_SHM_SH_JSSI0 0x0088 /* Measure JSSI 0 */
-#define B43_SHM_SH_JSSI1 0x008A /* Measure JSSI 1 */
-#define B43_SHM_SH_JSSIAUX 0x008C /* Measure JSSI AUX */
-/* SHM_SHARED crypto engine */
-#define B43_SHM_SH_DEFAULTIV 0x003C /* Default IV location */
-#define B43_SHM_SH_NRRXTRANS 0x003E /* # of soft RX transmitter addresses (max 8) */
-#define B43_SHM_SH_KTP 0x0056 /* Key table pointer */
-#define B43_SHM_SH_TKIPTSCTTAK 0x0318
-#define B43_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block (v4 firmware) */
-#define B43_SHM_SH_PSM 0x05F4 /* PSM transmitter address match block (rev < 5) */
-/* SHM_SHARED WME variables */
-#define B43_SHM_SH_EDCFSTAT 0x000E /* EDCF status */
-#define B43_SHM_SH_TXFCUR 0x0030 /* TXF current index */
-#define B43_SHM_SH_EDCFQ 0x0240 /* EDCF Q info */
-/* SHM_SHARED powersave mode related */
-#define B43_SHM_SH_SLOTT 0x0010 /* Slot time */
-#define B43_SHM_SH_DTIMPER 0x0012 /* DTIM period */
-#define B43_SHM_SH_NOSLPZNATDTIM 0x004C /* NOSLPZNAT DTIM */
-/* SHM_SHARED beacon/AP variables */
-#define B43_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */
-#define B43_SHM_SH_BTL1 0x001A /* Beacon template length 1 */
-#define B43_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */
-#define B43_SHM_SH_TIMBPOS 0x001E /* TIM B position in beacon */
-#define B43_SHM_SH_DTIMP 0x0012 /* DTIP period */
-#define B43_SHM_SH_MCASTCOOKIE 0x00A8 /* Last bcast/mcast frame ID */
-#define B43_SHM_SH_SFFBLIM 0x0044 /* Short frame fallback retry limit */
-#define B43_SHM_SH_LFFBLIM 0x0046 /* Long frame fallback retry limit */
-#define B43_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word (see PHY TX control) */
-#define B43_SHM_SH_EXTNPHYCTL 0x00B0 /* Extended bytes for beacon PHY control (N) */
-/* SHM_SHARED ACK/CTS control */
-#define B43_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word (see PHY TX control) */
-/* SHM_SHARED probe response variables */
-#define B43_SHM_SH_PRSSID 0x0160 /* Probe Response SSID */
-#define B43_SHM_SH_PRSSIDLEN 0x0048 /* Probe Response SSID length */
-#define B43_SHM_SH_PRTLEN 0x004A /* Probe Response template length */
-#define B43_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */
-#define B43_SHM_SH_PRPHYCTL 0x0188 /* Probe Response PHY TX control word */
-/* SHM_SHARED rate tables */
-#define B43_SHM_SH_OFDMDIRECT 0x01C0 /* Pointer to OFDM direct map */
-#define B43_SHM_SH_OFDMBASIC 0x01E0 /* Pointer to OFDM basic rate map */
-#define B43_SHM_SH_CCKDIRECT 0x0200 /* Pointer to CCK direct map */
-#define B43_SHM_SH_CCKBASIC 0x0220 /* Pointer to CCK basic rate map */
-/* SHM_SHARED microcode soft registers */
-#define B43_SHM_SH_UCODEREV 0x0000 /* Microcode revision */
-#define B43_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */
-#define B43_SHM_SH_UCODEDATE 0x0004 /* Microcode date */
-#define B43_SHM_SH_UCODETIME 0x0006 /* Microcode time */
-#define B43_SHM_SH_UCODESTAT 0x0040 /* Microcode debug status code */
-#define B43_SHM_SH_UCODESTAT_INVALID 0
-#define B43_SHM_SH_UCODESTAT_INIT 1
-#define B43_SHM_SH_UCODESTAT_ACTIVE 2
-#define B43_SHM_SH_UCODESTAT_SUSP 3 /* suspended */
-#define B43_SHM_SH_UCODESTAT_SLEEP 4 /* asleep (PS) */
-#define B43_SHM_SH_MAXBFRAMES 0x0080 /* Maximum number of frames in a burst */
-#define B43_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
-#define B43_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */
-
-/* SHM_SCRATCH offsets */
-#define B43_SHM_SC_MINCONT 0x0003 /* Minimum contention window */
-#define B43_SHM_SC_MAXCONT 0x0004 /* Maximum contention window */
-#define B43_SHM_SC_CURCONT 0x0005 /* Current contention window */
-#define B43_SHM_SC_SRLIMIT 0x0006 /* Short retry count limit */
-#define B43_SHM_SC_LRLIMIT 0x0007 /* Long retry count limit */
-#define B43_SHM_SC_DTIMC 0x0008 /* Current DTIM count */
-#define B43_SHM_SC_BTL0LEN 0x0015 /* Beacon 0 template length */
-#define B43_SHM_SC_BTL1LEN 0x0016 /* Beacon 1 template length */
-#define B43_SHM_SC_SCFB 0x0017 /* Short frame transmit count threshold for rate fallback */
-#define B43_SHM_SC_LCFB 0x0018 /* Long frame transmit count threshold for rate fallback */
-
-/* Hardware Radio Enable masks */
-#define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
-#define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
-
-/* HostFlags. See b43_hf_read/write() */
-#define B43_HF_ANTDIVHELP 0x000000000001ULL /* ucode antenna div helper */
-#define B43_HF_SYMW 0x000000000002ULL /* G-PHY SYM workaround */
-#define B43_HF_RXPULLW 0x000000000004ULL /* RX pullup workaround */
-#define B43_HF_CCKBOOST 0x000000000008ULL /* 4dB CCK power boost (exclusive with OFDM boost) */
-#define B43_HF_BTCOEX 0x000000000010ULL /* Bluetooth coexistance */
-#define B43_HF_GDCW 0x000000000020ULL /* G-PHY DC canceller filter bw workaround */
-#define B43_HF_OFDMPABOOST 0x000000000040ULL /* Enable PA gain boost for OFDM */
-#define B43_HF_ACPR 0x000000000080ULL /* Disable for Japan, channel 14 */
-#define B43_HF_EDCF 0x000000000100ULL /* on if WME and MAC suspended */
-#define B43_HF_TSSIRPSMW 0x000000000200ULL /* TSSI reset PSM ucode workaround */
-#define B43_HF_20IN40IQW 0x000000000200ULL /* 20 in 40 MHz I/Q workaround (rev >= 13 only) */
-#define B43_HF_DSCRQ 0x000000000400ULL /* Disable slow clock request in ucode */
-#define B43_HF_ACIW 0x000000000800ULL /* ACI workaround: shift bits by 2 on PHY CRS */
-#define B43_HF_2060W 0x000000001000ULL /* 2060 radio workaround */
-#define B43_HF_RADARW 0x000000002000ULL /* Radar workaround */
-#define B43_HF_USEDEFKEYS 0x000000004000ULL /* Enable use of default keys */
-#define B43_HF_AFTERBURNER 0x000000008000ULL /* Afterburner enabled */
-#define B43_HF_BT4PRIOCOEX 0x000000010000ULL /* Bluetooth 4-priority coexistance */
-#define B43_HF_FWKUP 0x000000020000ULL /* Fast wake-up ucode */
-#define B43_HF_VCORECALC 0x000000040000ULL /* Force VCO recalculation when powering up synthpu */
-#define B43_HF_PCISCW 0x000000080000ULL /* PCI slow clock workaround */
-#define B43_HF_4318TSSI 0x000000200000ULL /* 4318 TSSI */
-#define B43_HF_FBCMCFIFO 0x000000400000ULL /* Flush bcast/mcast FIFO immediately */
-#define B43_HF_HWPCTL 0x000000800000ULL /* Enable hardwarre power control */
-#define B43_HF_BTCOEXALT 0x000001000000ULL /* Bluetooth coexistance in alternate pins */
-#define B43_HF_TXBTCHECK 0x000002000000ULL /* Bluetooth check during transmission */
-#define B43_HF_SKCFPUP 0x000004000000ULL /* Skip CFP update */
-#define B43_HF_N40W 0x000008000000ULL /* N PHY 40 MHz workaround (rev >= 13 only) */
-#define B43_HF_ANTSEL 0x000020000000ULL /* Antenna selection (for testing antenna div.) */
-#define B43_HF_BT3COEXT 0x000020000000ULL /* Bluetooth 3-wire coexistence (rev >= 13 only) */
-#define B43_HF_BTCANT 0x000040000000ULL /* Bluetooth coexistence (antenna mode) (rev >= 13 only) */
-#define B43_HF_ANTSELEN 0x000100000000ULL /* Antenna selection enabled (rev >= 13 only) */
-#define B43_HF_ANTSELMODE 0x000200000000ULL /* Antenna selection mode (rev >= 13 only) */
-#define B43_HF_MLADVW 0x001000000000ULL /* N PHY ML ADV workaround (rev >= 13 only) */
-#define B43_HF_PR45960W 0x080000000000ULL /* PR 45960 workaround (rev >= 13 only) */
-
-/* MacFilter offsets. */
-#define B43_MACFILTER_SELF 0x0000
-#define B43_MACFILTER_BSSID 0x0003
-
-/* PowerControl */
-#define B43_PCTL_IN 0xB0
-#define B43_PCTL_OUT 0xB4
-#define B43_PCTL_OUTENABLE 0xB8
-#define B43_PCTL_XTAL_POWERUP 0x40
-#define B43_PCTL_PLL_POWERDOWN 0x80
-
-/* PowerControl Clock Modes */
-#define B43_PCTL_CLK_FAST 0x00
-#define B43_PCTL_CLK_SLOW 0x01
-#define B43_PCTL_CLK_DYNAMIC 0x02
-
-#define B43_PCTL_FORCE_SLOW 0x0800
-#define B43_PCTL_FORCE_PLL 0x1000
-#define B43_PCTL_DYN_XTAL 0x2000
-
-/* PHYVersioning */
-#define B43_PHYTYPE_A 0x00
-#define B43_PHYTYPE_B 0x01
-#define B43_PHYTYPE_G 0x02
-#define B43_PHYTYPE_N 0x04
-#define B43_PHYTYPE_LP 0x05
-
-/* PHYRegisters */
-#define B43_PHY_ILT_A_CTRL 0x0072
-#define B43_PHY_ILT_A_DATA1 0x0073
-#define B43_PHY_ILT_A_DATA2 0x0074
-#define B43_PHY_G_LO_CONTROL 0x0810
-#define B43_PHY_ILT_G_CTRL 0x0472
-#define B43_PHY_ILT_G_DATA1 0x0473
-#define B43_PHY_ILT_G_DATA2 0x0474
-#define B43_PHY_A_PCTL 0x007B
-#define B43_PHY_G_PCTL 0x0029
-#define B43_PHY_A_CRS 0x0029
-#define B43_PHY_RADIO_BITFIELD 0x0401
-#define B43_PHY_G_CRS 0x0429
-#define B43_PHY_NRSSILT_CTRL 0x0803
-#define B43_PHY_NRSSILT_DATA 0x0804
-
-/* RadioRegisters */
-#define B43_RADIOCTL_ID 0x01
-
-/* MAC Control bitfield */
-#define B43_MACCTL_ENABLED 0x00000001 /* MAC Enabled */
-#define B43_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */
-#define B43_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */
-#define B43_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */
-#define B43_MACCTL_SHM_UPPER 0x00000200 /* SHM Upper */
-#define B43_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */
-#define B43_MACCTL_PSM_DBG 0x00002000 /* Microcode debugging enabled */
-#define B43_MACCTL_GPOUTSMSK 0x0000C000 /* GPOUT Select Mask */
-#define B43_MACCTL_BE 0x00010000 /* Big Endian mode */
-#define B43_MACCTL_INFRA 0x00020000 /* Infrastructure mode */
-#define B43_MACCTL_AP 0x00040000 /* AccessPoint mode */
-#define B43_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */
-#define B43_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */
-#define B43_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep frames with bad PLCP */
-#define B43_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */
-#define B43_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */
-#define B43_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */
-#define B43_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */
-#define B43_MACCTL_AWAKE 0x04000000 /* Device is awake */
-#define B43_MACCTL_CLOSEDNET 0x08000000 /* Closed net (no SSID bcast) */
-#define B43_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */
-#define B43_MACCTL_DISCTXSTAT 0x20000000 /* Discard TX status */
-#define B43_MACCTL_DISCPMQ 0x40000000 /* Discard Power Management Queue */
-#define B43_MACCTL_GMODE 0x80000000 /* G Mode */
-
-/* MAC Command bitfield */
-#define B43_MACCMD_BEACON0_VALID 0x00000001 /* Beacon 0 in template RAM is busy/valid */
-#define B43_MACCMD_BEACON1_VALID 0x00000002 /* Beacon 1 in template RAM is busy/valid */
-#define B43_MACCMD_DFQ_VALID 0x00000004 /* Directed frame queue valid (IBSS PS mode, ATIM) */
-#define B43_MACCMD_CCA 0x00000008 /* Clear channel assessment */
-#define B43_MACCMD_BGNOISE 0x00000010 /* Background noise */
-
-/* 802.11 core specific TM State Low (SSB_TMSLOW) flags */
-#define B43_TMSLOW_GMODE 0x20000000 /* G Mode Enable */
-#define B43_TMSLOW_PHYCLKSPEED 0x00C00000 /* PHY clock speed mask (N-PHY only) */
-#define B43_TMSLOW_PHYCLKSPEED_40MHZ 0x00000000 /* 40 MHz PHY */
-#define B43_TMSLOW_PHYCLKSPEED_80MHZ 0x00400000 /* 80 MHz PHY */
-#define B43_TMSLOW_PHYCLKSPEED_160MHZ 0x00800000 /* 160 MHz PHY */
-#define B43_TMSLOW_PLLREFSEL 0x00200000 /* PLL Frequency Reference Select (rev >= 5) */
-#define B43_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */
-#define B43_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */
-#define B43_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */
-
-/* 802.11 core specific TM State High (SSB_TMSHIGH) flags */
-#define B43_TMSHIGH_DUALBAND_PHY 0x00080000 /* Dualband PHY available */
-#define B43_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available (rev >= 5) */
-#define B43_TMSHIGH_HAVE_5GHZ_PHY 0x00020000 /* 5 GHz PHY available (rev >= 5) */
-#define B43_TMSHIGH_HAVE_2GHZ_PHY 0x00010000 /* 2.4 GHz PHY available (rev >= 5) */
-
-/* Generic-Interrupt reasons. */
-#define B43_IRQ_MAC_SUSPENDED 0x00000001
-#define B43_IRQ_BEACON 0x00000002
-#define B43_IRQ_TBTT_INDI 0x00000004
-#define B43_IRQ_BEACON_TX_OK 0x00000008
-#define B43_IRQ_BEACON_CANCEL 0x00000010
-#define B43_IRQ_ATIM_END 0x00000020
-#define B43_IRQ_PMQ 0x00000040
-#define B43_IRQ_PIO_WORKAROUND 0x00000100
-#define B43_IRQ_MAC_TXERR 0x00000200
-#define B43_IRQ_PHY_TXERR 0x00000800
-#define B43_IRQ_PMEVENT 0x00001000
-#define B43_IRQ_TIMER0 0x00002000
-#define B43_IRQ_TIMER1 0x00004000
-#define B43_IRQ_DMA 0x00008000
-#define B43_IRQ_TXFIFO_FLUSH_OK 0x00010000
-#define B43_IRQ_CCA_MEASURE_OK 0x00020000
-#define B43_IRQ_NOISESAMPLE_OK 0x00040000
-#define B43_IRQ_UCODE_DEBUG 0x08000000
-#define B43_IRQ_RFKILL 0x10000000
-#define B43_IRQ_TX_OK 0x20000000
-#define B43_IRQ_PHY_G_CHANGED 0x40000000
-#define B43_IRQ_TIMEOUT 0x80000000
-
-#define B43_IRQ_ALL 0xFFFFFFFF
-#define B43_IRQ_MASKTEMPLATE (B43_IRQ_TBTT_INDI | \
- B43_IRQ_ATIM_END | \
- B43_IRQ_PMQ | \
- B43_IRQ_MAC_TXERR | \
- B43_IRQ_PHY_TXERR | \
- B43_IRQ_DMA | \
- B43_IRQ_TXFIFO_FLUSH_OK | \
- B43_IRQ_NOISESAMPLE_OK | \
- B43_IRQ_UCODE_DEBUG | \
- B43_IRQ_RFKILL | \
- B43_IRQ_TX_OK)
-
-/* The firmware register to fetch the debug-IRQ reason from. */
-#define B43_DEBUGIRQ_REASON_REG 63
-/* Debug-IRQ reasons. */
-#define B43_DEBUGIRQ_PANIC 0 /* The firmware panic'ed */
-#define B43_DEBUGIRQ_DUMP_SHM 1 /* Dump shared SHM */
-#define B43_DEBUGIRQ_DUMP_REGS 2 /* Dump the microcode registers */
-#define B43_DEBUGIRQ_MARKER 3 /* A "marker" was thrown by the firmware. */
-#define B43_DEBUGIRQ_ACK 0xFFFF /* The host writes that to ACK the IRQ */
-
-/* The firmware register that contains the "marker" line. */
-#define B43_MARKER_ID_REG 2
-#define B43_MARKER_LINE_REG 3
-
-/* The firmware register to fetch the panic reason from. */
-#define B43_FWPANIC_REASON_REG 3
-/* Firmware panic reason codes */
-#define B43_FWPANIC_DIE 0 /* Firmware died. Don't auto-restart it. */
-#define B43_FWPANIC_RESTART 1 /* Firmware died. Schedule a controller reset. */
-
-
-/* Device specific rate values.
- * The actual values defined here are (rate_in_mbps * 2).
- * Some code depends on this. Don't change it. */
-#define B43_CCK_RATE_1MB 0x02
-#define B43_CCK_RATE_2MB 0x04
-#define B43_CCK_RATE_5MB 0x0B
-#define B43_CCK_RATE_11MB 0x16
-#define B43_OFDM_RATE_6MB 0x0C
-#define B43_OFDM_RATE_9MB 0x12
-#define B43_OFDM_RATE_12MB 0x18
-#define B43_OFDM_RATE_18MB 0x24
-#define B43_OFDM_RATE_24MB 0x30
-#define B43_OFDM_RATE_36MB 0x48
-#define B43_OFDM_RATE_48MB 0x60
-#define B43_OFDM_RATE_54MB 0x6C
-/* Convert a b43 rate value to a rate in 100kbps */
-#define B43_RATE_TO_BASE100KBPS(rate) (((rate) * 10) / 2)
-
-#define B43_DEFAULT_SHORT_RETRY_LIMIT 7
-#define B43_DEFAULT_LONG_RETRY_LIMIT 4
-
-#define B43_PHY_TX_BADNESS_LIMIT 1000
-
-/* Max size of a security key */
-#define B43_SEC_KEYSIZE 16
-/* Security algorithms. */
-enum {
- B43_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
- B43_SEC_ALGO_WEP40,
- B43_SEC_ALGO_TKIP,
- B43_SEC_ALGO_AES,
- B43_SEC_ALGO_WEP104,
- B43_SEC_ALGO_AES_LEGACY,
-};
-
-struct b43_dmaring;
-
-/* The firmware file header */
-#define B43_FW_TYPE_UCODE 'u'
-#define B43_FW_TYPE_PCM 'p'
-#define B43_FW_TYPE_IV 'i'
-struct b43_fw_header {
- /* File type */
- u8 type;
- /* File format version */
- u8 ver;
- u8 __padding[2];
- /* Size of the data. For ucode and PCM this is in bytes.
- * For IV this is number-of-ivs. */
- __be32 size;
-} __attribute__((__packed__));
-
-/* Initial Value file format */
-#define B43_IV_OFFSET_MASK 0x7FFF
-#define B43_IV_32BIT 0x8000
-struct b43_iv {
- __be16 offset_size;
- union {
- __be16 d16;
- __be32 d32;
- } data __attribute__((__packed__));
-} __attribute__((__packed__));
-
-
-struct b43_phy {
- /* Band support flags. */
- bool supports_2ghz;
- bool supports_5ghz;
-
- /* GMODE bit enabled? */
- bool gmode;
-
- /* Analog Type */
- u8 analog;
- /* B43_PHYTYPE_ */
- u8 type;
- /* PHY revision number. */
- u8 rev;
-
- /* Radio versioning */
- u16 radio_manuf; /* Radio manufacturer */
- u16 radio_ver; /* Radio version */
- u8 radio_rev; /* Radio revision */
-
- bool dyn_tssi_tbl; /* tssi2dbm is kmalloc()ed. */
-
- /* ACI (adjacent channel interference) flags. */
- bool aci_enable;
- bool aci_wlan_automatic;
- bool aci_hw_rssi;
-
- /* Radio switched on/off */
- bool radio_on;
- struct {
- /* Values saved when turning the radio off.
- * They are needed when turning it on again. */
- bool valid;
- u16 rfover;
- u16 rfoverval;
- } radio_off_context;
-
- u16 minlowsig[2];
- u16 minlowsigpos[2];
-
- /* TSSI to dBm table in use */
- const s8 *tssi2dbm;
- /* Target idle TSSI */
- int tgt_idle_tssi;
- /* Current idle TSSI */
- int cur_idle_tssi;
-
- /* LocalOscillator control values. */
- struct b43_txpower_lo_control *lo_control;
- /* Values from b43_calc_loopback_gain() */
- s16 max_lb_gain; /* Maximum Loopback gain in hdB */
- s16 trsw_rx_gain; /* TRSW RX gain in hdB */
- s16 lna_lod_gain; /* LNA lod */
- s16 lna_gain; /* LNA */
- s16 pga_gain; /* PGA */
-
- /* Desired TX power level (in dBm).
- * This is set by the user and adjusted in b43_phy_xmitpower(). */
- u8 power_level;
- /* A-PHY TX Power control value. */
- u16 txpwr_offset;
-
- /* Current TX power level attenuation control values */
- struct b43_bbatt bbatt;
- struct b43_rfatt rfatt;
- u8 tx_control; /* B43_TXCTL_XXX */
-
- /* Hardware Power Control enabled? */
- bool hardware_power_control;
-
- /* Current Interference Mitigation mode */
- int interfmode;
- /* Stack of saved values from the Interference Mitigation code.
- * Each value in the stack is layed out as follows:
- * bit 0-11: offset
- * bit 12-15: register ID
- * bit 16-32: value
- * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
- */
-#define B43_INTERFSTACK_SIZE 26
- u32 interfstack[B43_INTERFSTACK_SIZE]; //FIXME: use a data structure
-
- /* Saved values from the NRSSI Slope calculation */
- s16 nrssi[2];
- s32 nrssislope;
- /* In memory nrssi lookup table. */
- s8 nrssi_lt[64];
-
- /* current channel */
- u8 channel;
-
- u16 lofcal;
-
- u16 initval; //FIXME rename?
-
- /* PHY TX errors counter. */
- atomic_t txerr_cnt;
-
- /* The device does address auto increment for the OFDM tables.
- * We cache the previously used address here and omit the address
- * write on the next table access, if possible. */
- u16 ofdmtab_addr; /* The address currently set in hardware. */
- enum { /* The last data flow direction. */
- B43_OFDMTAB_DIRECTION_UNKNOWN = 0,
- B43_OFDMTAB_DIRECTION_READ,
- B43_OFDMTAB_DIRECTION_WRITE,
- } ofdmtab_addr_direction;
-
-#if B43_DEBUG
- /* Manual TX-power control enabled? */
- bool manual_txpower_control;
- /* PHY registers locked by b43_phy_lock()? */
- bool phy_locked;
-#endif /* B43_DEBUG */
-};
-
-/* Data structures for DMA transmission, per 80211 core. */
-struct b43_dma {
- struct b43_dmaring *tx_ring_AC_BK; /* Background */
- struct b43_dmaring *tx_ring_AC_BE; /* Best Effort */
- struct b43_dmaring *tx_ring_AC_VI; /* Video */
- struct b43_dmaring *tx_ring_AC_VO; /* Voice */
- struct b43_dmaring *tx_ring_mcast; /* Multicast */
-
- struct b43_dmaring *rx_ring;
-};
-
-struct b43_pio_txqueue;
-struct b43_pio_rxqueue;
-
-/* Data structures for PIO transmission, per 80211 core. */
-struct b43_pio {
- struct b43_pio_txqueue *tx_queue_AC_BK; /* Background */
- struct b43_pio_txqueue *tx_queue_AC_BE; /* Best Effort */
- struct b43_pio_txqueue *tx_queue_AC_VI; /* Video */
- struct b43_pio_txqueue *tx_queue_AC_VO; /* Voice */
- struct b43_pio_txqueue *tx_queue_mcast; /* Multicast */
-
- struct b43_pio_rxqueue *rx_queue;
-};
-
-/* Context information for a noise calculation (Link Quality). */
-struct b43_noise_calculation {
- u8 channel_at_start;
- bool calculation_running;
- u8 nr_samples;
- s8 samples[8][4];
-};
-
-struct b43_stats {
- u8 link_noise;
- /* Store the last TX/RX times here for updating the leds. */
- unsigned long last_tx;
- unsigned long last_rx;
-};
-
-struct b43_key {
- /* If keyconf is NULL, this key is disabled.
- * keyconf is a cookie. Don't derefenrence it outside of the set_key
- * path, because b43 doesn't own it. */
- struct ieee80211_key_conf *keyconf;
- u8 algorithm;
-};
-
-/* SHM offsets to the QOS data structures for the 4 different queues. */
-#define B43_QOS_PARAMS(queue) (B43_SHM_SH_EDCFQ + \
- (B43_NR_QOSPARAMS * sizeof(u16) * (queue)))
-#define B43_QOS_BACKGROUND B43_QOS_PARAMS(0)
-#define B43_QOS_BESTEFFORT B43_QOS_PARAMS(1)
-#define B43_QOS_VIDEO B43_QOS_PARAMS(2)
-#define B43_QOS_VOICE B43_QOS_PARAMS(3)
-
-/* QOS parameter hardware data structure offsets. */
-#define B43_NR_QOSPARAMS 22
-enum {
- B43_QOSPARAM_TXOP = 0,
- B43_QOSPARAM_CWMIN,
- B43_QOSPARAM_CWMAX,
- B43_QOSPARAM_CWCUR,
- B43_QOSPARAM_AIFS,
- B43_QOSPARAM_BSLOTS,
- B43_QOSPARAM_REGGAP,
- B43_QOSPARAM_STATUS,
-};
-
-/* QOS parameters for a queue. */
-struct b43_qos_params {
- /* The QOS parameters */
- struct ieee80211_tx_queue_params p;
- /* Does this need to get uploaded to hardware? */
- bool need_hw_update;
-};
-
-struct b43_wldev;
-
-/* Data structure for the WLAN parts (802.11 cores) of the b43 chip. */
-struct b43_wl {
- /* Pointer to the active wireless device on this chip */
- struct b43_wldev *current_dev;
- /* Pointer to the ieee80211 hardware data structure */
- struct ieee80211_hw *hw;
-
- struct mutex mutex;
- spinlock_t irq_lock;
- /* R/W lock for data transmission.
- * Transmissions on 2+ queues can run concurrently, but somebody else
- * might sync with TX by write_lock_irqsave()'ing. */
- rwlock_t tx_lock;
- /* Lock for LEDs access. */
- spinlock_t leds_lock;
- /* Lock for SHM access. */
- spinlock_t shm_lock;
-
- /* We can only have one operating interface (802.11 core)
- * at a time. General information about this interface follows.
- */
-
- struct ieee80211_vif *vif;
- /* The MAC address of the operating interface. */
- u8 mac_addr[ETH_ALEN];
- /* Current BSSID */
- u8 bssid[ETH_ALEN];
- /* Interface type. (IEEE80211_IF_TYPE_XXX) */
- int if_type;
- /* Is the card operating in AP, STA or IBSS mode? */
- bool operating;
- /* filter flags */
- unsigned int filter_flags;
- /* Stats about the wireless interface */
- struct ieee80211_low_level_stats ieee_stats;
-
- struct hwrng rng;
- u8 rng_initialized;
- char rng_name[30 + 1];
-
- /* The RF-kill button */
- struct b43_rfkill rfkill;
-
- /* List of all wireless devices on this chip */
- struct list_head devlist;
- u8 nr_devs;
-
- bool radiotap_enabled;
-
- /* The beacon we are currently using (AP or IBSS mode).
- * This beacon stuff is protected by the irq_lock. */
- struct sk_buff *current_beacon;
- bool beacon0_uploaded;
- bool beacon1_uploaded;
- struct work_struct beacon_update_trigger;
-
- /* The current QOS parameters for the 4 queues.
- * This is protected by the irq_lock. */
- struct b43_qos_params qos_params[4];
- /* Workqueue for updating QOS parameters in hardware. */
- struct work_struct qos_update_work;
-};
-
-/* In-memory representation of a cached microcode file. */
-struct b43_firmware_file {
- const char *filename;
- const struct firmware *data;
-};
-
-/* Pointers to the firmware data and meta information about it. */
-struct b43_firmware {
- /* Microcode */
- struct b43_firmware_file ucode;
- /* PCM code */
- struct b43_firmware_file pcm;
- /* Initial MMIO values for the firmware */
- struct b43_firmware_file initvals;
- /* Initial MMIO values for the firmware, band-specific */
- struct b43_firmware_file initvals_band;
-
- /* Firmware revision */
- u16 rev;
- /* Firmware patchlevel */
- u16 patch;
-
- /* Set to true, if we are using an opensource firmware. */
- bool opensource;
- /* Set to true, if the core needs a PCM firmware, but
- * we failed to load one. This is always false for
- * core rev > 10, as these don't need PCM firmware. */
- bool pcm_request_failed;
-};
-
-/* Device (802.11 core) initialization status. */
-enum {
- B43_STAT_UNINIT = 0, /* Uninitialized. */
- B43_STAT_INITIALIZED = 1, /* Initialized, but not started, yet. */
- B43_STAT_STARTED = 2, /* Up and running. */
-};
-#define b43_status(wldev) atomic_read(&(wldev)->__init_status)
-#define b43_set_status(wldev, stat) do { \
- atomic_set(&(wldev)->__init_status, (stat)); \
- smp_wmb(); \
- } while (0)
-
-/* XXX--- HOW LOCKING WORKS IN B43 ---XXX
- *
- * You should always acquire both, wl->mutex and wl->irq_lock unless:
- * - You don't need to acquire wl->irq_lock, if the interface is stopped.
- * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet
- * and packet TX path (and _ONLY_ there.)
- */
-
-/* Data structure for one wireless device (802.11 core) */
-struct b43_wldev {
- struct ssb_device *dev;
- struct b43_wl *wl;
-
- /* The device initialization status.
- * Use b43_status() to query. */
- atomic_t __init_status;
- /* Saved init status for handling suspend. */
- int suspend_init_status;
-
- bool bad_frames_preempt; /* Use "Bad Frames Preemption" (default off) */
- bool dfq_valid; /* Directed frame queue valid (IBSS PS mode, ATIM) */
- bool short_slot; /* TRUE, if short slot timing is enabled. */
- bool radio_hw_enable; /* saved state of radio hardware enabled state */
- bool suspend_in_progress; /* TRUE, if we are in a suspend/resume cycle */
-
- /* PHY/Radio device. */
- struct b43_phy phy;
-
- union {
- /* DMA engines. */
- struct b43_dma dma;
- /* PIO engines. */
- struct b43_pio pio;
- };
- /* Use b43_using_pio_transfers() to check whether we are using
- * DMA or PIO data transfers. */
- bool __using_pio_transfers;
-
- /* Various statistics about the physical device. */
- struct b43_stats stats;
-
- /* The device LEDs. */
- struct b43_led led_tx;
- struct b43_led led_rx;
- struct b43_led led_assoc;
- struct b43_led led_radio;
-
- /* Reason code of the last interrupt. */
- u32 irq_reason;
- u32 dma_reason[6];
- /* saved irq enable/disable state bitfield. */
- u32 irq_savedstate;
- /* Link Quality calculation context. */
- struct b43_noise_calculation noisecalc;
- /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
- int mac_suspended;
-
- /* Interrupt Service Routine tasklet (bottom-half) */
- struct tasklet_struct isr_tasklet;
-
- /* Periodic tasks */
- struct delayed_work periodic_work;
- unsigned int periodic_state;
-
- struct work_struct restart_work;
-
- /* encryption/decryption */
- u16 ktp; /* Key table pointer */
- u8 max_nr_keys;
- struct b43_key key[58];
-
- /* Firmware data */
- struct b43_firmware fw;
-
- /* Devicelist in struct b43_wl (all 802.11 cores) */
- struct list_head list;
-
- /* Debugging stuff follows. */
-#ifdef CONFIG_B43_DEBUG
- struct b43_dfsentry *dfsentry;
-#endif
-};
-
-static inline struct b43_wl *hw_to_b43_wl(struct ieee80211_hw *hw)
-{
- return hw->priv;
-}
-
-static inline struct b43_wldev *dev_to_b43_wldev(struct device *dev)
-{
- struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
- return ssb_get_drvdata(ssb_dev);
-}
-
-/* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */
-static inline int b43_is_mode(struct b43_wl *wl, int type)
-{
- return (wl->operating && wl->if_type == type);
-}
-
-static inline u16 b43_read16(struct b43_wldev *dev, u16 offset)
-{
- return ssb_read16(dev->dev, offset);
-}
-
-static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value)
-{
- ssb_write16(dev->dev, offset, value);
-}
-
-static inline u32 b43_read32(struct b43_wldev *dev, u16 offset)
-{
- return ssb_read32(dev->dev, offset);
-}
-
-static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value)
-{
- ssb_write32(dev->dev, offset, value);
-}
-
-static inline bool b43_using_pio_transfers(struct b43_wldev *dev)
-{
-#ifdef CONFIG_B43_PIO
- return dev->__using_pio_transfers;
-#else
- return 0;
-#endif
-}
-
-#ifdef CONFIG_B43_FORCE_PIO
-# define B43_FORCE_PIO 1
-#else
-# define B43_FORCE_PIO 0
-#endif
-
-
-/* Message printing */
-void b43info(struct b43_wl *wl, const char *fmt, ...)
- __attribute__ ((format(printf, 2, 3)));
-void b43err(struct b43_wl *wl, const char *fmt, ...)
- __attribute__ ((format(printf, 2, 3)));
-void b43warn(struct b43_wl *wl, const char *fmt, ...)
- __attribute__ ((format(printf, 2, 3)));
-#if B43_DEBUG
-void b43dbg(struct b43_wl *wl, const char *fmt, ...)
- __attribute__ ((format(printf, 2, 3)));
-#else /* DEBUG */
-# define b43dbg(wl, fmt...) do { /* nothing */ } while (0)
-#endif /* DEBUG */
-
-/* A WARN_ON variant that vanishes when b43 debugging is disabled.
- * This _also_ evaluates the arg with debugging disabled. */
-#if B43_DEBUG
-# define B43_WARN_ON(x) WARN_ON(x)
-#else
-static inline bool __b43_warn_on_dummy(bool x) { return x; }
-# define B43_WARN_ON(x) __b43_warn_on_dummy(unlikely(!!(x)))
-#endif
-
-/* Convert an integer to a Q5.2 value */
-#define INT_TO_Q52(i) ((i) << 2)
-/* Convert a Q5.2 value to an integer (precision loss!) */
-#define Q52_TO_INT(q52) ((q52) >> 2)
-/* Macros for printing a value in Q5.2 format */
-#define Q52_FMT "%u.%u"
-#define Q52_ARG(q52) Q52_TO_INT(q52), ((((q52) & 0x3) * 100) / 4)
-
-#endif /* B43_H_ */
-/*
-
- Broadcom B43 wireless driver
-
- debugfs driver debugging code
-
- Copyright (c) 2005-2007 Michael Buesch <mb@bu3sch.de>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; see the file COPYING. If not, write to
- the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
- Boston, MA 02110-1301, USA.
-
-*/
-
-#include <linux/fs.h>
-#include <linux/debugfs.h>
-#include <linux/slab.h>
-#include <linux/netdevice.h>
-#include <linux/pci.h>
-#include <linux/mutex.h>
-
-#include "b43.h"
-#include "main.h"
-#include "debugfs.h"
-#include "dma.h"
-#include "xmit.h"
-
-
-/* The root directory. */
-static struct dentry *rootdir;
-
-struct b43_debugfs_fops {
- ssize_t (*read)(struct b43_wldev *dev, char *buf, size_t bufsize);
- int (*write)(struct b43_wldev *dev, const char *buf, size_t count);
- struct file_operations fops;
- /* Offset of struct b43_dfs_file in struct b43_dfsentry */
- size_t file_struct_offset;
- /* Take wl->irq_lock before calling read/write? */
- bool take_irqlock;
-};
-
-static inline
-struct b43_dfs_file * fops_to_dfs_file(struct b43_wldev *dev,
- const struct b43_debugfs_fops *dfops)
-{
- void *p;
-
- p = dev->dfsentry;
- p += dfops->file_struct_offset;
-
- return p;
-}
-
-
-#define fappend(fmt, x...) \
- do { \
- if (bufsize - count) \
- count += snprintf(buf + count, \
- bufsize - count, \
- fmt , ##x); \
- else \
- printk(KERN_ERR "b43: fappend overflow\n"); \
- } while (0)
-
-
-/* wl->irq_lock is locked */
-static ssize_t tsf_read_file(struct b43_wldev *dev,
- char *buf, size_t bufsize)
-{
- ssize_t count = 0;
- u64 tsf;
-
- b43_tsf_read(dev, &tsf);
- fappend("0x%08x%08x\n",
- (unsigned int)((tsf & 0xFFFFFFFF00000000ULL) >> 32),
- (unsigned int)(tsf & 0xFFFFFFFFULL));
-
- return count;
-}
-
-/* wl->irq_lock is locked */
-static int tsf_write_file(struct b43_wldev *dev,
- const char *buf, size_t count)
-{
- u64 tsf;
-
- if (sscanf(buf, "%llu", (unsigned long long *)(&tsf)) != 1)
- return -EINVAL;
- b43_tsf_write(dev, tsf);
-
- return 0;
-}
-
-/* wl->irq_lock is locked */
-static ssize_t ucode_regs_read_file(struct b43_wldev *dev,
- char *buf, size_t bufsize)
-{
- ssize_t count = 0;
- int i;
-
- for (i = 0; i < 64; i++) {
- fappend("r%d = 0x%04x\n", i,
- b43_shm_read16(dev, B43_SHM_SCRATCH, i));
- }
-
- return count;
-}
-
-/* wl->irq_lock is locked */
-static ssize_t shm_read_file(struct b43_wldev *dev,
- char *buf, size_t bufsize)
-{
- ssize_t count = 0;
- int i;
- u16 tmp;
- __le16 *le16buf = (__le16 *)buf;
-
- for (i = 0; i < 0x1000; i++) {
- if (bufsize < sizeof(tmp))
- break;
- tmp = b43_shm_read16(dev, B43_SHM_SHARED, 2 * i);
- le16buf[i] = cpu_to_le16(tmp);
- count += sizeof(tmp);
- bufsize -= sizeof(tmp);
- }
-
- return count;
-}
-
-static ssize_t txstat_read_file(struct b43_wldev *dev,
- char *buf, size_t bufsize)
-{
- struct b43_txstatus_log *log = &dev->dfsentry->txstatlog;
- ssize_t count = 0;
- unsigned long flags;
- int i, idx;
- struct b43_txstatus *stat;
-
- spin_lock_irqsave(&log->lock, flags);
- if (log->end < 0) {
- fappend("Nothing transmitted, yet\n");
- goto out_unlock;
- }
- fappend("b43 TX status reports:\n\n"
- "index | cookie | seq | phy_stat | frame_count | "
- "rts_count | supp_reason | pm_indicated | "
- "intermediate | for_ampdu | acked\n" "---\n");
- i = log->end + 1;
- idx = 0;
- while (1) {
- if (i == B43_NR_LOGGED_TXSTATUS)
- i = 0;
- stat = &(log->log[i]);
- if (stat->cookie) {
- fappend("%03d | "
- "0x%04X | 0x%04X | 0x%02X | "
- "0x%X | 0x%X | "
- "%u | %u | "
- "%u | %u | %u\n",
- idx,
- stat->cookie, stat->seq, stat->phy_stat,
- stat->frame_count, stat->rts_count,
- stat->supp_reason, stat->pm_indicated,
- stat->intermediate, stat->for_ampdu,
- stat->acked);
- idx++;
- }
- if (i == log->end)
- break;
- i++;
- }
-out_unlock:
- spin_unlock_irqrestore(&log->lock, flags);
-
- return count;
-}
-
-static ssize_t txpower_g_read_file(struct b43_wldev *dev,
- char *buf, size_t bufsize)
-{
- ssize_t count = 0;
-
- if (dev->phy.type != B43_PHYTYPE_G) {
- fappend("Device is not a G-PHY\n");
- goto out;
- }
- fappend("Control: %s\n", dev->phy.manual_txpower_control ?
- "MANUAL" : "AUTOMATIC");
- fappend("Baseband attenuation: %u\n", dev->phy.bbatt.att);
- fappend("Radio attenuation: %u\n", dev->phy.rfatt.att);
- fappend("TX Mixer Gain: %s\n",
- (dev->phy.tx_control & B43_TXCTL_TXMIX) ? "ON" : "OFF");
- fappend("PA Gain 2dB: %s\n",
- (dev->phy.tx_control & B43_TXCTL_PA2DB) ? "ON" : "OFF");
- fappend("PA Gain 3dB: %s\n",
- (dev->phy.tx_control & B43_TXCTL_PA3DB) ? "ON" : "OFF");
- fappend("\n\n");
- fappend("You can write to this file:\n");
- fappend("Writing \"auto\" enables automatic txpower control.\n");
- fappend
- ("Writing the attenuation values as \"bbatt rfatt txmix pa2db pa3db\" "
- "enables manual txpower control.\n");
- fappend("Example: 5 4 0 0 1\n");
- fappend("Enables manual control with Baseband attenuation 5, "
- "Radio attenuation 4, No TX Mixer Gain, "
- "No PA Gain 2dB, With PA Gain 3dB.\n");
-out:
- return count;
-}
-
-static int txpower_g_write_file(struct b43_wldev *dev,
- const char *buf, size_t count)
-{
- if (dev->phy.type != B43_PHYTYPE_G)
- return -ENODEV;
- if ((count >= 4) && (memcmp(buf, "auto", 4) == 0)) {
- /* Automatic control */
- dev->phy.manual_txpower_control = 0;
- b43_phy_xmitpower(dev);
- } else {
- int bbatt = 0, rfatt = 0, txmix = 0, pa2db = 0, pa3db = 0;
- /* Manual control */
- if (sscanf(buf, "%d %d %d %d %d", &bbatt, &rfatt,
- &txmix, &pa2db, &pa3db) != 5)
- return -EINVAL;
- b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
- dev->phy.manual_txpower_control = 1;
- dev->phy.bbatt.att = bbatt;
- dev->phy.rfatt.att = rfatt;
- dev->phy.tx_control = 0;
- if (txmix)
- dev->phy.tx_control |= B43_TXCTL_TXMIX;
- if (pa2db)
- dev->phy.tx_control |= B43_TXCTL_PA2DB;
- if (pa3db)
- dev->phy.tx_control |= B43_TXCTL_PA3DB;
- b43_phy_lock(dev);
- b43_radio_lock(dev);
- b43_set_txpower_g(dev, &dev->phy.bbatt,
- &dev->phy.rfatt, dev->phy.tx_control);
- b43_radio_unlock(dev);
- b43_phy_unlock(dev);
- }
-
- return 0;
-}
-
-/* wl->irq_lock is locked */
-static int restart_write_file(struct b43_wldev *dev,
- const char *buf, size_t count)
-{
- int err = 0;
-
- if (count > 0 && buf[0] == '1') {
- b43_controller_restart(dev, "manually restarted");
- } else
- err = -EINVAL;
-
- return err;
-}
-
-static unsigned long calc_expire_secs(unsigned long now,
- unsigned long time,
- unsigned long expire)
-{
- expire = time + expire;
-
- if (time_after(now, expire))
- return 0; /* expired */
- if (expire < now) {
- /* jiffies wrapped */
- expire -= MAX_JIFFY_OFFSET;
- now -= MAX_JIFFY_OFFSET;
- }
- B43_WARN_ON(expire < now);
-
- return (expire - now) / HZ;
-}
-
-static ssize_t loctls_read_file(struct b43_wldev *dev,
- char *buf, size_t bufsize)
-{
- ssize_t count = 0;
- struct b43_txpower_lo_control *lo;
- int i, err = 0;
- struct b43_lo_calib *cal;
- unsigned long now = jiffies;
- struct b43_phy *phy = &dev->phy;
-
- if (phy->type != B43_PHYTYPE_G) {
- fappend("Device is not a G-PHY\n");
- err = -ENODEV;
- goto out;
- }
- lo = phy->lo_control;
- fappend("-- Local Oscillator calibration data --\n\n");
- fappend("HW-power-control enabled: %d\n",
- dev->phy.hardware_power_control);
- fappend("TX Bias: 0x%02X, TX Magn: 0x%02X (expire in %lu sec)\n",
- lo->tx_bias, lo->tx_magn,
- calc_expire_secs(now, lo->txctl_measured_time,
- B43_LO_TXCTL_EXPIRE));
- fappend("Power Vector: 0x%08X%08X (expires in %lu sec)\n",
- (unsigned int)((lo->power_vector & 0xFFFFFFFF00000000ULL) >> 32),
- (unsigned int)(lo->power_vector & 0x00000000FFFFFFFFULL),
- calc_expire_secs(now, lo->pwr_vec_read_time,
- B43_LO_PWRVEC_EXPIRE));
-
- fappend("\nCalibrated settings:\n");
- list_for_each_entry(cal, &lo->calib_list, list) {
- bool active;
-
- active = (b43_compare_bbatt(&cal->bbatt, &phy->bbatt) &&
- b43_compare_rfatt(&cal->rfatt, &phy->rfatt));
- fappend("BB(%d), RF(%d,%d) -> I=%d, Q=%d "
- "(expires in %lu sec)%s\n",
- cal->bbatt.att,
- cal->rfatt.att, cal->rfatt.with_padmix,
- cal->ctl.i, cal->ctl.q,
- calc_expire_secs(now, cal->calib_time,
- B43_LO_CALIB_EXPIRE),
- active ? " ACTIVE" : "");
- }
-
- fappend("\nUsed RF attenuation values: Value(WithPadmix flag)\n");
- for (i = 0; i < lo->rfatt_list.len; i++) {
- fappend("%u(%d), ",
- lo->rfatt_list.list[i].att,
- lo->rfatt_list.list[i].with_padmix);
- }
- fappend("\n");
- fappend("\nUsed Baseband attenuation values:\n");
- for (i = 0; i < lo->bbatt_list.len; i++) {
- fappend("%u, ",
- lo->bbatt_list.list[i].att);
- }
- fappend("\n");
-
-out:
- return err ? err : count;
-}
-
-#undef fappend
-
-static int b43_debugfs_open(struct inode *inode, struct file *file)
-{
- file->private_data = inode->i_private;
- return 0;
-}
-
-static ssize_t b43_debugfs_read(struct file *file, char __user *userbuf,
- size_t count, loff_t *ppos)
-{
- struct b43_wldev *dev;
- struct b43_debugfs_fops *dfops;
- struct b43_dfs_file *dfile;
- ssize_t uninitialized_var(ret);
- char *buf;
- const size_t bufsize = 1024 * 16; /* 16 kiB buffer */
- const size_t buforder = get_order(bufsize);
- int err = 0;
-
- if (!count)
- return 0;
- dev = file->private_data;
- if (!dev)
- return -ENODEV;
-
- mutex_lock(&dev->wl->mutex);
- if (b43_status(dev) < B43_STAT_INITIALIZED) {
- err = -ENODEV;
- goto out_unlock;
- }
-
- dfops = container_of(file->f_op, struct b43_debugfs_fops, fops);
- if (!dfops->read) {
- err = -ENOSYS;
- goto out_unlock;
- }
- dfile = fops_to_dfs_file(dev, dfops);
-
- if (!dfile->buffer) {
- buf = (char *)__get_free_pages(GFP_KERNEL, buforder);
- if (!buf) {
- err = -ENOMEM;
- goto out_unlock;
- }
- memset(buf, 0, bufsize);
- if (dfops->take_irqlock) {
- spin_lock_irq(&dev->wl->irq_lock);
- ret = dfops->read(dev, buf, bufsize);
- spin_unlock_irq(&dev->wl->irq_lock);
- } else
- ret = dfops->read(dev, buf, bufsize);
- if (ret <= 0) {
- free_pages((unsigned long)buf, buforder);
- err = ret;
- goto out_unlock;
- }
- dfile->data_len = ret;
- dfile->buffer = buf;
- }
-
- ret = simple_read_from_buffer(userbuf, count, ppos,
- dfile->buffer,
- dfile->data_len);
- if (*ppos >= dfile->data_len) {
- free_pages((unsigned long)dfile->buffer, buforder);
- dfile->buffer = NULL;
- dfile->data_len = 0;
- }
-out_unlock:
- mutex_unlock(&dev->wl->mutex);
-
- return err ? err : ret;
-}
-
-static ssize_t b43_debugfs_write(struct file *file,
- const char __user *userbuf,
- size_t count, loff_t *ppos)
-{
- struct b43_wldev *dev;
- struct b43_debugfs_fops *dfops;
- char *buf;
- int err = 0;
-
- if (!count)
- return 0;
- if (count > PAGE_SIZE)
- return -E2BIG;
- dev = file->private_data;
- if (!dev)
- return -ENODEV;
-
- mutex_lock(&dev->wl->mutex);
- if (b43_status(dev) < B43_STAT_INITIALIZED) {
- err = -ENODEV;
- goto out_unlock;
- }
-
- dfops = container_of(file->f_op, struct b43_debugfs_fops, fops);
- if (!dfops->write) {
- err = -ENOSYS;
- goto out_unlock;
- }
-
- buf = (char *)get_zeroed_page(GFP_KERNEL);
- if (!buf) {
- err = -ENOMEM;
- goto out_unlock;
- }
- if (copy_from_user(buf, userbuf, count)) {
- err = -EFAULT;
- goto out_freepage;
- }
- if (dfops->take_irqlock) {
- spin_lock_irq(&dev->wl->irq_lock);
- err = dfops->write(dev, buf, count);
- spin_unlock_irq(&dev->wl->irq_lock);
- } else
- err = dfops->write(dev, buf, count);
- if (err)
- goto out_freepage;
-
-out_freepage:
- free_page((unsigned long)buf);
-out_unlock:
- mutex_unlock(&dev->wl->mutex);
-
- return err ? err : count;
-}
-
-
-#define B43_DEBUGFS_FOPS(name, _read, _write, _take_irqlock) \
- static struct b43_debugfs_fops fops_##name = { \
- .read = _read, \
- .write = _write, \
- .fops = { \
- .open = b43_debugfs_open, \
- .read = b43_debugfs_read, \
- .write = b43_debugfs_write, \
- }, \
- .file_struct_offset = offsetof(struct b43_dfsentry, \
- file_##name), \
- .take_irqlock = _take_irqlock, \
- }
-
-B43_DEBUGFS_FOPS(tsf, tsf_read_file, tsf_write_file, 1);
-B43_DEBUGFS_FOPS(ucode_regs, ucode_regs_read_file, NULL, 1);
-B43_DEBUGFS_FOPS(shm, shm_read_file, NULL, 1);
-B43_DEBUGFS_FOPS(txstat, txstat_read_file, NULL, 0);
-B43_DEBUGFS_FOPS(txpower_g, txpower_g_read_file, txpower_g_write_file, 0);
-B43_DEBUGFS_FOPS(restart, NULL, restart_write_file, 1);
-B43_DEBUGFS_FOPS(loctls, loctls_read_file, NULL, 0);
-
-
-int b43_debug(struct b43_wldev *dev, enum b43_dyndbg feature)
-{
- return !!(dev->dfsentry && dev->dfsentry->dyn_debug[feature]);
-}
-
-static void b43_remove_dynamic_debug(struct b43_wldev *dev)
-{
- struct b43_dfsentry *e = dev->dfsentry;
- int i;
-
- for (i = 0; i < __B43_NR_DYNDBG; i++)
- debugfs_remove(e->dyn_debug_dentries[i]);
-}
-
-static void b43_add_dynamic_debug(struct b43_wldev *dev)
-{
- struct b43_dfsentry *e = dev->dfsentry;
- struct dentry *d;
-
-#define add_dyn_dbg(name, id, initstate) do { \
- e->dyn_debug[id] = (initstate); \
- d = debugfs_create_bool(name, 0600, e->subdir, \
- &(e->dyn_debug[id])); \
- if (!IS_ERR(d)) \
- e->dyn_debug_dentries[id] = d; \
- } while (0)
-
- add_dyn_dbg("debug_xmitpower", B43_DBG_XMITPOWER, 0);
- add_dyn_dbg("debug_dmaoverflow", B43_DBG_DMAOVERFLOW, 0);
- add_dyn_dbg("debug_dmaverbose", B43_DBG_DMAVERBOSE, 0);
- add_dyn_dbg("debug_pwork_fast", B43_DBG_PWORK_FAST, 0);
- add_dyn_dbg("debug_pwork_stop", B43_DBG_PWORK_STOP, 0);
- add_dyn_dbg("debug_lo", B43_DBG_LO, 0);
-
-#undef add_dyn_dbg
-}
-
-void b43_debugfs_add_device(struct b43_wldev *dev)
-{
- struct b43_dfsentry *e;
- struct b43_txstatus_log *log;
- char devdir[16];
-
- B43_WARN_ON(!dev);
- e = kzalloc(sizeof(*e), GFP_KERNEL);
- if (!e) {
- b43err(dev->wl, "debugfs: add device OOM\n");
- return;
- }
- e->dev = dev;
- log = &e->txstatlog;
- log->log = kcalloc(B43_NR_LOGGED_TXSTATUS,
- sizeof(struct b43_txstatus), GFP_KERNEL);
- if (!log->log) {
- b43err(dev->wl, "debugfs: add device txstatus OOM\n");
- kfree(e);
- return;
- }
- log->end = -1;
- spin_lock_init(&log->lock);
-
- dev->dfsentry = e;
-
- snprintf(devdir, sizeof(devdir), "%s", wiphy_name(dev->wl->hw->wiphy));
- e->subdir = debugfs_create_dir(devdir, rootdir);
- if (!e->subdir || IS_ERR(e->subdir)) {
- if (e->subdir == ERR_PTR(-ENODEV)) {
- b43dbg(dev->wl, "DebugFS (CONFIG_DEBUG_FS) not "
- "enabled in kernel config\n");
- } else {
- b43err(dev->wl, "debugfs: cannot create %s directory\n",
- devdir);
- }
- dev->dfsentry = NULL;
- kfree(log->log);
- kfree(e);
- return;
- }
-
-#define ADD_FILE(name, mode) \
- do { \
- struct dentry *d; \
- d = debugfs_create_file(__stringify(name), \
- mode, e->subdir, dev, \
- &fops_##name.fops); \
- e->file_##name.dentry = NULL; \
- if (!IS_ERR(d)) \
- e->file_##name.dentry = d; \
- } while (0)
-
-
- ADD_FILE(tsf, 0600);
- ADD_FILE(ucode_regs, 0400);
- ADD_FILE(shm, 0400);
- ADD_FILE(txstat, 0400);
- ADD_FILE(txpower_g, 0600);
- ADD_FILE(restart, 0200);
- ADD_FILE(loctls, 0400);
-
-#undef ADD_FILE
-
- b43_add_dynamic_debug(dev);
-}
-
-void b43_debugfs_remove_device(struct b43_wldev *dev)
-{
- struct b43_dfsentry *e;
-
- if (!dev)
- return;
- e = dev->dfsentry;
- if (!e)
- return;
- b43_remove_dynamic_debug(dev);
-
- debugfs_remove(e->file_tsf.dentry);
- debugfs_remove(e->file_ucode_regs.dentry);
- debugfs_remove(e->file_shm.dentry);
- debugfs_remove(e->file_txstat.dentry);
- debugfs_remove(e->file_txpower_g.dentry);
- debugfs_remove(e->file_restart.dentry);
- debugfs_remove(e->file_loctls.dentry);
-
- debugfs_remove(e->subdir);
- kfree(e->txstatlog.log);
- kfree(e);
-}
-
-/* Called with IRQs disabled. */
-void b43_debugfs_log_txstat(struct b43_wldev *dev,
- const struct b43_txstatus *status)
-{
- struct b43_dfsentry *e = dev->dfsentry;
- struct b43_txstatus_log *log;
- struct b43_txstatus *cur;
- int i;
-
- if (!e)
- return;
- log = &e->txstatlog;
- spin_lock(&log->lock); /* IRQs are already disabled. */
- i = log->end + 1;
- if (i == B43_NR_LOGGED_TXSTATUS)
- i = 0;
- log->end = i;
- cur = &(log->log[i]);
- memcpy(cur, status, sizeof(*cur));
- spin_unlock(&log->lock);
-}
-
-void b43_debugfs_init(void)
-{
- rootdir = debugfs_create_dir(KBUILD_MODNAME, NULL);
- if (IS_ERR(rootdir))
- rootdir = NULL;
-}
-
-void b43_debugfs_exit(void)
-{
- debugfs_remove(rootdir);
-}
-#ifndef B43_DEBUGFS_H_
-#define B43_DEBUGFS_H_
-
-struct b43_wldev;
-struct b43_txstatus;
-
-enum b43_dyndbg { /* Dynamic debugging features */
- B43_DBG_XMITPOWER,
- B43_DBG_DMAOVERFLOW,
- B43_DBG_DMAVERBOSE,
- B43_DBG_PWORK_FAST,
- B43_DBG_PWORK_STOP,
- B43_DBG_LO,
- __B43_NR_DYNDBG,
-};
-
-#ifdef CONFIG_B43_DEBUG
-
-struct dentry;
-
-#define B43_NR_LOGGED_TXSTATUS 100
-
-struct b43_txstatus_log {
- struct b43_txstatus *log;
- int end;
- spinlock_t lock;
-};
-
-struct b43_dfs_file {
- struct dentry *dentry;
- char *buffer;
- size_t data_len;
-};
-
-struct b43_dfsentry {
- struct b43_wldev *dev;
- struct dentry *subdir;
-
- struct b43_dfs_file file_tsf;
- struct b43_dfs_file file_ucode_regs;
- struct b43_dfs_file file_shm;
- struct b43_dfs_file file_txstat;
- struct b43_dfs_file file_txpower_g;
- struct b43_dfs_file file_restart;
- struct b43_dfs_file file_loctls;
-
- struct b43_txstatus_log txstatlog;
-
- /* Enabled/Disabled list for the dynamic debugging features. */
- u32 dyn_debug[__B43_NR_DYNDBG];
- /* Dentries for the dynamic debugging entries. */
- struct dentry *dyn_debug_dentries[__B43_NR_DYNDBG];
-};
-
-int b43_debug(struct b43_wldev *dev, enum b43_dyndbg feature);
-
-void b43_debugfs_init(void);
-void b43_debugfs_exit(void);
-void b43_debugfs_add_device(struct b43_wldev *dev);
-void b43_debugfs_remove_device(struct b43_wldev *dev);
-void b43_debugfs_log_txstat(struct b43_wldev *dev,
- const struct b43_txstatus *status);
-
-#else /* CONFIG_B43_DEBUG */
-
-static inline int b43_debug(struct b43_wldev *dev, enum b43_dyndbg feature)
-{
- return 0;
-}
-
-static inline void b43_debugfs_init(void)
-{
-}
-static inline void b43_debugfs_exit(void)
-{
-}
-static inline void b43_debugfs_add_device(struct b43_wldev *dev)
-{
-}
-static inline void b43_debugfs_remove_device(struct b43_wldev *dev)
-{
-}
-static inline void b43_debugfs_log_txstat(struct b43_wldev *dev,
- const struct b43_txstatus *status)
-{
-}
-
-#endif /* CONFIG_B43_DEBUG */
-
-#endif /* B43_DEBUGFS_H_ */
-/*
-
- Broadcom B43 wireless driver
-
- DMA ringbuffer and descriptor allocation/management
-
- Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
-
- Some code in this file is derived from the b44.c driver
- Copyright (C) 2002 David S. Miller
- Copyright (C) Pekka Pietikainen
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; see the file COPYING. If not, write to
- the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
- Boston, MA 02110-1301, USA.
-
-*/
-
-#include "b43.h"
-#include "dma.h"
-#include "main.h"
-#include "debugfs.h"
-#include "xmit.h"
-
-#include <linux/dma-mapping.h>
-#include <linux/pci.h>
-#include <linux/delay.h>
-#include <linux/skbuff.h>
-#include <linux/etherdevice.h>
-#include <asm/div64.h>
-
-
-/* 32bit DMA ops. */
-static
-struct b43_dmadesc_generic *op32_idx2desc(struct b43_dmaring *ring,
- int slot,
- struct b43_dmadesc_meta **meta)
-{
- struct b43_dmadesc32 *desc;
-
- *meta = &(ring->meta[slot]);
- desc = ring->descbase;
- desc = &(desc[slot]);
-
- return (struct b43_dmadesc_generic *)desc;
-}
-
-static void op32_fill_descriptor(struct b43_dmaring *ring,
- struct b43_dmadesc_generic *desc,
- dma_addr_t dmaaddr, u16 bufsize,
- int start, int end, int irq)
-{
- struct b43_dmadesc32 *descbase = ring->descbase;
- int slot;
- u32 ctl;
- u32 addr;
- u32 addrext;
-
- slot = (int)(&(desc->dma32) - descbase);
- B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
-
- addr = (u32) (dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
- addrext = (u32) (dmaaddr & SSB_DMA_TRANSLATION_MASK)
- >> SSB_DMA_TRANSLATION_SHIFT;
- addr |= ssb_dma_translation(ring->dev->dev);
- ctl = (bufsize - ring->frameoffset)
- & B43_DMA32_DCTL_BYTECNT;
- if (slot == ring->nr_slots - 1)
- ctl |= B43_DMA32_DCTL_DTABLEEND;
- if (start)
- ctl |= B43_DMA32_DCTL_FRAMESTART;
- if (end)
- ctl |= B43_DMA32_DCTL_FRAMEEND;
- if (irq)
- ctl |= B43_DMA32_DCTL_IRQ;
- ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT)
- & B43_DMA32_DCTL_ADDREXT_MASK;
-
- desc->dma32.control = cpu_to_le32(ctl);
- desc->dma32.address = cpu_to_le32(addr);
-}
-
-static void op32_poke_tx(struct b43_dmaring *ring, int slot)
-{
- b43_dma_write(ring, B43_DMA32_TXINDEX,
- (u32) (slot * sizeof(struct b43_dmadesc32)));
-}
-
-static void op32_tx_suspend(struct b43_dmaring *ring)
-{
- b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
- | B43_DMA32_TXSUSPEND);
-}
-
-static void op32_tx_resume(struct b43_dmaring *ring)
-{
- b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
- & ~B43_DMA32_TXSUSPEND);
-}
-
-static int op32_get_current_rxslot(struct b43_dmaring *ring)
-{
- u32 val;
-
- val = b43_dma_read(ring, B43_DMA32_RXSTATUS);
- val &= B43_DMA32_RXDPTR;
-
- return (val / sizeof(struct b43_dmadesc32));
-}
-
-static void op32_set_current_rxslot(struct b43_dmaring *ring, int slot)
-{
- b43_dma_write(ring, B43_DMA32_RXINDEX,
- (u32) (slot * sizeof(struct b43_dmadesc32)));
-}
-
-static const struct b43_dma_ops dma32_ops = {
- .idx2desc = op32_idx2desc,
- .fill_descriptor = op32_fill_descriptor,
- .poke_tx = op32_poke_tx,
- .tx_suspend = op32_tx_suspend,
- .tx_resume = op32_tx_resume,
- .get_current_rxslot = op32_get_current_rxslot,
- .set_current_rxslot = op32_set_current_rxslot,
-};
-
-/* 64bit DMA ops. */
-static
-struct b43_dmadesc_generic *op64_idx2desc(struct b43_dmaring *ring,
- int slot,
- struct b43_dmadesc_meta **meta)
-{
- struct b43_dmadesc64 *desc;
-
- *meta = &(ring->meta[slot]);
- desc = ring->descbase;
- desc = &(desc[slot]);
-
- return (struct b43_dmadesc_generic *)desc;
-}
-
-static void op64_fill_descriptor(struct b43_dmaring *ring,
- struct b43_dmadesc_generic *desc,
- dma_addr_t dmaaddr, u16 bufsize,
- int start, int end, int irq)
-{
- struct b43_dmadesc64 *descbase = ring->descbase;
- int slot;
- u32 ctl0 = 0, ctl1 = 0;
- u32 addrlo, addrhi;
- u32 addrext;
-
- slot = (int)(&(desc->dma64) - descbase);
- B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
-
- addrlo = (u32) (dmaaddr & 0xFFFFFFFF);
- addrhi = (((u64) dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
- addrext = (((u64) dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
- >> SSB_DMA_TRANSLATION_SHIFT;
- addrhi |= (ssb_dma_translation(ring->dev->dev) << 1);
- if (slot == ring->nr_slots - 1)
- ctl0 |= B43_DMA64_DCTL0_DTABLEEND;
- if (start)
- ctl0 |= B43_DMA64_DCTL0_FRAMESTART;
- if (end)
- ctl0 |= B43_DMA64_DCTL0_FRAMEEND;
- if (irq)
- ctl0 |= B43_DMA64_DCTL0_IRQ;
- ctl1 |= (bufsize - ring->frameoffset)
- & B43_DMA64_DCTL1_BYTECNT;
- ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT)
- & B43_DMA64_DCTL1_ADDREXT_MASK;
-
- desc->dma64.control0 = cpu_to_le32(ctl0);
- desc->dma64.control1 = cpu_to_le32(ctl1);
- desc->dma64.address_low = cpu_to_le32(addrlo);
- desc->dma64.address_high = cpu_to_le32(addrhi);
-}
-
-static void op64_poke_tx(struct b43_dmaring *ring, int slot)
-{
- b43_dma_write(ring, B43_DMA64_TXINDEX,
- (u32) (slot * sizeof(struct b43_dmadesc64)));
-}
-
-static void op64_tx_suspend(struct b43_dmaring *ring)
-{
- b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
- | B43_DMA64_TXSUSPEND);
-}
-
-static void op64_tx_resume(struct b43_dmaring *ring)
-{
- b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
- & ~B43_DMA64_TXSUSPEND);
-}
-
-static int op64_get_current_rxslot(struct b43_dmaring *ring)
-{
- u32 val;
-
- val = b43_dma_read(ring, B43_DMA64_RXSTATUS);
- val &= B43_DMA64_RXSTATDPTR;
-
- return (val / sizeof(struct b43_dmadesc64));
-}
-
-static void op64_set_current_rxslot(struct b43_dmaring *ring, int slot)
-{
- b43_dma_write(ring, B43_DMA64_RXINDEX,
- (u32) (slot * sizeof(struct b43_dmadesc64)));
-}
-
-static const struct b43_dma_ops dma64_ops = {
- .idx2desc = op64_idx2desc,
- .fill_descriptor = op64_fill_descriptor,
- .poke_tx = op64_poke_tx,
- .tx_suspend = op64_tx_suspend,
- .tx_resume = op64_tx_resume,
- .get_current_rxslot = op64_get_current_rxslot,
- .set_current_rxslot = op64_set_current_rxslot,
-};
-
-static inline int free_slots(struct b43_dmaring *ring)
-{
- return (ring->nr_slots - ring->used_slots);
-}
-
-static inline int next_slot(struct b43_dmaring *ring, int slot)
-{
- B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
- if (slot == ring->nr_slots - 1)
- return 0;
- return slot + 1;
-}
-
-static inline int prev_slot(struct b43_dmaring *ring, int slot)
-{
- B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
- if (slot == 0)
- return ring->nr_slots - 1;
- return slot - 1;
-}
-
-#ifdef CONFIG_B43_DEBUG
-static void update_max_used_slots(struct b43_dmaring *ring,
- int current_used_slots)
-{
- if (current_used_slots <= ring->max_used_slots)
- return;
- ring->max_used_slots = current_used_slots;
- if (b43_debug(ring->dev, B43_DBG_DMAVERBOSE)) {
- b43dbg(ring->dev->wl,
- "max_used_slots increased to %d on %s ring %d\n",
- ring->max_used_slots,
- ring->tx ? "TX" : "RX", ring->index);
- }
-}
-#else
-static inline
- void update_max_used_slots(struct b43_dmaring *ring, int current_used_slots)
-{
-}
-#endif /* DEBUG */
-
-/* Request a slot for usage. */
-static inline int request_slot(struct b43_dmaring *ring)
-{
- int slot;
-
- B43_WARN_ON(!ring->tx);
- B43_WARN_ON(ring->stopped);
- B43_WARN_ON(free_slots(ring) == 0);
-
- slot = next_slot(ring, ring->current_slot);
- ring->current_slot = slot;
- ring->used_slots++;
-
- update_max_used_slots(ring, ring->used_slots);
-
- return slot;
-}
-
-static u16 b43_dmacontroller_base(enum b43_dmatype type, int controller_idx)
-{
- static const u16 map64[] = {
- B43_MMIO_DMA64_BASE0,
- B43_MMIO_DMA64_BASE1,
- B43_MMIO_DMA64_BASE2,
- B43_MMIO_DMA64_BASE3,
- B43_MMIO_DMA64_BASE4,
- B43_MMIO_DMA64_BASE5,
- };
- static const u16 map32[] = {
- B43_MMIO_DMA32_BASE0,
- B43_MMIO_DMA32_BASE1,
- B43_MMIO_DMA32_BASE2,
- B43_MMIO_DMA32_BASE3,
- B43_MMIO_DMA32_BASE4,
- B43_MMIO_DMA32_BASE5,
- };
-
- if (type == B43_DMA_64BIT) {
- B43_WARN_ON(!(controller_idx >= 0 &&
- controller_idx < ARRAY_SIZE(map64)));
- return map64[controller_idx];
- }
- B43_WARN_ON(!(controller_idx >= 0 &&
- controller_idx < ARRAY_SIZE(map32)));
- return map32[controller_idx];
-}
-
-static inline
- dma_addr_t map_descbuffer(struct b43_dmaring *ring,
- unsigned char *buf, size_t len, int tx)
-{
- dma_addr_t dmaaddr;
-
- if (tx) {
- dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
- buf, len, DMA_TO_DEVICE);
- } else {
- dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
- buf, len, DMA_FROM_DEVICE);
- }
-
- return dmaaddr;
-}
-
-static inline
- void unmap_descbuffer(struct b43_dmaring *ring,
- dma_addr_t addr, size_t len, int tx)
-{
- if (tx) {
- dma_unmap_single(ring->dev->dev->dma_dev,
- addr, len, DMA_TO_DEVICE);
- } else {
- dma_unmap_single(ring->dev->dev->dma_dev,
- addr, len, DMA_FROM_DEVICE);
- }
-}
-
-static inline
- void sync_descbuffer_for_cpu(struct b43_dmaring *ring,
- dma_addr_t addr, size_t len)
-{
- B43_WARN_ON(ring->tx);
- dma_sync_single_for_cpu(ring->dev->dev->dma_dev,
- addr, len, DMA_FROM_DEVICE);
-}
-
-static inline
- void sync_descbuffer_for_device(struct b43_dmaring *ring,
- dma_addr_t addr, size_t len)
-{
- B43_WARN_ON(ring->tx);
- dma_sync_single_for_device(ring->dev->dev->dma_dev,
- addr, len, DMA_FROM_DEVICE);
-}
-
-static inline
- void free_descriptor_buffer(struct b43_dmaring *ring,
- struct b43_dmadesc_meta *meta)
-{
- if (meta->skb) {
- dev_kfree_skb_any(meta->skb);
- meta->skb = NULL;
- }
-}
-
-static int alloc_ringmemory(struct b43_dmaring *ring)
-{
- struct device *dma_dev = ring->dev->dev->dma_dev;
- gfp_t flags = GFP_KERNEL;
-
- /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
- * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing
- * has shown that 4K is sufficient for the latter as long as the buffer
- * does not cross an 8K boundary.
- *
- * For unknown reasons - possibly a hardware error - the BCM4311 rev
- * 02, which uses 64-bit DMA, needs the ring buffer in very low memory,
- * which accounts for the GFP_DMA flag below.
- */
- if (ring->type == B43_DMA_64BIT)
- flags |= GFP_DMA;
- ring->descbase = dma_alloc_coherent(dma_dev, B43_DMA_RINGMEMSIZE,
- &(ring->dmabase), flags);
- if (!ring->descbase) {
- b43err(ring->dev->wl, "DMA ringmemory allocation failed\n");
- return -ENOMEM;
- }
- memset(ring->descbase, 0, B43_DMA_RINGMEMSIZE);
-
- return 0;
-}
-
-static void free_ringmemory(struct b43_dmaring *ring)
-{
- struct device *dma_dev = ring->dev->dev->dma_dev;
-
- dma_free_coherent(dma_dev, B43_DMA_RINGMEMSIZE,
- ring->descbase, ring->dmabase);
-}
-
-/* Reset the RX DMA channel */
-static int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base,
- enum b43_dmatype type)
-{
- int i;
- u32 value;
- u16 offset;
-
- might_sleep();
-
- offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXCTL : B43_DMA32_RXCTL;
- b43_write32(dev, mmio_base + offset, 0);
- for (i = 0; i < 10; i++) {
- offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXSTATUS :
- B43_DMA32_RXSTATUS;
- value = b43_read32(dev, mmio_base + offset);
- if (type == B43_DMA_64BIT) {
- value &= B43_DMA64_RXSTAT;
- if (value == B43_DMA64_RXSTAT_DISABLED) {
- i = -1;
- break;
- }
- } else {
- value &= B43_DMA32_RXSTATE;
- if (value == B43_DMA32_RXSTAT_DISABLED) {
- i = -1;
- break;
- }
- }
- msleep(1);
- }
- if (i != -1) {
- b43err(dev->wl, "DMA RX reset timed out\n");
- return -ENODEV;
- }
-
- return 0;
-}
-
-/* Reset the TX DMA channel */
-static int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base,
- enum b43_dmatype type)
-{
- int i;
- u32 value;
- u16 offset;
-
- might_sleep();
-
- for (i = 0; i < 10; i++) {
- offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
- B43_DMA32_TXSTATUS;
- value = b43_read32(dev, mmio_base + offset);
- if (type == B43_DMA_64BIT) {
- value &= B43_DMA64_TXSTAT;
- if (value == B43_DMA64_TXSTAT_DISABLED ||
- value == B43_DMA64_TXSTAT_IDLEWAIT ||
- value == B43_DMA64_TXSTAT_STOPPED)
- break;
- } else {
- value &= B43_DMA32_TXSTATE;
- if (value == B43_DMA32_TXSTAT_DISABLED ||
- value == B43_DMA32_TXSTAT_IDLEWAIT ||
- value == B43_DMA32_TXSTAT_STOPPED)
- break;
- }
- msleep(1);
- }
- offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXCTL : B43_DMA32_TXCTL;
- b43_write32(dev, mmio_base + offset, 0);
- for (i = 0; i < 10; i++) {
- offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
- B43_DMA32_TXSTATUS;
- value = b43_read32(dev, mmio_base + offset);
- if (type == B43_DMA_64BIT) {
- value &= B43_DMA64_TXSTAT;
- if (value == B43_DMA64_TXSTAT_DISABLED) {
- i = -1;
- break;
- }
- } else {
- value &= B43_DMA32_TXSTATE;
- if (value == B43_DMA32_TXSTAT_DISABLED) {
- i = -1;
- break;
- }
- }
- msleep(1);
- }
- if (i != -1) {
- b43err(dev->wl, "DMA TX reset timed out\n");
- return -ENODEV;
- }
- /* ensure the reset is completed. */
- msleep(1);
-
- return 0;
-}
-
-/* Check if a DMA mapping address is invalid. */
-static bool b43_dma_mapping_error(struct b43_dmaring *ring,
- dma_addr_t addr,
- size_t buffersize, bool dma_to_device)
-{
- if (unlikely(dma_mapping_error(addr)))
- return 1;
-
- switch (ring->type) {
- case B43_DMA_30BIT:
- if ((u64)addr + buffersize > (1ULL << 30))
- goto address_error;
- break;
- case B43_DMA_32BIT:
- if ((u64)addr + buffersize > (1ULL << 32))
- goto address_error;
- break;
- case B43_DMA_64BIT:
- /* Currently we can't have addresses beyond
- * 64bit in the kernel. */
- break;
- }
-
- /* The address is OK. */
- return 0;
-
-address_error:
- /* We can't support this address. Unmap it again. */
- unmap_descbuffer(ring, addr, buffersize, dma_to_device);
-
- return 1;
-}
-
-static int setup_rx_descbuffer(struct b43_dmaring *ring,
- struct b43_dmadesc_generic *desc,
- struct b43_dmadesc_meta *meta, gfp_t gfp_flags)
-{
- struct b43_rxhdr_fw4 *rxhdr;
- dma_addr_t dmaaddr;
- struct sk_buff *skb;
-
- B43_WARN_ON(ring->tx);
-
- skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
- if (unlikely(!skb))
- return -ENOMEM;
- dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0);
- if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
- /* ugh. try to realloc in zone_dma */
- gfp_flags |= GFP_DMA;
-
- dev_kfree_skb_any(skb);
-
- skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
- if (unlikely(!skb))
- return -ENOMEM;
- dmaaddr = map_descbuffer(ring, skb->data,
- ring->rx_buffersize, 0);
- }
-
- if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
- b43err(ring->dev->wl, "RX DMA buffer allocation failed\n");
- dev_kfree_skb_any(skb);
- return -EIO;
- }
-
- meta->skb = skb;
- meta->dmaaddr = dmaaddr;
- ring->ops->fill_descriptor(ring, desc, dmaaddr,
- ring->rx_buffersize, 0, 0, 0);
-
- rxhdr = (struct b43_rxhdr_fw4 *)(skb->data);
- rxhdr->frame_len = 0;
-
- return 0;
-}
-
-/* Allocate the initial descbuffers.
- * This is used for an RX ring only.
- */
-static int alloc_initial_descbuffers(struct b43_dmaring *ring)
-{
- int i, err = -ENOMEM;
- struct b43_dmadesc_generic *desc;
- struct b43_dmadesc_meta *meta;
-
- for (i = 0; i < ring->nr_slots; i++) {
- desc = ring->ops->idx2desc(ring, i, &meta);
-
- err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
- if (err) {
- b43err(ring->dev->wl,
- "Failed to allocate initial descbuffers\n");
- goto err_unwind;
- }
- }
- mb();
- ring->used_slots = ring->nr_slots;
- err = 0;
- out:
- return err;
-
- err_unwind:
- for (i--; i >= 0; i--) {
- desc = ring->ops->idx2desc(ring, i, &meta);
-
- unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
- dev_kfree_skb(meta->skb);
- }
- goto out;
-}
-
-/* Do initial setup of the DMA controller.
- * Reset the controller, write the ring busaddress
- * and switch the "enable" bit on.
- */
-static int dmacontroller_setup(struct b43_dmaring *ring)
-{
- int err = 0;
- u32 value;
- u32 addrext;
- u32 trans = ssb_dma_translation(ring->dev->dev);
-
- if (ring->tx) {
- if (ring->type == B43_DMA_64BIT) {
- u64 ringbase = (u64) (ring->dmabase);
-
- addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
- >> SSB_DMA_TRANSLATION_SHIFT;
- value = B43_DMA64_TXENABLE;
- value |= (addrext << B43_DMA64_TXADDREXT_SHIFT)
- & B43_DMA64_TXADDREXT_MASK;
- b43_dma_write(ring, B43_DMA64_TXCTL, value);
- b43_dma_write(ring, B43_DMA64_TXRINGLO,
- (ringbase & 0xFFFFFFFF));
- b43_dma_write(ring, B43_DMA64_TXRINGHI,
- ((ringbase >> 32) &
- ~SSB_DMA_TRANSLATION_MASK)
- | (trans << 1));
- } else {
- u32 ringbase = (u32) (ring->dmabase);
-
- addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
- >> SSB_DMA_TRANSLATION_SHIFT;
- value = B43_DMA32_TXENABLE;
- value |= (addrext << B43_DMA32_TXADDREXT_SHIFT)
- & B43_DMA32_TXADDREXT_MASK;
- b43_dma_write(ring, B43_DMA32_TXCTL, value);
- b43_dma_write(ring, B43_DMA32_TXRING,
- (ringbase & ~SSB_DMA_TRANSLATION_MASK)
- | trans);
- }
- } else {
- err = alloc_initial_descbuffers(ring);
- if (err)
- goto out;
- if (ring->type == B43_DMA_64BIT) {
- u64 ringbase = (u64) (ring->dmabase);
-
- addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
- >> SSB_DMA_TRANSLATION_SHIFT;
- value = (ring->frameoffset << B43_DMA64_RXFROFF_SHIFT);
- value |= B43_DMA64_RXENABLE;
- value |= (addrext << B43_DMA64_RXADDREXT_SHIFT)
- & B43_DMA64_RXADDREXT_MASK;
- b43_dma_write(ring, B43_DMA64_RXCTL, value);
- b43_dma_write(ring, B43_DMA64_RXRINGLO,
- (ringbase & 0xFFFFFFFF));
- b43_dma_write(ring, B43_DMA64_RXRINGHI,
- ((ringbase >> 32) &
- ~SSB_DMA_TRANSLATION_MASK)
- | (trans << 1));
- b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots *
- sizeof(struct b43_dmadesc64));
- } else {
- u32 ringbase = (u32) (ring->dmabase);
-
- addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
- >> SSB_DMA_TRANSLATION_SHIFT;
- value = (ring->frameoffset << B43_DMA32_RXFROFF_SHIFT);
- value |= B43_DMA32_RXENABLE;
- value |= (addrext << B43_DMA32_RXADDREXT_SHIFT)
- & B43_DMA32_RXADDREXT_MASK;
- b43_dma_write(ring, B43_DMA32_RXCTL, value);
- b43_dma_write(ring, B43_DMA32_RXRING,
- (ringbase & ~SSB_DMA_TRANSLATION_MASK)
- | trans);
- b43_dma_write(ring, B43_DMA32_RXINDEX, ring->nr_slots *
- sizeof(struct b43_dmadesc32));
- }
- }
-
-out:
- return err;
-}
-
-/* Shutdown the DMA controller. */
-static void dmacontroller_cleanup(struct b43_dmaring *ring)
-{
- if (ring->tx) {
- b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
- ring->type);
- if (ring->type == B43_DMA_64BIT) {
- b43_dma_write(ring, B43_DMA64_TXRINGLO, 0);
- b43_dma_write(ring, B43_DMA64_TXRINGHI, 0);
- } else
- b43_dma_write(ring, B43_DMA32_TXRING, 0);
- } else {
- b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
- ring->type);
- if (ring->type == B43_DMA_64BIT) {
- b43_dma_write(ring, B43_DMA64_RXRINGLO, 0);
- b43_dma_write(ring, B43_DMA64_RXRINGHI, 0);
- } else
- b43_dma_write(ring, B43_DMA32_RXRING, 0);
- }
-}
-
-static void free_all_descbuffers(struct b43_dmaring *ring)
-{
- struct b43_dmadesc_generic *desc;
- struct b43_dmadesc_meta *meta;
- int i;
-
- if (!ring->used_slots)
- return;
- for (i = 0; i < ring->nr_slots; i++) {
- desc = ring->ops->idx2desc(ring, i, &meta);
-
- if (!meta->skb) {
- B43_WARN_ON(!ring->tx);
- continue;
- }
- if (ring->tx) {
- unmap_descbuffer(ring, meta->dmaaddr,
- meta->skb->len, 1);
- } else {
- unmap_descbuffer(ring, meta->dmaaddr,
- ring->rx_buffersize, 0);
- }
- free_descriptor_buffer(ring, meta);
- }
-}
-
-static u64 supported_dma_mask(struct b43_wldev *dev)
-{
- u32 tmp;
- u16 mmio_base;
-
- tmp = b43_read32(dev, SSB_TMSHIGH);
- if (tmp & SSB_TMSHIGH_DMA64)
- return DMA_64BIT_MASK;
- mmio_base = b43_dmacontroller_base(0, 0);
- b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK);
- tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL);
- if (tmp & B43_DMA32_TXADDREXT_MASK)
- return DMA_32BIT_MASK;
-
- return DMA_30BIT_MASK;
-}
-
-static enum b43_dmatype dma_mask_to_engine_type(u64 dmamask)
-{
- if (dmamask == DMA_30BIT_MASK)
- return B43_DMA_30BIT;
- if (dmamask == DMA_32BIT_MASK)
- return B43_DMA_32BIT;
- if (dmamask == DMA_64BIT_MASK)
- return B43_DMA_64BIT;
- B43_WARN_ON(1);
- return B43_DMA_30BIT;
-}
-
-/* Main initialization function. */
-static
-struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
- int controller_index,
- int for_tx,
- enum b43_dmatype type)
-{
- struct b43_dmaring *ring;
- int err;
- int nr_slots;
- dma_addr_t dma_test;
-
- ring = kzalloc(sizeof(*ring), GFP_KERNEL);
- if (!ring)
- goto out;
- ring->type = type;
-
- nr_slots = B43_RXRING_SLOTS;
- if (for_tx)
- nr_slots = B43_TXRING_SLOTS;
-
- ring->meta = kcalloc(nr_slots, sizeof(struct b43_dmadesc_meta),
- GFP_KERNEL);
- if (!ring->meta)
- goto err_kfree_ring;
- if (for_tx) {
- ring->txhdr_cache = kcalloc(nr_slots,
- b43_txhdr_size(dev),
- GFP_KERNEL);
- if (!ring->txhdr_cache)
- goto err_kfree_meta;
-
- /* test for ability to dma to txhdr_cache */
- dma_test = dma_map_single(dev->dev->dma_dev,
- ring->txhdr_cache,
- b43_txhdr_size(dev),
- DMA_TO_DEVICE);
-
- if (b43_dma_mapping_error(ring, dma_test,
- b43_txhdr_size(dev), 1)) {
- /* ugh realloc */
- kfree(ring->txhdr_cache);
- ring->txhdr_cache = kcalloc(nr_slots,
- b43_txhdr_size(dev),
- GFP_KERNEL | GFP_DMA);
- if (!ring->txhdr_cache)
- goto err_kfree_meta;
-
- dma_test = dma_map_single(dev->dev->dma_dev,
- ring->txhdr_cache,
- b43_txhdr_size(dev),
- DMA_TO_DEVICE);
-
- if (b43_dma_mapping_error(ring, dma_test,
- b43_txhdr_size(dev), 1)) {
-
- b43err(dev->wl,
- "TXHDR DMA allocation failed\n");
- goto err_kfree_txhdr_cache;
- }
- }
-
- dma_unmap_single(dev->dev->dma_dev,
- dma_test, b43_txhdr_size(dev),
- DMA_TO_DEVICE);
- }
-
- ring->dev = dev;
- ring->nr_slots = nr_slots;
- ring->mmio_base = b43_dmacontroller_base(type, controller_index);
- ring->index = controller_index;
- if (type == B43_DMA_64BIT)
- ring->ops = &dma64_ops;
- else
- ring->ops = &dma32_ops;
- if (for_tx) {
- ring->tx = 1;
- ring->current_slot = -1;
- } else {
- if (ring->index == 0) {
- ring->rx_buffersize = B43_DMA0_RX_BUFFERSIZE;
- ring->frameoffset = B43_DMA0_RX_FRAMEOFFSET;
- } else if (ring->index == 3) {
- ring->rx_buffersize = B43_DMA3_RX_BUFFERSIZE;
- ring->frameoffset = B43_DMA3_RX_FRAMEOFFSET;
- } else
- B43_WARN_ON(1);
- }
- spin_lock_init(&ring->lock);
-#ifdef CONFIG_B43_DEBUG
- ring->last_injected_overflow = jiffies;
-#endif
-
- err = alloc_ringmemory(ring);
- if (err)
- goto err_kfree_txhdr_cache;
- err = dmacontroller_setup(ring);
- if (err)
- goto err_free_ringmemory;
-
- out:
- return ring;
-
- err_free_ringmemory:
- free_ringmemory(ring);
- err_kfree_txhdr_cache:
- kfree(ring->txhdr_cache);
- err_kfree_meta:
- kfree(ring->meta);
- err_kfree_ring:
- kfree(ring);
- ring = NULL;
- goto out;
-}
-
-#define divide(a, b) ({ \
- typeof(a) __a = a; \
- do_div(__a, b); \
- __a; \
- })
-
-#define modulo(a, b) ({ \
- typeof(a) __a = a; \
- do_div(__a, b); \
- })
-
-/* Main cleanup function. */
-static void b43_destroy_dmaring(struct b43_dmaring *ring,
- const char *ringname)
-{
- if (!ring)
- return;
-
-#ifdef CONFIG_B43_DEBUG
- {
- /* Print some statistics. */
- u64 failed_packets = ring->nr_failed_tx_packets;
- u64 succeed_packets = ring->nr_succeed_tx_packets;
- u64 nr_packets = failed_packets + succeed_packets;
- u64 permille_failed = 0, average_tries = 0;
-
- if (nr_packets)
- permille_failed = divide(failed_packets * 1000, nr_packets);
- if (nr_packets)
- average_tries = divide(ring->nr_total_packet_tries * 100, nr_packets);
-
- b43dbg(ring->dev->wl, "DMA-%u %s: "
- "Used slots %d/%d, Failed frames %llu/%llu = %llu.%01llu%%, "
- "Average tries %llu.%02llu\n",
- (unsigned int)(ring->type), ringname,
- ring->max_used_slots,
- ring->nr_slots,
- (unsigned long long)failed_packets,
- (unsigned long long)nr_packets,
- (unsigned long long)divide(permille_failed, 10),
- (unsigned long long)modulo(permille_failed, 10),
- (unsigned long long)divide(average_tries, 100),
- (unsigned long long)modulo(average_tries, 100));
- }
-#endif /* DEBUG */
-
- /* Device IRQs are disabled prior entering this function,
- * so no need to take care of concurrency with rx handler stuff.
- */
- dmacontroller_cleanup(ring);
- free_all_descbuffers(ring);
- free_ringmemory(ring);
-
- kfree(ring->txhdr_cache);
- kfree(ring->meta);
- kfree(ring);
-}
-
-#define destroy_ring(dma, ring) do { \
- b43_destroy_dmaring((dma)->ring, __stringify(ring)); \
- (dma)->ring = NULL; \
- } while (0)
-
-void b43_dma_free(struct b43_wldev *dev)
-{
- struct b43_dma *dma;
-
- if (b43_using_pio_transfers(dev))
- return;
- dma = &dev->dma;
-
- destroy_ring(dma, rx_ring);
- destroy_ring(dma, tx_ring_AC_BK);
- destroy_ring(dma, tx_ring_AC_BE);
- destroy_ring(dma, tx_ring_AC_VI);
- destroy_ring(dma, tx_ring_AC_VO);
- destroy_ring(dma, tx_ring_mcast);
-}
-
-static int b43_dma_set_mask(struct b43_wldev *dev, u64 mask)
-{
- u64 orig_mask = mask;
- bool fallback = 0;
- int err;
-
- /* Try to set the DMA mask. If it fails, try falling back to a
- * lower mask, as we can always also support a lower one. */
- while (1) {
- err = ssb_dma_set_mask(dev->dev, mask);
- if (!err)
- break;
- if (mask == DMA_64BIT_MASK) {
- mask = DMA_32BIT_MASK;
- fallback = 1;
- continue;
- }
- if (mask == DMA_32BIT_MASK) {
- mask = DMA_30BIT_MASK;
- fallback = 1;
- continue;
- }
- b43err(dev->wl, "The machine/kernel does not support "
- "the required %u-bit DMA mask\n",
- (unsigned int)dma_mask_to_engine_type(orig_mask));
- return -EOPNOTSUPP;
- }
- if (fallback) {
- b43info(dev->wl, "DMA mask fallback from %u-bit to %u-bit\n",
- (unsigned int)dma_mask_to_engine_type(orig_mask),
- (unsigned int)dma_mask_to_engine_type(mask));
- }
-
- return 0;
-}
-
-int b43_dma_init(struct b43_wldev *dev)
-{
- struct b43_dma *dma = &dev->dma;
- int err;
- u64 dmamask;
- enum b43_dmatype type;
-
- dmamask = supported_dma_mask(dev);
- type = dma_mask_to_engine_type(dmamask);
- err = b43_dma_set_mask(dev, dmamask);
- if (err)
- return err;
-
- err = -ENOMEM;
- /* setup TX DMA channels. */
- dma->tx_ring_AC_BK = b43_setup_dmaring(dev, 0, 1, type);
- if (!dma->tx_ring_AC_BK)
- goto out;
-
- dma->tx_ring_AC_BE = b43_setup_dmaring(dev, 1, 1, type);
- if (!dma->tx_ring_AC_BE)
- goto err_destroy_bk;
-
- dma->tx_ring_AC_VI = b43_setup_dmaring(dev, 2, 1, type);
- if (!dma->tx_ring_AC_VI)
- goto err_destroy_be;
-
- dma->tx_ring_AC_VO = b43_setup_dmaring(dev, 3, 1, type);
- if (!dma->tx_ring_AC_VO)
- goto err_destroy_vi;
-
- dma->tx_ring_mcast = b43_setup_dmaring(dev, 4, 1, type);
- if (!dma->tx_ring_mcast)
- goto err_destroy_vo;
-
- /* setup RX DMA channel. */
- dma->rx_ring = b43_setup_dmaring(dev, 0, 0, type);
- if (!dma->rx_ring)
- goto err_destroy_mcast;
-
- /* No support for the TX status DMA ring. */
- B43_WARN_ON(dev->dev->id.revision < 5);
-
- b43dbg(dev->wl, "%u-bit DMA initialized\n",
- (unsigned int)type);
- err = 0;
-out:
- return err;
-
-err_destroy_mcast:
- destroy_ring(dma, tx_ring_mcast);
-err_destroy_vo:
- destroy_ring(dma, tx_ring_AC_VO);
-err_destroy_vi:
- destroy_ring(dma, tx_ring_AC_VI);
-err_destroy_be:
- destroy_ring(dma, tx_ring_AC_BE);
-err_destroy_bk:
- destroy_ring(dma, tx_ring_AC_BK);
- return err;
-}
-
-/* Generate a cookie for the TX header. */
-static u16 generate_cookie(struct b43_dmaring *ring, int slot)
-{
- u16 cookie;
-
- /* Use the upper 4 bits of the cookie as
- * DMA controller ID and store the slot number
- * in the lower 12 bits.
- * Note that the cookie must never be 0, as this
- * is a special value used in RX path.
- * It can also not be 0xFFFF because that is special
- * for multicast frames.
- */
- cookie = (((u16)ring->index + 1) << 12);
- B43_WARN_ON(slot & ~0x0FFF);
- cookie |= (u16)slot;
-
- return cookie;
-}
-
-/* Inspect a cookie and find out to which controller/slot it belongs. */
-static
-struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot)
-{
- struct b43_dma *dma = &dev->dma;
- struct b43_dmaring *ring = NULL;
-
- switch (cookie & 0xF000) {
- case 0x1000:
- ring = dma->tx_ring_AC_BK;
- break;
- case 0x2000:
- ring = dma->tx_ring_AC_BE;
- break;
- case 0x3000:
- ring = dma->tx_ring_AC_VI;
- break;
- case 0x4000:
- ring = dma->tx_ring_AC_VO;
- break;
- case 0x5000:
- ring = dma->tx_ring_mcast;
- break;
- default:
- B43_WARN_ON(1);
- }
- *slot = (cookie & 0x0FFF);
- B43_WARN_ON(!(ring && *slot >= 0 && *slot < ring->nr_slots));
-
- return ring;
-}
-
-static int dma_tx_fragment(struct b43_dmaring *ring,
- struct sk_buff *skb)
-{
- const struct b43_dma_ops *ops = ring->ops;
- struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
- u8 *header;
- int slot, old_top_slot, old_used_slots;
- int err;
- struct b43_dmadesc_generic *desc;
- struct b43_dmadesc_meta *meta;
- struct b43_dmadesc_meta *meta_hdr;
- struct sk_buff *bounce_skb;
- u16 cookie;
- size_t hdrsize = b43_txhdr_size(ring->dev);
-
-#define SLOTS_PER_PACKET 2
-
- old_top_slot = ring->current_slot;
- old_used_slots = ring->used_slots;
-
- /* Get a slot for the header. */
- slot = request_slot(ring);
- desc = ops->idx2desc(ring, slot, &meta_hdr);
- memset(meta_hdr, 0, sizeof(*meta_hdr));
-
- header = &(ring->txhdr_cache[slot * hdrsize]);
- cookie = generate_cookie(ring, slot);
- err = b43_generate_txhdr(ring->dev, header,
- skb->data, skb->len, info, cookie);
- if (unlikely(err)) {
- ring->current_slot = old_top_slot;
- ring->used_slots = old_used_slots;
- return err;
- }
-
- meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
- hdrsize, 1);
- if (b43_dma_mapping_error(ring, meta_hdr->dmaaddr, hdrsize, 1)) {
- ring->current_slot = old_top_slot;
- ring->used_slots = old_used_slots;
- return -EIO;
- }
- ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
- hdrsize, 1, 0, 0);
-
- /* Get a slot for the payload. */
- slot = request_slot(ring);
- desc = ops->idx2desc(ring, slot, &meta);
- memset(meta, 0, sizeof(*meta));
-
- meta->skb = skb;
- meta->is_last_fragment = 1;
-
- meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
- /* create a bounce buffer in zone_dma on mapping failure. */
- if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
- bounce_skb = __dev_alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA);
- if (!bounce_skb) {
- ring->current_slot = old_top_slot;
- ring->used_slots = old_used_slots;
- err = -ENOMEM;
- goto out_unmap_hdr;
- }
-
- memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len);
- dev_kfree_skb_any(skb);
- skb = bounce_skb;
- meta->skb = skb;
- meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
- if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
- ring->current_slot = old_top_slot;
- ring->used_slots = old_used_slots;
- err = -EIO;
- goto out_free_bounce;
- }
- }
-
- ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1);
-
- if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
- /* Tell the firmware about the cookie of the last
- * mcast frame, so it can clear the more-data bit in it. */
- b43_shm_write16(ring->dev, B43_SHM_SHARED,
- B43_SHM_SH_MCASTCOOKIE, cookie);
- }
- /* Now transfer the whole frame. */
- wmb();
- ops->poke_tx(ring, next_slot(ring, slot));
- return 0;
-
-out_free_bounce:
- dev_kfree_skb_any(skb);
-out_unmap_hdr:
- unmap_descbuffer(ring, meta_hdr->dmaaddr,
- hdrsize, 1);
- return err;
-}
-
-static inline int should_inject_overflow(struct b43_dmaring *ring)
-{
-#ifdef CONFIG_B43_DEBUG
- if (unlikely(b43_debug(ring->dev, B43_DBG_DMAOVERFLOW))) {
- /* Check if we should inject another ringbuffer overflow
- * to test handling of this situation in the stack. */
- unsigned long next_overflow;
-
- next_overflow = ring->last_injected_overflow + HZ;
- if (time_after(jiffies, next_overflow)) {
- ring->last_injected_overflow = jiffies;
- b43dbg(ring->dev->wl,
- "Injecting TX ring overflow on "
- "DMA controller %d\n", ring->index);
- return 1;
- }
- }
-#endif /* CONFIG_B43_DEBUG */
- return 0;
-}
-
-/* Static mapping of mac80211's queues (priorities) to b43 DMA rings. */
-static struct b43_dmaring * select_ring_by_priority(struct b43_wldev *dev,
- u8 queue_prio)
-{
- struct b43_dmaring *ring;
-
- if (b43_modparam_qos) {
- /* 0 = highest priority */
- switch (queue_prio) {
- default:
- B43_WARN_ON(1);
- /* fallthrough */
- case 0:
- ring = dev->dma.tx_ring_AC_VO;
- break;
- case 1:
- ring = dev->dma.tx_ring_AC_VI;
- break;
- case 2:
- ring = dev->dma.tx_ring_AC_BE;
- break;
- case 3:
- ring = dev->dma.tx_ring_AC_BK;
- break;
- }
- } else
- ring = dev->dma.tx_ring_AC_BE;
-
- return ring;
-}
-
-int b43_dma_tx(struct b43_wldev *dev, struct sk_buff *skb)
-{
- struct b43_dmaring *ring;
- struct ieee80211_hdr *hdr;
- int err = 0;
- unsigned long flags;
- struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
-
- hdr = (struct ieee80211_hdr *)skb->data;
- if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
- /* The multicast ring will be sent after the DTIM */
- ring = dev->dma.tx_ring_mcast;
- /* Set the more-data bit. Ucode will clear it on
- * the last frame for us. */
- hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
- } else {
- /* Decide by priority where to put this frame. */
- ring = select_ring_by_priority(
- dev, skb_get_queue_mapping(skb));
- }
-
- spin_lock_irqsave(&ring->lock, flags);
- B43_WARN_ON(!ring->tx);
- if (unlikely(free_slots(ring) < SLOTS_PER_PACKET)) {
- b43warn(dev->wl, "DMA queue overflow\n");
- err = -ENOSPC;
- goto out_unlock;
- }
- /* Check if the queue was stopped in mac80211,
- * but we got called nevertheless.
- * That would be a mac80211 bug. */
- B43_WARN_ON(ring->stopped);
-
- /* Assign the queue number to the ring (if not already done before)
- * so TX status handling can use it. The queue to ring mapping is
- * static, so we don't need to store it per frame. */
- ring->queue_prio = skb_get_queue_mapping(skb);
-
- err = dma_tx_fragment(ring, skb);
- if (unlikely(err == -ENOKEY)) {
- /* Drop this packet, as we don't have the encryption key
- * anymore and must not transmit it unencrypted. */
- dev_kfree_skb_any(skb);
- err = 0;
- goto out_unlock;
- }
- if (unlikely(err)) {
- b43err(dev->wl, "DMA tx mapping failure\n");
- goto out_unlock;
- }
- ring->nr_tx_packets++;
- if ((free_slots(ring) < SLOTS_PER_PACKET) ||
- should_inject_overflow(ring)) {
- /* This TX ring is full. */
- ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
- ring->stopped = 1;
- if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
- b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index);
- }
- }
-out_unlock:
- spin_unlock_irqrestore(&ring->lock, flags);
-
- return err;
-}
-
-/* Called with IRQs disabled. */
-void b43_dma_handle_txstatus(struct b43_wldev *dev,
- const struct b43_txstatus *status)
-{
- const struct b43_dma_ops *ops;
- struct b43_dmaring *ring;
- struct b43_dmadesc_generic *desc;
- struct b43_dmadesc_meta *meta;
- int slot;
- bool frame_succeed;
-
- ring = parse_cookie(dev, status->cookie, &slot);
- if (unlikely(!ring))
- return;
-
- spin_lock(&ring->lock); /* IRQs are already disabled. */
-
- B43_WARN_ON(!ring->tx);
- ops = ring->ops;
- while (1) {
- B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
- desc = ops->idx2desc(ring, slot, &meta);
-
- if (meta->skb)
- unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len,
- 1);
- else
- unmap_descbuffer(ring, meta->dmaaddr,
- b43_txhdr_size(dev), 1);
-
- if (meta->is_last_fragment) {
- struct ieee80211_tx_info *info;
-
- BUG_ON(!meta->skb);
-
- info = IEEE80211_SKB_CB(meta->skb);
-
- memset(&info->status, 0, sizeof(info->status));
-
- /*
- * Call back to inform the ieee80211 subsystem about
- * the status of the transmission.
- */
- frame_succeed = b43_fill_txstatus_report(info, status);
-#ifdef CONFIG_B43_DEBUG
- if (frame_succeed)
- ring->nr_succeed_tx_packets++;
- else
- ring->nr_failed_tx_packets++;
- ring->nr_total_packet_tries += status->frame_count;
-#endif /* DEBUG */
- ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb);
-
- /* skb is freed by ieee80211_tx_status_irqsafe() */
- meta->skb = NULL;
- } else {
- /* No need to call free_descriptor_buffer here, as
- * this is only the txhdr, which is not allocated.
- */
- B43_WARN_ON(meta->skb);
- }
-
- /* Everything unmapped and free'd. So it's not used anymore. */
- ring->used_slots--;
-
- if (meta->is_last_fragment)
- break;
- slot = next_slot(ring, slot);
- }
- dev->stats.last_tx = jiffies;
- if (ring->stopped) {
- B43_WARN_ON(free_slots(ring) < SLOTS_PER_PACKET);
- ieee80211_wake_queue(dev->wl->hw, ring->queue_prio);
- ring->stopped = 0;
- if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
- b43dbg(dev->wl, "Woke up TX ring %d\n", ring->index);
- }
- }
-
- spin_unlock(&ring->lock);
-}
-
-void b43_dma_get_tx_stats(struct b43_wldev *dev,
- struct ieee80211_tx_queue_stats *stats)
-{
- const int nr_queues = dev->wl->hw->queues;
- struct b43_dmaring *ring;
- unsigned long flags;
- int i;
-
- for (i = 0; i < nr_queues; i++) {
- ring = select_ring_by_priority(dev, i);
-
- spin_lock_irqsave(&ring->lock, flags);
- stats[i].len = ring->used_slots / SLOTS_PER_PACKET;
- stats[i].limit = ring->nr_slots / SLOTS_PER_PACKET;
- stats[i].count = ring->nr_tx_packets;
- spin_unlock_irqrestore(&ring->lock, flags);
- }
-}
-
-static void dma_rx(struct b43_dmaring *ring, int *slot)
-{
- const struct b43_dma_ops *ops = ring->ops;
- struct b43_dmadesc_generic *desc;
- struct b43_dmadesc_meta *meta;
- struct b43_rxhdr_fw4 *rxhdr;
- struct sk_buff *skb;
- u16 len;
- int err;
- dma_addr_t dmaaddr;
-
- desc = ops->idx2desc(ring, *slot, &meta);
-
- sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
- skb = meta->skb;
-
- rxhdr = (struct b43_rxhdr_fw4 *)skb->data;
- len = le16_to_cpu(rxhdr->frame_len);
- if (len == 0) {
- int i = 0;
-
- do {
- udelay(2);
- barrier();
- len = le16_to_cpu(rxhdr->frame_len);
- } while (len == 0 && i++ < 5);
- if (unlikely(len == 0)) {
- /* recycle the descriptor buffer. */
- sync_descbuffer_for_device(ring, meta->dmaaddr,
- ring->rx_buffersize);
- goto drop;
- }
- }
- if (unlikely(len > ring->rx_buffersize)) {
- /* The data did not fit into one descriptor buffer
- * and is split over multiple buffers.
- * This should never happen, as we try to allocate buffers
- * big enough. So simply ignore this packet.
- */
- int cnt = 0;
- s32 tmp = len;
-
- while (1) {
- desc = ops->idx2desc(ring, *slot, &meta);
- /* recycle the descriptor buffer. */
- sync_descbuffer_for_device(ring, meta->dmaaddr,
- ring->rx_buffersize);
- *slot = next_slot(ring, *slot);
- cnt++;
- tmp -= ring->rx_buffersize;
- if (tmp <= 0)
- break;
- }
- b43err(ring->dev->wl, "DMA RX buffer too small "
- "(len: %u, buffer: %u, nr-dropped: %d)\n",
- len, ring->rx_buffersize, cnt);
- goto drop;
- }
-
- dmaaddr = meta->dmaaddr;
- err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
- if (unlikely(err)) {
- b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n");
- sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize);
- goto drop;
- }
-
- unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
- skb_put(skb, len + ring->frameoffset);
- skb_pull(skb, ring->frameoffset);
-
- b43_rx(ring->dev, skb, rxhdr);
-drop:
- return;
-}
-
-void b43_dma_rx(struct b43_dmaring *ring)
-{
- const struct b43_dma_ops *ops = ring->ops;
- int slot, current_slot;
- int used_slots = 0;
-
- B43_WARN_ON(ring->tx);
- current_slot = ops->get_current_rxslot(ring);
- B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots));
-
- slot = ring->current_slot;
- for (; slot != current_slot; slot = next_slot(ring, slot)) {
- dma_rx(ring, &slot);
- update_max_used_slots(ring, ++used_slots);
- }
- ops->set_current_rxslot(ring, slot);
- ring->current_slot = slot;
-}
-
-static void b43_dma_tx_suspend_ring(struct b43_dmaring *ring)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&ring->lock, flags);
- B43_WARN_ON(!ring->tx);
- ring->ops->tx_suspend(ring);
- spin_unlock_irqrestore(&ring->lock, flags);
-}
-
-static void b43_dma_tx_resume_ring(struct b43_dmaring *ring)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&ring->lock, flags);
- B43_WARN_ON(!ring->tx);
- ring->ops->tx_resume(ring);
- spin_unlock_irqrestore(&ring->lock, flags);
-}
-
-void b43_dma_tx_suspend(struct b43_wldev *dev)
-{
- b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
- b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BK);
- b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BE);
- b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VI);
- b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VO);
- b43_dma_tx_suspend_ring(dev->dma.tx_ring_mcast);
-}
-
-void b43_dma_tx_resume(struct b43_wldev *dev)
-{
- b43_dma_tx_resume_ring(dev->dma.tx_ring_mcast);
- b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VO);
- b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VI);
- b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BE);
- b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BK);
- b43_power_saving_ctl_bits(dev, 0);
-}
-
-#ifdef CONFIG_B43_PIO
-static void direct_fifo_rx(struct b43_wldev *dev, enum b43_dmatype type,
- u16 mmio_base, bool enable)
-{
- u32 ctl;
-
- if (type == B43_DMA_64BIT) {
- ctl = b43_read32(dev, mmio_base + B43_DMA64_RXCTL);
- ctl &= ~B43_DMA64_RXDIRECTFIFO;
- if (enable)
- ctl |= B43_DMA64_RXDIRECTFIFO;
- b43_write32(dev, mmio_base + B43_DMA64_RXCTL, ctl);
- } else {
- ctl = b43_read32(dev, mmio_base + B43_DMA32_RXCTL);
- ctl &= ~B43_DMA32_RXDIRECTFIFO;
- if (enable)
- ctl |= B43_DMA32_RXDIRECTFIFO;
- b43_write32(dev, mmio_base + B43_DMA32_RXCTL, ctl);
- }
-}
-
-/* Enable/Disable Direct FIFO Receive Mode (PIO) on a RX engine.
- * This is called from PIO code, so DMA structures are not available. */
-void b43_dma_direct_fifo_rx(struct b43_wldev *dev,
- unsigned int engine_index, bool enable)
-{
- enum b43_dmatype type;
- u16 mmio_base;
-
- type = dma_mask_to_engine_type(supported_dma_mask(dev));
-
- mmio_base = b43_dmacontroller_base(type, engine_index);
- direct_fifo_rx(dev, type, mmio_base, enable);
-}
-#endif /* CONFIG_B43_PIO */
-#ifndef B43_DMA_H_
-#define B43_DMA_H_
-
-#include <linux/list.h>
-#include <linux/spinlock.h>
-#include <linux/workqueue.h>
-#include <linux/linkage.h>
-#include <asm/atomic.h>
-
-#include "b43.h"
-
-/* DMA-Interrupt reasons. */
-#define B43_DMAIRQ_FATALMASK ((1 << 10) | (1 << 11) | (1 << 12) \
- | (1 << 14) | (1 << 15))
-#define B43_DMAIRQ_NONFATALMASK (1 << 13)
-#define B43_DMAIRQ_RX_DONE (1 << 16)
-
-/*** 32-bit DMA Engine. ***/
-
-/* 32-bit DMA controller registers. */
-#define B43_DMA32_TXCTL 0x00
-#define B43_DMA32_TXENABLE 0x00000001
-#define B43_DMA32_TXSUSPEND 0x00000002
-#define B43_DMA32_TXLOOPBACK 0x00000004
-#define B43_DMA32_TXFLUSH 0x00000010
-#define B43_DMA32_TXADDREXT_MASK 0x00030000
-#define B43_DMA32_TXADDREXT_SHIFT 16
-#define B43_DMA32_TXRING 0x04
-#define B43_DMA32_TXINDEX 0x08
-#define B43_DMA32_TXSTATUS 0x0C
-#define B43_DMA32_TXDPTR 0x00000FFF
-#define B43_DMA32_TXSTATE 0x0000F000
-#define B43_DMA32_TXSTAT_DISABLED 0x00000000
-#define B43_DMA32_TXSTAT_ACTIVE 0x00001000
-#define B43_DMA32_TXSTAT_IDLEWAIT 0x00002000
-#define B43_DMA32_TXSTAT_STOPPED 0x00003000
-#define B43_DMA32_TXSTAT_SUSP 0x00004000
-#define B43_DMA32_TXERROR 0x000F0000
-#define B43_DMA32_TXERR_NOERR 0x00000000
-#define B43_DMA32_TXERR_PROT 0x00010000
-#define B43_DMA32_TXERR_UNDERRUN 0x00020000
-#define B43_DMA32_TXERR_BUFREAD 0x00030000
-#define B43_DMA32_TXERR_DESCREAD 0x00040000
-#define B43_DMA32_TXACTIVE 0xFFF00000
-#define B43_DMA32_RXCTL 0x10
-#define B43_DMA32_RXENABLE 0x00000001
-#define B43_DMA32_RXFROFF_MASK 0x000000FE
-#define B43_DMA32_RXFROFF_SHIFT 1
-#define B43_DMA32_RXDIRECTFIFO 0x00000100
-#define B43_DMA32_RXADDREXT_MASK 0x00030000
-#define B43_DMA32_RXADDREXT_SHIFT 16
-#define B43_DMA32_RXRING 0x14
-#define B43_DMA32_RXINDEX 0x18
-#define B43_DMA32_RXSTATUS 0x1C
-#define B43_DMA32_RXDPTR 0x00000FFF
-#define B43_DMA32_RXSTATE 0x0000F000
-#define B43_DMA32_RXSTAT_DISABLED 0x00000000
-#define B43_DMA32_RXSTAT_ACTIVE 0x00001000
-#define B43_DMA32_RXSTAT_IDLEWAIT 0x00002000
-#define B43_DMA32_RXSTAT_STOPPED 0x00003000
-#define B43_DMA32_RXERROR 0x000F0000
-#define B43_DMA32_RXERR_NOERR 0x00000000
-#define B43_DMA32_RXERR_PROT 0x00010000
-#define B43_DMA32_RXERR_OVERFLOW 0x00020000
-#define B43_DMA32_RXERR_BUFWRITE 0x00030000
-#define B43_DMA32_RXERR_DESCREAD 0x00040000
-#define B43_DMA32_RXACTIVE 0xFFF00000
-
-/* 32-bit DMA descriptor. */
-struct b43_dmadesc32 {
- __le32 control;
- __le32 address;
-} __attribute__ ((__packed__));
-#define B43_DMA32_DCTL_BYTECNT 0x00001FFF
-#define B43_DMA32_DCTL_ADDREXT_MASK 0x00030000
-#define B43_DMA32_DCTL_ADDREXT_SHIFT 16
-#define B43_DMA32_DCTL_DTABLEEND 0x10000000
-#define B43_DMA32_DCTL_IRQ 0x20000000
-#define B43_DMA32_DCTL_FRAMEEND 0x40000000
-#define B43_DMA32_DCTL_FRAMESTART 0x80000000
-
-/*** 64-bit DMA Engine. ***/
-
-/* 64-bit DMA controller registers. */
-#define B43_DMA64_TXCTL 0x00
-#define B43_DMA64_TXENABLE 0x00000001
-#define B43_DMA64_TXSUSPEND 0x00000002
-#define B43_DMA64_TXLOOPBACK 0x00000004
-#define B43_DMA64_TXFLUSH 0x00000010
-#define B43_DMA64_TXADDREXT_MASK 0x00030000
-#define B43_DMA64_TXADDREXT_SHIFT 16
-#define B43_DMA64_TXINDEX 0x04
-#define B43_DMA64_TXRINGLO 0x08
-#define B43_DMA64_TXRINGHI 0x0C
-#define B43_DMA64_TXSTATUS 0x10
-#define B43_DMA64_TXSTATDPTR 0x00001FFF
-#define B43_DMA64_TXSTAT 0xF0000000
-#define B43_DMA64_TXSTAT_DISABLED 0x00000000
-#define B43_DMA64_TXSTAT_ACTIVE 0x10000000
-#define B43_DMA64_TXSTAT_IDLEWAIT 0x20000000
-#define B43_DMA64_TXSTAT_STOPPED 0x30000000
-#define B43_DMA64_TXSTAT_SUSP 0x40000000
-#define B43_DMA64_TXERROR 0x14
-#define B43_DMA64_TXERRDPTR 0x0001FFFF
-#define B43_DMA64_TXERR 0xF0000000
-#define B43_DMA64_TXERR_NOERR 0x00000000
-#define B43_DMA64_TXERR_PROT 0x10000000
-#define B43_DMA64_TXERR_UNDERRUN 0x20000000
-#define B43_DMA64_TXERR_TRANSFER 0x30000000
-#define B43_DMA64_TXERR_DESCREAD 0x40000000
-#define B43_DMA64_TXERR_CORE 0x50000000
-#define B43_DMA64_RXCTL 0x20
-#define B43_DMA64_RXENABLE 0x00000001
-#define B43_DMA64_RXFROFF_MASK 0x000000FE
-#define B43_DMA64_RXFROFF_SHIFT 1
-#define B43_DMA64_RXDIRECTFIFO 0x00000100
-#define B43_DMA64_RXADDREXT_MASK 0x00030000
-#define B43_DMA64_RXADDREXT_SHIFT 16
-#define B43_DMA64_RXINDEX 0x24
-#define B43_DMA64_RXRINGLO 0x28
-#define B43_DMA64_RXRINGHI 0x2C
-#define B43_DMA64_RXSTATUS 0x30
-#define B43_DMA64_RXSTATDPTR 0x00001FFF
-#define B43_DMA64_RXSTAT 0xF0000000
-#define B43_DMA64_RXSTAT_DISABLED 0x00000000
-#define B43_DMA64_RXSTAT_ACTIVE 0x10000000
-#define B43_DMA64_RXSTAT_IDLEWAIT 0x20000000
-#define B43_DMA64_RXSTAT_STOPPED 0x30000000
-#define B43_DMA64_RXSTAT_SUSP 0x40000000
-#define B43_DMA64_RXERROR 0x34
-#define B43_DMA64_RXERRDPTR 0x0001FFFF
-#define B43_DMA64_RXERR 0xF0000000
-#define B43_DMA64_RXERR_NOERR 0x00000000
-#define B43_DMA64_RXERR_PROT 0x10000000
-#define B43_DMA64_RXERR_UNDERRUN 0x20000000
-#define B43_DMA64_RXERR_TRANSFER 0x30000000
-#define B43_DMA64_RXERR_DESCREAD 0x40000000
-#define B43_DMA64_RXERR_CORE 0x50000000
-
-/* 64-bit DMA descriptor. */
-struct b43_dmadesc64 {
- __le32 control0;
- __le32 control1;
- __le32 address_low;
- __le32 address_high;
-} __attribute__ ((__packed__));
-#define B43_DMA64_DCTL0_DTABLEEND 0x10000000
-#define B43_DMA64_DCTL0_IRQ 0x20000000
-#define B43_DMA64_DCTL0_FRAMEEND 0x40000000
-#define B43_DMA64_DCTL0_FRAMESTART 0x80000000
-#define B43_DMA64_DCTL1_BYTECNT 0x00001FFF
-#define B43_DMA64_DCTL1_ADDREXT_MASK 0x00030000
-#define B43_DMA64_DCTL1_ADDREXT_SHIFT 16
-
-struct b43_dmadesc_generic {
- union {
- struct b43_dmadesc32 dma32;
- struct b43_dmadesc64 dma64;
- } __attribute__ ((__packed__));
-} __attribute__ ((__packed__));
-
-/* Misc DMA constants */
-#define B43_DMA_RINGMEMSIZE PAGE_SIZE
-#define B43_DMA0_RX_FRAMEOFFSET 30
-#define B43_DMA3_RX_FRAMEOFFSET 0
-
-/* DMA engine tuning knobs */
-#define B43_TXRING_SLOTS 128
-#define B43_RXRING_SLOTS 64
-#define B43_DMA0_RX_BUFFERSIZE (2304 + 100)
-#define B43_DMA3_RX_BUFFERSIZE 16
-
-struct sk_buff;
-struct b43_private;
-struct b43_txstatus;
-
-struct b43_dmadesc_meta {
- /* The kernel DMA-able buffer. */
- struct sk_buff *skb;
- /* DMA base bus-address of the descriptor buffer. */
- dma_addr_t dmaaddr;
- /* ieee80211 TX status. Only used once per 802.11 frag. */
- bool is_last_fragment;
-};
-
-struct b43_dmaring;
-
-/* Lowlevel DMA operations that differ between 32bit and 64bit DMA. */
-struct b43_dma_ops {
- struct b43_dmadesc_generic *(*idx2desc) (struct b43_dmaring * ring,
- int slot,
- struct b43_dmadesc_meta **
- meta);
- void (*fill_descriptor) (struct b43_dmaring * ring,
- struct b43_dmadesc_generic * desc,
- dma_addr_t dmaaddr, u16 bufsize, int start,
- int end, int irq);
- void (*poke_tx) (struct b43_dmaring * ring, int slot);
- void (*tx_suspend) (struct b43_dmaring * ring);
- void (*tx_resume) (struct b43_dmaring * ring);
- int (*get_current_rxslot) (struct b43_dmaring * ring);
- void (*set_current_rxslot) (struct b43_dmaring * ring, int slot);
-};
-
-enum b43_dmatype {
- B43_DMA_30BIT = 30,
- B43_DMA_32BIT = 32,
- B43_DMA_64BIT = 64,
-};
-
-struct b43_dmaring {
- /* Lowlevel DMA ops. */
- const struct b43_dma_ops *ops;
- /* Kernel virtual base address of the ring memory. */
- void *descbase;
- /* Meta data about all descriptors. */
- struct b43_dmadesc_meta *meta;
- /* Cache of TX headers for each slot.
- * This is to avoid an allocation on each TX.
- * This is NULL for an RX ring.
- */
- u8 *txhdr_cache;
- /* (Unadjusted) DMA base bus-address of the ring memory. */
- dma_addr_t dmabase;
- /* Number of descriptor slots in the ring. */
- int nr_slots;
- /* Number of used descriptor slots. */
- int used_slots;
- /* Currently used slot in the ring. */
- int current_slot;
- /* Total number of packets sent. Statistics only. */
- unsigned int nr_tx_packets;
- /* Frameoffset in octets. */
- u32 frameoffset;
- /* Descriptor buffer size. */
- u16 rx_buffersize;
- /* The MMIO base register of the DMA controller. */
- u16 mmio_base;
- /* DMA controller index number (0-5). */
- int index;
- /* Boolean. Is this a TX ring? */
- bool tx;
- /* The type of DMA engine used. */
- enum b43_dmatype type;
- /* Boolean. Is this ring stopped at ieee80211 level? */
- bool stopped;
- /* The QOS priority assigned to this ring. Only used for TX rings.
- * This is the mac80211 "queue" value. */
- u8 queue_prio;
- /* Lock, only used for TX. */
- spinlock_t lock;
- struct b43_wldev *dev;
-#ifdef CONFIG_B43_DEBUG
- /* Maximum number of used slots. */
- int max_used_slots;
- /* Last time we injected a ring overflow. */
- unsigned long last_injected_overflow;
- /* Statistics: Number of successfully transmitted packets */
- u64 nr_succeed_tx_packets;
- /* Statistics: Number of failed TX packets */
- u64 nr_failed_tx_packets;
- /* Statistics: Total number of TX plus all retries. */
- u64 nr_total_packet_tries;
-#endif /* CONFIG_B43_DEBUG */
-};
-
-static inline u32 b43_dma_read(struct b43_dmaring *ring, u16 offset)
-{
- return b43_read32(ring->dev, ring->mmio_base + offset);
-}
-
-static inline void b43_dma_write(struct b43_dmaring *ring, u16 offset, u32 value)
-{
- b43_write32(ring->dev, ring->mmio_base + offset, value);
-}
-
-int b43_dma_init(struct b43_wldev *dev);
-void b43_dma_free(struct b43_wldev *dev);
-
-void b43_dma_tx_suspend(struct b43_wldev *dev);
-void b43_dma_tx_resume(struct b43_wldev *dev);
-
-void b43_dma_get_tx_stats(struct b43_wldev *dev,
- struct ieee80211_tx_queue_stats *stats);
-
-int b43_dma_tx(struct b43_wldev *dev,
- struct sk_buff *skb);
-void b43_dma_handle_txstatus(struct b43_wldev *dev,
- const struct b43_txstatus *status);
-
-void b43_dma_rx(struct b43_dmaring *ring);
-
-void b43_dma_direct_fifo_rx(struct b43_wldev *dev,
- unsigned int engine_index, bool enable);
-
-#endif /* B43_DMA_H_ */
-/*
-
- Broadcom B43 wireless driver
- LED control
-
- Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
- Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
- Copyright (c) 2005-2007 Michael Buesch <mb@bu3sch.de>
- Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
- Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; see the file COPYING. If not, write to
- the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
- Boston, MA 02110-1301, USA.
-
-*/
-
-#include "b43.h"
-#include "leds.h"
-
-
-static void b43_led_turn_on(struct b43_wldev *dev, u8 led_index,
- bool activelow)
-{
- struct b43_wl *wl = dev->wl;
- unsigned long flags;
- u16 ctl;
-
- spin_lock_irqsave(&wl->leds_lock, flags);
- ctl = b43_read16(dev, B43_MMIO_GPIO_CONTROL);
- if (activelow)
- ctl &= ~(1 << led_index);
- else
- ctl |= (1 << led_index);
- b43_write16(dev, B43_MMIO_GPIO_CONTROL, ctl);
- spin_unlock_irqrestore(&wl->leds_lock, flags);
-}
-
-static void b43_led_turn_off(struct b43_wldev *dev, u8 led_index,
- bool activelow)
-{
- struct b43_wl *wl = dev->wl;
- unsigned long flags;
- u16 ctl;
-
- spin_lock_irqsave(&wl->leds_lock, flags);
- ctl = b43_read16(dev, B43_MMIO_GPIO_CONTROL);
- if (activelow)
- ctl |= (1 << led_index);
- else
- ctl &= ~(1 << led_index);
- b43_write16(dev, B43_MMIO_GPIO_CONTROL, ctl);
- spin_unlock_irqrestore(&wl->leds_lock, flags);
-}
-
-/* Callback from the LED subsystem. */
-static void b43_led_brightness_set(struct led_classdev *led_dev,
- enum led_brightness brightness)
-{
- struct b43_led *led = container_of(led_dev, struct b43_led, led_dev);
- struct b43_wldev *dev = led->dev;
- bool radio_enabled;
-
- /* Checking the radio-enabled status here is slightly racy,
- * but we want to avoid the locking overhead and we don't care
- * whether the LED has the wrong state for a second. */
- radio_enabled = (dev->phy.radio_on && dev->radio_hw_enable);
-
- if (brightness == LED_OFF || !radio_enabled)
- b43_led_turn_off(dev, led->index, led->activelow);
- else
- b43_led_turn_on(dev, led->index, led->activelow);
-}
-
-static int b43_register_led(struct b43_wldev *dev, struct b43_led *led,
- const char *name, char *default_trigger,
- u8 led_index, bool activelow)
-{
- int err;
-
- b43_led_turn_off(dev, led_index, activelow);
- if (led->dev)
- return -EEXIST;
- if (!default_trigger)
- return -EINVAL;
- led->dev = dev;
- led->index = led_index;
- led->activelow = activelow;
- strncpy(led->name, name, sizeof(led->name));
-
- led->led_dev.name = led->name;
- led->led_dev.default_trigger = default_trigger;
- led->led_dev.brightness_set = b43_led_brightness_set;
-
- err = led_classdev_register(dev->dev->dev, &led->led_dev);
- if (err) {
- b43warn(dev->wl, "LEDs: Failed to register %s\n", name);
- led->dev = NULL;
- return err;
- }
- return 0;
-}
-
-static void b43_unregister_led(struct b43_led *led)
-{
- if (!led->dev)
- return;
- led_classdev_unregister(&led->led_dev);
- b43_led_turn_off(led->dev, led->index, led->activelow);
- led->dev = NULL;
-}
-
-static void b43_map_led(struct b43_wldev *dev,
- u8 led_index,
- enum b43_led_behaviour behaviour,
- bool activelow)
-{
- struct ieee80211_hw *hw = dev->wl->hw;
- char name[B43_LED_MAX_NAME_LEN + 1];
-
- /* Map the b43 specific LED behaviour value to the
- * generic LED triggers. */
- switch (behaviour) {
- case B43_LED_INACTIVE:
- break;
- case B43_LED_OFF:
- b43_led_turn_off(dev, led_index, activelow);
- break;
- case B43_LED_ON:
- b43_led_turn_on(dev, led_index, activelow);
- break;
- case B43_LED_ACTIVITY:
- case B43_LED_TRANSFER:
- case B43_LED_APTRANSFER:
- snprintf(name, sizeof(name),
- "b43-%s::tx", wiphy_name(hw->wiphy));
- b43_register_led(dev, &dev->led_tx, name,
- ieee80211_get_tx_led_name(hw),
- led_index, activelow);
- snprintf(name, sizeof(name),
- "b43-%s::rx", wiphy_name(hw->wiphy));
- b43_register_led(dev, &dev->led_rx, name,
- ieee80211_get_rx_led_name(hw),
- led_index, activelow);
- break;
- case B43_LED_RADIO_ALL:
- case B43_LED_RADIO_A:
- case B43_LED_RADIO_B:
- case B43_LED_MODE_BG:
- snprintf(name, sizeof(name),
- "b43-%s::radio", wiphy_name(hw->wiphy));
- b43_register_led(dev, &dev->led_radio, name,
- b43_rfkill_led_name(dev),
- led_index, activelow);
- /* Sync the RF-kill LED state with the switch state. */
- if (dev->radio_hw_enable)
- b43_led_turn_on(dev, led_index, activelow);
- break;
- case B43_LED_WEIRD:
- case B43_LED_ASSOC:
- snprintf(name, sizeof(name),
- "b43-%s::assoc", wiphy_name(hw->wiphy));
- b43_register_led(dev, &dev->led_assoc, name,
- ieee80211_get_assoc_led_name(hw),
- led_index, activelow);
- break;
- default:
- b43warn(dev->wl, "LEDs: Unknown behaviour 0x%02X\n",
- behaviour);
- break;
- }
-}
-
-void b43_leds_init(struct b43_wldev *dev)
-{
- struct ssb_bus *bus = dev->dev->bus;
- u8 sprom[4];
- int i;
- enum b43_led_behaviour behaviour;
- bool activelow;
-
- sprom[0] = bus->sprom.gpio0;
- sprom[1] = bus->sprom.gpio1;
- sprom[2] = bus->sprom.gpio2;
- sprom[3] = bus->sprom.gpio3;
-
- for (i = 0; i < 4; i++) {
- if (sprom[i] == 0xFF) {
- /* There is no LED information in the SPROM
- * for this LED. Hardcode it here. */
- activelow = 0;
- switch (i) {
- case 0:
- behaviour = B43_LED_ACTIVITY;
- activelow = 1;
- if (bus->boardinfo.vendor == PCI_VENDOR_ID_COMPAQ)
- behaviour = B43_LED_RADIO_ALL;
- break;
- case 1:
- behaviour = B43_LED_RADIO_B;
- if (bus->boardinfo.vendor == PCI_VENDOR_ID_ASUSTEK)
- behaviour = B43_LED_ASSOC;
- break;
- case 2:
- behaviour = B43_LED_RADIO_A;
- break;
- case 3:
- behaviour = B43_LED_OFF;
- break;
- default:
- B43_WARN_ON(1);
- return;
- }
- } else {
- behaviour = sprom[i] & B43_LED_BEHAVIOUR;
- activelow = !!(sprom[i] & B43_LED_ACTIVELOW);
- }
- b43_map_led(dev, i, behaviour, activelow);
- }
-}
-
-void b43_leds_exit(struct b43_wldev *dev)
-{
- b43_unregister_led(&dev->led_tx);
- b43_unregister_led(&dev->led_rx);
- b43_unregister_led(&dev->led_assoc);
- b43_unregister_led(&dev->led_radio);
-}
-#ifndef B43_LEDS_H_
-#define B43_LEDS_H_
-
-struct b43_wldev;
-
-#ifdef CONFIG_B43_LEDS
-
-#include <linux/types.h>
-#include <linux/leds.h>
-
-
-#define B43_LED_MAX_NAME_LEN 31
-
-struct b43_led {
- struct b43_wldev *dev;
- /* The LED class device */
- struct led_classdev led_dev;
- /* The index number of the LED. */
- u8 index;
- /* If activelow is true, the LED is ON if the
- * bit is switched off. */
- bool activelow;
- /* The unique name string for this LED device. */
- char name[B43_LED_MAX_NAME_LEN + 1];
-};
-
-#define B43_LED_BEHAVIOUR 0x7F
-#define B43_LED_ACTIVELOW 0x80
-/* LED behaviour values */
-enum b43_led_behaviour {
- B43_LED_OFF,
- B43_LED_ON,
- B43_LED_ACTIVITY,
- B43_LED_RADIO_ALL,
- B43_LED_RADIO_A,
- B43_LED_RADIO_B,
- B43_LED_MODE_BG,
- B43_LED_TRANSFER,
- B43_LED_APTRANSFER,
- B43_LED_WEIRD, //FIXME
- B43_LED_ASSOC,
- B43_LED_INACTIVE,
-};
-
-void b43_leds_init(struct b43_wldev *dev);
-void b43_leds_exit(struct b43_wldev *dev);
-
-
-#else /* CONFIG_B43_LEDS */
-/* LED support disabled */
-
-struct b43_led {
- /* empty */
-};
-
-static inline void b43_leds_init(struct b43_wldev *dev)
-{
-}
-static inline void b43_leds_exit(struct b43_wldev *dev)
-{
-}
-#endif /* CONFIG_B43_LEDS */
-
-#endif /* B43_LEDS_H_ */
-/*
-
- Broadcom B43 wireless driver
-
- G PHY LO (LocalOscillator) Measuring and Control routines
-
- Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
- Copyright (c) 2005, 2006 Stefano Brivio <stefano.brivio@polimi.it>
- Copyright (c) 2005-2007 Michael Buesch <mb@bu3sch.de>
- Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
- Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; see the file COPYING. If not, write to
- the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
- Boston, MA 02110-1301, USA.
-
-*/
-
-#include "b43.h"
-#include "lo.h"
-#include "phy.h"
-#include "main.h"
-
-#include <linux/delay.h>
-#include <linux/sched.h>
-
-
-static struct b43_lo_calib * b43_find_lo_calib(struct b43_txpower_lo_control *lo,
- const struct b43_bbatt *bbatt,
- const struct b43_rfatt *rfatt)
-{
- struct b43_lo_calib *c;
-
- list_for_each_entry(c, &lo->calib_list, list) {
- if (!b43_compare_bbatt(&c->bbatt, bbatt))
- continue;
- if (!b43_compare_rfatt(&c->rfatt, rfatt))
- continue;
- return c;
- }
-
- return NULL;
-}
-
-/* Write the LocalOscillator Control (adjust) value-pair. */
-static void b43_lo_write(struct b43_wldev *dev, struct b43_loctl *control)
-{
- struct b43_phy *phy = &dev->phy;
- u16 value;
-
- if (B43_DEBUG) {
- if (unlikely(abs(control->i) > 16 || abs(control->q) > 16)) {
- b43dbg(dev->wl, "Invalid LO control pair "
- "(I: %d, Q: %d)\n", control->i, control->q);
- dump_stack();
- return;
- }
- }
- B43_WARN_ON(phy->type != B43_PHYTYPE_G);
-
- value = (u8) (control->q);
- value |= ((u8) (control->i)) << 8;
- b43_phy_write(dev, B43_PHY_LO_CTL, value);
-}
-
-static u16 lo_measure_feedthrough(struct b43_wldev *dev,
- u16 lna, u16 pga, u16 trsw_rx)
-{
- struct b43_phy *phy = &dev->phy;
- u16 rfover;
- u16 feedthrough;
-
- if (phy->gmode) {
- lna <<= B43_PHY_RFOVERVAL_LNA_SHIFT;
- pga <<= B43_PHY_RFOVERVAL_PGA_SHIFT;
-
- B43_WARN_ON(lna & ~B43_PHY_RFOVERVAL_LNA);
- B43_WARN_ON(pga & ~B43_PHY_RFOVERVAL_PGA);
-/*FIXME This assertion fails B43_WARN_ON(trsw_rx & ~(B43_PHY_RFOVERVAL_TRSWRX |
- B43_PHY_RFOVERVAL_BW));
-*/
- trsw_rx &= (B43_PHY_RFOVERVAL_TRSWRX | B43_PHY_RFOVERVAL_BW);
-
- /* Construct the RF Override Value */
- rfover = B43_PHY_RFOVERVAL_UNK;
- rfover |= pga;
- rfover |= lna;
- rfover |= trsw_rx;
- if ((dev->dev->bus->sprom.boardflags_lo & B43_BFL_EXTLNA)
- && phy->rev > 6)
- rfover |= B43_PHY_RFOVERVAL_EXTLNA;
-
- b43_phy_write(dev, B43_PHY_PGACTL, 0xE300);
- b43_phy_write(dev, B43_PHY_RFOVERVAL, rfover);
- udelay(10);
- rfover |= B43_PHY_RFOVERVAL_BW_LBW;
- b43_phy_write(dev, B43_PHY_RFOVERVAL, rfover);
- udelay(10);
- rfover |= B43_PHY_RFOVERVAL_BW_LPF;
- b43_phy_write(dev, B43_PHY_RFOVERVAL, rfover);
- udelay(10);
- b43_phy_write(dev, B43_PHY_PGACTL, 0xF300);
- } else {
- pga |= B43_PHY_PGACTL_UNKNOWN;
- b43_phy_write(dev, B43_PHY_PGACTL, pga);
- udelay(10);
- pga |= B43_PHY_PGACTL_LOWBANDW;
- b43_phy_write(dev, B43_PHY_PGACTL, pga);
- udelay(10);
- pga |= B43_PHY_PGACTL_LPF;
- b43_phy_write(dev, B43_PHY_PGACTL, pga);
- }
- udelay(21);
- feedthrough = b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
-
- /* This is a good place to check if we need to relax a bit,
- * as this is the main function called regularly
- * in the LO calibration. */
- cond_resched();
-
- return feedthrough;
-}
-
-/* TXCTL Register and Value Table.
- * Returns the "TXCTL Register".
- * "value" is the "TXCTL Value".
- * "pad_mix_gain" is the PAD Mixer Gain.
- */
-static u16 lo_txctl_register_table(struct b43_wldev *dev,
- u16 * value, u16 * pad_mix_gain)
-{
- struct b43_phy *phy = &dev->phy;
- u16 reg, v, padmix;
-
- if (phy->type == B43_PHYTYPE_B) {
- v = 0x30;
- if (phy->radio_rev <= 5) {
- reg = 0x43;
- padmix = 0;
- } else {
- reg = 0x52;
- padmix = 5;
- }
- } else {
- if (phy->rev >= 2 && phy->radio_rev == 8) {
- reg = 0x43;
- v = 0x10;
- padmix = 2;
- } else {
- reg = 0x52;
- v = 0x30;
- padmix = 5;
- }
- }
- if (value)
- *value = v;
- if (pad_mix_gain)
- *pad_mix_gain = padmix;
-
- return reg;
-}
-
-static void lo_measure_txctl_values(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- struct b43_txpower_lo_control *lo = phy->lo_control;
- u16 reg, mask;
- u16 trsw_rx, pga;
- u16 radio_pctl_reg;
-
- static const u8 tx_bias_values[] = {
- 0x09, 0x08, 0x0A, 0x01, 0x00,
- 0x02, 0x05, 0x04, 0x06,
- };
- static const u8 tx_magn_values[] = {
- 0x70, 0x40,
- };
-
- if (!has_loopback_gain(phy)) {
- radio_pctl_reg = 6;
- trsw_rx = 2;
- pga = 0;
- } else {
- int lb_gain; /* Loopback gain (in dB) */
-
- trsw_rx = 0;
- lb_gain = phy->max_lb_gain / 2;
- if (lb_gain > 10) {
- radio_pctl_reg = 0;
- pga = abs(10 - lb_gain) / 6;
- pga = clamp_val(pga, 0, 15);
- } else {
- int cmp_val;
- int tmp;
-
- pga = 0;
- cmp_val = 0x24;
- if ((phy->rev >= 2) &&
- (phy->radio_ver == 0x2050) && (phy->radio_rev == 8))
- cmp_val = 0x3C;
- tmp = lb_gain;
- if ((10 - lb_gain) < cmp_val)
- tmp = (10 - lb_gain);
- if (tmp < 0)
- tmp += 6;
- else
- tmp += 3;
- cmp_val /= 4;
- tmp /= 4;
- if (tmp >= cmp_val)
- radio_pctl_reg = cmp_val;
- else
- radio_pctl_reg = tmp;
- }
- }
- b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
- & 0xFFF0) | radio_pctl_reg);
- b43_phy_set_baseband_attenuation(dev, 2);
-
- reg = lo_txctl_register_table(dev, &mask, NULL);
- mask = ~mask;
- b43_radio_write16(dev, reg, b43_radio_read16(dev, reg)
- & mask);
-
- if (has_tx_magnification(phy)) {
- int i, j;
- int feedthrough;
- int min_feedth = 0xFFFF;
- u8 tx_magn, tx_bias;
-
- for (i = 0; i < ARRAY_SIZE(tx_magn_values); i++) {
- tx_magn = tx_magn_values[i];
- b43_radio_write16(dev, 0x52,
- (b43_radio_read16(dev, 0x52)
- & 0xFF0F) | tx_magn);
- for (j = 0; j < ARRAY_SIZE(tx_bias_values); j++) {
- tx_bias = tx_bias_values[j];
- b43_radio_write16(dev, 0x52,
- (b43_radio_read16(dev, 0x52)
- & 0xFFF0) | tx_bias);
- feedthrough =
- lo_measure_feedthrough(dev, 0, pga,
- trsw_rx);
- if (feedthrough < min_feedth) {
- lo->tx_bias = tx_bias;
- lo->tx_magn = tx_magn;
- min_feedth = feedthrough;
- }
- if (lo->tx_bias == 0)
- break;
- }
- b43_radio_write16(dev, 0x52,
- (b43_radio_read16(dev, 0x52)
- & 0xFF00) | lo->tx_bias | lo->
- tx_magn);
- }
- } else {
- lo->tx_magn = 0;
- lo->tx_bias = 0;
- b43_radio_write16(dev, 0x52, b43_radio_read16(dev, 0x52)
- & 0xFFF0); /* TX bias == 0 */
- }
- lo->txctl_measured_time = jiffies;
-}
-
-static void lo_read_power_vector(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- struct b43_txpower_lo_control *lo = phy->lo_control;
- int i;
- u64 tmp;
- u64 power_vector = 0;
-
- for (i = 0; i < 8; i += 2) {
- tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x310 + i);
- power_vector |= (tmp << (i * 8));
- /* Clear the vector on the device. */
- b43_shm_write16(dev, B43_SHM_SHARED, 0x310 + i, 0);
- }
- if (power_vector)
- lo->power_vector = power_vector;
- lo->pwr_vec_read_time = jiffies;
-}
-
-/* 802.11/LO/GPHY/MeasuringGains */
-static void lo_measure_gain_values(struct b43_wldev *dev,
- s16 max_rx_gain, int use_trsw_rx)
-{
- struct b43_phy *phy = &dev->phy;
- u16 tmp;
-
- if (max_rx_gain < 0)
- max_rx_gain = 0;
-
- if (has_loopback_gain(phy)) {
- int trsw_rx = 0;
- int trsw_rx_gain;
-
- if (use_trsw_rx) {
- trsw_rx_gain = phy->trsw_rx_gain / 2;
- if (max_rx_gain >= trsw_rx_gain) {
- trsw_rx_gain = max_rx_gain - trsw_rx_gain;
- trsw_rx = 0x20;
- }
- } else
- trsw_rx_gain = max_rx_gain;
- if (trsw_rx_gain < 9) {
- phy->lna_lod_gain = 0;
- } else {
- phy->lna_lod_gain = 1;
- trsw_rx_gain -= 8;
- }
- trsw_rx_gain = clamp_val(trsw_rx_gain, 0, 0x2D);
- phy->pga_gain = trsw_rx_gain / 3;
- if (phy->pga_gain >= 5) {
- phy->pga_gain -= 5;
- phy->lna_gain = 2;
- } else
- phy->lna_gain = 0;
- } else {
- phy->lna_gain = 0;
- phy->trsw_rx_gain = 0x20;
- if (max_rx_gain >= 0x14) {
- phy->lna_lod_gain = 1;
- phy->pga_gain = 2;
- } else if (max_rx_gain >= 0x12) {
- phy->lna_lod_gain = 1;
- phy->pga_gain = 1;
- } else if (max_rx_gain >= 0xF) {
- phy->lna_lod_gain = 1;
- phy->pga_gain = 0;
- } else {
- phy->lna_lod_gain = 0;
- phy->pga_gain = 0;
- }
- }
-
- tmp = b43_radio_read16(dev, 0x7A);
- if (phy->lna_lod_gain == 0)
- tmp &= ~0x0008;
- else
- tmp |= 0x0008;
- b43_radio_write16(dev, 0x7A, tmp);
-}
-
-struct lo_g_saved_values {
- u8 old_channel;
-
- /* Core registers */
- u16 reg_3F4;
- u16 reg_3E2;
-
- /* PHY registers */
- u16 phy_lo_mask;
- u16 phy_extg_01;
- u16 phy_dacctl_hwpctl;
- u16 phy_dacctl;
- u16 phy_cck_14;
- u16 phy_hpwr_tssictl;
- u16 phy_analogover;
- u16 phy_analogoverval;
- u16 phy_rfover;
- u16 phy_rfoverval;
- u16 phy_classctl;
- u16 phy_cck_3E;
- u16 phy_crs0;
- u16 phy_pgactl;
- u16 phy_cck_2A;
- u16 phy_syncctl;
- u16 phy_cck_30;
- u16 phy_cck_06;
-
- /* Radio registers */
- u16 radio_43;
- u16 radio_7A;
- u16 radio_52;
-};
-
-static void lo_measure_setup(struct b43_wldev *dev,
- struct lo_g_saved_values *sav)
-{
- struct ssb_sprom *sprom = &dev->dev->bus->sprom;
- struct b43_phy *phy = &dev->phy;
- struct b43_txpower_lo_control *lo = phy->lo_control;
- u16 tmp;
-
- if (b43_has_hardware_pctl(phy)) {
- sav->phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK);
- sav->phy_extg_01 = b43_phy_read(dev, B43_PHY_EXTG(0x01));
- sav->phy_dacctl_hwpctl = b43_phy_read(dev, B43_PHY_DACCTL);
- sav->phy_cck_14 = b43_phy_read(dev, B43_PHY_CCK(0x14));
- sav->phy_hpwr_tssictl = b43_phy_read(dev, B43_PHY_HPWR_TSSICTL);
-
- b43_phy_write(dev, B43_PHY_HPWR_TSSICTL,
- b43_phy_read(dev, B43_PHY_HPWR_TSSICTL)
- | 0x100);
- b43_phy_write(dev, B43_PHY_EXTG(0x01),
- b43_phy_read(dev, B43_PHY_EXTG(0x01))
- | 0x40);
- b43_phy_write(dev, B43_PHY_DACCTL,
- b43_phy_read(dev, B43_PHY_DACCTL)
- | 0x40);
- b43_phy_write(dev, B43_PHY_CCK(0x14),
- b43_phy_read(dev, B43_PHY_CCK(0x14))
- | 0x200);
- }
- if (phy->type == B43_PHYTYPE_B &&
- phy->radio_ver == 0x2050 && phy->radio_rev < 6) {
- b43_phy_write(dev, B43_PHY_CCK(0x16), 0x410);
- b43_phy_write(dev, B43_PHY_CCK(0x17), 0x820);
- }
- if (phy->rev >= 2) {
- sav->phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER);
- sav->phy_analogoverval =
- b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
- sav->phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER);
- sav->phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
- sav->phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
- sav->phy_cck_3E = b43_phy_read(dev, B43_PHY_CCK(0x3E));
- sav->phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
-
- b43_phy_write(dev, B43_PHY_CLASSCTL,
- b43_phy_read(dev, B43_PHY_CLASSCTL)
- & 0xFFFC);
- b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
- & 0x7FFF);
- b43_phy_write(dev, B43_PHY_ANALOGOVER,
- b43_phy_read(dev, B43_PHY_ANALOGOVER)
- | 0x0003);
- b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
- b43_phy_read(dev, B43_PHY_ANALOGOVERVAL)
- & 0xFFFC);
- if (phy->type == B43_PHYTYPE_G) {
- if ((phy->rev >= 7) &&
- (sprom->boardflags_lo & B43_BFL_EXTLNA)) {
- b43_phy_write(dev, B43_PHY_RFOVER, 0x933);
- } else {
- b43_phy_write(dev, B43_PHY_RFOVER, 0x133);
- }
- } else {
- b43_phy_write(dev, B43_PHY_RFOVER, 0);
- }
- b43_phy_write(dev, B43_PHY_CCK(0x3E), 0);
- }
- sav->reg_3F4 = b43_read16(dev, 0x3F4);
- sav->reg_3E2 = b43_read16(dev, 0x3E2);
- sav->radio_43 = b43_radio_read16(dev, 0x43);
- sav->radio_7A = b43_radio_read16(dev, 0x7A);
- sav->phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL);
- sav->phy_cck_2A = b43_phy_read(dev, B43_PHY_CCK(0x2A));
- sav->phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL);
- sav->phy_dacctl = b43_phy_read(dev, B43_PHY_DACCTL);
-
- if (!has_tx_magnification(phy)) {
- sav->radio_52 = b43_radio_read16(dev, 0x52);
- sav->radio_52 &= 0x00F0;
- }
- if (phy->type == B43_PHYTYPE_B) {
- sav->phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30));
- sav->phy_cck_06 = b43_phy_read(dev, B43_PHY_CCK(0x06));
- b43_phy_write(dev, B43_PHY_CCK(0x30), 0x00FF);
- b43_phy_write(dev, B43_PHY_CCK(0x06), 0x3F3F);
- } else {
- b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2)
- | 0x8000);
- }
- b43_write16(dev, 0x3F4, b43_read16(dev, 0x3F4)
- & 0xF000);
-
- tmp =
- (phy->type == B43_PHYTYPE_G) ? B43_PHY_LO_MASK : B43_PHY_CCK(0x2E);
- b43_phy_write(dev, tmp, 0x007F);
-
- tmp = sav->phy_syncctl;
- b43_phy_write(dev, B43_PHY_SYNCCTL, tmp & 0xFF7F);
- tmp = sav->radio_7A;
- b43_radio_write16(dev, 0x007A, tmp & 0xFFF0);
-
- b43_phy_write(dev, B43_PHY_CCK(0x2A), 0x8A3);
- if (phy->type == B43_PHYTYPE_G ||
- (phy->type == B43_PHYTYPE_B &&
- phy->radio_ver == 0x2050 && phy->radio_rev >= 6)) {
- b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1003);
- } else
- b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x0802);
- if (phy->rev >= 2)
- b43_dummy_transmission(dev);
- b43_radio_selectchannel(dev, 6, 0);
- b43_radio_read16(dev, 0x51); /* dummy read */
- if (phy->type == B43_PHYTYPE_G)
- b43_phy_write(dev, B43_PHY_CCK(0x2F), 0);
-
- /* Re-measure the txctl values, if needed. */
- if (time_before(lo->txctl_measured_time,
- jiffies - B43_LO_TXCTL_EXPIRE))
- lo_measure_txctl_values(dev);
-
- if (phy->type == B43_PHYTYPE_G && phy->rev >= 3) {
- b43_phy_write(dev, B43_PHY_LO_MASK, 0xC078);
- } else {
- if (phy->type == B43_PHYTYPE_B)
- b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8078);
- else
- b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078);
- }
-}
-
-static void lo_measure_restore(struct b43_wldev *dev,
- struct lo_g_saved_values *sav)
-{
- struct b43_phy *phy = &dev->phy;
- u16 tmp;
-
- if (phy->rev >= 2) {
- b43_phy_write(dev, B43_PHY_PGACTL, 0xE300);
- tmp = (phy->pga_gain << 8);
- b43_phy_write(dev, B43_PHY_RFOVERVAL, tmp | 0xA0);
- udelay(5);
- b43_phy_write(dev, B43_PHY_RFOVERVAL, tmp | 0xA2);
- udelay(2);
- b43_phy_write(dev, B43_PHY_RFOVERVAL, tmp | 0xA3);
- } else {
- tmp = (phy->pga_gain | 0xEFA0);
- b43_phy_write(dev, B43_PHY_PGACTL, tmp);
- }
- if (phy->type == B43_PHYTYPE_G) {
- if (phy->rev >= 3)
- b43_phy_write(dev, B43_PHY_CCK(0x2E), 0xC078);
- else
- b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8078);
- if (phy->rev >= 2)
- b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x0202);
- else
- b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x0101);
- }
- b43_write16(dev, 0x3F4, sav->reg_3F4);
- b43_phy_write(dev, B43_PHY_PGACTL, sav->phy_pgactl);
- b43_phy_write(dev, B43_PHY_CCK(0x2A), sav->phy_cck_2A);
- b43_phy_write(dev, B43_PHY_SYNCCTL, sav->phy_syncctl);
- b43_phy_write(dev, B43_PHY_DACCTL, sav->phy_dacctl);
- b43_radio_write16(dev, 0x43, sav->radio_43);
- b43_radio_write16(dev, 0x7A, sav->radio_7A);
- if (!has_tx_magnification(phy)) {
- tmp = sav->radio_52;
- b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
- & 0xFF0F) | tmp);
- }
- b43_write16(dev, 0x3E2, sav->reg_3E2);
- if (phy->type == B43_PHYTYPE_B &&
- phy->radio_ver == 0x2050 && phy->radio_rev <= 5) {
- b43_phy_write(dev, B43_PHY_CCK(0x30), sav->phy_cck_30);
- b43_phy_write(dev, B43_PHY_CCK(0x06), sav->phy_cck_06);
- }
- if (phy->rev >= 2) {
- b43_phy_write(dev, B43_PHY_ANALOGOVER, sav->phy_analogover);
- b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
- sav->phy_analogoverval);
- b43_phy_write(dev, B43_PHY_CLASSCTL, sav->phy_classctl);
- b43_phy_write(dev, B43_PHY_RFOVER, sav->phy_rfover);
- b43_phy_write(dev, B43_PHY_RFOVERVAL, sav->phy_rfoverval);
- b43_phy_write(dev, B43_PHY_CCK(0x3E), sav->phy_cck_3E);
- b43_phy_write(dev, B43_PHY_CRS0, sav->phy_crs0);
- }
- if (b43_has_hardware_pctl(phy)) {
- tmp = (sav->phy_lo_mask & 0xBFFF);
- b43_phy_write(dev, B43_PHY_LO_MASK, tmp);
- b43_phy_write(dev, B43_PHY_EXTG(0x01), sav->phy_extg_01);
- b43_phy_write(dev, B43_PHY_DACCTL, sav->phy_dacctl_hwpctl);
- b43_phy_write(dev, B43_PHY_CCK(0x14), sav->phy_cck_14);
- b43_phy_write(dev, B43_PHY_HPWR_TSSICTL, sav->phy_hpwr_tssictl);
- }
- b43_radio_selectchannel(dev, sav->old_channel, 1);
-}
-
-struct b43_lo_g_statemachine {
- int current_state;
- int nr_measured;
- int state_val_multiplier;
- u16 lowest_feedth;
- struct b43_loctl min_loctl;
-};
-
-/* Loop over each possible value in this state. */
-static int lo_probe_possible_loctls(struct b43_wldev *dev,
- struct b43_loctl *probe_loctl,
- struct b43_lo_g_statemachine *d)
-{
- struct b43_phy *phy = &dev->phy;
- struct b43_loctl test_loctl;
- struct b43_loctl orig_loctl;
- struct b43_loctl prev_loctl = {
- .i = -100,
- .q = -100,
- };
- int i;
- int begin, end;
- int found_lower = 0;
- u16 feedth;
-
- static const struct b43_loctl modifiers[] = {
- {.i = 1,.q = 1,},
- {.i = 1,.q = 0,},
- {.i = 1,.q = -1,},
- {.i = 0,.q = -1,},
- {.i = -1,.q = -1,},
- {.i = -1,.q = 0,},
- {.i = -1,.q = 1,},
- {.i = 0,.q = 1,},
- };
-
- if (d->current_state == 0) {
- begin = 1;
- end = 8;
- } else if (d->current_state % 2 == 0) {
- begin = d->current_state - 1;
- end = d->current_state + 1;
- } else {
- begin = d->current_state - 2;
- end = d->current_state + 2;
- }
- if (begin < 1)
- begin += 8;
- if (end > 8)
- end -= 8;
-
- memcpy(&orig_loctl, probe_loctl, sizeof(struct b43_loctl));
- i = begin;
- d->current_state = i;
- while (1) {
- B43_WARN_ON(!(i >= 1 && i <= 8));
- memcpy(&test_loctl, &orig_loctl, sizeof(struct b43_loctl));
- test_loctl.i += modifiers[i - 1].i * d->state_val_multiplier;
- test_loctl.q += modifiers[i - 1].q * d->state_val_multiplier;
- if ((test_loctl.i != prev_loctl.i ||
- test_loctl.q != prev_loctl.q) &&
- (abs(test_loctl.i) <= 16 && abs(test_loctl.q) <= 16)) {
- b43_lo_write(dev, &test_loctl);
- feedth = lo_measure_feedthrough(dev, phy->lna_gain,
- phy->pga_gain,
- phy->trsw_rx_gain);
- if (feedth < d->lowest_feedth) {
- memcpy(probe_loctl, &test_loctl,
- sizeof(struct b43_loctl));
- found_lower = 1;
- d->lowest_feedth = feedth;
- if ((d->nr_measured < 2) &&
- !has_loopback_gain(phy))
- break;
- }
- }
- memcpy(&prev_loctl, &test_loctl, sizeof(prev_loctl));
- if (i == end)
- break;
- if (i == 8)
- i = 1;
- else
- i++;
- d->current_state = i;
- }
-
- return found_lower;
-}
-
-static void lo_probe_loctls_statemachine(struct b43_wldev *dev,
- struct b43_loctl *loctl,
- int *max_rx_gain)
-{
- struct b43_phy *phy = &dev->phy;
- struct b43_lo_g_statemachine d;
- u16 feedth;
- int found_lower;
- struct b43_loctl probe_loctl;
- int max_repeat = 1, repeat_cnt = 0;
-
- d.nr_measured = 0;
- d.state_val_multiplier = 1;
- if (has_loopback_gain(phy))
- d.state_val_multiplier = 3;
-
- memcpy(&d.min_loctl, loctl, sizeof(struct b43_loctl));
- if (has_loopback_gain(phy))
- max_repeat = 4;
- do {
- b43_lo_write(dev, &d.min_loctl);
- feedth = lo_measure_feedthrough(dev, phy->lna_gain,
- phy->pga_gain,
- phy->trsw_rx_gain);
- if (feedth < 0x258) {
- if (feedth >= 0x12C)
- *max_rx_gain += 6;
- else
- *max_rx_gain += 3;
- feedth = lo_measure_feedthrough(dev, phy->lna_gain,
- phy->pga_gain,
- phy->trsw_rx_gain);
- }
- d.lowest_feedth = feedth;
-
- d.current_state = 0;
- do {
- B43_WARN_ON(!
- (d.current_state >= 0
- && d.current_state <= 8));
- memcpy(&probe_loctl, &d.min_loctl,
- sizeof(struct b43_loctl));
- found_lower =
- lo_probe_possible_loctls(dev, &probe_loctl, &d);
- if (!found_lower)
- break;
- if ((probe_loctl.i == d.min_loctl.i) &&
- (probe_loctl.q == d.min_loctl.q))
- break;
- memcpy(&d.min_loctl, &probe_loctl,
- sizeof(struct b43_loctl));
- d.nr_measured++;
- } while (d.nr_measured < 24);
- memcpy(loctl, &d.min_loctl, sizeof(struct b43_loctl));
-
- if (has_loopback_gain(phy)) {
- if (d.lowest_feedth > 0x1194)
- *max_rx_gain -= 6;
- else if (d.lowest_feedth < 0x5DC)
- *max_rx_gain += 3;
- if (repeat_cnt == 0) {
- if (d.lowest_feedth <= 0x5DC) {
- d.state_val_multiplier = 1;
- repeat_cnt++;
- } else
- d.state_val_multiplier = 2;
- } else if (repeat_cnt == 2)
- d.state_val_multiplier = 1;
- }
- lo_measure_gain_values(dev, *max_rx_gain,
- has_loopback_gain(phy));
- } while (++repeat_cnt < max_repeat);
-}
-
-static
-struct b43_lo_calib * b43_calibrate_lo_setting(struct b43_wldev *dev,
- const struct b43_bbatt *bbatt,
- const struct b43_rfatt *rfatt)
-{
- struct b43_phy *phy = &dev->phy;
- struct b43_loctl loctl = {
- .i = 0,
- .q = 0,
- };
- int max_rx_gain;
- struct b43_lo_calib *cal;
- struct lo_g_saved_values uninitialized_var(saved_regs);
- /* Values from the "TXCTL Register and Value Table" */
- u16 txctl_reg;
- u16 txctl_value;
- u16 pad_mix_gain;
-
- saved_regs.old_channel = phy->channel;
- b43_mac_suspend(dev);
- lo_measure_setup(dev, &saved_regs);
-
- txctl_reg = lo_txctl_register_table(dev, &txctl_value, &pad_mix_gain);
-
- b43_radio_write16(dev, 0x43,
- (b43_radio_read16(dev, 0x43) & 0xFFF0)
- | rfatt->att);
- b43_radio_write16(dev, txctl_reg,
- (b43_radio_read16(dev, txctl_reg) & ~txctl_value)
- | (rfatt->with_padmix) ? txctl_value : 0);
-
- max_rx_gain = rfatt->att * 2;
- max_rx_gain += bbatt->att / 2;
- if (rfatt->with_padmix)
- max_rx_gain -= pad_mix_gain;
- if (has_loopback_gain(phy))
- max_rx_gain += phy->max_lb_gain;
- lo_measure_gain_values(dev, max_rx_gain,
- has_loopback_gain(phy));
-
- b43_phy_set_baseband_attenuation(dev, bbatt->att);
- lo_probe_loctls_statemachine(dev, &loctl, &max_rx_gain);
-
- lo_measure_restore(dev, &saved_regs);
- b43_mac_enable(dev);
-
- if (b43_debug(dev, B43_DBG_LO)) {
- b43dbg(dev->wl, "LO: Calibrated for BB(%u), RF(%u,%u) "
- "=> I=%d Q=%d\n",
- bbatt->att, rfatt->att, rfatt->with_padmix,
- loctl.i, loctl.q);
- }
-
- cal = kmalloc(sizeof(*cal), GFP_KERNEL);
- if (!cal) {
- b43warn(dev->wl, "LO calib: out of memory\n");
- return NULL;
- }
- memcpy(&cal->bbatt, bbatt, sizeof(*bbatt));
- memcpy(&cal->rfatt, rfatt, sizeof(*rfatt));
- memcpy(&cal->ctl, &loctl, sizeof(loctl));
- cal->calib_time = jiffies;
- INIT_LIST_HEAD(&cal->list);
-
- return cal;
-}
-
-/* Get a calibrated LO setting for the given attenuation values.
- * Might return a NULL pointer under OOM! */
-static
-struct b43_lo_calib * b43_get_calib_lo_settings(struct b43_wldev *dev,
- const struct b43_bbatt *bbatt,
- const struct b43_rfatt *rfatt)
-{
- struct b43_txpower_lo_control *lo = dev->phy.lo_control;
- struct b43_lo_calib *c;
-
- c = b43_find_lo_calib(lo, bbatt, rfatt);
- if (c)
- return c;
- /* Not in the list of calibrated LO settings.
- * Calibrate it now. */
- c = b43_calibrate_lo_setting(dev, bbatt, rfatt);
- if (!c)
- return NULL;
- list_add(&c->list, &lo->calib_list);
-
- return c;
-}
-
-void b43_gphy_dc_lt_init(struct b43_wldev *dev, bool update_all)
-{
- struct b43_phy *phy = &dev->phy;
- struct b43_txpower_lo_control *lo = phy->lo_control;
- int i;
- int rf_offset, bb_offset;
- const struct b43_rfatt *rfatt;
- const struct b43_bbatt *bbatt;
- u64 power_vector;
- bool table_changed = 0;
-
- BUILD_BUG_ON(B43_DC_LT_SIZE != 32);
- B43_WARN_ON(lo->rfatt_list.len * lo->bbatt_list.len > 64);
-
- power_vector = lo->power_vector;
- if (!update_all && !power_vector)
- return; /* Nothing to do. */
-
- /* Suspend the MAC now to avoid continuous suspend/enable
- * cycles in the loop. */
- b43_mac_suspend(dev);
-
- for (i = 0; i < B43_DC_LT_SIZE * 2; i++) {
- struct b43_lo_calib *cal;
- int idx;
- u16 val;
-
- if (!update_all && !(power_vector & (((u64)1ULL) << i)))
- continue;
- /* Update the table entry for this power_vector bit.
- * The table rows are RFatt entries and columns are BBatt. */
- bb_offset = i / lo->rfatt_list.len;
- rf_offset = i % lo->rfatt_list.len;
- bbatt = &(lo->bbatt_list.list[bb_offset]);
- rfatt = &(lo->rfatt_list.list[rf_offset]);
-
- cal = b43_calibrate_lo_setting(dev, bbatt, rfatt);
- if (!cal) {
- b43warn(dev->wl, "LO: Could not "
- "calibrate DC table entry\n");
- continue;
- }
- /*FIXME: Is Q really in the low nibble? */
- val = (u8)(cal->ctl.q);
- val |= ((u8)(cal->ctl.i)) << 4;
- kfree(cal);
-
- /* Get the index into the hardware DC LT. */
- idx = i / 2;
- /* Change the table in memory. */
- if (i % 2) {
- /* Change the high byte. */
- lo->dc_lt[idx] = (lo->dc_lt[idx] & 0x00FF)
- | ((val & 0x00FF) << 8);
- } else {
- /* Change the low byte. */
- lo->dc_lt[idx] = (lo->dc_lt[idx] & 0xFF00)
- | (val & 0x00FF);
- }
- table_changed = 1;
- }
- if (table_changed) {
- /* The table changed in memory. Update the hardware table. */
- for (i = 0; i < B43_DC_LT_SIZE; i++)
- b43_phy_write(dev, 0x3A0 + i, lo->dc_lt[i]);
- }
- b43_mac_enable(dev);
-}
-
-/* Fixup the RF attenuation value for the case where we are
- * using the PAD mixer. */
-static inline void b43_lo_fixup_rfatt(struct b43_rfatt *rf)
-{
- if (!rf->with_padmix)
- return;
- if ((rf->att != 1) && (rf->att != 2) && (rf->att != 3))
- rf->att = 4;
-}
-
-void b43_lo_g_adjust(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- struct b43_lo_calib *cal;
- struct b43_rfatt rf;
-
- memcpy(&rf, &phy->rfatt, sizeof(rf));
- b43_lo_fixup_rfatt(&rf);
-
- cal = b43_get_calib_lo_settings(dev, &phy->bbatt, &rf);
- if (!cal)
- return;
- b43_lo_write(dev, &cal->ctl);
-}
-
-void b43_lo_g_adjust_to(struct b43_wldev *dev,
- u16 rfatt, u16 bbatt, u16 tx_control)
-{
- struct b43_rfatt rf;
- struct b43_bbatt bb;
- struct b43_lo_calib *cal;
-
- memset(&rf, 0, sizeof(rf));
- memset(&bb, 0, sizeof(bb));
- rf.att = rfatt;
- bb.att = bbatt;
- b43_lo_fixup_rfatt(&rf);
- cal = b43_get_calib_lo_settings(dev, &bb, &rf);
- if (!cal)
- return;
- b43_lo_write(dev, &cal->ctl);
-}
-
-/* Periodic LO maintanance work */
-void b43_lo_g_maintanance_work(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- struct b43_txpower_lo_control *lo = phy->lo_control;
- unsigned long now;
- unsigned long expire;
- struct b43_lo_calib *cal, *tmp;
- bool current_item_expired = 0;
- bool hwpctl;
-
- if (!lo)
- return;
- now = jiffies;
- hwpctl = b43_has_hardware_pctl(phy);
-
- if (hwpctl) {
- /* Read the power vector and update it, if needed. */
- expire = now - B43_LO_PWRVEC_EXPIRE;
- if (time_before(lo->pwr_vec_read_time, expire)) {
- lo_read_power_vector(dev);
- b43_gphy_dc_lt_init(dev, 0);
- }
- //FIXME Recalc the whole DC table from time to time?
- }
-
- if (hwpctl)
- return;
- /* Search for expired LO settings. Remove them.
- * Recalibrate the current setting, if expired. */
- expire = now - B43_LO_CALIB_EXPIRE;
- list_for_each_entry_safe(cal, tmp, &lo->calib_list, list) {
- if (!time_before(cal->calib_time, expire))
- continue;
- /* This item expired. */
- if (b43_compare_bbatt(&cal->bbatt, &phy->bbatt) &&
- b43_compare_rfatt(&cal->rfatt, &phy->rfatt)) {
- B43_WARN_ON(current_item_expired);
- current_item_expired = 1;
- }
- if (b43_debug(dev, B43_DBG_LO)) {
- b43dbg(dev->wl, "LO: Item BB(%u), RF(%u,%u), "
- "I=%d, Q=%d expired\n",
- cal->bbatt.att, cal->rfatt.att,
- cal->rfatt.with_padmix,
- cal->ctl.i, cal->ctl.q);
- }
- list_del(&cal->list);
- kfree(cal);
- }
- if (current_item_expired || unlikely(list_empty(&lo->calib_list))) {
- /* Recalibrate currently used LO setting. */
- if (b43_debug(dev, B43_DBG_LO))
- b43dbg(dev->wl, "LO: Recalibrating current LO setting\n");
- cal = b43_calibrate_lo_setting(dev, &phy->bbatt, &phy->rfatt);
- if (cal) {
- list_add(&cal->list, &lo->calib_list);
- b43_lo_write(dev, &cal->ctl);
- } else
- b43warn(dev->wl, "Failed to recalibrate current LO setting\n");
- }
-}
-
-void b43_lo_g_cleanup(struct b43_wldev *dev)
-{
- struct b43_txpower_lo_control *lo = dev->phy.lo_control;
- struct b43_lo_calib *cal, *tmp;
-
- if (!lo)
- return;
- list_for_each_entry_safe(cal, tmp, &lo->calib_list, list) {
- list_del(&cal->list);
- kfree(cal);
- }
-}
-
-/* LO Initialization */
-void b43_lo_g_init(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
-
- if (b43_has_hardware_pctl(phy)) {
- lo_read_power_vector(dev);
- b43_gphy_dc_lt_init(dev, 1);
- }
-}
-#ifndef B43_LO_H_
-#define B43_LO_H_
-
-#include "phy.h"
-
-struct b43_wldev;
-
-/* Local Oscillator control value-pair. */
-struct b43_loctl {
- /* Control values. */
- s8 i;
- s8 q;
-};
-/* Debugging: Poison value for i and q values. */
-#define B43_LOCTL_POISON 111
-
-/* This struct holds calibrated LO settings for a set of
- * Baseband and RF attenuation settings. */
-struct b43_lo_calib {
- /* The set of attenuation values this set of LO
- * control values is calibrated for. */
- struct b43_bbatt bbatt;
- struct b43_rfatt rfatt;
- /* The set of control values for the LO. */
- struct b43_loctl ctl;
- /* The time when these settings were calibrated (in jiffies) */
- unsigned long calib_time;
- /* List. */
- struct list_head list;
-};
-
-/* Size of the DC Lookup Table in 16bit words. */
-#define B43_DC_LT_SIZE 32
-
-/* Local Oscillator calibration information */
-struct b43_txpower_lo_control {
- /* Lists of RF and BB attenuation values for this device.
- * Used for building hardware power control tables. */
- struct b43_rfatt_list rfatt_list;
- struct b43_bbatt_list bbatt_list;
-
- /* The DC Lookup Table is cached in memory here.
- * Note that this is only used for Hardware Power Control. */
- u16 dc_lt[B43_DC_LT_SIZE];
-
- /* List of calibrated control values (struct b43_lo_calib). */
- struct list_head calib_list;
- /* Last time the power vector was read (jiffies). */
- unsigned long pwr_vec_read_time;
- /* Last time the txctl values were measured (jiffies). */
- unsigned long txctl_measured_time;
-
- /* Current TX Bias value */
- u8 tx_bias;
- /* Current TX Magnification Value (if used by the device) */
- u8 tx_magn;
-
- /* Saved device PowerVector */
- u64 power_vector;
-};
-
-/* Calibration expire timeouts.
- * Timeouts must be multiple of 15 seconds. To make sure
- * the item really expired when the 15 second timer hits, we
- * subtract two additional seconds from the timeout. */
-#define B43_LO_CALIB_EXPIRE (HZ * (30 - 2))
-#define B43_LO_PWRVEC_EXPIRE (HZ * (30 - 2))
-#define B43_LO_TXCTL_EXPIRE (HZ * (180 - 4))
-
-
-/* Adjust the Local Oscillator to the saved attenuation
- * and txctl values.
- */
-void b43_lo_g_adjust(struct b43_wldev *dev);
-/* Adjust to specific values. */
-void b43_lo_g_adjust_to(struct b43_wldev *dev,
- u16 rfatt, u16 bbatt, u16 tx_control);
-
-void b43_gphy_dc_lt_init(struct b43_wldev *dev, bool update_all);
-
-void b43_lo_g_maintanance_work(struct b43_wldev *dev);
-void b43_lo_g_cleanup(struct b43_wldev *dev);
-void b43_lo_g_init(struct b43_wldev *dev);
-
-#endif /* B43_LO_H_ */
-/*
-
- Broadcom B43 wireless driver
-
- Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
- Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
- Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
- Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
- Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
-
- Some parts of the code in this file are derived from the ipw2200
- driver Copyright(c) 2003 - 2004 Intel Corporation.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; see the file COPYING. If not, write to
- the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
- Boston, MA 02110-1301, USA.
-
-*/
-
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/moduleparam.h>
-#include <linux/if_arp.h>
-#include <linux/etherdevice.h>
-#include <linux/version.h>
-#include <linux/firmware.h>
-#include <linux/wireless.h>
-#include <linux/workqueue.h>
-#include <linux/skbuff.h>
-#include <linux/io.h>
-#include <linux/dma-mapping.h>
-#include <asm/unaligned.h>
-
-#include "b43.h"
-#include "main.h"
-#include "debugfs.h"
-#include "phy.h"
-#include "nphy.h"
-#include "dma.h"
-#include "pio.h"
-#include "sysfs.h"
-#include "xmit.h"
-#include "lo.h"
-#include "pcmcia.h"
-
-MODULE_DESCRIPTION("Broadcom B43 wireless driver");
-MODULE_AUTHOR("Martin Langer");
-MODULE_AUTHOR("Stefano Brivio");
-MODULE_AUTHOR("Michael Buesch");
-MODULE_LICENSE("GPL");
-
-MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
-
-
-static int modparam_bad_frames_preempt;
-module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
-MODULE_PARM_DESC(bad_frames_preempt,
- "enable(1) / disable(0) Bad Frames Preemption");
-
-static char modparam_fwpostfix[16];
-module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
-MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
-
-static int modparam_hwpctl;
-module_param_named(hwpctl, modparam_hwpctl, int, 0444);
-MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
-
-static int modparam_nohwcrypt;
-module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
-MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
-
-int b43_modparam_qos = 1;
-module_param_named(qos, b43_modparam_qos, int, 0444);
-MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
-
-static int modparam_btcoex = 1;
-module_param_named(btcoex, modparam_btcoex, int, 0444);
-MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistance (default on)");
-
-
-static const struct ssb_device_id b43_ssb_tbl[] = {
- SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
- SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
- SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
- SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
- SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
- SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
- SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
- SSB_DEVTABLE_END
-};
-
-MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
-
-/* Channel and ratetables are shared for all devices.
- * They can't be const, because ieee80211 puts some precalculated
- * data in there. This data is the same for all devices, so we don't
- * get concurrency issues */
-#define RATETAB_ENT(_rateid, _flags) \
- { \
- .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
- .hw_value = (_rateid), \
- .flags = (_flags), \
- }
-
-/*
- * NOTE: When changing this, sync with xmit.c's
- * b43_plcp_get_bitrate_idx_* functions!
- */
-static struct ieee80211_rate __b43_ratetable[] = {
- RATETAB_ENT(B43_CCK_RATE_1MB, 0),
- RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
- RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
- RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
- RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
- RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
- RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
- RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
- RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
- RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
- RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
- RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
-};
-
-#define b43_a_ratetable (__b43_ratetable + 4)
-#define b43_a_ratetable_size 8
-#define b43_b_ratetable (__b43_ratetable + 0)
-#define b43_b_ratetable_size 4
-#define b43_g_ratetable (__b43_ratetable + 0)
-#define b43_g_ratetable_size 12
-
-#define CHAN4G(_channel, _freq, _flags) { \
- .band = IEEE80211_BAND_2GHZ, \
- .center_freq = (_freq), \
- .hw_value = (_channel), \
- .flags = (_flags), \
- .max_antenna_gain = 0, \
- .max_power = 30, \
-}
-static struct ieee80211_channel b43_2ghz_chantable[] = {
- CHAN4G(1, 2412, 0),
- CHAN4G(2, 2417, 0),
- CHAN4G(3, 2422, 0),
- CHAN4G(4, 2427, 0),
- CHAN4G(5, 2432, 0),
- CHAN4G(6, 2437, 0),
- CHAN4G(7, 2442, 0),
- CHAN4G(8, 2447, 0),
- CHAN4G(9, 2452, 0),
- CHAN4G(10, 2457, 0),
- CHAN4G(11, 2462, 0),
- CHAN4G(12, 2467, 0),
- CHAN4G(13, 2472, 0),
- CHAN4G(14, 2484, 0),
-};
-#undef CHAN4G
-
-#define CHAN5G(_channel, _flags) { \
- .band = IEEE80211_BAND_5GHZ, \
- .center_freq = 5000 + (5 * (_channel)), \
- .hw_value = (_channel), \
- .flags = (_flags), \
- .max_antenna_gain = 0, \
- .max_power = 30, \
-}
-static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
- CHAN5G(32, 0), CHAN5G(34, 0),
- CHAN5G(36, 0), CHAN5G(38, 0),
- CHAN5G(40, 0), CHAN5G(42, 0),
- CHAN5G(44, 0), CHAN5G(46, 0),
- CHAN5G(48, 0), CHAN5G(50, 0),
- CHAN5G(52, 0), CHAN5G(54, 0),
- CHAN5G(56, 0), CHAN5G(58, 0),
- CHAN5G(60, 0), CHAN5G(62, 0),
- CHAN5G(64, 0), CHAN5G(66, 0),
- CHAN5G(68, 0), CHAN5G(70, 0),
- CHAN5G(72, 0), CHAN5G(74, 0),
- CHAN5G(76, 0), CHAN5G(78, 0),
- CHAN5G(80, 0), CHAN5G(82, 0),
- CHAN5G(84, 0), CHAN5G(86, 0),
- CHAN5G(88, 0), CHAN5G(90, 0),
- CHAN5G(92, 0), CHAN5G(94, 0),
- CHAN5G(96, 0), CHAN5G(98, 0),
- CHAN5G(100, 0), CHAN5G(102, 0),
- CHAN5G(104, 0), CHAN5G(106, 0),
- CHAN5G(108, 0), CHAN5G(110, 0),
- CHAN5G(112, 0), CHAN5G(114, 0),
- CHAN5G(116, 0), CHAN5G(118, 0),
- CHAN5G(120, 0), CHAN5G(122, 0),
- CHAN5G(124, 0), CHAN5G(126, 0),
- CHAN5G(128, 0), CHAN5G(130, 0),
- CHAN5G(132, 0), CHAN5G(134, 0),
- CHAN5G(136, 0), CHAN5G(138, 0),
- CHAN5G(140, 0), CHAN5G(142, 0),
- CHAN5G(144, 0), CHAN5G(145, 0),
- CHAN5G(146, 0), CHAN5G(147, 0),
- CHAN5G(148, 0), CHAN5G(149, 0),
- CHAN5G(150, 0), CHAN5G(151, 0),
- CHAN5G(152, 0), CHAN5G(153, 0),
- CHAN5G(154, 0), CHAN5G(155, 0),
- CHAN5G(156, 0), CHAN5G(157, 0),
- CHAN5G(158, 0), CHAN5G(159, 0),
- CHAN5G(160, 0), CHAN5G(161, 0),
- CHAN5G(162, 0), CHAN5G(163, 0),
- CHAN5G(164, 0), CHAN5G(165, 0),
- CHAN5G(166, 0), CHAN5G(168, 0),
- CHAN5G(170, 0), CHAN5G(172, 0),
- CHAN5G(174, 0), CHAN5G(176, 0),
- CHAN5G(178, 0), CHAN5G(180, 0),
- CHAN5G(182, 0), CHAN5G(184, 0),
- CHAN5G(186, 0), CHAN5G(188, 0),
- CHAN5G(190, 0), CHAN5G(192, 0),
- CHAN5G(194, 0), CHAN5G(196, 0),
- CHAN5G(198, 0), CHAN5G(200, 0),
- CHAN5G(202, 0), CHAN5G(204, 0),
- CHAN5G(206, 0), CHAN5G(208, 0),
- CHAN5G(210, 0), CHAN5G(212, 0),
- CHAN5G(214, 0), CHAN5G(216, 0),
- CHAN5G(218, 0), CHAN5G(220, 0),
- CHAN5G(222, 0), CHAN5G(224, 0),
- CHAN5G(226, 0), CHAN5G(228, 0),
-};
-
-static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
- CHAN5G(34, 0), CHAN5G(36, 0),
- CHAN5G(38, 0), CHAN5G(40, 0),
- CHAN5G(42, 0), CHAN5G(44, 0),
- CHAN5G(46, 0), CHAN5G(48, 0),
- CHAN5G(52, 0), CHAN5G(56, 0),
- CHAN5G(60, 0), CHAN5G(64, 0),
- CHAN5G(100, 0), CHAN5G(104, 0),
- CHAN5G(108, 0), CHAN5G(112, 0),
- CHAN5G(116, 0), CHAN5G(120, 0),
- CHAN5G(124, 0), CHAN5G(128, 0),
- CHAN5G(132, 0), CHAN5G(136, 0),
- CHAN5G(140, 0), CHAN5G(149, 0),
- CHAN5G(153, 0), CHAN5G(157, 0),
- CHAN5G(161, 0), CHAN5G(165, 0),
- CHAN5G(184, 0), CHAN5G(188, 0),
- CHAN5G(192, 0), CHAN5G(196, 0),
- CHAN5G(200, 0), CHAN5G(204, 0),
- CHAN5G(208, 0), CHAN5G(212, 0),
- CHAN5G(216, 0),
-};
-#undef CHAN5G
-
-static struct ieee80211_supported_band b43_band_5GHz_nphy = {
- .band = IEEE80211_BAND_5GHZ,
- .channels = b43_5ghz_nphy_chantable,
- .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
- .bitrates = b43_a_ratetable,
- .n_bitrates = b43_a_ratetable_size,
-};
-
-static struct ieee80211_supported_band b43_band_5GHz_aphy = {
- .band = IEEE80211_BAND_5GHZ,
- .channels = b43_5ghz_aphy_chantable,
- .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
- .bitrates = b43_a_ratetable,
- .n_bitrates = b43_a_ratetable_size,
-};
-
-static struct ieee80211_supported_band b43_band_2GHz = {
- .band = IEEE80211_BAND_2GHZ,
- .channels = b43_2ghz_chantable,
- .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
- .bitrates = b43_g_ratetable,
- .n_bitrates = b43_g_ratetable_size,
-};
-
-static void b43_wireless_core_exit(struct b43_wldev *dev);
-static int b43_wireless_core_init(struct b43_wldev *dev);
-static void b43_wireless_core_stop(struct b43_wldev *dev);
-static int b43_wireless_core_start(struct b43_wldev *dev);
-
-static int b43_ratelimit(struct b43_wl *wl)
-{
- if (!wl || !wl->current_dev)
- return 1;
- if (b43_status(wl->current_dev) < B43_STAT_STARTED)
- return 1;
- /* We are up and running.
- * Ratelimit the messages to avoid DoS over the net. */
- return net_ratelimit();
-}
-
-void b43info(struct b43_wl *wl, const char *fmt, ...)
-{
- va_list args;
-
- if (!b43_ratelimit(wl))
- return;
- va_start(args, fmt);
- printk(KERN_INFO "b43-%s: ",
- (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
- vprintk(fmt, args);
- va_end(args);
-}
-
-void b43err(struct b43_wl *wl, const char *fmt, ...)
-{
- va_list args;
-
- if (!b43_ratelimit(wl))
- return;
- va_start(args, fmt);
- printk(KERN_ERR "b43-%s ERROR: ",
- (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
- vprintk(fmt, args);
- va_end(args);
-}
-
-void b43warn(struct b43_wl *wl, const char *fmt, ...)
-{
- va_list args;
-
- if (!b43_ratelimit(wl))
- return;
- va_start(args, fmt);
- printk(KERN_WARNING "b43-%s warning: ",
- (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
- vprintk(fmt, args);
- va_end(args);
-}
-
-#if B43_DEBUG
-void b43dbg(struct b43_wl *wl, const char *fmt, ...)
-{
- va_list args;
-
- va_start(args, fmt);
- printk(KERN_DEBUG "b43-%s debug: ",
- (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
- vprintk(fmt, args);
- va_end(args);
-}
-#endif /* DEBUG */
-
-static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
-{
- u32 macctl;
-
- B43_WARN_ON(offset % 4 != 0);
-
- macctl = b43_read32(dev, B43_MMIO_MACCTL);
- if (macctl & B43_MACCTL_BE)
- val = swab32(val);
-
- b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
- mmiowb();
- b43_write32(dev, B43_MMIO_RAM_DATA, val);
-}
-
-static inline void b43_shm_control_word(struct b43_wldev *dev,
- u16 routing, u16 offset)
-{
- u32 control;
-
- /* "offset" is the WORD offset. */
- control = routing;
- control <<= 16;
- control |= offset;
- b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
-}
-
-u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
-{
- struct b43_wl *wl = dev->wl;
- unsigned long flags;
- u32 ret;
-
- spin_lock_irqsave(&wl->shm_lock, flags);
- if (routing == B43_SHM_SHARED) {
- B43_WARN_ON(offset & 0x0001);
- if (offset & 0x0003) {
- /* Unaligned access */
- b43_shm_control_word(dev, routing, offset >> 2);
- ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
- ret <<= 16;
- b43_shm_control_word(dev, routing, (offset >> 2) + 1);
- ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
-
- goto out;
- }
- offset >>= 2;
- }
- b43_shm_control_word(dev, routing, offset);
- ret = b43_read32(dev, B43_MMIO_SHM_DATA);
-out:
- spin_unlock_irqrestore(&wl->shm_lock, flags);
-
- return ret;
-}
-
-u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
-{
- struct b43_wl *wl = dev->wl;
- unsigned long flags;
- u16 ret;
-
- spin_lock_irqsave(&wl->shm_lock, flags);
- if (routing == B43_SHM_SHARED) {
- B43_WARN_ON(offset & 0x0001);
- if (offset & 0x0003) {
- /* Unaligned access */
- b43_shm_control_word(dev, routing, offset >> 2);
- ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
-
- goto out;
- }
- offset >>= 2;
- }
- b43_shm_control_word(dev, routing, offset);
- ret = b43_read16(dev, B43_MMIO_SHM_DATA);
-out:
- spin_unlock_irqrestore(&wl->shm_lock, flags);
-
- return ret;
-}
-
-void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
-{
- struct b43_wl *wl = dev->wl;
- unsigned long flags;
-
- spin_lock_irqsave(&wl->shm_lock, flags);
- if (routing == B43_SHM_SHARED) {
- B43_WARN_ON(offset & 0x0001);
- if (offset & 0x0003) {
- /* Unaligned access */
- b43_shm_control_word(dev, routing, offset >> 2);
- b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
- (value >> 16) & 0xffff);
- b43_shm_control_word(dev, routing, (offset >> 2) + 1);
- b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
- goto out;
- }
- offset >>= 2;
- }
- b43_shm_control_word(dev, routing, offset);
- b43_write32(dev, B43_MMIO_SHM_DATA, value);
-out:
- spin_unlock_irqrestore(&wl->shm_lock, flags);
-}
-
-void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
-{
- struct b43_wl *wl = dev->wl;
- unsigned long flags;
-
- spin_lock_irqsave(&wl->shm_lock, flags);
- if (routing == B43_SHM_SHARED) {
- B43_WARN_ON(offset & 0x0001);
- if (offset & 0x0003) {
- /* Unaligned access */
- b43_shm_control_word(dev, routing, offset >> 2);
- b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
- goto out;
- }
- offset >>= 2;
- }
- b43_shm_control_word(dev, routing, offset);
- b43_write16(dev, B43_MMIO_SHM_DATA, value);
-out:
- spin_unlock_irqrestore(&wl->shm_lock, flags);
-}
-
-/* Read HostFlags */
-u64 b43_hf_read(struct b43_wldev * dev)
-{
- u64 ret;
-
- ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
- ret <<= 16;
- ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
- ret <<= 16;
- ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
-
- return ret;
-}
-
-/* Write HostFlags */
-void b43_hf_write(struct b43_wldev *dev, u64 value)
-{
- u16 lo, mi, hi;
-
- lo = (value & 0x00000000FFFFULL);
- mi = (value & 0x0000FFFF0000ULL) >> 16;
- hi = (value & 0xFFFF00000000ULL) >> 32;
- b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
- b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
- b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
-}
-
-void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
-{
- /* We need to be careful. As we read the TSF from multiple
- * registers, we should take care of register overflows.
- * In theory, the whole tsf read process should be atomic.
- * We try to be atomic here, by restaring the read process,
- * if any of the high registers changed (overflew).
- */
- if (dev->dev->id.revision >= 3) {
- u32 low, high, high2;
-
- do {
- high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
- low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
- high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
- } while (unlikely(high != high2));
-
- *tsf = high;
- *tsf <<= 32;
- *tsf |= low;
- } else {
- u64 tmp;
- u16 v0, v1, v2, v3;
- u16 test1, test2, test3;
-
- do {
- v3 = b43_read16(dev, B43_MMIO_TSF_3);
- v2 = b43_read16(dev, B43_MMIO_TSF_2);
- v1 = b43_read16(dev, B43_MMIO_TSF_1);
- v0 = b43_read16(dev, B43_MMIO_TSF_0);
-
- test3 = b43_read16(dev, B43_MMIO_TSF_3);
- test2 = b43_read16(dev, B43_MMIO_TSF_2);
- test1 = b43_read16(dev, B43_MMIO_TSF_1);
- } while (v3 != test3 || v2 != test2 || v1 != test1);
-
- *tsf = v3;
- *tsf <<= 48;
- tmp = v2;
- tmp <<= 32;
- *tsf |= tmp;
- tmp = v1;
- tmp <<= 16;
- *tsf |= tmp;
- *tsf |= v0;
- }
-}
-
-static void b43_time_lock(struct b43_wldev *dev)
-{
- u32 macctl;
-
- macctl = b43_read32(dev, B43_MMIO_MACCTL);
- macctl |= B43_MACCTL_TBTTHOLD;
- b43_write32(dev, B43_MMIO_MACCTL, macctl);
- /* Commit the write */
- b43_read32(dev, B43_MMIO_MACCTL);
-}
-
-static void b43_time_unlock(struct b43_wldev *dev)
-{
- u32 macctl;
-
- macctl = b43_read32(dev, B43_MMIO_MACCTL);
- macctl &= ~B43_MACCTL_TBTTHOLD;
- b43_write32(dev, B43_MMIO_MACCTL, macctl);
- /* Commit the write */
- b43_read32(dev, B43_MMIO_MACCTL);
-}
-
-static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
-{
- /* Be careful with the in-progress timer.
- * First zero out the low register, so we have a full
- * register-overflow duration to complete the operation.
- */
- if (dev->dev->id.revision >= 3) {
- u32 lo = (tsf & 0x00000000FFFFFFFFULL);
- u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
-
- b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
- mmiowb();
- b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
- mmiowb();
- b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
- } else {
- u16 v0 = (tsf & 0x000000000000FFFFULL);
- u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
- u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
- u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
-
- b43_write16(dev, B43_MMIO_TSF_0, 0);
- mmiowb();
- b43_write16(dev, B43_MMIO_TSF_3, v3);
- mmiowb();
- b43_write16(dev, B43_MMIO_TSF_2, v2);
- mmiowb();
- b43_write16(dev, B43_MMIO_TSF_1, v1);
- mmiowb();
- b43_write16(dev, B43_MMIO_TSF_0, v0);
- }
-}
-
-void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
-{
- b43_time_lock(dev);
- b43_tsf_write_locked(dev, tsf);
- b43_time_unlock(dev);
-}
-
-static
-void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
-{
- static const u8 zero_addr[ETH_ALEN] = { 0 };
- u16 data;
-
- if (!mac)
- mac = zero_addr;
-
- offset |= 0x0020;
- b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
-
- data = mac[0];
- data |= mac[1] << 8;
- b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
- data = mac[2];
- data |= mac[3] << 8;
- b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
- data = mac[4];
- data |= mac[5] << 8;
- b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
-}
-
-static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
-{
- const u8 *mac;
- const u8 *bssid;
- u8 mac_bssid[ETH_ALEN * 2];
- int i;
- u32 tmp;
-
- bssid = dev->wl->bssid;
- mac = dev->wl->mac_addr;
-
- b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
-
- memcpy(mac_bssid, mac, ETH_ALEN);
- memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
-
- /* Write our MAC address and BSSID to template ram */
- for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
- tmp = (u32) (mac_bssid[i + 0]);
- tmp |= (u32) (mac_bssid[i + 1]) << 8;
- tmp |= (u32) (mac_bssid[i + 2]) << 16;
- tmp |= (u32) (mac_bssid[i + 3]) << 24;
- b43_ram_write(dev, 0x20 + i, tmp);
- }
-}
-
-static void b43_upload_card_macaddress(struct b43_wldev *dev)
-{
- b43_write_mac_bssid_templates(dev);
- b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
-}
-
-static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
-{
- /* slot_time is in usec. */
- if (dev->phy.type != B43_PHYTYPE_G)
- return;
- b43_write16(dev, 0x684, 510 + slot_time);
- b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
-}
-
-static void b43_short_slot_timing_enable(struct b43_wldev *dev)
-{
- b43_set_slot_time(dev, 9);
- dev->short_slot = 1;
-}
-
-static void b43_short_slot_timing_disable(struct b43_wldev *dev)
-{
- b43_set_slot_time(dev, 20);
- dev->short_slot = 0;
-}
-
-/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
- * Returns the _previously_ enabled IRQ mask.
- */
-static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
-{
- u32 old_mask;
-
- old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
- b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
-
- return old_mask;
-}
-
-/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
- * Returns the _previously_ enabled IRQ mask.
- */
-static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
-{
- u32 old_mask;
-
- old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
- b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
-
- return old_mask;
-}
-
-/* Synchronize IRQ top- and bottom-half.
- * IRQs must be masked before calling this.
- * This must not be called with the irq_lock held.
- */
-static void b43_synchronize_irq(struct b43_wldev *dev)
-{
- synchronize_irq(dev->dev->irq);
- tasklet_kill(&dev->isr_tasklet);
-}
-
-/* DummyTransmission function, as documented on
- * http://bcm-specs.sipsolutions.net/DummyTransmission
- */
-void b43_dummy_transmission(struct b43_wldev *dev)
-{
- struct b43_wl *wl = dev->wl;
- struct b43_phy *phy = &dev->phy;
- unsigned int i, max_loop;
- u16 value;
- u32 buffer[5] = {
- 0x00000000,
- 0x00D40000,
- 0x00000000,
- 0x01000000,
- 0x00000000,
- };
-
- switch (phy->type) {
- case B43_PHYTYPE_A:
- max_loop = 0x1E;
- buffer[0] = 0x000201CC;
- break;
- case B43_PHYTYPE_B:
- case B43_PHYTYPE_G:
- max_loop = 0xFA;
- buffer[0] = 0x000B846E;
- break;
- default:
- B43_WARN_ON(1);
- return;
- }
-
- spin_lock_irq(&wl->irq_lock);
- write_lock(&wl->tx_lock);
-
- for (i = 0; i < 5; i++)
- b43_ram_write(dev, i * 4, buffer[i]);
-
- /* Commit writes */
- b43_read32(dev, B43_MMIO_MACCTL);
-
- b43_write16(dev, 0x0568, 0x0000);
- b43_write16(dev, 0x07C0, 0x0000);
- value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
- b43_write16(dev, 0x050C, value);
- b43_write16(dev, 0x0508, 0x0000);
- b43_write16(dev, 0x050A, 0x0000);
- b43_write16(dev, 0x054C, 0x0000);
- b43_write16(dev, 0x056A, 0x0014);
- b43_write16(dev, 0x0568, 0x0826);
- b43_write16(dev, 0x0500, 0x0000);
- b43_write16(dev, 0x0502, 0x0030);
-
- if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
- b43_radio_write16(dev, 0x0051, 0x0017);
- for (i = 0x00; i < max_loop; i++) {
- value = b43_read16(dev, 0x050E);
- if (value & 0x0080)
- break;
- udelay(10);
- }
- for (i = 0x00; i < 0x0A; i++) {
- value = b43_read16(dev, 0x050E);
- if (value & 0x0400)
- break;
- udelay(10);
- }
- for (i = 0x00; i < 0x0A; i++) {
- value = b43_read16(dev, 0x0690);
- if (!(value & 0x0100))
- break;
- udelay(10);
- }
- if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
- b43_radio_write16(dev, 0x0051, 0x0037);
-
- write_unlock(&wl->tx_lock);
- spin_unlock_irq(&wl->irq_lock);
-}
-
-static void key_write(struct b43_wldev *dev,
- u8 index, u8 algorithm, const u8 * key)
-{
- unsigned int i;
- u32 offset;
- u16 value;
- u16 kidx;
-
- /* Key index/algo block */
- kidx = b43_kidx_to_fw(dev, index);
- value = ((kidx << 4) | algorithm);
- b43_shm_write16(dev, B43_SHM_SHARED,
- B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
-
- /* Write the key to the Key Table Pointer offset */
- offset = dev->ktp + (index * B43_SEC_KEYSIZE);
- for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
- value = key[i];
- value |= (u16) (key[i + 1]) << 8;
- b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
- }
-}
-
-static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
-{
- u32 addrtmp[2] = { 0, 0, };
- u8 per_sta_keys_start = 8;
-
- if (b43_new_kidx_api(dev))
- per_sta_keys_start = 4;
-
- B43_WARN_ON(index < per_sta_keys_start);
- /* We have two default TX keys and possibly two default RX keys.
- * Physical mac 0 is mapped to physical key 4 or 8, depending
- * on the firmware version.
- * So we must adjust the index here.
- */
- index -= per_sta_keys_start;
-
- if (addr) {
- addrtmp[0] = addr[0];
- addrtmp[0] |= ((u32) (addr[1]) << 8);
- addrtmp[0] |= ((u32) (addr[2]) << 16);
- addrtmp[0] |= ((u32) (addr[3]) << 24);
- addrtmp[1] = addr[4];
- addrtmp[1] |= ((u32) (addr[5]) << 8);
- }
-
- if (dev->dev->id.revision >= 5) {
- /* Receive match transmitter address mechanism */
- b43_shm_write32(dev, B43_SHM_RCMTA,
- (index * 2) + 0, addrtmp[0]);
- b43_shm_write16(dev, B43_SHM_RCMTA,
- (index * 2) + 1, addrtmp[1]);
- } else {
- /* RXE (Receive Engine) and
- * PSM (Programmable State Machine) mechanism
- */
- if (index < 8) {
- /* TODO write to RCM 16, 19, 22 and 25 */
- } else {
- b43_shm_write32(dev, B43_SHM_SHARED,
- B43_SHM_SH_PSM + (index * 6) + 0,
- addrtmp[0]);
- b43_shm_write16(dev, B43_SHM_SHARED,
- B43_SHM_SH_PSM + (index * 6) + 4,
- addrtmp[1]);
- }
- }
-}
-
-static void do_key_write(struct b43_wldev *dev,
- u8 index, u8 algorithm,
- const u8 * key, size_t key_len, const u8 * mac_addr)
-{
- u8 buf[B43_SEC_KEYSIZE] = { 0, };
- u8 per_sta_keys_start = 8;
-
- if (b43_new_kidx_api(dev))
- per_sta_keys_start = 4;
-
- B43_WARN_ON(index >= dev->max_nr_keys);
- B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
-
- if (index >= per_sta_keys_start)
- keymac_write(dev, index, NULL); /* First zero out mac. */
- if (key)
- memcpy(buf, key, key_len);
- key_write(dev, index, algorithm, buf);
- if (index >= per_sta_keys_start)
- keymac_write(dev, index, mac_addr);
-
- dev->key[index].algorithm = algorithm;
-}
-
-static int b43_key_write(struct b43_wldev *dev,
- int index, u8 algorithm,
- const u8 * key, size_t key_len,
- const u8 * mac_addr,
- struct ieee80211_key_conf *keyconf)
-{
- int i;
- int sta_keys_start;
-
- if (key_len > B43_SEC_KEYSIZE)
- return -EINVAL;
- for (i = 0; i < dev->max_nr_keys; i++) {
- /* Check that we don't already have this key. */
- B43_WARN_ON(dev->key[i].keyconf == keyconf);
- }
- if (index < 0) {
- /* Either pairwise key or address is 00:00:00:00:00:00
- * for transmit-only keys. Search the index. */
- if (b43_new_kidx_api(dev))
- sta_keys_start = 4;
- else
- sta_keys_start = 8;
- for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
- if (!dev->key[i].keyconf) {
- /* found empty */
- index = i;
- break;
- }
- }
- if (index < 0) {
- b43err(dev->wl, "Out of hardware key memory\n");
- return -ENOSPC;
- }
- } else
- B43_WARN_ON(index > 3);
-
- do_key_write(dev, index, algorithm, key, key_len, mac_addr);
- if ((index <= 3) && !b43_new_kidx_api(dev)) {
- /* Default RX key */
- B43_WARN_ON(mac_addr);
- do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
- }
- keyconf->hw_key_idx = index;
- dev->key[index].keyconf = keyconf;
-
- return 0;
-}
-
-static int b43_key_clear(struct b43_wldev *dev, int index)
-{
- if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
- return -EINVAL;
- do_key_write(dev, index, B43_SEC_ALGO_NONE,
- NULL, B43_SEC_KEYSIZE, NULL);
- if ((index <= 3) && !b43_new_kidx_api(dev)) {
- do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
- NULL, B43_SEC_KEYSIZE, NULL);
- }
- dev->key[index].keyconf = NULL;
-
- return 0;
-}
-
-static void b43_clear_keys(struct b43_wldev *dev)
-{
- int i;
-
- for (i = 0; i < dev->max_nr_keys; i++)
- b43_key_clear(dev, i);
-}
-
-void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
-{
- u32 macctl;
- u16 ucstat;
- bool hwps;
- bool awake;
- int i;
-
- B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
- (ps_flags & B43_PS_DISABLED));
- B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
-
- if (ps_flags & B43_PS_ENABLED) {
- hwps = 1;
- } else if (ps_flags & B43_PS_DISABLED) {
- hwps = 0;
- } else {
- //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
- // and thus is not an AP and we are associated, set bit 25
- }
- if (ps_flags & B43_PS_AWAKE) {
- awake = 1;
- } else if (ps_flags & B43_PS_ASLEEP) {
- awake = 0;
- } else {
- //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
- // or we are associated, or FIXME, or the latest PS-Poll packet sent was
- // successful, set bit26
- }
-
-/* FIXME: For now we force awake-on and hwps-off */
- hwps = 0;
- awake = 1;
-
- macctl = b43_read32(dev, B43_MMIO_MACCTL);
- if (hwps)
- macctl |= B43_MACCTL_HWPS;
- else
- macctl &= ~B43_MACCTL_HWPS;
- if (awake)
- macctl |= B43_MACCTL_AWAKE;
- else
- macctl &= ~B43_MACCTL_AWAKE;
- b43_write32(dev, B43_MMIO_MACCTL, macctl);
- /* Commit write */
- b43_read32(dev, B43_MMIO_MACCTL);
- if (awake && dev->dev->id.revision >= 5) {
- /* Wait for the microcode to wake up. */
- for (i = 0; i < 100; i++) {
- ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
- B43_SHM_SH_UCODESTAT);
- if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
- break;
- udelay(10);
- }
- }
-}
-
-/* Turn the Analog ON/OFF */
-static void b43_switch_analog(struct b43_wldev *dev, int on)
-{
- switch (dev->phy.type) {
- case B43_PHYTYPE_A:
- case B43_PHYTYPE_G:
- b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
- break;
- case B43_PHYTYPE_N:
- b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
- on ? 0 : 0x7FFF);
- break;
- default:
- B43_WARN_ON(1);
- }
-}
-
-void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
-{
- u32 tmslow;
- u32 macctl;
-
- flags |= B43_TMSLOW_PHYCLKEN;
- flags |= B43_TMSLOW_PHYRESET;
- ssb_device_enable(dev->dev, flags);
- msleep(2); /* Wait for the PLL to turn on. */
-
- /* Now take the PHY out of Reset again */
- tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
- tmslow |= SSB_TMSLOW_FGC;
- tmslow &= ~B43_TMSLOW_PHYRESET;
- ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
- ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
- msleep(1);
- tmslow &= ~SSB_TMSLOW_FGC;
- ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
- ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
- msleep(1);
-
- /* Turn Analog ON */
- b43_switch_analog(dev, 1);
-
- macctl = b43_read32(dev, B43_MMIO_MACCTL);
- macctl &= ~B43_MACCTL_GMODE;
- if (flags & B43_TMSLOW_GMODE)
- macctl |= B43_MACCTL_GMODE;
- macctl |= B43_MACCTL_IHR_ENABLED;
- b43_write32(dev, B43_MMIO_MACCTL, macctl);
-}
-
-static void handle_irq_transmit_status(struct b43_wldev *dev)
-{
- u32 v0, v1;
- u16 tmp;
- struct b43_txstatus stat;
-
- while (1) {
- v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
- if (!(v0 & 0x00000001))
- break;
- v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
-
- stat.cookie = (v0 >> 16);
- stat.seq = (v1 & 0x0000FFFF);
- stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
- tmp = (v0 & 0x0000FFFF);
- stat.frame_count = ((tmp & 0xF000) >> 12);
- stat.rts_count = ((tmp & 0x0F00) >> 8);
- stat.supp_reason = ((tmp & 0x001C) >> 2);
- stat.pm_indicated = !!(tmp & 0x0080);
- stat.intermediate = !!(tmp & 0x0040);
- stat.for_ampdu = !!(tmp & 0x0020);
- stat.acked = !!(tmp & 0x0002);
-
- b43_handle_txstatus(dev, &stat);
- }
-}
-
-static void drain_txstatus_queue(struct b43_wldev *dev)
-{
- u32 dummy;
-
- if (dev->dev->id.revision < 5)
- return;
- /* Read all entries from the microcode TXstatus FIFO
- * and throw them away.
- */
- while (1) {
- dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
- if (!(dummy & 0x00000001))
- break;
- dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
- }
-}
-
-static u32 b43_jssi_read(struct b43_wldev *dev)
-{
- u32 val = 0;
-
- val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
- val <<= 16;
- val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
-
- return val;
-}
-
-static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
-{
- b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
- b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
-}
-
-static void b43_generate_noise_sample(struct b43_wldev *dev)
-{
- b43_jssi_write(dev, 0x7F7F7F7F);
- b43_write32(dev, B43_MMIO_MACCMD,
- b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
- B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
-}
-
-static void b43_calculate_link_quality(struct b43_wldev *dev)
-{
- /* Top half of Link Quality calculation. */
-
- if (dev->noisecalc.calculation_running)
- return;
- dev->noisecalc.channel_at_start = dev->phy.channel;
- dev->noisecalc.calculation_running = 1;
- dev->noisecalc.nr_samples = 0;
-
- b43_generate_noise_sample(dev);
-}
-
-static void handle_irq_noise(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- u16 tmp;
- u8 noise[4];
- u8 i, j;
- s32 average;
-
- /* Bottom half of Link Quality calculation. */
-
- B43_WARN_ON(!dev->noisecalc.calculation_running);
- if (dev->noisecalc.channel_at_start != phy->channel)
- goto drop_calculation;
- *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
- if (noise[0] == 0x7F || noise[1] == 0x7F ||
- noise[2] == 0x7F || noise[3] == 0x7F)
- goto generate_new;
-
- /* Get the noise samples. */
- B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
- i = dev->noisecalc.nr_samples;
- noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
- noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
- noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
- noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
- dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
- dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
- dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
- dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
- dev->noisecalc.nr_samples++;
- if (dev->noisecalc.nr_samples == 8) {
- /* Calculate the Link Quality by the noise samples. */
- average = 0;
- for (i = 0; i < 8; i++) {
- for (j = 0; j < 4; j++)
- average += dev->noisecalc.samples[i][j];
- }
- average /= (8 * 4);
- average *= 125;
- average += 64;
- average /= 128;
- tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
- tmp = (tmp / 128) & 0x1F;
- if (tmp >= 8)
- average += 2;
- else
- average -= 25;
- if (tmp == 8)
- average -= 72;
- else
- average -= 48;
-
- dev->stats.link_noise = average;
- drop_calculation:
- dev->noisecalc.calculation_running = 0;
- return;
- }
- generate_new:
- b43_generate_noise_sample(dev);
-}
-
-static void handle_irq_tbtt_indication(struct b43_wldev *dev)
-{
- if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
- ///TODO: PS TBTT
- } else {
- if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
- b43_power_saving_ctl_bits(dev, 0);
- }
- if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
- dev->dfq_valid = 1;
-}
-
-static void handle_irq_atim_end(struct b43_wldev *dev)
-{
- if (dev->dfq_valid) {
- b43_write32(dev, B43_MMIO_MACCMD,
- b43_read32(dev, B43_MMIO_MACCMD)
- | B43_MACCMD_DFQ_VALID);
- dev->dfq_valid = 0;
- }
-}
-
-static void handle_irq_pmq(struct b43_wldev *dev)
-{
- u32 tmp;
-
- //TODO: AP mode.
-
- while (1) {
- tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
- if (!(tmp & 0x00000008))
- break;
- }
- /* 16bit write is odd, but correct. */
- b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
-}
-
-static void b43_write_template_common(struct b43_wldev *dev,
- const u8 * data, u16 size,
- u16 ram_offset,
- u16 shm_size_offset, u8 rate)
-{
- u32 i, tmp;
- struct b43_plcp_hdr4 plcp;
-
- plcp.data = 0;
- b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
- b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
- ram_offset += sizeof(u32);
- /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
- * So leave the first two bytes of the next write blank.
- */
- tmp = (u32) (data[0]) << 16;
- tmp |= (u32) (data[1]) << 24;
- b43_ram_write(dev, ram_offset, tmp);
- ram_offset += sizeof(u32);
- for (i = 2; i < size; i += sizeof(u32)) {
- tmp = (u32) (data[i + 0]);
- if (i + 1 < size)
- tmp |= (u32) (data[i + 1]) << 8;
- if (i + 2 < size)
- tmp |= (u32) (data[i + 2]) << 16;
- if (i + 3 < size)
- tmp |= (u32) (data[i + 3]) << 24;
- b43_ram_write(dev, ram_offset + i - 2, tmp);
- }
- b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
- size + sizeof(struct b43_plcp_hdr6));
-}
-
-/* Check if the use of the antenna that ieee80211 told us to
- * use is possible. This will fall back to DEFAULT.
- * "antenna_nr" is the antenna identifier we got from ieee80211. */
-u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
- u8 antenna_nr)
-{
- u8 antenna_mask;
-
- if (antenna_nr == 0) {
- /* Zero means "use default antenna". That's always OK. */
- return 0;
- }
-
- /* Get the mask of available antennas. */
- if (dev->phy.gmode)
- antenna_mask = dev->dev->bus->sprom.ant_available_bg;
- else
- antenna_mask = dev->dev->bus->sprom.ant_available_a;
-
- if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
- /* This antenna is not available. Fall back to default. */
- return 0;
- }
-
- return antenna_nr;
-}
-
-static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
-{
- antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
- switch (antenna) {
- case 0: /* default/diversity */
- return B43_ANTENNA_DEFAULT;
- case 1: /* Antenna 0 */
- return B43_ANTENNA0;
- case 2: /* Antenna 1 */
- return B43_ANTENNA1;
- case 3: /* Antenna 2 */
- return B43_ANTENNA2;
- case 4: /* Antenna 3 */
- return B43_ANTENNA3;
- default:
- return B43_ANTENNA_DEFAULT;
- }
-}
-
-/* Convert a b43 antenna number value to the PHY TX control value. */
-static u16 b43_antenna_to_phyctl(int antenna)
-{
- switch (antenna) {
- case B43_ANTENNA0:
- return B43_TXH_PHY_ANT0;
- case B43_ANTENNA1:
- return B43_TXH_PHY_ANT1;
- case B43_ANTENNA2:
- return B43_TXH_PHY_ANT2;
- case B43_ANTENNA3:
- return B43_TXH_PHY_ANT3;
- case B43_ANTENNA_AUTO:
- return B43_TXH_PHY_ANT01AUTO;
- }
- B43_WARN_ON(1);
- return 0;
-}
-
-static void b43_write_beacon_template(struct b43_wldev *dev,
- u16 ram_offset,
- u16 shm_size_offset)
-{
- unsigned int i, len, variable_len;
- const struct ieee80211_mgmt *bcn;
- const u8 *ie;
- bool tim_found = 0;
- unsigned int rate;
- u16 ctl;
- int antenna;
- struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
-
- bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
- len = min((size_t) dev->wl->current_beacon->len,
- 0x200 - sizeof(struct b43_plcp_hdr6));
- rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
-
- b43_write_template_common(dev, (const u8 *)bcn,
- len, ram_offset, shm_size_offset, rate);
-
- /* Write the PHY TX control parameters. */
- antenna = b43_antenna_from_ieee80211(dev, info->antenna_sel_tx);
- antenna = b43_antenna_to_phyctl(antenna);
- ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
- /* We can't send beacons with short preamble. Would get PHY errors. */
- ctl &= ~B43_TXH_PHY_SHORTPRMBL;
- ctl &= ~B43_TXH_PHY_ANT;
- ctl &= ~B43_TXH_PHY_ENC;
- ctl |= antenna;
- if (b43_is_cck_rate(rate))
- ctl |= B43_TXH_PHY_ENC_CCK;
- else
- ctl |= B43_TXH_PHY_ENC_OFDM;
- b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
-
- /* Find the position of the TIM and the DTIM_period value
- * and write them to SHM. */
- ie = bcn->u.beacon.variable;
- variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
- for (i = 0; i < variable_len - 2; ) {
- uint8_t ie_id, ie_len;
-
- ie_id = ie[i];
- ie_len = ie[i + 1];
- if (ie_id == 5) {
- u16 tim_position;
- u16 dtim_period;
- /* This is the TIM Information Element */
-
- /* Check whether the ie_len is in the beacon data range. */
- if (variable_len < ie_len + 2 + i)
- break;
- /* A valid TIM is at least 4 bytes long. */
- if (ie_len < 4)
- break;
- tim_found = 1;
-
- tim_position = sizeof(struct b43_plcp_hdr6);
- tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
- tim_position += i;
-
- dtim_period = ie[i + 3];
-
- b43_shm_write16(dev, B43_SHM_SHARED,
- B43_SHM_SH_TIMBPOS, tim_position);
- b43_shm_write16(dev, B43_SHM_SHARED,
- B43_SHM_SH_DTIMPER, dtim_period);
- break;
- }
- i += ie_len + 2;
- }
- if (!tim_found) {
- b43warn(dev->wl, "Did not find a valid TIM IE in "
- "the beacon template packet. AP or IBSS operation "
- "may be broken.\n");
- } else
- b43dbg(dev->wl, "Updated beacon template\n");
-}
-
-static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
- u16 shm_offset, u16 size,
- struct ieee80211_rate *rate)
-{
- struct b43_plcp_hdr4 plcp;
- u32 tmp;
- __le16 dur;
-
- plcp.data = 0;
- b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
- dur = ieee80211_generic_frame_duration(dev->wl->hw,
- dev->wl->vif, size,
- rate);
- /* Write PLCP in two parts and timing for packet transfer */
- tmp = le32_to_cpu(plcp.data);
- b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
- b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
- b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
-}
-
-/* Instead of using custom probe response template, this function
- * just patches custom beacon template by:
- * 1) Changing packet type
- * 2) Patching duration field
- * 3) Stripping TIM
- */
-static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
- u16 *dest_size,
- struct ieee80211_rate *rate)
-{
- const u8 *src_data;
- u8 *dest_data;
- u16 src_size, elem_size, src_pos, dest_pos;
- __le16 dur;
- struct ieee80211_hdr *hdr;
- size_t ie_start;
-
- src_size = dev->wl->current_beacon->len;
- src_data = (const u8 *)dev->wl->current_beacon->data;
-
- /* Get the start offset of the variable IEs in the packet. */
- ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
- B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
-
- if (B43_WARN_ON(src_size < ie_start))
- return NULL;
-
- dest_data = kmalloc(src_size, GFP_ATOMIC);
- if (unlikely(!dest_data))
- return NULL;
-
- /* Copy the static data and all Information Elements, except the TIM. */
- memcpy(dest_data, src_data, ie_start);
- src_pos = ie_start;
- dest_pos = ie_start;
- for ( ; src_pos < src_size - 2; src_pos += elem_size) {
- elem_size = src_data[src_pos + 1] + 2;
- if (src_data[src_pos] == 5) {
- /* This is the TIM. */
- continue;
- }
- memcpy(dest_data + dest_pos, src_data + src_pos,
- elem_size);
- dest_pos += elem_size;
- }
- *dest_size = dest_pos;
- hdr = (struct ieee80211_hdr *)dest_data;
-
- /* Set the frame control. */
- hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
- IEEE80211_STYPE_PROBE_RESP);
- dur = ieee80211_generic_frame_duration(dev->wl->hw,
- dev->wl->vif, *dest_size,
- rate);
- hdr->duration_id = dur;
-
- return dest_data;
-}
-
-static void b43_write_probe_resp_template(struct b43_wldev *dev,
- u16 ram_offset,
- u16 shm_size_offset,
- struct ieee80211_rate *rate)
-{
- const u8 *probe_resp_data;
- u16 size;
-
- size = dev->wl->current_beacon->len;
- probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
- if (unlikely(!probe_resp_data))
- return;
-
- /* Looks like PLCP headers plus packet timings are stored for
- * all possible basic rates
- */
- b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]);
- b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]);
- b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]);
- b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]);
-
- size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
- b43_write_template_common(dev, probe_resp_data,
- size, ram_offset, shm_size_offset,
- rate->hw_value);
- kfree(probe_resp_data);
-}
-
-static void handle_irq_beacon(struct b43_wldev *dev)
-{
- struct b43_wl *wl = dev->wl;
- u32 cmd, beacon0_valid, beacon1_valid;
-
- if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
- return;
-
- /* This is the bottom half of the asynchronous beacon update. */
-
- /* Ignore interrupt in the future. */
- dev->irq_savedstate &= ~B43_IRQ_BEACON;
-
- cmd = b43_read32(dev, B43_MMIO_MACCMD);
- beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
- beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
-
- /* Schedule interrupt manually, if busy. */
- if (beacon0_valid && beacon1_valid) {
- b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
- dev->irq_savedstate |= B43_IRQ_BEACON;
- return;
- }
-
- if (!beacon0_valid) {
- if (!wl->beacon0_uploaded) {
- b43_write_beacon_template(dev, 0x68, 0x18);
- b43_write_probe_resp_template(dev, 0x268, 0x4A,
- &__b43_ratetable[3]);
- wl->beacon0_uploaded = 1;
- }
- cmd = b43_read32(dev, B43_MMIO_MACCMD);
- cmd |= B43_MACCMD_BEACON0_VALID;
- b43_write32(dev, B43_MMIO_MACCMD, cmd);
- } else if (!beacon1_valid) {
- if (!wl->beacon1_uploaded) {
- b43_write_beacon_template(dev, 0x468, 0x1A);
- wl->beacon1_uploaded = 1;
- }
- cmd = b43_read32(dev, B43_MMIO_MACCMD);
- cmd |= B43_MACCMD_BEACON1_VALID;
- b43_write32(dev, B43_MMIO_MACCMD, cmd);
- }
-}
-
-static void b43_beacon_update_trigger_work(struct work_struct *work)
-{
- struct b43_wl *wl = container_of(work, struct b43_wl,
- beacon_update_trigger);
- struct b43_wldev *dev;
-
- mutex_lock(&wl->mutex);
- dev = wl->current_dev;
- if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
- spin_lock_irq(&wl->irq_lock);
- /* update beacon right away or defer to irq */
- dev->irq_savedstate = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
- handle_irq_beacon(dev);
- /* The handler might have updated the IRQ mask. */
- b43_write32(dev, B43_MMIO_GEN_IRQ_MASK,
- dev->irq_savedstate);
- mmiowb();
- spin_unlock_irq(&wl->irq_lock);
- }
- mutex_unlock(&wl->mutex);
-}
-
-/* Asynchronously update the packet templates in template RAM.
- * Locking: Requires wl->irq_lock to be locked. */
-static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon)
-{
- /* This is the top half of the ansynchronous beacon update.
- * The bottom half is the beacon IRQ.
- * Beacon update must be asynchronous to avoid sending an
- * invalid beacon. This can happen for example, if the firmware
- * transmits a beacon while we are updating it. */
-
- if (wl->current_beacon)
- dev_kfree_skb_any(wl->current_beacon);
- wl->current_beacon = beacon;
- wl->beacon0_uploaded = 0;
- wl->beacon1_uploaded = 0;
- queue_work(wl->hw->workqueue, &wl->beacon_update_trigger);
-}
-
-static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
-{
- u32 tmp;
- u16 i, len;
-
- len = min((u16) ssid_len, (u16) 0x100);
- for (i = 0; i < len; i += sizeof(u32)) {
- tmp = (u32) (ssid[i + 0]);
- if (i + 1 < len)
- tmp |= (u32) (ssid[i + 1]) << 8;
- if (i + 2 < len)
- tmp |= (u32) (ssid[i + 2]) << 16;
- if (i + 3 < len)
- tmp |= (u32) (ssid[i + 3]) << 24;
- b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
- }
- b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
-}
-
-static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
-{
- b43_time_lock(dev);
- if (dev->dev->id.revision >= 3) {
- b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
- b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
- } else {
- b43_write16(dev, 0x606, (beacon_int >> 6));
- b43_write16(dev, 0x610, beacon_int);
- }
- b43_time_unlock(dev);
- b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
-}
-
-static void b43_handle_firmware_panic(struct b43_wldev *dev)
-{
- u16 reason;
-
- /* Read the register that contains the reason code for the panic. */
- reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
- b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
-
- switch (reason) {
- default:
- b43dbg(dev->wl, "The panic reason is unknown.\n");
- /* fallthrough */
- case B43_FWPANIC_DIE:
- /* Do not restart the controller or firmware.
- * The device is nonfunctional from now on.
- * Restarting would result in this panic to trigger again,
- * so we avoid that recursion. */
- break;
- case B43_FWPANIC_RESTART:
- b43_controller_restart(dev, "Microcode panic");
- break;
- }
-}
-
-static void handle_irq_ucode_debug(struct b43_wldev *dev)
-{
- unsigned int i, cnt;
- u16 reason, marker_id, marker_line;
- __le16 *buf;
-
- /* The proprietary firmware doesn't have this IRQ. */
- if (!dev->fw.opensource)
- return;
-
- /* Read the register that contains the reason code for this IRQ. */
- reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
-
- switch (reason) {
- case B43_DEBUGIRQ_PANIC:
- b43_handle_firmware_panic(dev);
- break;
- case B43_DEBUGIRQ_DUMP_SHM:
- if (!B43_DEBUG)
- break; /* Only with driver debugging enabled. */
- buf = kmalloc(4096, GFP_ATOMIC);
- if (!buf) {
- b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
- goto out;
- }
- for (i = 0; i < 4096; i += 2) {
- u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
- buf[i / 2] = cpu_to_le16(tmp);
- }
- b43info(dev->wl, "Shared memory dump:\n");
- print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
- 16, 2, buf, 4096, 1);
- kfree(buf);
- break;
- case B43_DEBUGIRQ_DUMP_REGS:
- if (!B43_DEBUG)
- break; /* Only with driver debugging enabled. */
- b43info(dev->wl, "Microcode register dump:\n");
- for (i = 0, cnt = 0; i < 64; i++) {
- u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
- if (cnt == 0)
- printk(KERN_INFO);
- printk("r%02u: 0x%04X ", i, tmp);
- cnt++;
- if (cnt == 6) {
- printk("\n");
- cnt = 0;
- }
- }
- printk("\n");
- break;
- case B43_DEBUGIRQ_MARKER:
- if (!B43_DEBUG)
- break; /* Only with driver debugging enabled. */
- marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
- B43_MARKER_ID_REG);
- marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
- B43_MARKER_LINE_REG);
- b43info(dev->wl, "The firmware just executed the MARKER(%u) "
- "at line number %u\n",
- marker_id, marker_line);
- break;
- default:
- b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
- reason);
- }
-out:
- /* Acknowledge the debug-IRQ, so the firmware can continue. */
- b43_shm_write16(dev, B43_SHM_SCRATCH,
- B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
-}
-
-/* Interrupt handler bottom-half */
-static void b43_interrupt_tasklet(struct b43_wldev *dev)
-{
- u32 reason;
- u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
- u32 merged_dma_reason = 0;
- int i;
- unsigned long flags;
-
- spin_lock_irqsave(&dev->wl->irq_lock, flags);
-
- B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
-
- reason = dev->irq_reason;
- for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
- dma_reason[i] = dev->dma_reason[i];
- merged_dma_reason |= dma_reason[i];
- }
-
- if (unlikely(reason & B43_IRQ_MAC_TXERR))
- b43err(dev->wl, "MAC transmission error\n");
-
- if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
- b43err(dev->wl, "PHY transmission error\n");
- rmb();
- if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
- atomic_set(&dev->phy.txerr_cnt,
- B43_PHY_TX_BADNESS_LIMIT);
- b43err(dev->wl, "Too many PHY TX errors, "
- "restarting the controller\n");
- b43_controller_restart(dev, "PHY TX errors");
- }
- }
-
- if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
- B43_DMAIRQ_NONFATALMASK))) {
- if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
- b43err(dev->wl, "Fatal DMA error: "
- "0x%08X, 0x%08X, 0x%08X, "
- "0x%08X, 0x%08X, 0x%08X\n",
- dma_reason[0], dma_reason[1],
- dma_reason[2], dma_reason[3],
- dma_reason[4], dma_reason[5]);
- b43_controller_restart(dev, "DMA error");
- mmiowb();
- spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
- return;
- }
- if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
- b43err(dev->wl, "DMA error: "
- "0x%08X, 0x%08X, 0x%08X, "
- "0x%08X, 0x%08X, 0x%08X\n",
- dma_reason[0], dma_reason[1],
- dma_reason[2], dma_reason[3],
- dma_reason[4], dma_reason[5]);
- }
- }
-
- if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
- handle_irq_ucode_debug(dev);
- if (reason & B43_IRQ_TBTT_INDI)
- handle_irq_tbtt_indication(dev);
- if (reason & B43_IRQ_ATIM_END)
- handle_irq_atim_end(dev);
- if (reason & B43_IRQ_BEACON)
- handle_irq_beacon(dev);
- if (reason & B43_IRQ_PMQ)
- handle_irq_pmq(dev);
- if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
- ;/* TODO */
- if (reason & B43_IRQ_NOISESAMPLE_OK)
- handle_irq_noise(dev);
-
- /* Check the DMA reason registers for received data. */
- if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
- if (b43_using_pio_transfers(dev))
- b43_pio_rx(dev->pio.rx_queue);
- else
- b43_dma_rx(dev->dma.rx_ring);
- }
- B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
- B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
- B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
- B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
- B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
-
- if (reason & B43_IRQ_TX_OK)
- handle_irq_transmit_status(dev);
-
- b43_interrupt_enable(dev, dev->irq_savedstate);
- mmiowb();
- spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
-}
-
-static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
-{
- b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
-
- b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
- b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
- b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
- b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
- b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
- b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
-}
-
-/* Interrupt handler top-half */
-static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
-{
- irqreturn_t ret = IRQ_NONE;
- struct b43_wldev *dev = dev_id;
- u32 reason;
-
- if (!dev)
- return IRQ_NONE;
-
- spin_lock(&dev->wl->irq_lock);
-
- if (b43_status(dev) < B43_STAT_STARTED)
- goto out;
- reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
- if (reason == 0xffffffff) /* shared IRQ */
- goto out;
- ret = IRQ_HANDLED;
- reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
- if (!reason)
- goto out;
-
- dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
- & 0x0001DC00;
- dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
- & 0x0000DC00;
- dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
- & 0x0000DC00;
- dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
- & 0x0001DC00;
- dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
- & 0x0000DC00;
- dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
- & 0x0000DC00;
-
- b43_interrupt_ack(dev, reason);
- /* disable all IRQs. They are enabled again in the bottom half. */
- dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
- /* save the reason code and call our bottom half. */
- dev->irq_reason = reason;
- tasklet_schedule(&dev->isr_tasklet);
- out:
- mmiowb();
- spin_unlock(&dev->wl->irq_lock);
-
- return ret;
-}
-
-static void do_release_fw(struct b43_firmware_file *fw)
-{
- release_firmware(fw->data);
- fw->data = NULL;
- fw->filename = NULL;
-}
-
-static void b43_release_firmware(struct b43_wldev *dev)
-{
- do_release_fw(&dev->fw.ucode);
- do_release_fw(&dev->fw.pcm);
- do_release_fw(&dev->fw.initvals);
- do_release_fw(&dev->fw.initvals_band);
-}
-
-static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
-{
- const char *text;
-
- text = "You must go to "
- "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
- "and download the latest firmware (version 4).\n";
- if (error)
- b43err(wl, text);
- else
- b43warn(wl, text);
-}
-
-static int do_request_fw(struct b43_wldev *dev,
- const char *name,
- struct b43_firmware_file *fw,
- bool silent)
-{
- char path[sizeof(modparam_fwpostfix) + 32];
- const struct firmware *blob;
- struct b43_fw_header *hdr;
- u32 size;
- int err;
-
- if (!name) {
- /* Don't fetch anything. Free possibly cached firmware. */
- do_release_fw(fw);
- return 0;
- }
- if (fw->filename) {
- if (strcmp(fw->filename, name) == 0)
- return 0; /* Already have this fw. */
- /* Free the cached firmware first. */
- do_release_fw(fw);
- }
-
- snprintf(path, ARRAY_SIZE(path),
- "b43%s/%s.fw",
- modparam_fwpostfix, name);
- err = request_firmware(&blob, path, dev->dev->dev);
- if (err == -ENOENT) {
- if (!silent) {
- b43err(dev->wl, "Firmware file \"%s\" not found\n",
- path);
- }
- return err;
- } else if (err) {
- b43err(dev->wl, "Firmware file \"%s\" request failed (err=%d)\n",
- path, err);
- return err;
- }
- if (blob->size < sizeof(struct b43_fw_header))
- goto err_format;
- hdr = (struct b43_fw_header *)(blob->data);
- switch (hdr->type) {
- case B43_FW_TYPE_UCODE:
- case B43_FW_TYPE_PCM:
- size = be32_to_cpu(hdr->size);
- if (size != blob->size - sizeof(struct b43_fw_header))
- goto err_format;
- /* fallthrough */
- case B43_FW_TYPE_IV:
- if (hdr->ver != 1)
- goto err_format;
- break;
- default:
- goto err_format;
- }
-
- fw->data = blob;
- fw->filename = name;
-
- return 0;
-
-err_format:
- b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
- release_firmware(blob);
-
- return -EPROTO;
-}
-
-static int b43_request_firmware(struct b43_wldev *dev)
-{
- struct b43_firmware *fw = &dev->fw;
- const u8 rev = dev->dev->id.revision;
- const char *filename;
- u32 tmshigh;
- int err;
-
- /* Get microcode */
- tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
- if ((rev >= 5) && (rev <= 10))
- filename = "ucode5";
- else if ((rev >= 11) && (rev <= 12))
- filename = "ucode11";
- else if (rev >= 13)
- filename = "ucode13";
- else
- goto err_no_ucode;
- err = do_request_fw(dev, filename, &fw->ucode, 0);
- if (err)
- goto err_load;
-
- /* Get PCM code */
- if ((rev >= 5) && (rev <= 10))
- filename = "pcm5";
- else if (rev >= 11)
- filename = NULL;
- else
- goto err_no_pcm;
- fw->pcm_request_failed = 0;
- err = do_request_fw(dev, filename, &fw->pcm, 1);
- if (err == -ENOENT) {
- /* We did not find a PCM file? Not fatal, but
- * core rev <= 10 must do without hwcrypto then. */
- fw->pcm_request_failed = 1;
- } else if (err)
- goto err_load;
-
- /* Get initvals */
- switch (dev->phy.type) {
- case B43_PHYTYPE_A:
- if ((rev >= 5) && (rev <= 10)) {
- if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
- filename = "a0g1initvals5";
- else
- filename = "a0g0initvals5";
- } else
- goto err_no_initvals;
- break;
- case B43_PHYTYPE_G:
- if ((rev >= 5) && (rev <= 10))
- filename = "b0g0initvals5";
- else if (rev >= 13)
- filename = "b0g0initvals13";
- else
- goto err_no_initvals;
- break;
- case B43_PHYTYPE_N:
- if ((rev >= 11) && (rev <= 12))
- filename = "n0initvals11";
- else
- goto err_no_initvals;
- break;
- default:
- goto err_no_initvals;
- }
- err = do_request_fw(dev, filename, &fw->initvals, 0);
- if (err)
- goto err_load;
-
- /* Get bandswitch initvals */
- switch (dev->phy.type) {
- case B43_PHYTYPE_A:
- if ((rev >= 5) && (rev <= 10)) {
- if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
- filename = "a0g1bsinitvals5";
- else
- filename = "a0g0bsinitvals5";
- } else if (rev >= 11)
- filename = NULL;
- else
- goto err_no_initvals;
- break;
- case B43_PHYTYPE_G:
- if ((rev >= 5) && (rev <= 10))
- filename = "b0g0bsinitvals5";
- else if (rev >= 11)
- filename = NULL;
- else
- goto err_no_initvals;
- break;
- case B43_PHYTYPE_N:
- if ((rev >= 11) && (rev <= 12))
- filename = "n0bsinitvals11";
- else
- goto err_no_initvals;
- break;
- default:
- goto err_no_initvals;
- }
- err = do_request_fw(dev, filename, &fw->initvals_band, 0);
- if (err)
- goto err_load;
-
- return 0;
-
-err_load:
- b43_print_fw_helptext(dev->wl, 1);
- goto error;
-
-err_no_ucode:
- err = -ENODEV;
- b43err(dev->wl, "No microcode available for core rev %u\n", rev);
- goto error;
-
-err_no_pcm:
- err = -ENODEV;
- b43err(dev->wl, "No PCM available for core rev %u\n", rev);
- goto error;
-
-err_no_initvals:
- err = -ENODEV;
- b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
- "core rev %u\n", dev->phy.type, rev);
- goto error;
-
-error:
- b43_release_firmware(dev);
- return err;
-}
-
-static int b43_upload_microcode(struct b43_wldev *dev)
-{
- const size_t hdr_len = sizeof(struct b43_fw_header);
- const __be32 *data;
- unsigned int i, len;
- u16 fwrev, fwpatch, fwdate, fwtime;
- u32 tmp, macctl;
- int err = 0;
-
- /* Jump the microcode PSM to offset 0 */
- macctl = b43_read32(dev, B43_MMIO_MACCTL);
- B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
- macctl |= B43_MACCTL_PSM_JMP0;
- b43_write32(dev, B43_MMIO_MACCTL, macctl);
- /* Zero out all microcode PSM registers and shared memory. */
- for (i = 0; i < 64; i++)
- b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
- for (i = 0; i < 4096; i += 2)
- b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
-
- /* Upload Microcode. */
- data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
- len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
- b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
- for (i = 0; i < len; i++) {
- b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
- udelay(10);
- }
-
- if (dev->fw.pcm.data) {
- /* Upload PCM data. */
- data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
- len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
- b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
- b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
- /* No need for autoinc bit in SHM_HW */
- b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
- for (i = 0; i < len; i++) {
- b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
- udelay(10);
- }
- }
-
- b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
-
- /* Start the microcode PSM */
- macctl = b43_read32(dev, B43_MMIO_MACCTL);
- macctl &= ~B43_MACCTL_PSM_JMP0;
- macctl |= B43_MACCTL_PSM_RUN;
- b43_write32(dev, B43_MMIO_MACCTL, macctl);
-
- /* Wait for the microcode to load and respond */
- i = 0;
- while (1) {
- tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
- if (tmp == B43_IRQ_MAC_SUSPENDED)
- break;
- i++;
- if (i >= 20) {
- b43err(dev->wl, "Microcode not responding\n");
- b43_print_fw_helptext(dev->wl, 1);
- err = -ENODEV;
- goto error;
- }
- msleep_interruptible(50);
- if (signal_pending(current)) {
- err = -EINTR;
- goto error;
- }
- }
- b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
-
- /* Get and check the revisions. */
- fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
- fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
- fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
- fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
-
- if (fwrev <= 0x128) {
- b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
- "binary drivers older than version 4.x is unsupported. "
- "You must upgrade your firmware files.\n");
- b43_print_fw_helptext(dev->wl, 1);
- err = -EOPNOTSUPP;
- goto error;
- }
- dev->fw.rev = fwrev;
- dev->fw.patch = fwpatch;
- dev->fw.opensource = (fwdate == 0xFFFF);
-
- if (dev->fw.opensource) {
- /* Patchlevel info is encoded in the "time" field. */
- dev->fw.patch = fwtime;
- b43info(dev->wl, "Loading OpenSource firmware version %u.%u%s\n",
- dev->fw.rev, dev->fw.patch,
- dev->fw.pcm_request_failed ? " (Hardware crypto not supported)" : "");
- } else {
- b43info(dev->wl, "Loading firmware version %u.%u "
- "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
- fwrev, fwpatch,
- (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
- (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
- if (dev->fw.pcm_request_failed) {
- b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
- "Hardware accelerated cryptography is disabled.\n");
- b43_print_fw_helptext(dev->wl, 0);
- }
- }
-
- if (b43_is_old_txhdr_format(dev)) {
- b43warn(dev->wl, "You are using an old firmware image. "
- "Support for old firmware will be removed in July 2008.\n");
- b43_print_fw_helptext(dev->wl, 0);
- }
-
- return 0;
-
-error:
- macctl = b43_read32(dev, B43_MMIO_MACCTL);
- macctl &= ~B43_MACCTL_PSM_RUN;
- macctl |= B43_MACCTL_PSM_JMP0;
- b43_write32(dev, B43_MMIO_MACCTL, macctl);
-
- return err;
-}
-
-static int b43_write_initvals(struct b43_wldev *dev,
- const struct b43_iv *ivals,
- size_t count,
- size_t array_size)
-{
- const struct b43_iv *iv;
- u16 offset;
- size_t i;
- bool bit32;
-
- BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
- iv = ivals;
- for (i = 0; i < count; i++) {
- if (array_size < sizeof(iv->offset_size))
- goto err_format;
- array_size -= sizeof(iv->offset_size);
- offset = be16_to_cpu(iv->offset_size);
- bit32 = !!(offset & B43_IV_32BIT);
- offset &= B43_IV_OFFSET_MASK;
- if (offset >= 0x1000)
- goto err_format;
- if (bit32) {
- u32 value;
-
- if (array_size < sizeof(iv->data.d32))
- goto err_format;
- array_size -= sizeof(iv->data.d32);
-
- value = get_unaligned_be32(&iv->data.d32);
- b43_write32(dev, offset, value);
-
- iv = (const struct b43_iv *)((const uint8_t *)iv +
- sizeof(__be16) +
- sizeof(__be32));
- } else {
- u16 value;
-
- if (array_size < sizeof(iv->data.d16))
- goto err_format;
- array_size -= sizeof(iv->data.d16);
-
- value = be16_to_cpu(iv->data.d16);
- b43_write16(dev, offset, value);
-
- iv = (const struct b43_iv *)((const uint8_t *)iv +
- sizeof(__be16) +
- sizeof(__be16));
- }
- }
- if (array_size)
- goto err_format;
-
- return 0;
-
-err_format:
- b43err(dev->wl, "Initial Values Firmware file-format error.\n");
- b43_print_fw_helptext(dev->wl, 1);
-
- return -EPROTO;
-}
-
-static int b43_upload_initvals(struct b43_wldev *dev)
-{
- const size_t hdr_len = sizeof(struct b43_fw_header);
- const struct b43_fw_header *hdr;
- struct b43_firmware *fw = &dev->fw;
- const struct b43_iv *ivals;
- size_t count;
- int err;
-
- hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
- ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
- count = be32_to_cpu(hdr->size);
- err = b43_write_initvals(dev, ivals, count,
- fw->initvals.data->size - hdr_len);
- if (err)
- goto out;
- if (fw->initvals_band.data) {
- hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
- ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
- count = be32_to_cpu(hdr->size);
- err = b43_write_initvals(dev, ivals, count,
- fw->initvals_band.data->size - hdr_len);
- if (err)
- goto out;
- }
-out:
-
- return err;
-}
-
-/* Initialize the GPIOs
- * http://bcm-specs.sipsolutions.net/GPIO
- */
-static int b43_gpio_init(struct b43_wldev *dev)
-{
- struct ssb_bus *bus = dev->dev->bus;
- struct ssb_device *gpiodev, *pcidev = NULL;
- u32 mask, set;
-
- b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
- & ~B43_MACCTL_GPOUTSMSK);
-
- b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
- | 0x000F);
-
- mask = 0x0000001F;
- set = 0x0000000F;
- if (dev->dev->bus->chip_id == 0x4301) {
- mask |= 0x0060;
- set |= 0x0060;
- }
- if (0 /* FIXME: conditional unknown */ ) {
- b43_write16(dev, B43_MMIO_GPIO_MASK,
- b43_read16(dev, B43_MMIO_GPIO_MASK)
- | 0x0100);
- mask |= 0x0180;
- set |= 0x0180;
- }
- if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
- b43_write16(dev, B43_MMIO_GPIO_MASK,
- b43_read16(dev, B43_MMIO_GPIO_MASK)
- | 0x0200);
- mask |= 0x0200;
- set |= 0x0200;
- }
- if (dev->dev->id.revision >= 2)
- mask |= 0x0010; /* FIXME: This is redundant. */
-
-#ifdef CONFIG_SSB_DRIVER_PCICORE
- pcidev = bus->pcicore.dev;
-#endif
- gpiodev = bus->chipco.dev ? : pcidev;
- if (!gpiodev)
- return 0;
- ssb_write32(gpiodev, B43_GPIO_CONTROL,
- (ssb_read32(gpiodev, B43_GPIO_CONTROL)
- & mask) | set);
-
- return 0;
-}
-
-/* Turn off all GPIO stuff. Call this on module unload, for example. */
-static void b43_gpio_cleanup(struct b43_wldev *dev)
-{
- struct ssb_bus *bus = dev->dev->bus;
- struct ssb_device *gpiodev, *pcidev = NULL;
-
-#ifdef CONFIG_SSB_DRIVER_PCICORE
- pcidev = bus->pcicore.dev;
-#endif
- gpiodev = bus->chipco.dev ? : pcidev;
- if (!gpiodev)
- return;
- ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
-}
-
-/* http://bcm-specs.sipsolutions.net/EnableMac */
-void b43_mac_enable(struct b43_wldev *dev)
-{
- dev->mac_suspended--;
- B43_WARN_ON(dev->mac_suspended < 0);
- if (dev->mac_suspended == 0) {
- b43_write32(dev, B43_MMIO_MACCTL,
- b43_read32(dev, B43_MMIO_MACCTL)
- | B43_MACCTL_ENABLED);
- b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
- B43_IRQ_MAC_SUSPENDED);
- /* Commit writes */
- b43_read32(dev, B43_MMIO_MACCTL);
- b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
- b43_power_saving_ctl_bits(dev, 0);
- }
-}
-
-/* http://bcm-specs.sipsolutions.net/SuspendMAC */
-void b43_mac_suspend(struct b43_wldev *dev)
-{
- int i;
- u32 tmp;
-
- might_sleep();
- B43_WARN_ON(dev->mac_suspended < 0);
-
- if (dev->mac_suspended == 0) {
- b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
- b43_write32(dev, B43_MMIO_MACCTL,
- b43_read32(dev, B43_MMIO_MACCTL)
- & ~B43_MACCTL_ENABLED);
- /* force pci to flush the write */
- b43_read32(dev, B43_MMIO_MACCTL);
- for (i = 35; i; i--) {
- tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
- if (tmp & B43_IRQ_MAC_SUSPENDED)
- goto out;
- udelay(10);
- }
- /* Hm, it seems this will take some time. Use msleep(). */
- for (i = 40; i; i--) {
- tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
- if (tmp & B43_IRQ_MAC_SUSPENDED)
- goto out;
- msleep(1);
- }
- b43err(dev->wl, "MAC suspend failed\n");
- }
-out:
- dev->mac_suspended++;
-}
-
-static void b43_adjust_opmode(struct b43_wldev *dev)
-{
- struct b43_wl *wl = dev->wl;
- u32 ctl;
- u16 cfp_pretbtt;
-
- ctl = b43_read32(dev, B43_MMIO_MACCTL);
- /* Reset status to STA infrastructure mode. */
- ctl &= ~B43_MACCTL_AP;
- ctl &= ~B43_MACCTL_KEEP_CTL;
- ctl &= ~B43_MACCTL_KEEP_BADPLCP;
- ctl &= ~B43_MACCTL_KEEP_BAD;
- ctl &= ~B43_MACCTL_PROMISC;
- ctl &= ~B43_MACCTL_BEACPROMISC;
- ctl |= B43_MACCTL_INFRA;
-
- if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
- ctl |= B43_MACCTL_AP;
- else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
- ctl &= ~B43_MACCTL_INFRA;
-
- if (wl->filter_flags & FIF_CONTROL)
- ctl |= B43_MACCTL_KEEP_CTL;
- if (wl->filter_flags & FIF_FCSFAIL)
- ctl |= B43_MACCTL_KEEP_BAD;
- if (wl->filter_flags & FIF_PLCPFAIL)
- ctl |= B43_MACCTL_KEEP_BADPLCP;
- if (wl->filter_flags & FIF_PROMISC_IN_BSS)
- ctl |= B43_MACCTL_PROMISC;
- if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
- ctl |= B43_MACCTL_BEACPROMISC;
-
- /* Workaround: On old hardware the HW-MAC-address-filter
- * doesn't work properly, so always run promisc in filter
- * it in software. */
- if (dev->dev->id.revision <= 4)
- ctl |= B43_MACCTL_PROMISC;
-
- b43_write32(dev, B43_MMIO_MACCTL, ctl);
-
- cfp_pretbtt = 2;
- if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
- if (dev->dev->bus->chip_id == 0x4306 &&
- dev->dev->bus->chip_rev == 3)
- cfp_pretbtt = 100;
- else
- cfp_pretbtt = 50;
- }
- b43_write16(dev, 0x612, cfp_pretbtt);
-}
-
-static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
-{
- u16 offset;
-
- if (is_ofdm) {
- offset = 0x480;
- offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
- } else {
- offset = 0x4C0;
- offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
- }
- b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
- b43_shm_read16(dev, B43_SHM_SHARED, offset));
-}
-
-static void b43_rate_memory_init(struct b43_wldev *dev)
-{
- switch (dev->phy.type) {
- case B43_PHYTYPE_A:
- case B43_PHYTYPE_G:
- case B43_PHYTYPE_N:
- b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
- b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
- b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
- b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
- b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
- b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
- b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
- if (dev->phy.type == B43_PHYTYPE_A)
- break;
- /* fallthrough */
- case B43_PHYTYPE_B:
- b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
- b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
- b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
- b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
- break;
- default:
- B43_WARN_ON(1);
- }
-}
-
-/* Set the default values for the PHY TX Control Words. */
-static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
-{
- u16 ctl = 0;
-
- ctl |= B43_TXH_PHY_ENC_CCK;
- ctl |= B43_TXH_PHY_ANT01AUTO;
- ctl |= B43_TXH_PHY_TXPWR;
-
- b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
- b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
- b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
-}
-
-/* Set the TX-Antenna for management frames sent by firmware. */
-static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
-{
- u16 ant;
- u16 tmp;
-
- ant = b43_antenna_to_phyctl(antenna);
-
- /* For ACK/CTS */
- tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
- tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
- b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
- /* For Probe Resposes */
- tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
- tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
- b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
-}
-
-/* This is the opposite of b43_chip_init() */
-static void b43_chip_exit(struct b43_wldev *dev)
-{
- b43_radio_turn_off(dev, 1);
- b43_gpio_cleanup(dev);
- b43_lo_g_cleanup(dev);
- /* firmware is released later */
-}
-
-/* Initialize the chip
- * http://bcm-specs.sipsolutions.net/ChipInit
- */
-static int b43_chip_init(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- int err, tmp;
- u32 value32, macctl;
- u16 value16;
-
- /* Initialize the MAC control */
- macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
- if (dev->phy.gmode)
- macctl |= B43_MACCTL_GMODE;
- macctl |= B43_MACCTL_INFRA;
- b43_write32(dev, B43_MMIO_MACCTL, macctl);
-
- err = b43_request_firmware(dev);
- if (err)
- goto out;
- err = b43_upload_microcode(dev);
- if (err)
- goto out; /* firmware is released later */
-
- err = b43_gpio_init(dev);
- if (err)
- goto out; /* firmware is released later */
-
- err = b43_upload_initvals(dev);
- if (err)
- goto err_gpio_clean;
- b43_radio_turn_on(dev);
-
- b43_write16(dev, 0x03E6, 0x0000);
- err = b43_phy_init(dev);
- if (err)
- goto err_radio_off;
-
- /* Select initial Interference Mitigation. */
- tmp = phy->interfmode;
- phy->interfmode = B43_INTERFMODE_NONE;
- b43_radio_set_interference_mitigation(dev, tmp);
-
- b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
- b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
-
- if (phy->type == B43_PHYTYPE_B) {
- value16 = b43_read16(dev, 0x005E);
- value16 |= 0x0004;
- b43_write16(dev, 0x005E, value16);
- }
- b43_write32(dev, 0x0100, 0x01000000);
- if (dev->dev->id.revision < 5)
- b43_write32(dev, 0x010C, 0x01000000);
-
- b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
- & ~B43_MACCTL_INFRA);
- b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
- | B43_MACCTL_INFRA);
-
- /* Probe Response Timeout value */
- /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
- b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
-
- /* Initially set the wireless operation mode. */
- b43_adjust_opmode(dev);
-
- if (dev->dev->id.revision < 3) {
- b43_write16(dev, 0x060E, 0x0000);
- b43_write16(dev, 0x0610, 0x8000);
- b43_write16(dev, 0x0604, 0x0000);
- b43_write16(dev, 0x0606, 0x0200);
- } else {
- b43_write32(dev, 0x0188, 0x80000000);
- b43_write32(dev, 0x018C, 0x02000000);
- }
- b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
- b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
- b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
- b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
- b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
- b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
- b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
-
- value32 = ssb_read32(dev->dev, SSB_TMSLOW);
- value32 |= 0x00100000;
- ssb_write32(dev->dev, SSB_TMSLOW, value32);
-
- b43_write16(dev, B43_MMIO_POWERUP_DELAY,
- dev->dev->bus->chipco.fast_pwrup_delay);
-
- err = 0;
- b43dbg(dev->wl, "Chip initialized\n");
-out:
- return err;
-
-err_radio_off:
- b43_radio_turn_off(dev, 1);
-err_gpio_clean:
- b43_gpio_cleanup(dev);
- return err;
-}
-
-static void b43_periodic_every60sec(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
-
- if (phy->type != B43_PHYTYPE_G)
- return;
- if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
- b43_mac_suspend(dev);
- b43_calc_nrssi_slope(dev);
- if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
- u8 old_chan = phy->channel;
-
- /* VCO Calibration */
- if (old_chan >= 8)
- b43_radio_selectchannel(dev, 1, 0);
- else
- b43_radio_selectchannel(dev, 13, 0);
- b43_radio_selectchannel(dev, old_chan, 0);
- }
- b43_mac_enable(dev);
- }
-}
-
-static void b43_periodic_every30sec(struct b43_wldev *dev)
-{
- /* Update device statistics. */
- b43_calculate_link_quality(dev);
-}
-
-static void b43_periodic_every15sec(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
-
- if (phy->type == B43_PHYTYPE_G) {
- //TODO: update_aci_moving_average
- if (phy->aci_enable && phy->aci_wlan_automatic) {
- b43_mac_suspend(dev);
- if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
- if (0 /*TODO: bunch of conditions */ ) {
- b43_radio_set_interference_mitigation
- (dev, B43_INTERFMODE_MANUALWLAN);
- }
- } else if (1 /*TODO*/) {
- /*
- if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
- b43_radio_set_interference_mitigation(dev,
- B43_INTERFMODE_NONE);
- }
- */
- }
- b43_mac_enable(dev);
- } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
- phy->rev == 1) {
- //TODO: implement rev1 workaround
- }
- }
- b43_phy_xmitpower(dev); //FIXME: unless scanning?
- b43_lo_g_maintanance_work(dev);
- //TODO for APHY (temperature?)
-
- atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
- wmb();
-}
-
-static void do_periodic_work(struct b43_wldev *dev)
-{
- unsigned int state;
-
- state = dev->periodic_state;
- if (state % 4 == 0)
- b43_periodic_every60sec(dev);
- if (state % 2 == 0)
- b43_periodic_every30sec(dev);
- b43_periodic_every15sec(dev);
-}
-
-/* Periodic work locking policy:
- * The whole periodic work handler is protected by
- * wl->mutex. If another lock is needed somewhere in the
- * pwork callchain, it's aquired in-place, where it's needed.
- */
-static void b43_periodic_work_handler(struct work_struct *work)
-{
- struct b43_wldev *dev = container_of(work, struct b43_wldev,
- periodic_work.work);
- struct b43_wl *wl = dev->wl;
- unsigned long delay;
-
- mutex_lock(&wl->mutex);
-
- if (unlikely(b43_status(dev) != B43_STAT_STARTED))
- goto out;
- if (b43_debug(dev, B43_DBG_PWORK_STOP))
- goto out_requeue;
-
- do_periodic_work(dev);
-
- dev->periodic_state++;
-out_requeue:
- if (b43_debug(dev, B43_DBG_PWORK_FAST))
- delay = msecs_to_jiffies(50);
- else
- delay = round_jiffies_relative(HZ * 15);
- queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
-out:
- mutex_unlock(&wl->mutex);
-}
-
-static void b43_periodic_tasks_setup(struct b43_wldev *dev)
-{
- struct delayed_work *work = &dev->periodic_work;
-
- dev->periodic_state = 0;
- INIT_DELAYED_WORK(work, b43_periodic_work_handler);
- queue_delayed_work(dev->wl->hw->workqueue, work, 0);
-}
-
-/* Check if communication with the device works correctly. */
-static int b43_validate_chipaccess(struct b43_wldev *dev)
-{
- u32 v, backup;
-
- backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
-
- /* Check for read/write and endianness problems. */
- b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
- if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
- goto error;
- b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
- if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
- goto error;
-
- b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
-
- if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
- /* The 32bit register shadows the two 16bit registers
- * with update sideeffects. Validate this. */
- b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
- b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
- if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
- goto error;
- if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
- goto error;
- }
- b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
-
- v = b43_read32(dev, B43_MMIO_MACCTL);
- v |= B43_MACCTL_GMODE;
- if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
- goto error;
-
- return 0;
-error:
- b43err(dev->wl, "Failed to validate the chipaccess\n");
- return -ENODEV;
-}
-
-static void b43_security_init(struct b43_wldev *dev)
-{
- dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
- B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
- dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
- /* KTP is a word address, but we address SHM bytewise.
- * So multiply by two.
- */
- dev->ktp *= 2;
- if (dev->dev->id.revision >= 5) {
- /* Number of RCMTA address slots */
- b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
- }
- b43_clear_keys(dev);
-}
-
-static int b43_rng_read(struct hwrng *rng, u32 * data)
-{
- struct b43_wl *wl = (struct b43_wl *)rng->priv;
- unsigned long flags;
-
- /* Don't take wl->mutex here, as it could deadlock with
- * hwrng internal locking. It's not needed to take
- * wl->mutex here, anyway. */
-
- spin_lock_irqsave(&wl->irq_lock, flags);
- *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
- spin_unlock_irqrestore(&wl->irq_lock, flags);
-
- return (sizeof(u16));
-}
-
-static void b43_rng_exit(struct b43_wl *wl)
-{
- if (wl->rng_initialized)
- hwrng_unregister(&wl->rng);
-}
-
-static int b43_rng_init(struct b43_wl *wl)
-{
- int err;
-
- snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
- "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
- wl->rng.name = wl->rng_name;
- wl->rng.data_read = b43_rng_read;
- wl->rng.priv = (unsigned long)wl;
- wl->rng_initialized = 1;
- err = hwrng_register(&wl->rng);
- if (err) {
- wl->rng_initialized = 0;
- b43err(wl, "Failed to register the random "
- "number generator (%d)\n", err);
- }
-
- return err;
-}
-
-static int b43_op_tx(struct ieee80211_hw *hw,
- struct sk_buff *skb)
-{
- struct b43_wl *wl = hw_to_b43_wl(hw);
- struct b43_wldev *dev = wl->current_dev;
- unsigned long flags;
- int err;
-
- if (unlikely(skb->len < 2 + 2 + 6)) {
- /* Too short, this can't be a valid frame. */
- dev_kfree_skb_any(skb);
- return NETDEV_TX_OK;
- }
- B43_WARN_ON(skb_shinfo(skb)->nr_frags);
- if (unlikely(!dev))
- return NETDEV_TX_BUSY;
-
- /* Transmissions on seperate queues can run concurrently. */
- read_lock_irqsave(&wl->tx_lock, flags);
-
- err = -ENODEV;
- if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
- if (b43_using_pio_transfers(dev))
- err = b43_pio_tx(dev, skb);
- else
- err = b43_dma_tx(dev, skb);
- }
-
- read_unlock_irqrestore(&wl->tx_lock, flags);
-
- if (unlikely(err))
- return NETDEV_TX_BUSY;
- return NETDEV_TX_OK;
-}
-
-/* Locking: wl->irq_lock */
-static void b43_qos_params_upload(struct b43_wldev *dev,
- const struct ieee80211_tx_queue_params *p,
- u16 shm_offset)
-{
- u16 params[B43_NR_QOSPARAMS];
- int cw_min, cw_max, aifs, bslots, tmp;
- unsigned int i;
-
- const u16 aCWmin = 0x0001;
- const u16 aCWmax = 0x03FF;
-
- /* Calculate the default values for the parameters, if needed. */
- switch (shm_offset) {
- case B43_QOS_VOICE:
- aifs = (p->aifs == -1) ? 2 : p->aifs;
- cw_min = (p->cw_min == 0) ? ((aCWmin + 1) / 4 - 1) : p->cw_min;
- cw_max = (p->cw_max == 0) ? ((aCWmin + 1) / 2 - 1) : p->cw_max;
- break;
- case B43_QOS_VIDEO:
- aifs = (p->aifs == -1) ? 2 : p->aifs;
- cw_min = (p->cw_min == 0) ? ((aCWmin + 1) / 2 - 1) : p->cw_min;
- cw_max = (p->cw_max == 0) ? aCWmin : p->cw_max;
- break;
- case B43_QOS_BESTEFFORT:
- aifs = (p->aifs == -1) ? 3 : p->aifs;
- cw_min = (p->cw_min == 0) ? aCWmin : p->cw_min;
- cw_max = (p->cw_max == 0) ? aCWmax : p->cw_max;
- break;
- case B43_QOS_BACKGROUND:
- aifs = (p->aifs == -1) ? 7 : p->aifs;
- cw_min = (p->cw_min == 0) ? aCWmin : p->cw_min;
- cw_max = (p->cw_max == 0) ? aCWmax : p->cw_max;
- break;
- default:
- B43_WARN_ON(1);
- return;
- }
- if (cw_min <= 0)
- cw_min = aCWmin;
- if (cw_max <= 0)
- cw_max = aCWmin;
- bslots = b43_read16(dev, B43_MMIO_RNG) % cw_min;
-
- memset(¶ms, 0, sizeof(params));
-
- params[B43_QOSPARAM_TXOP] = p->txop * 32;
- params[B43_QOSPARAM_CWMIN] = cw_min;
- params[B43_QOSPARAM_CWMAX] = cw_max;
- params[B43_QOSPARAM_CWCUR] = cw_min;
- params[B43_QOSPARAM_AIFS] = aifs;
- params[B43_QOSPARAM_BSLOTS] = bslots;
- params[B43_QOSPARAM_REGGAP] = bslots + aifs;
-
- for (i = 0; i < ARRAY_SIZE(params); i++) {
- if (i == B43_QOSPARAM_STATUS) {
- tmp = b43_shm_read16(dev, B43_SHM_SHARED,
- shm_offset + (i * 2));
- /* Mark the parameters as updated. */
- tmp |= 0x100;
- b43_shm_write16(dev, B43_SHM_SHARED,
- shm_offset + (i * 2),
- tmp);
- } else {
- b43_shm_write16(dev, B43_SHM_SHARED,
- shm_offset + (i * 2),
- params[i]);
- }
- }
-}
-
-/* Update the QOS parameters in hardware. */
-static void b43_qos_update(struct b43_wldev *dev)
-{
- struct b43_wl *wl = dev->wl;
- struct b43_qos_params *params;
- unsigned long flags;
- unsigned int i;
-
- /* Mapping of mac80211 queues to b43 SHM offsets. */
- static const u16 qos_shm_offsets[] = {
- [0] = B43_QOS_VOICE,
- [1] = B43_QOS_VIDEO,
- [2] = B43_QOS_BESTEFFORT,
- [3] = B43_QOS_BACKGROUND,
- };
- BUILD_BUG_ON(ARRAY_SIZE(qos_shm_offsets) != ARRAY_SIZE(wl->qos_params));
-
- b43_mac_suspend(dev);
- spin_lock_irqsave(&wl->irq_lock, flags);
-
- for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
- params = &(wl->qos_params[i]);
- if (params->need_hw_update) {
- b43_qos_params_upload(dev, &(params->p),
- qos_shm_offsets[i]);
- params->need_hw_update = 0;
- }
- }
-
- spin_unlock_irqrestore(&wl->irq_lock, flags);
- b43_mac_enable(dev);
-}
-
-static void b43_qos_clear(struct b43_wl *wl)
-{
- struct b43_qos_params *params;
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
- params = &(wl->qos_params[i]);
-
- memset(&(params->p), 0, sizeof(params->p));
- params->p.aifs = -1;
- params->need_hw_update = 1;
- }
-}
-
-/* Initialize the core's QOS capabilities */
-static void b43_qos_init(struct b43_wldev *dev)
-{
- struct b43_wl *wl = dev->wl;
- unsigned int i;
-
- /* Upload the current QOS parameters. */
- for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++)
- wl->qos_params[i].need_hw_update = 1;
- b43_qos_update(dev);
-
- /* Enable QOS support. */
- b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
- b43_write16(dev, B43_MMIO_IFSCTL,
- b43_read16(dev, B43_MMIO_IFSCTL)
- | B43_MMIO_IFSCTL_USE_EDCF);
-}
-
-static void b43_qos_update_work(struct work_struct *work)
-{
- struct b43_wl *wl = container_of(work, struct b43_wl, qos_update_work);
- struct b43_wldev *dev;
-
- mutex_lock(&wl->mutex);
- dev = wl->current_dev;
- if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED)))
- b43_qos_update(dev);
- mutex_unlock(&wl->mutex);
-}
-
-static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
- const struct ieee80211_tx_queue_params *params)
-{
- struct b43_wl *wl = hw_to_b43_wl(hw);
- unsigned long flags;
- unsigned int queue = (unsigned int)_queue;
- struct b43_qos_params *p;
-
- if (queue >= ARRAY_SIZE(wl->qos_params)) {
- /* Queue not available or don't support setting
- * params on this queue. Return success to not
- * confuse mac80211. */
- return 0;
- }
-
- spin_lock_irqsave(&wl->irq_lock, flags);
- p = &(wl->qos_params[queue]);
- memcpy(&(p->p), params, sizeof(p->p));
- p->need_hw_update = 1;
- spin_unlock_irqrestore(&wl->irq_lock, flags);
-
- queue_work(hw->workqueue, &wl->qos_update_work);
-
- return 0;
-}
-
-static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
- struct ieee80211_tx_queue_stats *stats)
-{
- struct b43_wl *wl = hw_to_b43_wl(hw);
- struct b43_wldev *dev = wl->current_dev;
- unsigned long flags;
- int err = -ENODEV;
-
- if (!dev)
- goto out;
- spin_lock_irqsave(&wl->irq_lock, flags);
- if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
- if (b43_using_pio_transfers(dev))
- b43_pio_get_tx_stats(dev, stats);
- else
- b43_dma_get_tx_stats(dev, stats);
- err = 0;
- }
- spin_unlock_irqrestore(&wl->irq_lock, flags);
-out:
- return err;
-}
-
-static int b43_op_get_stats(struct ieee80211_hw *hw,
- struct ieee80211_low_level_stats *stats)
-{
- struct b43_wl *wl = hw_to_b43_wl(hw);
- unsigned long flags;
-
- spin_lock_irqsave(&wl->irq_lock, flags);
- memcpy(stats, &wl->ieee_stats, sizeof(*stats));
- spin_unlock_irqrestore(&wl->irq_lock, flags);
-
- return 0;
-}
-
-static void b43_put_phy_into_reset(struct b43_wldev *dev)
-{
- struct ssb_device *sdev = dev->dev;
- u32 tmslow;
-
- tmslow = ssb_read32(sdev, SSB_TMSLOW);
- tmslow &= ~B43_TMSLOW_GMODE;
- tmslow |= B43_TMSLOW_PHYRESET;
- tmslow |= SSB_TMSLOW_FGC;
- ssb_write32(sdev, SSB_TMSLOW, tmslow);
- msleep(1);
-
- tmslow = ssb_read32(sdev, SSB_TMSLOW);
- tmslow &= ~SSB_TMSLOW_FGC;
- tmslow |= B43_TMSLOW_PHYRESET;
- ssb_write32(sdev, SSB_TMSLOW, tmslow);
- msleep(1);
-}
-
-static const char * band_to_string(enum ieee80211_band band)
-{
- switch (band) {
- case IEEE80211_BAND_5GHZ:
- return "5";
- case IEEE80211_BAND_2GHZ:
- return "2.4";
- default:
- break;
- }
- B43_WARN_ON(1);
- return "";
-}
-
-/* Expects wl->mutex locked */
-static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
-{
- struct b43_wldev *up_dev = NULL;
- struct b43_wldev *down_dev;
- struct b43_wldev *d;
- int err;
- bool gmode;
- int prev_status;
-
- /* Find a device and PHY which supports the band. */
- list_for_each_entry(d, &wl->devlist, list) {
- switch (chan->band) {
- case IEEE80211_BAND_5GHZ:
- if (d->phy.supports_5ghz) {
- up_dev = d;
- gmode = 0;
- }
- break;
- case IEEE80211_BAND_2GHZ:
- if (d->phy.supports_2ghz) {
- up_dev = d;
- gmode = 1;
- }
- break;
- default:
- B43_WARN_ON(1);
- return -EINVAL;
- }
- if (up_dev)
- break;
- }
- if (!up_dev) {
- b43err(wl, "Could not find a device for %s-GHz band operation\n",
- band_to_string(chan->band));
- return -ENODEV;
- }
- if ((up_dev == wl->current_dev) &&
- (!!wl->current_dev->phy.gmode == !!gmode)) {
- /* This device is already running. */
- return 0;
- }
- b43dbg(wl, "Switching to %s-GHz band\n",
- band_to_string(chan->band));
- down_dev = wl->current_dev;
-
- prev_status = b43_status(down_dev);
- /* Shutdown the currently running core. */
- if (prev_status >= B43_STAT_STARTED)
- b43_wireless_core_stop(down_dev);
- if (prev_status >= B43_STAT_INITIALIZED)
- b43_wireless_core_exit(down_dev);
-
- if (down_dev != up_dev) {
- /* We switch to a different core, so we put PHY into
- * RESET on the old core. */
- b43_put_phy_into_reset(down_dev);
- }
-
- /* Now start the new core. */
- up_dev->phy.gmode = gmode;
- if (prev_status >= B43_STAT_INITIALIZED) {
- err = b43_wireless_core_init(up_dev);
- if (err) {
- b43err(wl, "Fatal: Could not initialize device for "
- "selected %s-GHz band\n",
- band_to_string(chan->band));
- goto init_failure;
- }
- }
- if (prev_status >= B43_STAT_STARTED) {
- err = b43_wireless_core_start(up_dev);
- if (err) {
- b43err(wl, "Fatal: Coult not start device for "
- "selected %s-GHz band\n",
- band_to_string(chan->band));
- b43_wireless_core_exit(up_dev);
- goto init_failure;
- }
- }
- B43_WARN_ON(b43_status(up_dev) != prev_status);
-
- wl->current_dev = up_dev;
-
- return 0;
-init_failure:
- /* Whoops, failed to init the new core. No core is operating now. */
- wl->current_dev = NULL;
- return err;
-}
-
-static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
-{
- struct b43_wl *wl = hw_to_b43_wl(hw);
- struct b43_wldev *dev;
- struct b43_phy *phy;
- unsigned long flags;
- int antenna;
- int err = 0;
- u32 savedirqs;
-
- mutex_lock(&wl->mutex);
-
- /* Switch the band (if necessary). This might change the active core. */
- err = b43_switch_band(wl, conf->channel);
- if (err)
- goto out_unlock_mutex;
- dev = wl->current_dev;
- phy = &dev->phy;
-
- /* Disable IRQs while reconfiguring the device.
- * This makes it possible to drop the spinlock throughout
- * the reconfiguration process. */
- spin_lock_irqsave(&wl->irq_lock, flags);
- if (b43_status(dev) < B43_STAT_STARTED) {
- spin_unlock_irqrestore(&wl->irq_lock, flags);
- goto out_unlock_mutex;
- }
- savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
- spin_unlock_irqrestore(&wl->irq_lock, flags);
- b43_synchronize_irq(dev);
-
- /* Switch to the requested channel.
- * The firmware takes care of races with the TX handler. */
- if (conf->channel->hw_value != phy->channel)
- b43_radio_selectchannel(dev, conf->channel->hw_value, 0);
-
- /* Enable/Disable ShortSlot timing. */
- if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
- dev->short_slot) {
- B43_WARN_ON(phy->type != B43_PHYTYPE_G);
- if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
- b43_short_slot_timing_enable(dev);
- else
- b43_short_slot_timing_disable(dev);
- }
-
- dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
-
- /* Adjust the desired TX power level. */
- if (conf->power_level != 0) {
- if (conf->power_level != phy->power_level) {
- phy->power_level = conf->power_level;
- b43_phy_xmitpower(dev);
- }
- }
-
- /* Antennas for RX and management frame TX. */
- antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
- b43_mgmtframe_txantenna(dev, antenna);
- antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
- b43_set_rx_antenna(dev, antenna);
-
- /* Update templates for AP mode. */
- if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
- b43_set_beacon_int(dev, conf->beacon_int);
-
- if (!!conf->radio_enabled != phy->radio_on) {
- if (conf->radio_enabled) {
- b43_radio_turn_on(dev);
- b43info(dev->wl, "Radio turned on by software\n");
- if (!dev->radio_hw_enable) {
- b43info(dev->wl, "The hardware RF-kill button "
- "still turns the radio physically off. "
- "Press the button to turn it on.\n");
- }
- } else {
- b43_radio_turn_off(dev, 0);
- b43info(dev->wl, "Radio turned off by software\n");
- }
- }
-
- spin_lock_irqsave(&wl->irq_lock, flags);
- b43_interrupt_enable(dev, savedirqs);
- mmiowb();
- spin_unlock_irqrestore(&wl->irq_lock, flags);
- out_unlock_mutex:
- mutex_unlock(&wl->mutex);
-
- return err;
-}
-
-static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
- const u8 *local_addr, const u8 *addr,
- struct ieee80211_key_conf *key)
-{
- struct b43_wl *wl = hw_to_b43_wl(hw);
- struct b43_wldev *dev;
- unsigned long flags;
- u8 algorithm;
- u8 index;
- int err;
- DECLARE_MAC_BUF(mac);
-
- if (modparam_nohwcrypt)
- return -ENOSPC; /* User disabled HW-crypto */
-
- mutex_lock(&wl->mutex);
- spin_lock_irqsave(&wl->irq_lock, flags);
-
- dev = wl->current_dev;
- err = -ENODEV;
- if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
- goto out_unlock;
-
- if (dev->fw.pcm_request_failed) {
- /* We don't have firmware for the crypto engine.
- * Must use software-crypto. */
- err = -EOPNOTSUPP;
- goto out_unlock;
- }
-
- err = -EINVAL;
- switch (key->alg) {
- case ALG_WEP:
- if (key->keylen == 5)
- algorithm = B43_SEC_ALGO_WEP40;
- else
- algorithm = B43_SEC_ALGO_WEP104;
- break;
- case ALG_TKIP:
- algorithm = B43_SEC_ALGO_TKIP;
- break;
- case ALG_CCMP:
- algorithm = B43_SEC_ALGO_AES;
- break;
- default:
- B43_WARN_ON(1);
- goto out_unlock;
- }
- index = (u8) (key->keyidx);
- if (index > 3)
- goto out_unlock;
-
- switch (cmd) {
- case SET_KEY:
- if (algorithm == B43_SEC_ALGO_TKIP) {
- /* FIXME: No TKIP hardware encryption for now. */
- err = -EOPNOTSUPP;
- goto out_unlock;
- }
-
- if (is_broadcast_ether_addr(addr)) {
- /* addr is FF:FF:FF:FF:FF:FF for default keys */
- err = b43_key_write(dev, index, algorithm,
- key->key, key->keylen, NULL, key);
- } else {
- /*
- * either pairwise key or address is 00:00:00:00:00:00
- * for transmit-only keys
- */
- err = b43_key_write(dev, -1, algorithm,
- key->key, key->keylen, addr, key);
- }
- if (err)
- goto out_unlock;
-
- if (algorithm == B43_SEC_ALGO_WEP40 ||
- algorithm == B43_SEC_ALGO_WEP104) {
- b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
- } else {
- b43_hf_write(dev,
- b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
- }
- key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
- break;
- case DISABLE_KEY: {
- err = b43_key_clear(dev, key->hw_key_idx);
- if (err)
- goto out_unlock;
- break;
- }
- default:
- B43_WARN_ON(1);
- }
-out_unlock:
- spin_unlock_irqrestore(&wl->irq_lock, flags);
- mutex_unlock(&wl->mutex);
- if (!err) {
- b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
- "mac: %s\n",
- cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
- print_mac(mac, addr));
- }
- return err;
-}
-
-static void b43_op_configure_filter(struct ieee80211_hw *hw,
- unsigned int changed, unsigned int *fflags,
- int mc_count, struct dev_addr_list *mc_list)
-{
- struct b43_wl *wl = hw_to_b43_wl(hw);
- struct b43_wldev *dev = wl->current_dev;
- unsigned long flags;
-
- if (!dev) {
- *fflags = 0;
- return;
- }
-
- spin_lock_irqsave(&wl->irq_lock, flags);
- *fflags &= FIF_PROMISC_IN_BSS |
- FIF_ALLMULTI |
- FIF_FCSFAIL |
- FIF_PLCPFAIL |
- FIF_CONTROL |
- FIF_OTHER_BSS |
- FIF_BCN_PRBRESP_PROMISC;
-
- changed &= FIF_PROMISC_IN_BSS |
- FIF_ALLMULTI |
- FIF_FCSFAIL |
- FIF_PLCPFAIL |
- FIF_CONTROL |
- FIF_OTHER_BSS |
- FIF_BCN_PRBRESP_PROMISC;
-
- wl->filter_flags = *fflags;
-
- if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
- b43_adjust_opmode(dev);
- spin_unlock_irqrestore(&wl->irq_lock, flags);
-}
-
-static int b43_op_config_interface(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif,
- struct ieee80211_if_conf *conf)
-{
- struct b43_wl *wl = hw_to_b43_wl(hw);
- struct b43_wldev *dev = wl->current_dev;
- unsigned long flags;
-
- if (!dev)
- return -ENODEV;
- mutex_lock(&wl->mutex);
- spin_lock_irqsave(&wl->irq_lock, flags);
- B43_WARN_ON(wl->vif != vif);
- if (conf->bssid)
- memcpy(wl->bssid, conf->bssid, ETH_ALEN);
- else
- memset(wl->bssid, 0, ETH_ALEN);
- if (b43_status(dev) >= B43_STAT_INITIALIZED) {
- if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
- B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
- b43_set_ssid(dev, conf->ssid, conf->ssid_len);
- if (conf->beacon)
- b43_update_templates(wl, conf->beacon);
- }
- b43_write_mac_bssid_templates(dev);
- }
- spin_unlock_irqrestore(&wl->irq_lock, flags);
- mutex_unlock(&wl->mutex);
-
- return 0;
-}
-
-/* Locking: wl->mutex */
-static void b43_wireless_core_stop(struct b43_wldev *dev)
-{
- struct b43_wl *wl = dev->wl;
- unsigned long flags;
-
- if (b43_status(dev) < B43_STAT_STARTED)
- return;
-
- /* Disable and sync interrupts. We must do this before than
- * setting the status to INITIALIZED, as the interrupt handler
- * won't care about IRQs then. */
- spin_lock_irqsave(&wl->irq_lock, flags);
- dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
- b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
- spin_unlock_irqrestore(&wl->irq_lock, flags);
- b43_synchronize_irq(dev);
-
- write_lock_irqsave(&wl->tx_lock, flags);
- b43_set_status(dev, B43_STAT_INITIALIZED);
- write_unlock_irqrestore(&wl->tx_lock, flags);
-
- b43_pio_stop(dev);
- mutex_unlock(&wl->mutex);
- /* Must unlock as it would otherwise deadlock. No races here.
- * Cancel the possibly running self-rearming periodic work. */
- cancel_delayed_work_sync(&dev->periodic_work);
- mutex_lock(&wl->mutex);
-
- b43_mac_suspend(dev);
- free_irq(dev->dev->irq, dev);
- b43dbg(wl, "Wireless interface stopped\n");
-}
-
-/* Locking: wl->mutex */
-static int b43_wireless_core_start(struct b43_wldev *dev)
-{
- int err;
-
- B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
-
- drain_txstatus_queue(dev);
- err = request_irq(dev->dev->irq, b43_interrupt_handler,
- IRQF_SHARED, KBUILD_MODNAME, dev);
- if (err) {
- b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
- goto out;
- }
-
- /* We are ready to run. */
- b43_set_status(dev, B43_STAT_STARTED);
-
- /* Start data flow (TX/RX). */
- b43_mac_enable(dev);
- b43_interrupt_enable(dev, dev->irq_savedstate);
-
- /* Start maintainance work */
- b43_periodic_tasks_setup(dev);
-
- b43dbg(dev->wl, "Wireless interface started\n");
- out:
- return err;
-}
-
-/* Get PHY and RADIO versioning numbers */
-static int b43_phy_versioning(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- u32 tmp;
- u8 analog_type;
- u8 phy_type;
- u8 phy_rev;
- u16 radio_manuf;
- u16 radio_ver;
- u16 radio_rev;
- int unsupported = 0;
-
- /* Get PHY versioning */
- tmp = b43_read16(dev, B43_MMIO_PHY_VER);
- analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
- phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
- phy_rev = (tmp & B43_PHYVER_VERSION);
- switch (phy_type) {
- case B43_PHYTYPE_A:
- if (phy_rev >= 4)
- unsupported = 1;
- break;
- case B43_PHYTYPE_B:
- if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
- && phy_rev != 7)
- unsupported = 1;
- break;
- case B43_PHYTYPE_G:
- if (phy_rev > 9)
- unsupported = 1;
- break;
-#ifdef CONFIG_B43_NPHY
- case B43_PHYTYPE_N:
- if (phy_rev > 1)
- unsupported = 1;
- break;
-#endif
- default:
- unsupported = 1;
- };
- if (unsupported) {
- b43err(dev->wl, "FOUND UNSUPPORTED PHY "
- "(Analog %u, Type %u, Revision %u)\n",
- analog_type, phy_type, phy_rev);
- return -EOPNOTSUPP;
- }
- b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
- analog_type, phy_type, phy_rev);
-
- /* Get RADIO versioning */
- if (dev->dev->bus->chip_id == 0x4317) {
- if (dev->dev->bus->chip_rev == 0)
- tmp = 0x3205017F;
- else if (dev->dev->bus->chip_rev == 1)
- tmp = 0x4205017F;
- else
- tmp = 0x5205017F;
- } else {
- b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
- tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
- b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
- tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
- }
- radio_manuf = (tmp & 0x00000FFF);
- radio_ver = (tmp & 0x0FFFF000) >> 12;
- radio_rev = (tmp & 0xF0000000) >> 28;
- if (radio_manuf != 0x17F /* Broadcom */)
- unsupported = 1;
- switch (phy_type) {
- case B43_PHYTYPE_A:
- if (radio_ver != 0x2060)
- unsupported = 1;
- if (radio_rev != 1)
- unsupported = 1;
- if (radio_manuf != 0x17F)
- unsupported = 1;
- break;
- case B43_PHYTYPE_B:
- if ((radio_ver & 0xFFF0) != 0x2050)
- unsupported = 1;
- break;
- case B43_PHYTYPE_G:
- if (radio_ver != 0x2050)
- unsupported = 1;
- break;
- case B43_PHYTYPE_N:
- if (radio_ver != 0x2055)
- unsupported = 1;
- break;
- default:
- B43_WARN_ON(1);
- }
- if (unsupported) {
- b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
- "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
- radio_manuf, radio_ver, radio_rev);
- return -EOPNOTSUPP;
- }
- b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
- radio_manuf, radio_ver, radio_rev);
-
- phy->radio_manuf = radio_manuf;
- phy->radio_ver = radio_ver;
- phy->radio_rev = radio_rev;
-
- phy->analog = analog_type;
- phy->type = phy_type;
- phy->rev = phy_rev;
-
- return 0;
-}
-
-static void setup_struct_phy_for_init(struct b43_wldev *dev,
- struct b43_phy *phy)
-{
- struct b43_txpower_lo_control *lo;
- int i;
-
- memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
- memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
-
- phy->aci_enable = 0;
- phy->aci_wlan_automatic = 0;
- phy->aci_hw_rssi = 0;
-
- phy->radio_off_context.valid = 0;
-
- lo = phy->lo_control;
- if (lo) {
- memset(lo, 0, sizeof(*(phy->lo_control)));
- lo->tx_bias = 0xFF;
- INIT_LIST_HEAD(&lo->calib_list);
- }
- phy->max_lb_gain = 0;
- phy->trsw_rx_gain = 0;
- phy->txpwr_offset = 0;
-
- /* NRSSI */
- phy->nrssislope = 0;
- for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
- phy->nrssi[i] = -1000;
- for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
- phy->nrssi_lt[i] = i;
-
- phy->lofcal = 0xFFFF;
- phy->initval = 0xFFFF;
-
- phy->interfmode = B43_INTERFMODE_NONE;
- phy->channel = 0xFF;
-
- phy->hardware_power_control = !!modparam_hwpctl;
-
- /* PHY TX errors counter. */
- atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
-
- /* OFDM-table address caching. */
- phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
-}
-
-static void setup_struct_wldev_for_init(struct b43_wldev *dev)
-{
- dev->dfq_valid = 0;
-
- /* Assume the radio is enabled. If it's not enabled, the state will
- * immediately get fixed on the first periodic work run. */
- dev->radio_hw_enable = 1;
-
- /* Stats */
- memset(&dev->stats, 0, sizeof(dev->stats));
-
- setup_struct_phy_for_init(dev, &dev->phy);
-
- /* IRQ related flags */
- dev->irq_reason = 0;
- memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
- dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
-
- dev->mac_suspended = 1;
-
- /* Noise calculation context */
- memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
-}
-
-static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
-{
- struct ssb_sprom *sprom = &dev->dev->bus->sprom;
- u64 hf;
-
- if (!modparam_btcoex)
- return;
- if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
- return;
- if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
- return;
-
- hf = b43_hf_read(dev);
- if (sprom->boardflags_lo & B43_BFL_BTCMOD)
- hf |= B43_HF_BTCOEXALT;
- else
- hf |= B43_HF_BTCOEX;
- b43_hf_write(dev, hf);
-}
-
-static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
-{
- if (!modparam_btcoex)
- return;
- //TODO
-}
-
-static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
-{
-#ifdef CONFIG_SSB_DRIVER_PCICORE
- struct ssb_bus *bus = dev->dev->bus;
- u32 tmp;
-
- if (bus->pcicore.dev &&
- bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
- bus->pcicore.dev->id.revision <= 5) {
- /* IMCFGLO timeouts workaround. */
- tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
- tmp &= ~SSB_IMCFGLO_REQTO;
- tmp &= ~SSB_IMCFGLO_SERTO;
- switch (bus->bustype) {
- case SSB_BUSTYPE_PCI:
- case SSB_BUSTYPE_PCMCIA:
- tmp |= 0x32;
- break;
- case SSB_BUSTYPE_SSB:
- tmp |= 0x53;
- break;
- }
- ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
- }
-#endif /* CONFIG_SSB_DRIVER_PCICORE */
-}
-
-/* Write the short and long frame retry limit values. */
-static void b43_set_retry_limits(struct b43_wldev *dev,
- unsigned int short_retry,
- unsigned int long_retry)
-{
- /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
- * the chip-internal counter. */
- short_retry = min(short_retry, (unsigned int)0xF);
- long_retry = min(long_retry, (unsigned int)0xF);
-
- b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
- short_retry);
- b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
- long_retry);
-}
-
-static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
-{
- u16 pu_delay;
-
- /* The time value is in microseconds. */
- if (dev->phy.type == B43_PHYTYPE_A)
- pu_delay = 3700;
- else
- pu_delay = 1050;
- if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS) || idle)
- pu_delay = 500;
- if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
- pu_delay = max(pu_delay, (u16)2400);
-
- b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
-}
-
-/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
-static void b43_set_pretbtt(struct b43_wldev *dev)
-{
- u16 pretbtt;
-
- /* The time value is in microseconds. */
- if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS)) {
- pretbtt = 2;
- } else {
- if (dev->phy.type == B43_PHYTYPE_A)
- pretbtt = 120;
- else
- pretbtt = 250;
- }
- b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
- b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
-}
-
-/* Shutdown a wireless core */
-/* Locking: wl->mutex */
-static void b43_wireless_core_exit(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- u32 macctl;
-
- B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
- if (b43_status(dev) != B43_STAT_INITIALIZED)
- return;
- b43_set_status(dev, B43_STAT_UNINIT);
-
- /* Stop the microcode PSM. */
- macctl = b43_read32(dev, B43_MMIO_MACCTL);
- macctl &= ~B43_MACCTL_PSM_RUN;
- macctl |= B43_MACCTL_PSM_JMP0;
- b43_write32(dev, B43_MMIO_MACCTL, macctl);
-
- if (!dev->suspend_in_progress) {
- b43_leds_exit(dev);
- b43_rng_exit(dev->wl);
- }
- b43_dma_free(dev);
- b43_pio_free(dev);
- b43_chip_exit(dev);
- b43_radio_turn_off(dev, 1);
- b43_switch_analog(dev, 0);
- if (phy->dyn_tssi_tbl)
- kfree(phy->tssi2dbm);
- kfree(phy->lo_control);
- phy->lo_control = NULL;
- if (dev->wl->current_beacon) {
- dev_kfree_skb_any(dev->wl->current_beacon);
- dev->wl->current_beacon = NULL;
- }
-
- ssb_device_disable(dev->dev, 0);
- ssb_bus_may_powerdown(dev->dev->bus);
-}
-
-/* Initialize a wireless core */
-static int b43_wireless_core_init(struct b43_wldev *dev)
-{
- struct b43_wl *wl = dev->wl;
- struct ssb_bus *bus = dev->dev->bus;
- struct ssb_sprom *sprom = &bus->sprom;
- struct b43_phy *phy = &dev->phy;
- int err;
- u64 hf;
- u32 tmp;
-
- B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
-
- err = ssb_bus_powerup(bus, 0);
- if (err)
- goto out;
- if (!ssb_device_is_enabled(dev->dev)) {
- tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
- b43_wireless_core_reset(dev, tmp);
- }
-
- if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
- phy->lo_control =
- kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
- if (!phy->lo_control) {
- err = -ENOMEM;
- goto err_busdown;
- }
- }
- setup_struct_wldev_for_init(dev);
-
- err = b43_phy_init_tssi2dbm_table(dev);
- if (err)
- goto err_kfree_lo_control;
-
- /* Enable IRQ routing to this device. */
- ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
-
- b43_imcfglo_timeouts_workaround(dev);
- b43_bluetooth_coext_disable(dev);
- b43_phy_early_init(dev);
- err = b43_chip_init(dev);
- if (err)
- goto err_kfree_tssitbl;
- b43_shm_write16(dev, B43_SHM_SHARED,
- B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
- hf = b43_hf_read(dev);
- if (phy->type == B43_PHYTYPE_G) {
- hf |= B43_HF_SYMW;
- if (phy->rev == 1)
- hf |= B43_HF_GDCW;
- if (sprom->boardflags_lo & B43_BFL_PACTRL)
- hf |= B43_HF_OFDMPABOOST;
- } else if (phy->type == B43_PHYTYPE_B) {
- hf |= B43_HF_SYMW;
- if (phy->rev >= 2 && phy->radio_ver == 0x2050)
- hf &= ~B43_HF_GDCW;
- }
- b43_hf_write(dev, hf);
-
- b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
- B43_DEFAULT_LONG_RETRY_LIMIT);
- b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
- b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
-
- /* Disable sending probe responses from firmware.
- * Setting the MaxTime to one usec will always trigger
- * a timeout, so we never send any probe resp.
- * A timeout of zero is infinite. */
- b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
-
- b43_rate_memory_init(dev);
- b43_set_phytxctl_defaults(dev);
-
- /* Minimum Contention Window */
- if (phy->type == B43_PHYTYPE_B) {
- b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
- } else {
- b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
- }
- /* Maximum Contention Window */
- b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
-
- if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
- dev->__using_pio_transfers = 1;
- err = b43_pio_init(dev);
- } else {
- dev->__using_pio_transfers = 0;
- err = b43_dma_init(dev);
- }
- if (err)
- goto err_chip_exit;
- b43_qos_init(dev);
- b43_set_synth_pu_delay(dev, 1);
- b43_bluetooth_coext_enable(dev);
-
- ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
- b43_upload_card_macaddress(dev);
- b43_security_init(dev);
- if (!dev->suspend_in_progress)
- b43_rng_init(wl);
-
- b43_set_status(dev, B43_STAT_INITIALIZED);
-
- if (!dev->suspend_in_progress)
- b43_leds_init(dev);
-out:
- return err;
-
- err_chip_exit:
- b43_chip_exit(dev);
- err_kfree_tssitbl:
- if (phy->dyn_tssi_tbl)
- kfree(phy->tssi2dbm);
- err_kfree_lo_control:
- kfree(phy->lo_control);
- phy->lo_control = NULL;
- err_busdown:
- ssb_bus_may_powerdown(bus);
- B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
- return err;
-}
-
-static int b43_op_add_interface(struct ieee80211_hw *hw,
- struct ieee80211_if_init_conf *conf)
-{
- struct b43_wl *wl = hw_to_b43_wl(hw);
- struct b43_wldev *dev;
- unsigned long flags;
- int err = -EOPNOTSUPP;
-
- /* TODO: allow WDS/AP devices to coexist */
-
- if (conf->type != IEEE80211_IF_TYPE_AP &&
- conf->type != IEEE80211_IF_TYPE_STA &&
- conf->type != IEEE80211_IF_TYPE_WDS &&
- conf->type != IEEE80211_IF_TYPE_IBSS)
- return -EOPNOTSUPP;
-
- mutex_lock(&wl->mutex);
- if (wl->operating)
- goto out_mutex_unlock;
-
- b43dbg(wl, "Adding Interface type %d\n", conf->type);
-
- dev = wl->current_dev;
- wl->operating = 1;
- wl->vif = conf->vif;
- wl->if_type = conf->type;
- memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
-
- spin_lock_irqsave(&wl->irq_lock, flags);
- b43_adjust_opmode(dev);
- b43_set_pretbtt(dev);
- b43_set_synth_pu_delay(dev, 0);
- b43_upload_card_macaddress(dev);
- spin_unlock_irqrestore(&wl->irq_lock, flags);
-
- err = 0;
- out_mutex_unlock:
- mutex_unlock(&wl->mutex);
-
- return err;
-}
-
-static void b43_op_remove_interface(struct ieee80211_hw *hw,
- struct ieee80211_if_init_conf *conf)
-{
- struct b43_wl *wl = hw_to_b43_wl(hw);
- struct b43_wldev *dev = wl->current_dev;
- unsigned long flags;
-
- b43dbg(wl, "Removing Interface type %d\n", conf->type);
-
- mutex_lock(&wl->mutex);
-
- B43_WARN_ON(!wl->operating);
- B43_WARN_ON(wl->vif != conf->vif);
- wl->vif = NULL;
-
- wl->operating = 0;
-
- spin_lock_irqsave(&wl->irq_lock, flags);
- b43_adjust_opmode(dev);
- memset(wl->mac_addr, 0, ETH_ALEN);
- b43_upload_card_macaddress(dev);
- spin_unlock_irqrestore(&wl->irq_lock, flags);
-
- mutex_unlock(&wl->mutex);
-}
-
-static int b43_op_start(struct ieee80211_hw *hw)
-{
- struct b43_wl *wl = hw_to_b43_wl(hw);
- struct b43_wldev *dev = wl->current_dev;
- int did_init = 0;
- int err = 0;
- bool do_rfkill_exit = 0;
-
- /* Kill all old instance specific information to make sure
- * the card won't use it in the short timeframe between start
- * and mac80211 reconfiguring it. */
- memset(wl->bssid, 0, ETH_ALEN);
- memset(wl->mac_addr, 0, ETH_ALEN);
- wl->filter_flags = 0;
- wl->radiotap_enabled = 0;
- b43_qos_clear(wl);
-
- /* First register RFkill.
- * LEDs that are registered later depend on it. */
- b43_rfkill_init(dev);
-
- mutex_lock(&wl->mutex);
-
- if (b43_status(dev) < B43_STAT_INITIALIZED) {
- err = b43_wireless_core_init(dev);
- if (err) {
- do_rfkill_exit = 1;
- goto out_mutex_unlock;
- }
- did_init = 1;
- }
-
- if (b43_status(dev) < B43_STAT_STARTED) {
- err = b43_wireless_core_start(dev);
- if (err) {
- if (did_init)
- b43_wireless_core_exit(dev);
- do_rfkill_exit = 1;
- goto out_mutex_unlock;
- }
- }
-
- out_mutex_unlock:
- mutex_unlock(&wl->mutex);
-
- if (do_rfkill_exit)
- b43_rfkill_exit(dev);
-
- return err;
-}
-
-static void b43_op_stop(struct ieee80211_hw *hw)
-{
- struct b43_wl *wl = hw_to_b43_wl(hw);
- struct b43_wldev *dev = wl->current_dev;
-
- b43_rfkill_exit(dev);
- cancel_work_sync(&(wl->qos_update_work));
- cancel_work_sync(&(wl->beacon_update_trigger));
-
- mutex_lock(&wl->mutex);
- if (b43_status(dev) >= B43_STAT_STARTED)
- b43_wireless_core_stop(dev);
- b43_wireless_core_exit(dev);
- mutex_unlock(&wl->mutex);
-}
-
-static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
- u32 short_retry_limit, u32 long_retry_limit)
-{
- struct b43_wl *wl = hw_to_b43_wl(hw);
- struct b43_wldev *dev;
- int err = 0;
-
- mutex_lock(&wl->mutex);
- dev = wl->current_dev;
- if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
- err = -ENODEV;
- goto out_unlock;
- }
- b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
-out_unlock:
- mutex_unlock(&wl->mutex);
-
- return err;
-}
-
-static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set)
-{
- struct b43_wl *wl = hw_to_b43_wl(hw);
- struct sk_buff *beacon;
- unsigned long flags;
-
- /* We could modify the existing beacon and set the aid bit in
- * the TIM field, but that would probably require resizing and
- * moving of data within the beacon template.
- * Simply request a new beacon and let mac80211 do the hard work. */
- beacon = ieee80211_beacon_get(hw, wl->vif);
- if (unlikely(!beacon))
- return -ENOMEM;
- spin_lock_irqsave(&wl->irq_lock, flags);
- b43_update_templates(wl, beacon);
- spin_unlock_irqrestore(&wl->irq_lock, flags);
-
- return 0;
-}
-
-static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw,
- struct sk_buff *beacon)
-{
- struct b43_wl *wl = hw_to_b43_wl(hw);
- unsigned long flags;
-
- spin_lock_irqsave(&wl->irq_lock, flags);
- b43_update_templates(wl, beacon);
- spin_unlock_irqrestore(&wl->irq_lock, flags);
-
- return 0;
-}
-
-static void b43_op_sta_notify(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif,
- enum sta_notify_cmd notify_cmd,
- const u8 *addr)
-{
- struct b43_wl *wl = hw_to_b43_wl(hw);
-
- B43_WARN_ON(!vif || wl->vif != vif);
-}
-
-static const struct ieee80211_ops b43_hw_ops = {
- .tx = b43_op_tx,
- .conf_tx = b43_op_conf_tx,
- .add_interface = b43_op_add_interface,
- .remove_interface = b43_op_remove_interface,
- .config = b43_op_config,
- .config_interface = b43_op_config_interface,
- .configure_filter = b43_op_configure_filter,
- .set_key = b43_op_set_key,
- .get_stats = b43_op_get_stats,
- .get_tx_stats = b43_op_get_tx_stats,
- .start = b43_op_start,
- .stop = b43_op_stop,
- .set_retry_limit = b43_op_set_retry_limit,
- .set_tim = b43_op_beacon_set_tim,
- .beacon_update = b43_op_ibss_beacon_update,
- .sta_notify = b43_op_sta_notify,
-};
-
-/* Hard-reset the chip. Do not call this directly.
- * Use b43_controller_restart()
- */
-static void b43_chip_reset(struct work_struct *work)
-{
- struct b43_wldev *dev =
- container_of(work, struct b43_wldev, restart_work);
- struct b43_wl *wl = dev->wl;
- int err = 0;
- int prev_status;
-
- mutex_lock(&wl->mutex);
-
- prev_status = b43_status(dev);
- /* Bring the device down... */
- if (prev_status >= B43_STAT_STARTED)
- b43_wireless_core_stop(dev);
- if (prev_status >= B43_STAT_INITIALIZED)
- b43_wireless_core_exit(dev);
-
- /* ...and up again. */
- if (prev_status >= B43_STAT_INITIALIZED) {
- err = b43_wireless_core_init(dev);
- if (err)
- goto out;
- }
- if (prev_status >= B43_STAT_STARTED) {
- err = b43_wireless_core_start(dev);
- if (err) {
- b43_wireless_core_exit(dev);
- goto out;
- }
- }
- out:
- mutex_unlock(&wl->mutex);
- if (err)
- b43err(wl, "Controller restart FAILED\n");
- else
- b43info(wl, "Controller restarted\n");
-}
-
-static int b43_setup_bands(struct b43_wldev *dev,
- bool have_2ghz_phy, bool have_5ghz_phy)
-{
- struct ieee80211_hw *hw = dev->wl->hw;
-
- if (have_2ghz_phy)
- hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
- if (dev->phy.type == B43_PHYTYPE_N) {
- if (have_5ghz_phy)
- hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
- } else {
- if (have_5ghz_phy)
- hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
- }
-
- dev->phy.supports_2ghz = have_2ghz_phy;
- dev->phy.supports_5ghz = have_5ghz_phy;
-
- return 0;
-}
-
-static void b43_wireless_core_detach(struct b43_wldev *dev)
-{
- /* We release firmware that late to not be required to re-request
- * is all the time when we reinit the core. */
- b43_release_firmware(dev);
-}
-
-static int b43_wireless_core_attach(struct b43_wldev *dev)
-{
- struct b43_wl *wl = dev->wl;
- struct ssb_bus *bus = dev->dev->bus;
- struct pci_dev *pdev = bus->host_pci;
- int err;
- bool have_2ghz_phy = 0, have_5ghz_phy = 0;
- u32 tmp;
-
- /* Do NOT do any device initialization here.
- * Do it in wireless_core_init() instead.
- * This function is for gathering basic information about the HW, only.
- * Also some structs may be set up here. But most likely you want to have
- * that in core_init(), too.
- */
-
- err = ssb_bus_powerup(bus, 0);
- if (err) {
- b43err(wl, "Bus powerup failed\n");
- goto out;
- }
- /* Get the PHY type. */
- if (dev->dev->id.revision >= 5) {
- u32 tmshigh;
-
- tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
- have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
- have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
- } else
- B43_WARN_ON(1);
-
- dev->phy.gmode = have_2ghz_phy;
- tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
- b43_wireless_core_reset(dev, tmp);
-
- err = b43_phy_versioning(dev);
- if (err)
- goto err_powerdown;
- /* Check if this device supports multiband. */
- if (!pdev ||
- (pdev->device != 0x4312 &&
- pdev->device != 0x4319 && pdev->device != 0x4324)) {
- /* No multiband support. */
- have_2ghz_phy = 0;
- have_5ghz_phy = 0;
- switch (dev->phy.type) {
- case B43_PHYTYPE_A:
- have_5ghz_phy = 1;
- break;
- case B43_PHYTYPE_G:
- case B43_PHYTYPE_N:
- have_2ghz_phy = 1;
- break;
- default:
- B43_WARN_ON(1);
- }
- }
- if (dev->phy.type == B43_PHYTYPE_A) {
- /* FIXME */
- b43err(wl, "IEEE 802.11a devices are unsupported\n");
- err = -EOPNOTSUPP;
- goto err_powerdown;
- }
- if (1 /* disable A-PHY */) {
- /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
- if (dev->phy.type != B43_PHYTYPE_N) {
- have_2ghz_phy = 1;
- have_5ghz_phy = 0;
- }
- }
-
- dev->phy.gmode = have_2ghz_phy;
- tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
- b43_wireless_core_reset(dev, tmp);
-
- err = b43_validate_chipaccess(dev);
- if (err)
- goto err_powerdown;
- err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
- if (err)
- goto err_powerdown;
-
- /* Now set some default "current_dev" */
- if (!wl->current_dev)
- wl->current_dev = dev;
- INIT_WORK(&dev->restart_work, b43_chip_reset);
-
- b43_radio_turn_off(dev, 1);
- b43_switch_analog(dev, 0);
- ssb_device_disable(dev->dev, 0);
- ssb_bus_may_powerdown(bus);
-
-out:
- return err;
-
-err_powerdown:
- ssb_bus_may_powerdown(bus);
- return err;
-}
-
-static void b43_one_core_detach(struct ssb_device *dev)
-{
- struct b43_wldev *wldev;
- struct b43_wl *wl;
-
- wldev = ssb_get_drvdata(dev);
- wl = wldev->wl;
- cancel_work_sync(&wldev->restart_work);
- b43_debugfs_remove_device(wldev);
- b43_wireless_core_detach(wldev);
- list_del(&wldev->list);
- wl->nr_devs--;
- ssb_set_drvdata(dev, NULL);
- kfree(wldev);
-}
-
-static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
-{
- struct b43_wldev *wldev;
- struct pci_dev *pdev;
- int err = -ENOMEM;
-
- if (!list_empty(&wl->devlist)) {
- /* We are not the first core on this chip. */
- pdev = dev->bus->host_pci;
- /* Only special chips support more than one wireless
- * core, although some of the other chips have more than
- * one wireless core as well. Check for this and
- * bail out early.
- */
- if (!pdev ||
- ((pdev->device != 0x4321) &&
- (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
- b43dbg(wl, "Ignoring unconnected 802.11 core\n");
- return -ENODEV;
- }
- }
-
- wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
- if (!wldev)
- goto out;
-
- wldev->dev = dev;
- wldev->wl = wl;
- b43_set_status(wldev, B43_STAT_UNINIT);
- wldev->bad_frames_preempt = modparam_bad_frames_preempt;
- tasklet_init(&wldev->isr_tasklet,
- (void (*)(unsigned long))b43_interrupt_tasklet,
- (unsigned long)wldev);
- INIT_LIST_HEAD(&wldev->list);
-
- err = b43_wireless_core_attach(wldev);
- if (err)
- goto err_kfree_wldev;
-
- list_add(&wldev->list, &wl->devlist);
- wl->nr_devs++;
- ssb_set_drvdata(dev, wldev);
- b43_debugfs_add_device(wldev);
-
- out:
- return err;
-
- err_kfree_wldev:
- kfree(wldev);
- return err;
-}
-
-#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
- (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
- (pdev->device == _device) && \
- (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
- (pdev->subsystem_device == _subdevice) )
-
-static void b43_sprom_fixup(struct ssb_bus *bus)
-{
- struct pci_dev *pdev;
-
- /* boardflags workarounds */
- if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
- bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
- bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
- if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
- bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
- bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
- if (bus->bustype == SSB_BUSTYPE_PCI) {
- pdev = bus->host_pci;
- if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
- IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
- IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013))
- bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
- }
-}
-
-static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
-{
- struct ieee80211_hw *hw = wl->hw;
-
- ssb_set_devtypedata(dev, NULL);
- ieee80211_free_hw(hw);
-}
-
-static int b43_wireless_init(struct ssb_device *dev)
-{
- struct ssb_sprom *sprom = &dev->bus->sprom;
- struct ieee80211_hw *hw;
- struct b43_wl *wl;
- int err = -ENOMEM;
-
- b43_sprom_fixup(dev->bus);
-
- hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
- if (!hw) {
- b43err(NULL, "Could not allocate ieee80211 device\n");
- goto out;
- }
-
- /* fill hw info */
- hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
- IEEE80211_HW_RX_INCLUDES_FCS |
- IEEE80211_HW_SIGNAL_DBM |
- IEEE80211_HW_NOISE_DBM;
-
- hw->queues = b43_modparam_qos ? 4 : 1;
- SET_IEEE80211_DEV(hw, dev->dev);
- if (is_valid_ether_addr(sprom->et1mac))
- SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
- else
- SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
-
- /* Get and initialize struct b43_wl */
- wl = hw_to_b43_wl(hw);
- memset(wl, 0, sizeof(*wl));
- wl->hw = hw;
- spin_lock_init(&wl->irq_lock);
- rwlock_init(&wl->tx_lock);
- spin_lock_init(&wl->leds_lock);
- spin_lock_init(&wl->shm_lock);
- mutex_init(&wl->mutex);
- INIT_LIST_HEAD(&wl->devlist);
- INIT_WORK(&wl->qos_update_work, b43_qos_update_work);
- INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
-
- ssb_set_devtypedata(dev, wl);
- b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
- err = 0;
- out:
- return err;
-}
-
-static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
-{
- struct b43_wl *wl;
- int err;
- int first = 0;
-
- wl = ssb_get_devtypedata(dev);
- if (!wl) {
- /* Probing the first core. Must setup common struct b43_wl */
- first = 1;
- err = b43_wireless_init(dev);
- if (err)
- goto out;
- wl = ssb_get_devtypedata(dev);
- B43_WARN_ON(!wl);
- }
- err = b43_one_core_attach(dev, wl);
- if (err)
- goto err_wireless_exit;
-
- if (first) {
- err = ieee80211_register_hw(wl->hw);
- if (err)
- goto err_one_core_detach;
- }
-
- out:
- return err;
-
- err_one_core_detach:
- b43_one_core_detach(dev);
- err_wireless_exit:
- if (first)
- b43_wireless_exit(dev, wl);
- return err;
-}
-
-static void b43_remove(struct ssb_device *dev)
-{
- struct b43_wl *wl = ssb_get_devtypedata(dev);
- struct b43_wldev *wldev = ssb_get_drvdata(dev);
-
- B43_WARN_ON(!wl);
- if (wl->current_dev == wldev)
- ieee80211_unregister_hw(wl->hw);
-
- b43_one_core_detach(dev);
-
- if (list_empty(&wl->devlist)) {
- /* Last core on the chip unregistered.
- * We can destroy common struct b43_wl.
- */
- b43_wireless_exit(dev, wl);
- }
-}
-
-/* Perform a hardware reset. This can be called from any context. */
-void b43_controller_restart(struct b43_wldev *dev, const char *reason)
-{
- /* Must avoid requeueing, if we are in shutdown. */
- if (b43_status(dev) < B43_STAT_INITIALIZED)
- return;
- b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
- queue_work(dev->wl->hw->workqueue, &dev->restart_work);
-}
-
-#ifdef CONFIG_PM
-
-static int b43_suspend(struct ssb_device *dev, pm_message_t state)
-{
- struct b43_wldev *wldev = ssb_get_drvdata(dev);
- struct b43_wl *wl = wldev->wl;
-
- b43dbg(wl, "Suspending...\n");
-
- mutex_lock(&wl->mutex);
- wldev->suspend_in_progress = true;
- wldev->suspend_init_status = b43_status(wldev);
- if (wldev->suspend_init_status >= B43_STAT_STARTED)
- b43_wireless_core_stop(wldev);
- if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
- b43_wireless_core_exit(wldev);
- mutex_unlock(&wl->mutex);
-
- b43dbg(wl, "Device suspended.\n");
-
- return 0;
-}
-
-static int b43_resume(struct ssb_device *dev)
-{
- struct b43_wldev *wldev = ssb_get_drvdata(dev);
- struct b43_wl *wl = wldev->wl;
- int err = 0;
-
- b43dbg(wl, "Resuming...\n");
-
- mutex_lock(&wl->mutex);
- if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
- err = b43_wireless_core_init(wldev);
- if (err) {
- b43err(wl, "Resume failed at core init\n");
- goto out;
- }
- }
- if (wldev->suspend_init_status >= B43_STAT_STARTED) {
- err = b43_wireless_core_start(wldev);
- if (err) {
- b43_leds_exit(wldev);
- b43_rng_exit(wldev->wl);
- b43_wireless_core_exit(wldev);
- b43err(wl, "Resume failed at core start\n");
- goto out;
- }
- }
- b43dbg(wl, "Device resumed.\n");
- out:
- wldev->suspend_in_progress = false;
- mutex_unlock(&wl->mutex);
- return err;
-}
-
-#else /* CONFIG_PM */
-# define b43_suspend NULL
-# define b43_resume NULL
-#endif /* CONFIG_PM */
-
-static struct ssb_driver b43_ssb_driver = {
- .name = KBUILD_MODNAME,
- .id_table = b43_ssb_tbl,
- .probe = b43_probe,
- .remove = b43_remove,
- .suspend = b43_suspend,
- .resume = b43_resume,
-};
-
-static void b43_print_driverinfo(void)
-{
- const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
- *feat_leds = "", *feat_rfkill = "";
-
-#ifdef CONFIG_B43_PCI_AUTOSELECT
- feat_pci = "P";
-#endif
-#ifdef CONFIG_B43_PCMCIA
- feat_pcmcia = "M";
-#endif
-#ifdef CONFIG_B43_NPHY
- feat_nphy = "N";
-#endif
-#ifdef CONFIG_B43_LEDS
- feat_leds = "L";
-#endif
-#ifdef CONFIG_B43_RFKILL
- feat_rfkill = "R";
-#endif
- printk(KERN_INFO "Broadcom 43xx driver loaded "
- "[ Features: %s%s%s%s%s, Firmware-ID: "
- B43_SUPPORTED_FIRMWARE_ID " ]\n",
- feat_pci, feat_pcmcia, feat_nphy,
- feat_leds, feat_rfkill);
-}
-
-static int __init b43_init(void)
-{
- int err;
-
- b43_debugfs_init();
- err = b43_pcmcia_init();
- if (err)
- goto err_dfs_exit;
- err = ssb_driver_register(&b43_ssb_driver);
- if (err)
- goto err_pcmcia_exit;
- b43_print_driverinfo();
-
- return err;
-
-err_pcmcia_exit:
- b43_pcmcia_exit();
-err_dfs_exit:
- b43_debugfs_exit();
- return err;
-}
-
-static void __exit b43_exit(void)
-{
- ssb_driver_unregister(&b43_ssb_driver);
- b43_pcmcia_exit();
- b43_debugfs_exit();
-}
-
-module_init(b43_init)
-module_exit(b43_exit)
-/*
-
- Broadcom B43 wireless driver
-
- Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
- Stefano Brivio <stefano.brivio@polimi.it>
- Michael Buesch <mb@bu3sch.de>
- Danny van Dyk <kugelfang@gentoo.org>
- Andreas Jaggi <andreas.jaggi@waterwave.ch>
-
- Some parts of the code in this file are derived from the ipw2200
- driver Copyright(c) 2003 - 2004 Intel Corporation.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; see the file COPYING. If not, write to
- the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
- Boston, MA 02110-1301, USA.
-
-*/
-
-#ifndef B43_MAIN_H_
-#define B43_MAIN_H_
-
-#include "b43.h"
-
-#define P4D_BYT3S(magic, nr_bytes) u8 __p4dding##magic[nr_bytes]
-#define P4D_BYTES(line, nr_bytes) P4D_BYT3S(line, nr_bytes)
-/* Magic helper macro to pad structures. Ignore those above. It's magic. */
-#define PAD_BYTES(nr_bytes) P4D_BYTES( __LINE__ , (nr_bytes))
-
-
-extern int b43_modparam_qos;
-
-
-/* Lightweight function to convert a frequency (in Mhz) to a channel number. */
-static inline u8 b43_freq_to_channel_5ghz(int freq)
-{
- return ((freq - 5000) / 5);
-}
-static inline u8 b43_freq_to_channel_2ghz(int freq)
-{
- u8 channel;
-
- if (freq == 2484)
- channel = 14;
- else
- channel = (freq - 2407) / 5;
-
- return channel;
-}
-
-/* Lightweight function to convert a channel number to a frequency (in Mhz). */
-static inline int b43_channel_to_freq_5ghz(u8 channel)
-{
- return (5000 + (5 * channel));
-}
-static inline int b43_channel_to_freq_2ghz(u8 channel)
-{
- int freq;
-
- if (channel == 14)
- freq = 2484;
- else
- freq = 2407 + (5 * channel);
-
- return freq;
-}
-
-static inline int b43_is_cck_rate(int rate)
-{
- return (rate == B43_CCK_RATE_1MB ||
- rate == B43_CCK_RATE_2MB ||
- rate == B43_CCK_RATE_5MB || rate == B43_CCK_RATE_11MB);
-}
-
-static inline int b43_is_ofdm_rate(int rate)
-{
- return !b43_is_cck_rate(rate);
-}
-
-u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
- u8 antenna_nr);
-
-void b43_tsf_read(struct b43_wldev *dev, u64 * tsf);
-void b43_tsf_write(struct b43_wldev *dev, u64 tsf);
-
-u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset);
-u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset);
-void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value);
-void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value);
-
-u64 b43_hf_read(struct b43_wldev *dev);
-void b43_hf_write(struct b43_wldev *dev, u64 value);
-
-void b43_dummy_transmission(struct b43_wldev *dev);
-
-void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags);
-
-void b43_controller_restart(struct b43_wldev *dev, const char *reason);
-
-#define B43_PS_ENABLED (1 << 0) /* Force enable hardware power saving */
-#define B43_PS_DISABLED (1 << 1) /* Force disable hardware power saving */
-#define B43_PS_AWAKE (1 << 2) /* Force device awake */
-#define B43_PS_ASLEEP (1 << 3) /* Force device asleep */
-void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags);
-
-void b43_mac_suspend(struct b43_wldev *dev);
-void b43_mac_enable(struct b43_wldev *dev);
-
-#endif /* B43_MAIN_H_ */
-/*
-
- Broadcom B43 wireless driver
- IEEE 802.11n PHY support
-
- Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; see the file COPYING. If not, write to
- the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
- Boston, MA 02110-1301, USA.
-
-*/
-
-#include <linux/delay.h>
-#include <linux/types.h>
-
-#include "b43.h"
-#include "nphy.h"
-#include "tables_nphy.h"
-
-
-void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
-{//TODO
-}
-
-void b43_nphy_xmitpower(struct b43_wldev *dev)
-{//TODO
-}
-
-static void b43_chantab_radio_upload(struct b43_wldev *dev,
- const struct b43_nphy_channeltab_entry *e)
-{
- b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
- b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
- b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
- b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
- b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
- b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
- b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
- b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
- b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
- b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
- b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
- b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
- b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
- b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
- b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
- b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
- b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
- b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
- b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
- b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
- b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
- b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
-}
-
-static void b43_chantab_phy_upload(struct b43_wldev *dev,
- const struct b43_nphy_channeltab_entry *e)
-{
- b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
- b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
- b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
- b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
- b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
- b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
-}
-
-static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
-{
- //TODO
-}
-
-/* Tune the hardware to a new channel. Don't call this directly.
- * Use b43_radio_selectchannel() */
-int b43_nphy_selectchannel(struct b43_wldev *dev, u8 channel)
-{
- const struct b43_nphy_channeltab_entry *tabent;
-
- tabent = b43_nphy_get_chantabent(dev, channel);
- if (!tabent)
- return -ESRCH;
-
- //FIXME enable/disable band select upper20 in RXCTL
- if (0 /*FIXME 5Ghz*/)
- b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
- else
- b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
- b43_chantab_radio_upload(dev, tabent);
- udelay(50);
- b43_radio_write16(dev, B2055_VCO_CAL10, 5);
- b43_radio_write16(dev, B2055_VCO_CAL10, 45);
- b43_radio_write16(dev, B2055_VCO_CAL10, 65);
- udelay(300);
- if (0 /*FIXME 5Ghz*/)
- b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
- else
- b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
- b43_chantab_phy_upload(dev, tabent);
- b43_nphy_tx_power_fix(dev);
-
- return 0;
-}
-
-static void b43_radio_init2055_pre(struct b43_wldev *dev)
-{
- b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
- ~B43_NPHY_RFCTL_CMD_PORFORCE);
- b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
- B43_NPHY_RFCTL_CMD_CHIP0PU |
- B43_NPHY_RFCTL_CMD_OEPORFORCE);
- b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
- B43_NPHY_RFCTL_CMD_PORFORCE);
-}
-
-static void b43_radio_init2055_post(struct b43_wldev *dev)
-{
- struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
- struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
- int i;
- u16 val;
-
- b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
- msleep(1);
- if ((sprom->revision != 4) || !(sprom->boardflags_hi & 0x0002)) {
- if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
- (binfo->type != 0x46D) ||
- (binfo->rev < 0x41)) {
- b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
- b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
- msleep(1);
- }
- }
- b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
- msleep(1);
- b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
- msleep(1);
- b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
- msleep(1);
- b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
- msleep(1);
- b43_radio_set(dev, B2055_CAL_MISC, 0x1);
- msleep(1);
- b43_radio_set(dev, B2055_CAL_MISC, 0x40);
- msleep(1);
- for (i = 0; i < 100; i++) {
- val = b43_radio_read16(dev, B2055_CAL_COUT2);
- if (val & 0x80)
- break;
- udelay(10);
- }
- msleep(1);
- b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
- msleep(1);
- b43_radio_selectchannel(dev, dev->phy.channel, 0);
- b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
- b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
- b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
- b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
-}
-
-/* Initialize a Broadcom 2055 N-radio */
-static void b43_radio_init2055(struct b43_wldev *dev)
-{
- b43_radio_init2055_pre(dev);
- if (b43_status(dev) < B43_STAT_INITIALIZED)
- b2055_upload_inittab(dev, 0, 1);
- else
- b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
- b43_radio_init2055_post(dev);
-}
-
-void b43_nphy_radio_turn_on(struct b43_wldev *dev)
-{
- b43_radio_init2055(dev);
-}
-
-void b43_nphy_radio_turn_off(struct b43_wldev *dev)
-{
- b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
- ~B43_NPHY_RFCTL_CMD_EN);
-}
-
-#define ntab_upload(dev, offset, data) do { \
- unsigned int i; \
- for (i = 0; i < (offset##_SIZE); i++) \
- b43_ntab_write(dev, (offset) + i, (data)[i]); \
- } while (0)
-
-/* Upload the N-PHY tables. */
-static void b43_nphy_tables_init(struct b43_wldev *dev)
-{
- /* Static tables */
- ntab_upload(dev, B43_NTAB_FRAMESTRUCT, b43_ntab_framestruct);
- ntab_upload(dev, B43_NTAB_FRAMELT, b43_ntab_framelookup);
- ntab_upload(dev, B43_NTAB_TMAP, b43_ntab_tmap);
- ntab_upload(dev, B43_NTAB_TDTRN, b43_ntab_tdtrn);
- ntab_upload(dev, B43_NTAB_INTLEVEL, b43_ntab_intlevel);
- ntab_upload(dev, B43_NTAB_PILOT, b43_ntab_pilot);
- ntab_upload(dev, B43_NTAB_PILOTLT, b43_ntab_pilotlt);
- ntab_upload(dev, B43_NTAB_TDI20A0, b43_ntab_tdi20a0);
- ntab_upload(dev, B43_NTAB_TDI20A1, b43_ntab_tdi20a1);
- ntab_upload(dev, B43_NTAB_TDI40A0, b43_ntab_tdi40a0);
- ntab_upload(dev, B43_NTAB_TDI40A1, b43_ntab_tdi40a1);
- ntab_upload(dev, B43_NTAB_BDI, b43_ntab_bdi);
- ntab_upload(dev, B43_NTAB_CHANEST, b43_ntab_channelest);
- ntab_upload(dev, B43_NTAB_MCS, b43_ntab_mcs);
-
- /* Volatile tables */
- ntab_upload(dev, B43_NTAB_NOISEVAR10, b43_ntab_noisevar10);
- ntab_upload(dev, B43_NTAB_NOISEVAR11, b43_ntab_noisevar11);
- ntab_upload(dev, B43_NTAB_C0_ESTPLT, b43_ntab_estimatepowerlt0);
- ntab_upload(dev, B43_NTAB_C1_ESTPLT, b43_ntab_estimatepowerlt1);
- ntab_upload(dev, B43_NTAB_C0_ADJPLT, b43_ntab_adjustpower0);
- ntab_upload(dev, B43_NTAB_C1_ADJPLT, b43_ntab_adjustpower1);
- ntab_upload(dev, B43_NTAB_C0_GAINCTL, b43_ntab_gainctl0);
- ntab_upload(dev, B43_NTAB_C1_GAINCTL, b43_ntab_gainctl1);
- ntab_upload(dev, B43_NTAB_C0_IQLT, b43_ntab_iqlt0);
- ntab_upload(dev, B43_NTAB_C1_IQLT, b43_ntab_iqlt1);
- ntab_upload(dev, B43_NTAB_C0_LOFEEDTH, b43_ntab_loftlt0);
- ntab_upload(dev, B43_NTAB_C1_LOFEEDTH, b43_ntab_loftlt1);
-}
-
-static void b43_nphy_workarounds(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- unsigned int i;
-
- b43_phy_set(dev, B43_NPHY_IQFLIP,
- B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
- if (1 /* FIXME band is 2.4GHz */) {
- b43_phy_set(dev, B43_NPHY_CLASSCTL,
- B43_NPHY_CLASSCTL_CCKEN);
- } else {
- b43_phy_mask(dev, B43_NPHY_CLASSCTL,
- ~B43_NPHY_CLASSCTL_CCKEN);
- }
- b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
- b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8);
-
- /* Fixup some tables */
- b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA);
- b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA);
- b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
- b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
- b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0);
- b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0);
- b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
- b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
- b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800);
- b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800);
-
- b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
- b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
- b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
- b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
-
- //TODO set RF sequence
-
- /* Set narrowband clip threshold */
- b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66);
- b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66);
-
- /* Set wideband clip 2 threshold */
- b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
- ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
- 21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT);
- b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
- ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
- 21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT);
-
- /* Set Clip 2 detect */
- b43_phy_set(dev, B43_NPHY_C1_CGAINI,
- B43_NPHY_C1_CGAINI_CL2DETECT);
- b43_phy_set(dev, B43_NPHY_C2_CGAINI,
- B43_NPHY_C2_CGAINI_CL2DETECT);
-
- if (0 /*FIXME*/) {
- /* Set dwell lengths */
- b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43);
- b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43);
- b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9);
- b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9);
-
- /* Set gain backoff */
- b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
- ~B43_NPHY_C1_CGAINI_GAINBKOFF,
- 1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT);
- b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
- ~B43_NPHY_C2_CGAINI_GAINBKOFF,
- 1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT);
-
- /* Set HPVGA2 index */
- b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
- ~B43_NPHY_C1_INITGAIN_HPVGA2,
- 6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
- b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
- ~B43_NPHY_C2_INITGAIN_HPVGA2,
- 6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
-
- //FIXME verify that the specs really mean to use autoinc here.
- for (i = 0; i < 3; i++)
- b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673);
- }
-
- /* Set minimum gain value */
- b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN,
- ~B43_NPHY_C1_MINGAIN,
- 23 << B43_NPHY_C1_MINGAIN_SHIFT);
- b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN,
- ~B43_NPHY_C2_MINGAIN,
- 23 << B43_NPHY_C2_MINGAIN_SHIFT);
-
- if (phy->rev < 2) {
- b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
- ~B43_NPHY_SCRAM_SIGCTL_SCM);
- }
-
- /* Set phase track alpha and beta */
- b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
- b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
- b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
- b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
- b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
- b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
-}
-
-static void b43_nphy_reset_cca(struct b43_wldev *dev)
-{
- u16 bbcfg;
-
- ssb_write32(dev->dev, SSB_TMSLOW,
- ssb_read32(dev->dev, SSB_TMSLOW) | SSB_TMSLOW_FGC);
- bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
- b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTCCA);
- b43_phy_write(dev, B43_NPHY_BBCFG,
- bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
- ssb_write32(dev->dev, SSB_TMSLOW,
- ssb_read32(dev->dev, SSB_TMSLOW) & ~SSB_TMSLOW_FGC);
-}
-
-enum b43_nphy_rf_sequence {
- B43_RFSEQ_RX2TX,
- B43_RFSEQ_TX2RX,
- B43_RFSEQ_RESET2RX,
- B43_RFSEQ_UPDATE_GAINH,
- B43_RFSEQ_UPDATE_GAINL,
- B43_RFSEQ_UPDATE_GAINU,
-};
-
-static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
- enum b43_nphy_rf_sequence seq)
-{
- static const u16 trigger[] = {
- [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
- [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
- [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
- [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
- [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
- [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
- };
- int i;
-
- B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
-
- b43_phy_set(dev, B43_NPHY_RFSEQMODE,
- B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
- b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
- for (i = 0; i < 200; i++) {
- if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
- goto ok;
- msleep(1);
- }
- b43err(dev->wl, "RF sequence status timeout\n");
-ok:
- b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
- ~(B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER));
-}
-
-static void b43_nphy_bphy_init(struct b43_wldev *dev)
-{
- unsigned int i;
- u16 val;
-
- val = 0x1E1F;
- for (i = 0; i < 14; i++) {
- b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
- val -= 0x202;
- }
- val = 0x3E3F;
- for (i = 0; i < 16; i++) {
- b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
- val -= 0x202;
- }
- b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
-}
-
-/* RSSI Calibration */
-static void b43_nphy_rssi_cal(struct b43_wldev *dev, u8 type)
-{
- //TODO
-}
-
-int b43_phy_initn(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- u16 tmp;
-
- //TODO: Spectral management
- b43_nphy_tables_init(dev);
-
- /* Clear all overrides */
- b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
- b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
- b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
- b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
- b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
- b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
- ~(B43_NPHY_RFSEQMODE_CAOVER |
- B43_NPHY_RFSEQMODE_TROVER));
- b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
-
- tmp = (phy->rev < 2) ? 64 : 59;
- b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
- ~B43_NPHY_BPHY_CTL3_SCALE,
- tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
-
- b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
- b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
-
- b43_phy_write(dev, B43_NPHY_TXREALFD, 184);
- b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 200);
- b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 80);
- b43_phy_write(dev, B43_NPHY_C2_BCLIPBKOFF, 511);
-
- //TODO MIMO-Config
- //TODO Update TX/RX chain
-
- if (phy->rev < 2) {
- b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
- b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
- }
- b43_nphy_workarounds(dev);
- b43_nphy_reset_cca(dev);
-
- ssb_write32(dev->dev, SSB_TMSLOW,
- ssb_read32(dev->dev, SSB_TMSLOW) | B43_TMSLOW_MACPHYCLKEN);
- b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
- b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
-
- b43_phy_read(dev, B43_NPHY_CLASSCTL); /* dummy read */
- //TODO read core1/2 clip1 thres regs
-
- if (1 /* FIXME Band is 2.4GHz */)
- b43_nphy_bphy_init(dev);
- //TODO disable TX power control
- //TODO Fix the TX power settings
- //TODO Init periodic calibration with reason 3
- b43_nphy_rssi_cal(dev, 2);
- b43_nphy_rssi_cal(dev, 0);
- b43_nphy_rssi_cal(dev, 1);
- //TODO get TX gain
- //TODO init superswitch
- //TODO calibrate LO
- //TODO idle TSSI TX pctl
- //TODO TX power control power setup
- //TODO table writes
- //TODO TX power control coefficients
- //TODO enable TX power control
- //TODO control antenna selection
- //TODO init radar detection
- //TODO reset channel if changed
-
- b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
- return 0;
-}
-#ifndef B43_NPHY_H_
-#define B43_NPHY_H_
-
-#include "phy.h"
-
-
-/* N-PHY registers. */
-
-#define B43_NPHY_BBCFG B43_PHY_N(0x001) /* BB config */
-#define B43_NPHY_BBCFG_RSTCCA 0x4000 /* Reset CCA */
-#define B43_NPHY_BBCFG_RSTRX 0x8000 /* Reset RX */
-#define B43_NPHY_CHANNEL B43_PHY_N(0x005) /* Channel */
-#define B43_NPHY_TXERR B43_PHY_N(0x007) /* TX error */
-#define B43_NPHY_BANDCTL B43_PHY_N(0x009) /* Band control */
-#define B43_NPHY_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
-#define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */
-#define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */
-#define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */
-#define B43_NPHY_BIST_STAT0 B43_PHY_N(0x00E) /* Built-in self test status 0 */
-#define B43_NPHY_BIST_STAT1 B43_PHY_N(0x00F) /* Built-in self test status 1 */
-
-#define B43_NPHY_C1_DESPWR B43_PHY_N(0x018) /* Core 1 desired power */
-#define B43_NPHY_C1_CCK_DESPWR B43_PHY_N(0x019) /* Core 1 CCK desired power */
-#define B43_NPHY_C1_BCLIPBKOFF B43_PHY_N(0x01A) /* Core 1 barely clip backoff */
-#define B43_NPHY_C1_CCK_BCLIPBKOFF B43_PHY_N(0x01B) /* Core 1 CCK barely clip backoff */
-#define B43_NPHY_C1_CGAINI B43_PHY_N(0x01C) /* Core 1 compute gain info */
-#define B43_NPHY_C1_CGAINI_GAINBKOFF 0x001F /* Gain backoff */
-#define B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT 0
-#define B43_NPHY_C1_CGAINI_CLIPGBKOFF 0x03E0 /* Clip gain backoff */
-#define B43_NPHY_C1_CGAINI_CLIPGBKOFF_SHIFT 5
-#define B43_NPHY_C1_CGAINI_GAINSTEP 0x1C00 /* Gain step */
-#define B43_NPHY_C1_CGAINI_GAINSTEP_SHIFT 10
-#define B43_NPHY_C1_CGAINI_CL2DETECT 0x2000 /* Clip 2 detect mask */
-#define B43_NPHY_C1_CCK_CGAINI B43_PHY_N(0x01D) /* Core 1 CCK compute gain info */
-#define B43_NPHY_C1_CCK_CGAINI_GAINBKOFF 0x001F /* Gain backoff */
-#define B43_NPHY_C1_CCK_CGAINI_CLIPGBKOFF 0x01E0 /* CCK barely clip gain backoff */
-#define B43_NPHY_C1_MINMAX_GAIN B43_PHY_N(0x01E) /* Core 1 min/max gain */
-#define B43_NPHY_C1_MINGAIN 0x00FF /* Minimum gain */
-#define B43_NPHY_C1_MINGAIN_SHIFT 0
-#define B43_NPHY_C1_MAXGAIN 0xFF00 /* Maximum gain */
-#define B43_NPHY_C1_MAXGAIN_SHIFT 8
-#define B43_NPHY_C1_CCK_MINMAX_GAIN B43_PHY_N(0x01F) /* Core 1 CCK min/max gain */
-#define B43_NPHY_C1_CCK_MINGAIN 0x00FF /* Minimum gain */
-#define B43_NPHY_C1_CCK_MINGAIN_SHIFT 0
-#define B43_NPHY_C1_CCK_MAXGAIN 0xFF00 /* Maximum gain */
-#define B43_NPHY_C1_CCK_MAXGAIN_SHIFT 8
-#define B43_NPHY_C1_INITGAIN B43_PHY_N(0x020) /* Core 1 initial gain code */
-#define B43_NPHY_C1_INITGAIN_EXTLNA 0x0001 /* External LNA index */
-#define B43_NPHY_C1_INITGAIN_LNA 0x0006 /* LNA index */
-#define B43_NPHY_C1_INITGAIN_LNAIDX_SHIFT 1
-#define B43_NPHY_C1_INITGAIN_HPVGA1 0x0078 /* HPVGA1 index */
-#define B43_NPHY_C1_INITGAIN_HPVGA1_SHIFT 3
-#define B43_NPHY_C1_INITGAIN_HPVGA2 0x0F80 /* HPVGA2 index */
-#define B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT 7
-#define B43_NPHY_C1_INITGAIN_TRRX 0x1000 /* TR RX index */
-#define B43_NPHY_C1_INITGAIN_TRTX 0x2000 /* TR TX index */
-#define B43_NPHY_C1_CLIP1_HIGAIN B43_PHY_N(0x021) /* Core 1 clip1 high gain code */
-#define B43_NPHY_C1_CLIP1_MEDGAIN B43_PHY_N(0x022) /* Core 1 clip1 medium gain code */
-#define B43_NPHY_C1_CLIP1_LOGAIN B43_PHY_N(0x023) /* Core 1 clip1 low gain code */
-#define B43_NPHY_C1_CLIP2_GAIN B43_PHY_N(0x024) /* Core 1 clip2 gain code */
-#define B43_NPHY_C1_FILTERGAIN B43_PHY_N(0x025) /* Core 1 filter gain */
-#define B43_NPHY_C1_LPF_QHPF_BW B43_PHY_N(0x026) /* Core 1 LPF Q HP F bandwidth */
-#define B43_NPHY_C1_CLIPWBTHRES B43_PHY_N(0x027) /* Core 1 clip wideband threshold */
-#define B43_NPHY_C1_CLIPWBTHRES_CLIP2 0x003F /* Clip 2 */
-#define B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT 0
-#define B43_NPHY_C1_CLIPWBTHRES_CLIP1 0x0FC0 /* Clip 1 */
-#define B43_NPHY_C1_CLIPWBTHRES_CLIP1_SHIFT 6
-#define B43_NPHY_C1_W1THRES B43_PHY_N(0x028) /* Core 1 W1 threshold */
-#define B43_NPHY_C1_EDTHRES B43_PHY_N(0x029) /* Core 1 ED threshold */
-#define B43_NPHY_C1_SMSIGTHRES B43_PHY_N(0x02A) /* Core 1 small sig threshold */
-#define B43_NPHY_C1_NBCLIPTHRES B43_PHY_N(0x02B) /* Core 1 NB clip threshold */
-#define B43_NPHY_C1_CLIP1THRES B43_PHY_N(0x02C) /* Core 1 clip1 threshold */
-#define B43_NPHY_C1_CLIP2THRES B43_PHY_N(0x02D) /* Core 1 clip2 threshold */
-
-#define B43_NPHY_C2_DESPWR B43_PHY_N(0x02E) /* Core 2 desired power */
-#define B43_NPHY_C2_CCK_DESPWR B43_PHY_N(0x02F) /* Core 2 CCK desired power */
-#define B43_NPHY_C2_BCLIPBKOFF B43_PHY_N(0x030) /* Core 2 barely clip backoff */
-#define B43_NPHY_C2_CCK_BCLIPBKOFF B43_PHY_N(0x031) /* Core 2 CCK barely clip backoff */
-#define B43_NPHY_C2_CGAINI B43_PHY_N(0x032) /* Core 2 compute gain info */
-#define B43_NPHY_C2_CGAINI_GAINBKOFF 0x001F /* Gain backoff */
-#define B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT 0
-#define B43_NPHY_C2_CGAINI_CLIPGBKOFF 0x03E0 /* Clip gain backoff */
-#define B43_NPHY_C2_CGAINI_CLIPGBKOFF_SHIFT 5
-#define B43_NPHY_C2_CGAINI_GAINSTEP 0x1C00 /* Gain step */
-#define B43_NPHY_C2_CGAINI_GAINSTEP_SHIFT 10
-#define B43_NPHY_C2_CGAINI_CL2DETECT 0x2000 /* Clip 2 detect mask */
-#define B43_NPHY_C2_CCK_CGAINI B43_PHY_N(0x033) /* Core 2 CCK compute gain info */
-#define B43_NPHY_C2_CCK_CGAINI_GAINBKOFF 0x001F /* Gain backoff */
-#define B43_NPHY_C2_CCK_CGAINI_CLIPGBKOFF 0x01E0 /* CCK barely clip gain backoff */
-#define B43_NPHY_C2_MINMAX_GAIN B43_PHY_N(0x034) /* Core 2 min/max gain */
-#define B43_NPHY_C2_MINGAIN 0x00FF /* Minimum gain */
-#define B43_NPHY_C2_MINGAIN_SHIFT 0
-#define B43_NPHY_C2_MAXGAIN 0xFF00 /* Maximum gain */
-#define B43_NPHY_C2_MAXGAIN_SHIFT 8
-#define B43_NPHY_C2_CCK_MINMAX_GAIN B43_PHY_N(0x035) /* Core 2 CCK min/max gain */
-#define B43_NPHY_C2_CCK_MINGAIN 0x00FF /* Minimum gain */
-#define B43_NPHY_C2_CCK_MINGAIN_SHIFT 0
-#define B43_NPHY_C2_CCK_MAXGAIN 0xFF00 /* Maximum gain */
-#define B43_NPHY_C2_CCK_MAXGAIN_SHIFT 8
-#define B43_NPHY_C2_INITGAIN B43_PHY_N(0x036) /* Core 2 initial gain code */
-#define B43_NPHY_C2_INITGAIN_EXTLNA 0x0001 /* External LNA index */
-#define B43_NPHY_C2_INITGAIN_LNA 0x0006 /* LNA index */
-#define B43_NPHY_C2_INITGAIN_LNAIDX_SHIFT 1
-#define B43_NPHY_C2_INITGAIN_HPVGA1 0x0078 /* HPVGA1 index */
-#define B43_NPHY_C2_INITGAIN_HPVGA1_SHIFT 3
-#define B43_NPHY_C2_INITGAIN_HPVGA2 0x0F80 /* HPVGA2 index */
-#define B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT 7
-#define B43_NPHY_C2_INITGAIN_TRRX 0x1000 /* TR RX index */
-#define B43_NPHY_C2_INITGAIN_TRTX 0x2000 /* TR TX index */
-#define B43_NPHY_C2_CLIP1_HIGAIN B43_PHY_N(0x037) /* Core 2 clip1 high gain code */
-#define B43_NPHY_C2_CLIP1_MEDGAIN B43_PHY_N(0x038) /* Core 2 clip1 medium gain code */
-#define B43_NPHY_C2_CLIP1_LOGAIN B43_PHY_N(0x039) /* Core 2 clip1 low gain code */
-#define B43_NPHY_C2_CLIP2_GAIN B43_PHY_N(0x03A) /* Core 2 clip2 gain code */
-#define B43_NPHY_C2_FILTERGAIN B43_PHY_N(0x03B) /* Core 2 filter gain */
-#define B43_NPHY_C2_LPF_QHPF_BW B43_PHY_N(0x03C) /* Core 2 LPF Q HP F bandwidth */
-#define B43_NPHY_C2_CLIPWBTHRES B43_PHY_N(0x03D) /* Core 2 clip wideband threshold */
-#define B43_NPHY_C2_CLIPWBTHRES_CLIP2 0x003F /* Clip 2 */
-#define B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT 0
-#define B43_NPHY_C2_CLIPWBTHRES_CLIP1 0x0FC0 /* Clip 1 */
-#define B43_NPHY_C2_CLIPWBTHRES_CLIP1_SHIFT 6
-#define B43_NPHY_C2_W1THRES B43_PHY_N(0x03E) /* Core 2 W1 threshold */
-#define B43_NPHY_C2_EDTHRES B43_PHY_N(0x03F) /* Core 2 ED threshold */
-#define B43_NPHY_C2_SMSIGTHRES B43_PHY_N(0x040) /* Core 2 small sig threshold */
-#define B43_NPHY_C2_NBCLIPTHRES B43_PHY_N(0x041) /* Core 2 NB clip threshold */
-#define B43_NPHY_C2_CLIP1THRES B43_PHY_N(0x042) /* Core 2 clip1 threshold */
-#define B43_NPHY_C2_CLIP2THRES B43_PHY_N(0x043) /* Core 2 clip2 threshold */
-
-#define B43_NPHY_CRS_THRES1 B43_PHY_N(0x044) /* CRS threshold 1 */
-#define B43_NPHY_CRS_THRES2 B43_PHY_N(0x045) /* CRS threshold 2 */
-#define B43_NPHY_CRS_THRES3 B43_PHY_N(0x046) /* CRS threshold 3 */
-#define B43_NPHY_CRSCTL B43_PHY_N(0x047) /* CRS control */
-#define B43_NPHY_DCFADDR B43_PHY_N(0x048) /* DC filter address */
-#define B43_NPHY_RXF20_NUM0 B43_PHY_N(0x049) /* RX filter 20 numerator 0 */
-#define B43_NPHY_RXF20_NUM1 B43_PHY_N(0x04A) /* RX filter 20 numerator 1 */
-#define B43_NPHY_RXF20_NUM2 B43_PHY_N(0x04B) /* RX filter 20 numerator 2 */
-#define B43_NPHY_RXF20_DENOM0 B43_PHY_N(0x04C) /* RX filter 20 denominator 0 */
-#define B43_NPHY_RXF20_DENOM1 B43_PHY_N(0x04D) /* RX filter 20 denominator 1 */
-#define B43_NPHY_RXF20_NUM10 B43_PHY_N(0x04E) /* RX filter 20 numerator 10 */
-#define B43_NPHY_RXF20_NUM11 B43_PHY_N(0x04F) /* RX filter 20 numerator 11 */
-#define B43_NPHY_RXF20_NUM12 B43_PHY_N(0x050) /* RX filter 20 numerator 12 */
-#define B43_NPHY_RXF20_DENOM10 B43_PHY_N(0x051) /* RX filter 20 denominator 10 */
-#define B43_NPHY_RXF20_DENOM11 B43_PHY_N(0x052) /* RX filter 20 denominator 11 */
-#define B43_NPHY_RXF40_NUM0 B43_PHY_N(0x053) /* RX filter 40 numerator 0 */
-#define B43_NPHY_RXF40_NUM1 B43_PHY_N(0x054) /* RX filter 40 numerator 1 */
-#define B43_NPHY_RXF40_NUM2 B43_PHY_N(0x055) /* RX filter 40 numerator 2 */
-#define B43_NPHY_RXF40_DENOM0 B43_PHY_N(0x056) /* RX filter 40 denominator 0 */
-#define B43_NPHY_RXF40_DENOM1 B43_PHY_N(0x057) /* RX filter 40 denominator 1 */
-#define B43_NPHY_RXF40_NUM10 B43_PHY_N(0x058) /* RX filter 40 numerator 10 */
-#define B43_NPHY_RXF40_NUM11 B43_PHY_N(0x059) /* RX filter 40 numerator 11 */
-#define B43_NPHY_RXF40_NUM12 B43_PHY_N(0x05A) /* RX filter 40 numerator 12 */
-#define B43_NPHY_RXF40_DENOM10 B43_PHY_N(0x05B) /* RX filter 40 denominator 10 */
-#define B43_NPHY_RXF40_DENOM11 B43_PHY_N(0x05C) /* RX filter 40 denominator 11 */
-#define B43_NPHY_PPROC_RSTLEN B43_PHY_N(0x060) /* Packet processing reset length */
-#define B43_NPHY_INITCARR_DLEN B43_PHY_N(0x061) /* Initial carrier detection length */
-#define B43_NPHY_CLIP1CARR_DLEN B43_PHY_N(0x062) /* Clip1 carrier detection length */
-#define B43_NPHY_CLIP2CARR_DLEN B43_PHY_N(0x063) /* Clip2 carrier detection length */
-#define B43_NPHY_INITGAIN_SLEN B43_PHY_N(0x064) /* Initial gain settle length */
-#define B43_NPHY_CLIP1GAIN_SLEN B43_PHY_N(0x065) /* Clip1 gain settle length */
-#define B43_NPHY_CLIP2GAIN_SLEN B43_PHY_N(0x066) /* Clip2 gain settle length */
-#define B43_NPHY_PACKGAIN_SLEN B43_PHY_N(0x067) /* Packet gain settle length */
-#define B43_NPHY_CARRSRC_TLEN B43_PHY_N(0x068) /* Carrier search timeout length */
-#define B43_NPHY_TISRC_TLEN B43_PHY_N(0x069) /* Timing search timeout length */
-#define B43_NPHY_ENDROP_TLEN B43_PHY_N(0x06A) /* Energy drop timeout length */
-#define B43_NPHY_CLIP1_NBDWELL_LEN B43_PHY_N(0x06B) /* Clip1 NB dwell length */
-#define B43_NPHY_CLIP2_NBDWELL_LEN B43_PHY_N(0x06C) /* Clip2 NB dwell length */
-#define B43_NPHY_W1CLIP1_DWELL_LEN B43_PHY_N(0x06D) /* W1 clip1 dwell length */
-#define B43_NPHY_W1CLIP2_DWELL_LEN B43_PHY_N(0x06E) /* W1 clip2 dwell length */
-#define B43_NPHY_W2CLIP1_DWELL_LEN B43_PHY_N(0x06F) /* W2 clip1 dwell length */
-#define B43_NPHY_PLOAD_CSENSE_EXTLEN B43_PHY_N(0x070) /* Payload carrier sense extension length */
-#define B43_NPHY_EDROP_CSENSE_EXTLEN B43_PHY_N(0x071) /* Energy drop carrier sense extension length */
-#define B43_NPHY_TABLE_ADDR B43_PHY_N(0x072) /* Table address */
-#define B43_NPHY_TABLE_DATALO B43_PHY_N(0x073) /* Table data low */
-#define B43_NPHY_TABLE_DATAHI B43_PHY_N(0x074) /* Table data high */
-#define B43_NPHY_WWISE_LENIDX B43_PHY_N(0x075) /* WWiSE length index */
-#define B43_NPHY_TGNSYNC_LENIDX B43_PHY_N(0x076) /* TGNsync length index */
-#define B43_NPHY_TXMACIF_HOLDOFF B43_PHY_N(0x077) /* TX MAC IF Hold off */
-#define B43_NPHY_RFCTL_CMD B43_PHY_N(0x078) /* RF control (command) */
-#define B43_NPHY_RFCTL_CMD_START 0x0001 /* Start sequence */
-#define B43_NPHY_RFCTL_CMD_RXTX 0x0002 /* RX/TX */
-#define B43_NPHY_RFCTL_CMD_CORESEL 0x0038 /* Core select */
-#define B43_NPHY_RFCTL_CMD_CORESEL_SHIFT 3
-#define B43_NPHY_RFCTL_CMD_PORFORCE 0x0040 /* POR force */
-#define B43_NPHY_RFCTL_CMD_OEPORFORCE 0x0080 /* OE POR force */
-#define B43_NPHY_RFCTL_CMD_RXEN 0x0100 /* RX enable */
-#define B43_NPHY_RFCTL_CMD_TXEN 0x0200 /* TX enable */
-#define B43_NPHY_RFCTL_CMD_CHIP0PU 0x0400 /* Chip0 PU */
-#define B43_NPHY_RFCTL_CMD_EN 0x0800 /* Radio enabled */
-#define B43_NPHY_RFCTL_CMD_SEQENCORE 0xF000 /* Seq en core */
-#define B43_NPHY_RFCTL_CMD_SEQENCORE_SHIFT 12
-#define B43_NPHY_RFCTL_RSSIO1 B43_PHY_N(0x07A) /* RF control (RSSI others 1) */
-#define B43_NPHY_RFCTL_RSSIO1_RXPD 0x0001 /* RX PD */
-#define B43_NPHY_RFCTL_RSSIO1_TXPD 0x0002 /* TX PD */
-#define B43_NPHY_RFCTL_RSSIO1_PAPD 0x0004 /* PA PD */
-#define B43_NPHY_RFCTL_RSSIO1_RSSICTL 0x0030 /* RSSI control */
-#define B43_NPHY_RFCTL_RSSIO1_LPFBW 0x00C0 /* LPF bandwidth */
-#define B43_NPHY_RFCTL_RSSIO1_HPFBWHI 0x0100 /* HPF bandwidth high */
-#define B43_NPHY_RFCTL_RSSIO1_HIQDISCO 0x0200 /* HIQ dis core */
-#define B43_NPHY_RFCTL_RXG1 B43_PHY_N(0x07B) /* RF control (RX gain 1) */
-#define B43_NPHY_RFCTL_TXG1 B43_PHY_N(0x07C) /* RF control (TX gain 1) */
-#define B43_NPHY_RFCTL_RSSIO2 B43_PHY_N(0x07D) /* RF control (RSSI others 2) */
-#define B43_NPHY_RFCTL_RSSIO2_RXPD 0x0001 /* RX PD */
-#define B43_NPHY_RFCTL_RSSIO2_TXPD 0x0002 /* TX PD */
-#define B43_NPHY_RFCTL_RSSIO2_PAPD 0x0004 /* PA PD */
-#define B43_NPHY_RFCTL_RSSIO2_RSSICTL 0x0030 /* RSSI control */
-#define B43_NPHY_RFCTL_RSSIO2_LPFBW 0x00C0 /* LPF bandwidth */
-#define B43_NPHY_RFCTL_RSSIO2_HPFBWHI 0x0100 /* HPF bandwidth high */
-#define B43_NPHY_RFCTL_RSSIO2_HIQDISCO 0x0200 /* HIQ dis core */
-#define B43_NPHY_RFCTL_RXG2 B43_PHY_N(0x07E) /* RF control (RX gain 2) */
-#define B43_NPHY_RFCTL_TXG2 B43_PHY_N(0x07F) /* RF control (TX gain 2) */
-#define B43_NPHY_RFCTL_RSSIO3 B43_PHY_N(0x080) /* RF control (RSSI others 3) */
-#define B43_NPHY_RFCTL_RSSIO3_RXPD 0x0001 /* RX PD */
-#define B43_NPHY_RFCTL_RSSIO3_TXPD 0x0002 /* TX PD */
-#define B43_NPHY_RFCTL_RSSIO3_PAPD 0x0004 /* PA PD */
-#define B43_NPHY_RFCTL_RSSIO3_RSSICTL 0x0030 /* RSSI control */
-#define B43_NPHY_RFCTL_RSSIO3_LPFBW 0x00C0 /* LPF bandwidth */
-#define B43_NPHY_RFCTL_RSSIO3_HPFBWHI 0x0100 /* HPF bandwidth high */
-#define B43_NPHY_RFCTL_RSSIO3_HIQDISCO 0x0200 /* HIQ dis core */
-#define B43_NPHY_RFCTL_RXG3 B43_PHY_N(0x081) /* RF control (RX gain 3) */
-#define B43_NPHY_RFCTL_TXG3 B43_PHY_N(0x082) /* RF control (TX gain 3) */
-#define B43_NPHY_RFCTL_RSSIO4 B43_PHY_N(0x083) /* RF control (RSSI others 4) */
-#define B43_NPHY_RFCTL_RSSIO4_RXPD 0x0001 /* RX PD */
-#define B43_NPHY_RFCTL_RSSIO4_TXPD 0x0002 /* TX PD */
-#define B43_NPHY_RFCTL_RSSIO4_PAPD 0x0004 /* PA PD */
-#define B43_NPHY_RFCTL_RSSIO4_RSSICTL 0x0030 /* RSSI control */
-#define B43_NPHY_RFCTL_RSSIO4_LPFBW 0x00C0 /* LPF bandwidth */
-#define B43_NPHY_RFCTL_RSSIO4_HPFBWHI 0x0100 /* HPF bandwidth high */
-#define B43_NPHY_RFCTL_RSSIO4_HIQDISCO 0x0200 /* HIQ dis core */
-#define B43_NPHY_RFCTL_RXG4 B43_PHY_N(0x084) /* RF control (RX gain 4) */
-#define B43_NPHY_RFCTL_TXG4 B43_PHY_N(0x085) /* RF control (TX gain 4) */
-#define B43_NPHY_C1_TXIQ_COMP_OFF B43_PHY_N(0x087) /* Core 1 TX I/Q comp offset */
-#define B43_NPHY_C2_TXIQ_COMP_OFF B43_PHY_N(0x088) /* Core 2 TX I/Q comp offset */
-#define B43_NPHY_C1_TXCTL B43_PHY_N(0x08B) /* Core 1 TX control */
-#define B43_NPHY_C2_TXCTL B43_PHY_N(0x08C) /* Core 2 TX control */
-#define B43_NPHY_SCRAM_SIGCTL B43_PHY_N(0x090) /* Scram signal control */
-#define B43_NPHY_SCRAM_SIGCTL_INITST 0x007F /* Initial state value */
-#define B43_NPHY_SCRAM_SIGCTL_INITST_SHIFT 0
-#define B43_NPHY_SCRAM_SIGCTL_SCM 0x0080 /* Scram control mode */
-#define B43_NPHY_SCRAM_SIGCTL_SICE 0x0100 /* Scram index control enable */
-#define B43_NPHY_SCRAM_SIGCTL_START 0xFE00 /* Scram start bit */
-#define B43_NPHY_SCRAM_SIGCTL_START_SHIFT 9
-#define B43_NPHY_RFCTL_INTC1 B43_PHY_N(0x091) /* RF control (intc 1) */
-#define B43_NPHY_RFCTL_INTC2 B43_PHY_N(0x092) /* RF control (intc 2) */
-#define B43_NPHY_RFCTL_INTC3 B43_PHY_N(0x093) /* RF control (intc 3) */
-#define B43_NPHY_RFCTL_INTC4 B43_PHY_N(0x094) /* RF control (intc 4) */
-#define B43_NPHY_NRDTO_WWISE B43_PHY_N(0x095) /* # datatones WWiSE */
-#define B43_NPHY_NRDTO_TGNSYNC B43_PHY_N(0x096) /* # datatones TGNsync */
-#define B43_NPHY_SIGFMOD_WWISE B43_PHY_N(0x097) /* Signal field mod WWiSE */
-#define B43_NPHY_LEG_SIGFMOD_11N B43_PHY_N(0x098) /* Legacy signal field mod 11n */
-#define B43_NPHY_HT_SIGFMOD_11N B43_PHY_N(0x099) /* HT signal field mod 11n */
-#define B43_NPHY_C1_RXIQ_COMPA0 B43_PHY_N(0x09A) /* Core 1 RX I/Q comp A0 */
-#define B43_NPHY_C1_RXIQ_COMPB0 B43_PHY_N(0x09B) /* Core 1 RX I/Q comp B0 */
-#define B43_NPHY_C2_RXIQ_COMPA1 B43_PHY_N(0x09C) /* Core 2 RX I/Q comp A1 */
-#define B43_NPHY_C2_RXIQ_COMPB1 B43_PHY_N(0x09D) /* Core 2 RX I/Q comp B1 */
-#define B43_NPHY_RXCTL B43_PHY_N(0x0A0) /* RX control */
-#define B43_NPHY_RXCTL_BSELU20 0x0010 /* Band select upper 20 */
-#define B43_NPHY_RXCTL_RIFSEN 0x0080 /* RIFS enable */
-#define B43_NPHY_RFSEQMODE B43_PHY_N(0x0A1) /* RF seq mode */
-#define B43_NPHY_RFSEQMODE_CAOVER 0x0001 /* Core active override */
-#define B43_NPHY_RFSEQMODE_TROVER 0x0002 /* Trigger override */
-#define B43_NPHY_RFSEQCA B43_PHY_N(0x0A2) /* RF seq core active */
-#define B43_NPHY_RFSEQCA_TXEN 0x000F /* TX enable */
-#define B43_NPHY_RFSEQCA_TXEN_SHIFT 0
-#define B43_NPHY_RFSEQCA_RXEN 0x00F0 /* RX enable */
-#define B43_NPHY_RFSEQCA_RXEN_SHIFT 4
-#define B43_NPHY_RFSEQCA_TXDIS 0x0F00 /* TX disable */
-#define B43_NPHY_RFSEQCA_TXDIS_SHIFT 8
-#define B43_NPHY_RFSEQCA_RXDIS 0xF000 /* RX disable */
-#define B43_NPHY_RFSEQCA_RXDIS_SHIFT 12
-#define B43_NPHY_RFSEQTR B43_PHY_N(0x0A3) /* RF seq trigger */
-#define B43_NPHY_RFSEQTR_RX2TX 0x0001 /* RX2TX */
-#define B43_NPHY_RFSEQTR_TX2RX 0x0002 /* TX2RX */
-#define B43_NPHY_RFSEQTR_UPGH 0x0004 /* Update gain H */
-#define B43_NPHY_RFSEQTR_UPGL 0x0008 /* Update gain L */
-#define B43_NPHY_RFSEQTR_UPGU 0x0010 /* Update gain U */
-#define B43_NPHY_RFSEQTR_RST2RX 0x0020 /* Reset to RX */
-#define B43_NPHY_RFSEQST B43_PHY_N(0x0A4) /* RF seq status. Values same as trigger. */
-#define B43_NPHY_AFECTL_OVER B43_PHY_N(0x0A5) /* AFE control override */
-#define B43_NPHY_AFECTL_C1 B43_PHY_N(0x0A6) /* AFE control core 1 */
-#define B43_NPHY_AFECTL_C2 B43_PHY_N(0x0A7) /* AFE control core 2 */
-#define B43_NPHY_AFECTL_C3 B43_PHY_N(0x0A8) /* AFE control core 3 */
-#define B43_NPHY_AFECTL_C4 B43_PHY_N(0x0A9) /* AFE control core 4 */
-#define B43_NPHY_AFECTL_DACGAIN1 B43_PHY_N(0x0AA) /* AFE control DAC gain 1 */
-#define B43_NPHY_AFECTL_DACGAIN2 B43_PHY_N(0x0AB) /* AFE control DAC gain 2 */
-#define B43_NPHY_AFECTL_DACGAIN3 B43_PHY_N(0x0AC) /* AFE control DAC gain 3 */
-#define B43_NPHY_AFECTL_DACGAIN4 B43_PHY_N(0x0AD) /* AFE control DAC gain 4 */
-#define B43_NPHY_STR_ADDR1 B43_PHY_N(0x0AE) /* STR address 1 */
-#define B43_NPHY_STR_ADDR2 B43_PHY_N(0x0AF) /* STR address 2 */
-#define B43_NPHY_CLASSCTL B43_PHY_N(0x0B0) /* Classifier control */
-#define B43_NPHY_CLASSCTL_CCKEN 0x0001 /* CCK enable */
-#define B43_NPHY_CLASSCTL_OFDMEN 0x0002 /* OFDM enable */
-#define B43_NPHY_CLASSCTL_WAITEDEN 0x0004 /* Waited enable */
-#define B43_NPHY_IQFLIP B43_PHY_N(0x0B1) /* I/Q flip */
-#define B43_NPHY_IQFLIP_ADC1 0x0001 /* ADC1 */
-#define B43_NPHY_IQFLIP_ADC2 0x0010 /* ADC2 */
-#define B43_NPHY_SISO_SNR_THRES B43_PHY_N(0x0B2) /* SISO SNR threshold */
-#define B43_NPHY_SIGMA_N_MULT B43_PHY_N(0x0B3) /* Sigma N multiplier */
-#define B43_NPHY_TXMACDELAY B43_PHY_N(0x0B4) /* TX MAC delay */
-#define B43_NPHY_TXFRAMEDELAY B43_PHY_N(0x0B5) /* TX frame delay */
-#define B43_NPHY_MLPARM B43_PHY_N(0x0B6) /* ML parameters */
-#define B43_NPHY_MLCTL B43_PHY_N(0x0B7) /* ML control */
-#define B43_NPHY_WWISE_20NCYCDAT B43_PHY_N(0x0B8) /* WWiSE 20 N cyc data */
-#define B43_NPHY_WWISE_40NCYCDAT B43_PHY_N(0x0B9) /* WWiSE 40 N cyc data */
-#define B43_NPHY_TGNSYNC_20NCYCDAT B43_PHY_N(0x0BA) /* TGNsync 20 N cyc data */
-#define B43_NPHY_TGNSYNC_40NCYCDAT B43_PHY_N(0x0BB) /* TGNsync 40 N cyc data */
-#define B43_NPHY_INITSWIZP B43_PHY_N(0x0BC) /* Initial swizzle pattern */
-#define B43_NPHY_TXTAILCNT B43_PHY_N(0x0BD) /* TX tail count value */
-#define B43_NPHY_BPHY_CTL1 B43_PHY_N(0x0BE) /* B PHY control 1 */
-#define B43_NPHY_BPHY_CTL2 B43_PHY_N(0x0BF) /* B PHY control 2 */
-#define B43_NPHY_BPHY_CTL2_LUT 0x001F /* LUT index */
-#define B43_NPHY_BPHY_CTL2_LUT_SHIFT 0
-#define B43_NPHY_BPHY_CTL2_MACDEL 0x7FE0 /* MAC delay */
-#define B43_NPHY_BPHY_CTL2_MACDEL_SHIFT 5
-#define B43_NPHY_IQLOCAL_CMD B43_PHY_N(0x0C0) /* I/Q LO cal command */
-#define B43_NPHY_IQLOCAL_CMD_EN 0x8000
-#define B43_NPHY_IQLOCAL_CMDNNUM B43_PHY_N(0x0C1) /* I/Q LO cal command N num */
-#define B43_NPHY_IQLOCAL_CMDGCTL B43_PHY_N(0x0C2) /* I/Q LO cal command G control */
-#define B43_NPHY_SAMP_CMD B43_PHY_N(0x0C3) /* Sample command */
-#define B43_NPHY_SAMP_CMD_STOP 0x0002 /* Stop */
-#define B43_NPHY_SAMP_LOOPCNT B43_PHY_N(0x0C4) /* Sample loop count */
-#define B43_NPHY_SAMP_WAITCNT B43_PHY_N(0x0C5) /* Sample wait count */
-#define B43_NPHY_SAMP_DEPCNT B43_PHY_N(0x0C6) /* Sample depth count */
-#define B43_NPHY_SAMP_STAT B43_PHY_N(0x0C7) /* Sample status */
-#define B43_NPHY_GPIO_LOOEN B43_PHY_N(0x0C8) /* GPIO low out enable */
-#define B43_NPHY_GPIO_HIOEN B43_PHY_N(0x0C9) /* GPIO high out enable */
-#define B43_NPHY_GPIO_SEL B43_PHY_N(0x0CA) /* GPIO select */
-#define B43_NPHY_GPIO_CLKCTL B43_PHY_N(0x0CB) /* GPIO clock control */
-#define B43_NPHY_TXF_20CO_AS0 B43_PHY_N(0x0CC) /* TX filter 20 coeff A stage 0 */
-#define B43_NPHY_TXF_20CO_AS1 B43_PHY_N(0x0CD) /* TX filter 20 coeff A stage 1 */
-#define B43_NPHY_TXF_20CO_AS2 B43_PHY_N(0x0CE) /* TX filter 20 coeff A stage 2 */
-#define B43_NPHY_TXF_20CO_B32S0 B43_PHY_N(0x0CF) /* TX filter 20 coeff B32 stage 0 */
-#define B43_NPHY_TXF_20CO_B1S0 B43_PHY_N(0x0D0) /* TX filter 20 coeff B1 stage 0 */
-#define B43_NPHY_TXF_20CO_B32S1 B43_PHY_N(0x0D1) /* TX filter 20 coeff B32 stage 1 */
-#define B43_NPHY_TXF_20CO_B1S1 B43_PHY_N(0x0D2) /* TX filter 20 coeff B1 stage 1 */
-#define B43_NPHY_TXF_20CO_B32S2 B43_PHY_N(0x0D3) /* TX filter 20 coeff B32 stage 2 */
-#define B43_NPHY_TXF_20CO_B1S2 B43_PHY_N(0x0D4) /* TX filter 20 coeff B1 stage 2 */
-#define B43_NPHY_SIGFLDTOL B43_PHY_N(0x0D5) /* Signal fld tolerance */
-#define B43_NPHY_TXSERFLD B43_PHY_N(0x0D6) /* TX service field */
-#define B43_NPHY_AFESEQ_RX2TX_PUD B43_PHY_N(0x0D7) /* AFE seq RX2TX power up/down delay */
-#define B43_NPHY_AFESEQ_TX2RX_PUD B43_PHY_N(0x0D8) /* AFE seq TX2RX power up/down delay */
-#define B43_NPHY_TGNSYNC_SCRAMI0 B43_PHY_N(0x0D9) /* TGNsync scram init 0 */
-#define B43_NPHY_TGNSYNC_SCRAMI1 B43_PHY_N(0x0DA) /* TGNsync scram init 1 */
-#define B43_NPHY_INITSWIZPATTLEG B43_PHY_N(0x0DB) /* Initial swizzle pattern leg */
-#define B43_NPHY_BPHY_CTL3 B43_PHY_N(0x0DC) /* B PHY control 3 */
-#define B43_NPHY_BPHY_CTL3_SCALE 0x00FF /* Scale */
-#define B43_NPHY_BPHY_CTL3_SCALE_SHIFT 0
-#define B43_NPHY_BPHY_CTL3_FSC 0xFF00 /* Frame start count value */
-#define B43_NPHY_BPHY_CTL3_FSC_SHIFT 8
-#define B43_NPHY_BPHY_CTL4 B43_PHY_N(0x0DD) /* B PHY control 4 */
-#define B43_NPHY_C1_TXBBMULT B43_PHY_N(0x0DE) /* Core 1 TX BB multiplier */
-#define B43_NPHY_C2_TXBBMULT B43_PHY_N(0x0DF) /* Core 2 TX BB multiplier */
-#define B43_NPHY_TXF_40CO_AS0 B43_PHY_N(0x0E1) /* TX filter 40 coeff A stage 0 */
-#define B43_NPHY_TXF_40CO_AS1 B43_PHY_N(0x0E2) /* TX filter 40 coeff A stage 1 */
-#define B43_NPHY_TXF_40CO_AS2 B43_PHY_N(0x0E3) /* TX filter 40 coeff A stage 2 */
-#define B43_NPHY_TXF_40CO_B32S0 B43_PHY_N(0x0E4) /* TX filter 40 coeff B32 stage 0 */
-#define B43_NPHY_TXF_40CO_B1S0 B43_PHY_N(0x0E5) /* TX filter 40 coeff B1 stage 0 */
-#define B43_NPHY_TXF_40CO_B32S1 B43_PHY_N(0x0E6) /* TX filter 40 coeff B32 stage 1 */
-#define B43_NPHY_TXF_40CO_B1S1 B43_PHY_N(0x0E7) /* TX filter 40 coeff B1 stage 1 */
-#define B43_NPHY_TXF_40CO_B32S2 B43_PHY_N(0x0E8) /* TX filter 40 coeff B32 stage 2 */
-#define B43_NPHY_TXF_40CO_B1S2 B43_PHY_N(0x0E9) /* TX filter 40 coeff B1 stage 2 */
-#define B43_NPHY_BIST_STAT2 B43_PHY_N(0x0EA) /* BIST status 2 */
-#define B43_NPHY_BIST_STAT3 B43_PHY_N(0x0EB) /* BIST status 3 */
-#define B43_NPHY_RFCTL_OVER B43_PHY_N(0x0EC) /* RF control override */
-#define B43_NPHY_MIMOCFG B43_PHY_N(0x0ED) /* MIMO config */
-#define B43_NPHY_MIMOCFG_GFMIX 0x0004 /* Greenfield or mixed mode */
-#define B43_NPHY_MIMOCFG_AUTO 0x0100 /* Greenfield/mixed mode auto */
-#define B43_NPHY_RADAR_BLNKCTL B43_PHY_N(0x0EE) /* Radar blank control */
-#define B43_NPHY_A0RADAR_FIFOCTL B43_PHY_N(0x0EF) /* Antenna 0 radar FIFO control */
-#define B43_NPHY_A1RADAR_FIFOCTL B43_PHY_N(0x0F0) /* Antenna 1 radar FIFO control */
-#define B43_NPHY_A0RADAR_FIFODAT B43_PHY_N(0x0F1) /* Antenna 0 radar FIFO data */
-#define B43_NPHY_A1RADAR_FIFODAT B43_PHY_N(0x0F2) /* Antenna 1 radar FIFO data */
-#define B43_NPHY_RADAR_THRES0 B43_PHY_N(0x0F3) /* Radar threshold 0 */
-#define B43_NPHY_RADAR_THRES1 B43_PHY_N(0x0F4) /* Radar threshold 1 */
-#define B43_NPHY_RADAR_THRES0R B43_PHY_N(0x0F5) /* Radar threshold 0R */
-#define B43_NPHY_RADAR_THRES1R B43_PHY_N(0x0F6) /* Radar threshold 1R */
-#define B43_NPHY_CSEN_20IN40_DLEN B43_PHY_N(0x0F7) /* Carrier sense 20 in 40 dwell length */
-#define B43_NPHY_RFCTL_LUT_TRSW_LO1 B43_PHY_N(0x0F8) /* RF control LUT TRSW lower 1 */
-#define B43_NPHY_RFCTL_LUT_TRSW_UP1 B43_PHY_N(0x0F9) /* RF control LUT TRSW upper 1 */
-#define B43_NPHY_RFCTL_LUT_TRSW_LO2 B43_PHY_N(0x0FA) /* RF control LUT TRSW lower 2 */
-#define B43_NPHY_RFCTL_LUT_TRSW_UP2 B43_PHY_N(0x0FB) /* RF control LUT TRSW upper 2 */
-#define B43_NPHY_RFCTL_LUT_TRSW_LO3 B43_PHY_N(0x0FC) /* RF control LUT TRSW lower 3 */
-#define B43_NPHY_RFCTL_LUT_TRSW_UP3 B43_PHY_N(0x0FD) /* RF control LUT TRSW upper 3 */
-#define B43_NPHY_RFCTL_LUT_TRSW_LO4 B43_PHY_N(0x0FE) /* RF control LUT TRSW lower 4 */
-#define B43_NPHY_RFCTL_LUT_TRSW_UP4 B43_PHY_N(0x0FF) /* RF control LUT TRSW upper 4 */
-#define B43_NPHY_RFCTL_LUT_LNAPA1 B43_PHY_N(0x100) /* RF control LUT LNA PA 1 */
-#define B43_NPHY_RFCTL_LUT_LNAPA2 B43_PHY_N(0x101) /* RF control LUT LNA PA 2 */
-#define B43_NPHY_RFCTL_LUT_LNAPA3 B43_PHY_N(0x102) /* RF control LUT LNA PA 3 */
-#define B43_NPHY_RFCTL_LUT_LNAPA4 B43_PHY_N(0x103) /* RF control LUT LNA PA 4 */
-#define B43_NPHY_TGNSYNC_CRCM0 B43_PHY_N(0x104) /* TGNsync CRC mask 0 */
-#define B43_NPHY_TGNSYNC_CRCM1 B43_PHY_N(0x105) /* TGNsync CRC mask 1 */
-#define B43_NPHY_TGNSYNC_CRCM2 B43_PHY_N(0x106) /* TGNsync CRC mask 2 */
-#define B43_NPHY_TGNSYNC_CRCM3 B43_PHY_N(0x107) /* TGNsync CRC mask 3 */
-#define B43_NPHY_TGNSYNC_CRCM4 B43_PHY_N(0x108) /* TGNsync CRC mask 4 */
-#define B43_NPHY_CRCPOLY B43_PHY_N(0x109) /* CRC polynomial */
-#define B43_NPHY_SIGCNT B43_PHY_N(0x10A) /* # sig count */
-#define B43_NPHY_SIGSTARTBIT_CTL B43_PHY_N(0x10B) /* Sig start bit control */
-#define B43_NPHY_CRCPOLY_ORDER B43_PHY_N(0x10C) /* CRC polynomial order */
-#define B43_NPHY_RFCTL_CST0 B43_PHY_N(0x10D) /* RF control core swap table 0 */
-#define B43_NPHY_RFCTL_CST1 B43_PHY_N(0x10E) /* RF control core swap table 1 */
-#define B43_NPHY_RFCTL_CST2O B43_PHY_N(0x10F) /* RF control core swap table 2 + others */
-#define B43_NPHY_BPHY_CTL5 B43_PHY_N(0x111) /* B PHY control 5 */
-#define B43_NPHY_RFSEQ_LPFBW B43_PHY_N(0x112) /* RF seq LPF bandwidth */
-#define B43_NPHY_TSSIBIAS1 B43_PHY_N(0x114) /* TSSI bias val 1 */
-#define B43_NPHY_TSSIBIAS2 B43_PHY_N(0x115) /* TSSI bias val 2 */
-#define B43_NPHY_TSSIBIAS_BIAS 0x00FF /* Bias */
-#define B43_NPHY_TSSIBIAS_BIAS_SHIFT 0
-#define B43_NPHY_TSSIBIAS_VAL 0xFF00 /* Value */
-#define B43_NPHY_TSSIBIAS_VAL_SHIFT 8
-#define B43_NPHY_ESTPWR1 B43_PHY_N(0x118) /* Estimated power 1 */
-#define B43_NPHY_ESTPWR2 B43_PHY_N(0x119) /* Estimated power 2 */
-#define B43_NPHY_ESTPWR_PWR 0x00FF /* Estimated power */
-#define B43_NPHY_ESTPWR_PWR_SHIFT 0
-#define B43_NPHY_ESTPWR_VALID 0x0100 /* Estimated power valid */
-#define B43_NPHY_TSSI_MAXTXFDT B43_PHY_N(0x11C) /* TSSI max TX frame delay time */
-#define B43_NPHY_TSSI_MAXTXFDT_VAL 0x00FF /* max TX frame delay time */
-#define B43_NPHY_TSSI_MAXTXFDT_VAL_SHIFT 0
-#define B43_NPHY_TSSI_MAXTDT B43_PHY_N(0x11D) /* TSSI max TSSI delay time */
-#define B43_NPHY_TSSI_MAXTDT_VAL 0x00FF /* max TSSI delay time */
-#define B43_NPHY_TSSI_MAXTDT_VAL_SHIFT 0
-#define B43_NPHY_ITSSI1 B43_PHY_N(0x11E) /* TSSI idle 1 */
-#define B43_NPHY_ITSSI2 B43_PHY_N(0x11F) /* TSSI idle 2 */
-#define B43_NPHY_ITSSI_VAL 0x00FF /* Idle TSSI */
-#define B43_NPHY_ITSSI_VAL_SHIFT 0
-#define B43_NPHY_TSSIMODE B43_PHY_N(0x122) /* TSSI mode */
-#define B43_NPHY_TSSIMODE_EN 0x0001 /* TSSI enable */
-#define B43_NPHY_TSSIMODE_PDEN 0x0002 /* Power det enable */
-#define B43_NPHY_RXMACIFM B43_PHY_N(0x123) /* RX Macif mode */
-#define B43_NPHY_CRSIT_COCNT_LO B43_PHY_N(0x124) /* CRS idle time CRS-on count (low) */
-#define B43_NPHY_CRSIT_COCNT_HI B43_PHY_N(0x125) /* CRS idle time CRS-on count (high) */
-#define B43_NPHY_CRSIT_MTCNT_LO B43_PHY_N(0x126) /* CRS idle time measure time count (low) */
-#define B43_NPHY_CRSIT_MTCNT_HI B43_PHY_N(0x127) /* CRS idle time measure time count (high) */
-#define B43_NPHY_SAMTWC B43_PHY_N(0x128) /* Sample tail wait count */
-#define B43_NPHY_IQEST_CMD B43_PHY_N(0x129) /* I/Q estimate command */
-#define B43_NPHY_IQEST_CMD_START 0x0001 /* Start */
-#define B43_NPHY_IQEST_CMD_MODE 0x0002 /* Mode */
-#define B43_NPHY_IQEST_WT B43_PHY_N(0x12A) /* I/Q estimate wait time */
-#define B43_NPHY_IQEST_WT_VAL 0x00FF /* Wait time */
-#define B43_NPHY_IQEST_WT_VAL_SHIFT 0
-#define B43_NPHY_IQEST_SAMCNT B43_PHY_N(0x12B) /* I/Q estimate sample count */
-#define B43_NPHY_IQEST_IQACC_LO0 B43_PHY_N(0x12C) /* I/Q estimate I/Q acc lo 0 */
-#define B43_NPHY_IQEST_IQACC_HI0 B43_PHY_N(0x12D) /* I/Q estimate I/Q acc hi 0 */
-#define B43_NPHY_IQEST_IPACC_LO0 B43_PHY_N(0x12E) /* I/Q estimate I power acc lo 0 */
-#define B43_NPHY_IQEST_IPACC_HI0 B43_PHY_N(0x12F) /* I/Q estimate I power acc hi 0 */
-#define B43_NPHY_IQEST_QPACC_LO0 B43_PHY_N(0x130) /* I/Q estimate Q power acc lo 0 */
-#define B43_NPHY_IQEST_QPACC_HI0 B43_PHY_N(0x131) /* I/Q estimate Q power acc hi 0 */
-#define B43_NPHY_IQEST_IQACC_LO1 B43_PHY_N(0x134) /* I/Q estimate I/Q acc lo 1 */
-#define B43_NPHY_IQEST_IQACC_HI1 B43_PHY_N(0x135) /* I/Q estimate I/Q acc hi 1 */
-#define B43_NPHY_IQEST_IPACC_LO1 B43_PHY_N(0x136) /* I/Q estimate I power acc lo 1 */
-#define B43_NPHY_IQEST_IPACC_HI1 B43_PHY_N(0x137) /* I/Q estimate I power acc hi 1 */
-#define B43_NPHY_IQEST_QPACC_LO1 B43_PHY_N(0x138) /* I/Q estimate Q power acc lo 1 */
-#define B43_NPHY_IQEST_QPACC_HI1 B43_PHY_N(0x139) /* I/Q estimate Q power acc hi 1 */
-#define B43_NPHY_MIMO_CRSTXEXT B43_PHY_N(0x13A) /* MIMO PHY CRS TX extension */
-#define B43_NPHY_PWRDET1 B43_PHY_N(0x13B) /* Power det 1 */
-#define B43_NPHY_PWRDET2 B43_PHY_N(0x13C) /* Power det 2 */
-#define B43_NPHY_MAXRSSI_DTIME B43_PHY_N(0x13F) /* RSSI max RSSI delay time */
-#define B43_NPHY_PIL_DW0 B43_PHY_N(0x141) /* Pilot data weight 0 */
-#define B43_NPHY_PIL_DW1 B43_PHY_N(0x142) /* Pilot data weight 1 */
-#define B43_NPHY_PIL_DW2 B43_PHY_N(0x143) /* Pilot data weight 2 */
-#define B43_NPHY_PIL_DW_BPSK 0x000F /* BPSK */
-#define B43_NPHY_PIL_DW_BPSK_SHIFT 0
-#define B43_NPHY_PIL_DW_QPSK 0x00F0 /* QPSK */
-#define B43_NPHY_PIL_DW_QPSK_SHIFT 4
-#define B43_NPHY_PIL_DW_16QAM 0x0F00 /* 16-QAM */
-#define B43_NPHY_PIL_DW_16QAM_SHIFT 8
-#define B43_NPHY_PIL_DW_64QAM 0xF000 /* 64-QAM */
-#define B43_NPHY_PIL_DW_64QAM_SHIFT 12
-#define B43_NPHY_FMDEM_CFG B43_PHY_N(0x144) /* FM demodulation config */
-#define B43_NPHY_PHASETR_A0 B43_PHY_N(0x145) /* Phase track alpha 0 */
-#define B43_NPHY_PHASETR_A1 B43_PHY_N(0x146) /* Phase track alpha 1 */
-#define B43_NPHY_PHASETR_A2 B43_PHY_N(0x147) /* Phase track alpha 2 */
-#define B43_NPHY_PHASETR_B0 B43_PHY_N(0x148) /* Phase track beta 0 */
-#define B43_NPHY_PHASETR_B1 B43_PHY_N(0x149) /* Phase track beta 1 */
-#define B43_NPHY_PHASETR_B2 B43_PHY_N(0x14A) /* Phase track beta 2 */
-#define B43_NPHY_PHASETR_CHG0 B43_PHY_N(0x14B) /* Phase track change 0 */
-#define B43_NPHY_PHASETR_CHG1 B43_PHY_N(0x14C) /* Phase track change 1 */
-#define B43_NPHY_PHASETW_OFF B43_PHY_N(0x14D) /* Phase track offset */
-#define B43_NPHY_RFCTL_DBG B43_PHY_N(0x14E) /* RF control debug */
-#define B43_NPHY_CCK_SHIFTB_REF B43_PHY_N(0x150) /* CCK shiftbits reference var */
-#define B43_NPHY_OVER_DGAIN0 B43_PHY_N(0x152) /* Override digital gain 0 */
-#define B43_NPHY_OVER_DGAIN1 B43_PHY_N(0x153) /* Override digital gain 1 */
-#define B43_NPHY_OVER_DGAIN_FDGV 0x0007 /* Force digital gain value */
-#define B43_NPHY_OVER_DGAIN_FDGV_SHIFT 0
-#define B43_NPHY_OVER_DGAIN_FDGEN 0x0008 /* Force digital gain enable */
-#define B43_NPHY_OVER_DGAIN_CCKDGECV 0xFF00 /* CCK digital gain enable count value */
-#define B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT 8
-#define B43_NPHY_BIST_STAT4 B43_PHY_N(0x156) /* BIST status 4 */
-#define B43_NPHY_RADAR_MAL B43_PHY_N(0x157) /* Radar MA length */
-#define B43_NPHY_RADAR_SRCCTL B43_PHY_N(0x158) /* Radar search control */
-#define B43_NPHY_VLD_DTSIG B43_PHY_N(0x159) /* VLD data tones sig */
-#define B43_NPHY_VLD_DTDAT B43_PHY_N(0x15A) /* VLD data tones data */
-#define B43_NPHY_C1_BPHY_RXIQCA0 B43_PHY_N(0x15B) /* Core 1 B PHY RX I/Q comp A0 */
-#define B43_NPHY_C1_BPHY_RXIQCB0 B43_PHY_N(0x15C) /* Core 1 B PHY RX I/Q comp B0 */
-#define B43_NPHY_C2_BPHY_RXIQCA1 B43_PHY_N(0x15D) /* Core 2 B PHY RX I/Q comp A1 */
-#define B43_NPHY_C2_BPHY_RXIQCB1 B43_PHY_N(0x15E) /* Core 2 B PHY RX I/Q comp B1 */
-#define B43_NPHY_FREQGAIN0 B43_PHY_N(0x160) /* Frequency gain 0 */
-#define B43_NPHY_FREQGAIN1 B43_PHY_N(0x161) /* Frequency gain 1 */
-#define B43_NPHY_FREQGAIN2 B43_PHY_N(0x162) /* Frequency gain 2 */
-#define B43_NPHY_FREQGAIN3 B43_PHY_N(0x163) /* Frequency gain 3 */
-#define B43_NPHY_FREQGAIN4 B43_PHY_N(0x164) /* Frequency gain 4 */
-#define B43_NPHY_FREQGAIN5 B43_PHY_N(0x165) /* Frequency gain 5 */
-#define B43_NPHY_FREQGAIN6 B43_PHY_N(0x166) /* Frequency gain 6 */
-#define B43_NPHY_FREQGAIN7 B43_PHY_N(0x167) /* Frequency gain 7 */
-#define B43_NPHY_FREQGAIN_BYPASS B43_PHY_N(0x168) /* Frequency gain bypass */
-#define B43_NPHY_TRLOSS B43_PHY_N(0x169) /* TR loss value */
-#define B43_NPHY_C1_ADCCLIP B43_PHY_N(0x16A) /* Core 1 ADC clip */
-#define B43_NPHY_C2_ADCCLIP B43_PHY_N(0x16B) /* Core 2 ADC clip */
-#define B43_NPHY_LTRN_OFFGAIN B43_PHY_N(0x16F) /* LTRN offset gain */
-#define B43_NPHY_LTRN_OFF B43_PHY_N(0x170) /* LTRN offset */
-#define B43_NPHY_NRDATAT_WWISE20SIG B43_PHY_N(0x171) /* # data tones WWiSE 20 sig */
-#define B43_NPHY_NRDATAT_WWISE40SIG B43_PHY_N(0x172) /* # data tones WWiSE 40 sig */
-#define B43_NPHY_NRDATAT_TGNSYNC20SIG B43_PHY_N(0x173) /* # data tones TGNsync 20 sig */
-#define B43_NPHY_NRDATAT_TGNSYNC40SIG B43_PHY_N(0x174) /* # data tones TGNsync 40 sig */
-#define B43_NPHY_WWISE_CRCM0 B43_PHY_N(0x175) /* WWiSE CRC mask 0 */
-#define B43_NPHY_WWISE_CRCM1 B43_PHY_N(0x176) /* WWiSE CRC mask 1 */
-#define B43_NPHY_WWISE_CRCM2 B43_PHY_N(0x177) /* WWiSE CRC mask 2 */
-#define B43_NPHY_WWISE_CRCM3 B43_PHY_N(0x178) /* WWiSE CRC mask 3 */
-#define B43_NPHY_WWISE_CRCM4 B43_PHY_N(0x179) /* WWiSE CRC mask 4 */
-#define B43_NPHY_CHANEST_CDDSH B43_PHY_N(0x17A) /* Channel estimate CDD shift */
-#define B43_NPHY_HTAGC_WCNT B43_PHY_N(0x17B) /* HT ADC wait counters */
-#define B43_NPHY_SQPARM B43_PHY_N(0x17C) /* SQ params */
-#define B43_NPHY_MCSDUP6M B43_PHY_N(0x17D) /* MCS dup 6M */
-#define B43_NPHY_NDATAT_DUP40 B43_PHY_N(0x17E) /* # data tones dup 40 */
-#define B43_NPHY_DUP40_TGNSYNC_CYCD B43_PHY_N(0x17F) /* Dup40 TGNsync cycle data */
-#define B43_NPHY_DUP40_GFBL B43_PHY_N(0x180) /* Dup40 GF format BL address */
-#define B43_NPHY_DUP40_BL B43_PHY_N(0x181) /* Dup40 format BL address */
-#define B43_NPHY_LEGDUP_FTA B43_PHY_N(0x182) /* Legacy dup frm table address */
-#define B43_NPHY_PACPROC_DBG B43_PHY_N(0x183) /* Packet processing debug */
-#define B43_NPHY_PIL_CYC1 B43_PHY_N(0x184) /* Pilot cycle counter 1 */
-#define B43_NPHY_PIL_CYC2 B43_PHY_N(0x185) /* Pilot cycle counter 2 */
-#define B43_NPHY_TXF_20CO_S0A1 B43_PHY_N(0x186) /* TX filter 20 coeff stage 0 A1 */
-#define B43_NPHY_TXF_20CO_S0A2 B43_PHY_N(0x187) /* TX filter 20 coeff stage 0 A2 */
-#define B43_NPHY_TXF_20CO_S1A1 B43_PHY_N(0x188) /* TX filter 20 coeff stage 1 A1 */
-#define B43_NPHY_TXF_20CO_S1A2 B43_PHY_N(0x189) /* TX filter 20 coeff stage 1 A2 */
-#define B43_NPHY_TXF_20CO_S2A1 B43_PHY_N(0x18A) /* TX filter 20 coeff stage 2 A1 */
-#define B43_NPHY_TXF_20CO_S2A2 B43_PHY_N(0x18B) /* TX filter 20 coeff stage 2 A2 */
-#define B43_NPHY_TXF_20CO_S0B1 B43_PHY_N(0x18C) /* TX filter 20 coeff stage 0 B1 */
-#define B43_NPHY_TXF_20CO_S0B2 B43_PHY_N(0x18D) /* TX filter 20 coeff stage 0 B2 */
-#define B43_NPHY_TXF_20CO_S0B3 B43_PHY_N(0x18E) /* TX filter 20 coeff stage 0 B3 */
-#define B43_NPHY_TXF_20CO_S1B1 B43_PHY_N(0x18F) /* TX filter 20 coeff stage 1 B1 */
-#define B43_NPHY_TXF_20CO_S1B2 B43_PHY_N(0x190) /* TX filter 20 coeff stage 1 B2 */
-#define B43_NPHY_TXF_20CO_S1B3 B43_PHY_N(0x191) /* TX filter 20 coeff stage 1 B3 */
-#define B43_NPHY_TXF_20CO_S2B1 B43_PHY_N(0x192) /* TX filter 20 coeff stage 2 B1 */
-#define B43_NPHY_TXF_20CO_S2B2 B43_PHY_N(0x193) /* TX filter 20 coeff stage 2 B2 */
-#define B43_NPHY_TXF_20CO_S2B3 B43_PHY_N(0x194) /* TX filter 20 coeff stage 2 B3 */
-#define B43_NPHY_TXF_40CO_S0A1 B43_PHY_N(0x195) /* TX filter 40 coeff stage 0 A1 */
-#define B43_NPHY_TXF_40CO_S0A2 B43_PHY_N(0x196) /* TX filter 40 coeff stage 0 A2 */
-#define B43_NPHY_TXF_40CO_S1A1 B43_PHY_N(0x197) /* TX filter 40 coeff stage 1 A1 */
-#define B43_NPHY_TXF_40CO_S1A2 B43_PHY_N(0x198) /* TX filter 40 coeff stage 1 A2 */
-#define B43_NPHY_TXF_40CO_S2A1 B43_PHY_N(0x199) /* TX filter 40 coeff stage 2 A1 */
-#define B43_NPHY_TXF_40CO_S2A2 B43_PHY_N(0x19A) /* TX filter 40 coeff stage 2 A2 */
-#define B43_NPHY_TXF_40CO_S0B1 B43_PHY_N(0x19B) /* TX filter 40 coeff stage 0 B1 */
-#define B43_NPHY_TXF_40CO_S0B2 B43_PHY_N(0x19C) /* TX filter 40 coeff stage 0 B2 */
-#define B43_NPHY_TXF_40CO_S0B3 B43_PHY_N(0x19D) /* TX filter 40 coeff stage 0 B3 */
-#define B43_NPHY_TXF_40CO_S1B1 B43_PHY_N(0x19E) /* TX filter 40 coeff stage 1 B1 */
-#define B43_NPHY_TXF_40CO_S1B2 B43_PHY_N(0x19F) /* TX filter 40 coeff stage 1 B2 */
-#define B43_NPHY_TXF_40CO_S1B3 B43_PHY_N(0x1A0) /* TX filter 40 coeff stage 1 B3 */
-#define B43_NPHY_TXF_40CO_S2B1 B43_PHY_N(0x1A1) /* TX filter 40 coeff stage 2 B1 */
-#define B43_NPHY_TXF_40CO_S2B2 B43_PHY_N(0x1A2) /* TX filter 40 coeff stage 2 B2 */
-#define B43_NPHY_TXF_40CO_S2B3 B43_PHY_N(0x1A3) /* TX filter 40 coeff stage 2 B3 */
-#define B43_NPHY_RSSIMC_0I_RSSI_X B43_PHY_N(0x1A4) /* RSSI multiplication coefficient 0 I RSSI X */
-#define B43_NPHY_RSSIMC_0I_RSSI_Y B43_PHY_N(0x1A5) /* RSSI multiplication coefficient 0 I RSSI Y */
-#define B43_NPHY_RSSIMC_0I_RSSI_Z B43_PHY_N(0x1A6) /* RSSI multiplication coefficient 0 I RSSI Z */
-#define B43_NPHY_RSSIMC_0I_TBD B43_PHY_N(0x1A7) /* RSSI multiplication coefficient 0 I TBD */
-#define B43_NPHY_RSSIMC_0I_PWRDET B43_PHY_N(0x1A8) /* RSSI multiplication coefficient 0 I power det */
-#define B43_NPHY_RSSIMC_0I_TSSI B43_PHY_N(0x1A9) /* RSSI multiplication coefficient 0 I TSSI */
-#define B43_NPHY_RSSIMC_0Q_RSSI_X B43_PHY_N(0x1AA) /* RSSI multiplication coefficient 0 Q RSSI X */
-#define B43_NPHY_RSSIMC_0Q_RSSI_Y B43_PHY_N(0x1AB) /* RSSI multiplication coefficient 0 Q RSSI Y */
-#define B43_NPHY_RSSIMC_0Q_RSSI_Z B43_PHY_N(0x1AC) /* RSSI multiplication coefficient 0 Q RSSI Z */
-#define B43_NPHY_RSSIMC_0Q_TBD B43_PHY_N(0x1AD) /* RSSI multiplication coefficient 0 Q TBD */
-#define B43_NPHY_RSSIMC_0Q_PWRDET B43_PHY_N(0x1AE) /* RSSI multiplication coefficient 0 Q power det */
-#define B43_NPHY_RSSIMC_0Q_TSSI B43_PHY_N(0x1AF) /* RSSI multiplication coefficient 0 Q TSSI */
-#define B43_NPHY_RSSIMC_1I_RSSI_X B43_PHY_N(0x1B0) /* RSSI multiplication coefficient 1 I RSSI X */
-#define B43_NPHY_RSSIMC_1I_RSSI_Y B43_PHY_N(0x1B1) /* RSSI multiplication coefficient 1 I RSSI Y */
-#define B43_NPHY_RSSIMC_1I_RSSI_Z B43_PHY_N(0x1B2) /* RSSI multiplication coefficient 1 I RSSI Z */
-#define B43_NPHY_RSSIMC_1I_TBD B43_PHY_N(0x1B3) /* RSSI multiplication coefficient 1 I TBD */
-#define B43_NPHY_RSSIMC_1I_PWRDET B43_PHY_N(0x1B4) /* RSSI multiplication coefficient 1 I power det */
-#define B43_NPHY_RSSIMC_1I_TSSI B43_PHY_N(0x1B5) /* RSSI multiplication coefficient 1 I TSSI */
-#define B43_NPHY_RSSIMC_1Q_RSSI_X B43_PHY_N(0x1B6) /* RSSI multiplication coefficient 1 Q RSSI X */
-#define B43_NPHY_RSSIMC_1Q_RSSI_Y B43_PHY_N(0x1B7) /* RSSI multiplication coefficient 1 Q RSSI Y */
-#define B43_NPHY_RSSIMC_1Q_RSSI_Z B43_PHY_N(0x1B8) /* RSSI multiplication coefficient 1 Q RSSI Z */
-#define B43_NPHY_RSSIMC_1Q_TBD B43_PHY_N(0x1B9) /* RSSI multiplication coefficient 1 Q TBD */
-#define B43_NPHY_RSSIMC_1Q_PWRDET B43_PHY_N(0x1BA) /* RSSI multiplication coefficient 1 Q power det */
-#define B43_NPHY_RSSIMC_1Q_TSSI B43_PHY_N(0x1BB) /* RSSI multiplication coefficient 1 Q TSSI */
-#define B43_NPHY_SAMC_WCNT B43_PHY_N(0x1BC) /* Sample collect wait counter */
-#define B43_NPHY_PTHROUGH_CNT B43_PHY_N(0x1BD) /* Pass-through counter */
-#define B43_NPHY_LTRN_OFF_G20L B43_PHY_N(0x1C4) /* LTRN offset gain 20L */
-#define B43_NPHY_LTRN_OFF_20L B43_PHY_N(0x1C5) /* LTRN offset 20L */
-#define B43_NPHY_LTRN_OFF_G20U B43_PHY_N(0x1C6) /* LTRN offset gain 20U */
-#define B43_NPHY_LTRN_OFF_20U B43_PHY_N(0x1C7) /* LTRN offset 20U */
-#define B43_NPHY_DSSSCCK_GAINSL B43_PHY_N(0x1C8) /* DSSS/CCK gain settle length */
-#define B43_NPHY_GPIO_LOOUT B43_PHY_N(0x1C9) /* GPIO low out */
-#define B43_NPHY_GPIO_HIOUT B43_PHY_N(0x1CA) /* GPIO high out */
-#define B43_NPHY_CRS_CHECK B43_PHY_N(0x1CB) /* CRS check */
-#define B43_NPHY_ML_LOGSS_RAT B43_PHY_N(0x1CC) /* ML/logss ratio */
-#define B43_NPHY_DUPSCALE B43_PHY_N(0x1CD) /* Dup scale */
-#define B43_NPHY_BW1A B43_PHY_N(0x1CE) /* BW 1A */
-#define B43_NPHY_BW2 B43_PHY_N(0x1CF) /* BW 2 */
-#define B43_NPHY_BW3 B43_PHY_N(0x1D0) /* BW 3 */
-#define B43_NPHY_BW4 B43_PHY_N(0x1D1) /* BW 4 */
-#define B43_NPHY_BW5 B43_PHY_N(0x1D2) /* BW 5 */
-#define B43_NPHY_BW6 B43_PHY_N(0x1D3) /* BW 6 */
-#define B43_NPHY_COALEN0 B43_PHY_N(0x1D4) /* Coarse length 0 */
-#define B43_NPHY_COALEN1 B43_PHY_N(0x1D5) /* Coarse length 1 */
-#define B43_NPHY_CRSTHRES_1U B43_PHY_N(0x1D6) /* CRS threshold 1 U */
-#define B43_NPHY_CRSTHRES_2U B43_PHY_N(0x1D7) /* CRS threshold 2 U */
-#define B43_NPHY_CRSTHRES_3U B43_PHY_N(0x1D8) /* CRS threshold 3 U */
-#define B43_NPHY_CRSCTL_U B43_PHY_N(0x1D9) /* CRS control U */
-#define B43_NPHY_CRSTHRES_1L B43_PHY_N(0x1DA) /* CRS threshold 1 L */
-#define B43_NPHY_CRSTHRES_2L B43_PHY_N(0x1DB) /* CRS threshold 2 L */
-#define B43_NPHY_CRSTHRES_3L B43_PHY_N(0x1DC) /* CRS threshold 3 L */
-#define B43_NPHY_CRSCTL_L B43_PHY_N(0x1DD) /* CRS control L */
-#define B43_NPHY_STRA_1U B43_PHY_N(0x1DE) /* STR address 1 U */
-#define B43_NPHY_STRA_2U B43_PHY_N(0x1DF) /* STR address 2 U */
-#define B43_NPHY_STRA_1L B43_PHY_N(0x1E0) /* STR address 1 L */
-#define B43_NPHY_STRA_2L B43_PHY_N(0x1E1) /* STR address 2 L */
-#define B43_NPHY_CRSCHECK1 B43_PHY_N(0x1E2) /* CRS check 1 */
-#define B43_NPHY_CRSCHECK2 B43_PHY_N(0x1E3) /* CRS check 2 */
-#define B43_NPHY_CRSCHECK3 B43_PHY_N(0x1E4) /* CRS check 3 */
-#define B43_NPHY_JMPSTP0 B43_PHY_N(0x1E5) /* Jump step 0 */
-#define B43_NPHY_JMPSTP1 B43_PHY_N(0x1E6) /* Jump step 1 */
-#define B43_NPHY_TXPCTL_CMD B43_PHY_N(0x1E7) /* TX power control command */
-#define B43_NPHY_TXPCTL_CMD_INIT 0x007F /* Init */
-#define B43_NPHY_TXPCTL_CMD_INIT_SHIFT 0
-#define B43_NPHY_TXPCTL_CMD_COEFF 0x2000 /* Power control coefficients */
-#define B43_NPHY_TXPCTL_CMD_HWPCTLEN 0x4000 /* Hardware TX power control enable */
-#define B43_NPHY_TXPCTL_CMD_PCTLEN 0x8000 /* TX power control enable */
-#define B43_NPHY_TXPCTL_N B43_PHY_N(0x1E8) /* TX power control N num */
-#define B43_NPHY_TXPCTL_N_TSSID 0x00FF /* N TSSI delay */
-#define B43_NPHY_TXPCTL_N_TSSID_SHIFT 0
-#define B43_NPHY_TXPCTL_N_NPTIL2 0x0700 /* N PT integer log2 */
-#define B43_NPHY_TXPCTL_N_NPTIL2_SHIFT 8
-#define B43_NPHY_TXPCTL_ITSSI B43_PHY_N(0x1E9) /* TX power control idle TSSI */
-#define B43_NPHY_TXPCTL_ITSSI_0 0x003F /* Idle TSSI 0 */
-#define B43_NPHY_TXPCTL_ITSSI_0_SHIFT 0
-#define B43_NPHY_TXPCTL_ITSSI_1 0x3F00 /* Idle TSSI 1 */
-#define B43_NPHY_TXPCTL_ITSSI_1_SHIFT 8
-#define B43_NPHY_TXPCTL_ITSSI_BINF 0x8000 /* Raw TSSI offset bin format */
-#define B43_NPHY_TXPCTL_TPWR B43_PHY_N(0x1EA) /* TX power control target power */
-#define B43_NPHY_TXPCTL_TPWR_0 0x00FF /* Power 0 */
-#define B43_NPHY_TXPCTL_TPWR_0_SHIFT 0
-#define B43_NPHY_TXPCTL_TPWR_1 0xFF00 /* Power 1 */
-#define B43_NPHY_TXPCTL_TPWR_1_SHIFT 8
-#define B43_NPHY_TXPCTL_BIDX B43_PHY_N(0x1EB) /* TX power control base index */
-#define B43_NPHY_TXPCTL_BIDX_0 0x007F /* uC base index 0 */
-#define B43_NPHY_TXPCTL_BIDX_0_SHIFT 0
-#define B43_NPHY_TXPCTL_BIDX_1 0x7F00 /* uC base index 1 */
-#define B43_NPHY_TXPCTL_BIDX_1_SHIFT 8
-#define B43_NPHY_TXPCTL_BIDX_LOAD 0x8000 /* Load base index */
-#define B43_NPHY_TXPCTL_PIDX B43_PHY_N(0x1EC) /* TX power control power index */
-#define B43_NPHY_TXPCTL_PIDX_0 0x007F /* uC power index 0 */
-#define B43_NPHY_TXPCTL_PIDX_0_SHIFT 0
-#define B43_NPHY_TXPCTL_PIDX_1 0x7F00 /* uC power index 1 */
-#define B43_NPHY_TXPCTL_PIDX_1_SHIFT 8
-#define B43_NPHY_C1_TXPCTL_STAT B43_PHY_N(0x1ED) /* Core 1 TX power control status */
-#define B43_NPHY_C2_TXPCTL_STAT B43_PHY_N(0x1EE) /* Core 2 TX power control status */
-#define B43_NPHY_TXPCTL_STAT_EST 0x00FF /* Estimated power */
-#define B43_NPHY_TXPCTL_STAT_EST_SHIFT 0
-#define B43_NPHY_TXPCTL_STAT_BIDX 0x7F00 /* Base index */
-#define B43_NPHY_TXPCTL_STAT_BIDX_SHIFT 8
-#define B43_NPHY_TXPCTL_STAT_ESTVALID 0x8000 /* Estimated power valid */
-#define B43_NPHY_SMALLSGS_LEN B43_PHY_N(0x1EF) /* Small sig gain settle length */
-#define B43_NPHY_PHYSTAT_GAIN0 B43_PHY_N(0x1F0) /* PHY stats gain info 0 */
-#define B43_NPHY_PHYSTAT_GAIN1 B43_PHY_N(0x1F1) /* PHY stats gain info 1 */
-#define B43_NPHY_PHYSTAT_FREQEST B43_PHY_N(0x1F2) /* PHY stats frequency estimate */
-#define B43_NPHY_PHYSTAT_ADVRET B43_PHY_N(0x1F3) /* PHY stats ADV retard */
-#define B43_NPHY_PHYLB_MODE B43_PHY_N(0x1F4) /* PHY loopback mode */
-#define B43_NPHY_TONE_MIDX20_1 B43_PHY_N(0x1F5) /* Tone map index 20/1 */
-#define B43_NPHY_TONE_MIDX20_2 B43_PHY_N(0x1F6) /* Tone map index 20/2 */
-#define B43_NPHY_TONE_MIDX20_3 B43_PHY_N(0x1F7) /* Tone map index 20/3 */
-#define B43_NPHY_TONE_MIDX40_1 B43_PHY_N(0x1F8) /* Tone map index 40/1 */
-#define B43_NPHY_TONE_MIDX40_2 B43_PHY_N(0x1F9) /* Tone map index 40/2 */
-#define B43_NPHY_TONE_MIDX40_3 B43_PHY_N(0x1FA) /* Tone map index 40/3 */
-#define B43_NPHY_TONE_MIDX40_4 B43_PHY_N(0x1FB) /* Tone map index 40/4 */
-#define B43_NPHY_PILTONE_MIDX1 B43_PHY_N(0x1FC) /* Pilot tone map index 1 */
-#define B43_NPHY_PILTONE_MIDX2 B43_PHY_N(0x1FD) /* Pilot tone map index 2 */
-#define B43_NPHY_PILTONE_MIDX3 B43_PHY_N(0x1FE) /* Pilot tone map index 3 */
-#define B43_NPHY_TXRIFS_FRDEL B43_PHY_N(0x1FF) /* TX RIFS frame delay */
-#define B43_NPHY_AFESEQ_RX2TX_PUD_40M B43_PHY_N(0x200) /* AFE seq rx2tx power up/down delay 40M */
-#define B43_NPHY_AFESEQ_TX2RX_PUD_40M B43_PHY_N(0x201) /* AFE seq tx2rx power up/down delay 40M */
-#define B43_NPHY_AFESEQ_RX2TX_PUD_20M B43_PHY_N(0x202) /* AFE seq rx2tx power up/down delay 20M */
-#define B43_NPHY_AFESEQ_TX2RX_PUD_20M B43_PHY_N(0x203) /* AFE seq tx2rx power up/down delay 20M */
-#define B43_NPHY_RX_SIGCTL B43_PHY_N(0x204) /* RX signal control */
-#define B43_NPHY_RXPIL_CYCNT0 B43_PHY_N(0x205) /* RX pilot cycle counter 0 */
-#define B43_NPHY_RXPIL_CYCNT1 B43_PHY_N(0x206) /* RX pilot cycle counter 1 */
-#define B43_NPHY_RXPIL_CYCNT2 B43_PHY_N(0x207) /* RX pilot cycle counter 2 */
-#define B43_NPHY_AFESEQ_RX2TX_PUD_10M B43_PHY_N(0x208) /* AFE seq rx2tx power up/down delay 10M */
-#define B43_NPHY_AFESEQ_TX2RX_PUD_10M B43_PHY_N(0x209) /* AFE seq tx2rx power up/down delay 10M */
-#define B43_NPHY_DSSSCCK_CRSEXTL B43_PHY_N(0x20A) /* DSSS/CCK CRS extension length */
-#define B43_NPHY_ML_LOGSS_RATSLOPE B43_PHY_N(0x20B) /* ML/logss ratio slope */
-#define B43_NPHY_RIFS_SRCTL B43_PHY_N(0x20C) /* RIFS search timeout length */
-#define B43_NPHY_TXREALFD B43_PHY_N(0x20D) /* TX real frame delay */
-#define B43_NPHY_HPANT_SWTHRES B43_PHY_N(0x20E) /* High power antenna switch threshold */
-#define B43_NPHY_EDCRS_ASSTHRES0 B43_PHY_N(0x210) /* ED CRS assert threshold 0 */
-#define B43_NPHY_EDCRS_ASSTHRES1 B43_PHY_N(0x211) /* ED CRS assert threshold 1 */
-#define B43_NPHY_EDCRS_DEASSTHRES0 B43_PHY_N(0x212) /* ED CRS deassert threshold 0 */
-#define B43_NPHY_EDCRS_DEASSTHRES1 B43_PHY_N(0x213) /* ED CRS deassert threshold 1 */
-#define B43_NPHY_STR_WTIME20U B43_PHY_N(0x214) /* STR wait time 20U */
-#define B43_NPHY_STR_WTIME20L B43_PHY_N(0x215) /* STR wait time 20L */
-#define B43_NPHY_TONE_MIDX657M B43_PHY_N(0x216) /* Tone map index 657M */
-#define B43_NPHY_HTSIGTONES B43_PHY_N(0x217) /* HT signal tones */
-#define B43_NPHY_RSSI1 B43_PHY_N(0x219) /* RSSI value 1 */
-#define B43_NPHY_RSSI2 B43_PHY_N(0x21A) /* RSSI value 2 */
-#define B43_NPHY_CHAN_ESTHANG B43_PHY_N(0x21D) /* Channel estimate hang */
-#define B43_NPHY_FINERX2_CGC B43_PHY_N(0x221) /* Fine RX 2 clock gate control */
-#define B43_NPHY_FINERX2_CGC_DECGC 0x0008 /* Decode gated clocks */
-#define B43_NPHY_TXPCTL_INIT B43_PHY_N(0x222) /* TX power controll init */
-#define B43_NPHY_TXPCTL_INIT_PIDXI1 0x00FF /* Power index init 1 */
-#define B43_NPHY_TXPCTL_INIT_PIDXI1_SHIFT 0
-
-
-
-/* Broadcom 2055 radio registers */
-
-#define B2055_GEN_SPARE 0x00 /* GEN spare */
-#define B2055_SP_PINPD 0x02 /* SP PIN PD */
-#define B2055_C1_SP_RSSI 0x03 /* SP RSSI Core 1 */
-#define B2055_C1_SP_PDMISC 0x04 /* SP PD MISC Core 1 */
-#define B2055_C2_SP_RSSI 0x05 /* SP RSSI Core 2 */
-#define B2055_C2_SP_PDMISC 0x06 /* SP PD MISC Core 2 */
-#define B2055_C1_SP_RXGC1 0x07 /* SP RX GC1 Core 1 */
-#define B2055_C1_SP_RXGC2 0x08 /* SP RX GC2 Core 1 */
-#define B2055_C2_SP_RXGC1 0x09 /* SP RX GC1 Core 2 */
-#define B2055_C2_SP_RXGC2 0x0A /* SP RX GC2 Core 2 */
-#define B2055_C1_SP_LPFBWSEL 0x0B /* SP LPF BW select Core 1 */
-#define B2055_C2_SP_LPFBWSEL 0x0C /* SP LPF BW select Core 2 */
-#define B2055_C1_SP_TXGC1 0x0D /* SP TX GC1 Core 1 */
-#define B2055_C1_SP_TXGC2 0x0E /* SP TX GC2 Core 1 */
-#define B2055_C2_SP_TXGC1 0x0F /* SP TX GC1 Core 2 */
-#define B2055_C2_SP_TXGC2 0x10 /* SP TX GC2 Core 2 */
-#define B2055_MASTER1 0x11 /* Master control 1 */
-#define B2055_MASTER2 0x12 /* Master control 2 */
-#define B2055_PD_LGEN 0x13 /* PD LGEN */
-#define B2055_PD_PLLTS 0x14 /* PD PLL TS */
-#define B2055_C1_PD_LGBUF 0x15 /* PD Core 1 LGBUF */
-#define B2055_C1_PD_TX 0x16 /* PD Core 1 TX */
-#define B2055_C1_PD_RXTX 0x17 /* PD Core 1 RXTX */
-#define B2055_C1_PD_RSSIMISC 0x18 /* PD Core 1 RSSI MISC */
-#define B2055_C2_PD_LGBUF 0x19 /* PD Core 2 LGBUF */
-#define B2055_C2_PD_TX 0x1A /* PD Core 2 TX */
-#define B2055_C2_PD_RXTX 0x1B /* PD Core 2 RXTX */
-#define B2055_C2_PD_RSSIMISC 0x1C /* PD Core 2 RSSI MISC */
-#define B2055_PWRDET_LGEN 0x1D /* PWRDET LGEN */
-#define B2055_C1_PWRDET_LGBUF 0x1E /* PWRDET LGBUF Core 1 */
-#define B2055_C1_PWRDET_RXTX 0x1F /* PWRDET RXTX Core 1 */
-#define B2055_C2_PWRDET_LGBUF 0x20 /* PWRDET LGBUF Core 2 */
-#define B2055_C2_PWRDET_RXTX 0x21 /* PWRDET RXTX Core 2 */
-#define B2055_RRCCAL_CS 0x22 /* RRCCAL Control spare */
-#define B2055_RRCCAL_NOPTSEL 0x23 /* RRCCAL N OPT SEL */
-#define B2055_CAL_MISC 0x24 /* CAL MISC */
-#define B2055_CAL_COUT 0x25 /* CAL Counter out */
-#define B2055_CAL_COUT2 0x26 /* CAL Counter out 2 */
-#define B2055_CAL_CVARCTL 0x27 /* CAL CVAR Control */
-#define B2055_CAL_RVARCTL 0x28 /* CAL RVAR Control */
-#define B2055_CAL_LPOCTL 0x29 /* CAL LPO Control */
-#define B2055_CAL_TS 0x2A /* CAL TS */
-#define B2055_CAL_RCCALRTS 0x2B /* CAL RCCAL READ TS */
-#define B2055_CAL_RCALRTS 0x2C /* CAL RCAL READ TS */
-#define B2055_PADDRV 0x2D /* PAD driver */
-#define B2055_XOCTL1 0x2E /* XO Control 1 */
-#define B2055_XOCTL2 0x2F /* XO Control 2 */
-#define B2055_XOREGUL 0x30 /* XO Regulator */
-#define B2055_XOMISC 0x31 /* XO misc */
-#define B2055_PLL_LFC1 0x32 /* PLL LF C1 */
-#define B2055_PLL_CALVTH 0x33 /* PLL CAL VTH */
-#define B2055_PLL_LFC2 0x34 /* PLL LF C2 */
-#define B2055_PLL_REF 0x35 /* PLL reference */
-#define B2055_PLL_LFR1 0x36 /* PLL LF R1 */
-#define B2055_PLL_PFDCP 0x37 /* PLL PFD CP */
-#define B2055_PLL_IDAC_CPOPAMP 0x38 /* PLL IDAC CPOPAMP */
-#define B2055_PLL_CPREG 0x39 /* PLL CP Regulator */
-#define B2055_PLL_RCAL 0x3A /* PLL RCAL */
-#define B2055_RF_PLLMOD0 0x3B /* RF PLL MOD0 */
-#define B2055_RF_PLLMOD1 0x3C /* RF PLL MOD1 */
-#define B2055_RF_MMDIDAC1 0x3D /* RF MMD IDAC 1 */
-#define B2055_RF_MMDIDAC0 0x3E /* RF MMD IDAC 0 */
-#define B2055_RF_MMDSP 0x3F /* RF MMD spare */
-#define B2055_VCO_CAL1 0x40 /* VCO cal 1 */
-#define B2055_VCO_CAL2 0x41 /* VCO cal 2 */
-#define B2055_VCO_CAL3 0x42 /* VCO cal 3 */
-#define B2055_VCO_CAL4 0x43 /* VCO cal 4 */
-#define B2055_VCO_CAL5 0x44 /* VCO cal 5 */
-#define B2055_VCO_CAL6 0x45 /* VCO cal 6 */
-#define B2055_VCO_CAL7 0x46 /* VCO cal 7 */
-#define B2055_VCO_CAL8 0x47 /* VCO cal 8 */
-#define B2055_VCO_CAL9 0x48 /* VCO cal 9 */
-#define B2055_VCO_CAL10 0x49 /* VCO cal 10 */
-#define B2055_VCO_CAL11 0x4A /* VCO cal 11 */
-#define B2055_VCO_CAL12 0x4B /* VCO cal 12 */
-#define B2055_VCO_CAL13 0x4C /* VCO cal 13 */
-#define B2055_VCO_CAL14 0x4D /* VCO cal 14 */
-#define B2055_VCO_CAL15 0x4E /* VCO cal 15 */
-#define B2055_VCO_CAL16 0x4F /* VCO cal 16 */
-#define B2055_VCO_KVCO 0x50 /* VCO KVCO */
-#define B2055_VCO_CAPTAIL 0x51 /* VCO CAP TAIL */
-#define B2055_VCO_IDACVCO 0x52 /* VCO IDAC VCO */
-#define B2055_VCO_REG 0x53 /* VCO Regulator */
-#define B2055_PLL_RFVTH 0x54 /* PLL RF VTH */
-#define B2055_LGBUF_CENBUF 0x55 /* LGBUF CEN BUF */
-#define B2055_LGEN_TUNE1 0x56 /* LGEN tune 1 */
-#define B2055_LGEN_TUNE2 0x57 /* LGEN tune 2 */
-#define B2055_LGEN_IDAC1 0x58 /* LGEN IDAC 1 */
-#define B2055_LGEN_IDAC2 0x59 /* LGEN IDAC 2 */
-#define B2055_LGEN_BIASC 0x5A /* LGEN BIAS counter */
-#define B2055_LGEN_BIASIDAC 0x5B /* LGEN BIAS IDAC */
-#define B2055_LGEN_RCAL 0x5C /* LGEN RCAL */
-#define B2055_LGEN_DIV 0x5D /* LGEN div */
-#define B2055_LGEN_SPARE2 0x5E /* LGEN spare 2 */
-#define B2055_C1_LGBUF_ATUNE 0x5F /* Core 1 LGBUF A tune */
-#define B2055_C1_LGBUF_GTUNE 0x60 /* Core 1 LGBUF G tune */
-#define B2055_C1_LGBUF_DIV 0x61 /* Core 1 LGBUF div */
-#define B2055_C1_LGBUF_AIDAC 0x62 /* Core 1 LGBUF A IDAC */
-#define B2055_C1_LGBUF_GIDAC 0x63 /* Core 1 LGBUF G IDAC */
-#define B2055_C1_LGBUF_IDACFO 0x64 /* Core 1 LGBUF IDAC filter override */
-#define B2055_C1_LGBUF_SPARE 0x65 /* Core 1 LGBUF spare */
-#define B2055_C1_RX_RFSPC1 0x66 /* Core 1 RX RF SPC1 */
-#define B2055_C1_RX_RFR1 0x67 /* Core 1 RX RF reg 1 */
-#define B2055_C1_RX_RFR2 0x68 /* Core 1 RX RF reg 2 */
-#define B2055_C1_RX_RFRCAL 0x69 /* Core 1 RX RF RCAL */
-#define B2055_C1_RX_BB_BLCMP 0x6A /* Core 1 RX Baseband BUFI LPF CMP */
-#define B2055_C1_RX_BB_LPF 0x6B /* Core 1 RX Baseband LPF */
-#define B2055_C1_RX_BB_MIDACHP 0x6C /* Core 1 RX Baseband MIDAC High-pass */
-#define B2055_C1_RX_BB_VGA1IDAC 0x6D /* Core 1 RX Baseband VGA1 IDAC */
-#define B2055_C1_RX_BB_VGA2IDAC 0x6E /* Core 1 RX Baseband VGA2 IDAC */
-#define B2055_C1_RX_BB_VGA3IDAC 0x6F /* Core 1 RX Baseband VGA3 IDAC */
-#define B2055_C1_RX_BB_BUFOCTL 0x70 /* Core 1 RX Baseband BUFO Control */
-#define B2055_C1_RX_BB_RCCALCTL 0x71 /* Core 1 RX Baseband RCCAL Control */
-#define B2055_C1_RX_BB_RSSICTL1 0x72 /* Core 1 RX Baseband RSSI Control 1 */
-#define B2055_C1_RX_BB_RSSICTL2 0x73 /* Core 1 RX Baseband RSSI Control 2 */
-#define B2055_C1_RX_BB_RSSICTL3 0x74 /* Core 1 RX Baseband RSSI Control 3 */
-#define B2055_C1_RX_BB_RSSICTL4 0x75 /* Core 1 RX Baseband RSSI Control 4 */
-#define B2055_C1_RX_BB_RSSICTL5 0x76 /* Core 1 RX Baseband RSSI Control 5 */
-#define B2055_C1_RX_BB_REG 0x77 /* Core 1 RX Baseband Regulator */
-#define B2055_C1_RX_BB_SPARE1 0x78 /* Core 1 RX Baseband spare 1 */
-#define B2055_C1_RX_TXBBRCAL 0x79 /* Core 1 RX TX BB RCAL */
-#define B2055_C1_TX_RF_SPGA 0x7A /* Core 1 TX RF SGM PGA */
-#define B2055_C1_TX_RF_SPAD 0x7B /* Core 1 TX RF SGM PAD */
-#define B2055_C1_TX_RF_CNTPGA1 0x7C /* Core 1 TX RF counter PGA 1 */
-#define B2055_C1_TX_RF_CNTPAD1 0x7D /* Core 1 TX RF counter PAD 1 */
-#define B2055_C1_TX_RF_PGAIDAC 0x7E /* Core 1 TX RF PGA IDAC */
-#define B2055_C1_TX_PGAPADTN 0x7F /* Core 1 TX PGA PAD TN */
-#define B2055_C1_TX_PADIDAC1 0x80 /* Core 1 TX PAD IDAC 1 */
-#define B2055_C1_TX_PADIDAC2 0x81 /* Core 1 TX PAD IDAC 2 */
-#define B2055_C1_TX_MXBGTRIM 0x82 /* Core 1 TX MX B/G TRIM */
-#define B2055_C1_TX_RF_RCAL 0x83 /* Core 1 TX RF RCAL */
-#define B2055_C1_TX_RF_PADTSSI1 0x84 /* Core 1 TX RF PAD TSSI1 */
-#define B2055_C1_TX_RF_PADTSSI2 0x85 /* Core 1 TX RF PAD TSSI2 */
-#define B2055_C1_TX_RF_SPARE 0x86 /* Core 1 TX RF spare */
-#define B2055_C1_TX_RF_IQCAL1 0x87 /* Core 1 TX RF I/Q CAL 1 */
-#define B2055_C1_TX_RF_IQCAL2 0x88 /* Core 1 TX RF I/Q CAL 2 */
-#define B2055_C1_TXBB_RCCAL 0x89 /* Core 1 TXBB RC CAL Control */
-#define B2055_C1_TXBB_LPF1 0x8A /* Core 1 TXBB LPF 1 */
-#define B2055_C1_TX_VOSCNCL 0x8B /* Core 1 TX VOS CNCL */
-#define B2055_C1_TX_LPF_MXGMIDAC 0x8C /* Core 1 TX LPF MXGM IDAC */
-#define B2055_C1_TX_BB_MXGM 0x8D /* Core 1 TX BB MXGM */
-#define B2055_C2_LGBUF_ATUNE 0x8E /* Core 2 LGBUF A tune */
-#define B2055_C2_LGBUF_GTUNE 0x8F /* Core 2 LGBUF G tune */
-#define B2055_C2_LGBUF_DIV 0x90 /* Core 2 LGBUF div */
-#define B2055_C2_LGBUF_AIDAC 0x91 /* Core 2 LGBUF A IDAC */
-#define B2055_C2_LGBUF_GIDAC 0x92 /* Core 2 LGBUF G IDAC */
-#define B2055_C2_LGBUF_IDACFO 0x93 /* Core 2 LGBUF IDAC filter override */
-#define B2055_C2_LGBUF_SPARE 0x94 /* Core 2 LGBUF spare */
-#define B2055_C2_RX_RFSPC1 0x95 /* Core 2 RX RF SPC1 */
-#define B2055_C2_RX_RFR1 0x96 /* Core 2 RX RF reg 1 */
-#define B2055_C2_RX_RFR2 0x97 /* Core 2 RX RF reg 2 */
-#define B2055_C2_RX_RFRCAL 0x98 /* Core 2 RX RF RCAL */
-#define B2055_C2_RX_BB_BLCMP 0x99 /* Core 2 RX Baseband BUFI LPF CMP */
-#define B2055_C2_RX_BB_LPF 0x9A /* Core 2 RX Baseband LPF */
-#define B2055_C2_RX_BB_MIDACHP 0x9B /* Core 2 RX Baseband MIDAC High-pass */
-#define B2055_C2_RX_BB_VGA1IDAC 0x9C /* Core 2 RX Baseband VGA1 IDAC */
-#define B2055_C2_RX_BB_VGA2IDAC 0x9D /* Core 2 RX Baseband VGA2 IDAC */
-#define B2055_C2_RX_BB_VGA3IDAC 0x9E /* Core 2 RX Baseband VGA3 IDAC */
-#define B2055_C2_RX_BB_BUFOCTL 0x9F /* Core 2 RX Baseband BUFO Control */
-#define B2055_C2_RX_BB_RCCALCTL 0xA0 /* Core 2 RX Baseband RCCAL Control */
-#define B2055_C2_RX_BB_RSSICTL1 0xA1 /* Core 2 RX Baseband RSSI Control 1 */
-#define B2055_C2_RX_BB_RSSICTL2 0xA2 /* Core 2 RX Baseband RSSI Control 2 */
-#define B2055_C2_RX_BB_RSSICTL3 0xA3 /* Core 2 RX Baseband RSSI Control 3 */
-#define B2055_C2_RX_BB_RSSICTL4 0xA4 /* Core 2 RX Baseband RSSI Control 4 */
-#define B2055_C2_RX_BB_RSSICTL5 0xA5 /* Core 2 RX Baseband RSSI Control 5 */
-#define B2055_C2_RX_BB_REG 0xA6 /* Core 2 RX Baseband Regulator */
-#define B2055_C2_RX_BB_SPARE1 0xA7 /* Core 2 RX Baseband spare 1 */
-#define B2055_C2_RX_TXBBRCAL 0xA8 /* Core 2 RX TX BB RCAL */
-#define B2055_C2_TX_RF_SPGA 0xA9 /* Core 2 TX RF SGM PGA */
-#define B2055_C2_TX_RF_SPAD 0xAA /* Core 2 TX RF SGM PAD */
-#define B2055_C2_TX_RF_CNTPGA1 0xAB /* Core 2 TX RF counter PGA 1 */
-#define B2055_C2_TX_RF_CNTPAD1 0xAC /* Core 2 TX RF counter PAD 1 */
-#define B2055_C2_TX_RF_PGAIDAC 0xAD /* Core 2 TX RF PGA IDAC */
-#define B2055_C2_TX_PGAPADTN 0xAE /* Core 2 TX PGA PAD TN */
-#define B2055_C2_TX_PADIDAC1 0xAF /* Core 2 TX PAD IDAC 1 */
-#define B2055_C2_TX_PADIDAC2 0xB0 /* Core 2 TX PAD IDAC 2 */
-#define B2055_C2_TX_MXBGTRIM 0xB1 /* Core 2 TX MX B/G TRIM */
-#define B2055_C2_TX_RF_RCAL 0xB2 /* Core 2 TX RF RCAL */
-#define B2055_C2_TX_RF_PADTSSI1 0xB3 /* Core 2 TX RF PAD TSSI1 */
-#define B2055_C2_TX_RF_PADTSSI2 0xB4 /* Core 2 TX RF PAD TSSI2 */
-#define B2055_C2_TX_RF_SPARE 0xB5 /* Core 2 TX RF spare */
-#define B2055_C2_TX_RF_IQCAL1 0xB6 /* Core 2 TX RF I/Q CAL 1 */
-#define B2055_C2_TX_RF_IQCAL2 0xB7 /* Core 2 TX RF I/Q CAL 2 */
-#define B2055_C2_TXBB_RCCAL 0xB8 /* Core 2 TXBB RC CAL Control */
-#define B2055_C2_TXBB_LPF1 0xB9 /* Core 2 TXBB LPF 1 */
-#define B2055_C2_TX_VOSCNCL 0xBA /* Core 2 TX VOS CNCL */
-#define B2055_C2_TX_LPF_MXGMIDAC 0xBB /* Core 2 TX LPF MXGM IDAC */
-#define B2055_C2_TX_BB_MXGM 0xBC /* Core 2 TX BB MXGM */
-#define B2055_PRG_GCHP21 0xBD /* PRG GC HPVGA23 21 */
-#define B2055_PRG_GCHP22 0xBE /* PRG GC HPVGA23 22 */
-#define B2055_PRG_GCHP23 0xBF /* PRG GC HPVGA23 23 */
-#define B2055_PRG_GCHP24 0xC0 /* PRG GC HPVGA23 24 */
-#define B2055_PRG_GCHP25 0xC1 /* PRG GC HPVGA23 25 */
-#define B2055_PRG_GCHP26 0xC2 /* PRG GC HPVGA23 26 */
-#define B2055_PRG_GCHP27 0xC3 /* PRG GC HPVGA23 27 */
-#define B2055_PRG_GCHP28 0xC4 /* PRG GC HPVGA23 28 */
-#define B2055_PRG_GCHP29 0xC5 /* PRG GC HPVGA23 29 */
-#define B2055_PRG_GCHP30 0xC6 /* PRG GC HPVGA23 30 */
-#define B2055_C1_LNA_GAINBST 0xCD /* Core 1 LNA GAINBST */
-#define B2055_C1_B0NB_RSSIVCM 0xD2 /* Core 1 B0 narrow-band RSSI VCM */
-#define B2055_C1_GENSPARE2 0xD6 /* Core 1 GEN spare 2 */
-#define B2055_C2_LNA_GAINBST 0xD9 /* Core 2 LNA GAINBST */
-#define B2055_C2_B0NB_RSSIVCM 0xDE /* Core 2 B0 narrow-band RSSI VCM */
-#define B2055_C2_GENSPARE2 0xE2 /* Core 2 GEN spare 2 */
-
-
-
-struct b43_wldev;
-
-
-#ifdef CONFIG_B43_NPHY
-/* N-PHY support enabled */
-
-int b43_phy_initn(struct b43_wldev *dev);
-
-void b43_nphy_radio_turn_on(struct b43_wldev *dev);
-void b43_nphy_radio_turn_off(struct b43_wldev *dev);
-
-int b43_nphy_selectchannel(struct b43_wldev *dev, u8 channel);
-
-void b43_nphy_xmitpower(struct b43_wldev *dev);
-void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna);
-
-
-#else /* CONFIG_B43_NPHY */
-/* N-PHY support disabled */
-
-
-static inline
-int b43_phy_initn(struct b43_wldev *dev)
-{
- return -EOPNOTSUPP;
-}
-
-static inline
-void b43_nphy_radio_turn_on(struct b43_wldev *dev)
-{
-}
-static inline
-void b43_nphy_radio_turn_off(struct b43_wldev *dev)
-{
-}
-
-static inline
-int b43_nphy_selectchannel(struct b43_wldev *dev, u8 channel)
-{
- return -ENOSYS;
-}
-
-static inline
-void b43_nphy_xmitpower(struct b43_wldev *dev)
-{
-}
-static inline
-void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
-{
-}
-
-#endif /* CONFIG_B43_NPHY */
-#endif /* B43_NPHY_H_ */
-/*
-
- Broadcom B43 wireless driver
-
- Copyright (c) 2007 Michael Buesch <mb@bu3sch.de>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; see the file COPYING. If not, write to
- the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
- Boston, MA 02110-1301, USA.
-
-*/
-
-#include "pcmcia.h"
-
-#include <linux/ssb/ssb.h>
-
-#include <pcmcia/cs_types.h>
-#include <pcmcia/cs.h>
-#include <pcmcia/cistpl.h>
-#include <pcmcia/ciscode.h>
-#include <pcmcia/ds.h>
-#include <pcmcia/cisreg.h>
-
-
-static /*const */ struct pcmcia_device_id b43_pcmcia_tbl[] = {
- PCMCIA_DEVICE_MANF_CARD(0x2D0, 0x448),
- PCMCIA_DEVICE_NULL,
-};
-
-MODULE_DEVICE_TABLE(pcmcia, b43_pcmcia_tbl);
-
-#ifdef CONFIG_PM
-static int b43_pcmcia_suspend(struct pcmcia_device *dev)
-{
- struct ssb_bus *ssb = dev->priv;
-
- return ssb_bus_suspend(ssb);
-}
-
-static int b43_pcmcia_resume(struct pcmcia_device *dev)
-{
- struct ssb_bus *ssb = dev->priv;
-
- return ssb_bus_resume(ssb);
-}
-#else /* CONFIG_PM */
-# define b43_pcmcia_suspend NULL
-# define b43_pcmcia_resume NULL
-#endif /* CONFIG_PM */
-
-static int __devinit b43_pcmcia_probe(struct pcmcia_device *dev)
-{
- struct ssb_bus *ssb;
- win_req_t win;
- memreq_t mem;
- tuple_t tuple;
- cisparse_t parse;
- int err = -ENOMEM;
- int res = 0;
- unsigned char buf[64];
-
- ssb = kzalloc(sizeof(*ssb), GFP_KERNEL);
- if (!ssb)
- goto out_error;
-
- err = -ENODEV;
- tuple.DesiredTuple = CISTPL_CONFIG;
- tuple.Attributes = 0;
- tuple.TupleData = buf;
- tuple.TupleDataMax = sizeof(buf);
- tuple.TupleOffset = 0;
-
- res = pcmcia_get_first_tuple(dev, &tuple);
- if (res != CS_SUCCESS)
- goto err_kfree_ssb;
- res = pcmcia_get_tuple_data(dev, &tuple);
- if (res != CS_SUCCESS)
- goto err_kfree_ssb;
- res = pcmcia_parse_tuple(dev, &tuple, &parse);
- if (res != CS_SUCCESS)
- goto err_kfree_ssb;
-
- dev->conf.ConfigBase = parse.config.base;
- dev->conf.Present = parse.config.rmask[0];
- dev->conf.Attributes = CONF_ENABLE_IRQ;
- dev->conf.IntType = INT_MEMORY_AND_IO;
-
- dev->io.BasePort2 = 0;
- dev->io.NumPorts2 = 0;
- dev->io.Attributes2 = 0;
-
- win.Attributes = WIN_ADDR_SPACE_MEM | WIN_MEMORY_TYPE_CM |
- WIN_ENABLE | WIN_DATA_WIDTH_16 |
- WIN_USE_WAIT;
- win.Base = 0;
- win.Size = SSB_CORE_SIZE;
- win.AccessSpeed = 250;
- res = pcmcia_request_window(&dev, &win, &dev->win);
- if (res != CS_SUCCESS)
- goto err_kfree_ssb;
-
- mem.CardOffset = 0;
- mem.Page = 0;
- res = pcmcia_map_mem_page(dev->win, &mem);
- if (res != CS_SUCCESS)
- goto err_disable;
-
- dev->irq.Attributes = IRQ_TYPE_DYNAMIC_SHARING;
- dev->irq.IRQInfo1 = IRQ_LEVEL_ID;
- dev->irq.Handler = NULL; /* The handler is registered later. */
- dev->irq.Instance = NULL;
- res = pcmcia_request_irq(dev, &dev->irq);
- if (res != CS_SUCCESS)
- goto err_disable;
-
- res = pcmcia_request_configuration(dev, &dev->conf);
- if (res != CS_SUCCESS)
- goto err_disable;
-
- err = ssb_bus_pcmciabus_register(ssb, dev, win.Base);
- if (err)
- goto err_disable;
- dev->priv = ssb;
-
- return 0;
-
-err_disable:
- pcmcia_disable_device(dev);
-err_kfree_ssb:
- kfree(ssb);
-out_error:
- printk(KERN_ERR "b43-pcmcia: Initialization failed (%d, %d)\n",
- res, err);
- return err;
-}
-
-static void __devexit b43_pcmcia_remove(struct pcmcia_device *dev)
-{
- struct ssb_bus *ssb = dev->priv;
-
- ssb_bus_unregister(ssb);
- pcmcia_disable_device(dev);
- kfree(ssb);
- dev->priv = NULL;
-}
-
-static struct pcmcia_driver b43_pcmcia_driver = {
- .owner = THIS_MODULE,
- .drv = {
- .name = "b43-pcmcia",
- },
- .id_table = b43_pcmcia_tbl,
- .probe = b43_pcmcia_probe,
- .remove = __devexit_p(b43_pcmcia_remove),
- .suspend = b43_pcmcia_suspend,
- .resume = b43_pcmcia_resume,
-};
-
-int b43_pcmcia_init(void)
-{
- return pcmcia_register_driver(&b43_pcmcia_driver);
-}
-
-void b43_pcmcia_exit(void)
-{
- pcmcia_unregister_driver(&b43_pcmcia_driver);
-}
-#ifndef B43_PCMCIA_H_
-#define B43_PCMCIA_H_
-
-#ifdef CONFIG_B43_PCMCIA
-
-int b43_pcmcia_init(void);
-void b43_pcmcia_exit(void);
-
-#else /* CONFIG_B43_PCMCIA */
-
-static inline int b43_pcmcia_init(void)
-{
- return 0;
-}
-static inline void b43_pcmcia_exit(void)
-{
-}
-
-#endif /* CONFIG_B43_PCMCIA */
-#endif /* B43_PCMCIA_H_ */
-/*
-
- Broadcom B43 wireless driver
-
- Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
- Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
- Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
- Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
- Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; see the file COPYING. If not, write to
- the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
- Boston, MA 02110-1301, USA.
-
-*/
-
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/types.h>
-#include <linux/bitrev.h>
-
-#include "b43.h"
-#include "phy.h"
-#include "nphy.h"
-#include "main.h"
-#include "tables.h"
-#include "lo.h"
-#include "wa.h"
-
-
-static const s8 b43_tssi2dbm_b_table[] = {
- 0x4D, 0x4C, 0x4B, 0x4A,
- 0x4A, 0x49, 0x48, 0x47,
- 0x47, 0x46, 0x45, 0x45,
- 0x44, 0x43, 0x42, 0x42,
- 0x41, 0x40, 0x3F, 0x3E,
- 0x3D, 0x3C, 0x3B, 0x3A,
- 0x39, 0x38, 0x37, 0x36,
- 0x35, 0x34, 0x32, 0x31,
- 0x30, 0x2F, 0x2D, 0x2C,
- 0x2B, 0x29, 0x28, 0x26,
- 0x25, 0x23, 0x21, 0x1F,
- 0x1D, 0x1A, 0x17, 0x14,
- 0x10, 0x0C, 0x06, 0x00,
- -7, -7, -7, -7,
- -7, -7, -7, -7,
- -7, -7, -7, -7,
-};
-
-static const s8 b43_tssi2dbm_g_table[] = {
- 77, 77, 77, 76,
- 76, 76, 75, 75,
- 74, 74, 73, 73,
- 73, 72, 72, 71,
- 71, 70, 70, 69,
- 68, 68, 67, 67,
- 66, 65, 65, 64,
- 63, 63, 62, 61,
- 60, 59, 58, 57,
- 56, 55, 54, 53,
- 52, 50, 49, 47,
- 45, 43, 40, 37,
- 33, 28, 22, 14,
- 5, -7, -20, -20,
- -20, -20, -20, -20,
- -20, -20, -20, -20,
-};
-
-const u8 b43_radio_channel_codes_bg[] = {
- 12, 17, 22, 27,
- 32, 37, 42, 47,
- 52, 57, 62, 67,
- 72, 84,
-};
-
-#define bitrev4(tmp) (bitrev8(tmp) >> 4)
-static void b43_phy_initg(struct b43_wldev *dev);
-
-static void generate_rfatt_list(struct b43_wldev *dev,
- struct b43_rfatt_list *list)
-{
- struct b43_phy *phy = &dev->phy;
-
- /* APHY.rev < 5 || GPHY.rev < 6 */
- static const struct b43_rfatt rfatt_0[] = {
- {.att = 3,.with_padmix = 0,},
- {.att = 1,.with_padmix = 0,},
- {.att = 5,.with_padmix = 0,},
- {.att = 7,.with_padmix = 0,},
- {.att = 9,.with_padmix = 0,},
- {.att = 2,.with_padmix = 0,},
- {.att = 0,.with_padmix = 0,},
- {.att = 4,.with_padmix = 0,},
- {.att = 6,.with_padmix = 0,},
- {.att = 8,.with_padmix = 0,},
- {.att = 1,.with_padmix = 1,},
- {.att = 2,.with_padmix = 1,},
- {.att = 3,.with_padmix = 1,},
- {.att = 4,.with_padmix = 1,},
- };
- /* Radio.rev == 8 && Radio.version == 0x2050 */
- static const struct b43_rfatt rfatt_1[] = {
- {.att = 2,.with_padmix = 1,},
- {.att = 4,.with_padmix = 1,},
- {.att = 6,.with_padmix = 1,},
- {.att = 8,.with_padmix = 1,},
- {.att = 10,.with_padmix = 1,},
- {.att = 12,.with_padmix = 1,},
- {.att = 14,.with_padmix = 1,},
- };
- /* Otherwise */
- static const struct b43_rfatt rfatt_2[] = {
- {.att = 0,.with_padmix = 1,},
- {.att = 2,.with_padmix = 1,},
- {.att = 4,.with_padmix = 1,},
- {.att = 6,.with_padmix = 1,},
- {.att = 8,.with_padmix = 1,},
- {.att = 9,.with_padmix = 1,},
- {.att = 9,.with_padmix = 1,},
- };
-
- if (!b43_has_hardware_pctl(phy)) {
- /* Software pctl */
- list->list = rfatt_0;
- list->len = ARRAY_SIZE(rfatt_0);
- list->min_val = 0;
- list->max_val = 9;
- return;
- }
- if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
- /* Hardware pctl */
- list->list = rfatt_1;
- list->len = ARRAY_SIZE(rfatt_1);
- list->min_val = 0;
- list->max_val = 14;
- return;
- }
- /* Hardware pctl */
- list->list = rfatt_2;
- list->len = ARRAY_SIZE(rfatt_2);
- list->min_val = 0;
- list->max_val = 9;
-}
-
-static void generate_bbatt_list(struct b43_wldev *dev,
- struct b43_bbatt_list *list)
-{
- static const struct b43_bbatt bbatt_0[] = {
- {.att = 0,},
- {.att = 1,},
- {.att = 2,},
- {.att = 3,},
- {.att = 4,},
- {.att = 5,},
- {.att = 6,},
- {.att = 7,},
- {.att = 8,},
- };
-
- list->list = bbatt_0;
- list->len = ARRAY_SIZE(bbatt_0);
- list->min_val = 0;
- list->max_val = 8;
-}
-
-bool b43_has_hardware_pctl(struct b43_phy *phy)
-{
- if (!phy->hardware_power_control)
- return 0;
- switch (phy->type) {
- case B43_PHYTYPE_A:
- if (phy->rev >= 5)
- return 1;
- break;
- case B43_PHYTYPE_G:
- if (phy->rev >= 6)
- return 1;
- break;
- default:
- B43_WARN_ON(1);
- }
- return 0;
-}
-
-static void b43_shm_clear_tssi(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
-
- switch (phy->type) {
- case B43_PHYTYPE_A:
- b43_shm_write16(dev, B43_SHM_SHARED, 0x0068, 0x7F7F);
- b43_shm_write16(dev, B43_SHM_SHARED, 0x006a, 0x7F7F);
- break;
- case B43_PHYTYPE_B:
- case B43_PHYTYPE_G:
- b43_shm_write16(dev, B43_SHM_SHARED, 0x0058, 0x7F7F);
- b43_shm_write16(dev, B43_SHM_SHARED, 0x005a, 0x7F7F);
- b43_shm_write16(dev, B43_SHM_SHARED, 0x0070, 0x7F7F);
- b43_shm_write16(dev, B43_SHM_SHARED, 0x0072, 0x7F7F);
- break;
- }
-}
-
-/* Lock the PHY registers against concurrent access from the microcode.
- * This lock is nonrecursive. */
-void b43_phy_lock(struct b43_wldev *dev)
-{
-#if B43_DEBUG
- B43_WARN_ON(dev->phy.phy_locked);
- dev->phy.phy_locked = 1;
-#endif
- B43_WARN_ON(dev->dev->id.revision < 3);
-
- if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
- b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
-}
-
-void b43_phy_unlock(struct b43_wldev *dev)
-{
-#if B43_DEBUG
- B43_WARN_ON(!dev->phy.phy_locked);
- dev->phy.phy_locked = 0;
-#endif
- B43_WARN_ON(dev->dev->id.revision < 3);
-
- if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
- b43_power_saving_ctl_bits(dev, 0);
-}
-
-/* Different PHYs require different register routing flags.
- * This adjusts (and does sanity checks on) the routing flags.
- */
-static inline u16 adjust_phyreg_for_phytype(struct b43_phy *phy,
- u16 offset, struct b43_wldev *dev)
-{
- if (phy->type == B43_PHYTYPE_A) {
- /* OFDM registers are base-registers for the A-PHY. */
- if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
- offset &= ~B43_PHYROUTE;
- offset |= B43_PHYROUTE_BASE;
- }
- }
-
-#if B43_DEBUG
- if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
- /* Ext-G registers are only available on G-PHYs */
- if (phy->type != B43_PHYTYPE_G) {
- b43err(dev->wl, "Invalid EXT-G PHY access at "
- "0x%04X on PHY type %u\n", offset, phy->type);
- dump_stack();
- }
- }
- if ((offset & B43_PHYROUTE) == B43_PHYROUTE_N_BMODE) {
- /* N-BMODE registers are only available on N-PHYs */
- if (phy->type != B43_PHYTYPE_N) {
- b43err(dev->wl, "Invalid N-BMODE PHY access at "
- "0x%04X on PHY type %u\n", offset, phy->type);
- dump_stack();
- }
- }
-#endif /* B43_DEBUG */
-
- return offset;
-}
-
-u16 b43_phy_read(struct b43_wldev * dev, u16 offset)
-{
- struct b43_phy *phy = &dev->phy;
-
- offset = adjust_phyreg_for_phytype(phy, offset, dev);
- b43_write16(dev, B43_MMIO_PHY_CONTROL, offset);
- return b43_read16(dev, B43_MMIO_PHY_DATA);
-}
-
-void b43_phy_write(struct b43_wldev *dev, u16 offset, u16 val)
-{
- struct b43_phy *phy = &dev->phy;
-
- offset = adjust_phyreg_for_phytype(phy, offset, dev);
- b43_write16(dev, B43_MMIO_PHY_CONTROL, offset);
- b43_write16(dev, B43_MMIO_PHY_DATA, val);
-}
-
-void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
-{
- b43_phy_write(dev, offset,
- b43_phy_read(dev, offset) & mask);
-}
-
-void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
-{
- b43_phy_write(dev, offset,
- b43_phy_read(dev, offset) | set);
-}
-
-void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
-{
- b43_phy_write(dev, offset,
- (b43_phy_read(dev, offset) & mask) | set);
-}
-
-/* Adjust the transmission power output (G-PHY) */
-void b43_set_txpower_g(struct b43_wldev *dev,
- const struct b43_bbatt *bbatt,
- const struct b43_rfatt *rfatt, u8 tx_control)
-{
- struct b43_phy *phy = &dev->phy;
- struct b43_txpower_lo_control *lo = phy->lo_control;
- u16 bb, rf;
- u16 tx_bias, tx_magn;
-
- bb = bbatt->att;
- rf = rfatt->att;
- tx_bias = lo->tx_bias;
- tx_magn = lo->tx_magn;
- if (unlikely(tx_bias == 0xFF))
- tx_bias = 0;
-
- /* Save the values for later */
- phy->tx_control = tx_control;
- memcpy(&phy->rfatt, rfatt, sizeof(*rfatt));
- phy->rfatt.with_padmix = !!(tx_control & B43_TXCTL_TXMIX);
- memcpy(&phy->bbatt, bbatt, sizeof(*bbatt));
-
- if (b43_debug(dev, B43_DBG_XMITPOWER)) {
- b43dbg(dev->wl, "Tuning TX-power to bbatt(%u), "
- "rfatt(%u), tx_control(0x%02X), "
- "tx_bias(0x%02X), tx_magn(0x%02X)\n",
- bb, rf, tx_control, tx_bias, tx_magn);
- }
-
- b43_phy_set_baseband_attenuation(dev, bb);
- b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RFATT, rf);
- if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
- b43_radio_write16(dev, 0x43,
- (rf & 0x000F) | (tx_control & 0x0070));
- } else {
- b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
- & 0xFFF0) | (rf & 0x000F));
- b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
- & ~0x0070) | (tx_control &
- 0x0070));
- }
- if (has_tx_magnification(phy)) {
- b43_radio_write16(dev, 0x52, tx_magn | tx_bias);
- } else {
- b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
- & 0xFFF0) | (tx_bias & 0x000F));
- }
- if (phy->type == B43_PHYTYPE_G)
- b43_lo_g_adjust(dev);
-}
-
-static void default_baseband_attenuation(struct b43_wldev *dev,
- struct b43_bbatt *bb)
-{
- struct b43_phy *phy = &dev->phy;
-
- if (phy->radio_ver == 0x2050 && phy->radio_rev < 6)
- bb->att = 0;
- else
- bb->att = 2;
-}
-
-static void default_radio_attenuation(struct b43_wldev *dev,
- struct b43_rfatt *rf)
-{
- struct ssb_bus *bus = dev->dev->bus;
- struct b43_phy *phy = &dev->phy;
-
- rf->with_padmix = 0;
-
- if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
- bus->boardinfo.type == SSB_BOARD_BCM4309G) {
- if (bus->boardinfo.rev < 0x43) {
- rf->att = 2;
- return;
- } else if (bus->boardinfo.rev < 0x51) {
- rf->att = 3;
- return;
- }
- }
-
- if (phy->type == B43_PHYTYPE_A) {
- rf->att = 0x60;
- return;
- }
-
- switch (phy->radio_ver) {
- case 0x2053:
- switch (phy->radio_rev) {
- case 1:
- rf->att = 6;
- return;
- }
- break;
- case 0x2050:
- switch (phy->radio_rev) {
- case 0:
- rf->att = 5;
- return;
- case 1:
- if (phy->type == B43_PHYTYPE_G) {
- if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
- && bus->boardinfo.type == SSB_BOARD_BCM4309G
- && bus->boardinfo.rev >= 30)
- rf->att = 3;
- else if (bus->boardinfo.vendor ==
- SSB_BOARDVENDOR_BCM
- && bus->boardinfo.type ==
- SSB_BOARD_BU4306)
- rf->att = 3;
- else
- rf->att = 1;
- } else {
- if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
- && bus->boardinfo.type == SSB_BOARD_BCM4309G
- && bus->boardinfo.rev >= 30)
- rf->att = 7;
- else
- rf->att = 6;
- }
- return;
- case 2:
- if (phy->type == B43_PHYTYPE_G) {
- if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
- && bus->boardinfo.type == SSB_BOARD_BCM4309G
- && bus->boardinfo.rev >= 30)
- rf->att = 3;
- else if (bus->boardinfo.vendor ==
- SSB_BOARDVENDOR_BCM
- && bus->boardinfo.type ==
- SSB_BOARD_BU4306)
- rf->att = 5;
- else if (bus->chip_id == 0x4320)
- rf->att = 4;
- else
- rf->att = 3;
- } else
- rf->att = 6;
- return;
- case 3:
- rf->att = 5;
- return;
- case 4:
- case 5:
- rf->att = 1;
- return;
- case 6:
- case 7:
- rf->att = 5;
- return;
- case 8:
- rf->att = 0xA;
- rf->with_padmix = 1;
- return;
- case 9:
- default:
- rf->att = 5;
- return;
- }
- }
- rf->att = 5;
-}
-
-static u16 default_tx_control(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
-
- if (phy->radio_ver != 0x2050)
- return 0;
- if (phy->radio_rev == 1)
- return B43_TXCTL_PA2DB | B43_TXCTL_TXMIX;
- if (phy->radio_rev < 6)
- return B43_TXCTL_PA2DB;
- if (phy->radio_rev == 8)
- return B43_TXCTL_TXMIX;
- return 0;
-}
-
-/* This func is called "PHY calibrate" in the specs... */
-void b43_phy_early_init(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- struct b43_txpower_lo_control *lo = phy->lo_control;
-
- default_baseband_attenuation(dev, &phy->bbatt);
- default_radio_attenuation(dev, &phy->rfatt);
- phy->tx_control = (default_tx_control(dev) << 4);
-
- /* Commit previous writes */
- b43_read32(dev, B43_MMIO_MACCTL);
-
- if (phy->type == B43_PHYTYPE_B || phy->type == B43_PHYTYPE_G) {
- generate_rfatt_list(dev, &lo->rfatt_list);
- generate_bbatt_list(dev, &lo->bbatt_list);
- }
- if (phy->type == B43_PHYTYPE_G && phy->rev == 1) {
- /* Workaround: Temporarly disable gmode through the early init
- * phase, as the gmode stuff is not needed for phy rev 1 */
- phy->gmode = 0;
- b43_wireless_core_reset(dev, 0);
- b43_phy_initg(dev);
- phy->gmode = 1;
- b43_wireless_core_reset(dev, B43_TMSLOW_GMODE);
- }
-}
-
-/* GPHY_TSSI_Power_Lookup_Table_Init */
-static void b43_gphy_tssi_power_lt_init(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- int i;
- u16 value;
-
- for (i = 0; i < 32; i++)
- b43_ofdmtab_write16(dev, 0x3C20, i, phy->tssi2dbm[i]);
- for (i = 32; i < 64; i++)
- b43_ofdmtab_write16(dev, 0x3C00, i - 32, phy->tssi2dbm[i]);
- for (i = 0; i < 64; i += 2) {
- value = (u16) phy->tssi2dbm[i];
- value |= ((u16) phy->tssi2dbm[i + 1]) << 8;
- b43_phy_write(dev, 0x380 + (i / 2), value);
- }
-}
-
-/* GPHY_Gain_Lookup_Table_Init */
-static void b43_gphy_gain_lt_init(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- struct b43_txpower_lo_control *lo = phy->lo_control;
- u16 nr_written = 0;
- u16 tmp;
- u8 rf, bb;
-
- for (rf = 0; rf < lo->rfatt_list.len; rf++) {
- for (bb = 0; bb < lo->bbatt_list.len; bb++) {
- if (nr_written >= 0x40)
- return;
- tmp = lo->bbatt_list.list[bb].att;
- tmp <<= 8;
- if (phy->radio_rev == 8)
- tmp |= 0x50;
- else
- tmp |= 0x40;
- tmp |= lo->rfatt_list.list[rf].att;
- b43_phy_write(dev, 0x3C0 + nr_written, tmp);
- nr_written++;
- }
- }
-}
-
-static void hardware_pctl_init_aphy(struct b43_wldev *dev)
-{
- //TODO
-}
-
-static void hardware_pctl_init_gphy(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
-
- b43_phy_write(dev, 0x0036, (b43_phy_read(dev, 0x0036) & 0xFFC0)
- | (phy->tgt_idle_tssi - phy->cur_idle_tssi));
- b43_phy_write(dev, 0x0478, (b43_phy_read(dev, 0x0478) & 0xFF00)
- | (phy->tgt_idle_tssi - phy->cur_idle_tssi));
- b43_gphy_tssi_power_lt_init(dev);
- b43_gphy_gain_lt_init(dev);
- b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060) & 0xFFBF);
- b43_phy_write(dev, 0x0014, 0x0000);
-
- B43_WARN_ON(phy->rev < 6);
- b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478)
- | 0x0800);
- b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478)
- & 0xFEFF);
- b43_phy_write(dev, 0x0801, b43_phy_read(dev, 0x0801)
- & 0xFFBF);
-
- b43_gphy_dc_lt_init(dev, 1);
-}
-
-/* HardwarePowerControl init for A and G PHY */
-static void b43_hardware_pctl_init(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
-
- if (!b43_has_hardware_pctl(phy)) {
- /* No hardware power control */
- b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_HWPCTL);
- return;
- }
- /* Init the hwpctl related hardware */
- switch (phy->type) {
- case B43_PHYTYPE_A:
- hardware_pctl_init_aphy(dev);
- break;
- case B43_PHYTYPE_G:
- hardware_pctl_init_gphy(dev);
- break;
- default:
- B43_WARN_ON(1);
- }
- /* Enable hardware pctl in firmware. */
- b43_hf_write(dev, b43_hf_read(dev) | B43_HF_HWPCTL);
-}
-
-static void b43_hardware_pctl_early_init(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
-
- if (!b43_has_hardware_pctl(phy)) {
- b43_phy_write(dev, 0x047A, 0xC111);
- return;
- }
-
- b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036) & 0xFEFF);
- b43_phy_write(dev, 0x002F, 0x0202);
- b43_phy_write(dev, 0x047C, b43_phy_read(dev, 0x047C) | 0x0002);
- b43_phy_write(dev, 0x047A, b43_phy_read(dev, 0x047A) | 0xF000);
- if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
- b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A)
- & 0xFF0F) | 0x0010);
- b43_phy_write(dev, 0x005D, b43_phy_read(dev, 0x005D)
- | 0x8000);
- b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E)
- & 0xFFC0) | 0x0010);
- b43_phy_write(dev, 0x002E, 0xC07F);
- b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
- | 0x0400);
- } else {
- b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
- | 0x0200);
- b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
- | 0x0400);
- b43_phy_write(dev, 0x005D, b43_phy_read(dev, 0x005D)
- & 0x7FFF);
- b43_phy_write(dev, 0x004F, b43_phy_read(dev, 0x004F)
- & 0xFFFE);
- b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E)
- & 0xFFC0) | 0x0010);
- b43_phy_write(dev, 0x002E, 0xC07F);
- b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A)
- & 0xFF0F) | 0x0010);
- }
-}
-
-/* Intialize B/G PHY power control
- * as described in http://bcm-specs.sipsolutions.net/InitPowerControl
- */
-static void b43_phy_init_pctl(struct b43_wldev *dev)
-{
- struct ssb_bus *bus = dev->dev->bus;
- struct b43_phy *phy = &dev->phy;
- struct b43_rfatt old_rfatt;
- struct b43_bbatt old_bbatt;
- u8 old_tx_control = 0;
-
- if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
- (bus->boardinfo.type == SSB_BOARD_BU4306))
- return;
-
- b43_phy_write(dev, 0x0028, 0x8018);
-
- /* This does something with the Analog... */
- b43_write16(dev, B43_MMIO_PHY0, b43_read16(dev, B43_MMIO_PHY0)
- & 0xFFDF);
-
- if (phy->type == B43_PHYTYPE_G && !phy->gmode)
- return;
- b43_hardware_pctl_early_init(dev);
- if (phy->cur_idle_tssi == 0) {
- if (phy->radio_ver == 0x2050 && phy->analog == 0) {
- b43_radio_write16(dev, 0x0076,
- (b43_radio_read16(dev, 0x0076)
- & 0x00F7) | 0x0084);
- } else {
- struct b43_rfatt rfatt;
- struct b43_bbatt bbatt;
-
- memcpy(&old_rfatt, &phy->rfatt, sizeof(old_rfatt));
- memcpy(&old_bbatt, &phy->bbatt, sizeof(old_bbatt));
- old_tx_control = phy->tx_control;
-
- bbatt.att = 11;
- if (phy->radio_rev == 8) {
- rfatt.att = 15;
- rfatt.with_padmix = 1;
- } else {
- rfatt.att = 9;
- rfatt.with_padmix = 0;
- }
- b43_set_txpower_g(dev, &bbatt, &rfatt, 0);
- }
- b43_dummy_transmission(dev);
- phy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_ITSSI);
- if (B43_DEBUG) {
- /* Current-Idle-TSSI sanity check. */
- if (abs(phy->cur_idle_tssi - phy->tgt_idle_tssi) >= 20) {
- b43dbg(dev->wl,
- "!WARNING! Idle-TSSI phy->cur_idle_tssi "
- "measuring failed. (cur=%d, tgt=%d). Disabling TX power "
- "adjustment.\n", phy->cur_idle_tssi,
- phy->tgt_idle_tssi);
- phy->cur_idle_tssi = 0;
- }
- }
- if (phy->radio_ver == 0x2050 && phy->analog == 0) {
- b43_radio_write16(dev, 0x0076,
- b43_radio_read16(dev, 0x0076)
- & 0xFF7B);
- } else {
- b43_set_txpower_g(dev, &old_bbatt,
- &old_rfatt, old_tx_control);
- }
- }
- b43_hardware_pctl_init(dev);
- b43_shm_clear_tssi(dev);
-}
-
-static void b43_phy_rssiagc(struct b43_wldev *dev, u8 enable)
-{
- int i;
-
- if (dev->phy.rev < 3) {
- if (enable)
- for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) {
- b43_ofdmtab_write16(dev,
- B43_OFDMTAB_LNAHPFGAIN1, i, 0xFFF8);
- b43_ofdmtab_write16(dev,
- B43_OFDMTAB_WRSSI, i, 0xFFF8);
- }
- else
- for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) {
- b43_ofdmtab_write16(dev,
- B43_OFDMTAB_LNAHPFGAIN1, i, b43_tab_rssiagc1[i]);
- b43_ofdmtab_write16(dev,
- B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc1[i]);
- }
- } else {
- if (enable)
- for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++)
- b43_ofdmtab_write16(dev,
- B43_OFDMTAB_WRSSI, i, 0x0820);
- else
- for (i = 0; i < B43_TAB_RSSIAGC2_SIZE; i++)
- b43_ofdmtab_write16(dev,
- B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc2[i]);
- }
-}
-
-static void b43_phy_ww(struct b43_wldev *dev)
-{
- u16 b, curr_s, best_s = 0xFFFF;
- int i;
-
- b43_phy_write(dev, B43_PHY_CRS0,
- b43_phy_read(dev, B43_PHY_CRS0) & ~B43_PHY_CRS0_EN);
- b43_phy_write(dev, B43_PHY_OFDM(0x1B),
- b43_phy_read(dev, B43_PHY_OFDM(0x1B)) | 0x1000);
- b43_phy_write(dev, B43_PHY_OFDM(0x82),
- (b43_phy_read(dev, B43_PHY_OFDM(0x82)) & 0xF0FF) | 0x0300);
- b43_radio_write16(dev, 0x0009,
- b43_radio_read16(dev, 0x0009) | 0x0080);
- b43_radio_write16(dev, 0x0012,
- (b43_radio_read16(dev, 0x0012) & 0xFFFC) | 0x0002);
- b43_wa_initgains(dev);
- b43_phy_write(dev, B43_PHY_OFDM(0xBA), 0x3ED5);
- b = b43_phy_read(dev, B43_PHY_PWRDOWN);
- b43_phy_write(dev, B43_PHY_PWRDOWN, (b & 0xFFF8) | 0x0005);
- b43_radio_write16(dev, 0x0004,
- b43_radio_read16(dev, 0x0004) | 0x0004);
- for (i = 0x10; i <= 0x20; i++) {
- b43_radio_write16(dev, 0x0013, i);
- curr_s = b43_phy_read(dev, B43_PHY_OTABLEQ) & 0x00FF;
- if (!curr_s) {
- best_s = 0x0000;
- break;
- } else if (curr_s >= 0x0080)
- curr_s = 0x0100 - curr_s;
- if (curr_s < best_s)
- best_s = curr_s;
- }
- b43_phy_write(dev, B43_PHY_PWRDOWN, b);
- b43_radio_write16(dev, 0x0004,
- b43_radio_read16(dev, 0x0004) & 0xFFFB);
- b43_radio_write16(dev, 0x0013, best_s);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 0xFFEC);
- b43_phy_write(dev, B43_PHY_OFDM(0xB7), 0x1E80);
- b43_phy_write(dev, B43_PHY_OFDM(0xB6), 0x1C00);
- b43_phy_write(dev, B43_PHY_OFDM(0xB5), 0x0EC0);
- b43_phy_write(dev, B43_PHY_OFDM(0xB2), 0x00C0);
- b43_phy_write(dev, B43_PHY_OFDM(0xB9), 0x1FFF);
- b43_phy_write(dev, B43_PHY_OFDM(0xBB),
- (b43_phy_read(dev, B43_PHY_OFDM(0xBB)) & 0xF000) | 0x0053);
- b43_phy_write(dev, B43_PHY_OFDM61,
- (b43_phy_read(dev, B43_PHY_OFDM61) & 0xFE1F) | 0x0120);
- b43_phy_write(dev, B43_PHY_OFDM(0x13),
- (b43_phy_read(dev, B43_PHY_OFDM(0x13)) & 0x0FFF) | 0x3000);
- b43_phy_write(dev, B43_PHY_OFDM(0x14),
- (b43_phy_read(dev, B43_PHY_OFDM(0x14)) & 0x0FFF) | 0x3000);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 6, 0x0017);
- for (i = 0; i < 6; i++)
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, i, 0x000F);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0D, 0x000E);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0E, 0x0011);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0F, 0x0013);
- b43_phy_write(dev, B43_PHY_OFDM(0x33), 0x5030);
- b43_phy_write(dev, B43_PHY_CRS0,
- b43_phy_read(dev, B43_PHY_CRS0) | B43_PHY_CRS0_EN);
-}
-
-/* Initialize APHY. This is also called for the GPHY in some cases. */
-static void b43_phy_inita(struct b43_wldev *dev)
-{
- struct ssb_bus *bus = dev->dev->bus;
- struct b43_phy *phy = &dev->phy;
-
- might_sleep();
-
- if (phy->rev >= 6) {
- if (phy->type == B43_PHYTYPE_A)
- b43_phy_write(dev, B43_PHY_OFDM(0x1B),
- b43_phy_read(dev, B43_PHY_OFDM(0x1B)) & ~0x1000);
- if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN)
- b43_phy_write(dev, B43_PHY_ENCORE,
- b43_phy_read(dev, B43_PHY_ENCORE) | 0x0010);
- else
- b43_phy_write(dev, B43_PHY_ENCORE,
- b43_phy_read(dev, B43_PHY_ENCORE) & ~0x1010);
- }
-
- b43_wa_all(dev);
-
- if (phy->type == B43_PHYTYPE_A) {
- if (phy->gmode && (phy->rev < 3))
- b43_phy_write(dev, 0x0034,
- b43_phy_read(dev, 0x0034) | 0x0001);
- b43_phy_rssiagc(dev, 0);
-
- b43_phy_write(dev, B43_PHY_CRS0,
- b43_phy_read(dev, B43_PHY_CRS0) | B43_PHY_CRS0_EN);
-
- b43_radio_init2060(dev);
-
- if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
- ((bus->boardinfo.type == SSB_BOARD_BU4306) ||
- (bus->boardinfo.type == SSB_BOARD_BU4309))) {
- ; //TODO: A PHY LO
- }
-
- if (phy->rev >= 3)
- b43_phy_ww(dev);
-
- hardware_pctl_init_aphy(dev);
-
- //TODO: radar detection
- }
-
- if ((phy->type == B43_PHYTYPE_G) &&
- (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)) {
- b43_phy_write(dev, B43_PHY_OFDM(0x6E),
- (b43_phy_read(dev, B43_PHY_OFDM(0x6E))
- & 0xE000) | 0x3CF);
- }
-}
-
-static void b43_phy_initb5(struct b43_wldev *dev)
-{
- struct ssb_bus *bus = dev->dev->bus;
- struct b43_phy *phy = &dev->phy;
- u16 offset, value;
- u8 old_channel;
-
- if (phy->analog == 1) {
- b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A)
- | 0x0050);
- }
- if ((bus->boardinfo.vendor != SSB_BOARDVENDOR_BCM) &&
- (bus->boardinfo.type != SSB_BOARD_BU4306)) {
- value = 0x2120;
- for (offset = 0x00A8; offset < 0x00C7; offset++) {
- b43_phy_write(dev, offset, value);
- value += 0x202;
- }
- }
- b43_phy_write(dev, 0x0035, (b43_phy_read(dev, 0x0035) & 0xF0FF)
- | 0x0700);
- if (phy->radio_ver == 0x2050)
- b43_phy_write(dev, 0x0038, 0x0667);
-
- if (phy->gmode || phy->rev >= 2) {
- if (phy->radio_ver == 0x2050) {
- b43_radio_write16(dev, 0x007A,
- b43_radio_read16(dev, 0x007A)
- | 0x0020);
- b43_radio_write16(dev, 0x0051,
- b43_radio_read16(dev, 0x0051)
- | 0x0004);
- }
- b43_write16(dev, B43_MMIO_PHY_RADIO, 0x0000);
-
- b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x0100);
- b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x2000);
-
- b43_phy_write(dev, 0x001C, 0x186A);
-
- b43_phy_write(dev, 0x0013,
- (b43_phy_read(dev, 0x0013) & 0x00FF) | 0x1900);
- b43_phy_write(dev, 0x0035,
- (b43_phy_read(dev, 0x0035) & 0xFFC0) | 0x0064);
- b43_phy_write(dev, 0x005D,
- (b43_phy_read(dev, 0x005D) & 0xFF80) | 0x000A);
- }
-
- if (dev->bad_frames_preempt) {
- b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
- b43_phy_read(dev,
- B43_PHY_RADIO_BITFIELD) | (1 << 11));
- }
-
- if (phy->analog == 1) {
- b43_phy_write(dev, 0x0026, 0xCE00);
- b43_phy_write(dev, 0x0021, 0x3763);
- b43_phy_write(dev, 0x0022, 0x1BC3);
- b43_phy_write(dev, 0x0023, 0x06F9);
- b43_phy_write(dev, 0x0024, 0x037E);
- } else
- b43_phy_write(dev, 0x0026, 0xCC00);
- b43_phy_write(dev, 0x0030, 0x00C6);
- b43_write16(dev, 0x03EC, 0x3F22);
-
- if (phy->analog == 1)
- b43_phy_write(dev, 0x0020, 0x3E1C);
- else
- b43_phy_write(dev, 0x0020, 0x301C);
-
- if (phy->analog == 0)
- b43_write16(dev, 0x03E4, 0x3000);
-
- old_channel = phy->channel;
- /* Force to channel 7, even if not supported. */
- b43_radio_selectchannel(dev, 7, 0);
-
- if (phy->radio_ver != 0x2050) {
- b43_radio_write16(dev, 0x0075, 0x0080);
- b43_radio_write16(dev, 0x0079, 0x0081);
- }
-
- b43_radio_write16(dev, 0x0050, 0x0020);
- b43_radio_write16(dev, 0x0050, 0x0023);
-
- if (phy->radio_ver == 0x2050) {
- b43_radio_write16(dev, 0x0050, 0x0020);
- b43_radio_write16(dev, 0x005A, 0x0070);
- }
-
- b43_radio_write16(dev, 0x005B, 0x007B);
- b43_radio_write16(dev, 0x005C, 0x00B0);
-
- b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0007);
-
- b43_radio_selectchannel(dev, old_channel, 0);
-
- b43_phy_write(dev, 0x0014, 0x0080);
- b43_phy_write(dev, 0x0032, 0x00CA);
- b43_phy_write(dev, 0x002A, 0x88A3);
-
- b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
-
- if (phy->radio_ver == 0x2050)
- b43_radio_write16(dev, 0x005D, 0x000D);
-
- b43_write16(dev, 0x03E4, (b43_read16(dev, 0x03E4) & 0xFFC0) | 0x0004);
-}
-
-static void b43_phy_initb6(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- u16 offset, val;
- u8 old_channel;
-
- b43_phy_write(dev, 0x003E, 0x817A);
- b43_radio_write16(dev, 0x007A,
- (b43_radio_read16(dev, 0x007A) | 0x0058));
- if (phy->radio_rev == 4 || phy->radio_rev == 5) {
- b43_radio_write16(dev, 0x51, 0x37);
- b43_radio_write16(dev, 0x52, 0x70);
- b43_radio_write16(dev, 0x53, 0xB3);
- b43_radio_write16(dev, 0x54, 0x9B);
- b43_radio_write16(dev, 0x5A, 0x88);
- b43_radio_write16(dev, 0x5B, 0x88);
- b43_radio_write16(dev, 0x5D, 0x88);
- b43_radio_write16(dev, 0x5E, 0x88);
- b43_radio_write16(dev, 0x7D, 0x88);
- b43_hf_write(dev, b43_hf_read(dev)
- | B43_HF_TSSIRPSMW);
- }
- B43_WARN_ON(phy->radio_rev == 6 || phy->radio_rev == 7); /* We had code for these revs here... */
- if (phy->radio_rev == 8) {
- b43_radio_write16(dev, 0x51, 0);
- b43_radio_write16(dev, 0x52, 0x40);
- b43_radio_write16(dev, 0x53, 0xB7);
- b43_radio_write16(dev, 0x54, 0x98);
- b43_radio_write16(dev, 0x5A, 0x88);
- b43_radio_write16(dev, 0x5B, 0x6B);
- b43_radio_write16(dev, 0x5C, 0x0F);
- if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_ALTIQ) {
- b43_radio_write16(dev, 0x5D, 0xFA);
- b43_radio_write16(dev, 0x5E, 0xD8);
- } else {
- b43_radio_write16(dev, 0x5D, 0xF5);
- b43_radio_write16(dev, 0x5E, 0xB8);
- }
- b43_radio_write16(dev, 0x0073, 0x0003);
- b43_radio_write16(dev, 0x007D, 0x00A8);
- b43_radio_write16(dev, 0x007C, 0x0001);
- b43_radio_write16(dev, 0x007E, 0x0008);
- }
- val = 0x1E1F;
- for (offset = 0x0088; offset < 0x0098; offset++) {
- b43_phy_write(dev, offset, val);
- val -= 0x0202;
- }
- val = 0x3E3F;
- for (offset = 0x0098; offset < 0x00A8; offset++) {
- b43_phy_write(dev, offset, val);
- val -= 0x0202;
- }
- val = 0x2120;
- for (offset = 0x00A8; offset < 0x00C8; offset++) {
- b43_phy_write(dev, offset, (val & 0x3F3F));
- val += 0x0202;
- }
- if (phy->type == B43_PHYTYPE_G) {
- b43_radio_write16(dev, 0x007A,
- b43_radio_read16(dev, 0x007A) | 0x0020);
- b43_radio_write16(dev, 0x0051,
- b43_radio_read16(dev, 0x0051) | 0x0004);
- b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x0100);
- b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x2000);
- b43_phy_write(dev, 0x5B, 0);
- b43_phy_write(dev, 0x5C, 0);
- }
-
- old_channel = phy->channel;
- if (old_channel >= 8)
- b43_radio_selectchannel(dev, 1, 0);
- else
- b43_radio_selectchannel(dev, 13, 0);
-
- b43_radio_write16(dev, 0x0050, 0x0020);
- b43_radio_write16(dev, 0x0050, 0x0023);
- udelay(40);
- if (phy->radio_rev < 6 || phy->radio_rev == 8) {
- b43_radio_write16(dev, 0x7C, (b43_radio_read16(dev, 0x7C)
- | 0x0002));
- b43_radio_write16(dev, 0x50, 0x20);
- }
- if (phy->radio_rev <= 2) {
- b43_radio_write16(dev, 0x7C, 0x20);
- b43_radio_write16(dev, 0x5A, 0x70);
- b43_radio_write16(dev, 0x5B, 0x7B);
- b43_radio_write16(dev, 0x5C, 0xB0);
- }
- b43_radio_write16(dev, 0x007A,
- (b43_radio_read16(dev, 0x007A) & 0x00F8) | 0x0007);
-
- b43_radio_selectchannel(dev, old_channel, 0);
-
- b43_phy_write(dev, 0x0014, 0x0200);
- if (phy->radio_rev >= 6)
- b43_phy_write(dev, 0x2A, 0x88C2);
- else
- b43_phy_write(dev, 0x2A, 0x8AC0);
- b43_phy_write(dev, 0x0038, 0x0668);
- b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
- if (phy->radio_rev <= 5) {
- b43_phy_write(dev, 0x5D, (b43_phy_read(dev, 0x5D)
- & 0xFF80) | 0x0003);
- }
- if (phy->radio_rev <= 2)
- b43_radio_write16(dev, 0x005D, 0x000D);
-
- if (phy->analog == 4) {
- b43_write16(dev, 0x3E4, 9);
- b43_phy_write(dev, 0x61, b43_phy_read(dev, 0x61)
- & 0x0FFF);
- } else {
- b43_phy_write(dev, 0x0002, (b43_phy_read(dev, 0x0002) & 0xFFC0)
- | 0x0004);
- }
- if (phy->type == B43_PHYTYPE_B)
- B43_WARN_ON(1);
- else if (phy->type == B43_PHYTYPE_G)
- b43_write16(dev, 0x03E6, 0x0);
-}
-
-static void b43_calc_loopback_gain(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- u16 backup_phy[16] = { 0 };
- u16 backup_radio[3];
- u16 backup_bband;
- u16 i, j, loop_i_max;
- u16 trsw_rx;
- u16 loop1_outer_done, loop1_inner_done;
-
- backup_phy[0] = b43_phy_read(dev, B43_PHY_CRS0);
- backup_phy[1] = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
- backup_phy[2] = b43_phy_read(dev, B43_PHY_RFOVER);
- backup_phy[3] = b43_phy_read(dev, B43_PHY_RFOVERVAL);
- if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
- backup_phy[4] = b43_phy_read(dev, B43_PHY_ANALOGOVER);
- backup_phy[5] = b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
- }
- backup_phy[6] = b43_phy_read(dev, B43_PHY_CCK(0x5A));
- backup_phy[7] = b43_phy_read(dev, B43_PHY_CCK(0x59));
- backup_phy[8] = b43_phy_read(dev, B43_PHY_CCK(0x58));
- backup_phy[9] = b43_phy_read(dev, B43_PHY_CCK(0x0A));
- backup_phy[10] = b43_phy_read(dev, B43_PHY_CCK(0x03));
- backup_phy[11] = b43_phy_read(dev, B43_PHY_LO_MASK);
- backup_phy[12] = b43_phy_read(dev, B43_PHY_LO_CTL);
- backup_phy[13] = b43_phy_read(dev, B43_PHY_CCK(0x2B));
- backup_phy[14] = b43_phy_read(dev, B43_PHY_PGACTL);
- backup_phy[15] = b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
- backup_bband = phy->bbatt.att;
- backup_radio[0] = b43_radio_read16(dev, 0x52);
- backup_radio[1] = b43_radio_read16(dev, 0x43);
- backup_radio[2] = b43_radio_read16(dev, 0x7A);
-
- b43_phy_write(dev, B43_PHY_CRS0,
- b43_phy_read(dev, B43_PHY_CRS0) & 0x3FFF);
- b43_phy_write(dev, B43_PHY_CCKBBANDCFG,
- b43_phy_read(dev, B43_PHY_CCKBBANDCFG) | 0x8000);
- b43_phy_write(dev, B43_PHY_RFOVER,
- b43_phy_read(dev, B43_PHY_RFOVER) | 0x0002);
- b43_phy_write(dev, B43_PHY_RFOVERVAL,
- b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xFFFD);
- b43_phy_write(dev, B43_PHY_RFOVER,
- b43_phy_read(dev, B43_PHY_RFOVER) | 0x0001);
- b43_phy_write(dev, B43_PHY_RFOVERVAL,
- b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xFFFE);
- if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
- b43_phy_write(dev, B43_PHY_ANALOGOVER,
- b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0001);
- b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
- b43_phy_read(dev,
- B43_PHY_ANALOGOVERVAL) & 0xFFFE);
- b43_phy_write(dev, B43_PHY_ANALOGOVER,
- b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0002);
- b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
- b43_phy_read(dev,
- B43_PHY_ANALOGOVERVAL) & 0xFFFD);
- }
- b43_phy_write(dev, B43_PHY_RFOVER,
- b43_phy_read(dev, B43_PHY_RFOVER) | 0x000C);
- b43_phy_write(dev, B43_PHY_RFOVERVAL,
- b43_phy_read(dev, B43_PHY_RFOVERVAL) | 0x000C);
- b43_phy_write(dev, B43_PHY_RFOVER,
- b43_phy_read(dev, B43_PHY_RFOVER) | 0x0030);
- b43_phy_write(dev, B43_PHY_RFOVERVAL,
- (b43_phy_read(dev, B43_PHY_RFOVERVAL)
- & 0xFFCF) | 0x10);
-
- b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0780);
- b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
- b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
-
- b43_phy_write(dev, B43_PHY_CCK(0x0A),
- b43_phy_read(dev, B43_PHY_CCK(0x0A)) | 0x2000);
- if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
- b43_phy_write(dev, B43_PHY_ANALOGOVER,
- b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0004);
- b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
- b43_phy_read(dev,
- B43_PHY_ANALOGOVERVAL) & 0xFFFB);
- }
- b43_phy_write(dev, B43_PHY_CCK(0x03),
- (b43_phy_read(dev, B43_PHY_CCK(0x03))
- & 0xFF9F) | 0x40);
-
- if (phy->radio_rev == 8) {
- b43_radio_write16(dev, 0x43, 0x000F);
- } else {
- b43_radio_write16(dev, 0x52, 0);
- b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
- & 0xFFF0) | 0x9);
- }
- b43_phy_set_baseband_attenuation(dev, 11);
-
- if (phy->rev >= 3)
- b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
- else
- b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
- b43_phy_write(dev, B43_PHY_LO_CTL, 0);
-
- b43_phy_write(dev, B43_PHY_CCK(0x2B),
- (b43_phy_read(dev, B43_PHY_CCK(0x2B))
- & 0xFFC0) | 0x01);
- b43_phy_write(dev, B43_PHY_CCK(0x2B),
- (b43_phy_read(dev, B43_PHY_CCK(0x2B))
- & 0xC0FF) | 0x800);
-
- b43_phy_write(dev, B43_PHY_RFOVER,
- b43_phy_read(dev, B43_PHY_RFOVER) | 0x0100);
- b43_phy_write(dev, B43_PHY_RFOVERVAL,
- b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xCFFF);
-
- if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_EXTLNA) {
- if (phy->rev >= 7) {
- b43_phy_write(dev, B43_PHY_RFOVER,
- b43_phy_read(dev, B43_PHY_RFOVER)
- | 0x0800);
- b43_phy_write(dev, B43_PHY_RFOVERVAL,
- b43_phy_read(dev, B43_PHY_RFOVERVAL)
- | 0x8000);
- }
- }
- b43_radio_write16(dev, 0x7A, b43_radio_read16(dev, 0x7A)
- & 0x00F7);
-
- j = 0;
- loop_i_max = (phy->radio_rev == 8) ? 15 : 9;
- for (i = 0; i < loop_i_max; i++) {
- for (j = 0; j < 16; j++) {
- b43_radio_write16(dev, 0x43, i);
- b43_phy_write(dev, B43_PHY_RFOVERVAL,
- (b43_phy_read(dev, B43_PHY_RFOVERVAL)
- & 0xF0FF) | (j << 8));
- b43_phy_write(dev, B43_PHY_PGACTL,
- (b43_phy_read(dev, B43_PHY_PGACTL)
- & 0x0FFF) | 0xA000);
- b43_phy_write(dev, B43_PHY_PGACTL,
- b43_phy_read(dev, B43_PHY_PGACTL)
- | 0xF000);
- udelay(20);
- if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
- goto exit_loop1;
- }
- }
- exit_loop1:
- loop1_outer_done = i;
- loop1_inner_done = j;
- if (j >= 8) {
- b43_phy_write(dev, B43_PHY_RFOVERVAL,
- b43_phy_read(dev, B43_PHY_RFOVERVAL)
- | 0x30);
- trsw_rx = 0x1B;
- for (j = j - 8; j < 16; j++) {
- b43_phy_write(dev, B43_PHY_RFOVERVAL,
- (b43_phy_read(dev, B43_PHY_RFOVERVAL)
- & 0xF0FF) | (j << 8));
- b43_phy_write(dev, B43_PHY_PGACTL,
- (b43_phy_read(dev, B43_PHY_PGACTL)
- & 0x0FFF) | 0xA000);
- b43_phy_write(dev, B43_PHY_PGACTL,
- b43_phy_read(dev, B43_PHY_PGACTL)
- | 0xF000);
- udelay(20);
- trsw_rx -= 3;
- if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
- goto exit_loop2;
- }
- } else
- trsw_rx = 0x18;
- exit_loop2:
-
- if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
- b43_phy_write(dev, B43_PHY_ANALOGOVER, backup_phy[4]);
- b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, backup_phy[5]);
- }
- b43_phy_write(dev, B43_PHY_CCK(0x5A), backup_phy[6]);
- b43_phy_write(dev, B43_PHY_CCK(0x59), backup_phy[7]);
- b43_phy_write(dev, B43_PHY_CCK(0x58), backup_phy[8]);
- b43_phy_write(dev, B43_PHY_CCK(0x0A), backup_phy[9]);
- b43_phy_write(dev, B43_PHY_CCK(0x03), backup_phy[10]);
- b43_phy_write(dev, B43_PHY_LO_MASK, backup_phy[11]);
- b43_phy_write(dev, B43_PHY_LO_CTL, backup_phy[12]);
- b43_phy_write(dev, B43_PHY_CCK(0x2B), backup_phy[13]);
- b43_phy_write(dev, B43_PHY_PGACTL, backup_phy[14]);
-
- b43_phy_set_baseband_attenuation(dev, backup_bband);
-
- b43_radio_write16(dev, 0x52, backup_radio[0]);
- b43_radio_write16(dev, 0x43, backup_radio[1]);
- b43_radio_write16(dev, 0x7A, backup_radio[2]);
-
- b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2] | 0x0003);
- udelay(10);
- b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2]);
- b43_phy_write(dev, B43_PHY_RFOVERVAL, backup_phy[3]);
- b43_phy_write(dev, B43_PHY_CRS0, backup_phy[0]);
- b43_phy_write(dev, B43_PHY_CCKBBANDCFG, backup_phy[1]);
-
- phy->max_lb_gain =
- ((loop1_inner_done * 6) - (loop1_outer_done * 4)) - 11;
- phy->trsw_rx_gain = trsw_rx * 2;
-}
-
-static void b43_phy_initg(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- u16 tmp;
-
- if (phy->rev == 1)
- b43_phy_initb5(dev);
- else
- b43_phy_initb6(dev);
-
- if (phy->rev >= 2 || phy->gmode)
- b43_phy_inita(dev);
-
- if (phy->rev >= 2) {
- b43_phy_write(dev, B43_PHY_ANALOGOVER, 0);
- b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 0);
- }
- if (phy->rev == 2) {
- b43_phy_write(dev, B43_PHY_RFOVER, 0);
- b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
- }
- if (phy->rev > 5) {
- b43_phy_write(dev, B43_PHY_RFOVER, 0x400);
- b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
- }
- if (phy->gmode || phy->rev >= 2) {
- tmp = b43_phy_read(dev, B43_PHY_VERSION_OFDM);
- tmp &= B43_PHYVER_VERSION;
- if (tmp == 3 || tmp == 5) {
- b43_phy_write(dev, B43_PHY_OFDM(0xC2), 0x1816);
- b43_phy_write(dev, B43_PHY_OFDM(0xC3), 0x8006);
- }
- if (tmp == 5) {
- b43_phy_write(dev, B43_PHY_OFDM(0xCC),
- (b43_phy_read(dev, B43_PHY_OFDM(0xCC))
- & 0x00FF) | 0x1F00);
- }
- }
- if ((phy->rev <= 2 && phy->gmode) || phy->rev >= 2)
- b43_phy_write(dev, B43_PHY_OFDM(0x7E), 0x78);
- if (phy->radio_rev == 8) {
- b43_phy_write(dev, B43_PHY_EXTG(0x01),
- b43_phy_read(dev, B43_PHY_EXTG(0x01))
- | 0x80);
- b43_phy_write(dev, B43_PHY_OFDM(0x3E),
- b43_phy_read(dev, B43_PHY_OFDM(0x3E))
- | 0x4);
- }
- if (has_loopback_gain(phy))
- b43_calc_loopback_gain(dev);
-
- if (phy->radio_rev != 8) {
- if (phy->initval == 0xFFFF)
- phy->initval = b43_radio_init2050(dev);
- else
- b43_radio_write16(dev, 0x0078, phy->initval);
- }
- b43_lo_g_init(dev);
- if (has_tx_magnification(phy)) {
- b43_radio_write16(dev, 0x52,
- (b43_radio_read16(dev, 0x52) & 0xFF00)
- | phy->lo_control->tx_bias | phy->
- lo_control->tx_magn);
- } else {
- b43_radio_write16(dev, 0x52,
- (b43_radio_read16(dev, 0x52) & 0xFFF0)
- | phy->lo_control->tx_bias);
- }
- if (phy->rev >= 6) {
- b43_phy_write(dev, B43_PHY_CCK(0x36),
- (b43_phy_read(dev, B43_PHY_CCK(0x36))
- & 0x0FFF) | (phy->lo_control->
- tx_bias << 12));
- }
- if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)
- b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075);
- else
- b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x807F);
- if (phy->rev < 2)
- b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x101);
- else
- b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x202);
- if (phy->gmode || phy->rev >= 2) {
- b43_lo_g_adjust(dev);
- b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078);
- }
-
- if (!(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI)) {
- /* The specs state to update the NRSSI LT with
- * the value 0x7FFFFFFF here. I think that is some weird
- * compiler optimization in the original driver.
- * Essentially, what we do here is resetting all NRSSI LT
- * entries to -32 (see the clamp_val() in nrssi_hw_update())
- */
- b43_nrssi_hw_update(dev, 0xFFFF); //FIXME?
- b43_calc_nrssi_threshold(dev);
- } else if (phy->gmode || phy->rev >= 2) {
- if (phy->nrssi[0] == -1000) {
- B43_WARN_ON(phy->nrssi[1] != -1000);
- b43_calc_nrssi_slope(dev);
- } else
- b43_calc_nrssi_threshold(dev);
- }
- if (phy->radio_rev == 8)
- b43_phy_write(dev, B43_PHY_EXTG(0x05), 0x3230);
- b43_phy_init_pctl(dev);
- /* FIXME: The spec says in the following if, the 0 should be replaced
- 'if OFDM may not be used in the current locale'
- but OFDM is legal everywhere */
- if ((dev->dev->bus->chip_id == 0x4306
- && dev->dev->bus->chip_package == 2) || 0) {
- b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
- & 0xBFFF);
- b43_phy_write(dev, B43_PHY_OFDM(0xC3),
- b43_phy_read(dev, B43_PHY_OFDM(0xC3))
- & 0x7FFF);
- }
-}
-
-/* Set the baseband attenuation value on chip. */
-void b43_phy_set_baseband_attenuation(struct b43_wldev *dev,
- u16 baseband_attenuation)
-{
- struct b43_phy *phy = &dev->phy;
-
- if (phy->analog == 0) {
- b43_write16(dev, B43_MMIO_PHY0, (b43_read16(dev, B43_MMIO_PHY0)
- & 0xFFF0) |
- baseband_attenuation);
- } else if (phy->analog > 1) {
- b43_phy_write(dev, B43_PHY_DACCTL,
- (b43_phy_read(dev, B43_PHY_DACCTL)
- & 0xFFC3) | (baseband_attenuation << 2));
- } else {
- b43_phy_write(dev, B43_PHY_DACCTL,
- (b43_phy_read(dev, B43_PHY_DACCTL)
- & 0xFF87) | (baseband_attenuation << 3));
- }
-}
-
-/* http://bcm-specs.sipsolutions.net/EstimatePowerOut
- * This function converts a TSSI value to dBm in Q5.2
- */
-static s8 b43_phy_estimate_power_out(struct b43_wldev *dev, s8 tssi)
-{
- struct b43_phy *phy = &dev->phy;
- s8 dbm = 0;
- s32 tmp;
-
- tmp = (phy->tgt_idle_tssi - phy->cur_idle_tssi + tssi);
-
- switch (phy->type) {
- case B43_PHYTYPE_A:
- tmp += 0x80;
- tmp = clamp_val(tmp, 0x00, 0xFF);
- dbm = phy->tssi2dbm[tmp];
- //TODO: There's a FIXME on the specs
- break;
- case B43_PHYTYPE_B:
- case B43_PHYTYPE_G:
- tmp = clamp_val(tmp, 0x00, 0x3F);
- dbm = phy->tssi2dbm[tmp];
- break;
- default:
- B43_WARN_ON(1);
- }
-
- return dbm;
-}
-
-void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
- int *_bbatt, int *_rfatt)
-{
- int rfatt = *_rfatt;
- int bbatt = *_bbatt;
- struct b43_txpower_lo_control *lo = dev->phy.lo_control;
-
- /* Get baseband and radio attenuation values into their permitted ranges.
- * Radio attenuation affects power level 4 times as much as baseband. */
-
- /* Range constants */
- const int rf_min = lo->rfatt_list.min_val;
- const int rf_max = lo->rfatt_list.max_val;
- const int bb_min = lo->bbatt_list.min_val;
- const int bb_max = lo->bbatt_list.max_val;
-
- while (1) {
- if (rfatt > rf_max && bbatt > bb_max - 4)
- break; /* Can not get it into ranges */
- if (rfatt < rf_min && bbatt < bb_min + 4)
- break; /* Can not get it into ranges */
- if (bbatt > bb_max && rfatt > rf_max - 1)
- break; /* Can not get it into ranges */
- if (bbatt < bb_min && rfatt < rf_min + 1)
- break; /* Can not get it into ranges */
-
- if (bbatt > bb_max) {
- bbatt -= 4;
- rfatt += 1;
- continue;
- }
- if (bbatt < bb_min) {
- bbatt += 4;
- rfatt -= 1;
- continue;
- }
- if (rfatt > rf_max) {
- rfatt -= 1;
- bbatt += 4;
- continue;
- }
- if (rfatt < rf_min) {
- rfatt += 1;
- bbatt -= 4;
- continue;
- }
- break;
- }
-
- *_rfatt = clamp_val(rfatt, rf_min, rf_max);
- *_bbatt = clamp_val(bbatt, bb_min, bb_max);
-}
-
-/* http://bcm-specs.sipsolutions.net/RecalculateTransmissionPower */
-void b43_phy_xmitpower(struct b43_wldev *dev)
-{
- struct ssb_bus *bus = dev->dev->bus;
- struct b43_phy *phy = &dev->phy;
-
- if (phy->cur_idle_tssi == 0)
- return;
- if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
- (bus->boardinfo.type == SSB_BOARD_BU4306))
- return;
-#ifdef CONFIG_B43_DEBUG
- if (phy->manual_txpower_control)
- return;
-#endif
-
- switch (phy->type) {
- case B43_PHYTYPE_A:{
-
- //TODO: Nothing for A PHYs yet :-/
-
- break;
- }
- case B43_PHYTYPE_B:
- case B43_PHYTYPE_G:{
- u16 tmp;
- s8 v0, v1, v2, v3;
- s8 average;
- int max_pwr;
- int desired_pwr, estimated_pwr, pwr_adjust;
- int rfatt_delta, bbatt_delta;
- int rfatt, bbatt;
- u8 tx_control;
-
- tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x0058);
- v0 = (s8) (tmp & 0x00FF);
- v1 = (s8) ((tmp & 0xFF00) >> 8);
- tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x005A);
- v2 = (s8) (tmp & 0x00FF);
- v3 = (s8) ((tmp & 0xFF00) >> 8);
- tmp = 0;
-
- if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F
- || v3 == 0x7F) {
- tmp =
- b43_shm_read16(dev, B43_SHM_SHARED, 0x0070);
- v0 = (s8) (tmp & 0x00FF);
- v1 = (s8) ((tmp & 0xFF00) >> 8);
- tmp =
- b43_shm_read16(dev, B43_SHM_SHARED, 0x0072);
- v2 = (s8) (tmp & 0x00FF);
- v3 = (s8) ((tmp & 0xFF00) >> 8);
- if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F
- || v3 == 0x7F)
- return;
- v0 = (v0 + 0x20) & 0x3F;
- v1 = (v1 + 0x20) & 0x3F;
- v2 = (v2 + 0x20) & 0x3F;
- v3 = (v3 + 0x20) & 0x3F;
- tmp = 1;
- }
- b43_shm_clear_tssi(dev);
-
- average = (v0 + v1 + v2 + v3 + 2) / 4;
-
- if (tmp
- && (b43_shm_read16(dev, B43_SHM_SHARED, 0x005E) &
- 0x8))
- average -= 13;
-
- estimated_pwr =
- b43_phy_estimate_power_out(dev, average);
-
- max_pwr = dev->dev->bus->sprom.maxpwr_bg;
- if ((dev->dev->bus->sprom.boardflags_lo
- & B43_BFL_PACTRL) && (phy->type == B43_PHYTYPE_G))
- max_pwr -= 0x3;
- if (unlikely(max_pwr <= 0)) {
- b43warn(dev->wl,
- "Invalid max-TX-power value in SPROM.\n");
- max_pwr = 60; /* fake it */
- dev->dev->bus->sprom.maxpwr_bg = max_pwr;
- }
-
- /*TODO:
- max_pwr = min(REG - dev->dev->bus->sprom.antennagain_bgphy - 0x6, max_pwr)
- where REG is the max power as per the regulatory domain
- */
-
- /* Get desired power (in Q5.2) */
- desired_pwr = INT_TO_Q52(phy->power_level);
- /* And limit it. max_pwr already is Q5.2 */
- desired_pwr = clamp_val(desired_pwr, 0, max_pwr);
- if (b43_debug(dev, B43_DBG_XMITPOWER)) {
- b43dbg(dev->wl,
- "Current TX power output: " Q52_FMT
- " dBm, " "Desired TX power output: "
- Q52_FMT " dBm\n", Q52_ARG(estimated_pwr),
- Q52_ARG(desired_pwr));
- }
-
- /* Calculate the adjustment delta. */
- pwr_adjust = desired_pwr - estimated_pwr;
-
- /* RF attenuation delta. */
- rfatt_delta = ((pwr_adjust + 7) / 8);
- /* Lower attenuation => Bigger power output. Negate it. */
- rfatt_delta = -rfatt_delta;
-
- /* Baseband attenuation delta. */
- bbatt_delta = pwr_adjust / 2;
- /* Lower attenuation => Bigger power output. Negate it. */
- bbatt_delta = -bbatt_delta;
- /* RF att affects power level 4 times as much as
- * Baseband attennuation. Subtract it. */
- bbatt_delta -= 4 * rfatt_delta;
-
- /* So do we finally need to adjust something? */
- if ((rfatt_delta == 0) && (bbatt_delta == 0))
- return;
-
- /* Calculate the new attenuation values. */
- bbatt = phy->bbatt.att;
- bbatt += bbatt_delta;
- rfatt = phy->rfatt.att;
- rfatt += rfatt_delta;
-
- b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
- tx_control = phy->tx_control;
- if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 2)) {
- if (rfatt <= 1) {
- if (tx_control == 0) {
- tx_control =
- B43_TXCTL_PA2DB |
- B43_TXCTL_TXMIX;
- rfatt += 2;
- bbatt += 2;
- } else if (dev->dev->bus->sprom.
- boardflags_lo &
- B43_BFL_PACTRL) {
- bbatt += 4 * (rfatt - 2);
- rfatt = 2;
- }
- } else if (rfatt > 4 && tx_control) {
- tx_control = 0;
- if (bbatt < 3) {
- rfatt -= 3;
- bbatt += 2;
- } else {
- rfatt -= 2;
- bbatt -= 2;
- }
- }
- }
- /* Save the control values */
- phy->tx_control = tx_control;
- b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
- phy->rfatt.att = rfatt;
- phy->bbatt.att = bbatt;
-
- /* Adjust the hardware */
- b43_phy_lock(dev);
- b43_radio_lock(dev);
- b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt,
- phy->tx_control);
- b43_radio_unlock(dev);
- b43_phy_unlock(dev);
- break;
- }
- case B43_PHYTYPE_N:
- b43_nphy_xmitpower(dev);
- break;
- default:
- B43_WARN_ON(1);
- }
-}
-
-static inline s32 b43_tssi2dbm_ad(s32 num, s32 den)
-{
- if (num < 0)
- return num / den;
- else
- return (num + den / 2) / den;
-}
-
-static inline
- s8 b43_tssi2dbm_entry(s8 entry[], u8 index, s16 pab0, s16 pab1, s16 pab2)
-{
- s32 m1, m2, f = 256, q, delta;
- s8 i = 0;
-
- m1 = b43_tssi2dbm_ad(16 * pab0 + index * pab1, 32);
- m2 = max(b43_tssi2dbm_ad(32768 + index * pab2, 256), 1);
- do {
- if (i > 15)
- return -EINVAL;
- q = b43_tssi2dbm_ad(f * 4096 -
- b43_tssi2dbm_ad(m2 * f, 16) * f, 2048);
- delta = abs(q - f);
- f = q;
- i++;
- } while (delta >= 2);
- entry[index] = clamp_val(b43_tssi2dbm_ad(m1 * f, 8192), -127, 128);
- return 0;
-}
-
-/* http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table */
-int b43_phy_init_tssi2dbm_table(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- s16 pab0, pab1, pab2;
- u8 idx;
- s8 *dyn_tssi2dbm;
-
- if (phy->type == B43_PHYTYPE_A) {
- pab0 = (s16) (dev->dev->bus->sprom.pa1b0);
- pab1 = (s16) (dev->dev->bus->sprom.pa1b1);
- pab2 = (s16) (dev->dev->bus->sprom.pa1b2);
- } else {
- pab0 = (s16) (dev->dev->bus->sprom.pa0b0);
- pab1 = (s16) (dev->dev->bus->sprom.pa0b1);
- pab2 = (s16) (dev->dev->bus->sprom.pa0b2);
- }
-
- if ((dev->dev->bus->chip_id == 0x4301) && (phy->radio_ver != 0x2050)) {
- phy->tgt_idle_tssi = 0x34;
- phy->tssi2dbm = b43_tssi2dbm_b_table;
- return 0;
- }
-
- if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
- pab0 != -1 && pab1 != -1 && pab2 != -1) {
- /* The pabX values are set in SPROM. Use them. */
- if (phy->type == B43_PHYTYPE_A) {
- if ((s8) dev->dev->bus->sprom.itssi_a != 0 &&
- (s8) dev->dev->bus->sprom.itssi_a != -1)
- phy->tgt_idle_tssi =
- (s8) (dev->dev->bus->sprom.itssi_a);
- else
- phy->tgt_idle_tssi = 62;
- } else {
- if ((s8) dev->dev->bus->sprom.itssi_bg != 0 &&
- (s8) dev->dev->bus->sprom.itssi_bg != -1)
- phy->tgt_idle_tssi =
- (s8) (dev->dev->bus->sprom.itssi_bg);
- else
- phy->tgt_idle_tssi = 62;
- }
- dyn_tssi2dbm = kmalloc(64, GFP_KERNEL);
- if (dyn_tssi2dbm == NULL) {
- b43err(dev->wl, "Could not allocate memory "
- "for tssi2dbm table\n");
- return -ENOMEM;
- }
- for (idx = 0; idx < 64; idx++)
- if (b43_tssi2dbm_entry
- (dyn_tssi2dbm, idx, pab0, pab1, pab2)) {
- phy->tssi2dbm = NULL;
- b43err(dev->wl, "Could not generate "
- "tssi2dBm table\n");
- kfree(dyn_tssi2dbm);
- return -ENODEV;
- }
- phy->tssi2dbm = dyn_tssi2dbm;
- phy->dyn_tssi_tbl = 1;
- } else {
- /* pabX values not set in SPROM. */
- switch (phy->type) {
- case B43_PHYTYPE_A:
- /* APHY needs a generated table. */
- phy->tssi2dbm = NULL;
- b43err(dev->wl, "Could not generate tssi2dBm "
- "table (wrong SPROM info)!\n");
- return -ENODEV;
- case B43_PHYTYPE_B:
- phy->tgt_idle_tssi = 0x34;
- phy->tssi2dbm = b43_tssi2dbm_b_table;
- break;
- case B43_PHYTYPE_G:
- phy->tgt_idle_tssi = 0x34;
- phy->tssi2dbm = b43_tssi2dbm_g_table;
- break;
- }
- }
-
- return 0;
-}
-
-int b43_phy_init(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- bool unsupported = 0;
- int err = 0;
-
- switch (phy->type) {
- case B43_PHYTYPE_A:
- if (phy->rev == 2 || phy->rev == 3)
- b43_phy_inita(dev);
- else
- unsupported = 1;
- break;
- case B43_PHYTYPE_G:
- b43_phy_initg(dev);
- break;
- case B43_PHYTYPE_N:
- err = b43_phy_initn(dev);
- break;
- default:
- unsupported = 1;
- }
- if (unsupported)
- b43err(dev->wl, "Unknown PHYTYPE found\n");
-
- return err;
-}
-
-void b43_set_rx_antenna(struct b43_wldev *dev, int antenna)
-{
- struct b43_phy *phy = &dev->phy;
- u64 hf;
- u16 tmp;
- int autodiv = 0;
-
- if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1)
- autodiv = 1;
-
- hf = b43_hf_read(dev);
- hf &= ~B43_HF_ANTDIVHELP;
- b43_hf_write(dev, hf);
-
- switch (phy->type) {
- case B43_PHYTYPE_A:
- case B43_PHYTYPE_G:
- tmp = b43_phy_read(dev, B43_PHY_BBANDCFG);
- tmp &= ~B43_PHY_BBANDCFG_RXANT;
- tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
- << B43_PHY_BBANDCFG_RXANT_SHIFT;
- b43_phy_write(dev, B43_PHY_BBANDCFG, tmp);
-
- if (autodiv) {
- tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
- if (antenna == B43_ANTENNA_AUTO0)
- tmp &= ~B43_PHY_ANTDWELL_AUTODIV1;
- else
- tmp |= B43_PHY_ANTDWELL_AUTODIV1;
- b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
- }
- if (phy->type == B43_PHYTYPE_G) {
- tmp = b43_phy_read(dev, B43_PHY_ANTWRSETT);
- if (autodiv)
- tmp |= B43_PHY_ANTWRSETT_ARXDIV;
- else
- tmp &= ~B43_PHY_ANTWRSETT_ARXDIV;
- b43_phy_write(dev, B43_PHY_ANTWRSETT, tmp);
- if (phy->rev >= 2) {
- tmp = b43_phy_read(dev, B43_PHY_OFDM61);
- tmp |= B43_PHY_OFDM61_10;
- b43_phy_write(dev, B43_PHY_OFDM61, tmp);
-
- tmp =
- b43_phy_read(dev, B43_PHY_DIVSRCHGAINBACK);
- tmp = (tmp & 0xFF00) | 0x15;
- b43_phy_write(dev, B43_PHY_DIVSRCHGAINBACK,
- tmp);
-
- if (phy->rev == 2) {
- b43_phy_write(dev, B43_PHY_ADIVRELATED,
- 8);
- } else {
- tmp =
- b43_phy_read(dev,
- B43_PHY_ADIVRELATED);
- tmp = (tmp & 0xFF00) | 8;
- b43_phy_write(dev, B43_PHY_ADIVRELATED,
- tmp);
- }
- }
- if (phy->rev >= 6)
- b43_phy_write(dev, B43_PHY_OFDM9B, 0xDC);
- } else {
- if (phy->rev < 3) {
- tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
- tmp = (tmp & 0xFF00) | 0x24;
- b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
- } else {
- tmp = b43_phy_read(dev, B43_PHY_OFDM61);
- tmp |= 0x10;
- b43_phy_write(dev, B43_PHY_OFDM61, tmp);
- if (phy->analog == 3) {
- b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
- 0x1D);
- b43_phy_write(dev, B43_PHY_ADIVRELATED,
- 8);
- } else {
- b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
- 0x3A);
- tmp =
- b43_phy_read(dev,
- B43_PHY_ADIVRELATED);
- tmp = (tmp & 0xFF00) | 8;
- b43_phy_write(dev, B43_PHY_ADIVRELATED,
- tmp);
- }
- }
- }
- break;
- case B43_PHYTYPE_B:
- tmp = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
- tmp &= ~B43_PHY_BBANDCFG_RXANT;
- tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
- << B43_PHY_BBANDCFG_RXANT_SHIFT;
- b43_phy_write(dev, B43_PHY_CCKBBANDCFG, tmp);
- break;
- case B43_PHYTYPE_N:
- b43_nphy_set_rxantenna(dev, antenna);
- break;
- default:
- B43_WARN_ON(1);
- }
-
- hf |= B43_HF_ANTDIVHELP;
- b43_hf_write(dev, hf);
-}
-
-/* Get the freq, as it has to be written to the device. */
-static inline u16 channel2freq_bg(u8 channel)
-{
- B43_WARN_ON(!(channel >= 1 && channel <= 14));
-
- return b43_radio_channel_codes_bg[channel - 1];
-}
-
-/* Get the freq, as it has to be written to the device. */
-static inline u16 channel2freq_a(u8 channel)
-{
- B43_WARN_ON(channel > 200);
-
- return (5000 + 5 * channel);
-}
-
-void b43_radio_lock(struct b43_wldev *dev)
-{
- u32 macctl;
-
- macctl = b43_read32(dev, B43_MMIO_MACCTL);
- B43_WARN_ON(macctl & B43_MACCTL_RADIOLOCK);
- macctl |= B43_MACCTL_RADIOLOCK;
- b43_write32(dev, B43_MMIO_MACCTL, macctl);
- /* Commit the write and wait for the device
- * to exit any radio register access. */
- b43_read32(dev, B43_MMIO_MACCTL);
- udelay(10);
-}
-
-void b43_radio_unlock(struct b43_wldev *dev)
-{
- u32 macctl;
-
- /* Commit any write */
- b43_read16(dev, B43_MMIO_PHY_VER);
- /* unlock */
- macctl = b43_read32(dev, B43_MMIO_MACCTL);
- B43_WARN_ON(!(macctl & B43_MACCTL_RADIOLOCK));
- macctl &= ~B43_MACCTL_RADIOLOCK;
- b43_write32(dev, B43_MMIO_MACCTL, macctl);
-}
-
-u16 b43_radio_read16(struct b43_wldev *dev, u16 offset)
-{
- struct b43_phy *phy = &dev->phy;
-
- /* Offset 1 is a 32-bit register. */
- B43_WARN_ON(offset == 1);
-
- switch (phy->type) {
- case B43_PHYTYPE_A:
- offset |= 0x40;
- break;
- case B43_PHYTYPE_B:
- if (phy->radio_ver == 0x2053) {
- if (offset < 0x70)
- offset += 0x80;
- else if (offset < 0x80)
- offset += 0x70;
- } else if (phy->radio_ver == 0x2050) {
- offset |= 0x80;
- } else
- B43_WARN_ON(1);
- break;
- case B43_PHYTYPE_G:
- offset |= 0x80;
- break;
- case B43_PHYTYPE_N:
- offset |= 0x100;
- break;
- case B43_PHYTYPE_LP:
- /* No adjustment required. */
- break;
- default:
- B43_WARN_ON(1);
- }
-
- b43_write16(dev, B43_MMIO_RADIO_CONTROL, offset);
- return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
-}
-
-void b43_radio_write16(struct b43_wldev *dev, u16 offset, u16 val)
-{
- /* Offset 1 is a 32-bit register. */
- B43_WARN_ON(offset == 1);
-
- b43_write16(dev, B43_MMIO_RADIO_CONTROL, offset);
- b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, val);
-}
-
-void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
-{
- b43_radio_write16(dev, offset,
- b43_radio_read16(dev, offset) & mask);
-}
-
-void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
-{
- b43_radio_write16(dev, offset,
- b43_radio_read16(dev, offset) | set);
-}
-
-void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
-{
- b43_radio_write16(dev, offset,
- (b43_radio_read16(dev, offset) & mask) | set);
-}
-
-static void b43_set_all_gains(struct b43_wldev *dev,
- s16 first, s16 second, s16 third)
-{
- struct b43_phy *phy = &dev->phy;
- u16 i;
- u16 start = 0x08, end = 0x18;
- u16 tmp;
- u16 table;
-
- if (phy->rev <= 1) {
- start = 0x10;
- end = 0x20;
- }
-
- table = B43_OFDMTAB_GAINX;
- if (phy->rev <= 1)
- table = B43_OFDMTAB_GAINX_R1;
- for (i = 0; i < 4; i++)
- b43_ofdmtab_write16(dev, table, i, first);
-
- for (i = start; i < end; i++)
- b43_ofdmtab_write16(dev, table, i, second);
-
- if (third != -1) {
- tmp = ((u16) third << 14) | ((u16) third << 6);
- b43_phy_write(dev, 0x04A0,
- (b43_phy_read(dev, 0x04A0) & 0xBFBF) | tmp);
- b43_phy_write(dev, 0x04A1,
- (b43_phy_read(dev, 0x04A1) & 0xBFBF) | tmp);
- b43_phy_write(dev, 0x04A2,
- (b43_phy_read(dev, 0x04A2) & 0xBFBF) | tmp);
- }
- b43_dummy_transmission(dev);
-}
-
-static void b43_set_original_gains(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- u16 i, tmp;
- u16 table;
- u16 start = 0x0008, end = 0x0018;
-
- if (phy->rev <= 1) {
- start = 0x0010;
- end = 0x0020;
- }
-
- table = B43_OFDMTAB_GAINX;
- if (phy->rev <= 1)
- table = B43_OFDMTAB_GAINX_R1;
- for (i = 0; i < 4; i++) {
- tmp = (i & 0xFFFC);
- tmp |= (i & 0x0001) << 1;
- tmp |= (i & 0x0002) >> 1;
-
- b43_ofdmtab_write16(dev, table, i, tmp);
- }
-
- for (i = start; i < end; i++)
- b43_ofdmtab_write16(dev, table, i, i - start);
-
- b43_phy_write(dev, 0x04A0,
- (b43_phy_read(dev, 0x04A0) & 0xBFBF) | 0x4040);
- b43_phy_write(dev, 0x04A1,
- (b43_phy_read(dev, 0x04A1) & 0xBFBF) | 0x4040);
- b43_phy_write(dev, 0x04A2,
- (b43_phy_read(dev, 0x04A2) & 0xBFBF) | 0x4000);
- b43_dummy_transmission(dev);
-}
-
-/* Synthetic PU workaround */
-static void b43_synth_pu_workaround(struct b43_wldev *dev, u8 channel)
-{
- struct b43_phy *phy = &dev->phy;
-
- might_sleep();
-
- if (phy->radio_ver != 0x2050 || phy->radio_rev >= 6) {
- /* We do not need the workaround. */
- return;
- }
-
- if (channel <= 10) {
- b43_write16(dev, B43_MMIO_CHANNEL,
- channel2freq_bg(channel + 4));
- } else {
- b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(1));
- }
- msleep(1);
- b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
-}
-
-u8 b43_radio_aci_detect(struct b43_wldev *dev, u8 channel)
-{
- struct b43_phy *phy = &dev->phy;
- u8 ret = 0;
- u16 saved, rssi, temp;
- int i, j = 0;
-
- saved = b43_phy_read(dev, 0x0403);
- b43_radio_selectchannel(dev, channel, 0);
- b43_phy_write(dev, 0x0403, (saved & 0xFFF8) | 5);
- if (phy->aci_hw_rssi)
- rssi = b43_phy_read(dev, 0x048A) & 0x3F;
- else
- rssi = saved & 0x3F;
- /* clamp temp to signed 5bit */
- if (rssi > 32)
- rssi -= 64;
- for (i = 0; i < 100; i++) {
- temp = (b43_phy_read(dev, 0x047F) >> 8) & 0x3F;
- if (temp > 32)
- temp -= 64;
- if (temp < rssi)
- j++;
- if (j >= 20)
- ret = 1;
- }
- b43_phy_write(dev, 0x0403, saved);
-
- return ret;
-}
-
-u8 b43_radio_aci_scan(struct b43_wldev * dev)
-{
- struct b43_phy *phy = &dev->phy;
- u8 ret[13];
- unsigned int channel = phy->channel;
- unsigned int i, j, start, end;
-
- if (!((phy->type == B43_PHYTYPE_G) && (phy->rev > 0)))
- return 0;
-
- b43_phy_lock(dev);
- b43_radio_lock(dev);
- b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC);
- b43_phy_write(dev, B43_PHY_G_CRS,
- b43_phy_read(dev, B43_PHY_G_CRS) & 0x7FFF);
- b43_set_all_gains(dev, 3, 8, 1);
-
- start = (channel - 5 > 0) ? channel - 5 : 1;
- end = (channel + 5 < 14) ? channel + 5 : 13;
-
- for (i = start; i <= end; i++) {
- if (abs(channel - i) > 2)
- ret[i - 1] = b43_radio_aci_detect(dev, i);
- }
- b43_radio_selectchannel(dev, channel, 0);
- b43_phy_write(dev, 0x0802,
- (b43_phy_read(dev, 0x0802) & 0xFFFC) | 0x0003);
- b43_phy_write(dev, 0x0403, b43_phy_read(dev, 0x0403) & 0xFFF8);
- b43_phy_write(dev, B43_PHY_G_CRS,
- b43_phy_read(dev, B43_PHY_G_CRS) | 0x8000);
- b43_set_original_gains(dev);
- for (i = 0; i < 13; i++) {
- if (!ret[i])
- continue;
- end = (i + 5 < 13) ? i + 5 : 13;
- for (j = i; j < end; j++)
- ret[j] = 1;
- }
- b43_radio_unlock(dev);
- b43_phy_unlock(dev);
-
- return ret[channel - 1];
-}
-
-/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
-void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val)
-{
- b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
- mmiowb();
- b43_phy_write(dev, B43_PHY_NRSSILT_DATA, (u16) val);
-}
-
-/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
-s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset)
-{
- u16 val;
-
- b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
- val = b43_phy_read(dev, B43_PHY_NRSSILT_DATA);
-
- return (s16) val;
-}
-
-/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
-void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val)
-{
- u16 i;
- s16 tmp;
-
- for (i = 0; i < 64; i++) {
- tmp = b43_nrssi_hw_read(dev, i);
- tmp -= val;
- tmp = clamp_val(tmp, -32, 31);
- b43_nrssi_hw_write(dev, i, tmp);
- }
-}
-
-/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
-void b43_nrssi_mem_update(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- s16 i, delta;
- s32 tmp;
-
- delta = 0x1F - phy->nrssi[0];
- for (i = 0; i < 64; i++) {
- tmp = (i - delta) * phy->nrssislope;
- tmp /= 0x10000;
- tmp += 0x3A;
- tmp = clamp_val(tmp, 0, 0x3F);
- phy->nrssi_lt[i] = tmp;
- }
-}
-
-static void b43_calc_nrssi_offset(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- u16 backup[20] = { 0 };
- s16 v47F;
- u16 i;
- u16 saved = 0xFFFF;
-
- backup[0] = b43_phy_read(dev, 0x0001);
- backup[1] = b43_phy_read(dev, 0x0811);
- backup[2] = b43_phy_read(dev, 0x0812);
- if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
- backup[3] = b43_phy_read(dev, 0x0814);
- backup[4] = b43_phy_read(dev, 0x0815);
- }
- backup[5] = b43_phy_read(dev, 0x005A);
- backup[6] = b43_phy_read(dev, 0x0059);
- backup[7] = b43_phy_read(dev, 0x0058);
- backup[8] = b43_phy_read(dev, 0x000A);
- backup[9] = b43_phy_read(dev, 0x0003);
- backup[10] = b43_radio_read16(dev, 0x007A);
- backup[11] = b43_radio_read16(dev, 0x0043);
-
- b43_phy_write(dev, 0x0429, b43_phy_read(dev, 0x0429) & 0x7FFF);
- b43_phy_write(dev, 0x0001,
- (b43_phy_read(dev, 0x0001) & 0x3FFF) | 0x4000);
- b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x000C);
- b43_phy_write(dev, 0x0812,
- (b43_phy_read(dev, 0x0812) & 0xFFF3) | 0x0004);
- b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & ~(0x1 | 0x2));
- if (phy->rev >= 6) {
- backup[12] = b43_phy_read(dev, 0x002E);
- backup[13] = b43_phy_read(dev, 0x002F);
- backup[14] = b43_phy_read(dev, 0x080F);
- backup[15] = b43_phy_read(dev, 0x0810);
- backup[16] = b43_phy_read(dev, 0x0801);
- backup[17] = b43_phy_read(dev, 0x0060);
- backup[18] = b43_phy_read(dev, 0x0014);
- backup[19] = b43_phy_read(dev, 0x0478);
-
- b43_phy_write(dev, 0x002E, 0);
- b43_phy_write(dev, 0x002F, 0);
- b43_phy_write(dev, 0x080F, 0);
- b43_phy_write(dev, 0x0810, 0);
- b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478) | 0x0100);
- b43_phy_write(dev, 0x0801, b43_phy_read(dev, 0x0801) | 0x0040);
- b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060) | 0x0040);
- b43_phy_write(dev, 0x0014, b43_phy_read(dev, 0x0014) | 0x0200);
- }
- b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0070);
- b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0080);
- udelay(30);
-
- v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
- if (v47F >= 0x20)
- v47F -= 0x40;
- if (v47F == 31) {
- for (i = 7; i >= 4; i--) {
- b43_radio_write16(dev, 0x007B, i);
- udelay(20);
- v47F =
- (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
- if (v47F >= 0x20)
- v47F -= 0x40;
- if (v47F < 31 && saved == 0xFFFF)
- saved = i;
- }
- if (saved == 0xFFFF)
- saved = 4;
- } else {
- b43_radio_write16(dev, 0x007A,
- b43_radio_read16(dev, 0x007A) & 0x007F);
- if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
- b43_phy_write(dev, 0x0814,
- b43_phy_read(dev, 0x0814) | 0x0001);
- b43_phy_write(dev, 0x0815,
- b43_phy_read(dev, 0x0815) & 0xFFFE);
- }
- b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x000C);
- b43_phy_write(dev, 0x0812, b43_phy_read(dev, 0x0812) | 0x000C);
- b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x0030);
- b43_phy_write(dev, 0x0812, b43_phy_read(dev, 0x0812) | 0x0030);
- b43_phy_write(dev, 0x005A, 0x0480);
- b43_phy_write(dev, 0x0059, 0x0810);
- b43_phy_write(dev, 0x0058, 0x000D);
- if (phy->rev == 0) {
- b43_phy_write(dev, 0x0003, 0x0122);
- } else {
- b43_phy_write(dev, 0x000A, b43_phy_read(dev, 0x000A)
- | 0x2000);
- }
- if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
- b43_phy_write(dev, 0x0814,
- b43_phy_read(dev, 0x0814) | 0x0004);
- b43_phy_write(dev, 0x0815,
- b43_phy_read(dev, 0x0815) & 0xFFFB);
- }
- b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003) & 0xFF9F)
- | 0x0040);
- b43_radio_write16(dev, 0x007A,
- b43_radio_read16(dev, 0x007A) | 0x000F);
- b43_set_all_gains(dev, 3, 0, 1);
- b43_radio_write16(dev, 0x0043, (b43_radio_read16(dev, 0x0043)
- & 0x00F0) | 0x000F);
- udelay(30);
- v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
- if (v47F >= 0x20)
- v47F -= 0x40;
- if (v47F == -32) {
- for (i = 0; i < 4; i++) {
- b43_radio_write16(dev, 0x007B, i);
- udelay(20);
- v47F =
- (s16) ((b43_phy_read(dev, 0x047F) >> 8) &
- 0x003F);
- if (v47F >= 0x20)
- v47F -= 0x40;
- if (v47F > -31 && saved == 0xFFFF)
- saved = i;
- }
- if (saved == 0xFFFF)
- saved = 3;
- } else
- saved = 0;
- }
- b43_radio_write16(dev, 0x007B, saved);
-
- if (phy->rev >= 6) {
- b43_phy_write(dev, 0x002E, backup[12]);
- b43_phy_write(dev, 0x002F, backup[13]);
- b43_phy_write(dev, 0x080F, backup[14]);
- b43_phy_write(dev, 0x0810, backup[15]);
- }
- if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
- b43_phy_write(dev, 0x0814, backup[3]);
- b43_phy_write(dev, 0x0815, backup[4]);
- }
- b43_phy_write(dev, 0x005A, backup[5]);
- b43_phy_write(dev, 0x0059, backup[6]);
- b43_phy_write(dev, 0x0058, backup[7]);
- b43_phy_write(dev, 0x000A, backup[8]);
- b43_phy_write(dev, 0x0003, backup[9]);
- b43_radio_write16(dev, 0x0043, backup[11]);
- b43_radio_write16(dev, 0x007A, backup[10]);
- b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x1 | 0x2);
- b43_phy_write(dev, 0x0429, b43_phy_read(dev, 0x0429) | 0x8000);
- b43_set_original_gains(dev);
- if (phy->rev >= 6) {
- b43_phy_write(dev, 0x0801, backup[16]);
- b43_phy_write(dev, 0x0060, backup[17]);
- b43_phy_write(dev, 0x0014, backup[18]);
- b43_phy_write(dev, 0x0478, backup[19]);
- }
- b43_phy_write(dev, 0x0001, backup[0]);
- b43_phy_write(dev, 0x0812, backup[2]);
- b43_phy_write(dev, 0x0811, backup[1]);
-}
-
-void b43_calc_nrssi_slope(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- u16 backup[18] = { 0 };
- u16 tmp;
- s16 nrssi0, nrssi1;
-
- switch (phy->type) {
- case B43_PHYTYPE_B:
- backup[0] = b43_radio_read16(dev, 0x007A);
- backup[1] = b43_radio_read16(dev, 0x0052);
- backup[2] = b43_radio_read16(dev, 0x0043);
- backup[3] = b43_phy_read(dev, 0x0030);
- backup[4] = b43_phy_read(dev, 0x0026);
- backup[5] = b43_phy_read(dev, 0x0015);
- backup[6] = b43_phy_read(dev, 0x002A);
- backup[7] = b43_phy_read(dev, 0x0020);
- backup[8] = b43_phy_read(dev, 0x005A);
- backup[9] = b43_phy_read(dev, 0x0059);
- backup[10] = b43_phy_read(dev, 0x0058);
- backup[11] = b43_read16(dev, 0x03E2);
- backup[12] = b43_read16(dev, 0x03E6);
- backup[13] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
-
- tmp = b43_radio_read16(dev, 0x007A);
- tmp &= (phy->rev >= 5) ? 0x007F : 0x000F;
- b43_radio_write16(dev, 0x007A, tmp);
- b43_phy_write(dev, 0x0030, 0x00FF);
- b43_write16(dev, 0x03EC, 0x7F7F);
- b43_phy_write(dev, 0x0026, 0x0000);
- b43_phy_write(dev, 0x0015, b43_phy_read(dev, 0x0015) | 0x0020);
- b43_phy_write(dev, 0x002A, 0x08A3);
- b43_radio_write16(dev, 0x007A,
- b43_radio_read16(dev, 0x007A) | 0x0080);
-
- nrssi0 = (s16) b43_phy_read(dev, 0x0027);
- b43_radio_write16(dev, 0x007A,
- b43_radio_read16(dev, 0x007A) & 0x007F);
- if (phy->rev >= 2) {
- b43_write16(dev, 0x03E6, 0x0040);
- } else if (phy->rev == 0) {
- b43_write16(dev, 0x03E6, 0x0122);
- } else {
- b43_write16(dev, B43_MMIO_CHANNEL_EXT,
- b43_read16(dev,
- B43_MMIO_CHANNEL_EXT) & 0x2000);
- }
- b43_phy_write(dev, 0x0020, 0x3F3F);
- b43_phy_write(dev, 0x0015, 0xF330);
- b43_radio_write16(dev, 0x005A, 0x0060);
- b43_radio_write16(dev, 0x0043,
- b43_radio_read16(dev, 0x0043) & 0x00F0);
- b43_phy_write(dev, 0x005A, 0x0480);
- b43_phy_write(dev, 0x0059, 0x0810);
- b43_phy_write(dev, 0x0058, 0x000D);
- udelay(20);
-
- nrssi1 = (s16) b43_phy_read(dev, 0x0027);
- b43_phy_write(dev, 0x0030, backup[3]);
- b43_radio_write16(dev, 0x007A, backup[0]);
- b43_write16(dev, 0x03E2, backup[11]);
- b43_phy_write(dev, 0x0026, backup[4]);
- b43_phy_write(dev, 0x0015, backup[5]);
- b43_phy_write(dev, 0x002A, backup[6]);
- b43_synth_pu_workaround(dev, phy->channel);
- if (phy->rev != 0)
- b43_write16(dev, 0x03F4, backup[13]);
-
- b43_phy_write(dev, 0x0020, backup[7]);
- b43_phy_write(dev, 0x005A, backup[8]);
- b43_phy_write(dev, 0x0059, backup[9]);
- b43_phy_write(dev, 0x0058, backup[10]);
- b43_radio_write16(dev, 0x0052, backup[1]);
- b43_radio_write16(dev, 0x0043, backup[2]);
-
- if (nrssi0 == nrssi1)
- phy->nrssislope = 0x00010000;
- else
- phy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
-
- if (nrssi0 <= -4) {
- phy->nrssi[0] = nrssi0;
- phy->nrssi[1] = nrssi1;
- }
- break;
- case B43_PHYTYPE_G:
- if (phy->radio_rev >= 9)
- return;
- if (phy->radio_rev == 8)
- b43_calc_nrssi_offset(dev);
-
- b43_phy_write(dev, B43_PHY_G_CRS,
- b43_phy_read(dev, B43_PHY_G_CRS) & 0x7FFF);
- b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC);
- backup[7] = b43_read16(dev, 0x03E2);
- b43_write16(dev, 0x03E2, b43_read16(dev, 0x03E2) | 0x8000);
- backup[0] = b43_radio_read16(dev, 0x007A);
- backup[1] = b43_radio_read16(dev, 0x0052);
- backup[2] = b43_radio_read16(dev, 0x0043);
- backup[3] = b43_phy_read(dev, 0x0015);
- backup[4] = b43_phy_read(dev, 0x005A);
- backup[5] = b43_phy_read(dev, 0x0059);
- backup[6] = b43_phy_read(dev, 0x0058);
- backup[8] = b43_read16(dev, 0x03E6);
- backup[9] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
- if (phy->rev >= 3) {
- backup[10] = b43_phy_read(dev, 0x002E);
- backup[11] = b43_phy_read(dev, 0x002F);
- backup[12] = b43_phy_read(dev, 0x080F);
- backup[13] = b43_phy_read(dev, B43_PHY_G_LO_CONTROL);
- backup[14] = b43_phy_read(dev, 0x0801);
- backup[15] = b43_phy_read(dev, 0x0060);
- backup[16] = b43_phy_read(dev, 0x0014);
- backup[17] = b43_phy_read(dev, 0x0478);
- b43_phy_write(dev, 0x002E, 0);
- b43_phy_write(dev, B43_PHY_G_LO_CONTROL, 0);
- switch (phy->rev) {
- case 4:
- case 6:
- case 7:
- b43_phy_write(dev, 0x0478,
- b43_phy_read(dev, 0x0478)
- | 0x0100);
- b43_phy_write(dev, 0x0801,
- b43_phy_read(dev, 0x0801)
- | 0x0040);
- break;
- case 3:
- case 5:
- b43_phy_write(dev, 0x0801,
- b43_phy_read(dev, 0x0801)
- & 0xFFBF);
- break;
- }
- b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060)
- | 0x0040);
- b43_phy_write(dev, 0x0014, b43_phy_read(dev, 0x0014)
- | 0x0200);
- }
- b43_radio_write16(dev, 0x007A,
- b43_radio_read16(dev, 0x007A) | 0x0070);
- b43_set_all_gains(dev, 0, 8, 0);
- b43_radio_write16(dev, 0x007A,
- b43_radio_read16(dev, 0x007A) & 0x00F7);
- if (phy->rev >= 2) {
- b43_phy_write(dev, 0x0811,
- (b43_phy_read(dev, 0x0811) & 0xFFCF) |
- 0x0030);
- b43_phy_write(dev, 0x0812,
- (b43_phy_read(dev, 0x0812) & 0xFFCF) |
- 0x0010);
- }
- b43_radio_write16(dev, 0x007A,
- b43_radio_read16(dev, 0x007A) | 0x0080);
- udelay(20);
-
- nrssi0 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
- if (nrssi0 >= 0x0020)
- nrssi0 -= 0x0040;
-
- b43_radio_write16(dev, 0x007A,
- b43_radio_read16(dev, 0x007A) & 0x007F);
- if (phy->rev >= 2) {
- b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003)
- & 0xFF9F) | 0x0040);
- }
-
- b43_write16(dev, B43_MMIO_CHANNEL_EXT,
- b43_read16(dev, B43_MMIO_CHANNEL_EXT)
- | 0x2000);
- b43_radio_write16(dev, 0x007A,
- b43_radio_read16(dev, 0x007A) | 0x000F);
- b43_phy_write(dev, 0x0015, 0xF330);
- if (phy->rev >= 2) {
- b43_phy_write(dev, 0x0812,
- (b43_phy_read(dev, 0x0812) & 0xFFCF) |
- 0x0020);
- b43_phy_write(dev, 0x0811,
- (b43_phy_read(dev, 0x0811) & 0xFFCF) |
- 0x0020);
- }
-
- b43_set_all_gains(dev, 3, 0, 1);
- if (phy->radio_rev == 8) {
- b43_radio_write16(dev, 0x0043, 0x001F);
- } else {
- tmp = b43_radio_read16(dev, 0x0052) & 0xFF0F;
- b43_radio_write16(dev, 0x0052, tmp | 0x0060);
- tmp = b43_radio_read16(dev, 0x0043) & 0xFFF0;
- b43_radio_write16(dev, 0x0043, tmp | 0x0009);
- }
- b43_phy_write(dev, 0x005A, 0x0480);
- b43_phy_write(dev, 0x0059, 0x0810);
- b43_phy_write(dev, 0x0058, 0x000D);
- udelay(20);
- nrssi1 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
- if (nrssi1 >= 0x0020)
- nrssi1 -= 0x0040;
- if (nrssi0 == nrssi1)
- phy->nrssislope = 0x00010000;
- else
- phy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
- if (nrssi0 >= -4) {
- phy->nrssi[0] = nrssi1;
- phy->nrssi[1] = nrssi0;
- }
- if (phy->rev >= 3) {
- b43_phy_write(dev, 0x002E, backup[10]);
- b43_phy_write(dev, 0x002F, backup[11]);
- b43_phy_write(dev, 0x080F, backup[12]);
- b43_phy_write(dev, B43_PHY_G_LO_CONTROL, backup[13]);
- }
- if (phy->rev >= 2) {
- b43_phy_write(dev, 0x0812,
- b43_phy_read(dev, 0x0812) & 0xFFCF);
- b43_phy_write(dev, 0x0811,
- b43_phy_read(dev, 0x0811) & 0xFFCF);
- }
-
- b43_radio_write16(dev, 0x007A, backup[0]);
- b43_radio_write16(dev, 0x0052, backup[1]);
- b43_radio_write16(dev, 0x0043, backup[2]);
- b43_write16(dev, 0x03E2, backup[7]);
- b43_write16(dev, 0x03E6, backup[8]);
- b43_write16(dev, B43_MMIO_CHANNEL_EXT, backup[9]);
- b43_phy_write(dev, 0x0015, backup[3]);
- b43_phy_write(dev, 0x005A, backup[4]);
- b43_phy_write(dev, 0x0059, backup[5]);
- b43_phy_write(dev, 0x0058, backup[6]);
- b43_synth_pu_workaround(dev, phy->channel);
- b43_phy_write(dev, 0x0802,
- b43_phy_read(dev, 0x0802) | (0x0001 | 0x0002));
- b43_set_original_gains(dev);
- b43_phy_write(dev, B43_PHY_G_CRS,
- b43_phy_read(dev, B43_PHY_G_CRS) | 0x8000);
- if (phy->rev >= 3) {
- b43_phy_write(dev, 0x0801, backup[14]);
- b43_phy_write(dev, 0x0060, backup[15]);
- b43_phy_write(dev, 0x0014, backup[16]);
- b43_phy_write(dev, 0x0478, backup[17]);
- }
- b43_nrssi_mem_update(dev);
- b43_calc_nrssi_threshold(dev);
- break;
- default:
- B43_WARN_ON(1);
- }
-}
-
-void b43_calc_nrssi_threshold(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- s32 threshold;
- s32 a, b;
- s16 tmp16;
- u16 tmp_u16;
-
- switch (phy->type) {
- case B43_PHYTYPE_B:{
- if (phy->radio_ver != 0x2050)
- return;
- if (!
- (dev->dev->bus->sprom.
- boardflags_lo & B43_BFL_RSSI))
- return;
-
- if (phy->radio_rev >= 6) {
- threshold =
- (phy->nrssi[1] - phy->nrssi[0]) * 32;
- threshold += 20 * (phy->nrssi[0] + 1);
- threshold /= 40;
- } else
- threshold = phy->nrssi[1] - 5;
-
- threshold = clamp_val(threshold, 0, 0x3E);
- b43_phy_read(dev, 0x0020); /* dummy read */
- b43_phy_write(dev, 0x0020,
- (((u16) threshold) << 8) | 0x001C);
-
- if (phy->radio_rev >= 6) {
- b43_phy_write(dev, 0x0087, 0x0E0D);
- b43_phy_write(dev, 0x0086, 0x0C0B);
- b43_phy_write(dev, 0x0085, 0x0A09);
- b43_phy_write(dev, 0x0084, 0x0808);
- b43_phy_write(dev, 0x0083, 0x0808);
- b43_phy_write(dev, 0x0082, 0x0604);
- b43_phy_write(dev, 0x0081, 0x0302);
- b43_phy_write(dev, 0x0080, 0x0100);
- }
- break;
- }
- case B43_PHYTYPE_G:
- if (!phy->gmode ||
- !(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI)) {
- tmp16 = b43_nrssi_hw_read(dev, 0x20);
- if (tmp16 >= 0x20)
- tmp16 -= 0x40;
- if (tmp16 < 3) {
- b43_phy_write(dev, 0x048A,
- (b43_phy_read(dev, 0x048A)
- & 0xF000) | 0x09EB);
- } else {
- b43_phy_write(dev, 0x048A,
- (b43_phy_read(dev, 0x048A)
- & 0xF000) | 0x0AED);
- }
- } else {
- if (phy->interfmode == B43_INTERFMODE_NONWLAN) {
- a = 0xE;
- b = 0xA;
- } else if (!phy->aci_wlan_automatic && phy->aci_enable) {
- a = 0x13;
- b = 0x12;
- } else {
- a = 0xE;
- b = 0x11;
- }
-
- a = a * (phy->nrssi[1] - phy->nrssi[0]);
- a += (phy->nrssi[0] << 6);
- if (a < 32)
- a += 31;
- else
- a += 32;
- a = a >> 6;
- a = clamp_val(a, -31, 31);
-
- b = b * (phy->nrssi[1] - phy->nrssi[0]);
- b += (phy->nrssi[0] << 6);
- if (b < 32)
- b += 31;
- else
- b += 32;
- b = b >> 6;
- b = clamp_val(b, -31, 31);
-
- tmp_u16 = b43_phy_read(dev, 0x048A) & 0xF000;
- tmp_u16 |= ((u32) b & 0x0000003F);
- tmp_u16 |= (((u32) a & 0x0000003F) << 6);
- b43_phy_write(dev, 0x048A, tmp_u16);
- }
- break;
- default:
- B43_WARN_ON(1);
- }
-}
-
-/* Stack implementation to save/restore values from the
- * interference mitigation code.
- * It is save to restore values in random order.
- */
-static void _stack_save(u32 * _stackptr, size_t * stackidx,
- u8 id, u16 offset, u16 value)
-{
- u32 *stackptr = &(_stackptr[*stackidx]);
-
- B43_WARN_ON(offset & 0xF000);
- B43_WARN_ON(id & 0xF0);
- *stackptr = offset;
- *stackptr |= ((u32) id) << 12;
- *stackptr |= ((u32) value) << 16;
- (*stackidx)++;
- B43_WARN_ON(*stackidx >= B43_INTERFSTACK_SIZE);
-}
-
-static u16 _stack_restore(u32 * stackptr, u8 id, u16 offset)
-{
- size_t i;
-
- B43_WARN_ON(offset & 0xF000);
- B43_WARN_ON(id & 0xF0);
- for (i = 0; i < B43_INTERFSTACK_SIZE; i++, stackptr++) {
- if ((*stackptr & 0x00000FFF) != offset)
- continue;
- if (((*stackptr & 0x0000F000) >> 12) != id)
- continue;
- return ((*stackptr & 0xFFFF0000) >> 16);
- }
- B43_WARN_ON(1);
-
- return 0;
-}
-
-#define phy_stacksave(offset) \
- do { \
- _stack_save(stack, &stackidx, 0x1, (offset), \
- b43_phy_read(dev, (offset))); \
- } while (0)
-#define phy_stackrestore(offset) \
- do { \
- b43_phy_write(dev, (offset), \
- _stack_restore(stack, 0x1, \
- (offset))); \
- } while (0)
-#define radio_stacksave(offset) \
- do { \
- _stack_save(stack, &stackidx, 0x2, (offset), \
- b43_radio_read16(dev, (offset))); \
- } while (0)
-#define radio_stackrestore(offset) \
- do { \
- b43_radio_write16(dev, (offset), \
- _stack_restore(stack, 0x2, \
- (offset))); \
- } while (0)
-#define ofdmtab_stacksave(table, offset) \
- do { \
- _stack_save(stack, &stackidx, 0x3, (offset)|(table), \
- b43_ofdmtab_read16(dev, (table), (offset))); \
- } while (0)
-#define ofdmtab_stackrestore(table, offset) \
- do { \
- b43_ofdmtab_write16(dev, (table), (offset), \
- _stack_restore(stack, 0x3, \
- (offset)|(table))); \
- } while (0)
-
-static void
-b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
-{
- struct b43_phy *phy = &dev->phy;
- u16 tmp, flipped;
- size_t stackidx = 0;
- u32 *stack = phy->interfstack;
-
- switch (mode) {
- case B43_INTERFMODE_NONWLAN:
- if (phy->rev != 1) {
- b43_phy_write(dev, 0x042B,
- b43_phy_read(dev, 0x042B) | 0x0800);
- b43_phy_write(dev, B43_PHY_G_CRS,
- b43_phy_read(dev,
- B43_PHY_G_CRS) & ~0x4000);
- break;
- }
- radio_stacksave(0x0078);
- tmp = (b43_radio_read16(dev, 0x0078) & 0x001E);
- B43_WARN_ON(tmp > 15);
- flipped = bitrev4(tmp);
- if (flipped < 10 && flipped >= 8)
- flipped = 7;
- else if (flipped >= 10)
- flipped -= 3;
- flipped = (bitrev4(flipped) << 1) | 0x0020;
- b43_radio_write16(dev, 0x0078, flipped);
-
- b43_calc_nrssi_threshold(dev);
-
- phy_stacksave(0x0406);
- b43_phy_write(dev, 0x0406, 0x7E28);
-
- b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x0800);
- b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
- b43_phy_read(dev,
- B43_PHY_RADIO_BITFIELD) | 0x1000);
-
- phy_stacksave(0x04A0);
- b43_phy_write(dev, 0x04A0,
- (b43_phy_read(dev, 0x04A0) & 0xC0C0) | 0x0008);
- phy_stacksave(0x04A1);
- b43_phy_write(dev, 0x04A1,
- (b43_phy_read(dev, 0x04A1) & 0xC0C0) | 0x0605);
- phy_stacksave(0x04A2);
- b43_phy_write(dev, 0x04A2,
- (b43_phy_read(dev, 0x04A2) & 0xC0C0) | 0x0204);
- phy_stacksave(0x04A8);
- b43_phy_write(dev, 0x04A8,
- (b43_phy_read(dev, 0x04A8) & 0xC0C0) | 0x0803);
- phy_stacksave(0x04AB);
- b43_phy_write(dev, 0x04AB,
- (b43_phy_read(dev, 0x04AB) & 0xC0C0) | 0x0605);
-
- phy_stacksave(0x04A7);
- b43_phy_write(dev, 0x04A7, 0x0002);
- phy_stacksave(0x04A3);
- b43_phy_write(dev, 0x04A3, 0x287A);
- phy_stacksave(0x04A9);
- b43_phy_write(dev, 0x04A9, 0x2027);
- phy_stacksave(0x0493);
- b43_phy_write(dev, 0x0493, 0x32F5);
- phy_stacksave(0x04AA);
- b43_phy_write(dev, 0x04AA, 0x2027);
- phy_stacksave(0x04AC);
- b43_phy_write(dev, 0x04AC, 0x32F5);
- break;
- case B43_INTERFMODE_MANUALWLAN:
- if (b43_phy_read(dev, 0x0033) & 0x0800)
- break;
-
- phy->aci_enable = 1;
-
- phy_stacksave(B43_PHY_RADIO_BITFIELD);
- phy_stacksave(B43_PHY_G_CRS);
- if (phy->rev < 2) {
- phy_stacksave(0x0406);
- } else {
- phy_stacksave(0x04C0);
- phy_stacksave(0x04C1);
- }
- phy_stacksave(0x0033);
- phy_stacksave(0x04A7);
- phy_stacksave(0x04A3);
- phy_stacksave(0x04A9);
- phy_stacksave(0x04AA);
- phy_stacksave(0x04AC);
- phy_stacksave(0x0493);
- phy_stacksave(0x04A1);
- phy_stacksave(0x04A0);
- phy_stacksave(0x04A2);
- phy_stacksave(0x048A);
- phy_stacksave(0x04A8);
- phy_stacksave(0x04AB);
- if (phy->rev == 2) {
- phy_stacksave(0x04AD);
- phy_stacksave(0x04AE);
- } else if (phy->rev >= 3) {
- phy_stacksave(0x04AD);
- phy_stacksave(0x0415);
- phy_stacksave(0x0416);
- phy_stacksave(0x0417);
- ofdmtab_stacksave(0x1A00, 0x2);
- ofdmtab_stacksave(0x1A00, 0x3);
- }
- phy_stacksave(0x042B);
- phy_stacksave(0x048C);
-
- b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
- b43_phy_read(dev, B43_PHY_RADIO_BITFIELD)
- & ~0x1000);
- b43_phy_write(dev, B43_PHY_G_CRS,
- (b43_phy_read(dev, B43_PHY_G_CRS)
- & 0xFFFC) | 0x0002);
-
- b43_phy_write(dev, 0x0033, 0x0800);
- b43_phy_write(dev, 0x04A3, 0x2027);
- b43_phy_write(dev, 0x04A9, 0x1CA8);
- b43_phy_write(dev, 0x0493, 0x287A);
- b43_phy_write(dev, 0x04AA, 0x1CA8);
- b43_phy_write(dev, 0x04AC, 0x287A);
-
- b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
- & 0xFFC0) | 0x001A);
- b43_phy_write(dev, 0x04A7, 0x000D);
-
- if (phy->rev < 2) {
- b43_phy_write(dev, 0x0406, 0xFF0D);
- } else if (phy->rev == 2) {
- b43_phy_write(dev, 0x04C0, 0xFFFF);
- b43_phy_write(dev, 0x04C1, 0x00A9);
- } else {
- b43_phy_write(dev, 0x04C0, 0x00C1);
- b43_phy_write(dev, 0x04C1, 0x0059);
- }
-
- b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
- & 0xC0FF) | 0x1800);
- b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
- & 0xFFC0) | 0x0015);
- b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
- & 0xCFFF) | 0x1000);
- b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
- & 0xF0FF) | 0x0A00);
- b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
- & 0xCFFF) | 0x1000);
- b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
- & 0xF0FF) | 0x0800);
- b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
- & 0xFFCF) | 0x0010);
- b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
- & 0xFFF0) | 0x0005);
- b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
- & 0xFFCF) | 0x0010);
- b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
- & 0xFFF0) | 0x0006);
- b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
- & 0xF0FF) | 0x0800);
- b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
- & 0xF0FF) | 0x0500);
- b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
- & 0xFFF0) | 0x000B);
-
- if (phy->rev >= 3) {
- b43_phy_write(dev, 0x048A, b43_phy_read(dev, 0x048A)
- & ~0x8000);
- b43_phy_write(dev, 0x0415, (b43_phy_read(dev, 0x0415)
- & 0x8000) | 0x36D8);
- b43_phy_write(dev, 0x0416, (b43_phy_read(dev, 0x0416)
- & 0x8000) | 0x36D8);
- b43_phy_write(dev, 0x0417, (b43_phy_read(dev, 0x0417)
- & 0xFE00) | 0x016D);
- } else {
- b43_phy_write(dev, 0x048A, b43_phy_read(dev, 0x048A)
- | 0x1000);
- b43_phy_write(dev, 0x048A, (b43_phy_read(dev, 0x048A)
- & 0x9FFF) | 0x2000);
- b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ACIW);
- }
- if (phy->rev >= 2) {
- b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B)
- | 0x0800);
- }
- b43_phy_write(dev, 0x048C, (b43_phy_read(dev, 0x048C)
- & 0xF0FF) | 0x0200);
- if (phy->rev == 2) {
- b43_phy_write(dev, 0x04AE, (b43_phy_read(dev, 0x04AE)
- & 0xFF00) | 0x007F);
- b43_phy_write(dev, 0x04AD, (b43_phy_read(dev, 0x04AD)
- & 0x00FF) | 0x1300);
- } else if (phy->rev >= 6) {
- b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F);
- b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F);
- b43_phy_write(dev, 0x04AD, b43_phy_read(dev, 0x04AD)
- & 0x00FF);
- }
- b43_calc_nrssi_slope(dev);
- break;
- default:
- B43_WARN_ON(1);
- }
-}
-
-static void
-b43_radio_interference_mitigation_disable(struct b43_wldev *dev, int mode)
-{
- struct b43_phy *phy = &dev->phy;
- u32 *stack = phy->interfstack;
-
- switch (mode) {
- case B43_INTERFMODE_NONWLAN:
- if (phy->rev != 1) {
- b43_phy_write(dev, 0x042B,
- b43_phy_read(dev, 0x042B) & ~0x0800);
- b43_phy_write(dev, B43_PHY_G_CRS,
- b43_phy_read(dev,
- B43_PHY_G_CRS) | 0x4000);
- break;
- }
- radio_stackrestore(0x0078);
- b43_calc_nrssi_threshold(dev);
- phy_stackrestore(0x0406);
- b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) & ~0x0800);
- if (!dev->bad_frames_preempt) {
- b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
- b43_phy_read(dev, B43_PHY_RADIO_BITFIELD)
- & ~(1 << 11));
- }
- b43_phy_write(dev, B43_PHY_G_CRS,
- b43_phy_read(dev, B43_PHY_G_CRS) | 0x4000);
- phy_stackrestore(0x04A0);
- phy_stackrestore(0x04A1);
- phy_stackrestore(0x04A2);
- phy_stackrestore(0x04A8);
- phy_stackrestore(0x04AB);
- phy_stackrestore(0x04A7);
- phy_stackrestore(0x04A3);
- phy_stackrestore(0x04A9);
- phy_stackrestore(0x0493);
- phy_stackrestore(0x04AA);
- phy_stackrestore(0x04AC);
- break;
- case B43_INTERFMODE_MANUALWLAN:
- if (!(b43_phy_read(dev, 0x0033) & 0x0800))
- break;
-
- phy->aci_enable = 0;
-
- phy_stackrestore(B43_PHY_RADIO_BITFIELD);
- phy_stackrestore(B43_PHY_G_CRS);
- phy_stackrestore(0x0033);
- phy_stackrestore(0x04A3);
- phy_stackrestore(0x04A9);
- phy_stackrestore(0x0493);
- phy_stackrestore(0x04AA);
- phy_stackrestore(0x04AC);
- phy_stackrestore(0x04A0);
- phy_stackrestore(0x04A7);
- if (phy->rev >= 2) {
- phy_stackrestore(0x04C0);
- phy_stackrestore(0x04C1);
- } else
- phy_stackrestore(0x0406);
- phy_stackrestore(0x04A1);
- phy_stackrestore(0x04AB);
- phy_stackrestore(0x04A8);
- if (phy->rev == 2) {
- phy_stackrestore(0x04AD);
- phy_stackrestore(0x04AE);
- } else if (phy->rev >= 3) {
- phy_stackrestore(0x04AD);
- phy_stackrestore(0x0415);
- phy_stackrestore(0x0416);
- phy_stackrestore(0x0417);
- ofdmtab_stackrestore(0x1A00, 0x2);
- ofdmtab_stackrestore(0x1A00, 0x3);
- }
- phy_stackrestore(0x04A2);
- phy_stackrestore(0x048A);
- phy_stackrestore(0x042B);
- phy_stackrestore(0x048C);
- b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ACIW);
- b43_calc_nrssi_slope(dev);
- break;
- default:
- B43_WARN_ON(1);
- }
-}
-
-#undef phy_stacksave
-#undef phy_stackrestore
-#undef radio_stacksave
-#undef radio_stackrestore
-#undef ofdmtab_stacksave
-#undef ofdmtab_stackrestore
-
-int b43_radio_set_interference_mitigation(struct b43_wldev *dev, int mode)
-{
- struct b43_phy *phy = &dev->phy;
- int currentmode;
-
- if ((phy->type != B43_PHYTYPE_G) || (phy->rev == 0) || (!phy->gmode))
- return -ENODEV;
-
- phy->aci_wlan_automatic = 0;
- switch (mode) {
- case B43_INTERFMODE_AUTOWLAN:
- phy->aci_wlan_automatic = 1;
- if (phy->aci_enable)
- mode = B43_INTERFMODE_MANUALWLAN;
- else
- mode = B43_INTERFMODE_NONE;
- break;
- case B43_INTERFMODE_NONE:
- case B43_INTERFMODE_NONWLAN:
- case B43_INTERFMODE_MANUALWLAN:
- break;
- default:
- return -EINVAL;
- }
-
- currentmode = phy->interfmode;
- if (currentmode == mode)
- return 0;
- if (currentmode != B43_INTERFMODE_NONE)
- b43_radio_interference_mitigation_disable(dev, currentmode);
-
- if (mode == B43_INTERFMODE_NONE) {
- phy->aci_enable = 0;
- phy->aci_hw_rssi = 0;
- } else
- b43_radio_interference_mitigation_enable(dev, mode);
- phy->interfmode = mode;
-
- return 0;
-}
-
-static u16 b43_radio_core_calibration_value(struct b43_wldev *dev)
-{
- u16 reg, index, ret;
-
- static const u8 rcc_table[] = {
- 0x02, 0x03, 0x01, 0x0F,
- 0x06, 0x07, 0x05, 0x0F,
- 0x0A, 0x0B, 0x09, 0x0F,
- 0x0E, 0x0F, 0x0D, 0x0F,
- };
-
- reg = b43_radio_read16(dev, 0x60);
- index = (reg & 0x001E) >> 1;
- ret = rcc_table[index] << 1;
- ret |= (reg & 0x0001);
- ret |= 0x0020;
-
- return ret;
-}
-
-#define LPD(L, P, D) (((L) << 2) | ((P) << 1) | ((D) << 0))
-static u16 radio2050_rfover_val(struct b43_wldev *dev,
- u16 phy_register, unsigned int lpd)
-{
- struct b43_phy *phy = &dev->phy;
- struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
-
- if (!phy->gmode)
- return 0;
-
- if (has_loopback_gain(phy)) {
- int max_lb_gain = phy->max_lb_gain;
- u16 extlna;
- u16 i;
-
- if (phy->radio_rev == 8)
- max_lb_gain += 0x3E;
- else
- max_lb_gain += 0x26;
- if (max_lb_gain >= 0x46) {
- extlna = 0x3000;
- max_lb_gain -= 0x46;
- } else if (max_lb_gain >= 0x3A) {
- extlna = 0x1000;
- max_lb_gain -= 0x3A;
- } else if (max_lb_gain >= 0x2E) {
- extlna = 0x2000;
- max_lb_gain -= 0x2E;
- } else {
- extlna = 0;
- max_lb_gain -= 0x10;
- }
-
- for (i = 0; i < 16; i++) {
- max_lb_gain -= (i * 6);
- if (max_lb_gain < 6)
- break;
- }
-
- if ((phy->rev < 7) ||
- !(sprom->boardflags_lo & B43_BFL_EXTLNA)) {
- if (phy_register == B43_PHY_RFOVER) {
- return 0x1B3;
- } else if (phy_register == B43_PHY_RFOVERVAL) {
- extlna |= (i << 8);
- switch (lpd) {
- case LPD(0, 1, 1):
- return 0x0F92;
- case LPD(0, 0, 1):
- case LPD(1, 0, 1):
- return (0x0092 | extlna);
- case LPD(1, 0, 0):
- return (0x0093 | extlna);
- }
- B43_WARN_ON(1);
- }
- B43_WARN_ON(1);
- } else {
- if (phy_register == B43_PHY_RFOVER) {
- return 0x9B3;
- } else if (phy_register == B43_PHY_RFOVERVAL) {
- if (extlna)
- extlna |= 0x8000;
- extlna |= (i << 8);
- switch (lpd) {
- case LPD(0, 1, 1):
- return 0x8F92;
- case LPD(0, 0, 1):
- return (0x8092 | extlna);
- case LPD(1, 0, 1):
- return (0x2092 | extlna);
- case LPD(1, 0, 0):
- return (0x2093 | extlna);
- }
- B43_WARN_ON(1);
- }
- B43_WARN_ON(1);
- }
- } else {
- if ((phy->rev < 7) ||
- !(sprom->boardflags_lo & B43_BFL_EXTLNA)) {
- if (phy_register == B43_PHY_RFOVER) {
- return 0x1B3;
- } else if (phy_register == B43_PHY_RFOVERVAL) {
- switch (lpd) {
- case LPD(0, 1, 1):
- return 0x0FB2;
- case LPD(0, 0, 1):
- return 0x00B2;
- case LPD(1, 0, 1):
- return 0x30B2;
- case LPD(1, 0, 0):
- return 0x30B3;
- }
- B43_WARN_ON(1);
- }
- B43_WARN_ON(1);
- } else {
- if (phy_register == B43_PHY_RFOVER) {
- return 0x9B3;
- } else if (phy_register == B43_PHY_RFOVERVAL) {
- switch (lpd) {
- case LPD(0, 1, 1):
- return 0x8FB2;
- case LPD(0, 0, 1):
- return 0x80B2;
- case LPD(1, 0, 1):
- return 0x20B2;
- case LPD(1, 0, 0):
- return 0x20B3;
- }
- B43_WARN_ON(1);
- }
- B43_WARN_ON(1);
- }
- }
- return 0;
-}
-
-struct init2050_saved_values {
- /* Core registers */
- u16 reg_3EC;
- u16 reg_3E6;
- u16 reg_3F4;
- /* Radio registers */
- u16 radio_43;
- u16 radio_51;
- u16 radio_52;
- /* PHY registers */
- u16 phy_pgactl;
- u16 phy_cck_5A;
- u16 phy_cck_59;
- u16 phy_cck_58;
- u16 phy_cck_30;
- u16 phy_rfover;
- u16 phy_rfoverval;
- u16 phy_analogover;
- u16 phy_analogoverval;
- u16 phy_crs0;
- u16 phy_classctl;
- u16 phy_lo_mask;
- u16 phy_lo_ctl;
- u16 phy_syncctl;
-};
-
-u16 b43_radio_init2050(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- struct init2050_saved_values sav;
- u16 rcc;
- u16 radio78;
- u16 ret;
- u16 i, j;
- u32 tmp1 = 0, tmp2 = 0;
-
- memset(&sav, 0, sizeof(sav)); /* get rid of "may be used uninitialized..." */
-
- sav.radio_43 = b43_radio_read16(dev, 0x43);
- sav.radio_51 = b43_radio_read16(dev, 0x51);
- sav.radio_52 = b43_radio_read16(dev, 0x52);
- sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL);
- sav.phy_cck_5A = b43_phy_read(dev, B43_PHY_CCK(0x5A));
- sav.phy_cck_59 = b43_phy_read(dev, B43_PHY_CCK(0x59));
- sav.phy_cck_58 = b43_phy_read(dev, B43_PHY_CCK(0x58));
-
- if (phy->type == B43_PHYTYPE_B) {
- sav.phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30));
- sav.reg_3EC = b43_read16(dev, 0x3EC);
-
- b43_phy_write(dev, B43_PHY_CCK(0x30), 0xFF);
- b43_write16(dev, 0x3EC, 0x3F3F);
- } else if (phy->gmode || phy->rev >= 2) {
- sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER);
- sav.phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
- sav.phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER);
- sav.phy_analogoverval =
- b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
- sav.phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
- sav.phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
-
- b43_phy_write(dev, B43_PHY_ANALOGOVER,
- b43_phy_read(dev, B43_PHY_ANALOGOVER)
- | 0x0003);
- b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
- b43_phy_read(dev, B43_PHY_ANALOGOVERVAL)
- & 0xFFFC);
- b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
- & 0x7FFF);
- b43_phy_write(dev, B43_PHY_CLASSCTL,
- b43_phy_read(dev, B43_PHY_CLASSCTL)
- & 0xFFFC);
- if (has_loopback_gain(phy)) {
- sav.phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK);
- sav.phy_lo_ctl = b43_phy_read(dev, B43_PHY_LO_CTL);
-
- if (phy->rev >= 3)
- b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
- else
- b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
- b43_phy_write(dev, B43_PHY_LO_CTL, 0);
- }
-
- b43_phy_write(dev, B43_PHY_RFOVERVAL,
- radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
- LPD(0, 1, 1)));
- b43_phy_write(dev, B43_PHY_RFOVER,
- radio2050_rfover_val(dev, B43_PHY_RFOVER, 0));
- }
- b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) | 0x8000);
-
- sav.phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL);
- b43_phy_write(dev, B43_PHY_SYNCCTL, b43_phy_read(dev, B43_PHY_SYNCCTL)
- & 0xFF7F);
- sav.reg_3E6 = b43_read16(dev, 0x3E6);
- sav.reg_3F4 = b43_read16(dev, 0x3F4);
-
- if (phy->analog == 0) {
- b43_write16(dev, 0x03E6, 0x0122);
- } else {
- if (phy->analog >= 2) {
- b43_phy_write(dev, B43_PHY_CCK(0x03),
- (b43_phy_read(dev, B43_PHY_CCK(0x03))
- & 0xFFBF) | 0x40);
- }
- b43_write16(dev, B43_MMIO_CHANNEL_EXT,
- (b43_read16(dev, B43_MMIO_CHANNEL_EXT) | 0x2000));
- }
-
- rcc = b43_radio_core_calibration_value(dev);
-
- if (phy->type == B43_PHYTYPE_B)
- b43_radio_write16(dev, 0x78, 0x26);
- if (phy->gmode || phy->rev >= 2) {
- b43_phy_write(dev, B43_PHY_RFOVERVAL,
- radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
- LPD(0, 1, 1)));
- }
- b43_phy_write(dev, B43_PHY_PGACTL, 0xBFAF);
- b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1403);
- if (phy->gmode || phy->rev >= 2) {
- b43_phy_write(dev, B43_PHY_RFOVERVAL,
- radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
- LPD(0, 0, 1)));
- }
- b43_phy_write(dev, B43_PHY_PGACTL, 0xBFA0);
- b43_radio_write16(dev, 0x51, b43_radio_read16(dev, 0x51)
- | 0x0004);
- if (phy->radio_rev == 8) {
- b43_radio_write16(dev, 0x43, 0x1F);
- } else {
- b43_radio_write16(dev, 0x52, 0);
- b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
- & 0xFFF0) | 0x0009);
- }
- b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
-
- for (i = 0; i < 16; i++) {
- b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0480);
- b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
- b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
- if (phy->gmode || phy->rev >= 2) {
- b43_phy_write(dev, B43_PHY_RFOVERVAL,
- radio2050_rfover_val(dev,
- B43_PHY_RFOVERVAL,
- LPD(1, 0, 1)));
- }
- b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
- udelay(10);
- if (phy->gmode || phy->rev >= 2) {
- b43_phy_write(dev, B43_PHY_RFOVERVAL,
- radio2050_rfover_val(dev,
- B43_PHY_RFOVERVAL,
- LPD(1, 0, 1)));
- }
- b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
- udelay(10);
- if (phy->gmode || phy->rev >= 2) {
- b43_phy_write(dev, B43_PHY_RFOVERVAL,
- radio2050_rfover_val(dev,
- B43_PHY_RFOVERVAL,
- LPD(1, 0, 0)));
- }
- b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
- udelay(20);
- tmp1 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
- b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
- if (phy->gmode || phy->rev >= 2) {
- b43_phy_write(dev, B43_PHY_RFOVERVAL,
- radio2050_rfover_val(dev,
- B43_PHY_RFOVERVAL,
- LPD(1, 0, 1)));
- }
- b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
- }
- udelay(10);
-
- b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
- tmp1++;
- tmp1 >>= 9;
-
- for (i = 0; i < 16; i++) {
- radio78 = (bitrev4(i) << 1) | 0x0020;
- b43_radio_write16(dev, 0x78, radio78);
- udelay(10);
- for (j = 0; j < 16; j++) {
- b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0D80);
- b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
- b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
- if (phy->gmode || phy->rev >= 2) {
- b43_phy_write(dev, B43_PHY_RFOVERVAL,
- radio2050_rfover_val(dev,
- B43_PHY_RFOVERVAL,
- LPD(1, 0,
- 1)));
- }
- b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
- udelay(10);
- if (phy->gmode || phy->rev >= 2) {
- b43_phy_write(dev, B43_PHY_RFOVERVAL,
- radio2050_rfover_val(dev,
- B43_PHY_RFOVERVAL,
- LPD(1, 0,
- 1)));
- }
- b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
- udelay(10);
- if (phy->gmode || phy->rev >= 2) {
- b43_phy_write(dev, B43_PHY_RFOVERVAL,
- radio2050_rfover_val(dev,
- B43_PHY_RFOVERVAL,
- LPD(1, 0,
- 0)));
- }
- b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
- udelay(10);
- tmp2 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
- b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
- if (phy->gmode || phy->rev >= 2) {
- b43_phy_write(dev, B43_PHY_RFOVERVAL,
- radio2050_rfover_val(dev,
- B43_PHY_RFOVERVAL,
- LPD(1, 0,
- 1)));
- }
- b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
- }
- tmp2++;
- tmp2 >>= 8;
- if (tmp1 < tmp2)
- break;
- }
-
- /* Restore the registers */
- b43_phy_write(dev, B43_PHY_PGACTL, sav.phy_pgactl);
- b43_radio_write16(dev, 0x51, sav.radio_51);
- b43_radio_write16(dev, 0x52, sav.radio_52);
- b43_radio_write16(dev, 0x43, sav.radio_43);
- b43_phy_write(dev, B43_PHY_CCK(0x5A), sav.phy_cck_5A);
- b43_phy_write(dev, B43_PHY_CCK(0x59), sav.phy_cck_59);
- b43_phy_write(dev, B43_PHY_CCK(0x58), sav.phy_cck_58);
- b43_write16(dev, 0x3E6, sav.reg_3E6);
- if (phy->analog != 0)
- b43_write16(dev, 0x3F4, sav.reg_3F4);
- b43_phy_write(dev, B43_PHY_SYNCCTL, sav.phy_syncctl);
- b43_synth_pu_workaround(dev, phy->channel);
- if (phy->type == B43_PHYTYPE_B) {
- b43_phy_write(dev, B43_PHY_CCK(0x30), sav.phy_cck_30);
- b43_write16(dev, 0x3EC, sav.reg_3EC);
- } else if (phy->gmode) {
- b43_write16(dev, B43_MMIO_PHY_RADIO,
- b43_read16(dev, B43_MMIO_PHY_RADIO)
- & 0x7FFF);
- b43_phy_write(dev, B43_PHY_RFOVER, sav.phy_rfover);
- b43_phy_write(dev, B43_PHY_RFOVERVAL, sav.phy_rfoverval);
- b43_phy_write(dev, B43_PHY_ANALOGOVER, sav.phy_analogover);
- b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
- sav.phy_analogoverval);
- b43_phy_write(dev, B43_PHY_CRS0, sav.phy_crs0);
- b43_phy_write(dev, B43_PHY_CLASSCTL, sav.phy_classctl);
- if (has_loopback_gain(phy)) {
- b43_phy_write(dev, B43_PHY_LO_MASK, sav.phy_lo_mask);
- b43_phy_write(dev, B43_PHY_LO_CTL, sav.phy_lo_ctl);
- }
- }
- if (i > 15)
- ret = radio78;
- else
- ret = rcc;
-
- return ret;
-}
-
-void b43_radio_init2060(struct b43_wldev *dev)
-{
- int err;
-
- b43_radio_write16(dev, 0x0004, 0x00C0);
- b43_radio_write16(dev, 0x0005, 0x0008);
- b43_radio_write16(dev, 0x0009, 0x0040);
- b43_radio_write16(dev, 0x0005, 0x00AA);
- b43_radio_write16(dev, 0x0032, 0x008F);
- b43_radio_write16(dev, 0x0006, 0x008F);
- b43_radio_write16(dev, 0x0034, 0x008F);
- b43_radio_write16(dev, 0x002C, 0x0007);
- b43_radio_write16(dev, 0x0082, 0x0080);
- b43_radio_write16(dev, 0x0080, 0x0000);
- b43_radio_write16(dev, 0x003F, 0x00DA);
- b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
- b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0010);
- b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
- b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
- msleep(1); /* delay 400usec */
-
- b43_radio_write16(dev, 0x0081,
- (b43_radio_read16(dev, 0x0081) & ~0x0020) | 0x0010);
- msleep(1); /* delay 400usec */
-
- b43_radio_write16(dev, 0x0005,
- (b43_radio_read16(dev, 0x0005) & ~0x0008) | 0x0008);
- b43_radio_write16(dev, 0x0085, b43_radio_read16(dev, 0x0085) & ~0x0010);
- b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
- b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0040);
- b43_radio_write16(dev, 0x0081,
- (b43_radio_read16(dev, 0x0081) & ~0x0040) | 0x0040);
- b43_radio_write16(dev, 0x0005,
- (b43_radio_read16(dev, 0x0081) & ~0x0008) | 0x0008);
- b43_phy_write(dev, 0x0063, 0xDDC6);
- b43_phy_write(dev, 0x0069, 0x07BE);
- b43_phy_write(dev, 0x006A, 0x0000);
-
- err = b43_radio_selectchannel(dev, B43_DEFAULT_CHANNEL_A, 0);
- B43_WARN_ON(err);
-
- msleep(1);
-}
-
-static inline u16 freq_r3A_value(u16 frequency)
-{
- u16 value;
-
- if (frequency < 5091)
- value = 0x0040;
- else if (frequency < 5321)
- value = 0x0000;
- else if (frequency < 5806)
- value = 0x0080;
- else
- value = 0x0040;
-
- return value;
-}
-
-void b43_radio_set_tx_iq(struct b43_wldev *dev)
-{
- static const u8 data_high[5] = { 0x00, 0x40, 0x80, 0x90, 0xD0 };
- static const u8 data_low[5] = { 0x00, 0x01, 0x05, 0x06, 0x0A };
- u16 tmp = b43_radio_read16(dev, 0x001E);
- int i, j;
-
- for (i = 0; i < 5; i++) {
- for (j = 0; j < 5; j++) {
- if (tmp == (data_high[i] << 4 | data_low[j])) {
- b43_phy_write(dev, 0x0069,
- (i - j) << 8 | 0x00C0);
- return;
- }
- }
- }
-}
-
-int b43_radio_selectchannel(struct b43_wldev *dev,
- u8 channel, int synthetic_pu_workaround)
-{
- struct b43_phy *phy = &dev->phy;
- u16 r8, tmp;
- u16 freq;
- u16 channelcookie, savedcookie;
- int err = 0;
-
- if (channel == 0xFF) {
- switch (phy->type) {
- case B43_PHYTYPE_A:
- channel = B43_DEFAULT_CHANNEL_A;
- break;
- case B43_PHYTYPE_B:
- case B43_PHYTYPE_G:
- channel = B43_DEFAULT_CHANNEL_BG;
- break;
- case B43_PHYTYPE_N:
- //FIXME check if we are on 2.4GHz or 5GHz and set a default channel.
- channel = 1;
- break;
- default:
- B43_WARN_ON(1);
- }
- }
-
- /* First we set the channel radio code to prevent the
- * firmware from sending ghost packets.
- */
- channelcookie = channel;
- if (0 /*FIXME on 5Ghz */)
- channelcookie |= 0x100;
- //FIXME set 40Mhz flag if required
- savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
- b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
-
- switch (phy->type) {
- case B43_PHYTYPE_A:
- if (channel > 200) {
- err = -EINVAL;
- goto out;
- }
- freq = channel2freq_a(channel);
-
- r8 = b43_radio_read16(dev, 0x0008);
- b43_write16(dev, 0x03F0, freq);
- b43_radio_write16(dev, 0x0008, r8);
-
- //TODO: write max channel TX power? to Radio 0x2D
- tmp = b43_radio_read16(dev, 0x002E);
- tmp &= 0x0080;
- //TODO: OR tmp with the Power out estimation for this channel?
- b43_radio_write16(dev, 0x002E, tmp);
-
- if (freq >= 4920 && freq <= 5500) {
- /*
- * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F;
- * = (freq * 0.025862069
- */
- r8 = 3 * freq / 116; /* is equal to r8 = freq * 0.025862 */
- }
- b43_radio_write16(dev, 0x0007, (r8 << 4) | r8);
- b43_radio_write16(dev, 0x0020, (r8 << 4) | r8);
- b43_radio_write16(dev, 0x0021, (r8 << 4) | r8);
- b43_radio_write16(dev, 0x0022, (b43_radio_read16(dev, 0x0022)
- & 0x000F) | (r8 << 4));
- b43_radio_write16(dev, 0x002A, (r8 << 4));
- b43_radio_write16(dev, 0x002B, (r8 << 4));
- b43_radio_write16(dev, 0x0008, (b43_radio_read16(dev, 0x0008)
- & 0x00F0) | (r8 << 4));
- b43_radio_write16(dev, 0x0029, (b43_radio_read16(dev, 0x0029)
- & 0xFF0F) | 0x00B0);
- b43_radio_write16(dev, 0x0035, 0x00AA);
- b43_radio_write16(dev, 0x0036, 0x0085);
- b43_radio_write16(dev, 0x003A, (b43_radio_read16(dev, 0x003A)
- & 0xFF20) |
- freq_r3A_value(freq));
- b43_radio_write16(dev, 0x003D,
- b43_radio_read16(dev, 0x003D) & 0x00FF);
- b43_radio_write16(dev, 0x0081, (b43_radio_read16(dev, 0x0081)
- & 0xFF7F) | 0x0080);
- b43_radio_write16(dev, 0x0035,
- b43_radio_read16(dev, 0x0035) & 0xFFEF);
- b43_radio_write16(dev, 0x0035, (b43_radio_read16(dev, 0x0035)
- & 0xFFEF) | 0x0010);
- b43_radio_set_tx_iq(dev);
- //TODO: TSSI2dbm workaround
- b43_phy_xmitpower(dev); //FIXME correct?
- break;
- case B43_PHYTYPE_G:
- if ((channel < 1) || (channel > 14)) {
- err = -EINVAL;
- goto out;
- }
-
- if (synthetic_pu_workaround)
- b43_synth_pu_workaround(dev, channel);
-
- b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
-
- if (channel == 14) {
- if (dev->dev->bus->sprom.country_code ==
- SSB_SPROM1CCODE_JAPAN)
- b43_hf_write(dev,
- b43_hf_read(dev) & ~B43_HF_ACPR);
- else
- b43_hf_write(dev,
- b43_hf_read(dev) | B43_HF_ACPR);
- b43_write16(dev, B43_MMIO_CHANNEL_EXT,
- b43_read16(dev, B43_MMIO_CHANNEL_EXT)
- | (1 << 11));
- } else {
- b43_write16(dev, B43_MMIO_CHANNEL_EXT,
- b43_read16(dev, B43_MMIO_CHANNEL_EXT)
- & 0xF7BF);
- }
- break;
- case B43_PHYTYPE_N:
- err = b43_nphy_selectchannel(dev, channel);
- if (err)
- goto out;
- break;
- default:
- B43_WARN_ON(1);
- }
-
- phy->channel = channel;
- /* Wait for the radio to tune to the channel and stabilize. */
- msleep(8);
-out:
- if (err) {
- b43_shm_write16(dev, B43_SHM_SHARED,
- B43_SHM_SH_CHAN, savedcookie);
- }
- return err;
-}
-
-void b43_radio_turn_on(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- int err;
- u8 channel;
-
- might_sleep();
-
- if (phy->radio_on)
- return;
-
- switch (phy->type) {
- case B43_PHYTYPE_A:
- b43_radio_write16(dev, 0x0004, 0x00C0);
- b43_radio_write16(dev, 0x0005, 0x0008);
- b43_phy_write(dev, 0x0010, b43_phy_read(dev, 0x0010) & 0xFFF7);
- b43_phy_write(dev, 0x0011, b43_phy_read(dev, 0x0011) & 0xFFF7);
- b43_radio_init2060(dev);
- break;
- case B43_PHYTYPE_B:
- case B43_PHYTYPE_G:
- b43_phy_write(dev, 0x0015, 0x8000);
- b43_phy_write(dev, 0x0015, 0xCC00);
- b43_phy_write(dev, 0x0015, (phy->gmode ? 0x00C0 : 0x0000));
- if (phy->radio_off_context.valid) {
- /* Restore the RFover values. */
- b43_phy_write(dev, B43_PHY_RFOVER,
- phy->radio_off_context.rfover);
- b43_phy_write(dev, B43_PHY_RFOVERVAL,
- phy->radio_off_context.rfoverval);
- phy->radio_off_context.valid = 0;
- }
- channel = phy->channel;
- err = b43_radio_selectchannel(dev, B43_DEFAULT_CHANNEL_BG, 1);
- err |= b43_radio_selectchannel(dev, channel, 0);
- B43_WARN_ON(err);
- break;
- case B43_PHYTYPE_N:
- b43_nphy_radio_turn_on(dev);
- break;
- default:
- B43_WARN_ON(1);
- }
- phy->radio_on = 1;
-}
-
-void b43_radio_turn_off(struct b43_wldev *dev, bool force)
-{
- struct b43_phy *phy = &dev->phy;
-
- if (!phy->radio_on && !force)
- return;
-
- switch (phy->type) {
- case B43_PHYTYPE_N:
- b43_nphy_radio_turn_off(dev);
- break;
- case B43_PHYTYPE_A:
- b43_radio_write16(dev, 0x0004, 0x00FF);
- b43_radio_write16(dev, 0x0005, 0x00FB);
- b43_phy_write(dev, 0x0010, b43_phy_read(dev, 0x0010) | 0x0008);
- b43_phy_write(dev, 0x0011, b43_phy_read(dev, 0x0011) | 0x0008);
- break;
- case B43_PHYTYPE_G: {
- u16 rfover, rfoverval;
-
- rfover = b43_phy_read(dev, B43_PHY_RFOVER);
- rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
- if (!force) {
- phy->radio_off_context.rfover = rfover;
- phy->radio_off_context.rfoverval = rfoverval;
- phy->radio_off_context.valid = 1;
- }
- b43_phy_write(dev, B43_PHY_RFOVER, rfover | 0x008C);
- b43_phy_write(dev, B43_PHY_RFOVERVAL, rfoverval & 0xFF73);
- break;
- }
- default:
- B43_WARN_ON(1);
- }
- phy->radio_on = 0;
-}
-#ifndef B43_PHY_H_
-#define B43_PHY_H_
-
-#include <linux/types.h>
-
-struct b43_wldev;
-struct b43_phy;
-
-/*** PHY Registers ***/
-
-/* Routing */
-#define B43_PHYROUTE 0x0C00 /* PHY register routing bits mask */
-#define B43_PHYROUTE_BASE 0x0000 /* Base registers */
-#define B43_PHYROUTE_OFDM_GPHY 0x0400 /* OFDM register routing for G-PHYs */
-#define B43_PHYROUTE_EXT_GPHY 0x0800 /* Extended G-PHY registers */
-#define B43_PHYROUTE_N_BMODE 0x0C00 /* N-PHY BMODE registers */
-
-/* CCK (B-PHY) registers. */
-#define B43_PHY_CCK(reg) ((reg) | B43_PHYROUTE_BASE)
-/* N-PHY registers. */
-#define B43_PHY_N(reg) ((reg) | B43_PHYROUTE_BASE)
-/* N-PHY BMODE registers. */
-#define B43_PHY_N_BMODE(reg) ((reg) | B43_PHYROUTE_N_BMODE)
-/* OFDM (A-PHY) registers. */
-#define B43_PHY_OFDM(reg) ((reg) | B43_PHYROUTE_OFDM_GPHY)
-/* Extended G-PHY registers. */
-#define B43_PHY_EXTG(reg) ((reg) | B43_PHYROUTE_EXT_GPHY)
-
-/* OFDM (A) PHY Registers */
-#define B43_PHY_VERSION_OFDM B43_PHY_OFDM(0x00) /* Versioning register for A-PHY */
-#define B43_PHY_BBANDCFG B43_PHY_OFDM(0x01) /* Baseband config */
-#define B43_PHY_BBANDCFG_RXANT 0x180 /* RX Antenna selection */
-#define B43_PHY_BBANDCFG_RXANT_SHIFT 7
-#define B43_PHY_PWRDOWN B43_PHY_OFDM(0x03) /* Powerdown */
-#define B43_PHY_CRSTHRES1_R1 B43_PHY_OFDM(0x06) /* CRS Threshold 1 (phy.rev 1 only) */
-#define B43_PHY_LNAHPFCTL B43_PHY_OFDM(0x1C) /* LNA/HPF control */
-#define B43_PHY_LPFGAINCTL B43_PHY_OFDM(0x20) /* LPF Gain control */
-#define B43_PHY_ADIVRELATED B43_PHY_OFDM(0x27) /* FIXME rename */
-#define B43_PHY_CRS0 B43_PHY_OFDM(0x29)
-#define B43_PHY_CRS0_EN 0x4000
-#define B43_PHY_PEAK_COUNT B43_PHY_OFDM(0x30)
-#define B43_PHY_ANTDWELL B43_PHY_OFDM(0x2B) /* Antenna dwell */
-#define B43_PHY_ANTDWELL_AUTODIV1 0x0100 /* Automatic RX diversity start antenna */
-#define B43_PHY_ENCORE B43_PHY_OFDM(0x49) /* "Encore" (RangeMax / BroadRange) */
-#define B43_PHY_ENCORE_EN 0x0200 /* Encore enable */
-#define B43_PHY_LMS B43_PHY_OFDM(0x55)
-#define B43_PHY_OFDM61 B43_PHY_OFDM(0x61) /* FIXME rename */
-#define B43_PHY_OFDM61_10 0x0010 /* FIXME rename */
-#define B43_PHY_IQBAL B43_PHY_OFDM(0x69) /* I/Q balance */
-#define B43_PHY_BBTXDC_BIAS B43_PHY_OFDM(0x6B) /* Baseband TX DC bias */
-#define B43_PHY_OTABLECTL B43_PHY_OFDM(0x72) /* OFDM table control (see below) */
-#define B43_PHY_OTABLEOFF 0x03FF /* OFDM table offset (see below) */
-#define B43_PHY_OTABLENR 0xFC00 /* OFDM table number (see below) */
-#define B43_PHY_OTABLENR_SHIFT 10
-#define B43_PHY_OTABLEI B43_PHY_OFDM(0x73) /* OFDM table data I */
-#define B43_PHY_OTABLEQ B43_PHY_OFDM(0x74) /* OFDM table data Q */
-#define B43_PHY_HPWR_TSSICTL B43_PHY_OFDM(0x78) /* Hardware power TSSI control */
-#define B43_PHY_ADCCTL B43_PHY_OFDM(0x7A) /* ADC control */
-#define B43_PHY_IDLE_TSSI B43_PHY_OFDM(0x7B)
-#define B43_PHY_A_TEMP_SENSE B43_PHY_OFDM(0x7C) /* A PHY temperature sense */
-#define B43_PHY_NRSSITHRES B43_PHY_OFDM(0x8A) /* NRSSI threshold */
-#define B43_PHY_ANTWRSETT B43_PHY_OFDM(0x8C) /* Antenna WR settle */
-#define B43_PHY_ANTWRSETT_ARXDIV 0x2000 /* Automatic RX diversity enabled */
-#define B43_PHY_CLIPPWRDOWNT B43_PHY_OFDM(0x93) /* Clip powerdown threshold */
-#define B43_PHY_OFDM9B B43_PHY_OFDM(0x9B) /* FIXME rename */
-#define B43_PHY_N1P1GAIN B43_PHY_OFDM(0xA0)
-#define B43_PHY_P1P2GAIN B43_PHY_OFDM(0xA1)
-#define B43_PHY_N1N2GAIN B43_PHY_OFDM(0xA2)
-#define B43_PHY_CLIPTHRES B43_PHY_OFDM(0xA3)
-#define B43_PHY_CLIPN1P2THRES B43_PHY_OFDM(0xA4)
-#define B43_PHY_CCKSHIFTBITS_WA B43_PHY_OFDM(0xA5) /* CCK shiftbits workaround, FIXME rename */
-#define B43_PHY_CCKSHIFTBITS B43_PHY_OFDM(0xA7) /* FIXME rename */
-#define B43_PHY_DIVSRCHIDX B43_PHY_OFDM(0xA8) /* Divider search gain/index */
-#define B43_PHY_CLIPP2THRES B43_PHY_OFDM(0xA9)
-#define B43_PHY_CLIPP3THRES B43_PHY_OFDM(0xAA)
-#define B43_PHY_DIVP1P2GAIN B43_PHY_OFDM(0xAB)
-#define B43_PHY_DIVSRCHGAINBACK B43_PHY_OFDM(0xAD) /* Divider search gain back */
-#define B43_PHY_DIVSRCHGAINCHNG B43_PHY_OFDM(0xAE) /* Divider search gain change */
-#define B43_PHY_CRSTHRES1 B43_PHY_OFDM(0xC0) /* CRS Threshold 1 (phy.rev >= 2 only) */
-#define B43_PHY_CRSTHRES2 B43_PHY_OFDM(0xC1) /* CRS Threshold 2 (phy.rev >= 2 only) */
-#define B43_PHY_TSSIP_LTBASE B43_PHY_OFDM(0x380) /* TSSI power lookup table base */
-#define B43_PHY_DC_LTBASE B43_PHY_OFDM(0x3A0) /* DC lookup table base */
-#define B43_PHY_GAIN_LTBASE B43_PHY_OFDM(0x3C0) /* Gain lookup table base */
-
-/* CCK (B) PHY Registers */
-#define B43_PHY_VERSION_CCK B43_PHY_CCK(0x00) /* Versioning register for B-PHY */
-#define B43_PHY_CCKBBANDCFG B43_PHY_CCK(0x01) /* Contains antenna 0/1 control bit */
-#define B43_PHY_PGACTL B43_PHY_CCK(0x15) /* PGA control */
-#define B43_PHY_PGACTL_LPF 0x1000 /* Low pass filter (?) */
-#define B43_PHY_PGACTL_LOWBANDW 0x0040 /* Low bandwidth flag */
-#define B43_PHY_PGACTL_UNKNOWN 0xEFA0
-#define B43_PHY_FBCTL1 B43_PHY_CCK(0x18) /* Frequency bandwidth control 1 */
-#define B43_PHY_ITSSI B43_PHY_CCK(0x29) /* Idle TSSI */
-#define B43_PHY_LO_LEAKAGE B43_PHY_CCK(0x2D) /* Measured LO leakage */
-#define B43_PHY_ENERGY B43_PHY_CCK(0x33) /* Energy */
-#define B43_PHY_SYNCCTL B43_PHY_CCK(0x35)
-#define B43_PHY_FBCTL2 B43_PHY_CCK(0x38) /* Frequency bandwidth control 2 */
-#define B43_PHY_DACCTL B43_PHY_CCK(0x60) /* DAC control */
-#define B43_PHY_RCCALOVER B43_PHY_CCK(0x78) /* RC calibration override */
-
-/* Extended G-PHY Registers */
-#define B43_PHY_CLASSCTL B43_PHY_EXTG(0x02) /* Classify control */
-#define B43_PHY_GTABCTL B43_PHY_EXTG(0x03) /* G-PHY table control (see below) */
-#define B43_PHY_GTABOFF 0x03FF /* G-PHY table offset (see below) */
-#define B43_PHY_GTABNR 0xFC00 /* G-PHY table number (see below) */
-#define B43_PHY_GTABNR_SHIFT 10
-#define B43_PHY_GTABDATA B43_PHY_EXTG(0x04) /* G-PHY table data */
-#define B43_PHY_LO_MASK B43_PHY_EXTG(0x0F) /* Local Oscillator control mask */
-#define B43_PHY_LO_CTL B43_PHY_EXTG(0x10) /* Local Oscillator control */
-#define B43_PHY_RFOVER B43_PHY_EXTG(0x11) /* RF override */
-#define B43_PHY_RFOVERVAL B43_PHY_EXTG(0x12) /* RF override value */
-#define B43_PHY_RFOVERVAL_EXTLNA 0x8000
-#define B43_PHY_RFOVERVAL_LNA 0x7000
-#define B43_PHY_RFOVERVAL_LNA_SHIFT 12
-#define B43_PHY_RFOVERVAL_PGA 0x0F00
-#define B43_PHY_RFOVERVAL_PGA_SHIFT 8
-#define B43_PHY_RFOVERVAL_UNK 0x0010 /* Unknown, always set. */
-#define B43_PHY_RFOVERVAL_TRSWRX 0x00E0
-#define B43_PHY_RFOVERVAL_BW 0x0003 /* Bandwidth flags */
-#define B43_PHY_RFOVERVAL_BW_LPF 0x0001 /* Low Pass Filter */
-#define B43_PHY_RFOVERVAL_BW_LBW 0x0002 /* Low Bandwidth (when set), high when unset */
-#define B43_PHY_ANALOGOVER B43_PHY_EXTG(0x14) /* Analog override */
-#define B43_PHY_ANALOGOVERVAL B43_PHY_EXTG(0x15) /* Analog override value */
-
-/*** OFDM table numbers ***/
-#define B43_OFDMTAB(number, offset) (((number) << B43_PHY_OTABLENR_SHIFT) | (offset))
-#define B43_OFDMTAB_AGC1 B43_OFDMTAB(0x00, 0)
-#define B43_OFDMTAB_GAIN0 B43_OFDMTAB(0x00, 0)
-#define B43_OFDMTAB_GAINX B43_OFDMTAB(0x01, 0) //TODO rename
-#define B43_OFDMTAB_GAIN1 B43_OFDMTAB(0x01, 4)
-#define B43_OFDMTAB_AGC3 B43_OFDMTAB(0x02, 0)
-#define B43_OFDMTAB_GAIN2 B43_OFDMTAB(0x02, 3)
-#define B43_OFDMTAB_LNAHPFGAIN1 B43_OFDMTAB(0x03, 0)
-#define B43_OFDMTAB_WRSSI B43_OFDMTAB(0x04, 0)
-#define B43_OFDMTAB_LNAHPFGAIN2 B43_OFDMTAB(0x04, 0)
-#define B43_OFDMTAB_NOISESCALE B43_OFDMTAB(0x05, 0)
-#define B43_OFDMTAB_AGC2 B43_OFDMTAB(0x06, 0)
-#define B43_OFDMTAB_ROTOR B43_OFDMTAB(0x08, 0)
-#define B43_OFDMTAB_ADVRETARD B43_OFDMTAB(0x09, 0)
-#define B43_OFDMTAB_DAC B43_OFDMTAB(0x0C, 0)
-#define B43_OFDMTAB_DC B43_OFDMTAB(0x0E, 7)
-#define B43_OFDMTAB_PWRDYN2 B43_OFDMTAB(0x0E, 12)
-#define B43_OFDMTAB_LNAGAIN B43_OFDMTAB(0x0E, 13)
-#define B43_OFDMTAB_UNKNOWN_0F B43_OFDMTAB(0x0F, 0) //TODO rename
-#define B43_OFDMTAB_UNKNOWN_APHY B43_OFDMTAB(0x0F, 7) //TODO rename
-#define B43_OFDMTAB_LPFGAIN B43_OFDMTAB(0x0F, 12)
-#define B43_OFDMTAB_RSSI B43_OFDMTAB(0x10, 0)
-#define B43_OFDMTAB_UNKNOWN_11 B43_OFDMTAB(0x11, 4) //TODO rename
-#define B43_OFDMTAB_AGC1_R1 B43_OFDMTAB(0x13, 0)
-#define B43_OFDMTAB_GAINX_R1 B43_OFDMTAB(0x14, 0) //TODO remove!
-#define B43_OFDMTAB_MINSIGSQ B43_OFDMTAB(0x14, 0)
-#define B43_OFDMTAB_AGC3_R1 B43_OFDMTAB(0x15, 0)
-#define B43_OFDMTAB_WRSSI_R1 B43_OFDMTAB(0x15, 4)
-#define B43_OFDMTAB_TSSI B43_OFDMTAB(0x15, 0)
-#define B43_OFDMTAB_DACRFPABB B43_OFDMTAB(0x16, 0)
-#define B43_OFDMTAB_DACOFF B43_OFDMTAB(0x17, 0)
-#define B43_OFDMTAB_DCBIAS B43_OFDMTAB(0x18, 0)
-
-u16 b43_ofdmtab_read16(struct b43_wldev *dev, u16 table, u16 offset);
-void b43_ofdmtab_write16(struct b43_wldev *dev, u16 table,
- u16 offset, u16 value);
-u32 b43_ofdmtab_read32(struct b43_wldev *dev, u16 table, u16 offset);
-void b43_ofdmtab_write32(struct b43_wldev *dev, u16 table,
- u16 offset, u32 value);
-
-/*** G-PHY table numbers */
-#define B43_GTAB(number, offset) (((number) << B43_PHY_GTABNR_SHIFT) | (offset))
-#define B43_GTAB_NRSSI B43_GTAB(0x00, 0)
-#define B43_GTAB_TRFEMW B43_GTAB(0x0C, 0x120)
-#define B43_GTAB_ORIGTR B43_GTAB(0x2E, 0x298)
-
-u16 b43_gtab_read(struct b43_wldev *dev, u16 table, u16 offset); //TODO implement
-void b43_gtab_write(struct b43_wldev *dev, u16 table, u16 offset, u16 value); //TODO implement
-
-#define B43_DEFAULT_CHANNEL_A 36
-#define B43_DEFAULT_CHANNEL_BG 6
-
-enum {
- B43_ANTENNA0, /* Antenna 0 */
- B43_ANTENNA1, /* Antenna 0 */
- B43_ANTENNA_AUTO1, /* Automatic, starting with antenna 1 */
- B43_ANTENNA_AUTO0, /* Automatic, starting with antenna 0 */
- B43_ANTENNA2,
- B43_ANTENNA3 = 8,
-
- B43_ANTENNA_AUTO = B43_ANTENNA_AUTO0,
- B43_ANTENNA_DEFAULT = B43_ANTENNA_AUTO,
-};
-
-enum {
- B43_INTERFMODE_NONE,
- B43_INTERFMODE_NONWLAN,
- B43_INTERFMODE_MANUALWLAN,
- B43_INTERFMODE_AUTOWLAN,
-};
-
-/* Masks for the different PHY versioning registers. */
-#define B43_PHYVER_ANALOG 0xF000
-#define B43_PHYVER_ANALOG_SHIFT 12
-#define B43_PHYVER_TYPE 0x0F00
-#define B43_PHYVER_TYPE_SHIFT 8
-#define B43_PHYVER_VERSION 0x00FF
-
-void b43_phy_lock(struct b43_wldev *dev);
-void b43_phy_unlock(struct b43_wldev *dev);
-
-
-/* Read a value from a PHY register */
-u16 b43_phy_read(struct b43_wldev *dev, u16 offset);
-/* Write a value to a PHY register */
-void b43_phy_write(struct b43_wldev *dev, u16 offset, u16 val);
-/* Mask a PHY register with a mask */
-void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask);
-/* OR a PHY register with a bitmap */
-void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set);
-/* Mask and OR a PHY register with a mask and bitmap */
-void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set);
-
-
-int b43_phy_init_tssi2dbm_table(struct b43_wldev *dev);
-
-void b43_phy_early_init(struct b43_wldev *dev);
-int b43_phy_init(struct b43_wldev *dev);
-
-void b43_set_rx_antenna(struct b43_wldev *dev, int antenna);
-
-void b43_phy_xmitpower(struct b43_wldev *dev);
-
-/* Returns the boolean whether the board has HardwarePowerControl */
-bool b43_has_hardware_pctl(struct b43_phy *phy);
-/* Returns the boolean whether "TX Magnification" is enabled. */
-#define has_tx_magnification(phy) \
- (((phy)->rev >= 2) && \
- ((phy)->radio_ver == 0x2050) && \
- ((phy)->radio_rev == 8))
-/* Card uses the loopback gain stuff */
-#define has_loopback_gain(phy) \
- (((phy)->rev > 1) || ((phy)->gmode))
-
-/* Radio Attenuation (RF Attenuation) */
-struct b43_rfatt {
- u8 att; /* Attenuation value */
- bool with_padmix; /* Flag, PAD Mixer enabled. */
-};
-struct b43_rfatt_list {
- /* Attenuation values list */
- const struct b43_rfatt *list;
- u8 len;
- /* Minimum/Maximum attenuation values */
- u8 min_val;
- u8 max_val;
-};
-
-/* Returns true, if the values are the same. */
-static inline bool b43_compare_rfatt(const struct b43_rfatt *a,
- const struct b43_rfatt *b)
-{
- return ((a->att == b->att) &&
- (a->with_padmix == b->with_padmix));
-}
-
-/* Baseband Attenuation */
-struct b43_bbatt {
- u8 att; /* Attenuation value */
-};
-struct b43_bbatt_list {
- /* Attenuation values list */
- const struct b43_bbatt *list;
- u8 len;
- /* Minimum/Maximum attenuation values */
- u8 min_val;
- u8 max_val;
-};
-
-/* Returns true, if the values are the same. */
-static inline bool b43_compare_bbatt(const struct b43_bbatt *a,
- const struct b43_bbatt *b)
-{
- return (a->att == b->att);
-}
-
-/* tx_control bits. */
-#define B43_TXCTL_PA3DB 0x40 /* PA Gain 3dB */
-#define B43_TXCTL_PA2DB 0x20 /* PA Gain 2dB */
-#define B43_TXCTL_TXMIX 0x10 /* TX Mixer Gain */
-
-/* Write BasebandAttenuation value to the device. */
-void b43_phy_set_baseband_attenuation(struct b43_wldev *dev,
- u16 baseband_attenuation);
-
-extern const u8 b43_radio_channel_codes_bg[];
-
-void b43_radio_lock(struct b43_wldev *dev);
-void b43_radio_unlock(struct b43_wldev *dev);
-
-
-/* Read a value from a 16bit radio register */
-u16 b43_radio_read16(struct b43_wldev *dev, u16 offset);
-/* Write a value to a 16bit radio register */
-void b43_radio_write16(struct b43_wldev *dev, u16 offset, u16 val);
-/* Mask a 16bit radio register with a mask */
-void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask);
-/* OR a 16bit radio register with a bitmap */
-void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set);
-/* Mask and OR a PHY register with a mask and bitmap */
-void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set);
-
-
-u16 b43_radio_init2050(struct b43_wldev *dev);
-void b43_radio_init2060(struct b43_wldev *dev);
-
-void b43_radio_turn_on(struct b43_wldev *dev);
-void b43_radio_turn_off(struct b43_wldev *dev, bool force);
-
-int b43_radio_selectchannel(struct b43_wldev *dev, u8 channel,
- int synthetic_pu_workaround);
-
-u8 b43_radio_aci_detect(struct b43_wldev *dev, u8 channel);
-u8 b43_radio_aci_scan(struct b43_wldev *dev);
-
-int b43_radio_set_interference_mitigation(struct b43_wldev *dev, int mode);
-
-void b43_calc_nrssi_slope(struct b43_wldev *dev);
-void b43_calc_nrssi_threshold(struct b43_wldev *dev);
-s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset);
-void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val);
-void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val);
-void b43_nrssi_mem_update(struct b43_wldev *dev);
-
-void b43_radio_set_tx_iq(struct b43_wldev *dev);
-u16 b43_radio_calibrationvalue(struct b43_wldev *dev);
-
-void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
- int *_bbatt, int *_rfatt);
-
-void b43_set_txpower_g(struct b43_wldev *dev,
- const struct b43_bbatt *bbatt,
- const struct b43_rfatt *rfatt, u8 tx_control);
-
-#endif /* B43_PHY_H_ */
-/*
-
- Broadcom B43 wireless driver
-
- PIO data transfer
-
- Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; see the file COPYING. If not, write to
- the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
- Boston, MA 02110-1301, USA.
-
-*/
-
-#include "b43.h"
-#include "pio.h"
-#include "dma.h"
-#include "main.h"
-#include "xmit.h"
-
-#include <linux/delay.h>
-
-
-static void b43_pio_rx_work(struct work_struct *work);
-
-
-static u16 generate_cookie(struct b43_pio_txqueue *q,
- struct b43_pio_txpacket *pack)
-{
- u16 cookie;
-
- /* Use the upper 4 bits of the cookie as
- * PIO controller ID and store the packet index number
- * in the lower 12 bits.
- * Note that the cookie must never be 0, as this
- * is a special value used in RX path.
- * It can also not be 0xFFFF because that is special
- * for multicast frames.
- */
- cookie = (((u16)q->index + 1) << 12);
- cookie |= pack->index;
-
- return cookie;
-}
-
-static
-struct b43_pio_txqueue * parse_cookie(struct b43_wldev *dev,
- u16 cookie,
- struct b43_pio_txpacket **pack)
-{
- struct b43_pio *pio = &dev->pio;
- struct b43_pio_txqueue *q = NULL;
- unsigned int pack_index;
-
- switch (cookie & 0xF000) {
- case 0x1000:
- q = pio->tx_queue_AC_BK;
- break;
- case 0x2000:
- q = pio->tx_queue_AC_BE;
- break;
- case 0x3000:
- q = pio->tx_queue_AC_VI;
- break;
- case 0x4000:
- q = pio->tx_queue_AC_VO;
- break;
- case 0x5000:
- q = pio->tx_queue_mcast;
- break;
- }
- if (B43_WARN_ON(!q))
- return NULL;
- pack_index = (cookie & 0x0FFF);
- if (B43_WARN_ON(pack_index >= ARRAY_SIZE(q->packets)))
- return NULL;
- *pack = &q->packets[pack_index];
-
- return q;
-}
-
-static u16 index_to_pioqueue_base(struct b43_wldev *dev,
- unsigned int index)
-{
- static const u16 bases[] = {
- B43_MMIO_PIO_BASE0,
- B43_MMIO_PIO_BASE1,
- B43_MMIO_PIO_BASE2,
- B43_MMIO_PIO_BASE3,
- B43_MMIO_PIO_BASE4,
- B43_MMIO_PIO_BASE5,
- B43_MMIO_PIO_BASE6,
- B43_MMIO_PIO_BASE7,
- };
- static const u16 bases_rev11[] = {
- B43_MMIO_PIO11_BASE0,
- B43_MMIO_PIO11_BASE1,
- B43_MMIO_PIO11_BASE2,
- B43_MMIO_PIO11_BASE3,
- B43_MMIO_PIO11_BASE4,
- B43_MMIO_PIO11_BASE5,
- };
-
- if (dev->dev->id.revision >= 11) {
- B43_WARN_ON(index >= ARRAY_SIZE(bases_rev11));
- return bases_rev11[index];
- }
- B43_WARN_ON(index >= ARRAY_SIZE(bases));
- return bases[index];
-}
-
-static u16 pio_txqueue_offset(struct b43_wldev *dev)
-{
- if (dev->dev->id.revision >= 11)
- return 0x18;
- return 0;
-}
-
-static u16 pio_rxqueue_offset(struct b43_wldev *dev)
-{
- if (dev->dev->id.revision >= 11)
- return 0x38;
- return 8;
-}
-
-static struct b43_pio_txqueue * b43_setup_pioqueue_tx(struct b43_wldev *dev,
- unsigned int index)
-{
- struct b43_pio_txqueue *q;
- struct b43_pio_txpacket *p;
- unsigned int i;
-
- q = kzalloc(sizeof(*q), GFP_KERNEL);
- if (!q)
- return NULL;
- spin_lock_init(&q->lock);
- q->dev = dev;
- q->rev = dev->dev->id.revision;
- q->mmio_base = index_to_pioqueue_base(dev, index) +
- pio_txqueue_offset(dev);
- q->index = index;
-
- q->free_packet_slots = B43_PIO_MAX_NR_TXPACKETS;
- if (q->rev >= 8) {
- q->buffer_size = 1920; //FIXME this constant is wrong.
- } else {
- q->buffer_size = b43_piotx_read16(q, B43_PIO_TXQBUFSIZE);
- q->buffer_size -= 80;
- }
-
- INIT_LIST_HEAD(&q->packets_list);
- for (i = 0; i < ARRAY_SIZE(q->packets); i++) {
- p = &(q->packets[i]);
- INIT_LIST_HEAD(&p->list);
- p->index = i;
- p->queue = q;
- list_add(&p->list, &q->packets_list);
- }
-
- return q;
-}
-
-static struct b43_pio_rxqueue * b43_setup_pioqueue_rx(struct b43_wldev *dev,
- unsigned int index)
-{
- struct b43_pio_rxqueue *q;
-
- q = kzalloc(sizeof(*q), GFP_KERNEL);
- if (!q)
- return NULL;
- spin_lock_init(&q->lock);
- q->dev = dev;
- q->rev = dev->dev->id.revision;
- q->mmio_base = index_to_pioqueue_base(dev, index) +
- pio_rxqueue_offset(dev);
- INIT_WORK(&q->rx_work, b43_pio_rx_work);
-
- /* Enable Direct FIFO RX (PIO) on the engine. */
- b43_dma_direct_fifo_rx(dev, index, 1);
-
- return q;
-}
-
-static void b43_pio_cancel_tx_packets(struct b43_pio_txqueue *q)
-{
- struct b43_pio_txpacket *pack;
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE(q->packets); i++) {
- pack = &(q->packets[i]);
- if (pack->skb) {
- dev_kfree_skb_any(pack->skb);
- pack->skb = NULL;
- }
- }
-}
-
-static void b43_destroy_pioqueue_tx(struct b43_pio_txqueue *q,
- const char *name)
-{
- if (!q)
- return;
- b43_pio_cancel_tx_packets(q);
- kfree(q);
-}
-
-static void b43_destroy_pioqueue_rx(struct b43_pio_rxqueue *q,
- const char *name)
-{
- if (!q)
- return;
- kfree(q);
-}
-
-#define destroy_queue_tx(pio, queue) do { \
- b43_destroy_pioqueue_tx((pio)->queue, __stringify(queue)); \
- (pio)->queue = NULL; \
- } while (0)
-
-#define destroy_queue_rx(pio, queue) do { \
- b43_destroy_pioqueue_rx((pio)->queue, __stringify(queue)); \
- (pio)->queue = NULL; \
- } while (0)
-
-void b43_pio_free(struct b43_wldev *dev)
-{
- struct b43_pio *pio;
-
- if (!b43_using_pio_transfers(dev))
- return;
- pio = &dev->pio;
-
- destroy_queue_rx(pio, rx_queue);
- destroy_queue_tx(pio, tx_queue_mcast);
- destroy_queue_tx(pio, tx_queue_AC_VO);
- destroy_queue_tx(pio, tx_queue_AC_VI);
- destroy_queue_tx(pio, tx_queue_AC_BE);
- destroy_queue_tx(pio, tx_queue_AC_BK);
-}
-
-void b43_pio_stop(struct b43_wldev *dev)
-{
- if (!b43_using_pio_transfers(dev))
- return;
- cancel_work_sync(&dev->pio.rx_queue->rx_work);
-}
-
-int b43_pio_init(struct b43_wldev *dev)
-{
- struct b43_pio *pio = &dev->pio;
- int err = -ENOMEM;
-
- b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
- & ~B43_MACCTL_BE);
- b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RXPADOFF, 0);
-
- pio->tx_queue_AC_BK = b43_setup_pioqueue_tx(dev, 0);
- if (!pio->tx_queue_AC_BK)
- goto out;
-
- pio->tx_queue_AC_BE = b43_setup_pioqueue_tx(dev, 1);
- if (!pio->tx_queue_AC_BE)
- goto err_destroy_bk;
-
- pio->tx_queue_AC_VI = b43_setup_pioqueue_tx(dev, 2);
- if (!pio->tx_queue_AC_VI)
- goto err_destroy_be;
-
- pio->tx_queue_AC_VO = b43_setup_pioqueue_tx(dev, 3);
- if (!pio->tx_queue_AC_VO)
- goto err_destroy_vi;
-
- pio->tx_queue_mcast = b43_setup_pioqueue_tx(dev, 4);
- if (!pio->tx_queue_mcast)
- goto err_destroy_vo;
-
- pio->rx_queue = b43_setup_pioqueue_rx(dev, 0);
- if (!pio->rx_queue)
- goto err_destroy_mcast;
-
- b43dbg(dev->wl, "PIO initialized\n");
- err = 0;
-out:
- return err;
-
-err_destroy_mcast:
- destroy_queue_tx(pio, tx_queue_mcast);
-err_destroy_vo:
- destroy_queue_tx(pio, tx_queue_AC_VO);
-err_destroy_vi:
- destroy_queue_tx(pio, tx_queue_AC_VI);
-err_destroy_be:
- destroy_queue_tx(pio, tx_queue_AC_BE);
-err_destroy_bk:
- destroy_queue_tx(pio, tx_queue_AC_BK);
- return err;
-}
-
-/* Static mapping of mac80211's queues (priorities) to b43 PIO queues. */
-static struct b43_pio_txqueue * select_queue_by_priority(struct b43_wldev *dev,
- u8 queue_prio)
-{
- struct b43_pio_txqueue *q;
-
- if (b43_modparam_qos) {
- /* 0 = highest priority */
- switch (queue_prio) {
- default:
- B43_WARN_ON(1);
- /* fallthrough */
- case 0:
- q = dev->pio.tx_queue_AC_VO;
- break;
- case 1:
- q = dev->pio.tx_queue_AC_VI;
- break;
- case 2:
- q = dev->pio.tx_queue_AC_BE;
- break;
- case 3:
- q = dev->pio.tx_queue_AC_BK;
- break;
- }
- } else
- q = dev->pio.tx_queue_AC_BE;
-
- return q;
-}
-
-static u16 tx_write_2byte_queue(struct b43_pio_txqueue *q,
- u16 ctl,
- const void *_data,
- unsigned int data_len)
-{
- struct b43_wldev *dev = q->dev;
- const u8 *data = _data;
-
- ctl |= B43_PIO_TXCTL_WRITELO | B43_PIO_TXCTL_WRITEHI;
- b43_piotx_write16(q, B43_PIO_TXCTL, ctl);
-
- ssb_block_write(dev->dev, data, (data_len & ~1),
- q->mmio_base + B43_PIO_TXDATA,
- sizeof(u16));
- if (data_len & 1) {
- /* Write the last byte. */
- ctl &= ~B43_PIO_TXCTL_WRITEHI;
- b43_piotx_write16(q, B43_PIO_TXCTL, ctl);
- b43_piotx_write16(q, B43_PIO_TXDATA, data[data_len - 1]);
- }
-
- return ctl;
-}
-
-static void pio_tx_frame_2byte_queue(struct b43_pio_txpacket *pack,
- const u8 *hdr, unsigned int hdrlen)
-{
- struct b43_pio_txqueue *q = pack->queue;
- const char *frame = pack->skb->data;
- unsigned int frame_len = pack->skb->len;
- u16 ctl;
-
- ctl = b43_piotx_read16(q, B43_PIO_TXCTL);
- ctl |= B43_PIO_TXCTL_FREADY;
- ctl &= ~B43_PIO_TXCTL_EOF;
-
- /* Transfer the header data. */
- ctl = tx_write_2byte_queue(q, ctl, hdr, hdrlen);
- /* Transfer the frame data. */
- ctl = tx_write_2byte_queue(q, ctl, frame, frame_len);
-
- ctl |= B43_PIO_TXCTL_EOF;
- b43_piotx_write16(q, B43_PIO_TXCTL, ctl);
-}
-
-static u32 tx_write_4byte_queue(struct b43_pio_txqueue *q,
- u32 ctl,
- const void *_data,
- unsigned int data_len)
-{
- struct b43_wldev *dev = q->dev;
- const u8 *data = _data;
-
- ctl |= B43_PIO8_TXCTL_0_7 | B43_PIO8_TXCTL_8_15 |
- B43_PIO8_TXCTL_16_23 | B43_PIO8_TXCTL_24_31;
- b43_piotx_write32(q, B43_PIO8_TXCTL, ctl);
-
- ssb_block_write(dev->dev, data, (data_len & ~3),
- q->mmio_base + B43_PIO8_TXDATA,
- sizeof(u32));
- if (data_len & 3) {
- u32 value = 0;
-
- /* Write the last few bytes. */
- ctl &= ~(B43_PIO8_TXCTL_8_15 | B43_PIO8_TXCTL_16_23 |
- B43_PIO8_TXCTL_24_31);
- data = &(data[data_len - 1]);
- switch (data_len & 3) {
- case 3:
- ctl |= B43_PIO8_TXCTL_16_23;
- value |= (u32)(*data) << 16;
- data--;
- case 2:
- ctl |= B43_PIO8_TXCTL_8_15;
- value |= (u32)(*data) << 8;
- data--;
- case 1:
- value |= (u32)(*data);
- }
- b43_piotx_write32(q, B43_PIO8_TXCTL, ctl);
- b43_piotx_write32(q, B43_PIO8_TXDATA, value);
- }
-
- return ctl;
-}
-
-static void pio_tx_frame_4byte_queue(struct b43_pio_txpacket *pack,
- const u8 *hdr, unsigned int hdrlen)
-{
- struct b43_pio_txqueue *q = pack->queue;
- const char *frame = pack->skb->data;
- unsigned int frame_len = pack->skb->len;
- u32 ctl;
-
- ctl = b43_piotx_read32(q, B43_PIO8_TXCTL);
- ctl |= B43_PIO8_TXCTL_FREADY;
- ctl &= ~B43_PIO8_TXCTL_EOF;
-
- /* Transfer the header data. */
- ctl = tx_write_4byte_queue(q, ctl, hdr, hdrlen);
- /* Transfer the frame data. */
- ctl = tx_write_4byte_queue(q, ctl, frame, frame_len);
-
- ctl |= B43_PIO8_TXCTL_EOF;
- b43_piotx_write32(q, B43_PIO_TXCTL, ctl);
-}
-
-static int pio_tx_frame(struct b43_pio_txqueue *q,
- struct sk_buff *skb)
-{
- struct b43_pio_txpacket *pack;
- struct b43_txhdr txhdr;
- u16 cookie;
- int err;
- unsigned int hdrlen;
- struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
-
- B43_WARN_ON(list_empty(&q->packets_list));
- pack = list_entry(q->packets_list.next,
- struct b43_pio_txpacket, list);
-
- cookie = generate_cookie(q, pack);
- hdrlen = b43_txhdr_size(q->dev);
- err = b43_generate_txhdr(q->dev, (u8 *)&txhdr, skb->data,
- skb->len, info, cookie);
- if (err)
- return err;
-
- if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
- /* Tell the firmware about the cookie of the last
- * mcast frame, so it can clear the more-data bit in it. */
- b43_shm_write16(q->dev, B43_SHM_SHARED,
- B43_SHM_SH_MCASTCOOKIE, cookie);
- }
-
- pack->skb = skb;
- if (q->rev >= 8)
- pio_tx_frame_4byte_queue(pack, (const u8 *)&txhdr, hdrlen);
- else
- pio_tx_frame_2byte_queue(pack, (const u8 *)&txhdr, hdrlen);
-
- /* Remove it from the list of available packet slots.
- * It will be put back when we receive the status report. */
- list_del(&pack->list);
-
- /* Update the queue statistics. */
- q->buffer_used += roundup(skb->len + hdrlen, 4);
- q->free_packet_slots -= 1;
-
- return 0;
-}
-
-int b43_pio_tx(struct b43_wldev *dev, struct sk_buff *skb)
-{
- struct b43_pio_txqueue *q;
- struct ieee80211_hdr *hdr;
- unsigned long flags;
- unsigned int hdrlen, total_len;
- int err = 0;
- struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
-
- hdr = (struct ieee80211_hdr *)skb->data;
-
- if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
- /* The multicast queue will be sent after the DTIM. */
- q = dev->pio.tx_queue_mcast;
- /* Set the frame More-Data bit. Ucode will clear it
- * for us on the last frame. */
- hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
- } else {
- /* Decide by priority where to put this frame. */
- q = select_queue_by_priority(dev, skb_get_queue_mapping(skb));
- }
-
- spin_lock_irqsave(&q->lock, flags);
-
- hdrlen = b43_txhdr_size(dev);
- total_len = roundup(skb->len + hdrlen, 4);
-
- if (unlikely(total_len > q->buffer_size)) {
- err = -ENOBUFS;
- b43dbg(dev->wl, "PIO: TX packet longer than queue.\n");
- goto out_unlock;
- }
- if (unlikely(q->free_packet_slots == 0)) {
- err = -ENOBUFS;
- b43warn(dev->wl, "PIO: TX packet overflow.\n");
- goto out_unlock;
- }
- B43_WARN_ON(q->buffer_used > q->buffer_size);
-
- if (total_len > (q->buffer_size - q->buffer_used)) {
- /* Not enough memory on the queue. */
- err = -EBUSY;
- ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
- q->stopped = 1;
- goto out_unlock;
- }
-
- /* Assign the queue number to the ring (if not already done before)
- * so TX status handling can use it. The mac80211-queue to b43-queue
- * mapping is static, so we don't need to store it per frame. */
- q->queue_prio = skb_get_queue_mapping(skb);
-
- err = pio_tx_frame(q, skb);
- if (unlikely(err == -ENOKEY)) {
- /* Drop this packet, as we don't have the encryption key
- * anymore and must not transmit it unencrypted. */
- dev_kfree_skb_any(skb);
- err = 0;
- goto out_unlock;
- }
- if (unlikely(err)) {
- b43err(dev->wl, "PIO transmission failure\n");
- goto out_unlock;
- }
- q->nr_tx_packets++;
-
- B43_WARN_ON(q->buffer_used > q->buffer_size);
- if (((q->buffer_size - q->buffer_used) < roundup(2 + 2 + 6, 4)) ||
- (q->free_packet_slots == 0)) {
- /* The queue is full. */
- ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
- q->stopped = 1;
- }
-
-out_unlock:
- spin_unlock_irqrestore(&q->lock, flags);
-
- return err;
-}
-
-/* Called with IRQs disabled. */
-void b43_pio_handle_txstatus(struct b43_wldev *dev,
- const struct b43_txstatus *status)
-{
- struct b43_pio_txqueue *q;
- struct b43_pio_txpacket *pack = NULL;
- unsigned int total_len;
- struct ieee80211_tx_info *info;
-
- q = parse_cookie(dev, status->cookie, &pack);
- if (unlikely(!q))
- return;
- B43_WARN_ON(!pack);
-
- spin_lock(&q->lock); /* IRQs are already disabled. */
-
- info = (void *)pack->skb;
- memset(&info->status, 0, sizeof(info->status));
-
- b43_fill_txstatus_report(info, status);
-
- total_len = pack->skb->len + b43_txhdr_size(dev);
- total_len = roundup(total_len, 4);
- q->buffer_used -= total_len;
- q->free_packet_slots += 1;
-
- ieee80211_tx_status_irqsafe(dev->wl->hw, pack->skb);
- pack->skb = NULL;
- list_add(&pack->list, &q->packets_list);
-
- if (q->stopped) {
- ieee80211_wake_queue(dev->wl->hw, q->queue_prio);
- q->stopped = 0;
- }
-
- spin_unlock(&q->lock);
-}
-
-void b43_pio_get_tx_stats(struct b43_wldev *dev,
- struct ieee80211_tx_queue_stats *stats)
-{
- const int nr_queues = dev->wl->hw->queues;
- struct b43_pio_txqueue *q;
- unsigned long flags;
- int i;
-
- for (i = 0; i < nr_queues; i++) {
- q = select_queue_by_priority(dev, i);
-
- spin_lock_irqsave(&q->lock, flags);
- stats[i].len = B43_PIO_MAX_NR_TXPACKETS - q->free_packet_slots;
- stats[i].limit = B43_PIO_MAX_NR_TXPACKETS;
- stats[i].count = q->nr_tx_packets;
- spin_unlock_irqrestore(&q->lock, flags);
- }
-}
-
-/* Returns whether we should fetch another frame. */
-static bool pio_rx_frame(struct b43_pio_rxqueue *q)
-{
- struct b43_wldev *dev = q->dev;
- struct b43_rxhdr_fw4 rxhdr;
- u16 len;
- u32 macstat;
- unsigned int i, padding;
- struct sk_buff *skb;
- const char *err_msg = NULL;
-
- memset(&rxhdr, 0, sizeof(rxhdr));
-
- /* Check if we have data and wait for it to get ready. */
- if (q->rev >= 8) {
- u32 ctl;
-
- ctl = b43_piorx_read32(q, B43_PIO8_RXCTL);
- if (!(ctl & B43_PIO8_RXCTL_FRAMERDY))
- return 0;
- b43_piorx_write32(q, B43_PIO8_RXCTL,
- B43_PIO8_RXCTL_FRAMERDY);
- for (i = 0; i < 10; i++) {
- ctl = b43_piorx_read32(q, B43_PIO8_RXCTL);
- if (ctl & B43_PIO8_RXCTL_DATARDY)
- goto data_ready;
- udelay(10);
- }
- } else {
- u16 ctl;
-
- ctl = b43_piorx_read16(q, B43_PIO_RXCTL);
- if (!(ctl & B43_PIO_RXCTL_FRAMERDY))
- return 0;
- b43_piorx_write16(q, B43_PIO_RXCTL,
- B43_PIO_RXCTL_FRAMERDY);
- for (i = 0; i < 10; i++) {
- ctl = b43_piorx_read16(q, B43_PIO_RXCTL);
- if (ctl & B43_PIO_RXCTL_DATARDY)
- goto data_ready;
- udelay(10);
- }
- }
- b43dbg(q->dev->wl, "PIO RX timed out\n");
- return 1;
-data_ready:
-
- /* Get the preamble (RX header) */
- if (q->rev >= 8) {
- ssb_block_read(dev->dev, &rxhdr, sizeof(rxhdr),
- q->mmio_base + B43_PIO8_RXDATA,
- sizeof(u32));
- } else {
- ssb_block_read(dev->dev, &rxhdr, sizeof(rxhdr),
- q->mmio_base + B43_PIO_RXDATA,
- sizeof(u16));
- }
- /* Sanity checks. */
- len = le16_to_cpu(rxhdr.frame_len);
- if (unlikely(len > 0x700)) {
- err_msg = "len > 0x700";
- goto rx_error;
- }
- if (unlikely(len == 0)) {
- err_msg = "len == 0";
- goto rx_error;
- }
-
- macstat = le32_to_cpu(rxhdr.mac_status);
- if (macstat & B43_RX_MAC_FCSERR) {
- if (!(q->dev->wl->filter_flags & FIF_FCSFAIL)) {
- /* Drop frames with failed FCS. */
- err_msg = "Frame FCS error";
- goto rx_error;
- }
- }
-
- /* We always pad 2 bytes, as that's what upstream code expects
- * due to the RX-header being 30 bytes. In case the frame is
- * unaligned, we pad another 2 bytes. */
- padding = (macstat & B43_RX_MAC_PADDING) ? 2 : 0;
- skb = dev_alloc_skb(len + padding + 2);
- if (unlikely(!skb)) {
- err_msg = "Out of memory";
- goto rx_error;
- }
- skb_reserve(skb, 2);
- skb_put(skb, len + padding);
- if (q->rev >= 8) {
- ssb_block_read(dev->dev, skb->data + padding, (len & ~3),
- q->mmio_base + B43_PIO8_RXDATA,
- sizeof(u32));
- if (len & 3) {
- u32 value;
- char *data;
-
- /* Read the last few bytes. */
- value = b43_piorx_read32(q, B43_PIO8_RXDATA);
- data = &(skb->data[len + padding - 1]);
- switch (len & 3) {
- case 3:
- *data = (value >> 16);
- data--;
- case 2:
- *data = (value >> 8);
- data--;
- case 1:
- *data = value;
- }
- }
- } else {
- ssb_block_read(dev->dev, skb->data + padding, (len & ~1),
- q->mmio_base + B43_PIO_RXDATA,
- sizeof(u16));
- if (len & 1) {
- u16 value;
-
- /* Read the last byte. */
- value = b43_piorx_read16(q, B43_PIO_RXDATA);
- skb->data[len + padding - 1] = value;
- }
- }
-
- b43_rx(q->dev, skb, &rxhdr);
-
- return 1;
-
-rx_error:
- if (err_msg)
- b43dbg(q->dev->wl, "PIO RX error: %s\n", err_msg);
- b43_piorx_write16(q, B43_PIO_RXCTL, B43_PIO_RXCTL_DATARDY);
- return 1;
-}
-
-/* RX workqueue. We can sleep, yay! */
-static void b43_pio_rx_work(struct work_struct *work)
-{
- struct b43_pio_rxqueue *q = container_of(work, struct b43_pio_rxqueue,
- rx_work);
- unsigned int budget = 50;
- bool stop;
-
- do {
- spin_lock_irq(&q->lock);
- stop = (pio_rx_frame(q) == 0);
- spin_unlock_irq(&q->lock);
- cond_resched();
- if (stop)
- break;
- } while (--budget);
-}
-
-/* Called with IRQs disabled. */
-void b43_pio_rx(struct b43_pio_rxqueue *q)
-{
- /* Due to latency issues we must run the RX path in
- * a workqueue to be able to schedule between packets. */
- queue_work(q->dev->wl->hw->workqueue, &q->rx_work);
-}
-
-static void b43_pio_tx_suspend_queue(struct b43_pio_txqueue *q)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&q->lock, flags);
- if (q->rev >= 8) {
- b43_piotx_write32(q, B43_PIO8_TXCTL,
- b43_piotx_read32(q, B43_PIO8_TXCTL)
- | B43_PIO8_TXCTL_SUSPREQ);
- } else {
- b43_piotx_write16(q, B43_PIO_TXCTL,
- b43_piotx_read16(q, B43_PIO_TXCTL)
- | B43_PIO_TXCTL_SUSPREQ);
- }
- spin_unlock_irqrestore(&q->lock, flags);
-}
-
-static void b43_pio_tx_resume_queue(struct b43_pio_txqueue *q)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&q->lock, flags);
- if (q->rev >= 8) {
- b43_piotx_write32(q, B43_PIO8_TXCTL,
- b43_piotx_read32(q, B43_PIO8_TXCTL)
- & ~B43_PIO8_TXCTL_SUSPREQ);
- } else {
- b43_piotx_write16(q, B43_PIO_TXCTL,
- b43_piotx_read16(q, B43_PIO_TXCTL)
- & ~B43_PIO_TXCTL_SUSPREQ);
- }
- spin_unlock_irqrestore(&q->lock, flags);
-}
-
-void b43_pio_tx_suspend(struct b43_wldev *dev)
-{
- b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
- b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_BK);
- b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_BE);
- b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_VI);
- b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_VO);
- b43_pio_tx_suspend_queue(dev->pio.tx_queue_mcast);
-}
-
-void b43_pio_tx_resume(struct b43_wldev *dev)
-{
- b43_pio_tx_resume_queue(dev->pio.tx_queue_mcast);
- b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_VO);
- b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_VI);
- b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_BE);
- b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_BK);
- b43_power_saving_ctl_bits(dev, 0);
-}
-#ifndef B43_PIO_H_
-#define B43_PIO_H_
-
-#include "b43.h"
-
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/list.h>
-#include <linux/skbuff.h>
-
-
-/*** Registers for PIO queues up to revision 7. ***/
-/* TX queue. */
-#define B43_PIO_TXCTL 0x00
-#define B43_PIO_TXCTL_WRITELO 0x0001
-#define B43_PIO_TXCTL_WRITEHI 0x0002
-#define B43_PIO_TXCTL_EOF 0x0004
-#define B43_PIO_TXCTL_FREADY 0x0008
-#define B43_PIO_TXCTL_FLUSHREQ 0x0020
-#define B43_PIO_TXCTL_FLUSHPEND 0x0040
-#define B43_PIO_TXCTL_SUSPREQ 0x0080
-#define B43_PIO_TXCTL_QSUSP 0x0100
-#define B43_PIO_TXCTL_COMMCNT 0xFC00
-#define B43_PIO_TXCTL_COMMCNT_SHIFT 10
-#define B43_PIO_TXDATA 0x02
-#define B43_PIO_TXQBUFSIZE 0x04
-/* RX queue. */
-#define B43_PIO_RXCTL 0x00
-#define B43_PIO_RXCTL_FRAMERDY 0x0001
-#define B43_PIO_RXCTL_DATARDY 0x0002
-#define B43_PIO_RXDATA 0x02
-
-/*** Registers for PIO queues revision 8 and later. ***/
-/* TX queue */
-#define B43_PIO8_TXCTL 0x00
-#define B43_PIO8_TXCTL_0_7 0x00000001
-#define B43_PIO8_TXCTL_8_15 0x00000002
-#define B43_PIO8_TXCTL_16_23 0x00000004
-#define B43_PIO8_TXCTL_24_31 0x00000008
-#define B43_PIO8_TXCTL_EOF 0x00000010
-#define B43_PIO8_TXCTL_FREADY 0x00000080
-#define B43_PIO8_TXCTL_SUSPREQ 0x00000100
-#define B43_PIO8_TXCTL_QSUSP 0x00000200
-#define B43_PIO8_TXCTL_FLUSHREQ 0x00000400
-#define B43_PIO8_TXCTL_FLUSHPEND 0x00000800
-#define B43_PIO8_TXDATA 0x04
-/* RX queue */
-#define B43_PIO8_RXCTL 0x00
-#define B43_PIO8_RXCTL_FRAMERDY 0x00000001
-#define B43_PIO8_RXCTL_DATARDY 0x00000002
-#define B43_PIO8_RXDATA 0x04
-
-
-/* The maximum number of TX-packets the HW can handle. */
-#define B43_PIO_MAX_NR_TXPACKETS 32
-
-
-#ifdef CONFIG_B43_PIO
-
-struct b43_pio_txpacket {
- /* Pointer to the TX queue we belong to. */
- struct b43_pio_txqueue *queue;
- /* The TX data packet. */
- struct sk_buff *skb;
- /* Index in the (struct b43_pio_txqueue)->packets array. */
- u8 index;
-
- struct list_head list;
-};
-
-struct b43_pio_txqueue {
- struct b43_wldev *dev;
- spinlock_t lock;
- u16 mmio_base;
-
- /* The device queue buffer size in bytes. */
- u16 buffer_size;
- /* The number of used bytes in the device queue buffer. */
- u16 buffer_used;
- /* The number of packets that can still get queued.
- * This is decremented on queueing a packet and incremented
- * after receiving the transmit status. */
- u16 free_packet_slots;
-
- /* True, if the mac80211 queue was stopped due to overflow at TX. */
- bool stopped;
- /* Our b43 queue index number */
- u8 index;
- /* The mac80211 QoS queue priority. */
- u8 queue_prio;
-
- /* Buffer for TX packet meta data. */
- struct b43_pio_txpacket packets[B43_PIO_MAX_NR_TXPACKETS];
- struct list_head packets_list;
-
- /* Total number of transmitted packets. */
- unsigned int nr_tx_packets;
-
- /* Shortcut to the 802.11 core revision. This is to
- * avoid horrible pointer dereferencing in the fastpaths. */
- u8 rev;
-};
-
-struct b43_pio_rxqueue {
- struct b43_wldev *dev;
- spinlock_t lock;
- u16 mmio_base;
-
- /* Work to reduce latency issues on RX. */
- struct work_struct rx_work;
-
- /* Shortcut to the 802.11 core revision. This is to
- * avoid horrible pointer dereferencing in the fastpaths. */
- u8 rev;
-};
-
-
-static inline u16 b43_piotx_read16(struct b43_pio_txqueue *q, u16 offset)
-{
- return b43_read16(q->dev, q->mmio_base + offset);
-}
-
-static inline u32 b43_piotx_read32(struct b43_pio_txqueue *q, u16 offset)
-{
- return b43_read32(q->dev, q->mmio_base + offset);
-}
-
-static inline void b43_piotx_write16(struct b43_pio_txqueue *q,
- u16 offset, u16 value)
-{
- b43_write16(q->dev, q->mmio_base + offset, value);
-}
-
-static inline void b43_piotx_write32(struct b43_pio_txqueue *q,
- u16 offset, u32 value)
-{
- b43_write32(q->dev, q->mmio_base + offset, value);
-}
-
-
-static inline u16 b43_piorx_read16(struct b43_pio_rxqueue *q, u16 offset)
-{
- return b43_read16(q->dev, q->mmio_base + offset);
-}
-
-static inline u32 b43_piorx_read32(struct b43_pio_rxqueue *q, u16 offset)
-{
- return b43_read32(q->dev, q->mmio_base + offset);
-}
-
-static inline void b43_piorx_write16(struct b43_pio_rxqueue *q,
- u16 offset, u16 value)
-{
- b43_write16(q->dev, q->mmio_base + offset, value);
-}
-
-static inline void b43_piorx_write32(struct b43_pio_rxqueue *q,
- u16 offset, u32 value)
-{
- b43_write32(q->dev, q->mmio_base + offset, value);
-}
-
-
-int b43_pio_init(struct b43_wldev *dev);
-void b43_pio_stop(struct b43_wldev *dev);
-void b43_pio_free(struct b43_wldev *dev);
-
-int b43_pio_tx(struct b43_wldev *dev, struct sk_buff *skb);
-void b43_pio_handle_txstatus(struct b43_wldev *dev,
- const struct b43_txstatus *status);
-void b43_pio_get_tx_stats(struct b43_wldev *dev,
- struct ieee80211_tx_queue_stats *stats);
-void b43_pio_rx(struct b43_pio_rxqueue *q);
-
-void b43_pio_tx_suspend(struct b43_wldev *dev);
-void b43_pio_tx_resume(struct b43_wldev *dev);
-
-
-#else /* CONFIG_B43_PIO */
-
-
-static inline int b43_pio_init(struct b43_wldev *dev)
-{
- return 0;
-}
-static inline void b43_pio_free(struct b43_wldev *dev)
-{
-}
-static inline void b43_pio_stop(struct b43_wldev *dev)
-{
-}
-static inline int b43_pio_tx(struct b43_wldev *dev,
- struct sk_buff *skb)
-{
- return 0;
-}
-static inline void b43_pio_handle_txstatus(struct b43_wldev *dev,
- const struct b43_txstatus *status)
-{
-}
-static inline void b43_pio_get_tx_stats(struct b43_wldev *dev,
- struct ieee80211_tx_queue_stats *stats)
-{
-}
-static inline void b43_pio_rx(struct b43_pio_rxqueue *q)
-{
-}
-static inline void b43_pio_tx_suspend(struct b43_wldev *dev)
-{
-}
-static inline void b43_pio_tx_resume(struct b43_wldev *dev)
-{
-}
-
-#endif /* CONFIG_B43_PIO */
-#endif /* B43_PIO_H_ */
-/*
-
- Broadcom B43 wireless driver
- RFKILL support
-
- Copyright (c) 2007 Michael Buesch <mb@bu3sch.de>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; see the file COPYING. If not, write to
- the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
- Boston, MA 02110-1301, USA.
-
-*/
-
-#include "rfkill.h"
-#include "b43.h"
-
-#include <linux/kmod.h>
-
-
-/* Returns TRUE, if the radio is enabled in hardware. */
-static bool b43_is_hw_radio_enabled(struct b43_wldev *dev)
-{
- if (dev->phy.rev >= 3) {
- if (!(b43_read32(dev, B43_MMIO_RADIO_HWENABLED_HI)
- & B43_MMIO_RADIO_HWENABLED_HI_MASK))
- return 1;
- } else {
- if (b43_read16(dev, B43_MMIO_RADIO_HWENABLED_LO)
- & B43_MMIO_RADIO_HWENABLED_LO_MASK)
- return 1;
- }
- return 0;
-}
-
-/* The poll callback for the hardware button. */
-static void b43_rfkill_poll(struct input_polled_dev *poll_dev)
-{
- struct b43_wldev *dev = poll_dev->private;
- struct b43_wl *wl = dev->wl;
- bool enabled;
- bool report_change = 0;
-
- mutex_lock(&wl->mutex);
- if (unlikely(b43_status(dev) < B43_STAT_INITIALIZED)) {
- mutex_unlock(&wl->mutex);
- return;
- }
- enabled = b43_is_hw_radio_enabled(dev);
- if (unlikely(enabled != dev->radio_hw_enable)) {
- dev->radio_hw_enable = enabled;
- report_change = 1;
- b43info(wl, "Radio hardware status changed to %s\n",
- enabled ? "ENABLED" : "DISABLED");
- }
- mutex_unlock(&wl->mutex);
-
- /* send the radio switch event to the system - note both a key press
- * and a release are required */
- if (unlikely(report_change)) {
- input_report_key(poll_dev->input, KEY_WLAN, 1);
- input_report_key(poll_dev->input, KEY_WLAN, 0);
- }
-}
-
-/* Called when the RFKILL toggled in software. */
-static int b43_rfkill_soft_toggle(void *data, enum rfkill_state state)
-{
- struct b43_wldev *dev = data;
- struct b43_wl *wl = dev->wl;
- int err = -EBUSY;
-
- if (!wl->rfkill.registered)
- return 0;
-
- mutex_lock(&wl->mutex);
- if (b43_status(dev) < B43_STAT_INITIALIZED)
- goto out_unlock;
- err = 0;
- switch (state) {
- case RFKILL_STATE_ON:
- if (!dev->radio_hw_enable) {
- /* No luck. We can't toggle the hardware RF-kill
- * button from software. */
- err = -EBUSY;
- goto out_unlock;
- }
- if (!dev->phy.radio_on)
- b43_radio_turn_on(dev);
- break;
- case RFKILL_STATE_OFF:
- if (dev->phy.radio_on)
- b43_radio_turn_off(dev, 0);
- break;
- }
-out_unlock:
- mutex_unlock(&wl->mutex);
-
- return err;
-}
-
-char * b43_rfkill_led_name(struct b43_wldev *dev)
-{
- struct b43_rfkill *rfk = &(dev->wl->rfkill);
-
- if (!rfk->registered)
- return NULL;
- return rfkill_get_led_name(rfk->rfkill);
-}
-
-void b43_rfkill_init(struct b43_wldev *dev)
-{
- struct b43_wl *wl = dev->wl;
- struct b43_rfkill *rfk = &(wl->rfkill);
- int err;
-
- rfk->registered = 0;
-
- rfk->rfkill = rfkill_allocate(dev->dev->dev, RFKILL_TYPE_WLAN);
- if (!rfk->rfkill)
- goto out_error;
- snprintf(rfk->name, sizeof(rfk->name),
- "b43-%s", wiphy_name(wl->hw->wiphy));
- rfk->rfkill->name = rfk->name;
- rfk->rfkill->state = RFKILL_STATE_ON;
- rfk->rfkill->data = dev;
- rfk->rfkill->toggle_radio = b43_rfkill_soft_toggle;
- rfk->rfkill->user_claim_unsupported = 1;
-
- rfk->poll_dev = input_allocate_polled_device();
- if (!rfk->poll_dev) {
- rfkill_free(rfk->rfkill);
- goto err_freed_rfk;
- }
-
- rfk->poll_dev->private = dev;
- rfk->poll_dev->poll = b43_rfkill_poll;
- rfk->poll_dev->poll_interval = 1000; /* msecs */
-
- rfk->poll_dev->input->name = rfk->name;
- rfk->poll_dev->input->id.bustype = BUS_HOST;
- rfk->poll_dev->input->id.vendor = dev->dev->bus->boardinfo.vendor;
- rfk->poll_dev->input->evbit[0] = BIT(EV_KEY);
- set_bit(KEY_WLAN, rfk->poll_dev->input->keybit);
-
- err = rfkill_register(rfk->rfkill);
- if (err)
- goto err_free_polldev;
-
-#ifdef CONFIG_RFKILL_INPUT_MODULE
- /* B43 RF-kill isn't useful without the rfkill-input subsystem.
- * Try to load the module. */
- err = request_module("rfkill-input");
- if (err)
- b43warn(wl, "Failed to load the rfkill-input module. "
- "The built-in radio LED will not work.\n");
-#endif /* CONFIG_RFKILL_INPUT */
-
- err = input_register_polled_device(rfk->poll_dev);
- if (err)
- goto err_unreg_rfk;
-
- rfk->registered = 1;
-
- return;
-err_unreg_rfk:
- rfkill_unregister(rfk->rfkill);
-err_free_polldev:
- input_free_polled_device(rfk->poll_dev);
- rfk->poll_dev = NULL;
-err_freed_rfk:
- rfk->rfkill = NULL;
-out_error:
- rfk->registered = 0;
- b43warn(wl, "RF-kill button init failed\n");
-}
-
-void b43_rfkill_exit(struct b43_wldev *dev)
-{
- struct b43_rfkill *rfk = &(dev->wl->rfkill);
-
- if (!rfk->registered)
- return;
- rfk->registered = 0;
-
- input_unregister_polled_device(rfk->poll_dev);
- rfkill_unregister(rfk->rfkill);
- input_free_polled_device(rfk->poll_dev);
- rfk->poll_dev = NULL;
- rfk->rfkill = NULL;
-}
-#ifndef B43_RFKILL_H_
-#define B43_RFKILL_H_
-
-struct b43_wldev;
-
-
-#ifdef CONFIG_B43_RFKILL
-
-#include <linux/rfkill.h>
-#include <linux/input-polldev.h>
-
-
-struct b43_rfkill {
- /* The RFKILL subsystem data structure */
- struct rfkill *rfkill;
- /* The poll device for the RFKILL input button */
- struct input_polled_dev *poll_dev;
- /* Did initialization succeed? Used for freeing. */
- bool registered;
- /* The unique name of this rfkill switch */
- char name[sizeof("b43-phy4294967295")];
-};
-
-/* The init function returns void, because we are not interested
- * in failing the b43 init process when rfkill init failed. */
-void b43_rfkill_init(struct b43_wldev *dev);
-void b43_rfkill_exit(struct b43_wldev *dev);
-
-char * b43_rfkill_led_name(struct b43_wldev *dev);
-
-
-#else /* CONFIG_B43_RFKILL */
-/* No RFKILL support. */
-
-struct b43_rfkill {
- /* empty */
-};
-
-static inline void b43_rfkill_init(struct b43_wldev *dev)
-{
-}
-static inline void b43_rfkill_exit(struct b43_wldev *dev)
-{
-}
-static inline char * b43_rfkill_led_name(struct b43_wldev *dev)
-{
- return NULL;
-}
-
-#endif /* CONFIG_B43_RFKILL */
-
-#endif /* B43_RFKILL_H_ */
-/*
-
- Broadcom B43 wireless driver
-
- SYSFS support routines
-
- Copyright (c) 2006 Michael Buesch <mb@bu3sch.de>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; see the file COPYING. If not, write to
- the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
- Boston, MA 02110-1301, USA.
-
-*/
-
-#include <linux/capability.h>
-#include <linux/io.h>
-
-#include "b43.h"
-#include "sysfs.h"
-#include "main.h"
-#include "phy.h"
-
-#define GENERIC_FILESIZE 64
-
-static int get_integer(const char *buf, size_t count)
-{
- char tmp[10 + 1] = { 0 };
- int ret = -EINVAL;
-
- if (count == 0)
- goto out;
- count = min(count, (size_t) 10);
- memcpy(tmp, buf, count);
- ret = simple_strtol(tmp, NULL, 10);
- out:
- return ret;
-}
-
-static ssize_t b43_attr_interfmode_show(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct b43_wldev *wldev = dev_to_b43_wldev(dev);
- ssize_t count = 0;
-
- if (!capable(CAP_NET_ADMIN))
- return -EPERM;
-
- mutex_lock(&wldev->wl->mutex);
-
- switch (wldev->phy.interfmode) {
- case B43_INTERFMODE_NONE:
- count =
- snprintf(buf, PAGE_SIZE,
- "0 (No Interference Mitigation)\n");
- break;
- case B43_INTERFMODE_NONWLAN:
- count =
- snprintf(buf, PAGE_SIZE,
- "1 (Non-WLAN Interference Mitigation)\n");
- break;
- case B43_INTERFMODE_MANUALWLAN:
- count =
- snprintf(buf, PAGE_SIZE,
- "2 (WLAN Interference Mitigation)\n");
- break;
- default:
- B43_WARN_ON(1);
- }
-
- mutex_unlock(&wldev->wl->mutex);
-
- return count;
-}
-
-static ssize_t b43_attr_interfmode_store(struct device *dev,
- struct device_attribute *attr,
- const char *buf, size_t count)
-{
- struct b43_wldev *wldev = dev_to_b43_wldev(dev);
- unsigned long flags;
- int err;
- int mode;
-
- if (!capable(CAP_NET_ADMIN))
- return -EPERM;
-
- mode = get_integer(buf, count);
- switch (mode) {
- case 0:
- mode = B43_INTERFMODE_NONE;
- break;
- case 1:
- mode = B43_INTERFMODE_NONWLAN;
- break;
- case 2:
- mode = B43_INTERFMODE_MANUALWLAN;
- break;
- case 3:
- mode = B43_INTERFMODE_AUTOWLAN;
- break;
- default:
- return -EINVAL;
- }
-
- mutex_lock(&wldev->wl->mutex);
- spin_lock_irqsave(&wldev->wl->irq_lock, flags);
-
- err = b43_radio_set_interference_mitigation(wldev, mode);
- if (err) {
- b43err(wldev->wl, "Interference Mitigation not "
- "supported by device\n");
- }
- mmiowb();
- spin_unlock_irqrestore(&wldev->wl->irq_lock, flags);
- mutex_unlock(&wldev->wl->mutex);
-
- return err ? err : count;
-}
-
-static DEVICE_ATTR(interference, 0644,
- b43_attr_interfmode_show, b43_attr_interfmode_store);
-
-int b43_sysfs_register(struct b43_wldev *wldev)
-{
- struct device *dev = wldev->dev->dev;
-
- B43_WARN_ON(b43_status(wldev) != B43_STAT_INITIALIZED);
-
- return device_create_file(dev, &dev_attr_interference);
-}
-
-void b43_sysfs_unregister(struct b43_wldev *wldev)
-{
- struct device *dev = wldev->dev->dev;
-
- device_remove_file(dev, &dev_attr_interference);
-}
-#ifndef B43_SYSFS_H_
-#define B43_SYSFS_H_
-
-struct b43_wldev;
-
-int b43_sysfs_register(struct b43_wldev *dev);
-void b43_sysfs_unregister(struct b43_wldev *dev);
-
-#endif /* B43_SYSFS_H_ */
-/*
-
- Broadcom B43 wireless driver
-
- Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
- Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
- Copyright (c) 2006, 2006 Michael Buesch <mb@bu3sch.de>
- Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
- Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; see the file COPYING. If not, write to
- the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
- Boston, MA 02110-1301, USA.
-
-*/
-
-#include "b43.h"
-#include "tables.h"
-#include "phy.h"
-
-const u32 b43_tab_rotor[] = {
- 0xFEB93FFD, 0xFEC63FFD, /* 0 */
- 0xFED23FFD, 0xFEDF3FFD,
- 0xFEEC3FFE, 0xFEF83FFE,
- 0xFF053FFE, 0xFF113FFE,
- 0xFF1E3FFE, 0xFF2A3FFF, /* 8 */
- 0xFF373FFF, 0xFF443FFF,
- 0xFF503FFF, 0xFF5D3FFF,
- 0xFF693FFF, 0xFF763FFF,
- 0xFF824000, 0xFF8F4000, /* 16 */
- 0xFF9B4000, 0xFFA84000,
- 0xFFB54000, 0xFFC14000,
- 0xFFCE4000, 0xFFDA4000,
- 0xFFE74000, 0xFFF34000, /* 24 */
- 0x00004000, 0x000D4000,
- 0x00194000, 0x00264000,
- 0x00324000, 0x003F4000,
- 0x004B4000, 0x00584000, /* 32 */
- 0x00654000, 0x00714000,
- 0x007E4000, 0x008A3FFF,
- 0x00973FFF, 0x00A33FFF,
- 0x00B03FFF, 0x00BC3FFF, /* 40 */
- 0x00C93FFF, 0x00D63FFF,
- 0x00E23FFE, 0x00EF3FFE,
- 0x00FB3FFE, 0x01083FFE,
- 0x01143FFE, 0x01213FFD, /* 48 */
- 0x012E3FFD, 0x013A3FFD,
- 0x01473FFD,
-};
-
-const u32 b43_tab_retard[] = {
- 0xDB93CB87, 0xD666CF64, /* 0 */
- 0xD1FDD358, 0xCDA6D826,
- 0xCA38DD9F, 0xC729E2B4,
- 0xC469E88E, 0xC26AEE2B,
- 0xC0DEF46C, 0xC073FA62, /* 8 */
- 0xC01D00D5, 0xC0760743,
- 0xC1560D1E, 0xC2E51369,
- 0xC4ED18FF, 0xC7AC1ED7,
- 0xCB2823B2, 0xCEFA28D9, /* 16 */
- 0xD2F62D3F, 0xD7BB3197,
- 0xDCE53568, 0xE1FE3875,
- 0xE7D13B35, 0xED663D35,
- 0xF39B3EC4, 0xF98E3FA7, /* 24 */
- 0x00004000, 0x06723FA7,
- 0x0C653EC4, 0x129A3D35,
- 0x182F3B35, 0x1E023875,
- 0x231B3568, 0x28453197, /* 32 */
- 0x2D0A2D3F, 0x310628D9,
- 0x34D823B2, 0x38541ED7,
- 0x3B1318FF, 0x3D1B1369,
- 0x3EAA0D1E, 0x3F8A0743, /* 40 */
- 0x3FE300D5, 0x3F8DFA62,
- 0x3F22F46C, 0x3D96EE2B,
- 0x3B97E88E, 0x38D7E2B4,
- 0x35C8DD9F, 0x325AD826, /* 48 */
- 0x2E03D358, 0x299ACF64,
- 0x246DCB87,
-};
-
-const u16 b43_tab_finefreqa[] = {
- 0x0082, 0x0082, 0x0102, 0x0182, /* 0 */
- 0x0202, 0x0282, 0x0302, 0x0382,
- 0x0402, 0x0482, 0x0502, 0x0582,
- 0x05E2, 0x0662, 0x06E2, 0x0762,
- 0x07E2, 0x0842, 0x08C2, 0x0942, /* 16 */
- 0x09C2, 0x0A22, 0x0AA2, 0x0B02,
- 0x0B82, 0x0BE2, 0x0C62, 0x0CC2,
- 0x0D42, 0x0DA2, 0x0E02, 0x0E62,
- 0x0EE2, 0x0F42, 0x0FA2, 0x1002, /* 32 */
- 0x1062, 0x10C2, 0x1122, 0x1182,
- 0x11E2, 0x1242, 0x12A2, 0x12E2,
- 0x1342, 0x13A2, 0x1402, 0x1442,
- 0x14A2, 0x14E2, 0x1542, 0x1582, /* 48 */
- 0x15E2, 0x1622, 0x1662, 0x16C1,
- 0x1701, 0x1741, 0x1781, 0x17E1,
- 0x1821, 0x1861, 0x18A1, 0x18E1,
- 0x1921, 0x1961, 0x19A1, 0x19E1, /* 64 */
- 0x1A21, 0x1A61, 0x1AA1, 0x1AC1,
- 0x1B01, 0x1B41, 0x1B81, 0x1BA1,
- 0x1BE1, 0x1C21, 0x1C41, 0x1C81,
- 0x1CA1, 0x1CE1, 0x1D01, 0x1D41, /* 80 */
- 0x1D61, 0x1DA1, 0x1DC1, 0x1E01,
- 0x1E21, 0x1E61, 0x1E81, 0x1EA1,
- 0x1EE1, 0x1F01, 0x1F21, 0x1F41,
- 0x1F81, 0x1FA1, 0x1FC1, 0x1FE1, /* 96 */
- 0x2001, 0x2041, 0x2061, 0x2081,
- 0x20A1, 0x20C1, 0x20E1, 0x2101,
- 0x2121, 0x2141, 0x2161, 0x2181,
- 0x21A1, 0x21C1, 0x21E1, 0x2201, /* 112 */
- 0x2221, 0x2241, 0x2261, 0x2281,
- 0x22A1, 0x22C1, 0x22C1, 0x22E1,
- 0x2301, 0x2321, 0x2341, 0x2361,
- 0x2361, 0x2381, 0x23A1, 0x23C1, /* 128 */
- 0x23E1, 0x23E1, 0x2401, 0x2421,
- 0x2441, 0x2441, 0x2461, 0x2481,
- 0x2481, 0x24A1, 0x24C1, 0x24C1,
- 0x24E1, 0x2501, 0x2501, 0x2521, /* 144 */
- 0x2541, 0x2541, 0x2561, 0x2561,
- 0x2581, 0x25A1, 0x25A1, 0x25C1,
- 0x25C1, 0x25E1, 0x2601, 0x2601,
- 0x2621, 0x2621, 0x2641, 0x2641, /* 160 */
- 0x2661, 0x2661, 0x2681, 0x2681,
- 0x26A1, 0x26A1, 0x26C1, 0x26C1,
- 0x26E1, 0x26E1, 0x2701, 0x2701,
- 0x2721, 0x2721, 0x2740, 0x2740, /* 176 */
- 0x2760, 0x2760, 0x2780, 0x2780,
- 0x2780, 0x27A0, 0x27A0, 0x27C0,
- 0x27C0, 0x27E0, 0x27E0, 0x27E0,
- 0x2800, 0x2800, 0x2820, 0x2820, /* 192 */
- 0x2820, 0x2840, 0x2840, 0x2840,
- 0x2860, 0x2860, 0x2880, 0x2880,
- 0x2880, 0x28A0, 0x28A0, 0x28A0,
- 0x28C0, 0x28C0, 0x28C0, 0x28E0, /* 208 */
- 0x28E0, 0x28E0, 0x2900, 0x2900,
- 0x2900, 0x2920, 0x2920, 0x2920,
- 0x2940, 0x2940, 0x2940, 0x2960,
- 0x2960, 0x2960, 0x2960, 0x2980, /* 224 */
- 0x2980, 0x2980, 0x29A0, 0x29A0,
- 0x29A0, 0x29A0, 0x29C0, 0x29C0,
- 0x29C0, 0x29E0, 0x29E0, 0x29E0,
- 0x29E0, 0x2A00, 0x2A00, 0x2A00, /* 240 */
- 0x2A00, 0x2A20, 0x2A20, 0x2A20,
- 0x2A20, 0x2A40, 0x2A40, 0x2A40,
- 0x2A40, 0x2A60, 0x2A60, 0x2A60,
-};
-
-const u16 b43_tab_finefreqg[] = {
- 0x0089, 0x02E9, 0x0409, 0x04E9, /* 0 */
- 0x05A9, 0x0669, 0x0709, 0x0789,
- 0x0829, 0x08A9, 0x0929, 0x0989,
- 0x0A09, 0x0A69, 0x0AC9, 0x0B29,
- 0x0BA9, 0x0BE9, 0x0C49, 0x0CA9, /* 16 */
- 0x0D09, 0x0D69, 0x0DA9, 0x0E09,
- 0x0E69, 0x0EA9, 0x0F09, 0x0F49,
- 0x0FA9, 0x0FE9, 0x1029, 0x1089,
- 0x10C9, 0x1109, 0x1169, 0x11A9, /* 32 */
- 0x11E9, 0x1229, 0x1289, 0x12C9,
- 0x1309, 0x1349, 0x1389, 0x13C9,
- 0x1409, 0x1449, 0x14A9, 0x14E9,
- 0x1529, 0x1569, 0x15A9, 0x15E9, /* 48 */
- 0x1629, 0x1669, 0x16A9, 0x16E8,
- 0x1728, 0x1768, 0x17A8, 0x17E8,
- 0x1828, 0x1868, 0x18A8, 0x18E8,
- 0x1928, 0x1968, 0x19A8, 0x19E8, /* 64 */
- 0x1A28, 0x1A68, 0x1AA8, 0x1AE8,
- 0x1B28, 0x1B68, 0x1BA8, 0x1BE8,
- 0x1C28, 0x1C68, 0x1CA8, 0x1CE8,
- 0x1D28, 0x1D68, 0x1DC8, 0x1E08, /* 80 */
- 0x1E48, 0x1E88, 0x1EC8, 0x1F08,
- 0x1F48, 0x1F88, 0x1FE8, 0x2028,
- 0x2068, 0x20A8, 0x2108, 0x2148,
- 0x2188, 0x21C8, 0x2228, 0x2268, /* 96 */
- 0x22C8, 0x2308, 0x2348, 0x23A8,
- 0x23E8, 0x2448, 0x24A8, 0x24E8,
- 0x2548, 0x25A8, 0x2608, 0x2668,
- 0x26C8, 0x2728, 0x2787, 0x27E7, /* 112 */
- 0x2847, 0x28C7, 0x2947, 0x29A7,
- 0x2A27, 0x2AC7, 0x2B47, 0x2BE7,
- 0x2CA7, 0x2D67, 0x2E47, 0x2F67,
- 0x3247, 0x3526, 0x3646, 0x3726, /* 128 */
- 0x3806, 0x38A6, 0x3946, 0x39E6,
- 0x3A66, 0x3AE6, 0x3B66, 0x3BC6,
- 0x3C45, 0x3CA5, 0x3D05, 0x3D85,
- 0x3DE5, 0x3E45, 0x3EA5, 0x3EE5, /* 144 */
- 0x3F45, 0x3FA5, 0x4005, 0x4045,
- 0x40A5, 0x40E5, 0x4145, 0x4185,
- 0x41E5, 0x4225, 0x4265, 0x42C5,
- 0x4305, 0x4345, 0x43A5, 0x43E5, /* 160 */
- 0x4424, 0x4464, 0x44C4, 0x4504,
- 0x4544, 0x4584, 0x45C4, 0x4604,
- 0x4644, 0x46A4, 0x46E4, 0x4724,
- 0x4764, 0x47A4, 0x47E4, 0x4824, /* 176 */
- 0x4864, 0x48A4, 0x48E4, 0x4924,
- 0x4964, 0x49A4, 0x49E4, 0x4A24,
- 0x4A64, 0x4AA4, 0x4AE4, 0x4B23,
- 0x4B63, 0x4BA3, 0x4BE3, 0x4C23, /* 192 */
- 0x4C63, 0x4CA3, 0x4CE3, 0x4D23,
- 0x4D63, 0x4DA3, 0x4DE3, 0x4E23,
- 0x4E63, 0x4EA3, 0x4EE3, 0x4F23,
- 0x4F63, 0x4FC3, 0x5003, 0x5043, /* 208 */
- 0x5083, 0x50C3, 0x5103, 0x5143,
- 0x5183, 0x51E2, 0x5222, 0x5262,
- 0x52A2, 0x52E2, 0x5342, 0x5382,
- 0x53C2, 0x5402, 0x5462, 0x54A2, /* 224 */
- 0x5502, 0x5542, 0x55A2, 0x55E2,
- 0x5642, 0x5682, 0x56E2, 0x5722,
- 0x5782, 0x57E1, 0x5841, 0x58A1,
- 0x5901, 0x5961, 0x59C1, 0x5A21, /* 240 */
- 0x5AA1, 0x5B01, 0x5B81, 0x5BE1,
- 0x5C61, 0x5D01, 0x5D80, 0x5E20,
- 0x5EE0, 0x5FA0, 0x6080, 0x61C0,
-};
-
-const u16 b43_tab_noisea2[] = {
- 0x0001, 0x0001, 0x0001, 0xFFFE,
- 0xFFFE, 0x3FFF, 0x1000, 0x0393,
-};
-
-const u16 b43_tab_noisea3[] = {
- 0x5E5E, 0x5E5E, 0x5E5E, 0x3F48,
- 0x4C4C, 0x4C4C, 0x4C4C, 0x2D36,
-};
-
-const u16 b43_tab_noiseg1[] = {
- 0x013C, 0x01F5, 0x031A, 0x0631,
- 0x0001, 0x0001, 0x0001, 0x0001,
-};
-
-const u16 b43_tab_noiseg2[] = {
- 0x5484, 0x3C40, 0x0000, 0x0000,
- 0x0000, 0x0000, 0x0000, 0x0000,
-};
-
-const u16 b43_tab_noisescalea2[] = {
- 0x6767, 0x6767, 0x6767, 0x6767, /* 0 */
- 0x6767, 0x6767, 0x6767, 0x6767,
- 0x6767, 0x6767, 0x6767, 0x6767,
- 0x6767, 0x6700, 0x6767, 0x6767,
- 0x6767, 0x6767, 0x6767, 0x6767, /* 16 */
- 0x6767, 0x6767, 0x6767, 0x6767,
- 0x6767, 0x6767, 0x0067,
-};
-
-const u16 b43_tab_noisescalea3[] = {
- 0x2323, 0x2323, 0x2323, 0x2323, /* 0 */
- 0x2323, 0x2323, 0x2323, 0x2323,
- 0x2323, 0x2323, 0x2323, 0x2323,
- 0x2323, 0x2300, 0x2323, 0x2323,
- 0x2323, 0x2323, 0x2323, 0x2323, /* 16 */
- 0x2323, 0x2323, 0x2323, 0x2323,
- 0x2323, 0x2323, 0x0023,
-};
-
-const u16 b43_tab_noisescaleg1[] = {
- 0x6C77, 0x5162, 0x3B40, 0x3335, /* 0 */
- 0x2F2D, 0x2A2A, 0x2527, 0x1F21,
- 0x1A1D, 0x1719, 0x1616, 0x1414,
- 0x1414, 0x1400, 0x1414, 0x1614,
- 0x1716, 0x1A19, 0x1F1D, 0x2521, /* 16 */
- 0x2A27, 0x2F2A, 0x332D, 0x3B35,
- 0x5140, 0x6C62, 0x0077,
-};
-
-const u16 b43_tab_noisescaleg2[] = {
- 0xD8DD, 0xCBD4, 0xBCC0, 0xB6B7, /* 0 */
- 0xB2B0, 0xADAD, 0xA7A9, 0x9FA1,
- 0x969B, 0x9195, 0x8F8F, 0x8A8A,
- 0x8A8A, 0x8A00, 0x8A8A, 0x8F8A,
- 0x918F, 0x9695, 0x9F9B, 0xA7A1, /* 16 */
- 0xADA9, 0xB2AD, 0xB6B0, 0xBCB7,
- 0xCBC0, 0xD8D4, 0x00DD,
-};
-
-const u16 b43_tab_noisescaleg3[] = {
- 0xA4A4, 0xA4A4, 0xA4A4, 0xA4A4, /* 0 */
- 0xA4A4, 0xA4A4, 0xA4A4, 0xA4A4,
- 0xA4A4, 0xA4A4, 0xA4A4, 0xA4A4,
- 0xA4A4, 0xA400, 0xA4A4, 0xA4A4,
- 0xA4A4, 0xA4A4, 0xA4A4, 0xA4A4, /* 16 */
- 0xA4A4, 0xA4A4, 0xA4A4, 0xA4A4,
- 0xA4A4, 0xA4A4, 0x00A4,
-};
-
-const u16 b43_tab_sigmasqr1[] = {
- 0x007A, 0x0075, 0x0071, 0x006C, /* 0 */
- 0x0067, 0x0063, 0x005E, 0x0059,
- 0x0054, 0x0050, 0x004B, 0x0046,
- 0x0042, 0x003D, 0x003D, 0x003D,
- 0x003D, 0x003D, 0x003D, 0x003D, /* 16 */
- 0x003D, 0x003D, 0x003D, 0x003D,
- 0x003D, 0x003D, 0x0000, 0x003D,
- 0x003D, 0x003D, 0x003D, 0x003D,
- 0x003D, 0x003D, 0x003D, 0x003D, /* 32 */
- 0x003D, 0x003D, 0x003D, 0x003D,
- 0x0042, 0x0046, 0x004B, 0x0050,
- 0x0054, 0x0059, 0x005E, 0x0063,
- 0x0067, 0x006C, 0x0071, 0x0075, /* 48 */
- 0x007A,
-};
-
-const u16 b43_tab_sigmasqr2[] = {
- 0x00DE, 0x00DC, 0x00DA, 0x00D8, /* 0 */
- 0x00D6, 0x00D4, 0x00D2, 0x00CF,
- 0x00CD, 0x00CA, 0x00C7, 0x00C4,
- 0x00C1, 0x00BE, 0x00BE, 0x00BE,
- 0x00BE, 0x00BE, 0x00BE, 0x00BE, /* 16 */
- 0x00BE, 0x00BE, 0x00BE, 0x00BE,
- 0x00BE, 0x00BE, 0x0000, 0x00BE,
- 0x00BE, 0x00BE, 0x00BE, 0x00BE,
- 0x00BE, 0x00BE, 0x00BE, 0x00BE, /* 32 */
- 0x00BE, 0x00BE, 0x00BE, 0x00BE,
- 0x00C1, 0x00C4, 0x00C7, 0x00CA,
- 0x00CD, 0x00CF, 0x00D2, 0x00D4,
- 0x00D6, 0x00D8, 0x00DA, 0x00DC, /* 48 */
- 0x00DE,
-};
-
-const u16 b43_tab_rssiagc1[] = {
- 0xFFF8, 0xFFF8, 0xFFF8, 0xFFF8, /* 0 */
- 0xFFF8, 0xFFF9, 0xFFFC, 0xFFFE,
- 0xFFF8, 0xFFF8, 0xFFF8, 0xFFF8,
- 0xFFF8, 0xFFF8, 0xFFF8, 0xFFF8,
-};
-
-const u16 b43_tab_rssiagc2[] = {
- 0x0820, 0x0820, 0x0920, 0x0C38, /* 0 */
- 0x0820, 0x0820, 0x0820, 0x0820,
- 0x0820, 0x0820, 0x0920, 0x0A38,
- 0x0820, 0x0820, 0x0820, 0x0820,
- 0x0820, 0x0820, 0x0920, 0x0A38, /* 16 */
- 0x0820, 0x0820, 0x0820, 0x0820,
- 0x0820, 0x0820, 0x0920, 0x0A38,
- 0x0820, 0x0820, 0x0820, 0x0820,
- 0x0820, 0x0820, 0x0920, 0x0A38, /* 32 */
- 0x0820, 0x0820, 0x0820, 0x0820,
- 0x0820, 0x0820, 0x0920, 0x0A38,
- 0x0820, 0x0820, 0x0820, 0x0820,
-};
-
-static inline void assert_sizes(void)
-{
- BUILD_BUG_ON(B43_TAB_ROTOR_SIZE != ARRAY_SIZE(b43_tab_rotor));
- BUILD_BUG_ON(B43_TAB_RETARD_SIZE != ARRAY_SIZE(b43_tab_retard));
- BUILD_BUG_ON(B43_TAB_FINEFREQA_SIZE != ARRAY_SIZE(b43_tab_finefreqa));
- BUILD_BUG_ON(B43_TAB_FINEFREQG_SIZE != ARRAY_SIZE(b43_tab_finefreqg));
- BUILD_BUG_ON(B43_TAB_NOISEA2_SIZE != ARRAY_SIZE(b43_tab_noisea2));
- BUILD_BUG_ON(B43_TAB_NOISEA3_SIZE != ARRAY_SIZE(b43_tab_noisea3));
- BUILD_BUG_ON(B43_TAB_NOISEG1_SIZE != ARRAY_SIZE(b43_tab_noiseg1));
- BUILD_BUG_ON(B43_TAB_NOISEG2_SIZE != ARRAY_SIZE(b43_tab_noiseg2));
- BUILD_BUG_ON(B43_TAB_NOISESCALE_SIZE !=
- ARRAY_SIZE(b43_tab_noisescalea2));
- BUILD_BUG_ON(B43_TAB_NOISESCALE_SIZE !=
- ARRAY_SIZE(b43_tab_noisescalea3));
- BUILD_BUG_ON(B43_TAB_NOISESCALE_SIZE !=
- ARRAY_SIZE(b43_tab_noisescaleg1));
- BUILD_BUG_ON(B43_TAB_NOISESCALE_SIZE !=
- ARRAY_SIZE(b43_tab_noisescaleg2));
- BUILD_BUG_ON(B43_TAB_NOISESCALE_SIZE !=
- ARRAY_SIZE(b43_tab_noisescaleg3));
- BUILD_BUG_ON(B43_TAB_SIGMASQR_SIZE != ARRAY_SIZE(b43_tab_sigmasqr1));
- BUILD_BUG_ON(B43_TAB_SIGMASQR_SIZE != ARRAY_SIZE(b43_tab_sigmasqr2));
- BUILD_BUG_ON(B43_TAB_RSSIAGC1_SIZE != ARRAY_SIZE(b43_tab_rssiagc1));
- BUILD_BUG_ON(B43_TAB_RSSIAGC2_SIZE != ARRAY_SIZE(b43_tab_rssiagc2));
-}
-
-u16 b43_ofdmtab_read16(struct b43_wldev *dev, u16 table, u16 offset)
-{
- struct b43_phy *phy = &dev->phy;
- u16 addr;
-
- addr = table + offset;
- if ((phy->ofdmtab_addr_direction != B43_OFDMTAB_DIRECTION_READ) ||
- (addr - 1 != phy->ofdmtab_addr)) {
- /* The hardware has a different address in memory. Update it. */
- b43_phy_write(dev, B43_PHY_OTABLECTL, addr);
- phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_READ;
- }
- phy->ofdmtab_addr = addr;
-
- return b43_phy_read(dev, B43_PHY_OTABLEI);
-
- /* Some compiletime assertions... */
- assert_sizes();
-}
-
-void b43_ofdmtab_write16(struct b43_wldev *dev, u16 table,
- u16 offset, u16 value)
-{
- struct b43_phy *phy = &dev->phy;
- u16 addr;
-
- addr = table + offset;
- if ((phy->ofdmtab_addr_direction != B43_OFDMTAB_DIRECTION_WRITE) ||
- (addr - 1 != phy->ofdmtab_addr)) {
- /* The hardware has a different address in memory. Update it. */
- b43_phy_write(dev, B43_PHY_OTABLECTL, addr);
- phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_WRITE;
- }
- phy->ofdmtab_addr = addr;
- b43_phy_write(dev, B43_PHY_OTABLEI, value);
-}
-
-u32 b43_ofdmtab_read32(struct b43_wldev *dev, u16 table, u16 offset)
-{
- struct b43_phy *phy = &dev->phy;
- u32 ret;
- u16 addr;
-
- addr = table + offset;
- if ((phy->ofdmtab_addr_direction != B43_OFDMTAB_DIRECTION_READ) ||
- (addr - 1 != phy->ofdmtab_addr)) {
- /* The hardware has a different address in memory. Update it. */
- b43_phy_write(dev, B43_PHY_OTABLECTL, addr);
- phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_READ;
- }
- phy->ofdmtab_addr = addr;
- ret = b43_phy_read(dev, B43_PHY_OTABLEQ);
- ret <<= 16;
- ret |= b43_phy_read(dev, B43_PHY_OTABLEI);
-
- return ret;
-}
-
-void b43_ofdmtab_write32(struct b43_wldev *dev, u16 table,
- u16 offset, u32 value)
-{
- struct b43_phy *phy = &dev->phy;
- u16 addr;
-
- addr = table + offset;
- if ((phy->ofdmtab_addr_direction != B43_OFDMTAB_DIRECTION_WRITE) ||
- (addr - 1 != phy->ofdmtab_addr)) {
- /* The hardware has a different address in memory. Update it. */
- b43_phy_write(dev, B43_PHY_OTABLECTL, addr);
- phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_WRITE;
- }
- phy->ofdmtab_addr = addr;
-
- b43_phy_write(dev, B43_PHY_OTABLEI, value);
- b43_phy_write(dev, B43_PHY_OTABLEQ, (value >> 16));
-}
-
-u16 b43_gtab_read(struct b43_wldev *dev, u16 table, u16 offset)
-{
- b43_phy_write(dev, B43_PHY_GTABCTL, table + offset);
- return b43_phy_read(dev, B43_PHY_GTABDATA);
-}
-
-void b43_gtab_write(struct b43_wldev *dev, u16 table, u16 offset, u16 value)
-{
- b43_phy_write(dev, B43_PHY_GTABCTL, table + offset);
- b43_phy_write(dev, B43_PHY_GTABDATA, value);
-}
-#ifndef B43_TABLES_H_
-#define B43_TABLES_H_
-
-#define B43_TAB_ROTOR_SIZE 53
-extern const u32 b43_tab_rotor[];
-#define B43_TAB_RETARD_SIZE 53
-extern const u32 b43_tab_retard[];
-#define B43_TAB_FINEFREQA_SIZE 256
-extern const u16 b43_tab_finefreqa[];
-#define B43_TAB_FINEFREQG_SIZE 256
-extern const u16 b43_tab_finefreqg[];
-#define B43_TAB_NOISEA2_SIZE 8
-extern const u16 b43_tab_noisea2[];
-#define B43_TAB_NOISEA3_SIZE 8
-extern const u16 b43_tab_noisea3[];
-#define B43_TAB_NOISEG1_SIZE 8
-extern const u16 b43_tab_noiseg1[];
-#define B43_TAB_NOISEG2_SIZE 8
-extern const u16 b43_tab_noiseg2[];
-#define B43_TAB_NOISESCALE_SIZE 27
-extern const u16 b43_tab_noisescalea2[];
-extern const u16 b43_tab_noisescalea3[];
-extern const u16 b43_tab_noisescaleg1[];
-extern const u16 b43_tab_noisescaleg2[];
-extern const u16 b43_tab_noisescaleg3[];
-#define B43_TAB_SIGMASQR_SIZE 53
-extern const u16 b43_tab_sigmasqr1[];
-extern const u16 b43_tab_sigmasqr2[];
-#define B43_TAB_RSSIAGC1_SIZE 16
-extern const u16 b43_tab_rssiagc1[];
-#define B43_TAB_RSSIAGC2_SIZE 48
-extern const u16 b43_tab_rssiagc2[];
-
-#endif /* B43_TABLES_H_ */
-/*
-
- Broadcom B43 wireless driver
- IEEE 802.11n PHY and radio device data tables
-
- Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; see the file COPYING. If not, write to
- the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
- Boston, MA 02110-1301, USA.
-
-*/
-
-#include "b43.h"
-#include "tables_nphy.h"
-#include "phy.h"
-#include "nphy.h"
-
-
-struct b2055_inittab_entry {
- /* Value to write if we use the 5GHz band. */
- u16 ghz5;
- /* Value to write if we use the 2.4GHz band. */
- u16 ghz2;
- /* Flags */
- u8 flags;
-#define B2055_INITTAB_ENTRY_OK 0x01
-#define B2055_INITTAB_UPLOAD 0x02
-};
-#define UPLOAD .flags = B2055_INITTAB_ENTRY_OK | B2055_INITTAB_UPLOAD
-#define NOUPLOAD .flags = B2055_INITTAB_ENTRY_OK
-
-static const struct b2055_inittab_entry b2055_inittab [] = {
- [B2055_SP_PINPD] = { .ghz5 = 0x0080, .ghz2 = 0x0080, NOUPLOAD, },
- [B2055_C1_SP_RSSI] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_C1_SP_PDMISC] = { .ghz5 = 0x0027, .ghz2 = 0x0027, NOUPLOAD, },
- [B2055_C2_SP_RSSI] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_C2_SP_PDMISC] = { .ghz5 = 0x0027, .ghz2 = 0x0027, NOUPLOAD, },
- [B2055_C1_SP_RXGC1] = { .ghz5 = 0x007F, .ghz2 = 0x007F, UPLOAD, },
- [B2055_C1_SP_RXGC2] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, },
- [B2055_C2_SP_RXGC1] = { .ghz5 = 0x007F, .ghz2 = 0x007F, UPLOAD, },
- [B2055_C2_SP_RXGC2] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, },
- [B2055_C1_SP_LPFBWSEL] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
- [B2055_C2_SP_LPFBWSEL] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
- [B2055_C1_SP_TXGC1] = { .ghz5 = 0x004F, .ghz2 = 0x004F, UPLOAD, },
- [B2055_C1_SP_TXGC2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, UPLOAD, },
- [B2055_C2_SP_TXGC1] = { .ghz5 = 0x004F, .ghz2 = 0x004F, UPLOAD, },
- [B2055_C2_SP_TXGC2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, UPLOAD, },
- [B2055_MASTER1] = { .ghz5 = 0x00D0, .ghz2 = 0x00D0, NOUPLOAD, },
- [B2055_MASTER2] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
- [B2055_PD_LGEN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_PD_PLLTS] = { .ghz5 = 0x0040, .ghz2 = 0x0040, NOUPLOAD, },
- [B2055_C1_PD_LGBUF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_C1_PD_TX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_C1_PD_RXTX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_C1_PD_RSSIMISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_C2_PD_LGBUF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_C2_PD_TX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_C2_PD_RXTX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_C2_PD_RSSIMISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_PWRDET_LGEN] = { .ghz5 = 0x00C0, .ghz2 = 0x00C0, NOUPLOAD, },
- [B2055_C1_PWRDET_LGBUF] = { .ghz5 = 0x00FF, .ghz2 = 0x00FF, NOUPLOAD, },
- [B2055_C1_PWRDET_RXTX] = { .ghz5 = 0x00C0, .ghz2 = 0x00C0, NOUPLOAD, },
- [B2055_C2_PWRDET_LGBUF] = { .ghz5 = 0x00FF, .ghz2 = 0x00FF, NOUPLOAD, },
- [B2055_C2_PWRDET_RXTX] = { .ghz5 = 0x00C0, .ghz2 = 0x00C0, NOUPLOAD, },
- [B2055_RRCCAL_CS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_RRCCAL_NOPTSEL] = { .ghz5 = 0x002C, .ghz2 = 0x002C, NOUPLOAD, },
- [B2055_CAL_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_CAL_COUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_CAL_COUT2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_CAL_CVARCTL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_CAL_RVARCTL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_CAL_LPOCTL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_CAL_TS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_CAL_RCCALRTS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_CAL_RCALRTS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_PADDRV] = { .ghz5 = 0x00A4, .ghz2 = 0x00A4, NOUPLOAD, },
- [B2055_XOCTL1] = { .ghz5 = 0x0038, .ghz2 = 0x0038, NOUPLOAD, },
- [B2055_XOCTL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_XOREGUL] = { .ghz5 = 0x0004, .ghz2 = 0x0004, UPLOAD, },
- [B2055_XOMISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_PLL_LFC1] = { .ghz5 = 0x000A, .ghz2 = 0x000A, NOUPLOAD, },
- [B2055_PLL_CALVTH] = { .ghz5 = 0x0087, .ghz2 = 0x0087, NOUPLOAD, },
- [B2055_PLL_LFC2] = { .ghz5 = 0x0009, .ghz2 = 0x0009, NOUPLOAD, },
- [B2055_PLL_REF] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, },
- [B2055_PLL_LFR1] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, },
- [B2055_PLL_PFDCP] = { .ghz5 = 0x0018, .ghz2 = 0x0018, UPLOAD, },
- [B2055_PLL_IDAC_CPOPAMP] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
- [B2055_PLL_CPREG] = { .ghz5 = 0x0004, .ghz2 = 0x0004, UPLOAD, },
- [B2055_PLL_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
- [B2055_RF_PLLMOD0] = { .ghz5 = 0x009E, .ghz2 = 0x009E, NOUPLOAD, },
- [B2055_RF_PLLMOD1] = { .ghz5 = 0x0009, .ghz2 = 0x0009, NOUPLOAD, },
- [B2055_RF_MMDIDAC1] = { .ghz5 = 0x00C8, .ghz2 = 0x00C8, UPLOAD, },
- [B2055_RF_MMDIDAC0] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
- [B2055_RF_MMDSP] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_VCO_CAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_VCO_CAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_VCO_CAL3] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
- [B2055_VCO_CAL4] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
- [B2055_VCO_CAL5] = { .ghz5 = 0x0096, .ghz2 = 0x0096, NOUPLOAD, },
- [B2055_VCO_CAL6] = { .ghz5 = 0x003E, .ghz2 = 0x003E, NOUPLOAD, },
- [B2055_VCO_CAL7] = { .ghz5 = 0x003E, .ghz2 = 0x003E, NOUPLOAD, },
- [B2055_VCO_CAL8] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
- [B2055_VCO_CAL9] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
- [B2055_VCO_CAL10] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
- [B2055_VCO_CAL11] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
- [B2055_VCO_CAL12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_VCO_CAL13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_VCO_CAL14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_VCO_CAL15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_VCO_CAL16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_VCO_KVCO] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
- [B2055_VCO_CAPTAIL] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
- [B2055_VCO_IDACVCO] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
- [B2055_VCO_REG] = { .ghz5 = 0x0084, .ghz2 = 0x0084, UPLOAD, },
- [B2055_PLL_RFVTH] = { .ghz5 = 0x00C3, .ghz2 = 0x00C3, NOUPLOAD, },
- [B2055_LGBUF_CENBUF] = { .ghz5 = 0x008F, .ghz2 = 0x008F, NOUPLOAD, },
- [B2055_LGEN_TUNE1] = { .ghz5 = 0x00FF, .ghz2 = 0x00FF, NOUPLOAD, },
- [B2055_LGEN_TUNE2] = { .ghz5 = 0x00FF, .ghz2 = 0x00FF, NOUPLOAD, },
- [B2055_LGEN_IDAC1] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
- [B2055_LGEN_IDAC2] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
- [B2055_LGEN_BIASC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_LGEN_BIASIDAC] = { .ghz5 = 0x00CC, .ghz2 = 0x00CC, NOUPLOAD, },
- [B2055_LGEN_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
- [B2055_LGEN_DIV] = { .ghz5 = 0x0080, .ghz2 = 0x0080, NOUPLOAD, },
- [B2055_LGEN_SPARE2] = { .ghz5 = 0x0080, .ghz2 = 0x0080, NOUPLOAD, },
- [B2055_C1_LGBUF_ATUNE] = { .ghz5 = 0x00F8, .ghz2 = 0x00F8, NOUPLOAD, },
- [B2055_C1_LGBUF_GTUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
- [B2055_C1_LGBUF_DIV] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
- [B2055_C1_LGBUF_AIDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0008, UPLOAD, },
- [B2055_C1_LGBUF_GIDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
- [B2055_C1_LGBUF_IDACFO] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_C1_LGBUF_SPARE] = { .ghz5 = 0x0001, .ghz2 = 0x0001, UPLOAD, },
- [B2055_C1_RX_RFSPC1] = { .ghz5 = 0x008A, .ghz2 = 0x008A, NOUPLOAD, },
- [B2055_C1_RX_RFR1] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
- [B2055_C1_RX_RFR2] = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, },
- [B2055_C1_RX_RFRCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
- [B2055_C1_RX_BB_BLCMP] = { .ghz5 = 0x00A0, .ghz2 = 0x00A0, NOUPLOAD, },
- [B2055_C1_RX_BB_LPF] = { .ghz5 = 0x000A, .ghz2 = 0x000A, NOUPLOAD, },
- [B2055_C1_RX_BB_MIDACHP] = { .ghz5 = 0x0087, .ghz2 = 0x0087, UPLOAD, },
- [B2055_C1_RX_BB_VGA1IDAC] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, },
- [B2055_C1_RX_BB_VGA2IDAC] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, },
- [B2055_C1_RX_BB_VGA3IDAC] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, },
- [B2055_C1_RX_BB_BUFOCTL] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, },
- [B2055_C1_RX_BB_RCCALCTL] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, },
- [B2055_C1_RX_BB_RSSICTL1] = { .ghz5 = 0x006A, .ghz2 = 0x006A, UPLOAD, },
- [B2055_C1_RX_BB_RSSICTL2] = { .ghz5 = 0x00AB, .ghz2 = 0x00AB, UPLOAD, },
- [B2055_C1_RX_BB_RSSICTL3] = { .ghz5 = 0x0013, .ghz2 = 0x0013, UPLOAD, },
- [B2055_C1_RX_BB_RSSICTL4] = { .ghz5 = 0x00C1, .ghz2 = 0x00C1, UPLOAD, },
- [B2055_C1_RX_BB_RSSICTL5] = { .ghz5 = 0x00AA, .ghz2 = 0x00AA, UPLOAD, },
- [B2055_C1_RX_BB_REG] = { .ghz5 = 0x0087, .ghz2 = 0x0087, UPLOAD, },
- [B2055_C1_RX_BB_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_C1_RX_TXBBRCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
- [B2055_C1_TX_RF_SPGA] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
- [B2055_C1_TX_RF_SPAD] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
- [B2055_C1_TX_RF_CNTPGA1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
- [B2055_C1_TX_RF_CNTPAD1] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, },
- [B2055_C1_TX_RF_PGAIDAC] = { .ghz5 = 0x0097, .ghz2 = 0x0097, UPLOAD, },
- [B2055_C1_TX_PGAPADTN] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
- [B2055_C1_TX_PADIDAC1] = { .ghz5 = 0x0014, .ghz2 = 0x0014, UPLOAD, },
- [B2055_C1_TX_PADIDAC2] = { .ghz5 = 0x0033, .ghz2 = 0x0033, NOUPLOAD, },
- [B2055_C1_TX_MXBGTRIM] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
- [B2055_C1_TX_RF_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
- [B2055_C1_TX_RF_PADTSSI1] = { .ghz5 = 0x0003, .ghz2 = 0x0003, UPLOAD, },
- [B2055_C1_TX_RF_PADTSSI2] = { .ghz5 = 0x000A, .ghz2 = 0x000A, NOUPLOAD, },
- [B2055_C1_TX_RF_SPARE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, UPLOAD, },
- [B2055_C1_TX_RF_IQCAL1] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, },
- [B2055_C1_TX_RF_IQCAL2] = { .ghz5 = 0x00A4, .ghz2 = 0x00A4, NOUPLOAD, },
- [B2055_C1_TXBB_RCCAL] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, },
- [B2055_C1_TXBB_LPF1] = { .ghz5 = 0x0028, .ghz2 = 0x0028, NOUPLOAD, },
- [B2055_C1_TX_VOSCNCL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_C1_TX_LPF_MXGMIDAC] = { .ghz5 = 0x004A, .ghz2 = 0x004A, NOUPLOAD, },
- [B2055_C1_TX_BB_MXGM] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_C2_LGBUF_ATUNE] = { .ghz5 = 0x00F8, .ghz2 = 0x00F8, NOUPLOAD, },
- [B2055_C2_LGBUF_GTUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
- [B2055_C2_LGBUF_DIV] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
- [B2055_C2_LGBUF_AIDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0008, UPLOAD, },
- [B2055_C2_LGBUF_GIDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
- [B2055_C2_LGBUF_IDACFO] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_C2_LGBUF_SPARE] = { .ghz5 = 0x0001, .ghz2 = 0x0001, UPLOAD, },
- [B2055_C2_RX_RFSPC1] = { .ghz5 = 0x008A, .ghz2 = 0x008A, NOUPLOAD, },
- [B2055_C2_RX_RFR1] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
- [B2055_C2_RX_RFR2] = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, },
- [B2055_C2_RX_RFRCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
- [B2055_C2_RX_BB_BLCMP] = { .ghz5 = 0x00A0, .ghz2 = 0x00A0, NOUPLOAD, },
- [B2055_C2_RX_BB_LPF] = { .ghz5 = 0x000A, .ghz2 = 0x000A, NOUPLOAD, },
- [B2055_C2_RX_BB_MIDACHP] = { .ghz5 = 0x0087, .ghz2 = 0x0087, UPLOAD, },
- [B2055_C2_RX_BB_VGA1IDAC] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, },
- [B2055_C2_RX_BB_VGA2IDAC] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, },
- [B2055_C2_RX_BB_VGA3IDAC] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, },
- [B2055_C2_RX_BB_BUFOCTL] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, },
- [B2055_C2_RX_BB_RCCALCTL] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, },
- [B2055_C2_RX_BB_RSSICTL1] = { .ghz5 = 0x006A, .ghz2 = 0x006A, UPLOAD, },
- [B2055_C2_RX_BB_RSSICTL2] = { .ghz5 = 0x00AB, .ghz2 = 0x00AB, UPLOAD, },
- [B2055_C2_RX_BB_RSSICTL3] = { .ghz5 = 0x0013, .ghz2 = 0x0013, UPLOAD, },
- [B2055_C2_RX_BB_RSSICTL4] = { .ghz5 = 0x00C1, .ghz2 = 0x00C1, UPLOAD, },
- [B2055_C2_RX_BB_RSSICTL5] = { .ghz5 = 0x00AA, .ghz2 = 0x00AA, UPLOAD, },
- [B2055_C2_RX_BB_REG] = { .ghz5 = 0x0087, .ghz2 = 0x0087, UPLOAD, },
- [B2055_C2_RX_BB_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_C2_RX_TXBBRCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
- [B2055_C2_TX_RF_SPGA] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
- [B2055_C2_TX_RF_SPAD] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
- [B2055_C2_TX_RF_CNTPGA1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
- [B2055_C2_TX_RF_CNTPAD1] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, },
- [B2055_C2_TX_RF_PGAIDAC] = { .ghz5 = 0x0097, .ghz2 = 0x0097, UPLOAD, },
- [B2055_C2_TX_PGAPADTN] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
- [B2055_C2_TX_PADIDAC1] = { .ghz5 = 0x0014, .ghz2 = 0x0014, UPLOAD, },
- [B2055_C2_TX_PADIDAC2] = { .ghz5 = 0x0033, .ghz2 = 0x0033, NOUPLOAD, },
- [B2055_C2_TX_MXBGTRIM] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
- [B2055_C2_TX_RF_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
- [B2055_C2_TX_RF_PADTSSI1] = { .ghz5 = 0x0003, .ghz2 = 0x0003, UPLOAD, },
- [B2055_C2_TX_RF_PADTSSI2] = { .ghz5 = 0x000A, .ghz2 = 0x000A, NOUPLOAD, },
- [B2055_C2_TX_RF_SPARE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, UPLOAD, },
- [B2055_C2_TX_RF_IQCAL1] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, },
- [B2055_C2_TX_RF_IQCAL2] = { .ghz5 = 0x00A4, .ghz2 = 0x00A4, NOUPLOAD, },
- [B2055_C2_TXBB_RCCAL] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, },
- [B2055_C2_TXBB_LPF1] = { .ghz5 = 0x0028, .ghz2 = 0x0028, NOUPLOAD, },
- [B2055_C2_TX_VOSCNCL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_C2_TX_LPF_MXGMIDAC] = { .ghz5 = 0x004A, .ghz2 = 0x004A, NOUPLOAD, },
- [B2055_C2_TX_BB_MXGM] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_PRG_GCHP21] = { .ghz5 = 0x0071, .ghz2 = 0x0071, NOUPLOAD, },
- [B2055_PRG_GCHP22] = { .ghz5 = 0x0072, .ghz2 = 0x0072, NOUPLOAD, },
- [B2055_PRG_GCHP23] = { .ghz5 = 0x0073, .ghz2 = 0x0073, NOUPLOAD, },
- [B2055_PRG_GCHP24] = { .ghz5 = 0x0074, .ghz2 = 0x0074, NOUPLOAD, },
- [B2055_PRG_GCHP25] = { .ghz5 = 0x0075, .ghz2 = 0x0075, NOUPLOAD, },
- [B2055_PRG_GCHP26] = { .ghz5 = 0x0076, .ghz2 = 0x0076, NOUPLOAD, },
- [B2055_PRG_GCHP27] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, },
- [B2055_PRG_GCHP28] = { .ghz5 = 0x0078, .ghz2 = 0x0078, NOUPLOAD, },
- [B2055_PRG_GCHP29] = { .ghz5 = 0x0079, .ghz2 = 0x0079, NOUPLOAD, },
- [B2055_PRG_GCHP30] = { .ghz5 = 0x007A, .ghz2 = 0x007A, NOUPLOAD, },
- [0xC7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [0xC8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [0xC9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [0xCA] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [0xCB] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [0xCC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_C1_LNA_GAINBST] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [0xCE] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [0xCF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [0xD0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [0xD1] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, },
- [B2055_C1_B0NB_RSSIVCM] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
- [0xD3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [0xD4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [0xD5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_C1_GENSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [0xD7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [0xD8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_C2_LNA_GAINBST] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [0xDA] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [0xDB] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [0xDC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [0xDD] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, },
- [B2055_C2_B0NB_RSSIVCM] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
- [0xDF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [0xE0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [0xE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
- [B2055_C2_GENSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
-};
-
-
-void b2055_upload_inittab(struct b43_wldev *dev,
- bool ghz5, bool ignore_uploadflag)
-{
- const struct b2055_inittab_entry *e;
- unsigned int i;
- u16 value;
-
- for (i = 0; i < ARRAY_SIZE(b2055_inittab); i++) {
- e = &(b2055_inittab[i]);
- if (!(e->flags & B2055_INITTAB_ENTRY_OK))
- continue;
- if ((e->flags & B2055_INITTAB_UPLOAD) || ignore_uploadflag) {
- if (ghz5)
- value = e->ghz5;
- else
- value = e->ghz2;
- b43_radio_write16(dev, i, value);
- }
- }
-}
-
-
-#define RADIOREGS(r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, \
- r12, r13, r14, r15, r16, r17, r18, r19, r20, r21) \
- .radio_pll_ref = r0, \
- .radio_rf_pllmod0 = r1, \
- .radio_rf_pllmod1 = r2, \
- .radio_vco_captail = r3, \
- .radio_vco_cal1 = r4, \
- .radio_vco_cal2 = r5, \
- .radio_pll_lfc1 = r6, \
- .radio_pll_lfr1 = r7, \
- .radio_pll_lfc2 = r8, \
- .radio_lgbuf_cenbuf = r9, \
- .radio_lgen_tune1 = r10, \
- .radio_lgen_tune2 = r11, \
- .radio_c1_lgbuf_atune = r12, \
- .radio_c1_lgbuf_gtune = r13, \
- .radio_c1_rx_rfr1 = r14, \
- .radio_c1_tx_pgapadtn = r15, \
- .radio_c1_tx_mxbgtrim = r16, \
- .radio_c2_lgbuf_atune = r17, \
- .radio_c2_lgbuf_gtune = r18, \
- .radio_c2_rx_rfr1 = r19, \
- .radio_c2_tx_pgapadtn = r20, \
- .radio_c2_tx_mxbgtrim = r21
-
-#define PHYREGS(r0, r1, r2, r3, r4, r5) \
- .phy_bw1a = r0, \
- .phy_bw2 = r1, \
- .phy_bw3 = r2, \
- .phy_bw4 = r3, \
- .phy_bw5 = r4, \
- .phy_bw6 = r5
-
-static const struct b43_nphy_channeltab_entry b43_nphy_channeltab[] = {
- { .channel = 184,
- .freq = 4920, /* MHz */
- .unk2 = 3280,
- RADIOREGS(0x71, 0x01, 0xEC, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xFF, 0xFF, 0xFF, 0x00, 0x0F, 0x0F,
- 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
- PHYREGS(0xB407, 0xB007, 0xAC07, 0x1402, 0x1502, 0x1602),
- },
- { .channel = 186,
- .freq = 4930, /* MHz */
- .unk2 = 3287,
- RADIOREGS(0x71, 0x01, 0xED, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xFF, 0xFF, 0xFF, 0x00, 0x0F, 0x0F,
- 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
- PHYREGS(0xB807, 0xB407, 0xB007, 0x1302, 0x1402, 0x1502),
- },
- { .channel = 188,
- .freq = 4940, /* MHz */
- .unk2 = 3293,
- RADIOREGS(0x71, 0x01, 0xEE, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F,
- 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
- PHYREGS(0xBC07, 0xB807, 0xB407, 0x1202, 0x1302, 0x1402),
- },
- { .channel = 190,
- .freq = 4950, /* MHz */
- .unk2 = 3300,
- RADIOREGS(0x71, 0x01, 0xEF, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F,
- 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
- PHYREGS(0xC007, 0xBC07, 0xB807, 0x1102, 0x1202, 0x1302),
- },
- { .channel = 192,
- .freq = 4960, /* MHz */
- .unk2 = 3307,
- RADIOREGS(0x71, 0x01, 0xF0, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F,
- 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
- PHYREGS(0xC407, 0xC007, 0xBC07, 0x0F02, 0x1102, 0x1202),
- },
- { .channel = 194,
- .freq = 4970, /* MHz */
- .unk2 = 3313,
- RADIOREGS(0x71, 0x01, 0xF1, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F,
- 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
- PHYREGS(0xC807, 0xC407, 0xC007, 0x0E02, 0x0F02, 0x1102),
- },
- { .channel = 196,
- .freq = 4980, /* MHz */
- .unk2 = 3320,
- RADIOREGS(0x71, 0x01, 0xF2, 0x0E, 0xFF, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F,
- 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
- PHYREGS(0xCC07, 0xC807, 0xC407, 0x0D02, 0x0E02, 0x0F02),
- },
- { .channel = 198,
- .freq = 4990, /* MHz */
- .unk2 = 3327,
- RADIOREGS(0x71, 0x01, 0xF3, 0x0E, 0xFF, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F,
- 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
- PHYREGS(0xD007, 0xCC07, 0xC807, 0x0C02, 0x0D02, 0x0E02),
- },
- { .channel = 200,
- .freq = 5000, /* MHz */
- .unk2 = 3333,
- RADIOREGS(0x71, 0x01, 0xF4, 0x0E, 0xFF, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F,
- 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
- PHYREGS(0xD407, 0xD007, 0xCC07, 0x0B02, 0x0C02, 0x0D02),
- },
- { .channel = 202,
- .freq = 5010, /* MHz */
- .unk2 = 3340,
- RADIOREGS(0x71, 0x01, 0xF5, 0x0E, 0xFF, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F,
- 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
- PHYREGS(0xD807, 0xD407, 0xD007, 0x0A02, 0x0B02, 0x0C02),
- },
- { .channel = 204,
- .freq = 5020, /* MHz */
- .unk2 = 3347,
- RADIOREGS(0x71, 0x01, 0xF6, 0x0E, 0xF7, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F,
- 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
- PHYREGS(0xDC07, 0xD807, 0xD407, 0x0902, 0x0A02, 0x0B02),
- },
- { .channel = 206,
- .freq = 5030, /* MHz */
- .unk2 = 3353,
- RADIOREGS(0x71, 0x01, 0xF7, 0x0E, 0xF7, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F,
- 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
- PHYREGS(0xE007, 0xDC07, 0xD807, 0x0802, 0x0902, 0x0A02),
- },
- { .channel = 208,
- .freq = 5040, /* MHz */
- .unk2 = 3360,
- RADIOREGS(0x71, 0x01, 0xF8, 0x0D, 0xEF, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F,
- 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
- PHYREGS(0xE407, 0xE007, 0xDC07, 0x0702, 0x0802, 0x0902),
- },
- { .channel = 210,
- .freq = 5050, /* MHz */
- .unk2 = 3367,
- RADIOREGS(0x71, 0x01, 0xF9, 0x0D, 0xEF, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F,
- 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
- PHYREGS(0xE807, 0xE407, 0xE007, 0x0602, 0x0702, 0x0802),
- },
- { .channel = 212,
- .freq = 5060, /* MHz */
- .unk2 = 3373,
- RADIOREGS(0x71, 0x01, 0xFA, 0x0D, 0xE6, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xBB, 0xBB, 0xFF, 0x00, 0x0E, 0x0F,
- 0x8E, 0xFF, 0x00, 0x0E, 0x0F, 0x8E),
- PHYREGS(0xEC07, 0xE807, 0xE407, 0x0502, 0x0602, 0x0702),
- },
- { .channel = 214,
- .freq = 5070, /* MHz */
- .unk2 = 3380,
- RADIOREGS(0x71, 0x01, 0xFB, 0x0D, 0xE6, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xBB, 0xBB, 0xFF, 0x00, 0x0E, 0x0F,
- 0x8E, 0xFF, 0x00, 0x0E, 0x0F, 0x8E),
- PHYREGS(0xF007, 0xEC07, 0xE807, 0x0402, 0x0502, 0x0602),
- },
- { .channel = 216,
- .freq = 5080, /* MHz */
- .unk2 = 3387,
- RADIOREGS(0x71, 0x01, 0xFC, 0x0D, 0xDE, 0x01, 0x04, 0x0A,
- 0x00, 0x8E, 0xBB, 0xBB, 0xEE, 0x00, 0x0E, 0x0F,
- 0x8D, 0xEE, 0x00, 0x0E, 0x0F, 0x8D),
- PHYREGS(0xF407, 0xF007, 0xEC07, 0x0302, 0x0402, 0x0502),
- },
- { .channel = 218,
- .freq = 5090, /* MHz */
- .unk2 = 3393,
- RADIOREGS(0x71, 0x01, 0xFD, 0x0D, 0xDE, 0x01, 0x04, 0x0A,
- 0x00, 0x8E, 0xBB, 0xBB, 0xEE, 0x00, 0x0E, 0x0F,
- 0x8D, 0xEE, 0x00, 0x0E, 0x0F, 0x8D),
- PHYREGS(0xF807, 0xF407, 0xF007, 0x0202, 0x0302, 0x0402),
- },
- { .channel = 220,
- .freq = 5100, /* MHz */
- .unk2 = 3400,
- RADIOREGS(0x71, 0x01, 0xFE, 0x0C, 0xD6, 0x01, 0x04, 0x0A,
- 0x00, 0x8E, 0xAA, 0xAA, 0xEE, 0x00, 0x0D, 0x0F,
- 0x8D, 0xEE, 0x00, 0x0D, 0x0F, 0x8D),
- PHYREGS(0xFC07, 0xF807, 0xF407, 0x0102, 0x0202, 0x0302),
- },
- { .channel = 222,
- .freq = 5110, /* MHz */
- .unk2 = 3407,
- RADIOREGS(0x71, 0x01, 0xFF, 0x0C, 0xD6, 0x01, 0x04, 0x0A,
- 0x00, 0x8E, 0xAA, 0xAA, 0xEE, 0x00, 0x0D, 0x0F,
- 0x8D, 0xEE, 0x00, 0x0D, 0x0F, 0x8D),
- PHYREGS(0x0008, 0xFC07, 0xF807, 0x0002, 0x0102, 0x0202),
- },
- { .channel = 224,
- .freq = 5120, /* MHz */
- .unk2 = 3413,
- RADIOREGS(0x71, 0x02, 0x00, 0x0C, 0xCE, 0x01, 0x04, 0x0A,
- 0x00, 0x8D, 0xAA, 0xAA, 0xDD, 0x00, 0x0D, 0x0F,
- 0x8C, 0xDD, 0x00, 0x0D, 0x0F, 0x8C),
- PHYREGS(0x0408, 0x0008, 0xFC07, 0xFF01, 0x0002, 0x0102),
- },
- { .channel = 226,
- .freq = 5130, /* MHz */
- .unk2 = 3420,
- RADIOREGS(0x71, 0x02, 0x01, 0x0C, 0xCE, 0x01, 0x04, 0x0A,
- 0x00, 0x8D, 0xAA, 0xAA, 0xDD, 0x00, 0x0D, 0x0F,
- 0x8C, 0xDD, 0x00, 0x0D, 0x0F, 0x8C),
- PHYREGS(0x0808, 0x0408, 0x0008, 0xFE01, 0xFF01, 0x0002),
- },
- { .channel = 228,
- .freq = 5140, /* MHz */
- .unk2 = 3427,
- RADIOREGS(0x71, 0x02, 0x02, 0x0C, 0xC6, 0x01, 0x04, 0x0A,
- 0x00, 0x8D, 0x99, 0x99, 0xDD, 0x00, 0x0C, 0x0E,
- 0x8B, 0xDD, 0x00, 0x0C, 0x0E, 0x8B),
- PHYREGS(0x0C08, 0x0808, 0x0408, 0xFD01, 0xFE01, 0xFF01),
- },
- { .channel = 32,
- .freq = 5160, /* MHz */
- .unk2 = 3440,
- RADIOREGS(0x71, 0x02, 0x04, 0x0B, 0xBE, 0x01, 0x04, 0x0A,
- 0x00, 0x8C, 0x99, 0x99, 0xCC, 0x00, 0x0B, 0x0D,
- 0x8A, 0xCC, 0x00, 0x0B, 0x0D, 0x8A),
- PHYREGS(0x1408, 0x1008, 0x0C08, 0xFB01, 0xFC01, 0xFD01),
- },
- { .channel = 34,
- .freq = 5170, /* MHz */
- .unk2 = 3447,
- RADIOREGS(0x71, 0x02, 0x05, 0x0B, 0xBE, 0x01, 0x04, 0x0A,
- 0x00, 0x8C, 0x99, 0x99, 0xCC, 0x00, 0x0B, 0x0D,
- 0x8A, 0xCC, 0x00, 0x0B, 0x0D, 0x8A),
- PHYREGS(0x1808, 0x1408, 0x1008, 0xFA01, 0xFB01, 0xFC01),
- },
- { .channel = 36,
- .freq = 5180, /* MHz */
- .unk2 = 3453,
- RADIOREGS(0x71, 0x02, 0x06, 0x0B, 0xB6, 0x01, 0x04, 0x0A,
- 0x00, 0x8C, 0x88, 0x88, 0xCC, 0x00, 0x0B, 0x0C,
- 0x89, 0xCC, 0x00, 0x0B, 0x0C, 0x89),
- PHYREGS(0x1C08, 0x1808, 0x1408, 0xF901, 0xFA01, 0xFB01),
- },
- { .channel = 38,
- .freq = 5190, /* MHz */
- .unk2 = 3460,
- RADIOREGS(0x71, 0x02, 0x07, 0x0B, 0xB6, 0x01, 0x04, 0x0A,
- 0x00, 0x8C, 0x88, 0x88, 0xCC, 0x00, 0x0B, 0x0C,
- 0x89, 0xCC, 0x00, 0x0B, 0x0C, 0x89),
- PHYREGS(0x2008, 0x1C08, 0x1808, 0xF801, 0xF901, 0xFA01),
- },
- { .channel = 40,
- .freq = 5200, /* MHz */
- .unk2 = 3467,
- RADIOREGS(0x71, 0x02, 0x08, 0x0B, 0xAF, 0x01, 0x04, 0x0A,
- 0x00, 0x8B, 0x88, 0x88, 0xBB, 0x00, 0x0A, 0x0B,
- 0x89, 0xBB, 0x00, 0x0A, 0x0B, 0x89),
- PHYREGS(0x2408, 0x2008, 0x1C08, 0xF701, 0xF801, 0xF901),
- },
- { .channel = 42,
- .freq = 5210, /* MHz */
- .unk2 = 3473,
- RADIOREGS(0x71, 0x02, 0x09, 0x0B, 0xAF, 0x01, 0x04, 0x0A,
- 0x00, 0x8B, 0x88, 0x88, 0xBB, 0x00, 0x0A, 0x0B,
- 0x89, 0xBB, 0x00, 0x0A, 0x0B, 0x89),
- PHYREGS(0x2808, 0x2408, 0x2008, 0xF601, 0xF701, 0xF801),
- },
- { .channel = 44,
- .freq = 5220, /* MHz */
- .unk2 = 3480,
- RADIOREGS(0x71, 0x02, 0x0A, 0x0A, 0xA7, 0x01, 0x04, 0x0A,
- 0x00, 0x8B, 0x77, 0x77, 0xBB, 0x00, 0x09, 0x0A,
- 0x88, 0xBB, 0x00, 0x09, 0x0A, 0x88),
- PHYREGS(0x2C08, 0x2808, 0x2408, 0xF501, 0xF601, 0xF701),
- },
- { .channel = 46,
- .freq = 5230, /* MHz */
- .unk2 = 3487,
- RADIOREGS(0x71, 0x02, 0x0B, 0x0A, 0xA7, 0x01, 0x04, 0x0A,
- 0x00, 0x8B, 0x77, 0x77, 0xBB, 0x00, 0x09, 0x0A,
- 0x88, 0xBB, 0x00, 0x09, 0x0A, 0x88),
- PHYREGS(0x3008, 0x2C08, 0x2808, 0xF401, 0xF501, 0xF601),
- },
- { .channel = 48,
- .freq = 5240, /* MHz */
- .unk2 = 3493,
- RADIOREGS(0x71, 0x02, 0x0C, 0x0A, 0xA0, 0x01, 0x04, 0x0A,
- 0x00, 0x8A, 0x77, 0x77, 0xAA, 0x00, 0x09, 0x0A,
- 0x87, 0xAA, 0x00, 0x09, 0x0A, 0x87),
- PHYREGS(0x3408, 0x3008, 0x2C08, 0xF301, 0xF401, 0xF501),
- },
- { .channel = 50,
- .freq = 5250, /* MHz */
- .unk2 = 3500,
- RADIOREGS(0x71, 0x02, 0x0D, 0x0A, 0xA0, 0x01, 0x04, 0x0A,
- 0x00, 0x8A, 0x77, 0x77, 0xAA, 0x00, 0x09, 0x0A,
- 0x87, 0xAA, 0x00, 0x09, 0x0A, 0x87),
- PHYREGS(0x3808, 0x3408, 0x3008, 0xF201, 0xF301, 0xF401),
- },
- { .channel = 52,
- .freq = 5260, /* MHz */
- .unk2 = 3507,
- RADIOREGS(0x71, 0x02, 0x0E, 0x0A, 0x98, 0x01, 0x04, 0x0A,
- 0x00, 0x8A, 0x66, 0x66, 0xAA, 0x00, 0x08, 0x09,
- 0x87, 0xAA, 0x00, 0x08, 0x09, 0x87),
- PHYREGS(0x3C08, 0x3808, 0x3408, 0xF101, 0xF201, 0xF301),
- },
- { .channel = 54,
- .freq = 5270, /* MHz */
- .unk2 = 3513,
- RADIOREGS(0x71, 0x02, 0x0F, 0x0A, 0x98, 0x01, 0x04, 0x0A,
- 0x00, 0x8A, 0x66, 0x66, 0xAA, 0x00, 0x08, 0x09,
- 0x87, 0xAA, 0x00, 0x08, 0x09, 0x87),
- PHYREGS(0x4008, 0x3C08, 0x3808, 0xF001, 0xF101, 0xF201),
- },
- { .channel = 56,
- .freq = 5280, /* MHz */
- .unk2 = 3520,
- RADIOREGS(0x71, 0x02, 0x10, 0x09, 0x91, 0x01, 0x04, 0x0A,
- 0x00, 0x89, 0x66, 0x66, 0x99, 0x00, 0x08, 0x08,
- 0x86, 0x99, 0x00, 0x08, 0x08, 0x86),
- PHYREGS(0x4408, 0x4008, 0x3C08, 0xF001, 0xF001, 0xF101),
- },
- { .channel = 58,
- .freq = 5290, /* MHz */
- .unk2 = 3527,
- RADIOREGS(0x71, 0x02, 0x11, 0x09, 0x91, 0x01, 0x04, 0x0A,
- 0x00, 0x89, 0x66, 0x66, 0x99, 0x00, 0x08, 0x08,
- 0x86, 0x99, 0x00, 0x08, 0x08, 0x86),
- PHYREGS(0x4808, 0x4408, 0x4008, 0xEF01, 0xF001, 0xF001),
- },
- { .channel = 60,
- .freq = 5300, /* MHz */
- .unk2 = 3533,
- RADIOREGS(0x71, 0x02, 0x12, 0x09, 0x8A, 0x01, 0x04, 0x0A,
- 0x00, 0x89, 0x55, 0x55, 0x99, 0x00, 0x08, 0x07,
- 0x85, 0x99, 0x00, 0x08, 0x07, 0x85),
- PHYREGS(0x4C08, 0x4808, 0x4408, 0xEE01, 0xEF01, 0xF001),
- },
- { .channel = 62,
- .freq = 5310, /* MHz */
- .unk2 = 3540,
- RADIOREGS(0x71, 0x02, 0x13, 0x09, 0x8A, 0x01, 0x04, 0x0A,
- 0x00, 0x89, 0x55, 0x55, 0x99, 0x00, 0x08, 0x07,
- 0x85, 0x99, 0x00, 0x08, 0x07, 0x85),
- PHYREGS(0x5008, 0x4C08, 0x4808, 0xED01, 0xEE01, 0xEF01),
- },
- { .channel = 64,
- .freq = 5320, /* MHz */
- .unk2 = 3547,
- RADIOREGS(0x71, 0x02, 0x14, 0x09, 0x83, 0x01, 0x04, 0x0A,
- 0x00, 0x88, 0x55, 0x55, 0x88, 0x00, 0x07, 0x07,
- 0x84, 0x88, 0x00, 0x07, 0x07, 0x84),
- PHYREGS(0x5408, 0x5008, 0x4C08, 0xEC01, 0xED01, 0xEE01),
- },
- { .channel = 66,
- .freq = 5330, /* MHz */
- .unk2 = 3553,
- RADIOREGS(0x71, 0x02, 0x15, 0x09, 0x83, 0x01, 0x04, 0x0A,
- 0x00, 0x88, 0x55, 0x55, 0x88, 0x00, 0x07, 0x07,
- 0x84, 0x88, 0x00, 0x07, 0x07, 0x84),
- PHYREGS(0x5808, 0x5408, 0x5008, 0xEB01, 0xEC01, 0xED01),
- },
- { .channel = 68,
- .freq = 5340, /* MHz */
- .unk2 = 3560,
- RADIOREGS(0x71, 0x02, 0x16, 0x08, 0x7C, 0x01, 0x04, 0x0A,
- 0x00, 0x88, 0x44, 0x44, 0x88, 0x00, 0x07, 0x06,
- 0x84, 0x88, 0x00, 0x07, 0x06, 0x84),
- PHYREGS(0x5C08, 0x5808, 0x5408, 0xEA01, 0xEB01, 0xEC01),
- },
- { .channel = 70,
- .freq = 5350, /* MHz */
- .unk2 = 3567,
- RADIOREGS(0x71, 0x02, 0x17, 0x08, 0x7C, 0x01, 0x04, 0x0A,
- 0x00, 0x88, 0x44, 0x44, 0x88, 0x00, 0x07, 0x06,
- 0x84, 0x88, 0x00, 0x07, 0x06, 0x84),
- PHYREGS(0x6008, 0x5C08, 0x5808, 0xE901, 0xEA01, 0xEB01),
- },
- { .channel = 72,
- .freq = 5360, /* MHz */
- .unk2 = 3573,
- RADIOREGS(0x71, 0x02, 0x18, 0x08, 0x75, 0x01, 0x04, 0x0A,
- 0x00, 0x87, 0x44, 0x44, 0x77, 0x00, 0x06, 0x05,
- 0x83, 0x77, 0x00, 0x06, 0x05, 0x83),
- PHYREGS(0x6408, 0x6008, 0x5C08, 0xE801, 0xE901, 0xEA01),
- },
- { .channel = 74,
- .freq = 5370, /* MHz */
- .unk2 = 3580,
- RADIOREGS(0x71, 0x02, 0x19, 0x08, 0x75, 0x01, 0x04, 0x0A,
- 0x00, 0x87, 0x44, 0x44, 0x77, 0x00, 0x06, 0x05,
- 0x83, 0x77, 0x00, 0x06, 0x05, 0x83),
- PHYREGS(0x6808, 0x6408, 0x6008, 0xE701, 0xE801, 0xE901),
- },
- { .channel = 76,
- .freq = 5380, /* MHz */
- .unk2 = 3587,
- RADIOREGS(0x71, 0x02, 0x1A, 0x08, 0x6E, 0x01, 0x04, 0x0A,
- 0x00, 0x87, 0x33, 0x33, 0x77, 0x00, 0x06, 0x04,
- 0x82, 0x77, 0x00, 0x06, 0x04, 0x82),
- PHYREGS(0x6C08, 0x6808, 0x6408, 0xE601, 0xE701, 0xE801),
- },
- { .channel = 78,
- .freq = 5390, /* MHz */
- .unk2 = 3593,
- RADIOREGS(0x71, 0x02, 0x1B, 0x08, 0x6E, 0x01, 0x04, 0x0A,
- 0x00, 0x87, 0x33, 0x33, 0x77, 0x00, 0x06, 0x04,
- 0x82, 0x77, 0x00, 0x06, 0x04, 0x82),
- PHYREGS(0x7008, 0x6C08, 0x6808, 0xE501, 0xE601, 0xE701),
- },
- { .channel = 80,
- .freq = 5400, /* MHz */
- .unk2 = 3600,
- RADIOREGS(0x71, 0x02, 0x1C, 0x07, 0x67, 0x01, 0x04, 0x0A,
- 0x00, 0x86, 0x33, 0x33, 0x66, 0x00, 0x05, 0x04,
- 0x81, 0x66, 0x00, 0x05, 0x04, 0x81),
- PHYREGS(0x7408, 0x7008, 0x6C08, 0xE501, 0xE501, 0xE601),
- },
- { .channel = 82,
- .freq = 5410, /* MHz */
- .unk2 = 3607,
- RADIOREGS(0x71, 0x02, 0x1D, 0x07, 0x67, 0x01, 0x04, 0x0A,
- 0x00, 0x86, 0x33, 0x33, 0x66, 0x00, 0x05, 0x04,
- 0x81, 0x66, 0x00, 0x05, 0x04, 0x81),
- PHYREGS(0x7808, 0x7408, 0x7008, 0xE401, 0xE501, 0xE501),
- },
- { .channel = 84,
- .freq = 5420, /* MHz */
- .unk2 = 3613,
- RADIOREGS(0x71, 0x02, 0x1E, 0x07, 0x61, 0x01, 0x04, 0x0A,
- 0x00, 0x86, 0x22, 0x22, 0x66, 0x00, 0x05, 0x03,
- 0x80, 0x66, 0x00, 0x05, 0x03, 0x80),
- PHYREGS(0x7C08, 0x7808, 0x7408, 0xE301, 0xE401, 0xE501),
- },
- { .channel = 86,
- .freq = 5430, /* MHz */
- .unk2 = 3620,
- RADIOREGS(0x71, 0x02, 0x1F, 0x07, 0x61, 0x01, 0x04, 0x0A,
- 0x00, 0x86, 0x22, 0x22, 0x66, 0x00, 0x05, 0x03,
- 0x80, 0x66, 0x00, 0x05, 0x03, 0x80),
- PHYREGS(0x8008, 0x7C08, 0x7808, 0xE201, 0xE301, 0xE401),
- },
- { .channel = 88,
- .freq = 5440, /* MHz */
- .unk2 = 3627,
- RADIOREGS(0x71, 0x02, 0x20, 0x07, 0x5A, 0x01, 0x04, 0x0A,
- 0x00, 0x85, 0x22, 0x22, 0x55, 0x00, 0x04, 0x02,
- 0x80, 0x55, 0x00, 0x04, 0x02, 0x80),
- PHYREGS(0x8408, 0x8008, 0x7C08, 0xE101, 0xE201, 0xE301),
- },
- { .channel = 90,
- .freq = 5450, /* MHz */
- .unk2 = 3633,
- RADIOREGS(0x71, 0x02, 0x21, 0x07, 0x5A, 0x01, 0x04, 0x0A,
- 0x00, 0x85, 0x22, 0x22, 0x55, 0x00, 0x04, 0x02,
- 0x80, 0x55, 0x00, 0x04, 0x02, 0x80),
- PHYREGS(0x8808, 0x8408, 0x8008, 0xE001, 0xE101, 0xE201),
- },
- { .channel = 92,
- .freq = 5460, /* MHz */
- .unk2 = 3640,
- RADIOREGS(0x71, 0x02, 0x22, 0x06, 0x53, 0x01, 0x04, 0x0A,
- 0x00, 0x85, 0x11, 0x11, 0x55, 0x00, 0x04, 0x01,
- 0x80, 0x55, 0x00, 0x04, 0x01, 0x80),
- PHYREGS(0x8C08, 0x8808, 0x8408, 0xDF01, 0xE001, 0xE101),
- },
- { .channel = 94,
- .freq = 5470, /* MHz */
- .unk2 = 3647,
- RADIOREGS(0x71, 0x02, 0x23, 0x06, 0x53, 0x01, 0x04, 0x0A,
- 0x00, 0x85, 0x11, 0x11, 0x55, 0x00, 0x04, 0x01,
- 0x80, 0x55, 0x00, 0x04, 0x01, 0x80),
- PHYREGS(0x9008, 0x8C08, 0x8808, 0xDE01, 0xDF01, 0xE001),
- },
- { .channel = 96,
- .freq = 5480, /* MHz */
- .unk2 = 3653,
- RADIOREGS(0x71, 0x02, 0x24, 0x06, 0x4D, 0x01, 0x04, 0x0A,
- 0x00, 0x84, 0x11, 0x11, 0x44, 0x00, 0x03, 0x00,
- 0x80, 0x44, 0x00, 0x03, 0x00, 0x80),
- PHYREGS(0x9408, 0x9008, 0x8C08, 0xDD01, 0xDE01, 0xDF01),
- },
- { .channel = 98,
- .freq = 5490, /* MHz */
- .unk2 = 3660,
- RADIOREGS(0x71, 0x02, 0x25, 0x06, 0x4D, 0x01, 0x04, 0x0A,
- 0x00, 0x84, 0x11, 0x11, 0x44, 0x00, 0x03, 0x00,
- 0x80, 0x44, 0x00, 0x03, 0x00, 0x80),
- PHYREGS(0x9808, 0x9408, 0x9008, 0xDD01, 0xDD01, 0xDE01),
- },
- { .channel = 100,
- .freq = 5500, /* MHz */
- .unk2 = 3667,
- RADIOREGS(0x71, 0x02, 0x26, 0x06, 0x47, 0x01, 0x04, 0x0A,
- 0x00, 0x84, 0x00, 0x00, 0x44, 0x00, 0x03, 0x00,
- 0x80, 0x44, 0x00, 0x03, 0x00, 0x80),
- PHYREGS(0x9C08, 0x9808, 0x9408, 0xDC01, 0xDD01, 0xDD01),
- },
- { .channel = 102,
- .freq = 5510, /* MHz */
- .unk2 = 3673,
- RADIOREGS(0x71, 0x02, 0x27, 0x06, 0x47, 0x01, 0x04, 0x0A,
- 0x00, 0x84, 0x00, 0x00, 0x44, 0x00, 0x03, 0x00,
- 0x80, 0x44, 0x00, 0x03, 0x00, 0x80),
- PHYREGS(0xA008, 0x9C08, 0x9808, 0xDB01, 0xDC01, 0xDD01),
- },
- { .channel = 104,
- .freq = 5520, /* MHz */
- .unk2 = 3680,
- RADIOREGS(0x71, 0x02, 0x28, 0x05, 0x40, 0x01, 0x04, 0x0A,
- 0x00, 0x83, 0x00, 0x00, 0x33, 0x00, 0x02, 0x00,
- 0x80, 0x33, 0x00, 0x02, 0x00, 0x80),
- PHYREGS(0xA408, 0xA008, 0x9C08, 0xDA01, 0xDB01, 0xDC01),
- },
- { .channel = 106,
- .freq = 5530, /* MHz */
- .unk2 = 3687,
- RADIOREGS(0x71, 0x02, 0x29, 0x05, 0x40, 0x01, 0x04, 0x0A,
- 0x00, 0x83, 0x00, 0x00, 0x33, 0x00, 0x02, 0x00,
- 0x80, 0x33, 0x00, 0x02, 0x00, 0x80),
- PHYREGS(0xA808, 0xA408, 0xA008, 0xD901, 0xDA01, 0xDB01),
- },
- { .channel = 108,
- .freq = 5540, /* MHz */
- .unk2 = 3693,
- RADIOREGS(0x71, 0x02, 0x2A, 0x05, 0x3A, 0x01, 0x04, 0x0A,
- 0x00, 0x83, 0x00, 0x00, 0x33, 0x00, 0x02, 0x00,
- 0x80, 0x33, 0x00, 0x02, 0x00, 0x80),
- PHYREGS(0xAC08, 0xA808, 0xA408, 0xD801, 0xD901, 0xDA01),
- },
- { .channel = 110,
- .freq = 5550, /* MHz */
- .unk2 = 3700,
- RADIOREGS(0x71, 0x02, 0x2B, 0x05, 0x3A, 0x01, 0x04, 0x0A,
- 0x00, 0x83, 0x00, 0x00, 0x33, 0x00, 0x02, 0x00,
- 0x80, 0x33, 0x00, 0x02, 0x00, 0x80),
- PHYREGS(0xB008, 0xAC08, 0xA808, 0xD701, 0xD801, 0xD901),
- },
- { .channel = 112,
- .freq = 5560, /* MHz */
- .unk2 = 3707,
- RADIOREGS(0x71, 0x02, 0x2C, 0x05, 0x34, 0x01, 0x04, 0x0A,
- 0x00, 0x82, 0x00, 0x00, 0x22, 0x00, 0x01, 0x00,
- 0x80, 0x22, 0x00, 0x01, 0x00, 0x80),
- PHYREGS(0xB408, 0xB008, 0xAC08, 0xD701, 0xD701, 0xD801),
- },
- { .channel = 114,
- .freq = 5570, /* MHz */
- .unk2 = 3713,
- RADIOREGS(0x71, 0x02, 0x2D, 0x05, 0x34, 0x01, 0x04, 0x0A,
- 0x00, 0x82, 0x00, 0x00, 0x22, 0x00, 0x01, 0x00,
- 0x80, 0x22, 0x00, 0x01, 0x00, 0x80),
- PHYREGS(0xB808, 0xB408, 0xB008, 0xD601, 0xD701, 0xD701),
- },
- { .channel = 116,
- .freq = 5580, /* MHz */
- .unk2 = 3720,
- RADIOREGS(0x71, 0x02, 0x2E, 0x04, 0x2E, 0x01, 0x04, 0x0A,
- 0x00, 0x82, 0x00, 0x00, 0x22, 0x00, 0x01, 0x00,
- 0x80, 0x22, 0x00, 0x01, 0x00, 0x80),
- PHYREGS(0xBC08, 0xB808, 0xB408, 0xD501, 0xD601, 0xD701),
- },
- { .channel = 118,
- .freq = 5590, /* MHz */
- .unk2 = 3727,
- RADIOREGS(0x71, 0x02, 0x2F, 0x04, 0x2E, 0x01, 0x04, 0x0A,
- 0x00, 0x82, 0x00, 0x00, 0x22, 0x00, 0x01, 0x00,
- 0x80, 0x22, 0x00, 0x01, 0x00, 0x80),
- PHYREGS(0xC008, 0xBC08, 0xB808, 0xD401, 0xD501, 0xD601),
- },
- { .channel = 120,
- .freq = 5600, /* MHz */
- .unk2 = 3733,
- RADIOREGS(0x71, 0x02, 0x30, 0x04, 0x28, 0x01, 0x04, 0x0A,
- 0x00, 0x81, 0x00, 0x00, 0x11, 0x00, 0x01, 0x00,
- 0x80, 0x11, 0x00, 0x01, 0x00, 0x80),
- PHYREGS(0xC408, 0xC008, 0xBC08, 0xD301, 0xD401, 0xD501),
- },
- { .channel = 122,
- .freq = 5610, /* MHz */
- .unk2 = 3740,
- RADIOREGS(0x71, 0x02, 0x31, 0x04, 0x28, 0x01, 0x04, 0x0A,
- 0x00, 0x81, 0x00, 0x00, 0x11, 0x00, 0x01, 0x00,
- 0x80, 0x11, 0x00, 0x01, 0x00, 0x80),
- PHYREGS(0xC808, 0xC408, 0xC008, 0xD201, 0xD301, 0xD401),
- },
- { .channel = 124,
- .freq = 5620, /* MHz */
- .unk2 = 3747,
- RADIOREGS(0x71, 0x02, 0x32, 0x04, 0x21, 0x01, 0x04, 0x0A,
- 0x00, 0x81, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00,
- 0x80, 0x11, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0xCC08, 0xC808, 0xC408, 0xD201, 0xD201, 0xD301),
- },
- { .channel = 126,
- .freq = 5630, /* MHz */
- .unk2 = 3753,
- RADIOREGS(0x71, 0x02, 0x33, 0x04, 0x21, 0x01, 0x04, 0x0A,
- 0x00, 0x81, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00,
- 0x80, 0x11, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0xD008, 0xCC08, 0xC808, 0xD101, 0xD201, 0xD201),
- },
- { .channel = 128,
- .freq = 5640, /* MHz */
- .unk2 = 3760,
- RADIOREGS(0x71, 0x02, 0x34, 0x03, 0x1C, 0x01, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0xD408, 0xD008, 0xCC08, 0xD001, 0xD101, 0xD201),
- },
- { .channel = 130,
- .freq = 5650, /* MHz */
- .unk2 = 3767,
- RADIOREGS(0x71, 0x02, 0x35, 0x03, 0x1C, 0x01, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0xD808, 0xD408, 0xD008, 0xCF01, 0xD001, 0xD101),
- },
- { .channel = 132,
- .freq = 5660, /* MHz */
- .unk2 = 3773,
- RADIOREGS(0x71, 0x02, 0x36, 0x03, 0x16, 0x01, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0xDC08, 0xD808, 0xD408, 0xCE01, 0xCF01, 0xD001),
- },
- { .channel = 134,
- .freq = 5670, /* MHz */
- .unk2 = 3780,
- RADIOREGS(0x71, 0x02, 0x37, 0x03, 0x16, 0x01, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0xE008, 0xDC08, 0xD808, 0xCE01, 0xCE01, 0xCF01),
- },
- { .channel = 136,
- .freq = 5680, /* MHz */
- .unk2 = 3787,
- RADIOREGS(0x71, 0x02, 0x38, 0x03, 0x10, 0x01, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0xE408, 0xE008, 0xDC08, 0xCD01, 0xCE01, 0xCE01),
- },
- { .channel = 138,
- .freq = 5690, /* MHz */
- .unk2 = 3793,
- RADIOREGS(0x71, 0x02, 0x39, 0x03, 0x10, 0x01, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0xE808, 0xE408, 0xE008, 0xCC01, 0xCD01, 0xCE01),
- },
- { .channel = 140,
- .freq = 5700, /* MHz */
- .unk2 = 3800,
- RADIOREGS(0x71, 0x02, 0x3A, 0x02, 0x0A, 0x01, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0xEC08, 0xE808, 0xE408, 0xCB01, 0xCC01, 0xCD01),
- },
- { .channel = 142,
- .freq = 5710, /* MHz */
- .unk2 = 3807,
- RADIOREGS(0x71, 0x02, 0x3B, 0x02, 0x0A, 0x01, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0xF008, 0xEC08, 0xE808, 0xCA01, 0xCB01, 0xCC01),
- },
- { .channel = 144,
- .freq = 5720, /* MHz */
- .unk2 = 3813,
- RADIOREGS(0x71, 0x02, 0x3C, 0x02, 0x0A, 0x01, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0xF408, 0xF008, 0xEC08, 0xC901, 0xCA01, 0xCB01),
- },
- { .channel = 145,
- .freq = 5725, /* MHz */
- .unk2 = 3817,
- RADIOREGS(0x72, 0x04, 0x79, 0x02, 0x03, 0x01, 0x03, 0x14,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0xF608, 0xF208, 0xEE08, 0xC901, 0xCA01, 0xCB01),
- },
- { .channel = 146,
- .freq = 5730, /* MHz */
- .unk2 = 3820,
- RADIOREGS(0x71, 0x02, 0x3D, 0x02, 0x0A, 0x01, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0xF808, 0xF408, 0xF008, 0xC901, 0xC901, 0xCA01),
- },
- { .channel = 147,
- .freq = 5735, /* MHz */
- .unk2 = 3823,
- RADIOREGS(0x72, 0x04, 0x7B, 0x02, 0x03, 0x01, 0x03, 0x14,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0xFA08, 0xF608, 0xF208, 0xC801, 0xC901, 0xCA01),
- },
- { .channel = 148,
- .freq = 5740, /* MHz */
- .unk2 = 3827,
- RADIOREGS(0x71, 0x02, 0x3E, 0x02, 0x0A, 0x01, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0xFC08, 0xF808, 0xF408, 0xC801, 0xC901, 0xC901),
- },
- { .channel = 149,
- .freq = 5745, /* MHz */
- .unk2 = 3830,
- RADIOREGS(0x72, 0x04, 0x7D, 0x02, 0xFE, 0x00, 0x03, 0x14,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0xFE08, 0xFA08, 0xF608, 0xC801, 0xC801, 0xC901),
- },
- { .channel = 150,
- .freq = 5750, /* MHz */
- .unk2 = 3833,
- RADIOREGS(0x71, 0x02, 0x3F, 0x02, 0x0A, 0x01, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0x0009, 0xFC08, 0xF808, 0xC701, 0xC801, 0xC901),
- },
- { .channel = 151,
- .freq = 5755, /* MHz */
- .unk2 = 3837,
- RADIOREGS(0x72, 0x04, 0x7F, 0x02, 0xFE, 0x00, 0x03, 0x14,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0x0209, 0xFE08, 0xFA08, 0xC701, 0xC801, 0xC801),
- },
- { .channel = 152,
- .freq = 5760, /* MHz */
- .unk2 = 3840,
- RADIOREGS(0x71, 0x02, 0x40, 0x02, 0x0A, 0x01, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0x0409, 0x0009, 0xFC08, 0xC601, 0xC701, 0xC801),
- },
- { .channel = 153,
- .freq = 5765, /* MHz */
- .unk2 = 3843,
- RADIOREGS(0x72, 0x04, 0x81, 0x02, 0xF8, 0x00, 0x03, 0x14,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0x0609, 0x0209, 0xFE08, 0xC601, 0xC701, 0xC801),
- },
- { .channel = 154,
- .freq = 5770, /* MHz */
- .unk2 = 3847,
- RADIOREGS(0x71, 0x02, 0x41, 0x02, 0x0A, 0x01, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0x0809, 0x0409, 0x0009, 0xC601, 0xC601, 0xC701),
- },
- { .channel = 155,
- .freq = 5775, /* MHz */
- .unk2 = 3850,
- RADIOREGS(0x72, 0x04, 0x83, 0x02, 0xF8, 0x00, 0x03, 0x14,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0x0A09, 0x0609, 0x0209, 0xC501, 0xC601, 0xC701),
- },
- { .channel = 156,
- .freq = 5780, /* MHz */
- .unk2 = 3853,
- RADIOREGS(0x71, 0x02, 0x42, 0x02, 0x0A, 0x01, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0x0C09, 0x0809, 0x0409, 0xC501, 0xC601, 0xC601),
- },
- { .channel = 157,
- .freq = 5785, /* MHz */
- .unk2 = 3857,
- RADIOREGS(0x72, 0x04, 0x85, 0x02, 0xF2, 0x00, 0x03, 0x14,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0x0E09, 0x0A09, 0x0609, 0xC401, 0xC501, 0xC601),
- },
- { .channel = 158,
- .freq = 5790, /* MHz */
- .unk2 = 3860,
- RADIOREGS(0x71, 0x02, 0x43, 0x02, 0x0A, 0x01, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0x1009, 0x0C09, 0x0809, 0xC401, 0xC501, 0xC601),
- },
- { .channel = 159,
- .freq = 5795, /* MHz */
- .unk2 = 3863,
- RADIOREGS(0x72, 0x04, 0x87, 0x02, 0xF2, 0x00, 0x03, 0x14,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0x1209, 0x0E09, 0x0A09, 0xC401, 0xC401, 0xC501),
- },
- { .channel = 160,
- .freq = 5800, /* MHz */
- .unk2 = 3867,
- RADIOREGS(0x71, 0x02, 0x44, 0x01, 0x0A, 0x01, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0x1409, 0x1009, 0x0C09, 0xC301, 0xC401, 0xC501),
- },
- { .channel = 161,
- .freq = 5805, /* MHz */
- .unk2 = 3870,
- RADIOREGS(0x72, 0x04, 0x89, 0x01, 0xED, 0x00, 0x03, 0x14,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0x1609, 0x1209, 0x0E09, 0xC301, 0xC401, 0xC401),
- },
- { .channel = 162,
- .freq = 5810, /* MHz */
- .unk2 = 3873,
- RADIOREGS(0x71, 0x02, 0x45, 0x01, 0x0A, 0x01, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0x1809, 0x1409, 0x1009, 0xC201, 0xC301, 0xC401),
- },
- { .channel = 163,
- .freq = 5815, /* MHz */
- .unk2 = 3877,
- RADIOREGS(0x72, 0x04, 0x8B, 0x01, 0xED, 0x00, 0x03, 0x14,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0x1A09, 0x1609, 0x1209, 0xC201, 0xC301, 0xC401),
- },
- { .channel = 164,
- .freq = 5820, /* MHz */
- .unk2 = 3880,
- RADIOREGS(0x71, 0x02, 0x46, 0x01, 0x0A, 0x01, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0x1C09, 0x1809, 0x1409, 0xC201, 0xC201, 0xC301),
- },
- { .channel = 165,
- .freq = 5825, /* MHz */
- .unk2 = 3883,
- RADIOREGS(0x72, 0x04, 0x8D, 0x01, 0xED, 0x00, 0x03, 0x14,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0x1E09, 0x1A09, 0x1609, 0xC101, 0xC201, 0xC301),
- },
- { .channel = 166,
- .freq = 5830, /* MHz */
- .unk2 = 3887,
- RADIOREGS(0x71, 0x02, 0x47, 0x01, 0x0A, 0x01, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0x2009, 0x1C09, 0x1809, 0xC101, 0xC201, 0xC201),
- },
- { .channel = 168,
- .freq = 5840, /* MHz */
- .unk2 = 3893,
- RADIOREGS(0x71, 0x02, 0x48, 0x01, 0x0A, 0x01, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0x2409, 0x2009, 0x1C09, 0xC001, 0xC101, 0xC201),
- },
- { .channel = 170,
- .freq = 5850, /* MHz */
- .unk2 = 3900,
- RADIOREGS(0x71, 0x02, 0x49, 0x01, 0xE0, 0x00, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0x2809, 0x2409, 0x2009, 0xBF01, 0xC001, 0xC101),
- },
- { .channel = 172,
- .freq = 5860, /* MHz */
- .unk2 = 3907,
- RADIOREGS(0x71, 0x02, 0x4A, 0x01, 0xDE, 0x00, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0x2C09, 0x2809, 0x2409, 0xBF01, 0xBF01, 0xC001),
- },
- { .channel = 174,
- .freq = 5870, /* MHz */
- .unk2 = 3913,
- RADIOREGS(0x71, 0x02, 0x4B, 0x00, 0xDB, 0x00, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0x3009, 0x2C09, 0x2809, 0xBE01, 0xBF01, 0xBF01),
- },
- { .channel = 176,
- .freq = 5880, /* MHz */
- .unk2 = 3920,
- RADIOREGS(0x71, 0x02, 0x4C, 0x00, 0xD8, 0x00, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0x3409, 0x3009, 0x2C09, 0xBD01, 0xBE01, 0xBF01),
- },
- { .channel = 178,
- .freq = 5890, /* MHz */
- .unk2 = 3927,
- RADIOREGS(0x71, 0x02, 0x4D, 0x00, 0xD6, 0x00, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0x3809, 0x3409, 0x3009, 0xBC01, 0xBD01, 0xBE01),
- },
- { .channel = 180,
- .freq = 5900, /* MHz */
- .unk2 = 3933,
- RADIOREGS(0x71, 0x02, 0x4E, 0x00, 0xD3, 0x00, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0x3C09, 0x3809, 0x3409, 0xBC01, 0xBC01, 0xBD01),
- },
- { .channel = 182,
- .freq = 5910, /* MHz */
- .unk2 = 3940,
- RADIOREGS(0x71, 0x02, 0x4F, 0x00, 0xD6, 0x00, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
- PHYREGS(0x4009, 0x3C09, 0x3809, 0xBB01, 0xBC01, 0xBC01),
- },
- { .channel = 1,
- .freq = 2412, /* MHz */
- .unk2 = 3216,
- RADIOREGS(0x73, 0x09, 0x6C, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0D, 0x0C,
- 0x80, 0xFF, 0x88, 0x0D, 0x0C, 0x80),
- PHYREGS(0xC903, 0xC503, 0xC103, 0x3A04, 0x3F04, 0x4304),
- },
- { .channel = 2,
- .freq = 2417, /* MHz */
- .unk2 = 3223,
- RADIOREGS(0x73, 0x09, 0x71, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x0B,
- 0x80, 0xFF, 0x88, 0x0C, 0x0B, 0x80),
- PHYREGS(0xCB03, 0xC703, 0xC303, 0x3804, 0x3D04, 0x4104),
- },
- { .channel = 3,
- .freq = 2422, /* MHz */
- .unk2 = 3229,
- RADIOREGS(0x73, 0x09, 0x76, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x0A,
- 0x80, 0xFF, 0x88, 0x0C, 0x0A, 0x80),
- PHYREGS(0xCD03, 0xC903, 0xC503, 0x3604, 0x3A04, 0x3F04),
- },
- { .channel = 4,
- .freq = 2427, /* MHz */
- .unk2 = 3236,
- RADIOREGS(0x73, 0x09, 0x7B, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x0A,
- 0x80, 0xFF, 0x88, 0x0C, 0x0A, 0x80),
- PHYREGS(0xCF03, 0xCB03, 0xC703, 0x3404, 0x3804, 0x3D04),
- },
- { .channel = 5,
- .freq = 2432, /* MHz */
- .unk2 = 3243,
- RADIOREGS(0x73, 0x09, 0x80, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x09,
- 0x80, 0xFF, 0x88, 0x0C, 0x09, 0x80),
- PHYREGS(0xD103, 0xCD03, 0xC903, 0x3104, 0x3604, 0x3A04),
- },
- { .channel = 6,
- .freq = 2437, /* MHz */
- .unk2 = 3249,
- RADIOREGS(0x73, 0x09, 0x85, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0B, 0x08,
- 0x80, 0xFF, 0x88, 0x0B, 0x08, 0x80),
- PHYREGS(0xD303, 0xCF03, 0xCB03, 0x2F04, 0x3404, 0x3804),
- },
- { .channel = 7,
- .freq = 2442, /* MHz */
- .unk2 = 3256,
- RADIOREGS(0x73, 0x09, 0x8A, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0A, 0x07,
- 0x80, 0xFF, 0x88, 0x0A, 0x07, 0x80),
- PHYREGS(0xD503, 0xD103, 0xCD03, 0x2D04, 0x3104, 0x3604),
- },
- { .channel = 8,
- .freq = 2447, /* MHz */
- .unk2 = 3263,
- RADIOREGS(0x73, 0x09, 0x8F, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0A, 0x06,
- 0x80, 0xFF, 0x88, 0x0A, 0x06, 0x80),
- PHYREGS(0xD703, 0xD303, 0xCF03, 0x2B04, 0x2F04, 0x3404),
- },
- { .channel = 9,
- .freq = 2452, /* MHz */
- .unk2 = 3269,
- RADIOREGS(0x73, 0x09, 0x94, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x09, 0x06,
- 0x80, 0xFF, 0x88, 0x09, 0x06, 0x80),
- PHYREGS(0xD903, 0xD503, 0xD103, 0x2904, 0x2D04, 0x3104),
- },
- { .channel = 10,
- .freq = 2457, /* MHz */
- .unk2 = 3276,
- RADIOREGS(0x73, 0x09, 0x99, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x08, 0x05,
- 0x80, 0xFF, 0x88, 0x08, 0x05, 0x80),
- PHYREGS(0xDB03, 0xD703, 0xD303, 0x2704, 0x2B04, 0x2F04),
- },
- { .channel = 11,
- .freq = 2462, /* MHz */
- .unk2 = 3283,
- RADIOREGS(0x73, 0x09, 0x9E, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x08, 0x04,
- 0x80, 0xFF, 0x88, 0x08, 0x04, 0x80),
- PHYREGS(0xDD03, 0xD903, 0xD503, 0x2404, 0x2904, 0x2D04),
- },
- { .channel = 12,
- .freq = 2467, /* MHz */
- .unk2 = 3289,
- RADIOREGS(0x73, 0x09, 0xA3, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x08, 0x03,
- 0x80, 0xFF, 0x88, 0x08, 0x03, 0x80),
- PHYREGS(0xDF03, 0xDB03, 0xD703, 0x2204, 0x2704, 0x2B04),
- },
- { .channel = 13,
- .freq = 2472, /* MHz */
- .unk2 = 3296,
- RADIOREGS(0x73, 0x09, 0xA8, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x07, 0x03,
- 0x80, 0xFF, 0x88, 0x07, 0x03, 0x80),
- PHYREGS(0xE103, 0xDD03, 0xD903, 0x2004, 0x2404, 0x2904),
- },
- { .channel = 14,
- .freq = 2484, /* MHz */
- .unk2 = 3312,
- RADIOREGS(0x73, 0x09, 0xB4, 0x0F, 0xFF, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x07, 0x01,
- 0x80, 0xFF, 0x88, 0x07, 0x01, 0x80),
- PHYREGS(0xE603, 0xE203, 0xDE03, 0x1B04, 0x1F04, 0x2404),
- },
-};
-
-const struct b43_nphy_channeltab_entry *
-b43_nphy_get_chantabent(struct b43_wldev *dev, u8 channel)
-{
- const struct b43_nphy_channeltab_entry *e;
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE(b43_nphy_channeltab); i++) {
- e = &(b43_nphy_channeltab[i]);
- if (e->channel == channel)
- return e;
- }
-
- return NULL;
-}
-
-
-const u8 b43_ntab_adjustpower0[] = {
- 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01,
- 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x03, 0x03,
- 0x04, 0x04, 0x04, 0x04, 0x05, 0x05, 0x05, 0x05,
- 0x06, 0x06, 0x06, 0x06, 0x07, 0x07, 0x07, 0x07,
- 0x08, 0x08, 0x08, 0x08, 0x09, 0x09, 0x09, 0x09,
- 0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x0B, 0x0B, 0x0B,
- 0x0C, 0x0C, 0x0C, 0x0C, 0x0D, 0x0D, 0x0D, 0x0D,
- 0x0E, 0x0E, 0x0E, 0x0E, 0x0F, 0x0F, 0x0F, 0x0F,
- 0x10, 0x10, 0x10, 0x10, 0x11, 0x11, 0x11, 0x11,
- 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x13,
- 0x14, 0x14, 0x14, 0x14, 0x15, 0x15, 0x15, 0x15,
- 0x16, 0x16, 0x16, 0x16, 0x17, 0x17, 0x17, 0x17,
- 0x18, 0x18, 0x18, 0x18, 0x19, 0x19, 0x19, 0x19,
- 0x1A, 0x1A, 0x1A, 0x1A, 0x1B, 0x1B, 0x1B, 0x1B,
- 0x1C, 0x1C, 0x1C, 0x1C, 0x1D, 0x1D, 0x1D, 0x1D,
- 0x1E, 0x1E, 0x1E, 0x1E, 0x1F, 0x1F, 0x1F, 0x1F,
-};
-
-const u8 b43_ntab_adjustpower1[] = {
- 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01,
- 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x03, 0x03,
- 0x04, 0x04, 0x04, 0x04, 0x05, 0x05, 0x05, 0x05,
- 0x06, 0x06, 0x06, 0x06, 0x07, 0x07, 0x07, 0x07,
- 0x08, 0x08, 0x08, 0x08, 0x09, 0x09, 0x09, 0x09,
- 0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x0B, 0x0B, 0x0B,
- 0x0C, 0x0C, 0x0C, 0x0C, 0x0D, 0x0D, 0x0D, 0x0D,
- 0x0E, 0x0E, 0x0E, 0x0E, 0x0F, 0x0F, 0x0F, 0x0F,
- 0x10, 0x10, 0x10, 0x10, 0x11, 0x11, 0x11, 0x11,
- 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x13,
- 0x14, 0x14, 0x14, 0x14, 0x15, 0x15, 0x15, 0x15,
- 0x16, 0x16, 0x16, 0x16, 0x17, 0x17, 0x17, 0x17,
- 0x18, 0x18, 0x18, 0x18, 0x19, 0x19, 0x19, 0x19,
- 0x1A, 0x1A, 0x1A, 0x1A, 0x1B, 0x1B, 0x1B, 0x1B,
- 0x1C, 0x1C, 0x1C, 0x1C, 0x1D, 0x1D, 0x1D, 0x1D,
- 0x1E, 0x1E, 0x1E, 0x1E, 0x1F, 0x1F, 0x1F, 0x1F,
-};
-
-const u16 b43_ntab_bdi[] = {
- 0x0070, 0x0126, 0x012C, 0x0246, 0x048D, 0x04D2,
-};
-
-const u32 b43_ntab_channelest[] = {
- 0x44444444, 0x44444444, 0x44444444, 0x44444444,
- 0x44444444, 0x44444444, 0x44444444, 0x44444444,
- 0x10101010, 0x10101010, 0x10101010, 0x10101010,
- 0x10101010, 0x10101010, 0x10101010, 0x10101010,
- 0x44444444, 0x44444444, 0x44444444, 0x44444444,
- 0x44444444, 0x44444444, 0x44444444, 0x44444444,
- 0x10101010, 0x10101010, 0x10101010, 0x10101010,
- 0x10101010, 0x10101010, 0x10101010, 0x10101010,
- 0x44444444, 0x44444444, 0x44444444, 0x44444444,
- 0x44444444, 0x44444444, 0x44444444, 0x44444444,
- 0x44444444, 0x44444444, 0x44444444, 0x44444444,
- 0x44444444, 0x44444444, 0x44444444, 0x44444444,
- 0x10101010, 0x10101010, 0x10101010, 0x10101010,
- 0x10101010, 0x10101010, 0x10101010, 0x10101010,
- 0x10101010, 0x10101010, 0x10101010, 0x10101010,
- 0x10101010, 0x10101010, 0x10101010, 0x10101010,
- 0x44444444, 0x44444444, 0x44444444, 0x44444444,
- 0x44444444, 0x44444444, 0x44444444, 0x44444444,
- 0x44444444, 0x44444444, 0x44444444, 0x44444444,
- 0x44444444, 0x44444444, 0x44444444, 0x44444444,
- 0x10101010, 0x10101010, 0x10101010, 0x10101010,
- 0x10101010, 0x10101010, 0x10101010, 0x10101010,
- 0x10101010, 0x10101010, 0x10101010, 0x10101010,
- 0x10101010, 0x10101010, 0x10101010, 0x10101010,
-};
-
-const u8 b43_ntab_estimatepowerlt0[] = {
- 0x50, 0x4F, 0x4E, 0x4D, 0x4C, 0x4B, 0x4A, 0x49,
- 0x48, 0x47, 0x46, 0x45, 0x44, 0x43, 0x42, 0x41,
- 0x40, 0x3F, 0x3E, 0x3D, 0x3C, 0x3B, 0x3A, 0x39,
- 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31,
- 0x30, 0x2F, 0x2E, 0x2D, 0x2C, 0x2B, 0x2A, 0x29,
- 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21,
- 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19,
- 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11,
-};
-
-const u8 b43_ntab_estimatepowerlt1[] = {
- 0x50, 0x4F, 0x4E, 0x4D, 0x4C, 0x4B, 0x4A, 0x49,
- 0x48, 0x47, 0x46, 0x45, 0x44, 0x43, 0x42, 0x41,
- 0x40, 0x3F, 0x3E, 0x3D, 0x3C, 0x3B, 0x3A, 0x39,
- 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31,
- 0x30, 0x2F, 0x2E, 0x2D, 0x2C, 0x2B, 0x2A, 0x29,
- 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21,
- 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19,
- 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11,
-};
-
-const u8 b43_ntab_framelookup[] = {
- 0x02, 0x04, 0x14, 0x14, 0x03, 0x05, 0x16, 0x16,
- 0x0A, 0x0C, 0x1C, 0x1C, 0x0B, 0x0D, 0x1E, 0x1E,
- 0x06, 0x08, 0x18, 0x18, 0x07, 0x09, 0x1A, 0x1A,
- 0x0E, 0x10, 0x20, 0x28, 0x0F, 0x11, 0x22, 0x2A,
-};
-
-const u32 b43_ntab_framestruct[] = {
- 0x08004A04, 0x00100000, 0x01000A05, 0x00100020,
- 0x09804506, 0x00100030, 0x09804507, 0x00100030,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x08004A0C, 0x00100008, 0x01000A0D, 0x00100028,
- 0x0980450E, 0x00100038, 0x0980450F, 0x00100038,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000A04, 0x00100000, 0x11008A05, 0x00100020,
- 0x1980C506, 0x00100030, 0x21810506, 0x00100030,
- 0x21810506, 0x00100030, 0x01800504, 0x00100030,
- 0x11808505, 0x00100030, 0x29814507, 0x01100030,
- 0x00000A04, 0x00100000, 0x11008A05, 0x00100020,
- 0x21810506, 0x00100030, 0x21810506, 0x00100030,
- 0x29814507, 0x01100030, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000A0C, 0x00100008, 0x11008A0D, 0x00100028,
- 0x1980C50E, 0x00100038, 0x2181050E, 0x00100038,
- 0x2181050E, 0x00100038, 0x0180050C, 0x00100038,
- 0x1180850D, 0x00100038, 0x2981450F, 0x01100038,
- 0x00000A0C, 0x00100008, 0x11008A0D, 0x00100028,
- 0x2181050E, 0x00100038, 0x2181050E, 0x00100038,
- 0x2981450F, 0x01100038, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x08004A04, 0x00100000, 0x01000A05, 0x00100020,
- 0x1980C506, 0x00100030, 0x1980C506, 0x00100030,
- 0x11808504, 0x00100030, 0x3981CA05, 0x00100030,
- 0x29814507, 0x01100030, 0x00000000, 0x00000000,
- 0x10008A04, 0x00100000, 0x3981CA05, 0x00100030,
- 0x1980C506, 0x00100030, 0x29814507, 0x01100030,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x08004A0C, 0x00100008, 0x01000A0D, 0x00100028,
- 0x1980C50E, 0x00100038, 0x1980C50E, 0x00100038,
- 0x1180850C, 0x00100038, 0x3981CA0D, 0x00100038,
- 0x2981450F, 0x01100038, 0x00000000, 0x00000000,
- 0x10008A0C, 0x00100008, 0x3981CA0D, 0x00100038,
- 0x1980C50E, 0x00100038, 0x2981450F, 0x01100038,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x40021404, 0x00100000, 0x02001405, 0x00100040,
- 0x0B004A06, 0x01900060, 0x13008A06, 0x01900060,
- 0x13008A06, 0x01900060, 0x43020A04, 0x00100060,
- 0x1B00CA05, 0x00100060, 0x23010A07, 0x01500060,
- 0x40021404, 0x00100000, 0x1A00D405, 0x00100040,
- 0x13008A06, 0x01900060, 0x13008A06, 0x01900060,
- 0x23010A07, 0x01500060, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x4002140C, 0x00100010, 0x0200140D, 0x00100050,
- 0x0B004A0E, 0x01900070, 0x13008A0E, 0x01900070,
- 0x13008A0E, 0x01900070, 0x43020A0C, 0x00100070,
- 0x1B00CA0D, 0x00100070, 0x23010A0F, 0x01500070,
- 0x4002140C, 0x00100010, 0x1A00D40D, 0x00100050,
- 0x13008A0E, 0x01900070, 0x13008A0E, 0x01900070,
- 0x23010A0F, 0x01500070, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x50029404, 0x00100000, 0x32019405, 0x00100040,
- 0x0B004A06, 0x01900060, 0x0B004A06, 0x01900060,
- 0x5B02CA04, 0x00100060, 0x3B01D405, 0x00100060,
- 0x23010A07, 0x01500060, 0x00000000, 0x00000000,
- 0x5802D404, 0x00100000, 0x3B01D405, 0x00100060,
- 0x0B004A06, 0x01900060, 0x23010A07, 0x01500060,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x5002940C, 0x00100010, 0x3201940D, 0x00100050,
- 0x0B004A0E, 0x01900070, 0x0B004A0E, 0x01900070,
- 0x5B02CA0C, 0x00100070, 0x3B01D40D, 0x00100070,
- 0x23010A0F, 0x01500070, 0x00000000, 0x00000000,
- 0x5802D40C, 0x00100010, 0x3B01D40D, 0x00100070,
- 0x0B004A0E, 0x01900070, 0x23010A0F, 0x01500070,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x40021404, 0x000F4800, 0x62031405, 0x00100040,
- 0x53028A06, 0x01900060, 0x53028A07, 0x01900060,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x4002140C, 0x000F4810, 0x6203140D, 0x00100050,
- 0x53028A0E, 0x01900070, 0x53028A0F, 0x01900070,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000A0C, 0x00100008, 0x11008A0D, 0x00100028,
- 0x1980C50E, 0x00100038, 0x2181050E, 0x00100038,
- 0x2181050E, 0x00100038, 0x0180050C, 0x00100038,
- 0x1180850D, 0x00100038, 0x1181850D, 0x00100038,
- 0x2981450F, 0x01100038, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000A0C, 0x00100008, 0x11008A0D, 0x00100028,
- 0x2181050E, 0x00100038, 0x2181050E, 0x00100038,
- 0x1181850D, 0x00100038, 0x2981450F, 0x01100038,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x08004A04, 0x00100000, 0x01000A05, 0x00100020,
- 0x0180C506, 0x00100030, 0x0180C506, 0x00100030,
- 0x2180C50C, 0x00100030, 0x49820A0D, 0x0016A130,
- 0x41824A0D, 0x0016A130, 0x2981450F, 0x01100030,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x2000CA0C, 0x00100000, 0x49820A0D, 0x0016A130,
- 0x1980C50E, 0x00100030, 0x41824A0D, 0x0016A130,
- 0x2981450F, 0x01100030, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x4002140C, 0x00100010, 0x0200140D, 0x00100050,
- 0x0B004A0E, 0x01900070, 0x13008A0E, 0x01900070,
- 0x13008A0E, 0x01900070, 0x43020A0C, 0x00100070,
- 0x1B00CA0D, 0x00100070, 0x1B014A0D, 0x00100070,
- 0x23010A0F, 0x01500070, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x4002140C, 0x00100010, 0x1A00D40D, 0x00100050,
- 0x13008A0E, 0x01900070, 0x13008A0E, 0x01900070,
- 0x1B014A0D, 0x00100070, 0x23010A0F, 0x01500070,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x50029404, 0x00100000, 0x32019405, 0x00100040,
- 0x03004A06, 0x01900060, 0x03004A06, 0x01900060,
- 0x6B030A0C, 0x00100060, 0x4B02140D, 0x0016A160,
- 0x4302540D, 0x0016A160, 0x23010A0F, 0x01500060,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x6B03140C, 0x00100060, 0x4B02140D, 0x0016A160,
- 0x0B004A0E, 0x01900060, 0x4302540D, 0x0016A160,
- 0x23010A0F, 0x01500060, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x40021404, 0x00100000, 0x1A00D405, 0x00100040,
- 0x53028A06, 0x01900060, 0x5B02CA06, 0x01900060,
- 0x5B02CA06, 0x01900060, 0x43020A04, 0x00100060,
- 0x1B00CA05, 0x00100060, 0x53028A07, 0x0190C060,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x4002140C, 0x00100010, 0x1A00D40D, 0x00100050,
- 0x53028A0E, 0x01900070, 0x5B02CA0E, 0x01900070,
- 0x5B02CA0E, 0x01900070, 0x43020A0C, 0x00100070,
- 0x1B00CA0D, 0x00100070, 0x53028A0F, 0x0190C070,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x40021404, 0x00100000, 0x1A00D405, 0x00100040,
- 0x5B02CA06, 0x01900060, 0x5B02CA06, 0x01900060,
- 0x53028A07, 0x0190C060, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x4002140C, 0x00100010, 0x1A00D40D, 0x00100050,
- 0x5B02CA0E, 0x01900070, 0x5B02CA0E, 0x01900070,
- 0x53028A0F, 0x0190C070, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-};
-
-const u32 b43_ntab_gainctl0[] = {
- 0x007F003F, 0x007E013F, 0x007D023E, 0x007C033E,
- 0x007B043D, 0x007A053D, 0x0079063C, 0x0078073C,
- 0x0077083B, 0x0076093B, 0x00750A3A, 0x00740B3A,
- 0x00730C39, 0x00720D39, 0x00710E38, 0x00700F38,
- 0x006F0037, 0x006E0137, 0x006D0236, 0x006C0336,
- 0x006B0435, 0x006A0535, 0x00690634, 0x00680734,
- 0x00670833, 0x00660933, 0x00650A32, 0x00640B32,
- 0x00630C31, 0x00620D31, 0x00610E30, 0x00600F30,
- 0x005F002F, 0x005E012F, 0x005D022E, 0x005C032E,
- 0x005B042D, 0x005A052D, 0x0059062C, 0x0058072C,
- 0x0057082B, 0x0056092B, 0x00550A2A, 0x00540B2A,
- 0x00530C29, 0x00520D29, 0x00510E28, 0x00500F28,
- 0x004F0027, 0x004E0127, 0x004D0226, 0x004C0326,
- 0x004B0425, 0x004A0525, 0x00490624, 0x00480724,
- 0x00470823, 0x00460923, 0x00450A22, 0x00440B22,
- 0x00430C21, 0x00420D21, 0x00410E20, 0x00400F20,
- 0x003F001F, 0x003E011F, 0x003D021E, 0x003C031E,
- 0x003B041D, 0x003A051D, 0x0039061C, 0x0038071C,
- 0x0037081B, 0x0036091B, 0x00350A1A, 0x00340B1A,
- 0x00330C19, 0x00320D19, 0x00310E18, 0x00300F18,
- 0x002F0017, 0x002E0117, 0x002D0216, 0x002C0316,
- 0x002B0415, 0x002A0515, 0x00290614, 0x00280714,
- 0x00270813, 0x00260913, 0x00250A12, 0x00240B12,
- 0x00230C11, 0x00220D11, 0x00210E10, 0x00200F10,
- 0x001F000F, 0x001E010F, 0x001D020E, 0x001C030E,
- 0x001B040D, 0x001A050D, 0x0019060C, 0x0018070C,
- 0x0017080B, 0x0016090B, 0x00150A0A, 0x00140B0A,
- 0x00130C09, 0x00120D09, 0x00110E08, 0x00100F08,
- 0x000F0007, 0x000E0107, 0x000D0206, 0x000C0306,
- 0x000B0405, 0x000A0505, 0x00090604, 0x00080704,
- 0x00070803, 0x00060903, 0x00050A02, 0x00040B02,
- 0x00030C01, 0x00020D01, 0x00010E00, 0x00000F00,
-};
-
-const u32 b43_ntab_gainctl1[] = {
- 0x007F003F, 0x007E013F, 0x007D023E, 0x007C033E,
- 0x007B043D, 0x007A053D, 0x0079063C, 0x0078073C,
- 0x0077083B, 0x0076093B, 0x00750A3A, 0x00740B3A,
- 0x00730C39, 0x00720D39, 0x00710E38, 0x00700F38,
- 0x006F0037, 0x006E0137, 0x006D0236, 0x006C0336,
- 0x006B0435, 0x006A0535, 0x00690634, 0x00680734,
- 0x00670833, 0x00660933, 0x00650A32, 0x00640B32,
- 0x00630C31, 0x00620D31, 0x00610E30, 0x00600F30,
- 0x005F002F, 0x005E012F, 0x005D022E, 0x005C032E,
- 0x005B042D, 0x005A052D, 0x0059062C, 0x0058072C,
- 0x0057082B, 0x0056092B, 0x00550A2A, 0x00540B2A,
- 0x00530C29, 0x00520D29, 0x00510E28, 0x00500F28,
- 0x004F0027, 0x004E0127, 0x004D0226, 0x004C0326,
- 0x004B0425, 0x004A0525, 0x00490624, 0x00480724,
- 0x00470823, 0x00460923, 0x00450A22, 0x00440B22,
- 0x00430C21, 0x00420D21, 0x00410E20, 0x00400F20,
- 0x003F001F, 0x003E011F, 0x003D021E, 0x003C031E,
- 0x003B041D, 0x003A051D, 0x0039061C, 0x0038071C,
- 0x0037081B, 0x0036091B, 0x00350A1A, 0x00340B1A,
- 0x00330C19, 0x00320D19, 0x00310E18, 0x00300F18,
- 0x002F0017, 0x002E0117, 0x002D0216, 0x002C0316,
- 0x002B0415, 0x002A0515, 0x00290614, 0x00280714,
- 0x00270813, 0x00260913, 0x00250A12, 0x00240B12,
- 0x00230C11, 0x00220D11, 0x00210E10, 0x00200F10,
- 0x001F000F, 0x001E010F, 0x001D020E, 0x001C030E,
- 0x001B040D, 0x001A050D, 0x0019060C, 0x0018070C,
- 0x0017080B, 0x0016090B, 0x00150A0A, 0x00140B0A,
- 0x00130C09, 0x00120D09, 0x00110E08, 0x00100F08,
- 0x000F0007, 0x000E0107, 0x000D0206, 0x000C0306,
- 0x000B0405, 0x000A0505, 0x00090604, 0x00080704,
- 0x00070803, 0x00060903, 0x00050A02, 0x00040B02,
- 0x00030C01, 0x00020D01, 0x00010E00, 0x00000F00,
-};
-
-const u32 b43_ntab_intlevel[] = {
- 0x00802070, 0x0671188D, 0x0A60192C, 0x0A300E46,
- 0x00C1188D, 0x080024D2, 0x00000070,
-};
-
-const u32 b43_ntab_iqlt0[] = {
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
-};
-
-const u32 b43_ntab_iqlt1[] = {
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
- 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F,
-};
-
-const u16 b43_ntab_loftlt0[] = {
- 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
- 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
- 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
- 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
- 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
- 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
- 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
- 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
- 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
- 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
- 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
- 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
- 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
- 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
- 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
- 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
- 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
- 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
- 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
- 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
- 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
- 0x0002, 0x0103,
-};
-
-const u16 b43_ntab_loftlt1[] = {
- 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
- 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
- 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
- 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
- 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
- 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
- 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
- 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
- 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
- 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
- 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
- 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
- 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
- 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
- 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
- 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
- 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
- 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
- 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
- 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103,
- 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101,
- 0x0002, 0x0103,
-};
-
-const u8 b43_ntab_mcs[] = {
- 0x00, 0x08, 0x0A, 0x10, 0x12, 0x19, 0x1A, 0x1C,
- 0x40, 0x48, 0x4A, 0x50, 0x52, 0x59, 0x5A, 0x5C,
- 0x80, 0x88, 0x8A, 0x90, 0x92, 0x99, 0x9A, 0x9C,
- 0xC0, 0xC8, 0xCA, 0xD0, 0xD2, 0xD9, 0xDA, 0xDC,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x01, 0x02, 0x04, 0x08, 0x09, 0x0A, 0x0C,
- 0x10, 0x11, 0x12, 0x14, 0x18, 0x19, 0x1A, 0x1C,
- 0x20, 0x21, 0x22, 0x24, 0x40, 0x41, 0x42, 0x44,
- 0x48, 0x49, 0x4A, 0x4C, 0x50, 0x51, 0x52, 0x54,
- 0x58, 0x59, 0x5A, 0x5C, 0x60, 0x61, 0x62, 0x64,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-};
-
-const u32 b43_ntab_noisevar10[] = {
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
-};
-
-const u32 b43_ntab_noisevar11[] = {
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
- 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D,
-};
-
-const u16 b43_ntab_pilot[] = {
- 0xFF08, 0xFF08, 0xFF08, 0xFF08, 0xFF08, 0xFF08,
- 0xFF08, 0xFF08, 0x80D5, 0x80D5, 0x80D5, 0x80D5,
- 0x80D5, 0x80D5, 0x80D5, 0x80D5, 0xFF0A, 0xFF82,
- 0xFFA0, 0xFF28, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFF82, 0xFFA0, 0xFF28, 0xFF0A, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xF83F, 0xFA1F, 0xFA97, 0xFAB5,
- 0xF2BD, 0xF0BF, 0xFFFF, 0xFFFF, 0xF017, 0xF815,
- 0xF215, 0xF095, 0xF035, 0xF01D, 0xFFFF, 0xFFFF,
- 0xFF08, 0xFF02, 0xFF80, 0xFF20, 0xFF08, 0xFF02,
- 0xFF80, 0xFF20, 0xF01F, 0xF817, 0xFA15, 0xF295,
- 0xF0B5, 0xF03D, 0xFFFF, 0xFFFF, 0xF82A, 0xFA0A,
- 0xFA82, 0xFAA0, 0xF2A8, 0xF0AA, 0xFFFF, 0xFFFF,
- 0xF002, 0xF800, 0xF200, 0xF080, 0xF020, 0xF008,
- 0xFFFF, 0xFFFF, 0xF00A, 0xF802, 0xFA00, 0xF280,
- 0xF0A0, 0xF028, 0xFFFF, 0xFFFF,
-};
-
-const u32 b43_ntab_pilotlt[] = {
- 0x76540123, 0x62407351, 0x76543201, 0x76540213,
- 0x76540123, 0x76430521,
-};
-
-const u32 b43_ntab_tdi20a0[] = {
- 0x00091226, 0x000A1429, 0x000B56AD, 0x000C58B0,
- 0x000D5AB3, 0x000E9CB6, 0x000F9EBA, 0x0000C13D,
- 0x00020301, 0x00030504, 0x00040708, 0x0005090B,
- 0x00064B8E, 0x00095291, 0x000A5494, 0x000B9718,
- 0x000C9927, 0x000D9B2A, 0x000EDD2E, 0x000FDF31,
- 0x000101B4, 0x000243B7, 0x000345BB, 0x000447BE,
- 0x00058982, 0x00068C05, 0x00099309, 0x000A950C,
- 0x000BD78F, 0x000CD992, 0x000DDB96, 0x000F1D99,
- 0x00005FA8, 0x0001422C, 0x0002842F, 0x00038632,
- 0x00048835, 0x0005CA38, 0x0006CCBC, 0x0009D3BF,
- 0x000B1603, 0x000C1806, 0x000D1A0A, 0x000E1C0D,
- 0x000F5E10, 0x00008093, 0x00018297, 0x0002C49A,
- 0x0003C680, 0x0004C880, 0x00060B00, 0x00070D00,
- 0x00000000, 0x00000000, 0x00000000,
-};
-
-const u32 b43_ntab_tdi20a1[] = {
- 0x00014B26, 0x00028D29, 0x000393AD, 0x00049630,
- 0x0005D833, 0x0006DA36, 0x00099C3A, 0x000A9E3D,
- 0x000BC081, 0x000CC284, 0x000DC488, 0x000F068B,
- 0x0000488E, 0x00018B91, 0x0002D214, 0x0003D418,
- 0x0004D6A7, 0x000618AA, 0x00071AAE, 0x0009DCB1,
- 0x000B1EB4, 0x000C0137, 0x000D033B, 0x000E053E,
- 0x000F4702, 0x00008905, 0x00020C09, 0x0003128C,
- 0x0004148F, 0x00051712, 0x00065916, 0x00091B19,
- 0x000A1D28, 0x000B5F2C, 0x000C41AF, 0x000D43B2,
- 0x000E85B5, 0x000F87B8, 0x0000C9BC, 0x00024CBF,
- 0x00035303, 0x00045506, 0x0005978A, 0x0006998D,
- 0x00095B90, 0x000A5D93, 0x000B9F97, 0x000C821A,
- 0x000D8400, 0x000EC600, 0x000FC800, 0x00010A00,
- 0x00000000, 0x00000000, 0x00000000,
-};
-
-const u32 b43_ntab_tdi40a0[] = {
- 0x0011A346, 0x00136CCF, 0x0014F5D9, 0x001641E2,
- 0x0017CB6B, 0x00195475, 0x001B2383, 0x001CAD0C,
- 0x001E7616, 0x0000821F, 0x00020BA8, 0x0003D4B2,
- 0x00056447, 0x00072DD0, 0x0008B6DA, 0x000A02E3,
- 0x000B8C6C, 0x000D15F6, 0x0011E484, 0x0013AE0D,
- 0x00153717, 0x00168320, 0x00180CA9, 0x00199633,
- 0x001B6548, 0x001CEED1, 0x001EB7DB, 0x0000C3E4,
- 0x00024D6D, 0x000416F7, 0x0005A585, 0x00076F0F,
- 0x0008F818, 0x000A4421, 0x000BCDAB, 0x000D9734,
- 0x00122649, 0x0013EFD2, 0x001578DC, 0x0016C4E5,
- 0x00184E6E, 0x001A17F8, 0x001BA686, 0x001D3010,
- 0x001EF999, 0x00010522, 0x00028EAC, 0x00045835,
- 0x0005E74A, 0x0007B0D3, 0x00093A5D, 0x000A85E6,
- 0x000C0F6F, 0x000DD8F9, 0x00126787, 0x00143111,
- 0x0015BA9A, 0x00170623, 0x00188FAD, 0x001A5936,
- 0x001BE84B, 0x001DB1D4, 0x001F3B5E, 0x000146E7,
- 0x00031070, 0x000499FA, 0x00062888, 0x0007F212,
- 0x00097B9B, 0x000AC7A4, 0x000C50AE, 0x000E1A37,
- 0x0012A94C, 0x001472D5, 0x0015FC5F, 0x00174868,
- 0x0018D171, 0x001A9AFB, 0x001C2989, 0x001DF313,
- 0x001F7C9C, 0x000188A5, 0x000351AF, 0x0004DB38,
- 0x0006AA4D, 0x000833D7, 0x0009BD60, 0x000B0969,
- 0x000C9273, 0x000E5BFC, 0x00132A8A, 0x0014B414,
- 0x00163D9D, 0x001789A6, 0x001912B0, 0x001ADC39,
- 0x001C6BCE, 0x001E34D8, 0x001FBE61, 0x0001CA6A,
- 0x00039374, 0x00051CFD, 0x0006EC0B, 0x00087515,
- 0x0009FE9E, 0x000B4AA7, 0x000CD3B1, 0x000E9D3A,
- 0x00000000, 0x00000000,
-};
-
-const u32 b43_ntab_tdi40a1[] = {
- 0x001EDB36, 0x000129CA, 0x0002B353, 0x00047CDD,
- 0x0005C8E6, 0x000791EF, 0x00091BF9, 0x000AAA07,
- 0x000C3391, 0x000DFD1A, 0x00120923, 0x0013D22D,
- 0x00155C37, 0x0016EACB, 0x00187454, 0x001A3DDE,
- 0x001B89E7, 0x001D12F0, 0x001F1CFA, 0x00016B88,
- 0x00033492, 0x0004BE1B, 0x00060A24, 0x0007D32E,
- 0x00095D38, 0x000AEC4C, 0x000C7555, 0x000E3EDF,
- 0x00124AE8, 0x001413F1, 0x0015A37B, 0x00172C89,
- 0x0018B593, 0x001A419C, 0x001BCB25, 0x001D942F,
- 0x001F63B9, 0x0001AD4D, 0x00037657, 0x0004C260,
- 0x00068BE9, 0x000814F3, 0x0009A47C, 0x000B2D8A,
- 0x000CB694, 0x000E429D, 0x00128C26, 0x001455B0,
- 0x0015E4BA, 0x00176E4E, 0x0018F758, 0x001A8361,
- 0x001C0CEA, 0x001DD674, 0x001FA57D, 0x0001EE8B,
- 0x0003B795, 0x0005039E, 0x0006CD27, 0x000856B1,
- 0x0009E5C6, 0x000B6F4F, 0x000CF859, 0x000E8462,
- 0x00130DEB, 0x00149775, 0x00162603, 0x0017AF8C,
- 0x00193896, 0x001AC49F, 0x001C4E28, 0x001E17B2,
- 0x0000A6C7, 0x00023050, 0x0003F9DA, 0x00054563,
- 0x00070EEC, 0x00089876, 0x000A2704, 0x000BB08D,
- 0x000D3A17, 0x001185A0, 0x00134F29, 0x0014D8B3,
- 0x001667C8, 0x0017F151, 0x00197ADB, 0x001B0664,
- 0x001C8FED, 0x001E5977, 0x0000E805, 0x0002718F,
- 0x00043B18, 0x000586A1, 0x0007502B, 0x0008D9B4,
- 0x000A68C9, 0x000BF252, 0x000DBBDC, 0x0011C7E5,
- 0x001390EE, 0x00151A78, 0x0016A906, 0x00183290,
- 0x0019BC19, 0x001B4822, 0x001CD12C, 0x001E9AB5,
- 0x00000000, 0x00000000,
-};
-
-const u32 b43_ntab_tdtrn[] = {
- 0x061C061C, 0x0050EE68, 0xF592FE36, 0xFE5212F6,
- 0x00000C38, 0xFE5212F6, 0xF592FE36, 0x0050EE68,
- 0x061C061C, 0xEE680050, 0xFE36F592, 0x12F6FE52,
- 0x0C380000, 0x12F6FE52, 0xFE36F592, 0xEE680050,
- 0x061C061C, 0x0050EE68, 0xF592FE36, 0xFE5212F6,
- 0x00000C38, 0xFE5212F6, 0xF592FE36, 0x0050EE68,
- 0x061C061C, 0xEE680050, 0xFE36F592, 0x12F6FE52,
- 0x0C380000, 0x12F6FE52, 0xFE36F592, 0xEE680050,
- 0x05E305E3, 0x004DEF0C, 0xF5F3FE47, 0xFE611246,
- 0x00000BC7, 0xFE611246, 0xF5F3FE47, 0x004DEF0C,
- 0x05E305E3, 0xEF0C004D, 0xFE47F5F3, 0x1246FE61,
- 0x0BC70000, 0x1246FE61, 0xFE47F5F3, 0xEF0C004D,
- 0x05E305E3, 0x004DEF0C, 0xF5F3FE47, 0xFE611246,
- 0x00000BC7, 0xFE611246, 0xF5F3FE47, 0x004DEF0C,
- 0x05E305E3, 0xEF0C004D, 0xFE47F5F3, 0x1246FE61,
- 0x0BC70000, 0x1246FE61, 0xFE47F5F3, 0xEF0C004D,
- 0xFA58FA58, 0xF895043B, 0xFF4C09C0, 0xFBC6FFA8,
- 0xFB84F384, 0x0798F6F9, 0x05760122, 0x058409F6,
- 0x0B500000, 0x05B7F542, 0x08860432, 0x06DDFEE7,
- 0xFB84F384, 0xF9D90664, 0xF7E8025C, 0x00FFF7BD,
- 0x05A805A8, 0xF7BD00FF, 0x025CF7E8, 0x0664F9D9,
- 0xF384FB84, 0xFEE706DD, 0x04320886, 0xF54205B7,
- 0x00000B50, 0x09F60584, 0x01220576, 0xF6F90798,
- 0xF384FB84, 0xFFA8FBC6, 0x09C0FF4C, 0x043BF895,
- 0x02D402D4, 0x07DE0270, 0xFC96079C, 0xF90AFE94,
- 0xFE00FF2C, 0x02D4065D, 0x092A0096, 0x0014FBB8,
- 0xFD2CFD2C, 0x076AFB3C, 0x0096F752, 0xF991FD87,
- 0xFB2C0200, 0xFEB8F960, 0x08E0FC96, 0x049802A8,
- 0xFD2CFD2C, 0x02A80498, 0xFC9608E0, 0xF960FEB8,
- 0x0200FB2C, 0xFD87F991, 0xF7520096, 0xFB3C076A,
- 0xFD2CFD2C, 0xFBB80014, 0x0096092A, 0x065D02D4,
- 0xFF2CFE00, 0xFE94F90A, 0x079CFC96, 0x027007DE,
- 0x02D402D4, 0x027007DE, 0x079CFC96, 0xFE94F90A,
- 0xFF2CFE00, 0x065D02D4, 0x0096092A, 0xFBB80014,
- 0xFD2CFD2C, 0xFB3C076A, 0xF7520096, 0xFD87F991,
- 0x0200FB2C, 0xF960FEB8, 0xFC9608E0, 0x02A80498,
- 0xFD2CFD2C, 0x049802A8, 0x08E0FC96, 0xFEB8F960,
- 0xFB2C0200, 0xF991FD87, 0x0096F752, 0x076AFB3C,
- 0xFD2CFD2C, 0x0014FBB8, 0x092A0096, 0x02D4065D,
- 0xFE00FF2C, 0xF90AFE94, 0xFC96079C, 0x07DE0270,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x062A0000, 0xFEFA0759, 0x08B80908, 0xF396FC2D,
- 0xF9D6045C, 0xFC4EF608, 0xF748F596, 0x07B207BF,
- 0x062A062A, 0xF84EF841, 0xF748F596, 0x03B209F8,
- 0xF9D6045C, 0x0C6A03D3, 0x08B80908, 0x0106F8A7,
- 0x062A0000, 0xFEFAF8A7, 0x08B8F6F8, 0xF39603D3,
- 0xF9D6FBA4, 0xFC4E09F8, 0xF7480A6A, 0x07B2F841,
- 0x062AF9D6, 0xF84E07BF, 0xF7480A6A, 0x03B2F608,
- 0xF9D6FBA4, 0x0C6AFC2D, 0x08B8F6F8, 0x01060759,
- 0x062A0000, 0xFEFA0759, 0x08B80908, 0xF396FC2D,
- 0xF9D6045C, 0xFC4EF608, 0xF748F596, 0x07B207BF,
- 0x062A062A, 0xF84EF841, 0xF748F596, 0x03B209F8,
- 0xF9D6045C, 0x0C6A03D3, 0x08B80908, 0x0106F8A7,
- 0x062A0000, 0xFEFAF8A7, 0x08B8F6F8, 0xF39603D3,
- 0xF9D6FBA4, 0xFC4E09F8, 0xF7480A6A, 0x07B2F841,
- 0x062AF9D6, 0xF84E07BF, 0xF7480A6A, 0x03B2F608,
- 0xF9D6FBA4, 0x0C6AFC2D, 0x08B8F6F8, 0x01060759,
- 0x061C061C, 0xFF30009D, 0xFFB21141, 0xFD87FB54,
- 0xF65DFE59, 0x02EEF99E, 0x0166F03C, 0xFFF809B6,
- 0x000008A4, 0x000AF42B, 0x00EFF577, 0xFA840BF2,
- 0xFC02FF51, 0x08260F67, 0xFFF0036F, 0x0842F9C3,
- 0x00000000, 0x063DF7BE, 0xFC910010, 0xF099F7DA,
- 0x00AF03FE, 0xF40E057C, 0x0A89FF11, 0x0BD5FFF6,
- 0xF75C0000, 0xF64A0008, 0x0FC4FE9A, 0x0662FD12,
- 0x01A709A3, 0x04AC0279, 0xEEBF004E, 0xFF6300D0,
- 0xF9E4F9E4, 0x00D0FF63, 0x004EEEBF, 0x027904AC,
- 0x09A301A7, 0xFD120662, 0xFE9A0FC4, 0x0008F64A,
- 0x0000F75C, 0xFFF60BD5, 0xFF110A89, 0x057CF40E,
- 0x03FE00AF, 0xF7DAF099, 0x0010FC91, 0xF7BE063D,
- 0x00000000, 0xF9C30842, 0x036FFFF0, 0x0F670826,
- 0xFF51FC02, 0x0BF2FA84, 0xF57700EF, 0xF42B000A,
- 0x08A40000, 0x09B6FFF8, 0xF03C0166, 0xF99E02EE,
- 0xFE59F65D, 0xFB54FD87, 0x1141FFB2, 0x009DFF30,
- 0x05E30000, 0xFF060705, 0x085408A0, 0xF425FC59,
- 0xFA1D042A, 0xFC78F67A, 0xF7ACF60E, 0x075A0766,
- 0x05E305E3, 0xF8A6F89A, 0xF7ACF60E, 0x03880986,
- 0xFA1D042A, 0x0BDB03A7, 0x085408A0, 0x00FAF8FB,
- 0x05E30000, 0xFF06F8FB, 0x0854F760, 0xF42503A7,
- 0xFA1DFBD6, 0xFC780986, 0xF7AC09F2, 0x075AF89A,
- 0x05E3FA1D, 0xF8A60766, 0xF7AC09F2, 0x0388F67A,
- 0xFA1DFBD6, 0x0BDBFC59, 0x0854F760, 0x00FA0705,
- 0x05E30000, 0xFF060705, 0x085408A0, 0xF425FC59,
- 0xFA1D042A, 0xFC78F67A, 0xF7ACF60E, 0x075A0766,
- 0x05E305E3, 0xF8A6F89A, 0xF7ACF60E, 0x03880986,
- 0xFA1D042A, 0x0BDB03A7, 0x085408A0, 0x00FAF8FB,
- 0x05E30000, 0xFF06F8FB, 0x0854F760, 0xF42503A7,
- 0xFA1DFBD6, 0xFC780986, 0xF7AC09F2, 0x075AF89A,
- 0x05E3FA1D, 0xF8A60766, 0xF7AC09F2, 0x0388F67A,
- 0xFA1DFBD6, 0x0BDBFC59, 0x0854F760, 0x00FA0705,
- 0xFA58FA58, 0xF8F0FE00, 0x0448073D, 0xFDC9FE46,
- 0xF9910258, 0x089D0407, 0xFD5CF71A, 0x02AFFDE0,
- 0x083E0496, 0xFF5A0740, 0xFF7AFD97, 0x00FE01F1,
- 0x0009082E, 0xFA94FF75, 0xFECDF8EA, 0xFFB0F693,
- 0xFD2CFA58, 0x0433FF16, 0xFBA405DD, 0xFA610341,
- 0x06A606CB, 0x0039FD2D, 0x0677FA97, 0x01FA05E0,
- 0xF896003E, 0x075A068B, 0x012CFC3E, 0xFA23F98D,
- 0xFC7CFD43, 0xFF90FC0D, 0x01C10982, 0x00C601D6,
- 0xFD2CFD2C, 0x01D600C6, 0x098201C1, 0xFC0DFF90,
- 0xFD43FC7C, 0xF98DFA23, 0xFC3E012C, 0x068B075A,
- 0x003EF896, 0x05E001FA, 0xFA970677, 0xFD2D0039,
- 0x06CB06A6, 0x0341FA61, 0x05DDFBA4, 0xFF160433,
- 0xFA58FD2C, 0xF693FFB0, 0xF8EAFECD, 0xFF75FA94,
- 0x082E0009, 0x01F100FE, 0xFD97FF7A, 0x0740FF5A,
- 0x0496083E, 0xFDE002AF, 0xF71AFD5C, 0x0407089D,
- 0x0258F991, 0xFE46FDC9, 0x073D0448, 0xFE00F8F0,
- 0xFD2CFD2C, 0xFCE00500, 0xFC09FDDC, 0xFE680157,
- 0x04C70571, 0xFC3AFF21, 0xFCD70228, 0x056D0277,
- 0x0200FE00, 0x0022F927, 0xFE3C032B, 0xFC44FF3C,
- 0x03E9FBDB, 0x04570313, 0x04C9FF5C, 0x000D03B8,
- 0xFA580000, 0xFBE900D2, 0xF9D0FE0B, 0x0125FDF9,
- 0x042501BF, 0x0328FA2B, 0xFFA902F0, 0xFA250157,
- 0x0200FE00, 0x03740438, 0xFF0405FD, 0x030CFE52,
- 0x0037FB39, 0xFF6904C5, 0x04F8FD23, 0xFD31FC1B,
- 0xFD2CFD2C, 0xFC1BFD31, 0xFD2304F8, 0x04C5FF69,
- 0xFB390037, 0xFE52030C, 0x05FDFF04, 0x04380374,
- 0xFE000200, 0x0157FA25, 0x02F0FFA9, 0xFA2B0328,
- 0x01BF0425, 0xFDF90125, 0xFE0BF9D0, 0x00D2FBE9,
- 0x0000FA58, 0x03B8000D, 0xFF5C04C9, 0x03130457,
- 0xFBDB03E9, 0xFF3CFC44, 0x032BFE3C, 0xF9270022,
- 0xFE000200, 0x0277056D, 0x0228FCD7, 0xFF21FC3A,
- 0x057104C7, 0x0157FE68, 0xFDDCFC09, 0x0500FCE0,
- 0xFD2CFD2C, 0x0500FCE0, 0xFDDCFC09, 0x0157FE68,
- 0x057104C7, 0xFF21FC3A, 0x0228FCD7, 0x0277056D,
- 0xFE000200, 0xF9270022, 0x032BFE3C, 0xFF3CFC44,
- 0xFBDB03E9, 0x03130457, 0xFF5C04C9, 0x03B8000D,
- 0x0000FA58, 0x00D2FBE9, 0xFE0BF9D0, 0xFDF90125,
- 0x01BF0425, 0xFA2B0328, 0x02F0FFA9, 0x0157FA25,
- 0xFE000200, 0x04380374, 0x05FDFF04, 0xFE52030C,
- 0xFB390037, 0x04C5FF69, 0xFD2304F8, 0xFC1BFD31,
- 0xFD2CFD2C, 0xFD31FC1B, 0x04F8FD23, 0xFF6904C5,
- 0x0037FB39, 0x030CFE52, 0xFF0405FD, 0x03740438,
- 0x0200FE00, 0xFA250157, 0xFFA902F0, 0x0328FA2B,
- 0x042501BF, 0x0125FDF9, 0xF9D0FE0B, 0xFBE900D2,
- 0xFA580000, 0x000D03B8, 0x04C9FF5C, 0x04570313,
- 0x03E9FBDB, 0xFC44FF3C, 0xFE3C032B, 0x0022F927,
- 0x0200FE00, 0x056D0277, 0xFCD70228, 0xFC3AFF21,
- 0x04C70571, 0xFE680157, 0xFC09FDDC, 0xFCE00500,
- 0x05A80000, 0xFF1006BE, 0x0800084A, 0xF49CFC7E,
- 0xFA580400, 0xFC9CF6DA, 0xF800F672, 0x0710071C,
- 0x05A805A8, 0xF8F0F8E4, 0xF800F672, 0x03640926,
- 0xFA580400, 0x0B640382, 0x0800084A, 0x00F0F942,
- 0x05A80000, 0xFF10F942, 0x0800F7B6, 0xF49C0382,
- 0xFA58FC00, 0xFC9C0926, 0xF800098E, 0x0710F8E4,
- 0x05A8FA58, 0xF8F0071C, 0xF800098E, 0x0364F6DA,
- 0xFA58FC00, 0x0B64FC7E, 0x0800F7B6, 0x00F006BE,
- 0x05A80000, 0xFF1006BE, 0x0800084A, 0xF49CFC7E,
- 0xFA580400, 0xFC9CF6DA, 0xF800F672, 0x0710071C,
- 0x05A805A8, 0xF8F0F8E4, 0xF800F672, 0x03640926,
- 0xFA580400, 0x0B640382, 0x0800084A, 0x00F0F942,
- 0x05A80000, 0xFF10F942, 0x0800F7B6, 0xF49C0382,
- 0xFA58FC00, 0xFC9C0926, 0xF800098E, 0x0710F8E4,
- 0x05A8FA58, 0xF8F0071C, 0xF800098E, 0x0364F6DA,
- 0xFA58FC00, 0x0B64FC7E, 0x0800F7B6, 0x00F006BE,
-};
-
-const u32 b43_ntab_tmap[] = {
- 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888,
- 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
- 0xF1111110, 0x11111111, 0x11F11111, 0x00000111,
- 0x11000000, 0x1111F111, 0x11111111, 0x111111F1,
- 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x000AA888,
- 0x88880000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
- 0xA1111110, 0x11111111, 0x11C11111, 0x00000111,
- 0x11000000, 0x1111A111, 0x11111111, 0x111111A1,
- 0xA2222220, 0x22222222, 0x22C22222, 0x00000222,
- 0x22000000, 0x2222A222, 0x22222222, 0x222222A2,
- 0xF1111110, 0x11111111, 0x11F11111, 0x00011111,
- 0x11110000, 0x1111F111, 0x11111111, 0x111111F1,
- 0xA8AA88A0, 0xA88888A8, 0xA8A8A88A, 0x00088AAA,
- 0xAAAA0000, 0xA8A8AA88, 0xA88AAAAA, 0xAAAA8A8A,
- 0xAAA8AAA0, 0x8AAA8AAA, 0xAA8A8A8A, 0x000AAA88,
- 0x8AAA0000, 0xAAA8A888, 0x8AA88A8A, 0x8A88A888,
- 0x08080A00, 0x0A08080A, 0x080A0A08, 0x00080808,
- 0x080A0000, 0x080A0808, 0x080A0808, 0x0A0A0A08,
- 0xA0A0A0A0, 0x80A0A080, 0x8080A0A0, 0x00008080,
- 0x80A00000, 0x80A080A0, 0xA080A0A0, 0x8080A0A0,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x99999000, 0x9B9B99BB, 0x9BB99999, 0x9999B9B9,
- 0x9B99BB90, 0x9BBBBB9B, 0x9B9B9BB9, 0x00000999,
- 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
- 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00AAA888,
- 0x22000000, 0x2222B222, 0x22222222, 0x222222B2,
- 0xB2222220, 0x22222222, 0x22D22222, 0x00000222,
- 0x11000000, 0x1111A111, 0x11111111, 0x111111A1,
- 0xA1111110, 0x11111111, 0x11C11111, 0x00000111,
- 0x33000000, 0x3333B333, 0x33333333, 0x333333B3,
- 0xB3333330, 0x33333333, 0x33D33333, 0x00000333,
- 0x22000000, 0x2222A222, 0x22222222, 0x222222A2,
- 0xA2222220, 0x22222222, 0x22C22222, 0x00000222,
- 0x99B99B00, 0x9B9B99BB, 0x9BB99999, 0x9999B9B9,
- 0x9B99BB99, 0x9BBBBB9B, 0x9B9B9BB9, 0x00000999,
- 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
- 0x8A88AA88, 0x8AAAAA8A, 0x8A8A8AA8, 0x08AAA888,
- 0x22222200, 0x2222F222, 0x22222222, 0x222222F2,
- 0x22222222, 0x22222222, 0x22F22222, 0x00000222,
- 0x11000000, 0x1111F111, 0x11111111, 0x11111111,
- 0xF1111111, 0x11111111, 0x11F11111, 0x01111111,
- 0xBB9BB900, 0xB9B9BB99, 0xB99BBBBB, 0xBBBB9B9B,
- 0xB9BB99BB, 0xB99999B9, 0xB9B9B99B, 0x00000BBB,
- 0xAA000000, 0xA8A8AA88, 0xA88AAAAA, 0xAAAA8A8A,
- 0xA8AA88AA, 0xA88888A8, 0xA8A8A88A, 0x0A888AAA,
- 0xAA000000, 0xA8A8AA88, 0xA88AAAAA, 0xAAAA8A8A,
- 0xA8AA88A0, 0xA88888A8, 0xA8A8A88A, 0x00000AAA,
- 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
- 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888,
- 0xBBBBBB00, 0x999BBBBB, 0x9BB99B9B, 0xB9B9B9BB,
- 0xB9B99BBB, 0xB9B9B9BB, 0xB9BB9B99, 0x00000999,
- 0x8A000000, 0xAA88A888, 0xA88888AA, 0xA88A8A88,
- 0xA88AA88A, 0x88A8AAAA, 0xA8AA8AAA, 0x0888A88A,
- 0x0B0B0B00, 0x090B0B0B, 0x0B090B0B, 0x0909090B,
- 0x09090B0B, 0x09090B0B, 0x09090B09, 0x00000909,
- 0x0A000000, 0x0A080808, 0x080A080A, 0x080A0A08,
- 0x080A080A, 0x0808080A, 0x0A0A0A08, 0x0808080A,
- 0xB0B0B000, 0x9090B0B0, 0x90B09090, 0xB0B0B090,
- 0xB0B090B0, 0x90B0B0B0, 0xB0B09090, 0x00000090,
- 0x80000000, 0xA080A080, 0xA08080A0, 0xA0808080,
- 0xA080A080, 0x80A0A0A0, 0xA0A080A0, 0x00A0A0A0,
- 0x22000000, 0x2222F222, 0x22222222, 0x222222F2,
- 0xF2222220, 0x22222222, 0x22F22222, 0x00000222,
- 0x11000000, 0x1111F111, 0x11111111, 0x111111F1,
- 0xF1111110, 0x11111111, 0x11F11111, 0x00000111,
- 0x33000000, 0x3333F333, 0x33333333, 0x333333F3,
- 0xF3333330, 0x33333333, 0x33F33333, 0x00000333,
- 0x22000000, 0x2222F222, 0x22222222, 0x222222F2,
- 0xF2222220, 0x22222222, 0x22F22222, 0x00000222,
- 0x99000000, 0x9B9B99BB, 0x9BB99999, 0x9999B9B9,
- 0x9B99BB90, 0x9BBBBB9B, 0x9B9B9BB9, 0x00000999,
- 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
- 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888,
- 0x88888000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
- 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888,
- 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
- 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00AAA888,
- 0x88A88A00, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
- 0x8A88AA88, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888,
- 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
- 0x8A88AA88, 0x8AAAAA8A, 0x8A8A8AA8, 0x08AAA888,
- 0x11000000, 0x1111A111, 0x11111111, 0x111111A1,
- 0xA1111110, 0x11111111, 0x11C11111, 0x00000111,
- 0x11000000, 0x1111A111, 0x11111111, 0x111111A1,
- 0xA1111110, 0x11111111, 0x11C11111, 0x00000111,
- 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
- 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888,
- 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8,
- 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-};
-
-static inline void assert_ntab_array_sizes(void)
-{
-#undef check
-#define check(table, size) \
- BUILD_BUG_ON(ARRAY_SIZE(b43_ntab_##table) != B43_NTAB_##size##_SIZE)
-
- check(adjustpower0, C0_ADJPLT);
- check(adjustpower1, C1_ADJPLT);
- check(bdi, BDI);
- check(channelest, CHANEST);
- check(estimatepowerlt0, C0_ESTPLT);
- check(estimatepowerlt1, C1_ESTPLT);
- check(framelookup, FRAMELT);
- check(framestruct, FRAMESTRUCT);
- check(gainctl0, C0_GAINCTL);
- check(gainctl1, C1_GAINCTL);
- check(intlevel, INTLEVEL);
- check(iqlt0, C0_IQLT);
- check(iqlt1, C1_IQLT);
- check(loftlt0, C0_LOFEEDTH);
- check(loftlt1, C1_LOFEEDTH);
- check(mcs, MCS);
- check(noisevar10, NOISEVAR10);
- check(noisevar11, NOISEVAR11);
- check(pilot, PILOT);
- check(pilotlt, PILOTLT);
- check(tdi20a0, TDI20A0);
- check(tdi20a1, TDI20A1);
- check(tdi40a0, TDI40A0);
- check(tdi40a1, TDI40A1);
- check(tdtrn, TDTRN);
- check(tmap, TMAP);
-
-#undef check
-}
-
-void b43_ntab_write(struct b43_wldev *dev, u32 offset, u32 value)
-{
- u32 type;
-
- type = offset & B43_NTAB_TYPEMASK;
- offset &= 0xFFFF;
-
- switch (type) {
- case B43_NTAB_8BIT:
- B43_WARN_ON(value & ~0xFF);
- b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset);
- b43_phy_write(dev, B43_NPHY_TABLE_DATALO, value);
- break;
- case B43_NTAB_16BIT:
- B43_WARN_ON(value & ~0xFFFF);
- b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset);
- b43_phy_write(dev, B43_NPHY_TABLE_DATALO, value);
- break;
- case B43_NTAB_32BIT:
- b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset);
- b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, value >> 16);
- b43_phy_write(dev, B43_NPHY_TABLE_DATALO, value & 0xFFFF);
- break;
- default:
- B43_WARN_ON(1);
- }
-
- return;
-
- /* Some compiletime assertions... */
- assert_ntab_array_sizes();
-}
-#ifndef B43_TABLES_NPHY_H_
-#define B43_TABLES_NPHY_H_
-
-#include <linux/types.h>
-
-
-struct b43_nphy_channeltab_entry {
- /* The channel number */
- u8 channel;
- /* Radio register values on channelswitch */
- u8 radio_pll_ref;
- u8 radio_rf_pllmod0;
- u8 radio_rf_pllmod1;
- u8 radio_vco_captail;
- u8 radio_vco_cal1;
- u8 radio_vco_cal2;
- u8 radio_pll_lfc1;
- u8 radio_pll_lfr1;
- u8 radio_pll_lfc2;
- u8 radio_lgbuf_cenbuf;
- u8 radio_lgen_tune1;
- u8 radio_lgen_tune2;
- u8 radio_c1_lgbuf_atune;
- u8 radio_c1_lgbuf_gtune;
- u8 radio_c1_rx_rfr1;
- u8 radio_c1_tx_pgapadtn;
- u8 radio_c1_tx_mxbgtrim;
- u8 radio_c2_lgbuf_atune;
- u8 radio_c2_lgbuf_gtune;
- u8 radio_c2_rx_rfr1;
- u8 radio_c2_tx_pgapadtn;
- u8 radio_c2_tx_mxbgtrim;
- /* PHY register values on channelswitch */
- u16 phy_bw1a;
- u16 phy_bw2;
- u16 phy_bw3;
- u16 phy_bw4;
- u16 phy_bw5;
- u16 phy_bw6;
- /* The channel frequency in MHz */
- u16 freq;
- /* An unknown value */
- u16 unk2;
-};
-
-
-struct b43_wldev;
-
-/* Upload the default register value table.
- * If "ghz5" is true, we upload the 5Ghz table. Otherwise the 2.4Ghz
- * table is uploaded. If "ignore_uploadflag" is true, we upload any value
- * and ignore the "UPLOAD" flag. */
-void b2055_upload_inittab(struct b43_wldev *dev,
- bool ghz5, bool ignore_uploadflag);
-
-
-/* Get the NPHY Channel Switch Table entry for a channel number.
- * Returns NULL on failure to find an entry. */
-const struct b43_nphy_channeltab_entry *
-b43_nphy_get_chantabent(struct b43_wldev *dev, u8 channel);
-
-
-/* The N-PHY tables. */
-
-#define B43_NTAB_TYPEMASK 0xF0000000
-#define B43_NTAB_8BIT 0x10000000
-#define B43_NTAB_16BIT 0x20000000
-#define B43_NTAB_32BIT 0x30000000
-#define B43_NTAB8(table, offset) (((table) << 10) | (offset) | B43_NTAB_8BIT)
-#define B43_NTAB16(table, offset) (((table) << 10) | (offset) | B43_NTAB_16BIT)
-#define B43_NTAB32(table, offset) (((table) << 10) | (offset) | B43_NTAB_32BIT)
-
-/* Static N-PHY tables */
-#define B43_NTAB_FRAMESTRUCT B43_NTAB32(0x0A, 0x000) /* Frame Struct Table */
-#define B43_NTAB_FRAMESTRUCT_SIZE 832
-#define B43_NTAB_FRAMELT B43_NTAB8 (0x18, 0x000) /* Frame Lookup Table */
-#define B43_NTAB_FRAMELT_SIZE 32
-#define B43_NTAB_TMAP B43_NTAB32(0x0C, 0x000) /* T Map Table */
-#define B43_NTAB_TMAP_SIZE 448
-#define B43_NTAB_TDTRN B43_NTAB32(0x0E, 0x000) /* TDTRN Table */
-#define B43_NTAB_TDTRN_SIZE 704
-#define B43_NTAB_INTLEVEL B43_NTAB32(0x0D, 0x000) /* Int Level Table */
-#define B43_NTAB_INTLEVEL_SIZE 7
-#define B43_NTAB_PILOT B43_NTAB16(0x0B, 0x000) /* Pilot Table */
-#define B43_NTAB_PILOT_SIZE 88
-#define B43_NTAB_PILOTLT B43_NTAB32(0x14, 0x000) /* Pilot Lookup Table */
-#define B43_NTAB_PILOTLT_SIZE 6
-#define B43_NTAB_TDI20A0 B43_NTAB32(0x13, 0x080) /* TDI Table 20 Antenna 0 */
-#define B43_NTAB_TDI20A0_SIZE 55
-#define B43_NTAB_TDI20A1 B43_NTAB32(0x13, 0x100) /* TDI Table 20 Antenna 1 */
-#define B43_NTAB_TDI20A1_SIZE 55
-#define B43_NTAB_TDI40A0 B43_NTAB32(0x13, 0x280) /* TDI Table 40 Antenna 0 */
-#define B43_NTAB_TDI40A0_SIZE 110
-#define B43_NTAB_TDI40A1 B43_NTAB32(0x13, 0x300) /* TDI Table 40 Antenna 1 */
-#define B43_NTAB_TDI40A1_SIZE 110
-#define B43_NTAB_BDI B43_NTAB16(0x15, 0x000) /* BDI Table */
-#define B43_NTAB_BDI_SIZE 6
-#define B43_NTAB_CHANEST B43_NTAB32(0x16, 0x000) /* Channel Estimate Table */
-#define B43_NTAB_CHANEST_SIZE 96
-#define B43_NTAB_MCS B43_NTAB8 (0x12, 0x000) /* MCS Table */
-#define B43_NTAB_MCS_SIZE 128
-
-/* Volatile N-PHY tables */
-#define B43_NTAB_NOISEVAR10 B43_NTAB32(0x10, 0x000) /* Noise Var Table 10 */
-#define B43_NTAB_NOISEVAR10_SIZE 256
-#define B43_NTAB_NOISEVAR11 B43_NTAB32(0x10, 0x080) /* Noise Var Table 11 */
-#define B43_NTAB_NOISEVAR11_SIZE 256
-#define B43_NTAB_C0_ESTPLT B43_NTAB8 (0x1A, 0x000) /* Estimate Power Lookup Table Core 0 */
-#define B43_NTAB_C0_ESTPLT_SIZE 64
-#define B43_NTAB_C1_ESTPLT B43_NTAB8 (0x1B, 0x000) /* Estimate Power Lookup Table Core 1 */
-#define B43_NTAB_C1_ESTPLT_SIZE 64
-#define B43_NTAB_C0_ADJPLT B43_NTAB8 (0x1A, 0x040) /* Adjust Power Lookup Table Core 0 */
-#define B43_NTAB_C0_ADJPLT_SIZE 128
-#define B43_NTAB_C1_ADJPLT B43_NTAB8 (0x1B, 0x040) /* Adjust Power Lookup Table Core 1 */
-#define B43_NTAB_C1_ADJPLT_SIZE 128
-#define B43_NTAB_C0_GAINCTL B43_NTAB32(0x1A, 0x0C0) /* Gain Control Lookup Table Core 0 */
-#define B43_NTAB_C0_GAINCTL_SIZE 128
-#define B43_NTAB_C1_GAINCTL B43_NTAB32(0x1B, 0x0C0) /* Gain Control Lookup Table Core 1 */
-#define B43_NTAB_C1_GAINCTL_SIZE 128
-#define B43_NTAB_C0_IQLT B43_NTAB32(0x1A, 0x140) /* IQ Lookup Table Core 0 */
-#define B43_NTAB_C0_IQLT_SIZE 128
-#define B43_NTAB_C1_IQLT B43_NTAB32(0x1B, 0x140) /* IQ Lookup Table Core 1 */
-#define B43_NTAB_C1_IQLT_SIZE 128
-#define B43_NTAB_C0_LOFEEDTH B43_NTAB16(0x1A, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 0 */
-#define B43_NTAB_C0_LOFEEDTH_SIZE 128
-#define B43_NTAB_C1_LOFEEDTH B43_NTAB16(0x1B, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 1 */
-#define B43_NTAB_C1_LOFEEDTH_SIZE 128
-
-void b43_ntab_write(struct b43_wldev *dev, u32 offset, u32 value);
-
-extern const u8 b43_ntab_adjustpower0[];
-extern const u8 b43_ntab_adjustpower1[];
-extern const u16 b43_ntab_bdi[];
-extern const u32 b43_ntab_channelest[];
-extern const u8 b43_ntab_estimatepowerlt0[];
-extern const u8 b43_ntab_estimatepowerlt1[];
-extern const u8 b43_ntab_framelookup[];
-extern const u32 b43_ntab_framestruct[];
-extern const u32 b43_ntab_gainctl0[];
-extern const u32 b43_ntab_gainctl1[];
-extern const u32 b43_ntab_intlevel[];
-extern const u32 b43_ntab_iqlt0[];
-extern const u32 b43_ntab_iqlt1[];
-extern const u16 b43_ntab_loftlt0[];
-extern const u16 b43_ntab_loftlt1[];
-extern const u8 b43_ntab_mcs[];
-extern const u32 b43_ntab_noisevar10[];
-extern const u32 b43_ntab_noisevar11[];
-extern const u16 b43_ntab_pilot[];
-extern const u32 b43_ntab_pilotlt[];
-extern const u32 b43_ntab_tdi20a0[];
-extern const u32 b43_ntab_tdi20a1[];
-extern const u32 b43_ntab_tdi40a0[];
-extern const u32 b43_ntab_tdi40a1[];
-extern const u32 b43_ntab_tdtrn[];
-extern const u32 b43_ntab_tmap[];
-
-
-#endif /* B43_TABLES_NPHY_H_ */
-/*
-
- Broadcom B43 wireless driver
-
- PHY workarounds.
-
- Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
- Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; see the file COPYING. If not, write to
- the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
- Boston, MA 02110-1301, USA.
-
-*/
-
-#include "b43.h"
-#include "main.h"
-#include "tables.h"
-#include "phy.h"
-#include "wa.h"
-
-static void b43_wa_papd(struct b43_wldev *dev)
-{
- u16 backup;
-
- backup = b43_ofdmtab_read16(dev, B43_OFDMTAB_PWRDYN2, 0);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_PWRDYN2, 0, 7);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_APHY, 0, 0);
- b43_dummy_transmission(dev);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_PWRDYN2, 0, backup);
-}
-
-static void b43_wa_auxclipthr(struct b43_wldev *dev)
-{
- b43_phy_write(dev, B43_PHY_OFDM(0x8E), 0x3800);
-}
-
-static void b43_wa_afcdac(struct b43_wldev *dev)
-{
- b43_phy_write(dev, 0x0035, 0x03FF);
- b43_phy_write(dev, 0x0036, 0x0400);
-}
-
-static void b43_wa_txdc_offset(struct b43_wldev *dev)
-{
- b43_ofdmtab_write16(dev, B43_OFDMTAB_DC, 0, 0x0051);
-}
-
-void b43_wa_initgains(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
-
- b43_phy_write(dev, B43_PHY_LNAHPFCTL, 0x1FF9);
- b43_phy_write(dev, B43_PHY_LPFGAINCTL,
- b43_phy_read(dev, B43_PHY_LPFGAINCTL) & 0xFF0F);
- if (phy->rev <= 2)
- b43_ofdmtab_write16(dev, B43_OFDMTAB_LPFGAIN, 0, 0x1FBF);
- b43_radio_write16(dev, 0x0002, 0x1FBF);
-
- b43_phy_write(dev, 0x0024, 0x4680);
- b43_phy_write(dev, 0x0020, 0x0003);
- b43_phy_write(dev, 0x001D, 0x0F40);
- b43_phy_write(dev, 0x001F, 0x1C00);
- if (phy->rev <= 3)
- b43_phy_write(dev, 0x002A,
- (b43_phy_read(dev, 0x002A) & 0x00FF) | 0x0400);
- else if (phy->rev == 5) {
- b43_phy_write(dev, 0x002A,
- (b43_phy_read(dev, 0x002A) & 0x00FF) | 0x1A00);
- b43_phy_write(dev, 0x00CC, 0x2121);
- }
- if (phy->rev >= 3)
- b43_phy_write(dev, 0x00BA, 0x3ED5);
-}
-
-static void b43_wa_divider(struct b43_wldev *dev)
-{
- b43_phy_write(dev, 0x002B, b43_phy_read(dev, 0x002B) & ~0x0100);
- b43_phy_write(dev, 0x008E, 0x58C1);
-}
-
-static void b43_wa_gt(struct b43_wldev *dev) /* Gain table. */
-{
- if (dev->phy.rev <= 2) {
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 0, 15);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 1, 31);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 2, 42);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 3, 48);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 4, 58);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 0, 19);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 1, 19);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 2, 19);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 3, 19);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 4, 21);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 5, 21);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 6, 25);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN1, 0, 3);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN1, 1, 3);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN1, 2, 7);
- } else {
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 0, 19);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 1, 19);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 2, 19);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 3, 19);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 4, 21);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 5, 21);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 6, 25);
- }
-}
-
-static void b43_wa_rssi_lt(struct b43_wldev *dev) /* RSSI lookup table */
-{
- int i;
-
- if (0 /* FIXME: For APHY.rev=2 this might be needed */) {
- for (i = 0; i < 8; i++)
- b43_ofdmtab_write16(dev, B43_OFDMTAB_RSSI, i, i + 8);
- for (i = 8; i < 16; i++)
- b43_ofdmtab_write16(dev, B43_OFDMTAB_RSSI, i, i - 8);
- } else {
- for (i = 0; i < 64; i++)
- b43_ofdmtab_write16(dev, B43_OFDMTAB_RSSI, i, i);
- }
-}
-
-static void b43_wa_analog(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
- u16 ofdmrev;
-
- ofdmrev = b43_phy_read(dev, B43_PHY_VERSION_OFDM) & B43_PHYVER_VERSION;
- if (ofdmrev > 2) {
- if (phy->type == B43_PHYTYPE_A)
- b43_phy_write(dev, B43_PHY_PWRDOWN, 0x1808);
- else
- b43_phy_write(dev, B43_PHY_PWRDOWN, 0x1000);
- } else {
- b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 3, 0x1044);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 4, 0x7201);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 6, 0x0040);
- }
-}
-
-static void b43_wa_dac(struct b43_wldev *dev)
-{
- if (dev->phy.analog == 1)
- b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 1,
- (b43_ofdmtab_read16(dev, B43_OFDMTAB_DAC, 1) & ~0x0034) | 0x0008);
- else
- b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 1,
- (b43_ofdmtab_read16(dev, B43_OFDMTAB_DAC, 1) & ~0x0078) | 0x0010);
-}
-
-static void b43_wa_fft(struct b43_wldev *dev) /* Fine frequency table */
-{
- int i;
-
- if (dev->phy.type == B43_PHYTYPE_A)
- for (i = 0; i < B43_TAB_FINEFREQA_SIZE; i++)
- b43_ofdmtab_write16(dev, B43_OFDMTAB_DACRFPABB, i, b43_tab_finefreqa[i]);
- else
- for (i = 0; i < B43_TAB_FINEFREQG_SIZE; i++)
- b43_ofdmtab_write16(dev, B43_OFDMTAB_DACRFPABB, i, b43_tab_finefreqg[i]);
-}
-
-static void b43_wa_nft(struct b43_wldev *dev) /* Noise figure table */
-{
- struct b43_phy *phy = &dev->phy;
- int i;
-
- if (phy->type == B43_PHYTYPE_A) {
- if (phy->rev == 2)
- for (i = 0; i < B43_TAB_NOISEA2_SIZE; i++)
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noisea2[i]);
- else
- for (i = 0; i < B43_TAB_NOISEA3_SIZE; i++)
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noisea3[i]);
- } else {
- if (phy->rev == 1)
- for (i = 0; i < B43_TAB_NOISEG1_SIZE; i++)
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noiseg1[i]);
- else
- for (i = 0; i < B43_TAB_NOISEG2_SIZE; i++)
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noiseg2[i]);
- }
-}
-
-static void b43_wa_rt(struct b43_wldev *dev) /* Rotor table */
-{
- int i;
-
- for (i = 0; i < B43_TAB_ROTOR_SIZE; i++)
- b43_ofdmtab_write32(dev, B43_OFDMTAB_ROTOR, i, b43_tab_rotor[i]);
-}
-
-static void b43_write_null_nst(struct b43_wldev *dev)
-{
- int i;
-
- for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
- b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE, i, 0);
-}
-
-static void b43_write_nst(struct b43_wldev *dev, const u16 *nst)
-{
- int i;
-
- for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
- b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE, i, nst[i]);
-}
-
-static void b43_wa_nst(struct b43_wldev *dev) /* Noise scale table */
-{
- struct b43_phy *phy = &dev->phy;
-
- if (phy->type == B43_PHYTYPE_A) {
- if (phy->rev <= 1)
- b43_write_null_nst(dev);
- else if (phy->rev == 2)
- b43_write_nst(dev, b43_tab_noisescalea2);
- else if (phy->rev == 3)
- b43_write_nst(dev, b43_tab_noisescalea3);
- else
- b43_write_nst(dev, b43_tab_noisescaleg3);
- } else {
- if (phy->rev >= 6) {
- if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN)
- b43_write_nst(dev, b43_tab_noisescaleg3);
- else
- b43_write_nst(dev, b43_tab_noisescaleg2);
- } else {
- b43_write_nst(dev, b43_tab_noisescaleg1);
- }
- }
-}
-
-static void b43_wa_art(struct b43_wldev *dev) /* ADV retard table */
-{
- int i;
-
- for (i = 0; i < B43_TAB_RETARD_SIZE; i++)
- b43_ofdmtab_write32(dev, B43_OFDMTAB_ADVRETARD,
- i, b43_tab_retard[i]);
-}
-
-static void b43_wa_txlna_gain(struct b43_wldev *dev)
-{
- b43_ofdmtab_write16(dev, B43_OFDMTAB_DC, 13, 0x0000);
-}
-
-static void b43_wa_crs_reset(struct b43_wldev *dev)
-{
- b43_phy_write(dev, 0x002C, 0x0064);
-}
-
-static void b43_wa_2060txlna_gain(struct b43_wldev *dev)
-{
- b43_hf_write(dev, b43_hf_read(dev) |
- B43_HF_2060W);
-}
-
-static void b43_wa_lms(struct b43_wldev *dev)
-{
- b43_phy_write(dev, 0x0055,
- (b43_phy_read(dev, 0x0055) & 0xFFC0) | 0x0004);
-}
-
-static void b43_wa_mixedsignal(struct b43_wldev *dev)
-{
- b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 1, 3);
-}
-
-static void b43_wa_msst(struct b43_wldev *dev) /* Min sigma square table */
-{
- struct b43_phy *phy = &dev->phy;
- int i;
- const u16 *tab;
-
- if (phy->type == B43_PHYTYPE_A) {
- tab = b43_tab_sigmasqr1;
- } else if (phy->type == B43_PHYTYPE_G) {
- tab = b43_tab_sigmasqr2;
- } else {
- B43_WARN_ON(1);
- return;
- }
-
- for (i = 0; i < B43_TAB_SIGMASQR_SIZE; i++) {
- b43_ofdmtab_write16(dev, B43_OFDMTAB_MINSIGSQ,
- i, tab[i]);
- }
-}
-
-static void b43_wa_iqadc(struct b43_wldev *dev)
-{
- if (dev->phy.analog == 4)
- b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 0,
- b43_ofdmtab_read16(dev, B43_OFDMTAB_DAC, 0) & ~0xF000);
-}
-
-static void b43_wa_crs_ed(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
-
- if (phy->rev == 1) {
- b43_phy_write(dev, B43_PHY_CRSTHRES1_R1, 0x4F19);
- } else if (phy->rev == 2) {
- b43_phy_write(dev, B43_PHY_CRSTHRES1, 0x1861);
- b43_phy_write(dev, B43_PHY_CRSTHRES2, 0x0271);
- b43_phy_write(dev, B43_PHY_ANTDWELL,
- b43_phy_read(dev, B43_PHY_ANTDWELL)
- | 0x0800);
- } else {
- b43_phy_write(dev, B43_PHY_CRSTHRES1, 0x0098);
- b43_phy_write(dev, B43_PHY_CRSTHRES2, 0x0070);
- b43_phy_write(dev, B43_PHY_OFDM(0xC9), 0x0080);
- b43_phy_write(dev, B43_PHY_ANTDWELL,
- b43_phy_read(dev, B43_PHY_ANTDWELL)
- | 0x0800);
- }
-}
-
-static void b43_wa_crs_thr(struct b43_wldev *dev)
-{
- b43_phy_write(dev, B43_PHY_CRS0,
- (b43_phy_read(dev, B43_PHY_CRS0) & ~0x03C0) | 0xD000);
-}
-
-static void b43_wa_crs_blank(struct b43_wldev *dev)
-{
- b43_phy_write(dev, B43_PHY_OFDM(0x2C), 0x005A);
-}
-
-static void b43_wa_cck_shiftbits(struct b43_wldev *dev)
-{
- b43_phy_write(dev, B43_PHY_CCKSHIFTBITS, 0x0026);
-}
-
-static void b43_wa_wrssi_offset(struct b43_wldev *dev)
-{
- int i;
-
- if (dev->phy.rev == 1) {
- for (i = 0; i < 16; i++) {
- b43_ofdmtab_write16(dev, B43_OFDMTAB_WRSSI_R1,
- i, 0x0020);
- }
- } else {
- for (i = 0; i < 32; i++) {
- b43_ofdmtab_write16(dev, B43_OFDMTAB_WRSSI,
- i, 0x0820);
- }
- }
-}
-
-static void b43_wa_txpuoff_rxpuon(struct b43_wldev *dev)
-{
- b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_0F, 2, 15);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_0F, 3, 20);
-}
-
-static void b43_wa_altagc(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
-
- if (phy->rev == 1) {
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 254);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 1, 13);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 2, 19);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 3, 25);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 0, 0x2710);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 1, 0x9B83);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 2, 0x9B83);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 3, 0x0F8D);
- b43_phy_write(dev, B43_PHY_LMS, 4);
- } else {
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0, 254);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 1, 13);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 2, 19);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 3, 25);
- }
-
- b43_phy_write(dev, B43_PHY_CCKSHIFTBITS_WA,
- (b43_phy_read(dev, B43_PHY_CCKSHIFTBITS_WA) & ~0xFF00) | 0x5700);
- b43_phy_write(dev, B43_PHY_OFDM(0x1A),
- (b43_phy_read(dev, B43_PHY_OFDM(0x1A)) & ~0x007F) | 0x000F);
- b43_phy_write(dev, B43_PHY_OFDM(0x1A),
- (b43_phy_read(dev, B43_PHY_OFDM(0x1A)) & ~0x3F80) | 0x2B80);
- b43_phy_write(dev, B43_PHY_ANTWRSETT,
- (b43_phy_read(dev, B43_PHY_ANTWRSETT) & 0xF0FF) | 0x0300);
- b43_radio_write16(dev, 0x7A,
- b43_radio_read16(dev, 0x7A) | 0x0008);
- b43_phy_write(dev, B43_PHY_N1P1GAIN,
- (b43_phy_read(dev, B43_PHY_N1P1GAIN) & ~0x000F) | 0x0008);
- b43_phy_write(dev, B43_PHY_P1P2GAIN,
- (b43_phy_read(dev, B43_PHY_P1P2GAIN) & ~0x0F00) | 0x0600);
- b43_phy_write(dev, B43_PHY_N1N2GAIN,
- (b43_phy_read(dev, B43_PHY_N1N2GAIN) & ~0x0F00) | 0x0700);
- b43_phy_write(dev, B43_PHY_N1P1GAIN,
- (b43_phy_read(dev, B43_PHY_N1P1GAIN) & ~0x0F00) | 0x0100);
- if (phy->rev == 1) {
- b43_phy_write(dev, B43_PHY_N1N2GAIN,
- (b43_phy_read(dev, B43_PHY_N1N2GAIN)
- & ~0x000F) | 0x0007);
- }
- b43_phy_write(dev, B43_PHY_OFDM(0x88),
- (b43_phy_read(dev, B43_PHY_OFDM(0x88)) & ~0x00FF) | 0x001C);
- b43_phy_write(dev, B43_PHY_OFDM(0x88),
- (b43_phy_read(dev, B43_PHY_OFDM(0x88)) & ~0x3F00) | 0x0200);
- b43_phy_write(dev, B43_PHY_OFDM(0x96),
- (b43_phy_read(dev, B43_PHY_OFDM(0x96)) & ~0x00FF) | 0x001C);
- b43_phy_write(dev, B43_PHY_OFDM(0x89),
- (b43_phy_read(dev, B43_PHY_OFDM(0x89)) & ~0x00FF) | 0x0020);
- b43_phy_write(dev, B43_PHY_OFDM(0x89),
- (b43_phy_read(dev, B43_PHY_OFDM(0x89)) & ~0x3F00) | 0x0200);
- b43_phy_write(dev, B43_PHY_OFDM(0x82),
- (b43_phy_read(dev, B43_PHY_OFDM(0x82)) & ~0x00FF) | 0x002E);
- b43_phy_write(dev, B43_PHY_OFDM(0x96),
- (b43_phy_read(dev, B43_PHY_OFDM(0x96)) & ~0xFF00) | 0x1A00);
- b43_phy_write(dev, B43_PHY_OFDM(0x81),
- (b43_phy_read(dev, B43_PHY_OFDM(0x81)) & ~0x00FF) | 0x0028);
- b43_phy_write(dev, B43_PHY_OFDM(0x81),
- (b43_phy_read(dev, B43_PHY_OFDM(0x81)) & ~0xFF00) | 0x2C00);
- if (phy->rev == 1) {
- b43_phy_write(dev, B43_PHY_PEAK_COUNT, 0x092B);
- b43_phy_write(dev, B43_PHY_OFDM(0x1B),
- (b43_phy_read(dev, B43_PHY_OFDM(0x1B)) & ~0x001E) | 0x0002);
- } else {
- b43_phy_write(dev, B43_PHY_OFDM(0x1B),
- b43_phy_read(dev, B43_PHY_OFDM(0x1B)) & ~0x001E);
- b43_phy_write(dev, B43_PHY_OFDM(0x1F), 0x287A);
- b43_phy_write(dev, B43_PHY_LPFGAINCTL,
- (b43_phy_read(dev, B43_PHY_LPFGAINCTL) & ~0x000F) | 0x0004);
- if (phy->rev >= 6) {
- b43_phy_write(dev, B43_PHY_OFDM(0x22), 0x287A);
- b43_phy_write(dev, B43_PHY_LPFGAINCTL,
- (b43_phy_read(dev, B43_PHY_LPFGAINCTL) & ~0xF000) | 0x3000);
- }
- }
- b43_phy_write(dev, B43_PHY_DIVSRCHIDX,
- (b43_phy_read(dev, B43_PHY_DIVSRCHIDX) & 0x8080) | 0x7874);
- b43_phy_write(dev, B43_PHY_OFDM(0x8E), 0x1C00);
- if (phy->rev == 1) {
- b43_phy_write(dev, B43_PHY_DIVP1P2GAIN,
- (b43_phy_read(dev, B43_PHY_DIVP1P2GAIN) & ~0x0F00) | 0x0600);
- b43_phy_write(dev, B43_PHY_OFDM(0x8B), 0x005E);
- b43_phy_write(dev, B43_PHY_ANTWRSETT,
- (b43_phy_read(dev, B43_PHY_ANTWRSETT) & ~0x00FF) | 0x001E);
- b43_phy_write(dev, B43_PHY_OFDM(0x8D), 0x0002);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 0, 0);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 1, 7);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 2, 16);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 3, 28);
- } else {
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 0, 0);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 1, 7);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 2, 16);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 3, 28);
- }
- if (phy->rev >= 6) {
- b43_phy_write(dev, B43_PHY_OFDM(0x26),
- b43_phy_read(dev, B43_PHY_OFDM(0x26)) & ~0x0003);
- b43_phy_write(dev, B43_PHY_OFDM(0x26),
- b43_phy_read(dev, B43_PHY_OFDM(0x26)) & ~0x1000);
- }
- b43_phy_read(dev, B43_PHY_VERSION_OFDM); /* Dummy read */
-}
-
-static void b43_wa_tr_ltov(struct b43_wldev *dev) /* TR Lookup Table Original Values */
-{
- b43_gtab_write(dev, B43_GTAB_ORIGTR, 0, 0xC480);
-}
-
-static void b43_wa_cpll_nonpilot(struct b43_wldev *dev)
-{
- b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_11, 0, 0);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_11, 1, 0);
-}
-
-static void b43_wa_rssi_adc(struct b43_wldev *dev)
-{
- if (dev->phy.analog == 4)
- b43_phy_write(dev, 0x00DC, 0x7454);
-}
-
-static void b43_wa_boards_a(struct b43_wldev *dev)
-{
- struct ssb_bus *bus = dev->dev->bus;
-
- if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
- bus->boardinfo.type == SSB_BOARD_BU4306 &&
- bus->boardinfo.rev < 0x30) {
- b43_phy_write(dev, 0x0010, 0xE000);
- b43_phy_write(dev, 0x0013, 0x0140);
- b43_phy_write(dev, 0x0014, 0x0280);
- } else {
- if (bus->boardinfo.type == SSB_BOARD_MP4318 &&
- bus->boardinfo.rev < 0x20) {
- b43_phy_write(dev, 0x0013, 0x0210);
- b43_phy_write(dev, 0x0014, 0x0840);
- } else {
- b43_phy_write(dev, 0x0013, 0x0140);
- b43_phy_write(dev, 0x0014, 0x0280);
- }
- if (dev->phy.rev <= 4)
- b43_phy_write(dev, 0x0010, 0xE000);
- else
- b43_phy_write(dev, 0x0010, 0x2000);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_DC, 1, 0x0039);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_APHY, 7, 0x0040);
- }
-}
-
-static void b43_wa_boards_g(struct b43_wldev *dev)
-{
- struct ssb_bus *bus = dev->dev->bus;
- struct b43_phy *phy = &dev->phy;
-
- if (bus->boardinfo.vendor != SSB_BOARDVENDOR_BCM ||
- bus->boardinfo.type != SSB_BOARD_BU4306 ||
- bus->boardinfo.rev != 0x17) {
- if (phy->rev < 2) {
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX_R1, 1, 0x0002);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX_R1, 2, 0x0001);
- } else {
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 1, 0x0002);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 2, 0x0001);
- if ((bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
- (phy->rev >= 7)) {
- b43_phy_write(dev, B43_PHY_EXTG(0x11),
- b43_phy_read(dev, B43_PHY_EXTG(0x11)) & 0xF7FF);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0020, 0x0001);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0021, 0x0001);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0022, 0x0001);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0023, 0x0000);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0000, 0x0000);
- b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0003, 0x0002);
- }
- }
- }
- if (bus->sprom.boardflags_lo & B43_BFL_FEM) {
- b43_phy_write(dev, B43_PHY_GTABCTL, 0x3120);
- b43_phy_write(dev, B43_PHY_GTABDATA, 0xC480);
- }
-}
-
-void b43_wa_all(struct b43_wldev *dev)
-{
- struct b43_phy *phy = &dev->phy;
-
- if (phy->type == B43_PHYTYPE_A) {
- switch (phy->rev) {
- case 2:
- b43_wa_papd(dev);
- b43_wa_auxclipthr(dev);
- b43_wa_afcdac(dev);
- b43_wa_txdc_offset(dev);
- b43_wa_initgains(dev);
- b43_wa_divider(dev);
- b43_wa_gt(dev);
- b43_wa_rssi_lt(dev);
- b43_wa_analog(dev);
- b43_wa_dac(dev);
- b43_wa_fft(dev);
- b43_wa_nft(dev);
- b43_wa_rt(dev);
- b43_wa_nst(dev);
- b43_wa_art(dev);
- b43_wa_txlna_gain(dev);
- b43_wa_crs_reset(dev);
- b43_wa_2060txlna_gain(dev);
- b43_wa_lms(dev);
- break;
- case 3:
- b43_wa_papd(dev);
- b43_wa_mixedsignal(dev);
- b43_wa_rssi_lt(dev);
- b43_wa_txdc_offset(dev);
- b43_wa_initgains(dev);
- b43_wa_dac(dev);
- b43_wa_nft(dev);
- b43_wa_nst(dev);
- b43_wa_msst(dev);
- b43_wa_analog(dev);
- b43_wa_gt(dev);
- b43_wa_txpuoff_rxpuon(dev);
- b43_wa_txlna_gain(dev);
- break;
- case 5:
- b43_wa_iqadc(dev);
- case 6:
- b43_wa_papd(dev);
- b43_wa_rssi_lt(dev);
- b43_wa_txdc_offset(dev);
- b43_wa_initgains(dev);
- b43_wa_dac(dev);
- b43_wa_nft(dev);
- b43_wa_nst(dev);
- b43_wa_msst(dev);
- b43_wa_analog(dev);
- b43_wa_gt(dev);
- b43_wa_txpuoff_rxpuon(dev);
- b43_wa_txlna_gain(dev);
- break;
- case 7:
- b43_wa_iqadc(dev);
- b43_wa_papd(dev);
- b43_wa_rssi_lt(dev);
- b43_wa_txdc_offset(dev);
- b43_wa_initgains(dev);
- b43_wa_dac(dev);
- b43_wa_nft(dev);
- b43_wa_nst(dev);
- b43_wa_msst(dev);
- b43_wa_analog(dev);
- b43_wa_gt(dev);
- b43_wa_txpuoff_rxpuon(dev);
- b43_wa_txlna_gain(dev);
- b43_wa_rssi_adc(dev);
- default:
- B43_WARN_ON(1);
- }
- b43_wa_boards_a(dev);
- } else if (phy->type == B43_PHYTYPE_G) {
- switch (phy->rev) {
- case 1://XXX review rev1
- b43_wa_crs_ed(dev);
- b43_wa_crs_thr(dev);
- b43_wa_crs_blank(dev);
- b43_wa_cck_shiftbits(dev);
- b43_wa_fft(dev);
- b43_wa_nft(dev);
- b43_wa_rt(dev);
- b43_wa_nst(dev);
- b43_wa_art(dev);
- b43_wa_wrssi_offset(dev);
- b43_wa_altagc(dev);
- break;
- case 2:
- case 6:
- case 7:
- case 8:
- case 9:
- b43_wa_tr_ltov(dev);
- b43_wa_crs_ed(dev);
- b43_wa_rssi_lt(dev);
- b43_wa_nft(dev);
- b43_wa_nst(dev);
- b43_wa_msst(dev);
- b43_wa_wrssi_offset(dev);
- b43_wa_altagc(dev);
- b43_wa_analog(dev);
- b43_wa_txpuoff_rxpuon(dev);
- break;
- default:
- B43_WARN_ON(1);
- }
- b43_wa_boards_g(dev);
- } else { /* No N PHY support so far */
- B43_WARN_ON(1);
- }
-
- b43_wa_cpll_nonpilot(dev);
-}
-#ifndef B43_WA_H_
-#define B43_WA_H_
-
-void b43_wa_initgains(struct b43_wldev *dev);
-void b43_wa_all(struct b43_wldev *dev);
-
-#endif /* B43_WA_H_ */
-/*
-
- Broadcom B43 wireless driver
-
- Transmission (TX/RX) related functions.
-
- Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
- Copyright (C) 2005 Stefano Brivio <stefano.brivio@polimi.it>
- Copyright (C) 2005, 2006 Michael Buesch <mb@bu3sch.de>
- Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
- Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; see the file COPYING. If not, write to
- the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
- Boston, MA 02110-1301, USA.
-
-*/
-
-#include "xmit.h"
-#include "phy.h"
-#include "dma.h"
-#include "pio.h"
-
-
-/* Extract the bitrate index out of a CCK PLCP header. */
-static int b43_plcp_get_bitrate_idx_cck(struct b43_plcp_hdr6 *plcp)
-{
- switch (plcp->raw[0]) {
- case 0x0A:
- return 0;
- case 0x14:
- return 1;
- case 0x37:
- return 2;
- case 0x6E:
- return 3;
- }
- B43_WARN_ON(1);
- return -1;
-}
-
-/* Extract the bitrate index out of an OFDM PLCP header. */
-static u8 b43_plcp_get_bitrate_idx_ofdm(struct b43_plcp_hdr6 *plcp, bool aphy)
-{
- int base = aphy ? 0 : 4;
-
- switch (plcp->raw[0] & 0xF) {
- case 0xB:
- return base + 0;
- case 0xF:
- return base + 1;
- case 0xA:
- return base + 2;
- case 0xE:
- return base + 3;
- case 0x9:
- return base + 4;
- case 0xD:
- return base + 5;
- case 0x8:
- return base + 6;
- case 0xC:
- return base + 7;
- }
- B43_WARN_ON(1);
- return -1;
-}
-
-u8 b43_plcp_get_ratecode_cck(const u8 bitrate)
-{
- switch (bitrate) {
- case B43_CCK_RATE_1MB:
- return 0x0A;
- case B43_CCK_RATE_2MB:
- return 0x14;
- case B43_CCK_RATE_5MB:
- return 0x37;
- case B43_CCK_RATE_11MB:
- return 0x6E;
- }
- B43_WARN_ON(1);
- return 0;
-}
-
-u8 b43_plcp_get_ratecode_ofdm(const u8 bitrate)
-{
- switch (bitrate) {
- case B43_OFDM_RATE_6MB:
- return 0xB;
- case B43_OFDM_RATE_9MB:
- return 0xF;
- case B43_OFDM_RATE_12MB:
- return 0xA;
- case B43_OFDM_RATE_18MB:
- return 0xE;
- case B43_OFDM_RATE_24MB:
- return 0x9;
- case B43_OFDM_RATE_36MB:
- return 0xD;
- case B43_OFDM_RATE_48MB:
- return 0x8;
- case B43_OFDM_RATE_54MB:
- return 0xC;
- }
- B43_WARN_ON(1);
- return 0;
-}
-
-void b43_generate_plcp_hdr(struct b43_plcp_hdr4 *plcp,
- const u16 octets, const u8 bitrate)
-{
- __le32 *data = &(plcp->data);
- __u8 *raw = plcp->raw;
-
- if (b43_is_ofdm_rate(bitrate)) {
- u32 d;
-
- d = b43_plcp_get_ratecode_ofdm(bitrate);
- B43_WARN_ON(octets & 0xF000);
- d |= (octets << 5);
- *data = cpu_to_le32(d);
- } else {
- u32 plen;
-
- plen = octets * 16 / bitrate;
- if ((octets * 16 % bitrate) > 0) {
- plen++;
- if ((bitrate == B43_CCK_RATE_11MB)
- && ((octets * 8 % 11) < 4)) {
- raw[1] = 0x84;
- } else
- raw[1] = 0x04;
- } else
- raw[1] = 0x04;
- *data |= cpu_to_le32(plen << 16);
- raw[0] = b43_plcp_get_ratecode_cck(bitrate);
- }
-}
-
-static u8 b43_calc_fallback_rate(u8 bitrate)
-{
- switch (bitrate) {
- case B43_CCK_RATE_1MB:
- return B43_CCK_RATE_1MB;
- case B43_CCK_RATE_2MB:
- return B43_CCK_RATE_1MB;
- case B43_CCK_RATE_5MB:
- return B43_CCK_RATE_2MB;
- case B43_CCK_RATE_11MB:
- return B43_CCK_RATE_5MB;
- case B43_OFDM_RATE_6MB:
- return B43_CCK_RATE_5MB;
- case B43_OFDM_RATE_9MB:
- return B43_OFDM_RATE_6MB;
- case B43_OFDM_RATE_12MB:
- return B43_OFDM_RATE_9MB;
- case B43_OFDM_RATE_18MB:
- return B43_OFDM_RATE_12MB;
- case B43_OFDM_RATE_24MB:
- return B43_OFDM_RATE_18MB;
- case B43_OFDM_RATE_36MB:
- return B43_OFDM_RATE_24MB;
- case B43_OFDM_RATE_48MB:
- return B43_OFDM_RATE_36MB;
- case B43_OFDM_RATE_54MB:
- return B43_OFDM_RATE_48MB;
- }
- B43_WARN_ON(1);
- return 0;
-}
-
-/* Generate a TX data header. */
-int b43_generate_txhdr(struct b43_wldev *dev,
- u8 *_txhdr,
- const unsigned char *fragment_data,
- unsigned int fragment_len,
- const struct ieee80211_tx_info *info,
- u16 cookie)
-{
- struct b43_txhdr *txhdr = (struct b43_txhdr *)_txhdr;
- const struct b43_phy *phy = &dev->phy;
- const struct ieee80211_hdr *wlhdr =
- (const struct ieee80211_hdr *)fragment_data;
- int use_encryption = (!(info->flags & IEEE80211_TX_CTL_DO_NOT_ENCRYPT));
- u16 fctl = le16_to_cpu(wlhdr->frame_control);
- struct ieee80211_rate *fbrate;
- u8 rate, rate_fb;
- int rate_ofdm, rate_fb_ofdm;
- unsigned int plcp_fragment_len;
- u32 mac_ctl = 0;
- u16 phy_ctl = 0;
- u8 extra_ft = 0;
- struct ieee80211_rate *txrate;
-
- memset(txhdr, 0, sizeof(*txhdr));
-
- txrate = ieee80211_get_tx_rate(dev->wl->hw, info);
- rate = txrate ? txrate->hw_value : B43_CCK_RATE_1MB;
- rate_ofdm = b43_is_ofdm_rate(rate);
- fbrate = ieee80211_get_alt_retry_rate(dev->wl->hw, info) ? : txrate;
- rate_fb = fbrate->hw_value;
- rate_fb_ofdm = b43_is_ofdm_rate(rate_fb);
-
- if (rate_ofdm)
- txhdr->phy_rate = b43_plcp_get_ratecode_ofdm(rate);
- else
- txhdr->phy_rate = b43_plcp_get_ratecode_cck(rate);
- txhdr->mac_frame_ctl = wlhdr->frame_control;
- memcpy(txhdr->tx_receiver, wlhdr->addr1, 6);
-
- /* Calculate duration for fallback rate */
- if ((rate_fb == rate) ||
- (wlhdr->duration_id & cpu_to_le16(0x8000)) ||
- (wlhdr->duration_id == cpu_to_le16(0))) {
- /* If the fallback rate equals the normal rate or the
- * dur_id field contains an AID, CFP magic or 0,
- * use the original dur_id field. */
- txhdr->dur_fb = wlhdr->duration_id;
- } else {
- txhdr->dur_fb = ieee80211_generic_frame_duration(
- dev->wl->hw, info->control.vif, fragment_len, fbrate);
- }
-
- plcp_fragment_len = fragment_len + FCS_LEN;
- if (use_encryption) {
- u8 key_idx = info->control.hw_key->hw_key_idx;
- struct b43_key *key;
- int wlhdr_len;
- size_t iv_len;
-
- B43_WARN_ON(key_idx >= dev->max_nr_keys);
- key = &(dev->key[key_idx]);
-
- if (unlikely(!key->keyconf)) {
- /* This key is invalid. This might only happen
- * in a short timeframe after machine resume before
- * we were able to reconfigure keys.
- * Drop this packet completely. Do not transmit it
- * unencrypted to avoid leaking information. */
- return -ENOKEY;
- }
-
- /* Hardware appends ICV. */
- plcp_fragment_len += info->control.icv_len;
-
- key_idx = b43_kidx_to_fw(dev, key_idx);
- mac_ctl |= (key_idx << B43_TXH_MAC_KEYIDX_SHIFT) &
- B43_TXH_MAC_KEYIDX;
- mac_ctl |= (key->algorithm << B43_TXH_MAC_KEYALG_SHIFT) &
- B43_TXH_MAC_KEYALG;
- wlhdr_len = ieee80211_get_hdrlen(fctl);
- iv_len = min((size_t) info->control.iv_len,
- ARRAY_SIZE(txhdr->iv));
- memcpy(txhdr->iv, ((u8 *) wlhdr) + wlhdr_len, iv_len);
- }
- if (b43_is_old_txhdr_format(dev)) {
- b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)(&txhdr->old_format.plcp),
- plcp_fragment_len, rate);
- } else {
- b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)(&txhdr->new_format.plcp),
- plcp_fragment_len, rate);
- }
- b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)(&txhdr->plcp_fb),
- plcp_fragment_len, rate_fb);
-
- /* Extra Frame Types */
- if (rate_fb_ofdm)
- extra_ft |= B43_TXH_EFT_FB_OFDM;
- else
- extra_ft |= B43_TXH_EFT_FB_CCK;
-
- /* Set channel radio code. Note that the micrcode ORs 0x100 to
- * this value before comparing it to the value in SHM, if this
- * is a 5Ghz packet.
- */
- txhdr->chan_radio_code = phy->channel;
-
- /* PHY TX Control word */
- if (rate_ofdm)
- phy_ctl |= B43_TXH_PHY_ENC_OFDM;
- else
- phy_ctl |= B43_TXH_PHY_ENC_CCK;
- if (info->flags & IEEE80211_TX_CTL_SHORT_PREAMBLE)
- phy_ctl |= B43_TXH_PHY_SHORTPRMBL;
-
- switch (b43_ieee80211_antenna_sanitize(dev, info->antenna_sel_tx)) {
- case 0: /* Default */
- phy_ctl |= B43_TXH_PHY_ANT01AUTO;
- break;
- case 1: /* Antenna 0 */
- phy_ctl |= B43_TXH_PHY_ANT0;
- break;
- case 2: /* Antenna 1 */
- phy_ctl |= B43_TXH_PHY_ANT1;
- break;
- case 3: /* Antenna 2 */
- phy_ctl |= B43_TXH_PHY_ANT2;
- break;
- case 4: /* Antenna 3 */
- phy_ctl |= B43_TXH_PHY_ANT3;
- break;
- default:
- B43_WARN_ON(1);
- }
-
- /* MAC control */
- if (!(info->flags & IEEE80211_TX_CTL_NO_ACK))
- mac_ctl |= B43_TXH_MAC_ACK;
- if (!(((fctl & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_CTL) &&
- ((fctl & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_PSPOLL)))
- mac_ctl |= B43_TXH_MAC_HWSEQ;
- if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
- mac_ctl |= B43_TXH_MAC_STMSDU;
- if (phy->type == B43_PHYTYPE_A)
- mac_ctl |= B43_TXH_MAC_5GHZ;
- if (info->flags & IEEE80211_TX_CTL_LONG_RETRY_LIMIT)
- mac_ctl |= B43_TXH_MAC_LONGFRAME;
-
- /* Generate the RTS or CTS-to-self frame */
- if ((info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) ||
- (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT)) {
- unsigned int len;
- struct ieee80211_hdr *hdr;
- int rts_rate, rts_rate_fb;
- int rts_rate_ofdm, rts_rate_fb_ofdm;
- struct b43_plcp_hdr6 *plcp;
- struct ieee80211_rate *rts_cts_rate;
-
- rts_cts_rate = ieee80211_get_rts_cts_rate(dev->wl->hw, info);
-
- rts_rate = rts_cts_rate ? rts_cts_rate->hw_value : B43_CCK_RATE_1MB;
- rts_rate_ofdm = b43_is_ofdm_rate(rts_rate);
- rts_rate_fb = b43_calc_fallback_rate(rts_rate);
- rts_rate_fb_ofdm = b43_is_ofdm_rate(rts_rate_fb);
-
- if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
- struct ieee80211_cts *cts;
-
- if (b43_is_old_txhdr_format(dev)) {
- cts = (struct ieee80211_cts *)
- (txhdr->old_format.rts_frame);
- } else {
- cts = (struct ieee80211_cts *)
- (txhdr->new_format.rts_frame);
- }
- ieee80211_ctstoself_get(dev->wl->hw, info->control.vif,
- fragment_data, fragment_len,
- info, cts);
- mac_ctl |= B43_TXH_MAC_SENDCTS;
- len = sizeof(struct ieee80211_cts);
- } else {
- struct ieee80211_rts *rts;
-
- if (b43_is_old_txhdr_format(dev)) {
- rts = (struct ieee80211_rts *)
- (txhdr->old_format.rts_frame);
- } else {
- rts = (struct ieee80211_rts *)
- (txhdr->new_format.rts_frame);
- }
- ieee80211_rts_get(dev->wl->hw, info->control.vif,
- fragment_data, fragment_len,
- info, rts);
- mac_ctl |= B43_TXH_MAC_SENDRTS;
- len = sizeof(struct ieee80211_rts);
- }
- len += FCS_LEN;
-
- /* Generate the PLCP headers for the RTS/CTS frame */
- if (b43_is_old_txhdr_format(dev))
- plcp = &txhdr->old_format.rts_plcp;
- else
- plcp = &txhdr->new_format.rts_plcp;
- b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)plcp,
- len, rts_rate);
- plcp = &txhdr->rts_plcp_fb;
- b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)plcp,
- len, rts_rate_fb);
-
- if (b43_is_old_txhdr_format(dev)) {
- hdr = (struct ieee80211_hdr *)
- (&txhdr->old_format.rts_frame);
- } else {
- hdr = (struct ieee80211_hdr *)
- (&txhdr->new_format.rts_frame);
- }
- txhdr->rts_dur_fb = hdr->duration_id;
-
- if (rts_rate_ofdm) {
- extra_ft |= B43_TXH_EFT_RTS_OFDM;
- txhdr->phy_rate_rts =
- b43_plcp_get_ratecode_ofdm(rts_rate);
- } else {
- extra_ft |= B43_TXH_EFT_RTS_CCK;
- txhdr->phy_rate_rts =
- b43_plcp_get_ratecode_cck(rts_rate);
- }
- if (rts_rate_fb_ofdm)
- extra_ft |= B43_TXH_EFT_RTSFB_OFDM;
- else
- extra_ft |= B43_TXH_EFT_RTSFB_CCK;
- }
-
- /* Magic cookie */
- if (b43_is_old_txhdr_format(dev))
- txhdr->old_format.cookie = cpu_to_le16(cookie);
- else
- txhdr->new_format.cookie = cpu_to_le16(cookie);
-
- /* Apply the bitfields */
- txhdr->mac_ctl = cpu_to_le32(mac_ctl);
- txhdr->phy_ctl = cpu_to_le16(phy_ctl);
- txhdr->extra_ft = extra_ft;
-
- return 0;
-}
-
-static s8 b43_rssi_postprocess(struct b43_wldev *dev,
- u8 in_rssi, int ofdm,
- int adjust_2053, int adjust_2050)
-{
- struct b43_phy *phy = &dev->phy;
- s32 tmp;
-
- switch (phy->radio_ver) {
- case 0x2050:
- if (ofdm) {
- tmp = in_rssi;
- if (tmp > 127)
- tmp -= 256;
- tmp *= 73;
- tmp /= 64;
- if (adjust_2050)
- tmp += 25;
- else
- tmp -= 3;
- } else {
- if (dev->dev->bus->sprom.
- boardflags_lo & B43_BFL_RSSI) {
- if (in_rssi > 63)
- in_rssi = 63;
- tmp = phy->nrssi_lt[in_rssi];
- tmp = 31 - tmp;
- tmp *= -131;
- tmp /= 128;
- tmp -= 57;
- } else {
- tmp = in_rssi;
- tmp = 31 - tmp;
- tmp *= -149;
- tmp /= 128;
- tmp -= 68;
- }
- if (phy->type == B43_PHYTYPE_G && adjust_2050)
- tmp += 25;
- }
- break;
- case 0x2060:
- if (in_rssi > 127)
- tmp = in_rssi - 256;
- else
- tmp = in_rssi;
- break;
- default:
- tmp = in_rssi;
- tmp -= 11;
- tmp *= 103;
- tmp /= 64;
- if (adjust_2053)
- tmp -= 109;
- else
- tmp -= 83;
- }
-
- return (s8) tmp;
-}
-
-//TODO
-#if 0
-static s8 b43_rssinoise_postprocess(struct b43_wldev *dev, u8 in_rssi)
-{
- struct b43_phy *phy = &dev->phy;
- s8 ret;
-
- if (phy->type == B43_PHYTYPE_A) {
- //TODO: Incomplete specs.
- ret = 0;
- } else
- ret = b43_rssi_postprocess(dev, in_rssi, 0, 1, 1);
-
- return ret;
-}
-#endif
-
-void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr)
-{
- struct ieee80211_rx_status status;
- struct b43_plcp_hdr6 *plcp;
- struct ieee80211_hdr *wlhdr;
- const struct b43_rxhdr_fw4 *rxhdr = _rxhdr;
- u16 fctl;
- u16 phystat0, phystat3, chanstat, mactime;
- u32 macstat;
- u16 chanid;
- u16 phytype;
- int padding;
-
- memset(&status, 0, sizeof(status));
-
- /* Get metadata about the frame from the header. */
- phystat0 = le16_to_cpu(rxhdr->phy_status0);
- phystat3 = le16_to_cpu(rxhdr->phy_status3);
- macstat = le32_to_cpu(rxhdr->mac_status);
- mactime = le16_to_cpu(rxhdr->mac_time);
- chanstat = le16_to_cpu(rxhdr->channel);
- phytype = chanstat & B43_RX_CHAN_PHYTYPE;
-
- if (macstat & B43_RX_MAC_FCSERR)
- dev->wl->ieee_stats.dot11FCSErrorCount++;
- if (macstat & B43_RX_MAC_DECERR) {
- /* Decryption with the given key failed.
- * Drop the packet. We also won't be able to decrypt it with
- * the key in software. */
- goto drop;
- }
-
- /* Skip PLCP and padding */
- padding = (macstat & B43_RX_MAC_PADDING) ? 2 : 0;
- if (unlikely(skb->len < (sizeof(struct b43_plcp_hdr6) + padding))) {
- b43dbg(dev->wl, "RX: Packet size underrun (1)\n");
- goto drop;
- }
- plcp = (struct b43_plcp_hdr6 *)(skb->data + padding);
- skb_pull(skb, sizeof(struct b43_plcp_hdr6) + padding);
- /* The skb contains the Wireless Header + payload data now */
- if (unlikely(skb->len < (2 + 2 + 6 /*minimum hdr */ + FCS_LEN))) {
- b43dbg(dev->wl, "RX: Packet size underrun (2)\n");
- goto drop;
- }
- wlhdr = (struct ieee80211_hdr *)(skb->data);
- fctl = le16_to_cpu(wlhdr->frame_control);
-
- if (macstat & B43_RX_MAC_DEC) {
- unsigned int keyidx;
- int wlhdr_len;
-
- keyidx = ((macstat & B43_RX_MAC_KEYIDX)
- >> B43_RX_MAC_KEYIDX_SHIFT);
- /* We must adjust the key index here. We want the "physical"
- * key index, but the ucode passed it slightly different.
- */
- keyidx = b43_kidx_to_raw(dev, keyidx);
- B43_WARN_ON(keyidx >= dev->max_nr_keys);
-
- if (dev->key[keyidx].algorithm != B43_SEC_ALGO_NONE) {
- wlhdr_len = ieee80211_get_hdrlen(fctl);
- if (unlikely(skb->len < (wlhdr_len + 3))) {
- b43dbg(dev->wl,
- "RX: Packet size underrun (3)\n");
- goto drop;
- }
- status.flag |= RX_FLAG_DECRYPTED;
- }
- }
-
- /* Link quality statistics */
- status.noise = dev->stats.link_noise;
- if ((chanstat & B43_RX_CHAN_PHYTYPE) == B43_PHYTYPE_N) {
-// s8 rssi = max(rxhdr->power0, rxhdr->power1);
- //TODO: Find out what the rssi value is (dBm or percentage?)
- // and also find out what the maximum possible value is.
- // Fill status.ssi and status.signal fields.
- } else {
- status.signal = b43_rssi_postprocess(dev, rxhdr->jssi,
- (phystat0 & B43_RX_PHYST0_OFDM),
- (phystat0 & B43_RX_PHYST0_GAINCTL),
- (phystat3 & B43_RX_PHYST3_TRSTATE));
- status.qual = (rxhdr->jssi * 100) / B43_RX_MAX_SSI;
- }
-
- if (phystat0 & B43_RX_PHYST0_OFDM)
- status.rate_idx = b43_plcp_get_bitrate_idx_ofdm(plcp,
- phytype == B43_PHYTYPE_A);
- else
- status.rate_idx = b43_plcp_get_bitrate_idx_cck(plcp);
- status.antenna = !!(phystat0 & B43_RX_PHYST0_ANT);
-
- /*
- * All frames on monitor interfaces and beacons always need a full
- * 64-bit timestamp. Monitor interfaces need it for diagnostic
- * purposes and beacons for IBSS merging.
- * This code assumes we get to process the packet within 16 bits
- * of timestamp, i.e. about 65 milliseconds after the PHY received
- * the first symbol.
- */
- if (((fctl & (IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE))
- == (IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_BEACON)) ||
- dev->wl->radiotap_enabled) {
- u16 low_mactime_now;
-
- b43_tsf_read(dev, &status.mactime);
- low_mactime_now = status.mactime;
- status.mactime = status.mactime & ~0xFFFFULL;
- status.mactime += mactime;
- if (low_mactime_now <= mactime)
- status.mactime -= 0x10000;
- status.flag |= RX_FLAG_TSFT;
- }
-
- chanid = (chanstat & B43_RX_CHAN_ID) >> B43_RX_CHAN_ID_SHIFT;
- switch (chanstat & B43_RX_CHAN_PHYTYPE) {
- case B43_PHYTYPE_A:
- status.band = IEEE80211_BAND_5GHZ;
- B43_WARN_ON(1);
- /* FIXME: We don't really know which value the "chanid" contains.
- * So the following assignment might be wrong. */
- status.freq = b43_channel_to_freq_5ghz(chanid);
- break;
- case B43_PHYTYPE_G:
- status.band = IEEE80211_BAND_2GHZ;
- /* chanid is the radio channel cookie value as used
- * to tune the radio. */
- status.freq = chanid + 2400;
- break;
- case B43_PHYTYPE_N:
- /* chanid is the SHM channel cookie. Which is the plain
- * channel number in b43. */
- if (chanstat & B43_RX_CHAN_5GHZ) {
- status.band = IEEE80211_BAND_5GHZ;
- status.freq = b43_freq_to_channel_5ghz(chanid);
- } else {
- status.band = IEEE80211_BAND_2GHZ;
- status.freq = b43_freq_to_channel_2ghz(chanid);
- }
- break;
- default:
- B43_WARN_ON(1);
- goto drop;
- }
-
- dev->stats.last_rx = jiffies;
- ieee80211_rx_irqsafe(dev->wl->hw, skb, &status);
-
- return;
-drop:
- b43dbg(dev->wl, "RX: Packet dropped\n");
- dev_kfree_skb_any(skb);
-}
-
-void b43_handle_txstatus(struct b43_wldev *dev,
- const struct b43_txstatus *status)
-{
- b43_debugfs_log_txstat(dev, status);
-
- if (status->intermediate)
- return;
- if (status->for_ampdu)
- return;
- if (!status->acked)
- dev->wl->ieee_stats.dot11ACKFailureCount++;
- if (status->rts_count) {
- if (status->rts_count == 0xF) //FIXME
- dev->wl->ieee_stats.dot11RTSFailureCount++;
- else
- dev->wl->ieee_stats.dot11RTSSuccessCount++;
- }
-
- if (b43_using_pio_transfers(dev))
- b43_pio_handle_txstatus(dev, status);
- else
- b43_dma_handle_txstatus(dev, status);
-}
-
-/* Fill out the mac80211 TXstatus report based on the b43-specific
- * txstatus report data. This returns a boolean whether the frame was
- * successfully transmitted. */
-bool b43_fill_txstatus_report(struct ieee80211_tx_info *report,
- const struct b43_txstatus *status)
-{
- bool frame_success = 1;
-
- if (status->acked) {
- /* The frame was ACKed. */
- report->flags |= IEEE80211_TX_STAT_ACK;
- } else {
- /* The frame was not ACKed... */
- if (!(report->flags & IEEE80211_TX_CTL_NO_ACK)) {
- /* ...but we expected an ACK. */
- frame_success = 0;
- report->status.excessive_retries = 1;
- }
- }
- if (status->frame_count == 0) {
- /* The frame was not transmitted at all. */
- report->status.retry_count = 0;
- } else
- report->status.retry_count = status->frame_count - 1;
-
- return frame_success;
-}
-
-/* Stop any TX operation on the device (suspend the hardware queues) */
-void b43_tx_suspend(struct b43_wldev *dev)
-{
- if (b43_using_pio_transfers(dev))
- b43_pio_tx_suspend(dev);
- else
- b43_dma_tx_suspend(dev);
-}
-
-/* Resume any TX operation on the device (resume the hardware queues) */
-void b43_tx_resume(struct b43_wldev *dev)
-{
- if (b43_using_pio_transfers(dev))
- b43_pio_tx_resume(dev);
- else
- b43_dma_tx_resume(dev);
-}
-#ifndef B43_XMIT_H_
-#define B43_XMIT_H_
-
-#include "main.h"
-
-#define _b43_declare_plcp_hdr(size) \
- struct b43_plcp_hdr##size { \
- union { \
- __le32 data; \
- __u8 raw[size]; \
- } __attribute__((__packed__)); \
- } __attribute__((__packed__))
-
-/* struct b43_plcp_hdr4 */
-_b43_declare_plcp_hdr(4);
-/* struct b43_plcp_hdr6 */
-_b43_declare_plcp_hdr(6);
-
-#undef _b43_declare_plcp_hdr
-
-/* TX header for v4 firmware */
-struct b43_txhdr {
- __le32 mac_ctl; /* MAC TX control */
- __le16 mac_frame_ctl; /* Copy of the FrameControl field */
- __le16 tx_fes_time_norm; /* TX FES Time Normal */
- __le16 phy_ctl; /* PHY TX control */
- __le16 phy_ctl1; /* PHY TX control word 1 */
- __le16 phy_ctl1_fb; /* PHY TX control word 1 for fallback rates */
- __le16 phy_ctl1_rts; /* PHY TX control word 1 RTS */
- __le16 phy_ctl1_rts_fb; /* PHY TX control word 1 RTS for fallback rates */
- __u8 phy_rate; /* PHY rate */
- __u8 phy_rate_rts; /* PHY rate for RTS/CTS */
- __u8 extra_ft; /* Extra Frame Types */
- __u8 chan_radio_code; /* Channel Radio Code */
- __u8 iv[16]; /* Encryption IV */
- __u8 tx_receiver[6]; /* TX Frame Receiver address */
- __le16 tx_fes_time_fb; /* TX FES Time Fallback */
- struct b43_plcp_hdr6 rts_plcp_fb; /* RTS fallback PLCP header */
- __le16 rts_dur_fb; /* RTS fallback duration */
- struct b43_plcp_hdr6 plcp_fb; /* Fallback PLCP header */
- __le16 dur_fb; /* Fallback duration */
- __le16 mimo_modelen; /* MIMO mode length */
- __le16 mimo_ratelen_fb; /* MIMO fallback rate length */
- __le32 timeout; /* Timeout */
-
- union {
- /* The new r410 format. */
- struct {
- __le16 mimo_antenna; /* MIMO antenna select */
- __le16 preload_size; /* Preload size */
- PAD_BYTES(2);
- __le16 cookie; /* TX frame cookie */
- __le16 tx_status; /* TX status */
- struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */
- __u8 rts_frame[16]; /* The RTS frame (if used) */
- PAD_BYTES(2);
- struct b43_plcp_hdr6 plcp; /* Main PLCP header */
- } new_format __attribute__ ((__packed__));
-
- /* The old r351 format. */
- struct {
- PAD_BYTES(2);
- __le16 cookie; /* TX frame cookie */
- __le16 tx_status; /* TX status */
- struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */
- __u8 rts_frame[16]; /* The RTS frame (if used) */
- PAD_BYTES(2);
- struct b43_plcp_hdr6 plcp; /* Main PLCP header */
- } old_format __attribute__ ((__packed__));
-
- } __attribute__ ((__packed__));
-} __attribute__ ((__packed__));
-
-/* MAC TX control */
-#define B43_TXH_MAC_USEFBR 0x10000000 /* Use fallback rate for this AMPDU */
-#define B43_TXH_MAC_KEYIDX 0x0FF00000 /* Security key index */
-#define B43_TXH_MAC_KEYIDX_SHIFT 20
-#define B43_TXH_MAC_KEYALG 0x00070000 /* Security key algorithm */
-#define B43_TXH_MAC_KEYALG_SHIFT 16
-#define B43_TXH_MAC_AMIC 0x00008000 /* AMIC */
-#define B43_TXH_MAC_RIFS 0x00004000 /* Use RIFS */
-#define B43_TXH_MAC_LIFETIME 0x00002000 /* Lifetime */
-#define B43_TXH_MAC_FRAMEBURST 0x00001000 /* Frameburst */
-#define B43_TXH_MAC_SENDCTS 0x00000800 /* Send CTS-to-self */
-#define B43_TXH_MAC_AMPDU 0x00000600 /* AMPDU status */
-#define B43_TXH_MAC_AMPDU_MPDU 0x00000000 /* Regular MPDU, not an AMPDU */
-#define B43_TXH_MAC_AMPDU_FIRST 0x00000200 /* First MPDU or AMPDU */
-#define B43_TXH_MAC_AMPDU_INTER 0x00000400 /* Intermediate MPDU or AMPDU */
-#define B43_TXH_MAC_AMPDU_LAST 0x00000600 /* Last (or only) MPDU of AMPDU */
-#define B43_TXH_MAC_40MHZ 0x00000100 /* Use 40 MHz bandwidth */
-#define B43_TXH_MAC_5GHZ 0x00000080 /* 5GHz band */
-#define B43_TXH_MAC_DFCS 0x00000040 /* DFCS */
-#define B43_TXH_MAC_IGNPMQ 0x00000020 /* Ignore PMQ */
-#define B43_TXH_MAC_HWSEQ 0x00000010 /* Use Hardware Sequence Number */
-#define B43_TXH_MAC_STMSDU 0x00000008 /* Start MSDU */
-#define B43_TXH_MAC_SENDRTS 0x00000004 /* Send RTS */
-#define B43_TXH_MAC_LONGFRAME 0x00000002 /* Long frame */
-#define B43_TXH_MAC_ACK 0x00000001 /* Immediate ACK */
-
-/* Extra Frame Types */
-#define B43_TXH_EFT_FB 0x03 /* Data frame fallback encoding */
-#define B43_TXH_EFT_FB_CCK 0x00 /* CCK */
-#define B43_TXH_EFT_FB_OFDM 0x01 /* OFDM */
-#define B43_TXH_EFT_FB_EWC 0x02 /* EWC */
-#define B43_TXH_EFT_FB_N 0x03 /* N */
-#define B43_TXH_EFT_RTS 0x0C /* RTS/CTS encoding */
-#define B43_TXH_EFT_RTS_CCK 0x00 /* CCK */
-#define B43_TXH_EFT_RTS_OFDM 0x04 /* OFDM */
-#define B43_TXH_EFT_RTS_EWC 0x08 /* EWC */
-#define B43_TXH_EFT_RTS_N 0x0C /* N */
-#define B43_TXH_EFT_RTSFB 0x30 /* RTS/CTS fallback encoding */
-#define B43_TXH_EFT_RTSFB_CCK 0x00 /* CCK */
-#define B43_TXH_EFT_RTSFB_OFDM 0x10 /* OFDM */
-#define B43_TXH_EFT_RTSFB_EWC 0x20 /* EWC */
-#define B43_TXH_EFT_RTSFB_N 0x30 /* N */
-
-/* PHY TX control word */
-#define B43_TXH_PHY_ENC 0x0003 /* Data frame encoding */
-#define B43_TXH_PHY_ENC_CCK 0x0000 /* CCK */
-#define B43_TXH_PHY_ENC_OFDM 0x0001 /* OFDM */
-#define B43_TXH_PHY_ENC_EWC 0x0002 /* EWC */
-#define B43_TXH_PHY_ENC_N 0x0003 /* N */
-#define B43_TXH_PHY_SHORTPRMBL 0x0010 /* Use short preamble */
-#define B43_TXH_PHY_ANT 0x03C0 /* Antenna selection */
-#define B43_TXH_PHY_ANT0 0x0000 /* Use antenna 0 */
-#define B43_TXH_PHY_ANT1 0x0040 /* Use antenna 1 */
-#define B43_TXH_PHY_ANT01AUTO 0x00C0 /* Use antenna 0/1 auto */
-#define B43_TXH_PHY_ANT2 0x0100 /* Use antenna 2 */
-#define B43_TXH_PHY_ANT3 0x0200 /* Use antenna 3 */
-#define B43_TXH_PHY_TXPWR 0xFC00 /* TX power */
-#define B43_TXH_PHY_TXPWR_SHIFT 10
-
-/* PHY TX control word 1 */
-#define B43_TXH_PHY1_BW 0x0007 /* Bandwidth */
-#define B43_TXH_PHY1_BW_10 0x0000 /* 10 MHz */
-#define B43_TXH_PHY1_BW_10U 0x0001 /* 10 MHz upper */
-#define B43_TXH_PHY1_BW_20 0x0002 /* 20 MHz */
-#define B43_TXH_PHY1_BW_20U 0x0003 /* 20 MHz upper */
-#define B43_TXH_PHY1_BW_40 0x0004 /* 40 MHz */
-#define B43_TXH_PHY1_BW_40DUP 0x0005 /* 50 MHz duplicate */
-#define B43_TXH_PHY1_MODE 0x0038 /* Mode */
-#define B43_TXH_PHY1_MODE_SISO 0x0000 /* SISO */
-#define B43_TXH_PHY1_MODE_CDD 0x0008 /* CDD */
-#define B43_TXH_PHY1_MODE_STBC 0x0010 /* STBC */
-#define B43_TXH_PHY1_MODE_SDM 0x0018 /* SDM */
-#define B43_TXH_PHY1_CRATE 0x0700 /* Coding rate */
-#define B43_TXH_PHY1_CRATE_1_2 0x0000 /* 1/2 */
-#define B43_TXH_PHY1_CRATE_2_3 0x0100 /* 2/3 */
-#define B43_TXH_PHY1_CRATE_3_4 0x0200 /* 3/4 */
-#define B43_TXH_PHY1_CRATE_4_5 0x0300 /* 4/5 */
-#define B43_TXH_PHY1_CRATE_5_6 0x0400 /* 5/6 */
-#define B43_TXH_PHY1_CRATE_7_8 0x0600 /* 7/8 */
-#define B43_TXH_PHY1_MODUL 0x3800 /* Modulation scheme */
-#define B43_TXH_PHY1_MODUL_BPSK 0x0000 /* BPSK */
-#define B43_TXH_PHY1_MODUL_QPSK 0x0800 /* QPSK */
-#define B43_TXH_PHY1_MODUL_QAM16 0x1000 /* QAM16 */
-#define B43_TXH_PHY1_MODUL_QAM64 0x1800 /* QAM64 */
-#define B43_TXH_PHY1_MODUL_QAM256 0x2000 /* QAM256 */
-
-
-/* r351 firmware compatibility stuff. */
-static inline
-bool b43_is_old_txhdr_format(struct b43_wldev *dev)
-{
- return (dev->fw.rev <= 351);
-}
-
-static inline
-size_t b43_txhdr_size(struct b43_wldev *dev)
-{
- if (b43_is_old_txhdr_format(dev))
- return 100 + sizeof(struct b43_plcp_hdr6);
- return 104 + sizeof(struct b43_plcp_hdr6);
-}
-
-
-int b43_generate_txhdr(struct b43_wldev *dev,
- u8 * txhdr,
- const unsigned char *fragment_data,
- unsigned int fragment_len,
- const struct ieee80211_tx_info *txctl, u16 cookie);
-
-/* Transmit Status */
-struct b43_txstatus {
- u16 cookie; /* The cookie from the txhdr */
- u16 seq; /* Sequence number */
- u8 phy_stat; /* PHY TX status */
- u8 frame_count; /* Frame transmit count */
- u8 rts_count; /* RTS transmit count */
- u8 supp_reason; /* Suppression reason */
- /* flags */
- u8 pm_indicated; /* PM mode indicated to AP */
- u8 intermediate; /* Intermediate status notification (not final) */
- u8 for_ampdu; /* Status is for an AMPDU (afterburner) */
- u8 acked; /* Wireless ACK received */
-};
-
-/* txstatus supp_reason values */
-enum {
- B43_TXST_SUPP_NONE, /* Not suppressed */
- B43_TXST_SUPP_PMQ, /* Suppressed due to PMQ entry */
- B43_TXST_SUPP_FLUSH, /* Suppressed due to flush request */
- B43_TXST_SUPP_PREV, /* Previous fragment failed */
- B43_TXST_SUPP_CHAN, /* Channel mismatch */
- B43_TXST_SUPP_LIFE, /* Lifetime expired */
- B43_TXST_SUPP_UNDER, /* Buffer underflow */
- B43_TXST_SUPP_ABNACK, /* Afterburner NACK */
-};
-
-/* Receive header for v4 firmware. */
-struct b43_rxhdr_fw4 {
- __le16 frame_len; /* Frame length */
- PAD_BYTES(2);
- __le16 phy_status0; /* PHY RX Status 0 */
- union {
- /* RSSI for A/B/G-PHYs */
- struct {
- __u8 jssi; /* PHY RX Status 1: JSSI */
- __u8 sig_qual; /* PHY RX Status 1: Signal Quality */
- } __attribute__ ((__packed__));
-
- /* RSSI for N-PHYs */
- struct {
- __s8 power0; /* PHY RX Status 1: Power 0 */
- __s8 power1; /* PHY RX Status 1: Power 1 */
- } __attribute__ ((__packed__));
- } __attribute__ ((__packed__));
- __le16 phy_status2; /* PHY RX Status 2 */
- __le16 phy_status3; /* PHY RX Status 3 */
- __le32 mac_status; /* MAC RX status */
- __le16 mac_time;
- __le16 channel;
-} __attribute__ ((__packed__));
-
-/* PHY RX Status 0 */
-#define B43_RX_PHYST0_GAINCTL 0x4000 /* Gain Control */
-#define B43_RX_PHYST0_PLCPHCF 0x0200
-#define B43_RX_PHYST0_PLCPFV 0x0100
-#define B43_RX_PHYST0_SHORTPRMBL 0x0080 /* Received with Short Preamble */
-#define B43_RX_PHYST0_LCRS 0x0040
-#define B43_RX_PHYST0_ANT 0x0020 /* Antenna */
-#define B43_RX_PHYST0_UNSRATE 0x0010
-#define B43_RX_PHYST0_CLIP 0x000C
-#define B43_RX_PHYST0_CLIP_SHIFT 2
-#define B43_RX_PHYST0_FTYPE 0x0003 /* Frame type */
-#define B43_RX_PHYST0_CCK 0x0000 /* Frame type: CCK */
-#define B43_RX_PHYST0_OFDM 0x0001 /* Frame type: OFDM */
-#define B43_RX_PHYST0_PRE_N 0x0002 /* Pre-standard N-PHY frame */
-#define B43_RX_PHYST0_STD_N 0x0003 /* Standard N-PHY frame */
-
-/* PHY RX Status 2 */
-#define B43_RX_PHYST2_LNAG 0xC000 /* LNA Gain */
-#define B43_RX_PHYST2_LNAG_SHIFT 14
-#define B43_RX_PHYST2_PNAG 0x3C00 /* PNA Gain */
-#define B43_RX_PHYST2_PNAG_SHIFT 10
-#define B43_RX_PHYST2_FOFF 0x03FF /* F offset */
-
-/* PHY RX Status 3 */
-#define B43_RX_PHYST3_DIGG 0x1800 /* DIG Gain */
-#define B43_RX_PHYST3_DIGG_SHIFT 11
-#define B43_RX_PHYST3_TRSTATE 0x0400 /* TR state */
-
-/* MAC RX Status */
-#define B43_RX_MAC_RXST_VALID 0x01000000 /* PHY RXST valid */
-#define B43_RX_MAC_TKIP_MICERR 0x00100000 /* TKIP MIC error */
-#define B43_RX_MAC_TKIP_MICATT 0x00080000 /* TKIP MIC attempted */
-#define B43_RX_MAC_AGGTYPE 0x00060000 /* Aggregation type */
-#define B43_RX_MAC_AGGTYPE_SHIFT 17
-#define B43_RX_MAC_AMSDU 0x00010000 /* A-MSDU mask */
-#define B43_RX_MAC_BEACONSENT 0x00008000 /* Beacon sent flag */
-#define B43_RX_MAC_KEYIDX 0x000007E0 /* Key index */
-#define B43_RX_MAC_KEYIDX_SHIFT 5
-#define B43_RX_MAC_DECERR 0x00000010 /* Decrypt error */
-#define B43_RX_MAC_DEC 0x00000008 /* Decryption attempted */
-#define B43_RX_MAC_PADDING 0x00000004 /* Pad bytes present */
-#define B43_RX_MAC_RESP 0x00000002 /* Response frame transmitted */
-#define B43_RX_MAC_FCSERR 0x00000001 /* FCS error */
-
-/* RX channel */
-#define B43_RX_CHAN_40MHZ 0x1000 /* 40 Mhz channel width */
-#define B43_RX_CHAN_5GHZ 0x0800 /* 5 Ghz band */
-#define B43_RX_CHAN_ID 0x07F8 /* Channel ID */
-#define B43_RX_CHAN_ID_SHIFT 3
-#define B43_RX_CHAN_PHYTYPE 0x0007 /* PHY type */
-
-
-u8 b43_plcp_get_ratecode_cck(const u8 bitrate);
-u8 b43_plcp_get_ratecode_ofdm(const u8 bitrate);
-
-void b43_generate_plcp_hdr(struct b43_plcp_hdr4 *plcp,
- const u16 octets, const u8 bitrate);
-
-void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr);
-
-void b43_handle_txstatus(struct b43_wldev *dev,
- const struct b43_txstatus *status);
-bool b43_fill_txstatus_report(struct ieee80211_tx_info *report,
- const struct b43_txstatus *status);
-
-void b43_tx_suspend(struct b43_wldev *dev);
-void b43_tx_resume(struct b43_wldev *dev);
-
-
-/* Helper functions for converting the key-table index from "firmware-format"
- * to "raw-format" and back. The firmware API changed for this at some revision.
- * We need to account for that here. */
-static inline int b43_new_kidx_api(struct b43_wldev *dev)
-{
- /* FIXME: Not sure the change was at rev 351 */
- return (dev->fw.rev >= 351);
-}
-static inline u8 b43_kidx_to_fw(struct b43_wldev *dev, u8 raw_kidx)
-{
- u8 firmware_kidx;
- if (b43_new_kidx_api(dev)) {
- firmware_kidx = raw_kidx;
- } else {
- if (raw_kidx >= 4) /* Is per STA key? */
- firmware_kidx = raw_kidx - 4;
- else
- firmware_kidx = raw_kidx; /* TX default key */
- }
- return firmware_kidx;
-}
-static inline u8 b43_kidx_to_raw(struct b43_wldev *dev, u8 firmware_kidx)
-{
- u8 raw_kidx;
- if (b43_new_kidx_api(dev))
- raw_kidx = firmware_kidx;
- else
- raw_kidx = firmware_kidx + 4; /* RX default keys or per STA keys */
- return raw_kidx;
-}
-
-#endif /* B43_XMIT_H_ */
projects / openwrt / staging / mkresin.git / commitdiff