/dts-v1/;
-#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/clock/mt7621-clk.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/mips-gic.h>
+#include <dt-bindings/reset/mt7621-reset.h>
/ {
#address-cells = <1>;
bootargs = "console=ttyS0,57600";
};
- pll: pll {
- compatible = "mediatek,mt7621-pll", "syscon";
-
- #clock-cells = <1>;
- clock-output-names = "cpu", "bus";
- };
-
- sysclock: sysclock {
- #clock-cells = <0>;
- compatible = "fixed-clock";
-
- /* FIXME: there should be way to detect this */
- clock-frequency = <50000000>;
- };
-
palmbus: palmbus@1e000000 {
compatible = "palmbus";
reg = <0x1e000000 0x100000>;
#size-cells = <1>;
sysc: syscon@0 {
- compatible = "mtk,mt7621-sysc", "syscon";
+ compatible = "mediatek,mt7621-sysc", "syscon";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ ralink,memctl = <&memc>;
+ clock-output-names = "xtal", "cpu", "bus",
+ "50m", "125m", "150m",
+ "250m", "270m";
reg = <0x0 0x100>;
};
- wdt: wdt@100 {
+ wdt: watchdog@100 {
compatible = "mediatek,mt7621-wdt";
reg = <0x100 0x100>;
+ mediatek,sysctl = <&sysc>;
};
gpio: gpio@600 {
#interrupt-cells = <2>;
compatible = "mediatek,mt7621-gpio";
gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 95>;
interrupt-controller;
reg = <0x600 0x100>;
interrupt-parent = <&gic>;
compatible = "mediatek,mt7621-i2c";
reg = <0x900 0x100>;
- clocks = <&sysclock>;
+ clocks = <&sysc MT7621_CLK_I2C>;
+ clock-names = "i2c";
- resets = <&rstctrl 16>;
+ resets = <&sysc MT7621_RST_I2C>;
reset-names = "i2c";
#address-cells = <1>;
compatible = "mediatek,mt7621-i2s";
reg = <0xa00 0x100>;
- clocks = <&sysclock>;
+ clocks = <&sysc MT7621_CLK_I2S>;
- resets = <&rstctrl 17>;
+ resets = <&sysc MT7621_RST_I2S>;
reset-names = "i2s";
interrupt-parent = <&gic>;
status = "disabled";
};
- systick: systick@500 {
- compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
- reg = <0x500 0x10>;
-
- resets = <&rstctrl 28>;
- reset-names = "intc";
-
- interrupt-parent = <&gic>;
- interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- memc: syscon@5000 {
- compatible = "mtk,mt7621-memc", "syscon";
+ memc: memory-controller@5000 {
+ compatible = "mediatek,mt7621-memc", "syscon";
reg = <0x5000 0x1000>;
};
compatible = "ns16550a";
reg = <0xc00 0x100>;
- clock-frequency = <50000000>;
+ clocks = <&sysc MT7621_CLK_UART1>;
+
+ resets = <&sysc MT7621_RST_UART1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
compatible = "ns16550a";
reg = <0xd00 0x100>;
- clock-frequency = <50000000>;
+ clocks = <&sysc MT7621_CLK_UART2>;
+
+ resets = <&sysc MT7621_RST_UART2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
compatible = "ns16550a";
reg = <0xe00 0x100>;
- clock-frequency = <50000000>;
+ clocks = <&sysc MT7621_CLK_UART3>;
+
+ resets = <&sysc MT7621_RST_UART3>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x100>;
- clocks = <&pll MT7621_CLK_BUS>;
+ clocks = <&sysc MT7621_CLK_SPI>;
+ clock-names = "spi";
- resets = <&rstctrl 18>;
+ resets = <&sysc MT7621_RST_SPI>;
reset-names = "spi";
#address-cells = <1>;
compatible = "ralink,rt3883-gdma";
reg = <0x2800 0x800>;
- resets = <&rstctrl 14>;
+ resets = <&sysc MT7621_RST_GDMA>;
reset-names = "dma";
interrupt-parent = <&gic>;
compatible = "mediatek,mt7621-hsdma";
reg = <0x7000 0x1000>;
- resets = <&rstctrl 5>;
+ resets = <&sysc MT7621_RST_HSDMA>;
reset-names = "hsdma";
interrupt-parent = <&gic>;
};
};
- rstctrl: rstctrl {
- compatible = "ralink,rt2880-reset";
- #reset-cells = <1>;
- };
-
- clkctrl: clkctrl {
- compatible = "ralink,rt2880-clock";
- #clock-cells = <1>;
- };
-
sdhci: sdhci@1e130000 {
status = "disabled";
0x1e1d0700 0x0100>;
reg-names = "mac", "ippc";
- clocks = <&sysclock>;
+ clocks = <&sysc MT7621_CLK_XTAL>;
clock-names = "sys_ck";
interrupt-parent = <&gic>;
timer {
compatible = "mti,gic-timer";
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
- clocks = <&pll MT7621_CLK_CPU>;
+ clocks = <&sysc MT7621_CLK_CPU>;
};
};
- nficlock: nficlock {
- #clock-cells = <0>;
- compatible = "fixed-clock";
-
- clock-frequency = <125000000>;
- };
-
cpc: cpc@1fbf0000 {
compatible = "mti,mips-cpc";
reg = <0x1fbf0000 0x8000>;
0x1e003800 0x800>;
reg-names = "nfi", "ecc";
- clocks = <&nficlock>;
+ clocks = <&sysc MT7621_CLK_NAND>;
clock-names = "nfi_clk";
};
+ crypto: crypto@1e004000 {
+ compatible = "mediatek,mtk-eip93";
+ reg = <0x1e004000 0x1000>;
+
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 19 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
ethernet: ethernet@1e100000 {
compatible = "mediatek,mt7621-eth";
reg = <0x1e100000 0x10000>;
- clocks = <&sysclock>;
- clock-names = "ethif";
+ clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>;
+ clock-names = "fe", "ethif";
#address-cells = <1>;
#size-cells = <0>;
- resets = <&rstctrl 6 &rstctrl 23>;
+ resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>;
reset-names = "fe", "eth";
interrupt-parent = <&gic>;
compatible = "mediatek,eth-mac";
reg = <1>;
status = "disabled";
- phy-mode = "rgmii-rxid";
+ phy-mode = "rgmii";
};
mdio: mdio-bus {
compatible = "mediatek,mt7621";
reg = <0x1f>;
mediatek,mcm;
- resets = <&rstctrl 2>;
+ resets = <&sysc MT7621_RST_MCM>;
reset-names = "mcm";
interrupt-controller;
#interrupt-cells = <1>;
port@6 {
reg = <6>;
- label = "cpu";
ethernet = <&gmac0>;
phy-mode = "rgmii";
device_type = "pci";
- ranges = <0x02000000 0 0x00000000 0x60000000 0 0x10000000>, /* pci memory */
+ ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
<0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
- interrupt-parent = <&gic>;
- interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
- GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
- GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
-
status = "disabled";
- resets = <&rstctrl 24>, <&rstctrl 25>, <&rstctrl 26>;
- reset-names = "pcie0", "pcie1", "pcie2";
- clocks = <&clkctrl 24>, <&clkctrl 25>, <&clkctrl 26>;
- clock-names = "pcie0", "pcie1", "pcie2";
- phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
- phy-names = "pcie-phy0", "pcie-phy2";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xF800 0 0 0>;
+ interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
#size-cells = <2>;
device_type = "pci";
ranges;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&sysc MT7621_RST_PCIE0>;
+ clocks = <&sysc MT7621_CLK_PCIE0>;
+ phys = <&pcie0_phy 1>;
+ phy-names = "pcie-phy0";
};
pcie1: pcie@1,0 {
#size-cells = <2>;
device_type = "pci";
ranges;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&sysc MT7621_RST_PCIE1>;
+ clocks = <&sysc MT7621_CLK_PCIE1>;
+ phys = <&pcie0_phy 1>;
+ phy-names = "pcie-phy1";
};
pcie2: pcie@2,0 {
#size-cells = <2>;
device_type = "pci";
ranges;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&sysc MT7621_RST_PCIE2>;
+ clocks = <&sysc MT7621_CLK_PCIE2>;
+ phys = <&pcie2_phy 0>;
+ phy-names = "pcie-phy2";
};
};
pcie0_phy: pcie-phy@1e149000 {
compatible = "mediatek,mt7621-pci-phy";
reg = <0x1e149000 0x0700>;
+ clocks = <&sysc MT7621_CLK_XTAL>;
#phy-cells = <1>;
};
pcie2_phy: pcie-phy@1e14a000 {
compatible = "mediatek,mt7621-pci-phy";
reg = <0x1e14a000 0x0700>;
+ clocks = <&sysc MT7621_CLK_XTAL>;
#phy-cells = <1>;
};
};
projects / openwrt / staging / wigyori.git / blobdiff