ar71xx: add initial support for the QCA955X SoCs
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / arch / mips / ath79 / dev-eth.c
1 /*
2 * Atheros AR71xx SoC platform devices
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22
23 #include <asm/mach-ath79/ath79.h>
24 #include <asm/mach-ath79/ar71xx_regs.h>
25 #include <asm/mach-ath79/irq.h>
26
27 #include "common.h"
28 #include "dev-eth.h"
29
30 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
31
32 static struct resource ath79_mdio0_resources[] = {
33 {
34 .name = "mdio_base",
35 .flags = IORESOURCE_MEM,
36 .start = AR71XX_GE0_BASE,
37 .end = AR71XX_GE0_BASE + 0x200 - 1,
38 }
39 };
40
41 static struct ag71xx_mdio_platform_data ath79_mdio0_data;
42
43 struct platform_device ath79_mdio0_device = {
44 .name = "ag71xx-mdio",
45 .id = 0,
46 .resource = ath79_mdio0_resources,
47 .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
48 .dev = {
49 .platform_data = &ath79_mdio0_data,
50 },
51 };
52
53 static struct resource ath79_mdio1_resources[] = {
54 {
55 .name = "mdio_base",
56 .flags = IORESOURCE_MEM,
57 .start = AR71XX_GE1_BASE,
58 .end = AR71XX_GE1_BASE + 0x200 - 1,
59 }
60 };
61
62 static struct ag71xx_mdio_platform_data ath79_mdio1_data;
63
64 struct platform_device ath79_mdio1_device = {
65 .name = "ag71xx-mdio",
66 .id = 1,
67 .resource = ath79_mdio1_resources,
68 .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
69 .dev = {
70 .platform_data = &ath79_mdio1_data,
71 },
72 };
73
74 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
75 {
76 void __iomem *base;
77 u32 t;
78
79 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
80
81 t = __raw_readl(base + cfg_reg);
82 t &= ~(3 << shift);
83 t |= (2 << shift);
84 __raw_writel(t, base + cfg_reg);
85 udelay(100);
86
87 __raw_writel(pll_val, base + pll_reg);
88
89 t |= (3 << shift);
90 __raw_writel(t, base + cfg_reg);
91 udelay(100);
92
93 t &= ~(3 << shift);
94 __raw_writel(t, base + cfg_reg);
95 udelay(100);
96
97 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
98 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
99
100 iounmap(base);
101 }
102
103 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
104 unsigned int mii_if)
105 {
106 void __iomem *base;
107 u32 t;
108
109 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
110
111 t = __raw_readl(base + reg);
112 t &= ~(AR71XX_MII_CTRL_IF_MASK);
113 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
114 __raw_writel(t, base + reg);
115
116 iounmap(base);
117 }
118
119 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
120 {
121 void __iomem *base;
122 unsigned int mii_speed;
123 u32 t;
124
125 switch (speed) {
126 case SPEED_10:
127 mii_speed = AR71XX_MII_CTRL_SPEED_10;
128 break;
129 case SPEED_100:
130 mii_speed = AR71XX_MII_CTRL_SPEED_100;
131 break;
132 case SPEED_1000:
133 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
134 break;
135 default:
136 BUG();
137 }
138
139 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
140
141 t = __raw_readl(base + reg);
142 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
143 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
144 __raw_writel(t, base + reg);
145
146 iounmap(base);
147 }
148
149 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
150 {
151 struct platform_device *mdio_dev;
152 struct ag71xx_mdio_platform_data *mdio_data;
153 unsigned int max_id;
154
155 if (ath79_soc == ATH79_SOC_AR9341 ||
156 ath79_soc == ATH79_SOC_AR9342 ||
157 ath79_soc == ATH79_SOC_AR9344 ||
158 ath79_soc == ATH79_SOC_QCA9558)
159 max_id = 1;
160 else
161 max_id = 0;
162
163 if (id > max_id) {
164 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
165 return;
166 }
167
168 switch (ath79_soc) {
169 case ATH79_SOC_AR7241:
170 case ATH79_SOC_AR9330:
171 case ATH79_SOC_AR9331:
172 mdio_dev = &ath79_mdio1_device;
173 mdio_data = &ath79_mdio1_data;
174 break;
175
176 case ATH79_SOC_AR9341:
177 case ATH79_SOC_AR9342:
178 case ATH79_SOC_AR9344:
179 case ATH79_SOC_QCA9558:
180 if (id == 0) {
181 mdio_dev = &ath79_mdio0_device;
182 mdio_data = &ath79_mdio0_data;
183 } else {
184 mdio_dev = &ath79_mdio1_device;
185 mdio_data = &ath79_mdio1_data;
186 }
187 break;
188
189 case ATH79_SOC_AR7242:
190 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
191 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
192 AR71XX_ETH0_PLL_SHIFT);
193 /* fall through */
194 default:
195 mdio_dev = &ath79_mdio0_device;
196 mdio_data = &ath79_mdio0_data;
197 break;
198 }
199
200 mdio_data->phy_mask = phy_mask;
201
202 switch (ath79_soc) {
203 case ATH79_SOC_AR7240:
204 mdio_data->is_ar7240 = 1;
205 /* fall through */
206 case ATH79_SOC_AR7241:
207 mdio_data->builtin_switch = 1;
208 break;
209
210 case ATH79_SOC_AR9330:
211 mdio_data->is_ar9330 = 1;
212 /* fall through */
213 case ATH79_SOC_AR9331:
214 mdio_data->builtin_switch = 1;
215 break;
216
217 case ATH79_SOC_AR9341:
218 case ATH79_SOC_AR9342:
219 case ATH79_SOC_AR9344:
220 case ATH79_SOC_QCA9558:
221 if (id == 1)
222 mdio_data->builtin_switch = 1;
223 mdio_data->is_ar934x = 1;
224 break;
225
226 default:
227 break;
228 }
229
230 platform_device_register(mdio_dev);
231 }
232
233 struct ath79_eth_pll_data ath79_eth0_pll_data;
234 struct ath79_eth_pll_data ath79_eth1_pll_data;
235
236 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
237 {
238 struct ath79_eth_pll_data *pll_data;
239 u32 pll_val;
240
241 switch (mac) {
242 case 0:
243 pll_data = &ath79_eth0_pll_data;
244 break;
245 case 1:
246 pll_data = &ath79_eth1_pll_data;
247 break;
248 default:
249 BUG();
250 }
251
252 switch (speed) {
253 case SPEED_10:
254 pll_val = pll_data->pll_10;
255 break;
256 case SPEED_100:
257 pll_val = pll_data->pll_100;
258 break;
259 case SPEED_1000:
260 pll_val = pll_data->pll_1000;
261 break;
262 default:
263 BUG();
264 }
265
266 return pll_val;
267 }
268
269 static void ath79_set_speed_ge0(int speed)
270 {
271 u32 val = ath79_get_eth_pll(0, speed);
272
273 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
274 val, AR71XX_ETH0_PLL_SHIFT);
275 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
276 }
277
278 static void ath79_set_speed_ge1(int speed)
279 {
280 u32 val = ath79_get_eth_pll(1, speed);
281
282 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
283 val, AR71XX_ETH1_PLL_SHIFT);
284 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
285 }
286
287 static void ar7242_set_speed_ge0(int speed)
288 {
289 u32 val = ath79_get_eth_pll(0, speed);
290 void __iomem *base;
291
292 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
293 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
294 iounmap(base);
295 }
296
297 static void ar91xx_set_speed_ge0(int speed)
298 {
299 u32 val = ath79_get_eth_pll(0, speed);
300
301 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
302 val, AR913X_ETH0_PLL_SHIFT);
303 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
304 }
305
306 static void ar91xx_set_speed_ge1(int speed)
307 {
308 u32 val = ath79_get_eth_pll(1, speed);
309
310 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
311 val, AR913X_ETH1_PLL_SHIFT);
312 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
313 }
314
315 static void ar934x_set_speed_ge0(int speed)
316 {
317 void __iomem *base;
318 u32 val = ath79_get_eth_pll(0, speed);
319
320 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
321 __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
322 iounmap(base);
323 }
324
325 static void ath79_set_speed_dummy(int speed)
326 {
327 }
328
329 static void ath79_ddr_no_flush(void)
330 {
331 }
332
333 static void ath79_ddr_flush_ge0(void)
334 {
335 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
336 }
337
338 static void ath79_ddr_flush_ge1(void)
339 {
340 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
341 }
342
343 static void ar724x_ddr_flush_ge0(void)
344 {
345 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
346 }
347
348 static void ar724x_ddr_flush_ge1(void)
349 {
350 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
351 }
352
353 static void ar91xx_ddr_flush_ge0(void)
354 {
355 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
356 }
357
358 static void ar91xx_ddr_flush_ge1(void)
359 {
360 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
361 }
362
363 static void ar933x_ddr_flush_ge0(void)
364 {
365 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
366 }
367
368 static void ar933x_ddr_flush_ge1(void)
369 {
370 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
371 }
372
373 static struct resource ath79_eth0_resources[] = {
374 {
375 .name = "mac_base",
376 .flags = IORESOURCE_MEM,
377 .start = AR71XX_GE0_BASE,
378 .end = AR71XX_GE0_BASE + 0x200 - 1,
379 }, {
380 .name = "mac_irq",
381 .flags = IORESOURCE_IRQ,
382 .start = ATH79_CPU_IRQ_GE0,
383 .end = ATH79_CPU_IRQ_GE0,
384 },
385 };
386
387 struct ag71xx_platform_data ath79_eth0_data = {
388 .reset_bit = AR71XX_RESET_GE0_MAC,
389 };
390
391 struct platform_device ath79_eth0_device = {
392 .name = "ag71xx",
393 .id = 0,
394 .resource = ath79_eth0_resources,
395 .num_resources = ARRAY_SIZE(ath79_eth0_resources),
396 .dev = {
397 .platform_data = &ath79_eth0_data,
398 },
399 };
400
401 static struct resource ath79_eth1_resources[] = {
402 {
403 .name = "mac_base",
404 .flags = IORESOURCE_MEM,
405 .start = AR71XX_GE1_BASE,
406 .end = AR71XX_GE1_BASE + 0x200 - 1,
407 }, {
408 .name = "mac_irq",
409 .flags = IORESOURCE_IRQ,
410 .start = ATH79_CPU_IRQ_GE1,
411 .end = ATH79_CPU_IRQ_GE1,
412 },
413 };
414
415 struct ag71xx_platform_data ath79_eth1_data = {
416 .reset_bit = AR71XX_RESET_GE1_MAC,
417 };
418
419 struct platform_device ath79_eth1_device = {
420 .name = "ag71xx",
421 .id = 1,
422 .resource = ath79_eth1_resources,
423 .num_resources = ARRAY_SIZE(ath79_eth1_resources),
424 .dev = {
425 .platform_data = &ath79_eth1_data,
426 },
427 };
428
429 struct ag71xx_switch_platform_data ath79_switch_data;
430
431 #define AR71XX_PLL_VAL_1000 0x00110000
432 #define AR71XX_PLL_VAL_100 0x00001099
433 #define AR71XX_PLL_VAL_10 0x00991099
434
435 #define AR724X_PLL_VAL_1000 0x00110000
436 #define AR724X_PLL_VAL_100 0x00001099
437 #define AR724X_PLL_VAL_10 0x00991099
438
439 #define AR7242_PLL_VAL_1000 0x16000000
440 #define AR7242_PLL_VAL_100 0x00000101
441 #define AR7242_PLL_VAL_10 0x00001616
442
443 #define AR913X_PLL_VAL_1000 0x1a000000
444 #define AR913X_PLL_VAL_100 0x13000a44
445 #define AR913X_PLL_VAL_10 0x00441099
446
447 #define AR933X_PLL_VAL_1000 0x00110000
448 #define AR933X_PLL_VAL_100 0x00001099
449 #define AR933X_PLL_VAL_10 0x00991099
450
451 #define AR934X_PLL_VAL_1000 0x16000000
452 #define AR934X_PLL_VAL_100 0x00000101
453 #define AR934X_PLL_VAL_10 0x00001616
454
455 static void __init ath79_init_eth_pll_data(unsigned int id)
456 {
457 struct ath79_eth_pll_data *pll_data;
458 u32 pll_10, pll_100, pll_1000;
459
460 switch (id) {
461 case 0:
462 pll_data = &ath79_eth0_pll_data;
463 break;
464 case 1:
465 pll_data = &ath79_eth1_pll_data;
466 break;
467 default:
468 BUG();
469 }
470
471 switch (ath79_soc) {
472 case ATH79_SOC_AR7130:
473 case ATH79_SOC_AR7141:
474 case ATH79_SOC_AR7161:
475 pll_10 = AR71XX_PLL_VAL_10;
476 pll_100 = AR71XX_PLL_VAL_100;
477 pll_1000 = AR71XX_PLL_VAL_1000;
478 break;
479
480 case ATH79_SOC_AR7240:
481 case ATH79_SOC_AR7241:
482 pll_10 = AR724X_PLL_VAL_10;
483 pll_100 = AR724X_PLL_VAL_100;
484 pll_1000 = AR724X_PLL_VAL_1000;
485 break;
486
487 case ATH79_SOC_AR7242:
488 pll_10 = AR7242_PLL_VAL_10;
489 pll_100 = AR7242_PLL_VAL_100;
490 pll_1000 = AR7242_PLL_VAL_1000;
491 break;
492
493 case ATH79_SOC_AR9130:
494 case ATH79_SOC_AR9132:
495 pll_10 = AR913X_PLL_VAL_10;
496 pll_100 = AR913X_PLL_VAL_100;
497 pll_1000 = AR913X_PLL_VAL_1000;
498 break;
499
500 case ATH79_SOC_AR9330:
501 case ATH79_SOC_AR9331:
502 pll_10 = AR933X_PLL_VAL_10;
503 pll_100 = AR933X_PLL_VAL_100;
504 pll_1000 = AR933X_PLL_VAL_1000;
505 break;
506
507 case ATH79_SOC_AR9341:
508 case ATH79_SOC_AR9342:
509 case ATH79_SOC_AR9344:
510 case ATH79_SOC_QCA9558:
511 pll_10 = AR934X_PLL_VAL_10;
512 pll_100 = AR934X_PLL_VAL_100;
513 pll_1000 = AR934X_PLL_VAL_1000;
514 break;
515
516 default:
517 BUG();
518 }
519
520 if (!pll_data->pll_10)
521 pll_data->pll_10 = pll_10;
522
523 if (!pll_data->pll_100)
524 pll_data->pll_100 = pll_100;
525
526 if (!pll_data->pll_1000)
527 pll_data->pll_1000 = pll_1000;
528 }
529
530 static int __init ath79_setup_phy_if_mode(unsigned int id,
531 struct ag71xx_platform_data *pdata)
532 {
533 unsigned int mii_if;
534
535 switch (id) {
536 case 0:
537 switch (ath79_soc) {
538 case ATH79_SOC_AR7130:
539 case ATH79_SOC_AR7141:
540 case ATH79_SOC_AR7161:
541 case ATH79_SOC_AR9130:
542 case ATH79_SOC_AR9132:
543 switch (pdata->phy_if_mode) {
544 case PHY_INTERFACE_MODE_MII:
545 mii_if = AR71XX_MII0_CTRL_IF_MII;
546 break;
547 case PHY_INTERFACE_MODE_GMII:
548 mii_if = AR71XX_MII0_CTRL_IF_GMII;
549 break;
550 case PHY_INTERFACE_MODE_RGMII:
551 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
552 break;
553 case PHY_INTERFACE_MODE_RMII:
554 mii_if = AR71XX_MII0_CTRL_IF_RMII;
555 break;
556 default:
557 return -EINVAL;
558 }
559 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
560 break;
561
562 case ATH79_SOC_AR7240:
563 case ATH79_SOC_AR7241:
564 case ATH79_SOC_AR9330:
565 case ATH79_SOC_AR9331:
566 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
567 break;
568
569 case ATH79_SOC_AR7242:
570 /* FIXME */
571
572 case ATH79_SOC_AR9341:
573 case ATH79_SOC_AR9342:
574 case ATH79_SOC_AR9344:
575 case ATH79_SOC_QCA9558:
576 switch (pdata->phy_if_mode) {
577 case PHY_INTERFACE_MODE_MII:
578 case PHY_INTERFACE_MODE_GMII:
579 case PHY_INTERFACE_MODE_RGMII:
580 case PHY_INTERFACE_MODE_RMII:
581 break;
582 default:
583 return -EINVAL;
584 }
585 break;
586
587 default:
588 BUG();
589 }
590 break;
591 case 1:
592 switch (ath79_soc) {
593 case ATH79_SOC_AR7130:
594 case ATH79_SOC_AR7141:
595 case ATH79_SOC_AR7161:
596 case ATH79_SOC_AR9130:
597 case ATH79_SOC_AR9132:
598 switch (pdata->phy_if_mode) {
599 case PHY_INTERFACE_MODE_RMII:
600 mii_if = AR71XX_MII1_CTRL_IF_RMII;
601 break;
602 case PHY_INTERFACE_MODE_RGMII:
603 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
604 break;
605 default:
606 return -EINVAL;
607 }
608 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
609 break;
610
611 case ATH79_SOC_AR7240:
612 case ATH79_SOC_AR7241:
613 case ATH79_SOC_AR9330:
614 case ATH79_SOC_AR9331:
615 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
616 break;
617
618 case ATH79_SOC_AR7242:
619 /* FIXME */
620
621 case ATH79_SOC_AR9341:
622 case ATH79_SOC_AR9342:
623 case ATH79_SOC_AR9344:
624 case ATH79_SOC_QCA9558:
625 switch (pdata->phy_if_mode) {
626 case PHY_INTERFACE_MODE_MII:
627 case PHY_INTERFACE_MODE_GMII:
628 break;
629 default:
630 return -EINVAL;
631 }
632 break;
633
634 default:
635 BUG();
636 }
637 break;
638 }
639
640 return 0;
641 }
642
643 void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
644 {
645 void __iomem *base;
646 u32 t;
647
648 base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE);
649
650 t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
651 t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
652 if (mac)
653 t |= AR933X_ETH_CFG_SW_PHY_SWAP;
654 if (mdio)
655 t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
656 __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG);
657
658 iounmap(base);
659 }
660
661 static int ath79_eth_instance __initdata;
662 void __init ath79_register_eth(unsigned int id)
663 {
664 struct platform_device *pdev;
665 struct ag71xx_platform_data *pdata;
666 int err;
667
668 if (id > 1) {
669 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
670 return;
671 }
672
673 ath79_init_eth_pll_data(id);
674
675 if (id == 0)
676 pdev = &ath79_eth0_device;
677 else
678 pdev = &ath79_eth1_device;
679
680 pdata = pdev->dev.platform_data;
681
682 err = ath79_setup_phy_if_mode(id, pdata);
683 if (err) {
684 printk(KERN_ERR
685 "ar71xx: invalid PHY interface mode for GE%u\n", id);
686 return;
687 }
688
689 switch (ath79_soc) {
690 case ATH79_SOC_AR7130:
691 if (id == 0) {
692 pdata->ddr_flush = ath79_ddr_flush_ge0;
693 pdata->set_speed = ath79_set_speed_ge0;
694 } else {
695 pdata->ddr_flush = ath79_ddr_flush_ge1;
696 pdata->set_speed = ath79_set_speed_ge1;
697 }
698 break;
699
700 case ATH79_SOC_AR7141:
701 case ATH79_SOC_AR7161:
702 if (id == 0) {
703 pdata->ddr_flush = ath79_ddr_flush_ge0;
704 pdata->set_speed = ath79_set_speed_ge0;
705 } else {
706 pdata->ddr_flush = ath79_ddr_flush_ge1;
707 pdata->set_speed = ath79_set_speed_ge1;
708 }
709 pdata->has_gbit = 1;
710 break;
711
712 case ATH79_SOC_AR7242:
713 if (id == 0) {
714 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
715 AR71XX_RESET_GE0_PHY;
716 pdata->ddr_flush = ar724x_ddr_flush_ge0;
717 pdata->set_speed = ar7242_set_speed_ge0;
718 } else {
719 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
720 AR71XX_RESET_GE1_PHY;
721 pdata->ddr_flush = ar724x_ddr_flush_ge1;
722 pdata->set_speed = ath79_set_speed_dummy;
723 }
724 pdata->has_gbit = 1;
725 pdata->is_ar724x = 1;
726
727 if (!pdata->fifo_cfg1)
728 pdata->fifo_cfg1 = 0x0010ffff;
729 if (!pdata->fifo_cfg2)
730 pdata->fifo_cfg2 = 0x015500aa;
731 if (!pdata->fifo_cfg3)
732 pdata->fifo_cfg3 = 0x01f00140;
733 break;
734
735 case ATH79_SOC_AR7241:
736 if (id == 0)
737 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
738 else
739 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
740 /* fall through */
741 case ATH79_SOC_AR7240:
742 if (id == 0) {
743 pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
744 pdata->ddr_flush = ar724x_ddr_flush_ge0;
745 pdata->set_speed = ath79_set_speed_dummy;
746
747 pdata->phy_mask = BIT(4);
748 } else {
749 pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
750 pdata->ddr_flush = ar724x_ddr_flush_ge1;
751 pdata->set_speed = ath79_set_speed_dummy;
752
753 pdata->speed = SPEED_1000;
754 pdata->duplex = DUPLEX_FULL;
755 pdata->switch_data = &ath79_switch_data;
756
757 ath79_switch_data.phy_poll_mask |= BIT(4);
758 }
759 pdata->has_gbit = 1;
760 pdata->is_ar724x = 1;
761 if (ath79_soc == ATH79_SOC_AR7240)
762 pdata->is_ar7240 = 1;
763
764 if (!pdata->fifo_cfg1)
765 pdata->fifo_cfg1 = 0x0010ffff;
766 if (!pdata->fifo_cfg2)
767 pdata->fifo_cfg2 = 0x015500aa;
768 if (!pdata->fifo_cfg3)
769 pdata->fifo_cfg3 = 0x01f00140;
770 break;
771
772 case ATH79_SOC_AR9130:
773 if (id == 0) {
774 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
775 pdata->set_speed = ar91xx_set_speed_ge0;
776 } else {
777 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
778 pdata->set_speed = ar91xx_set_speed_ge1;
779 }
780 pdata->is_ar91xx = 1;
781 break;
782
783 case ATH79_SOC_AR9132:
784 if (id == 0) {
785 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
786 pdata->set_speed = ar91xx_set_speed_ge0;
787 } else {
788 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
789 pdata->set_speed = ar91xx_set_speed_ge1;
790 }
791 pdata->is_ar91xx = 1;
792 pdata->has_gbit = 1;
793 break;
794
795 case ATH79_SOC_AR9330:
796 case ATH79_SOC_AR9331:
797 if (id == 0) {
798 pdata->reset_bit = AR933X_RESET_GE0_MAC |
799 AR933X_RESET_GE0_MDIO;
800 pdata->ddr_flush = ar933x_ddr_flush_ge0;
801 pdata->set_speed = ath79_set_speed_dummy;
802
803 pdata->phy_mask = BIT(4);
804 } else {
805 pdata->reset_bit = AR933X_RESET_GE1_MAC |
806 AR933X_RESET_GE1_MDIO;
807 pdata->ddr_flush = ar933x_ddr_flush_ge1;
808 pdata->set_speed = ath79_set_speed_dummy;
809
810 pdata->speed = SPEED_1000;
811 pdata->duplex = DUPLEX_FULL;
812 pdata->switch_data = &ath79_switch_data;
813
814 ath79_switch_data.phy_poll_mask |= BIT(4);
815 }
816
817 pdata->has_gbit = 1;
818 pdata->is_ar724x = 1;
819
820 if (!pdata->fifo_cfg1)
821 pdata->fifo_cfg1 = 0x0010ffff;
822 if (!pdata->fifo_cfg2)
823 pdata->fifo_cfg2 = 0x015500aa;
824 if (!pdata->fifo_cfg3)
825 pdata->fifo_cfg3 = 0x01f00140;
826 break;
827
828 case ATH79_SOC_AR9341:
829 case ATH79_SOC_AR9342:
830 case ATH79_SOC_AR9344:
831 case ATH79_SOC_QCA9558:
832 if (id == 0) {
833 pdata->reset_bit = AR934X_RESET_GE0_MAC |
834 AR934X_RESET_GE0_MDIO;
835 pdata->set_speed = ar934x_set_speed_ge0;
836 } else {
837 pdata->reset_bit = AR934X_RESET_GE1_MAC |
838 AR934X_RESET_GE1_MDIO;
839 pdata->set_speed = ath79_set_speed_dummy;
840
841 pdata->switch_data = &ath79_switch_data;
842
843 /* reset the built-in switch */
844 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
845 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
846 }
847
848 pdata->ddr_flush = ath79_ddr_no_flush;
849 pdata->has_gbit = 1;
850 pdata->is_ar724x = 1;
851
852 if (!pdata->fifo_cfg1)
853 pdata->fifo_cfg1 = 0x0010ffff;
854 if (!pdata->fifo_cfg2)
855 pdata->fifo_cfg2 = 0x015500aa;
856 if (!pdata->fifo_cfg3)
857 pdata->fifo_cfg3 = 0x01f00140;
858 break;
859
860 default:
861 BUG();
862 }
863
864 switch (pdata->phy_if_mode) {
865 case PHY_INTERFACE_MODE_GMII:
866 case PHY_INTERFACE_MODE_RGMII:
867 if (!pdata->has_gbit) {
868 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
869 id);
870 return;
871 }
872 /* fallthrough */
873 default:
874 break;
875 }
876
877 if (!is_valid_ether_addr(pdata->mac_addr)) {
878 random_ether_addr(pdata->mac_addr);
879 printk(KERN_DEBUG
880 "ar71xx: using random MAC address for eth%d\n",
881 ath79_eth_instance);
882 }
883
884 if (pdata->mii_bus_dev == NULL) {
885 switch (ath79_soc) {
886 case ATH79_SOC_AR9341:
887 case ATH79_SOC_AR9342:
888 case ATH79_SOC_AR9344:
889 case ATH79_SOC_QCA9558:
890 if (id == 0)
891 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
892 else
893 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
894 break;
895
896 case ATH79_SOC_AR7241:
897 case ATH79_SOC_AR9330:
898 case ATH79_SOC_AR9331:
899 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
900 break;
901
902 default:
903 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
904 break;
905 }
906 }
907
908 /* Reset the device */
909 ath79_device_reset_set(pdata->reset_bit);
910 mdelay(100);
911
912 ath79_device_reset_clear(pdata->reset_bit);
913 mdelay(100);
914
915 platform_device_register(pdev);
916 ath79_eth_instance++;
917 }
918
919 void __init ath79_set_mac_base(unsigned char *mac)
920 {
921 memcpy(ath79_mac_base, mac, ETH_ALEN);
922 }
923
924 void __init ath79_parse_mac_addr(char *mac_str)
925 {
926 u8 tmp[ETH_ALEN];
927 int t;
928
929 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
930 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
931
932 if (t != ETH_ALEN)
933 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
934 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
935
936 if (t == ETH_ALEN)
937 ath79_set_mac_base(tmp);
938 else
939 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
940 "\"%s\"\n", mac_str);
941 }
942
943 static int __init ath79_ethaddr_setup(char *str)
944 {
945 ath79_parse_mac_addr(str);
946 return 1;
947 }
948 __setup("ethaddr=", ath79_ethaddr_setup);
949
950 static int __init ath79_kmac_setup(char *str)
951 {
952 ath79_parse_mac_addr(str);
953 return 1;
954 }
955 __setup("kmac=", ath79_kmac_setup);
956
957 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
958 int offset)
959 {
960 int t;
961
962 if (!is_valid_ether_addr(src)) {
963 memset(dst, '\0', ETH_ALEN);
964 return;
965 }
966
967 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
968 t += offset;
969
970 dst[0] = src[0];
971 dst[1] = src[1];
972 dst[2] = src[2];
973 dst[3] = (t >> 16) & 0xff;
974 dst[4] = (t >> 8) & 0xff;
975 dst[5] = t & 0xff;
976 }
977
978 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
979 {
980 int i;
981
982 if (!is_valid_ether_addr(src)) {
983 memset(dst, '\0', ETH_ALEN);
984 return;
985 }
986
987 for (i = 0; i < ETH_ALEN; i++)
988 dst[i] = src[i];
989 dst[0] |= 0x02;
990 }