ar71xx: add initial support for the QCA955X SoCs
authorGabor Juhos <juhosg@openwrt.org>
Thu, 5 Jul 2012 08:26:47 +0000 (08:26 +0000)
committerGabor Juhos <juhosg@openwrt.org>
Thu, 5 Jul 2012 08:26:47 +0000 (08:26 +0000)
SVN-Revision: 32606

23 files changed:
target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
target/linux/ar71xx/patches-3.3/160-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.3/161-MIPS-ath79-add-SoC-detection-code-for-the-QCA9558-So.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.3/164-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.3/165-MIPS-ath79-add-QCA955X-specific-glue-to-ath79_device.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.3/166-MIPS-ath79-register-UART-for-the-QCA955X-SoCs.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.3/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.3/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.3/169-MIPS-ath79-allow-to-specify-bus-number-in-PCI-IRQ-ma.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.3/170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch [new file with mode: 0644]
target/linux/ar71xx/patches-3.3/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch
target/linux/ar71xx/patches-3.3/502-MIPS-ath79-export-ath79_gpio_base.patch
target/linux/ar71xx/patches-3.3/503-MIPS-ath79-add-flash-acquire-release.patch
target/linux/ar71xx/patches-3.3/504-MIPS-ath79-add-ath79_device_reset_get.patch
target/linux/ar71xx/patches-3.3/509-MIPS-ath79-process-board-kernel-option.patch
target/linux/ar71xx/patches-3.3/511-MIPS-ath79-add-ath79_set_usb_power_gpio.patch
target/linux/ar71xx/patches-3.3/521-MIPS-ath79-enable-UART-for-early_serial.patch
target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
target/linux/ar71xx/patches-3.3/602-MIPS-ath79-add-openwrt-stuff.patch
target/linux/ar71xx/patches-3.3/610-MIPS-ath79-openwrt-machines.patch
target/linux/ar71xx/patches-3.3/620-MIPS-ath79-OTP-support.patch

index 45817e1..e6a5076 100644 (file)
@@ -154,7 +154,8 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
 
        if (ath79_soc == ATH79_SOC_AR9341 ||
            ath79_soc == ATH79_SOC_AR9342 ||
-           ath79_soc == ATH79_SOC_AR9344)
+           ath79_soc == ATH79_SOC_AR9344 ||
+           ath79_soc == ATH79_SOC_QCA9558)
                max_id = 1;
        else
                max_id = 0;
@@ -175,6 +176,7 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
        case ATH79_SOC_AR9341:
        case ATH79_SOC_AR9342:
        case ATH79_SOC_AR9344:
+       case ATH79_SOC_QCA9558:
                if (id == 0) {
                        mdio_dev = &ath79_mdio0_device;
                        mdio_data = &ath79_mdio0_data;
@@ -215,6 +217,7 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
        case ATH79_SOC_AR9341:
        case ATH79_SOC_AR9342:
        case ATH79_SOC_AR9344:
+       case ATH79_SOC_QCA9558:
                if (id == 1)
                        mdio_data->builtin_switch = 1;
                mdio_data->is_ar934x = 1;
@@ -504,6 +507,7 @@ static void __init ath79_init_eth_pll_data(unsigned int id)
        case ATH79_SOC_AR9341:
        case ATH79_SOC_AR9342:
        case ATH79_SOC_AR9344:
+       case ATH79_SOC_QCA9558:
                pll_10 = AR934X_PLL_VAL_10;
                pll_100 = AR934X_PLL_VAL_100;
                pll_1000 = AR934X_PLL_VAL_1000;
@@ -568,6 +572,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
                case ATH79_SOC_AR9341:
                case ATH79_SOC_AR9342:
                case ATH79_SOC_AR9344:
+               case ATH79_SOC_QCA9558:
                        switch (pdata->phy_if_mode) {
                        case PHY_INTERFACE_MODE_MII:
                        case PHY_INTERFACE_MODE_GMII:
@@ -616,6 +621,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
                case ATH79_SOC_AR9341:
                case ATH79_SOC_AR9342:
                case ATH79_SOC_AR9344:
+               case ATH79_SOC_QCA9558:
                        switch (pdata->phy_if_mode) {
                        case PHY_INTERFACE_MODE_MII:
                        case PHY_INTERFACE_MODE_GMII:
@@ -822,6 +828,7 @@ void __init ath79_register_eth(unsigned int id)
        case ATH79_SOC_AR9341:
        case ATH79_SOC_AR9342:
        case ATH79_SOC_AR9344:
+       case ATH79_SOC_QCA9558:
                if (id == 0) {
                        pdata->reset_bit = AR934X_RESET_GE0_MAC |
                                           AR934X_RESET_GE0_MDIO;
@@ -879,6 +886,7 @@ void __init ath79_register_eth(unsigned int id)
                case ATH79_SOC_AR9341:
                case ATH79_SOC_AR9342:
                case ATH79_SOC_AR9344:
+               case ATH79_SOC_QCA9558:
                        if (id == 0)
                                pdata->mii_bus_dev = &ath79_mdio0_device.dev;
                        else
diff --git a/target/linux/ar71xx/patches-3.3/160-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch b/target/linux/ar71xx/patches-3.3/160-MIPS-ath79-add-early-printk-support-for-the-QCA955X-.patch
new file mode 100644 (file)
index 0000000..4f781ed
--- /dev/null
@@ -0,0 +1,31 @@
+From 114df1e368b8503de1fe63e97d6eea521eecfbe4 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 24 Jun 2012 13:40:38 +0200
+Subject: [PATCH 16/34] MIPS: ath79: add early printk support for the QCA955X SoCs
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/early_printk.c                 |    1 +
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    1 +
+ 2 files changed, 2 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/ath79/early_printk.c
++++ b/arch/mips/ath79/early_printk.c
+@@ -74,6 +74,7 @@ static void prom_putchar_init(void)
+       case REV_ID_MAJOR_AR9341:
+       case REV_ID_MAJOR_AR9342:
+       case REV_ID_MAJOR_AR9344:
++      case REV_ID_MAJOR_QCA9558:
+               _prom_putchar = prom_putchar_ar71xx;
+               break;
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -368,6 +368,7 @@
+ #define REV_ID_MAJOR_AR9341           0x0120
+ #define REV_ID_MAJOR_AR9342           0x1120
+ #define REV_ID_MAJOR_AR9344           0x2120
++#define REV_ID_MAJOR_QCA9558          0x1130
+ #define AR71XX_REV_ID_MINOR_MASK      0x3
+ #define AR71XX_REV_ID_MINOR_AR7130    0x0
diff --git a/target/linux/ar71xx/patches-3.3/161-MIPS-ath79-add-SoC-detection-code-for-the-QCA9558-So.patch b/target/linux/ar71xx/patches-3.3/161-MIPS-ath79-add-SoC-detection-code-for-the-QCA9558-So.patch
new file mode 100644 (file)
index 0000000..e9b18e6
--- /dev/null
@@ -0,0 +1,91 @@
+From 3c3c0eccf63b12fea98fd0eb65d0ccf69a7c5a57 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 24 Jun 2012 13:42:16 +0200
+Subject: [PATCH 17/34] MIPS: ath79: add SoC detection code for the QCA9558 SoC
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/Kconfig                        |    4 ++++
+ arch/mips/ath79/setup.c                        |   12 +++++++++++-
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    2 ++
+ arch/mips/include/asm/mach-ath79/ath79.h       |   11 +++++++++++
+ 4 files changed, 28 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -88,6 +88,10 @@ config SOC_AR934X
+       select PCI_AR724X if PCI
+       def_bool n
++config SOC_QCA955X
++      select USB_ARCH_HAS_EHCI
++      def_bool n
++
+ config PCI_AR724X
+       def_bool n
+--- a/arch/mips/ath79/setup.c
++++ b/arch/mips/ath79/setup.c
+@@ -164,13 +164,23 @@ static void __init ath79_detect_sys_type
+               rev = id & AR934X_REV_ID_REVISION_MASK;
+               break;
++      case REV_ID_MAJOR_QCA9558:
++              ath79_soc = ATH79_SOC_QCA9558;
++              chip = "9558";
++              rev = id & AR944X_REV_ID_REVISION_MASK;
++              break;
++
+       default:
+               panic("ath79: unknown SoC, id:0x%08x", id);
+       }
+       ath79_soc_rev = rev;
+-      sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
++      if (soc_is_qca955x())
++              sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
++                      chip, rev);
++      else
++              sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
+       pr_info("SoC: %s\n", ath79_sys_type);
+ }
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -389,6 +389,8 @@
+ #define AR934X_REV_ID_REVISION_MASK     0xf
++#define AR944X_REV_ID_REVISION_MASK   0xf
++
+ /*
+  * SPI block
+  */
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -32,6 +32,7 @@ enum ath79_soc_type {
+       ATH79_SOC_AR9341,
+       ATH79_SOC_AR9342,
+       ATH79_SOC_AR9344,
++      ATH79_SOC_QCA9558,
+ };
+ extern enum ath79_soc_type ath79_soc;
+@@ -98,6 +99,16 @@ static inline int soc_is_ar934x(void)
+       return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
+ }
++static inline int soc_is_qca9558(void)
++{
++      return ath79_soc == ATH79_SOC_QCA9558;
++}
++
++static inline int soc_is_qca955x(void)
++{
++      return soc_is_qca9558();
++}
++
+ extern void __iomem *ath79_ddr_base;
+ extern void __iomem *ath79_pll_base;
+ extern void __iomem *ath79_reset_base;
diff --git a/target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch b/target/linux/ar71xx/patches-3.3/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch
new file mode 100644 (file)
index 0000000..ff8be83
--- /dev/null
@@ -0,0 +1,167 @@
+From f465a16766a015a31d4e83af1ad62cc718d64f5a Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 24 Jun 2012 13:43:08 +0200
+Subject: [PATCH 18/34] MIPS: ath79: add clock setup for the QCA955X SoCs
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/clock.c                        |   78 ++++++++++++++++++++++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |   39 ++++++++++++
+ 2 files changed, 117 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -242,6 +242,82 @@ static void __init ar934x_clocks_init(vo
+       ath79_uart_clk.rate = ath79_ref_clk.rate;
+ }
++static void __init qca955x_clocks_init(void)
++{
++      u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
++      u32 cpu_pll, ddr_pll;
++      u32 bootstrap;
++
++      bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
++      if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
++              ath79_ref_clk.rate = 40 * 1000 * 1000;
++      else
++              ath79_ref_clk.rate = 25 * 1000 * 1000;
++
++      pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
++      out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
++                QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
++      ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
++                QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
++      nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
++             QCA955X_PLL_CPU_CONFIG_NINT_MASK;
++      frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
++             QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
++
++      cpu_pll = nint * ath79_ref_clk.rate / ref_div;
++      cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6));
++      cpu_pll /= (1 << out_div);
++
++      pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
++      out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
++                QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
++      ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
++                QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
++      nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
++             QCA955X_PLL_DDR_CONFIG_NINT_MASK;
++      frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
++             QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
++
++      ddr_pll = nint * ath79_ref_clk.rate / ref_div;
++      ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10));
++      ddr_pll /= (1 << out_div);
++
++      clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
++
++      postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
++                QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
++
++      if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
++              ath79_cpu_clk.rate = ath79_ref_clk.rate;
++      else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
++              ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
++      else
++              ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
++
++      postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
++                QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
++
++      if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
++              ath79_ddr_clk.rate = ath79_ref_clk.rate;
++      else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
++              ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
++      else
++              ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
++
++      postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
++                QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
++
++      if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
++              ath79_ahb_clk.rate = ath79_ref_clk.rate;
++      else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
++              ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
++      else
++              ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
++
++      ath79_wdt_clk.rate = ath79_ref_clk.rate;
++      ath79_uart_clk.rate = ath79_ref_clk.rate;
++}
++
+ void __init ath79_clocks_init(void)
+ {
+       if (soc_is_ar71xx())
+@@ -254,6 +330,8 @@ void __init ath79_clocks_init(void)
+               ar933x_clocks_init();
+       else if (soc_is_ar934x())
+               ar934x_clocks_init();
++      else if (soc_is_qca955x())
++              qca955x_clocks_init();
+       else
+               BUG();
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -223,6 +223,41 @@
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL        BIT(21)
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL        BIT(24)
++#define QCA955X_PLL_CPU_CONFIG_REG            0x00
++#define QCA955X_PLL_DDR_CONFIG_REG            0x04
++#define QCA955X_PLL_CLK_CTRL_REG              0x08
++
++#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT    0
++#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK     0x3f
++#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT     6
++#define QCA955X_PLL_CPU_CONFIG_NINT_MASK      0x3f
++#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT   12
++#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK    0x1f
++#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT   19
++#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK    0x3
++
++#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT    0
++#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK     0x3ff
++#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT     10
++#define QCA955X_PLL_DDR_CONFIG_NINT_MASK      0x3f
++#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT   16
++#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK    0x1f
++#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT   23
++#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK    0x7
++
++#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS           BIT(2)
++#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS           BIT(3)
++#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS           BIT(4)
++#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT               5
++#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK                0x1f
++#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT               10
++#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK                0x1f
++#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT               15
++#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK                0x1f
++#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL               BIT(20)
++#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL               BIT(21)
++#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL               BIT(24)
++
+ /*
+  * USB_CONFIG block
+  */
+@@ -262,6 +297,8 @@
+ #define AR934X_RESET_REG_BOOTSTRAP            0xb0
+ #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
++#define QCA955X_RESET_REG_BOOTSTRAP           0xb0
++
+ #define MISC_INT_ETHSW                        BIT(12)
+ #define MISC_INT_TIMER4                       BIT(10)
+ #define MISC_INT_TIMER3                       BIT(9)
+@@ -339,6 +376,8 @@
+ #define AR934X_BOOTSTRAP_SDRAM_DISABLED       BIT(1)
+ #define AR934X_BOOTSTRAP_DDR1         BIT(0)
++#define QCA955X_BOOTSTRAP_REF_CLK_40  BIT(4)
++
+ #define AR934X_PCIE_WMAC_INT_WMAC_MISC                BIT(0)
+ #define AR934X_PCIE_WMAC_INT_WMAC_TX          BIT(1)
+ #define AR934X_PCIE_WMAC_INT_WMAC_RXLP                BIT(2)
diff --git a/target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch b/target/linux/ar71xx/patches-3.3/163-MIPS-ath79-add-IRQ-handling-code-for-the-QCA955X-SoC.patch
new file mode 100644 (file)
index 0000000..e4e2c30
--- /dev/null
@@ -0,0 +1,239 @@
+From 5d0de52f8e36916485a61b820916b71b5d918e6f Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 24 Jun 2012 13:44:23 +0200
+Subject: [PATCH 19/34] MIPS: ath79: add IRQ handling code for the QCA955X SoCs
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/irq.c                          |  110 ++++++++++++++++++++++--
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |   32 +++++++
+ arch/mips/include/asm/mach-ath79/irq.h         |    9 ++-
+ 3 files changed, 142 insertions(+), 9 deletions(-)
+
+--- a/arch/mips/ath79/irq.c
++++ b/arch/mips/ath79/irq.c
+@@ -130,7 +130,10 @@ static void __init ath79_misc_irq_init(v
+       if (soc_is_ar71xx() || soc_is_ar913x())
+               ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
+-      else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x())
++      else if (soc_is_ar724x() ||
++               soc_is_ar933x() ||
++               soc_is_ar934x() ||
++               soc_is_qca955x())
+               ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
+       else
+               BUG();
+@@ -177,6 +180,88 @@ static void ar934x_ip2_irq_init(void)
+       irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch);
+ }
++static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
++{
++      u32 status;
++
++      disable_irq_nosync(irq);
++
++      status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
++      status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
++
++      if (status == 0) {
++              spurious_interrupt();
++              goto enable;
++      }
++
++      if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
++              /* TODO: flush DDR? */
++              generic_handle_irq(ATH79_IP2_IRQ(0));
++      }
++
++      if (status & QCA955X_EXT_INT_WMAC_ALL) {
++              /* TODO: flsuh DDR? */
++              generic_handle_irq(ATH79_IP2_IRQ(1));
++      }
++
++enable:
++      enable_irq(irq);
++}
++
++static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
++{
++      u32 status;
++
++      disable_irq_nosync(irq);
++
++      status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
++      status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
++                QCA955X_EXT_INT_USB1 |
++                QCA955X_EXT_INT_USB2;
++
++      if (status == 0) {
++              spurious_interrupt();
++              goto enable;
++      }
++
++      if (status & QCA955X_EXT_INT_USB1) {
++              /* TODO: flush DDR? */
++              generic_handle_irq(ATH79_IP3_IRQ(0));
++      }
++
++      if (status & QCA955X_EXT_INT_USB2) {
++              /* TODO: flsuh DDR? */
++              generic_handle_irq(ATH79_IP3_IRQ(1));
++      }
++
++      if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
++              /* TODO: flush DDR? */
++              generic_handle_irq(ATH79_IP3_IRQ(2));
++      }
++
++enable:
++      enable_irq(irq);
++}
++
++static void qca955x_irq_init(void)
++{
++      int i;
++
++      for (i = ATH79_IP2_IRQ_BASE;
++           i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
++              irq_set_chip_and_handler(i, &dummy_irq_chip,
++                                       handle_level_irq);
++
++      irq_set_chained_handler(ATH79_CPU_IRQ_IP2, qca955x_ip2_irq_dispatch);
++
++      for (i = ATH79_IP3_IRQ_BASE;
++           i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
++              irq_set_chip_and_handler(i, &dummy_irq_chip,
++                                       handle_level_irq);
++
++      irq_set_chained_handler(ATH79_CPU_IRQ_IP3, qca955x_ip3_irq_dispatch);
++}
++
+ asmlinkage void plat_irq_dispatch(void)
+ {
+       unsigned long pending;
+@@ -212,6 +297,17 @@ asmlinkage void plat_irq_dispatch(void)
+  * Issue a flush in the handlers to ensure that the driver sees
+  * the update.
+  */
++
++static void ath79_default_ip2_handler(void)
++{
++      do_IRQ(ATH79_CPU_IRQ_IP2);
++}
++
++static void ath79_default_ip3_handler(void)
++{
++      do_IRQ(ATH79_CPU_IRQ_USB);
++}
++
+ static void ar71xx_ip2_handler(void)
+ {
+       ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI);
+@@ -236,11 +332,6 @@ static void ar933x_ip2_handler(void)
+       do_IRQ(ATH79_CPU_IRQ_IP2);
+ }
+-static void ar934x_ip2_handler(void)
+-{
+-      do_IRQ(ATH79_CPU_IRQ_IP2);
+-}
+-
+ static void ar71xx_ip3_handler(void)
+ {
+       ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
+@@ -286,8 +377,11 @@ void __init arch_init_irq(void)
+               ath79_ip2_handler = ar933x_ip2_handler;
+               ath79_ip3_handler = ar933x_ip3_handler;
+       } else if (soc_is_ar934x()) {
+-              ath79_ip2_handler = ar934x_ip2_handler;
++              ath79_ip2_handler = ath79_default_ip2_handler;
+               ath79_ip3_handler = ar934x_ip3_handler;
++      } else if (soc_is_qca955x()) {
++              ath79_ip2_handler = ath79_default_ip2_handler;
++              ath79_ip3_handler = ath79_default_ip3_handler;
+       } else {
+               BUG();
+       }
+@@ -298,4 +392,6 @@ void __init arch_init_irq(void)
+       if (soc_is_ar934x())
+               ar934x_ip2_irq_init();
++      else if (soc_is_qca955x())
++              qca955x_irq_init();
+ }
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -298,6 +298,7 @@
+ #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
+ #define QCA955X_RESET_REG_BOOTSTRAP           0xb0
++#define QCA955X_RESET_REG_EXT_INT_STATUS      0xac
+ #define MISC_INT_ETHSW                        BIT(12)
+ #define MISC_INT_TIMER4                       BIT(10)
+@@ -396,6 +397,37 @@
+        AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
+        AR934X_PCIE_WMAC_INT_PCIE_RC3)
++#define QCA955X_EXT_INT_WMAC_MISC             BIT(0)
++#define QCA955X_EXT_INT_WMAC_TX                       BIT(1)
++#define QCA955X_EXT_INT_WMAC_RXLP             BIT(2)
++#define QCA955X_EXT_INT_WMAC_RXHP             BIT(3)
++#define QCA955X_EXT_INT_PCIE_RC1              BIT(4)
++#define QCA955X_EXT_INT_PCIE_RC1_INT0         BIT(5)
++#define QCA955X_EXT_INT_PCIE_RC1_INT1         BIT(6)
++#define QCA955X_EXT_INT_PCIE_RC1_INT2         BIT(7)
++#define QCA955X_EXT_INT_PCIE_RC1_INT3         BIT(8)
++#define QCA955X_EXT_INT_PCIE_RC2              BIT(12)
++#define QCA955X_EXT_INT_PCIE_RC2_INT0         BIT(13)
++#define QCA955X_EXT_INT_PCIE_RC2_INT1         BIT(14)
++#define QCA955X_EXT_INT_PCIE_RC2_INT2         BIT(15)
++#define QCA955X_EXT_INT_PCIE_RC2_INT3         BIT(16)
++#define QCA955X_EXT_INT_USB1                  BIT(24)
++#define QCA955X_EXT_INT_USB2                  BIT(28)
++
++#define QCA955X_EXT_INT_WMAC_ALL \
++      (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
++       QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
++
++#define QCA955X_EXT_INT_PCIE_RC1_ALL \
++      (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
++       QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
++       QCA955X_EXT_INT_PCIE_RC1_INT3)
++
++#define QCA955X_EXT_INT_PCIE_RC2_ALL \
++      (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
++       QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
++       QCA955X_EXT_INT_PCIE_RC2_INT3)
++
+ #define REV_ID_MAJOR_MASK             0xfff0
+ #define REV_ID_MAJOR_AR71XX           0x00a0
+ #define REV_ID_MAJOR_AR913X           0x00b0
+--- a/arch/mips/include/asm/mach-ath79/irq.h
++++ b/arch/mips/include/asm/mach-ath79/irq.h
+@@ -10,7 +10,7 @@
+ #define __ASM_MACH_ATH79_IRQ_H
+ #define MIPS_CPU_IRQ_BASE     0
+-#define NR_IRQS                       48
++#define NR_IRQS                       51
+ #define ATH79_MISC_IRQ_BASE   8
+ #define ATH79_MISC_IRQ_COUNT  32
+@@ -23,8 +23,13 @@
+ #define ATH79_IP2_IRQ_COUNT   2
+ #define ATH79_IP2_IRQ(_x)     (ATH79_IP2_IRQ_BASE + (_x))
++#define ATH79_IP3_IRQ_BASE    (ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT)
++#define ATH79_IP3_IRQ_COUNT     3
++#define ATH79_IP3_IRQ(_x)       (ATH79_IP3_IRQ_BASE + (_x))
++
+ #define ATH79_CPU_IRQ_IP2     (MIPS_CPU_IRQ_BASE + 2)
+-#define ATH79_CPU_IRQ_USB     (MIPS_CPU_IRQ_BASE + 3)
++#define ATH79_CPU_IRQ_IP3     (MIPS_CPU_IRQ_BASE + 3)
++#define ATH79_CPU_IRQ_USB     ATH79_CPU_IRQ_IP3
+ #define ATH79_CPU_IRQ_GE0     (MIPS_CPU_IRQ_BASE + 4)
+ #define ATH79_CPU_IRQ_GE1     (MIPS_CPU_IRQ_BASE + 5)
+ #define ATH79_CPU_IRQ_MISC    (MIPS_CPU_IRQ_BASE + 6)
diff --git a/target/linux/ar71xx/patches-3.3/164-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch b/target/linux/ar71xx/patches-3.3/164-MIPS-ath79-add-GPIO-setup-code-for-the-QCA955X-SoCs.patch
new file mode 100644 (file)
index 0000000..9dba29a
--- /dev/null
@@ -0,0 +1,38 @@
+From c9a552f3007f0621b2440ae17bad816578299e52 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 24 Jun 2012 13:45:27 +0200
+Subject: [PATCH 20/34] MIPS: ath79: add GPIO setup code for the QCA955X SoCs
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/gpio.c                         |    4 +++-
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    1 +
+ 2 files changed, 4 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -196,12 +196,14 @@ void __init ath79_gpio_init(void)
+               ath79_gpio_count = AR933X_GPIO_COUNT;
+       else if (soc_is_ar934x())
+               ath79_gpio_count = AR934X_GPIO_COUNT;
++      else if (soc_is_qca955x())
++              ath79_gpio_count = QCA955X_GPIO_COUNT;
+       else
+               BUG();
+       ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
+       ath79_gpio_chip.ngpio = ath79_gpio_count;
+-      if (soc_is_ar934x()) {
++      if (soc_is_ar934x() || soc_is_qca955x()) {
+               ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
+               ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
+       }
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -504,5 +504,6 @@
+ #define AR913X_GPIO_COUNT             22
+ #define AR933X_GPIO_COUNT             30
+ #define AR934X_GPIO_COUNT             23
++#define QCA955X_GPIO_COUNT            24
+ #endif /* __ASM_MACH_AR71XX_REGS_H */
diff --git a/target/linux/ar71xx/patches-3.3/165-MIPS-ath79-add-QCA955X-specific-glue-to-ath79_device.patch b/target/linux/ar71xx/patches-3.3/165-MIPS-ath79-add-QCA955X-specific-glue-to-ath79_device.patch
new file mode 100644 (file)
index 0000000..f3e3b6e
--- /dev/null
@@ -0,0 +1,31 @@
+From 68368e80b4db83afe39664a7d43c8b5c7b8ac3b4 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 24 Jun 2012 13:49:33 +0200
+Subject: [PATCH 21/34] MIPS: ath79: add QCA955X specific glue to ath79_device_reset_{set,clear}
+
+---
+ arch/mips/ath79/common.c |    6 ++++--
+ 1 files changed, 4 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -70,7 +70,8 @@ void ath79_device_reset_set(u32 mask)
+               reg = AR913X_RESET_REG_RESET_MODULE;
+       else if (soc_is_ar933x())
+               reg = AR933X_RESET_REG_RESET_MODULE;
+-      else if (soc_is_ar934x())
++      else if (soc_is_ar934x() ||
++               soc_is_qca955x())
+               reg = AR934X_RESET_REG_RESET_MODULE;
+       else
+               BUG();
+@@ -96,7 +97,8 @@ void ath79_device_reset_clear(u32 mask)
+               reg = AR913X_RESET_REG_RESET_MODULE;
+       else if (soc_is_ar933x())
+               reg = AR933X_RESET_REG_RESET_MODULE;
+-      else if (soc_is_ar934x())
++      else if (soc_is_ar934x() ||
++               soc_is_qca955x())
+               reg = AR934X_RESET_REG_RESET_MODULE;
+       else
+               BUG();
diff --git a/target/linux/ar71xx/patches-3.3/166-MIPS-ath79-register-UART-for-the-QCA955X-SoCs.patch b/target/linux/ar71xx/patches-3.3/166-MIPS-ath79-register-UART-for-the-QCA955X-SoCs.patch
new file mode 100644 (file)
index 0000000..aacb8bb
--- /dev/null
@@ -0,0 +1,22 @@
+From f7d7b362b51c51c1ae80bb7ade2039d6f74d4070 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 24 Jun 2012 13:46:26 +0200
+Subject: [PATCH 22/34] MIPS: ath79: register UART for the QCA955X SoCs
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/dev-common.c |    3 ++-
+ 1 files changed, 2 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/ath79/dev-common.c
++++ b/arch/mips/ath79/dev-common.c
+@@ -90,7 +90,8 @@ void __init ath79_register_uart(void)
+       if (soc_is_ar71xx() ||
+           soc_is_ar724x() ||
+           soc_is_ar913x() ||
+-          soc_is_ar934x()) {
++          soc_is_ar934x() ||
++          soc_is_qca955x()) {
+               ath79_uart_data[0].uartclk = clk_get_rate(clk);
+               platform_device_register(&ath79_uart_device);
+       } else if (soc_is_ar933x()) {
diff --git a/target/linux/ar71xx/patches-3.3/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch b/target/linux/ar71xx/patches-3.3/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch
new file mode 100644 (file)
index 0000000..c6b7814
--- /dev/null
@@ -0,0 +1,93 @@
+From e4ba5e2bffd1f373f57dd692233aa6b7b46ae76c Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 24 Jun 2012 13:47:35 +0200
+Subject: [PATCH 23/34] MIPS: ath79: add USB controller registration code for the QCA955X SoCs
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/dev-usb.c                      |   46 ++++++++++++++++++++++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    4 ++
+ 2 files changed, 50 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/ath79/dev-usb.c
++++ b/arch/mips/ath79/dev-usb.c
+@@ -75,6 +75,8 @@ static void __init ath79_usb_init_resour
+                                          unsigned long size,
+                                          int irq)
+ {
++      memset(res, 0, sizeof(res));
++
+       res[0].flags = IORESOURCE_MEM;
+       res[0].start = base;
+       res[0].end = base + size - 1;
+@@ -219,6 +221,48 @@ static void __init ar934x_usb_setup(void
+       platform_device_register(&ath79_ehci_device);
+ }
++static void __init qca955x_usb_setup(void)
++{
++      struct platform_device *pdev;
++
++      ath79_usb_init_resource(ath79_ehci_resources,
++                              QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE,
++                              ATH79_IP3_IRQ(0));
++
++      pdev = platform_device_register_resndata(NULL, "ehci-platform", 0,
++                                               ath79_ehci_resources,
++                                               ARRAY_SIZE(ath79_ehci_resources),
++                                               &ath79_ehci_pdata_v2,
++                                               sizeof(ath79_ehci_pdata_v2));
++      if (IS_ERR(pdev)) {
++              pr_err("Unable to register USB %d device, err=%d\n", 0,
++                      (int) PTR_ERR(pdev));
++              return;
++      }
++
++      pdev->dev.dma_mask = &ath79_ehci_dmamask;
++      pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
++
++      ath79_usb_init_resource(ath79_ehci_resources,
++                              QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE,
++                              ATH79_IP3_IRQ(1));
++
++      pdev = platform_device_register_resndata(NULL, "ehci-platform", 1,
++                                               ath79_ehci_resources,
++                                               ARRAY_SIZE(ath79_ehci_resources),
++                                               &ath79_ehci_pdata_v2,
++                                               sizeof(ath79_ehci_pdata_v2));
++
++      if (IS_ERR(pdev)) {
++              pr_err("Unable to register USB %d device, err=%d\n", 1,
++                      (int) PTR_ERR(pdev));
++              return;
++      }
++
++      pdev->dev.dma_mask = &ath79_ehci_dmamask;
++      pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
++}
++
+ void __init ath79_register_usb(void)
+ {
+       if (soc_is_ar71xx())
+@@ -233,6 +277,8 @@ void __init ath79_register_usb(void)
+               ar933x_usb_setup();
+       else if (soc_is_ar934x())
+               ar934x_usb_setup();
++      else if (soc_is_qca955x())
++              qca955x_usb_setup();
+       else
+               BUG();
+ }
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -92,6 +92,10 @@
+ #define AR934X_EHCI_BASE      0x1b000000
+ #define AR934X_EHCI_SIZE      0x1000
++#define QCA955X_EHCI0_BASE    0x1b000000
++#define QCA955X_EHCI1_BASE    0x1b400000
++#define QCA955X_EHCI_SIZE     0x1000
++
+ /*
+  * DDR_CTRL block
+  */
diff --git a/target/linux/ar71xx/patches-3.3/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch b/target/linux/ar71xx/patches-3.3/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch
new file mode 100644 (file)
index 0000000..f5dabad
--- /dev/null
@@ -0,0 +1,70 @@
+From 0568e7f92ecf2bfd2af0a5c59b1249fef002c89f Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Tue, 3 Jul 2012 10:24:43 +0200
+Subject: [PATCH 24/34] MIPS: ath79: add WMAC registration code for the QCA955X SoCs
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/Kconfig                        |    2 +-
+ arch/mips/ath79/dev-wmac.c                     |   20 ++++++++++++++++++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |    2 ++
+ 3 files changed, 23 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -108,7 +108,7 @@ config ATH79_DEV_USB
+       def_bool n
+ config ATH79_DEV_WMAC
+-      depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X)
++      depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
+       def_bool n
+ endif
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -116,6 +116,24 @@ static void ar934x_wmac_setup(void)
+               ath79_wmac_data.is_clk_25mhz = true;
+ }
++static void qca955x_wmac_setup(void)
++{
++      u32 t;
++
++      ath79_wmac_device.name = "qca955x_wmac";
++
++      ath79_wmac_resources[0].start = QCA955X_WMAC_BASE;
++      ath79_wmac_resources[0].end = QCA955X_WMAC_BASE + QCA955X_WMAC_SIZE - 1;
++      ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
++      ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
++
++      t = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
++      if (t & QCA955X_BOOTSTRAP_REF_CLK_40)
++              ath79_wmac_data.is_clk_25mhz = false;
++      else
++              ath79_wmac_data.is_clk_25mhz = true;
++}
++
+ void __init ath79_register_wmac(u8 *cal_data)
+ {
+       if (soc_is_ar913x())
+@@ -124,6 +142,8 @@ void __init ath79_register_wmac(u8 *cal_
+               ar933x_wmac_setup();
+       else if (soc_is_ar934x())
+               ar934x_wmac_setup();
++      else if (soc_is_qca955x())
++              qca955x_wmac_setup();
+       else
+               BUG();
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -92,6 +92,8 @@
+ #define AR934X_EHCI_BASE      0x1b000000
+ #define AR934X_EHCI_SIZE      0x1000
++#define QCA955X_WMAC_BASE     (AR71XX_APB_BASE + 0x00100000)
++#define QCA955X_WMAC_SIZE     0x20000
+ #define QCA955X_EHCI0_BASE    0x1b000000
+ #define QCA955X_EHCI1_BASE    0x1b400000
+ #define QCA955X_EHCI_SIZE     0x1000
diff --git a/target/linux/ar71xx/patches-3.3/169-MIPS-ath79-allow-to-specify-bus-number-in-PCI-IRQ-ma.patch b/target/linux/ar71xx/patches-3.3/169-MIPS-ath79-allow-to-specify-bus-number-in-PCI-IRQ-ma.patch
new file mode 100644 (file)
index 0000000..bd95d71
--- /dev/null
@@ -0,0 +1,34 @@
+From 12c68e4fccadc22a0470177141a57892a76e4a2b Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 24 Jun 2012 15:33:16 +0200
+Subject: [PATCH 25/34] MIPS: ath79: allow to specify bus number in PCI IRQ maps
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/pci.c |    4 +++-
+ arch/mips/ath79/pci.h |    1 +
+ 2 files changed, 4 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -75,7 +75,9 @@ int __init pcibios_map_irq(const struct
+               const struct ath79_pci_irq *entry;
+               entry = &ath79_pci_irq_map[i];
+-              if (entry->slot == slot && entry->pin == pin) {
++              if (entry->bus == dev->bus->number &&
++                  entry->slot == slot &&
++                  entry->pin == pin) {
+                       irq = entry->irq;
+                       break;
+               }
+--- a/arch/mips/ath79/pci.h
++++ b/arch/mips/ath79/pci.h
+@@ -14,6 +14,7 @@
+ #define _ATH79_PCI_H
+ struct ath79_pci_irq {
++      int     bus;
+       u8      slot;
+       u8      pin;
+       int     irq;
diff --git a/target/linux/ar71xx/patches-3.3/170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch b/target/linux/ar71xx/patches-3.3/170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch
new file mode 100644 (file)
index 0000000..ccf25ed
--- /dev/null
@@ -0,0 +1,103 @@
+From 8bb54348722216a1dd6905d9d031ebdaa3a544a4 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 24 Jun 2012 23:05:20 +0200
+Subject: [PATCH 26/34] MIPS: ath79: add PCI controller registration code for the QCA9558 SoC
+
+---
+ arch/mips/ath79/Kconfig                        |    2 +
+ arch/mips/ath79/pci.c                          |   36 ++++++++++++++++++++++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h |   13 ++++++++
+ 3 files changed, 51 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -90,6 +90,8 @@ config SOC_AR934X
+ config SOC_QCA955X
+       select USB_ARCH_HAS_EHCI
++      select HW_HAS_PCI
++      select PCI_AR724X if PCI
+       def_bool n
+ config PCI_AR724X
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -49,6 +49,21 @@ static const struct ath79_pci_irq ar724x
+       }
+ };
++static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = {
++      {
++              .bus    = 0,
++              .slot   = 0,
++              .pin    = 1,
++              .irq    = ATH79_PCI_IRQ(0),
++      },
++      {
++              .bus    = 1,
++              .slot   = 0,
++              .pin    = 1,
++              .irq    = ATH79_PCI_IRQ(1),
++      },
++};
++
+ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
+ {
+       int irq = -1;
+@@ -64,6 +79,9 @@ int __init pcibios_map_irq(const struct
+                          soc_is_ar9344()) {
+                       ath79_pci_irq_map = ar724x_pci_irq_map;
+                       ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
++              } else if (soc_is_qca955x()) {
++                      ath79_pci_irq_map = qca955x_pci_irq_map;
++                      ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
+               } else {
+                       pr_crit("pci %s: invalid irq map\n",
+                               pci_name((struct pci_dev *) dev));
+@@ -215,6 +233,24 @@ int __init ath79_register_pci(void)
+                                                AR724X_PCI_MEM_SIZE,
+                                                0,
+                                                ATH79_IP2_IRQ(0));
++      } else if (soc_is_qca9558()) {
++              pdev = ath79_register_pci_ar724x(0,
++                                               QCA955X_PCI_CFG_BASE0,
++                                               QCA955X_PCI_CTRL_BASE0,
++                                               QCA955X_PCI_CRP_BASE0,
++                                               QCA955X_PCI_MEM_BASE0,
++                                               QCA955X_PCI_MEM_SIZE,
++                                               0,
++                                               ATH79_IP2_IRQ(0));
++
++              pdev = ath79_register_pci_ar724x(1,
++                                               QCA955X_PCI_CFG_BASE1,
++                                               QCA955X_PCI_CTRL_BASE1,
++                                               QCA955X_PCI_CRP_BASE1,
++                                               QCA955X_PCI_MEM_BASE1,
++                                               QCA955X_PCI_MEM_SIZE,
++                                               1,
++                                               ATH79_IP3_IRQ(2));
+       } else {
+               /* No PCI support */
+               return -ENODEV;
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -92,6 +92,19 @@
+ #define AR934X_EHCI_BASE      0x1b000000
+ #define AR934X_EHCI_SIZE      0x1000
++#define QCA955X_PCI_MEM_BASE0 0x10000000
++#define QCA955X_PCI_MEM_BASE1 0x12000000
++#define QCA955X_PCI_MEM_SIZE  0x02000000
++#define QCA955X_PCI_CFG_BASE0 0x14000000
++#define QCA955X_PCI_CFG_BASE1 0x16000000
++#define QCA955X_PCI_CFG_SIZE  0x1000
++#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
++#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
++#define QCA955X_PCI_CRP_SIZE  0x1000
++#define QCA955X_PCI_CTRL_BASE0        (AR71XX_APB_BASE + 0x000f0000)
++#define QCA955X_PCI_CTRL_BASE1        (AR71XX_APB_BASE + 0x00280000)
++#define QCA955X_PCI_CTRL_SIZE 0x100
++
+ #define QCA955X_WMAC_BASE     (AR71XX_APB_BASE + 0x00100000)
+ #define QCA955X_WMAC_SIZE     0x20000
+ #define QCA955X_EHCI0_BASE    0x1b000000
index 1ce8906..bab4f70 100644 (file)
@@ -16,7 +16,7 @@
  static struct ath9k_platform_data ath79_wmac_data;
  
  static struct resource ath79_wmac_resources[] = {
-@@ -116,7 +118,7 @@ static void ar934x_wmac_setup(void)
+@@ -134,7 +136,7 @@ static void qca955x_wmac_setup(void)
                ath79_wmac_data.is_clk_25mhz = true;
  }
  
@@ -25,7 +25,7 @@
  {
        if (soc_is_ar913x())
                ar913x_wmac_setup();
-@@ -131,5 +133,10 @@ void __init ath79_register_wmac(u8 *cal_
+@@ -151,5 +153,10 @@ void __init ath79_register_wmac(u8 *cal_
                memcpy(ath79_wmac_data.eeprom_data, cal_data,
                       sizeof(ath79_wmac_data.eeprom_data));
  
index 9b16c42..0a218a6 100644 (file)
@@ -13,7 +13,7 @@
  
 --- a/arch/mips/include/asm/mach-ath79/ath79.h
 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -99,6 +99,7 @@ static inline int soc_is_ar934x(void)
+@@ -110,6 +110,7 @@ static inline int soc_is_qca955x(void)
  }
  
  extern void __iomem *ath79_ddr_base;
index 2c9cad1..81350ca 100644 (file)
@@ -8,7 +8,7 @@
  
  u32 ath79_cpu_freq;
  EXPORT_SYMBOL_GPL(ath79_cpu_freq);
-@@ -107,3 +108,16 @@ void ath79_device_reset_clear(u32 mask)
+@@ -109,3 +110,16 @@ void ath79_device_reset_clear(u32 mask)
        spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
  }
  EXPORT_SYMBOL_GPL(ath79_device_reset_clear);
@@ -27,7 +27,7 @@
 +
 --- a/arch/mips/include/asm/mach-ath79/ath79.h
 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -126,4 +126,7 @@ static inline u32 ath79_reset_rr(unsigne
+@@ -137,4 +137,7 @@ static inline u32 ath79_reset_rr(unsigne
  void ath79_device_reset_set(u32 mask);
  void ath79_device_reset_clear(u32 mask);
  
index 5179a53..5578099 100644 (file)
@@ -1,6 +1,6 @@
 --- a/arch/mips/include/asm/mach-ath79/ath79.h
 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
-@@ -125,6 +125,7 @@ static inline u32 ath79_reset_rr(unsigne
+@@ -136,6 +136,7 @@ static inline u32 ath79_reset_rr(unsigne
  
  void ath79_device_reset_set(u32 mask);
  void ath79_device_reset_clear(u32 mask);
@@ -10,7 +10,7 @@
  void ath79_flash_release(void);
 --- a/arch/mips/ath79/common.c
 +++ b/arch/mips/ath79/common.c
-@@ -109,6 +109,32 @@ void ath79_device_reset_clear(u32 mask)
+@@ -111,6 +111,32 @@ void ath79_device_reset_clear(u32 mask)
  }
  EXPORT_SYMBOL_GPL(ath79_device_reset_clear);
  
index 8b7e2d4..9236c66 100644 (file)
@@ -1,6 +1,6 @@
 --- a/arch/mips/ath79/setup.c
 +++ b/arch/mips/ath79/setup.c
-@@ -215,6 +215,8 @@ void __init plat_time_init(void)
+@@ -225,6 +225,8 @@ void __init plat_time_init(void)
        mips_hpt_frequency = clk_get_rate(clk) / 2;
  }
  
index fa81789..91a793d 100644 (file)
@@ -8,7 +8,7 @@
  #include <linux/dma-mapping.h>
  #include <linux/platform_device.h>
  #include <linux/usb/ehci_pdriver.h>
-@@ -236,3 +237,26 @@ void __init ath79_register_usb(void)
+@@ -282,3 +283,26 @@ void __init ath79_register_usb(void)
        else
                BUG();
  }
index b96ea3a..489bc96 100644 (file)
@@ -47,7 +47,7 @@
  static void prom_putchar_init(void)
  {
        void __iomem *base;
-@@ -84,8 +124,10 @@ static void prom_putchar_init(void)
+@@ -85,8 +125,10 @@ static void prom_putchar_init(void)
  
        default:
                _prom_putchar = prom_putchar_dummy;
index cb18fd2..7166475 100644 (file)
  #define AR934X_WMAC_BASE      (AR71XX_APB_BASE + 0x00100000)
  #define AR934X_WMAC_SIZE      0x20000
  #define AR934X_EHCI_BASE      0x1b000000
-@@ -146,6 +156,9 @@
+@@ -110,6 +120,8 @@
+ #define QCA955X_EHCI0_BASE    0x1b000000
+ #define QCA955X_EHCI1_BASE    0x1b400000
+ #define QCA955X_EHCI_SIZE     0x1000
++#define QCA955X_GMAC_BASE     (AR71XX_APB_BASE + 0x00070000)
++#define QCA955X_GMAC_SIZE     0x40
+ /*
+  * DDR_CTRL block
+@@ -165,6 +177,9 @@
  #define AR71XX_AHB_DIV_SHIFT          20
  #define AR71XX_AHB_DIV_MASK           0x7
  
@@ -46,7 +55,7 @@
  #define AR724X_PLL_REG_CPU_CONFIG     0x00
  #define AR724X_PLL_REG_PCIE_CONFIG    0x18
  
-@@ -158,6 +171,8 @@
+@@ -177,6 +192,8 @@
  #define AR724X_DDR_DIV_SHIFT          22
  #define AR724X_DDR_DIV_MASK           0x3
  
@@ -55,7 +64,7 @@
  #define AR913X_PLL_REG_CPU_CONFIG     0x00
  #define AR913X_PLL_REG_ETH_CONFIG     0x04
  #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
-@@ -170,6 +185,9 @@
+@@ -189,6 +206,9 @@
  #define AR913X_AHB_DIV_SHIFT          19
  #define AR913X_AHB_DIV_MASK           0x1
  
@@ -65,7 +74,7 @@
  #define AR933X_PLL_CPU_CONFIG_REG     0x00
  #define AR933X_PLL_CLOCK_CTRL_REG     0x08
  
-@@ -191,6 +209,7 @@
+@@ -210,6 +230,7 @@
  #define AR934X_PLL_CPU_CONFIG_REG             0x00
  #define AR934X_PLL_DDR_CONFIG_REG             0x04
  #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG               0x08
@@ -73,7 +82,7 @@
  
  #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT     0
  #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK      0x3f
-@@ -311,16 +330,50 @@
+@@ -368,16 +389,50 @@
  #define AR913X_RESET_USB_HOST         BIT(5)
  #define AR913X_RESET_USB_PHY          BIT(4)
  
  #define AR933X_BOOTSTRAP_REF_CLK_40   BIT(0)
  
  #define AR934X_BOOTSTRAP_SW_OPTION8   BIT(23)
-@@ -425,10 +478,138 @@
+@@ -518,6 +573,14 @@
  #define AR71XX_GPIO_REG_INT_ENABLE    0x24
  #define AR71XX_GPIO_REG_FUNC          0x28
  
  #define AR71XX_GPIO_COUNT             16
  #define AR724X_GPIO_COUNT             18
  #define AR913X_GPIO_COUNT             22
- #define AR933X_GPIO_COUNT             30
+@@ -525,4 +588,133 @@
  #define AR934X_GPIO_COUNT             23
+ #define QCA955X_GPIO_COUNT            24
  
 +#define AR71XX_GPIO_FUNC_STEREO_EN            BIT(17)
 +#define AR71XX_GPIO_FUNC_SLIC_EN              BIT(16)
 +#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
 +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
 +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST       BIT(13)
++
++/*
++ * QCA955X GMAC Interface
++ */
++
++#define QCA955X_GMAC_REG_ETH_CFG      0x00
++
++#define QCA955X_ETH_CFG_RGMII_GMAC0   BIT(0)
++#define QCA955X_ETH_CFG_SGMII_GMAC0   BIT(6)
 +
  #endif /* __ASM_MACH_AR71XX_REGS_H */
index a29d791..d2cbf5a 100644 (file)
@@ -1,6 +1,6 @@
 --- a/arch/mips/ath79/Kconfig
 +++ b/arch/mips/ath79/Kconfig
-@@ -88,6 +88,20 @@ config SOC_AR934X
+@@ -94,6 +94,20 @@ config SOC_QCA955X
        select PCI_AR724X if PCI
        def_bool n
  
@@ -21,8 +21,8 @@
  config PCI_AR724X
        def_bool n
  
-@@ -107,4 +121,10 @@ config ATH79_DEV_WMAC
-       depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X)
+@@ -113,4 +127,10 @@ config ATH79_DEV_WMAC
+       depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
        def_bool n
  
 +config ATH79_NVRAM
index b132f58..cced6f1 100644 (file)
  endmenu
  
  config SOC_AR71XX
-@@ -96,10 +561,6 @@ config SOC_AR934X
+@@ -102,10 +567,6 @@ config SOC_QCA955X
        select PCI_AR724X if PCI
        def_bool n
  
  config ATH79_DEV_AP9X_PCI
        select ATH79_PCI_ATH9K_FIXUP
        def_bool n
-@@ -110,7 +571,14 @@ config ATH79_DEV_DSA
+@@ -116,7 +577,14 @@ config ATH79_DEV_DSA
  config ATH79_DEV_ETH
        def_bool n
  
        def_bool n
  
  config ATH79_DEV_GPIO_BUTTONS
-@@ -135,4 +603,7 @@ config ATH79_NVRAM
+@@ -141,4 +609,7 @@ config ATH79_NVRAM
  config ATH79_PCI_ATH9K_FIXUP
        def_bool n
  
index 7859eba..0c24ff5 100644 (file)
@@ -1,6 +1,6 @@
 --- a/arch/mips/ath79/dev-wmac.c
 +++ b/arch/mips/ath79/dev-wmac.c
-@@ -121,6 +121,137 @@ static void ar934x_wmac_setup(void)
+@@ -139,6 +139,137 @@ static void qca955x_wmac_setup(void)
                ath79_wmac_data.is_clk_25mhz = true;
  }
  
  #endif /* _ATH79_DEV_WMAC_H */
 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-@@ -102,6 +102,14 @@
- #define AR934X_EHCI_BASE      0x1b000000
- #define AR934X_EHCI_SIZE      0x1000
+@@ -123,6 +123,14 @@
+ #define QCA955X_GMAC_BASE     (AR71XX_APB_BASE + 0x00070000)
+ #define QCA955X_GMAC_SIZE     0x40
  
 +#define AR9300_OTP_BASE               0x14000
 +#define AR9300_OTP_STATUS     0x15f18