1 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
2 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
4 #include <linux/bitops.h>
6 #define AR71XX_APB_BASE 0x18000000
7 +#define AR71XX_GE0_BASE 0x19000000
8 +#define AR71XX_GE0_SIZE 0x10000
9 +#define AR71XX_GE1_BASE 0x1a000000
10 +#define AR71XX_GE1_SIZE 0x10000
11 #define AR71XX_EHCI_BASE 0x1b000000
12 #define AR71XX_EHCI_SIZE 0x1000
13 #define AR71XX_OHCI_BASE 0x1c000000
15 #define AR71XX_PLL_SIZE 0x100
16 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
17 #define AR71XX_RESET_SIZE 0x100
18 +#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
19 +#define AR71XX_MII_SIZE 0x100
21 #define AR71XX_PCI_MEM_BASE 0x10000000
22 #define AR71XX_PCI_MEM_SIZE 0x07000000
25 #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
26 #define AR933X_UART_SIZE 0x14
27 +#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
28 +#define AR933X_GMAC_SIZE 0x04
29 #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
30 #define AR933X_WMAC_SIZE 0x20000
31 #define AR933X_EHCI_BASE 0x1b000000
32 #define AR933X_EHCI_SIZE 0x1000
34 +#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
35 +#define AR934X_GMAC_SIZE 0x14
36 #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
37 #define AR934X_WMAC_SIZE 0x20000
38 #define AR934X_EHCI_BASE 0x1b000000
40 #define QCA955X_EHCI0_BASE 0x1b000000
41 #define QCA955X_EHCI1_BASE 0x1b400000
42 #define QCA955X_EHCI_SIZE 0x1000
43 +#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
44 +#define QCA955X_GMAC_SIZE 0x40
49 #define AR71XX_AHB_DIV_SHIFT 20
50 #define AR71XX_AHB_DIV_MASK 0x7
52 +#define AR71XX_ETH0_PLL_SHIFT 17
53 +#define AR71XX_ETH1_PLL_SHIFT 19
55 #define AR724X_PLL_REG_CPU_CONFIG 0x00
56 #define AR724X_PLL_REG_PCIE_CONFIG 0x18
59 #define AR724X_DDR_DIV_SHIFT 22
60 #define AR724X_DDR_DIV_MASK 0x3
62 +#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
64 #define AR913X_PLL_REG_CPU_CONFIG 0x00
65 #define AR913X_PLL_REG_ETH_CONFIG 0x04
66 #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
68 #define AR913X_AHB_DIV_SHIFT 19
69 #define AR913X_AHB_DIV_MASK 0x1
71 +#define AR913X_ETH0_PLL_SHIFT 20
72 +#define AR913X_ETH1_PLL_SHIFT 22
74 #define AR933X_PLL_CPU_CONFIG_REG 0x00
75 #define AR933X_PLL_CLOCK_CTRL_REG 0x08
78 #define AR934X_PLL_CPU_CONFIG_REG 0x00
79 #define AR934X_PLL_DDR_CONFIG_REG 0x04
80 #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
81 +#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c
83 #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
84 #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
86 #define AR913X_RESET_USB_HOST BIT(5)
87 #define AR913X_RESET_USB_PHY BIT(4)
89 +#define AR933X_RESET_GE1_MDIO BIT(23)
90 +#define AR933X_RESET_GE0_MDIO BIT(22)
91 +#define AR933X_RESET_GE1_MAC BIT(13)
92 #define AR933X_RESET_WMAC BIT(11)
93 +#define AR933X_RESET_GE0_MAC BIT(9)
94 #define AR933X_RESET_USB_HOST BIT(5)
95 #define AR933X_RESET_USB_PHY BIT(4)
96 #define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
98 +#define AR934X_RESET_HOST BIT(31)
99 +#define AR934X_RESET_SLIC BIT(30)
100 +#define AR934X_RESET_HDMA BIT(29)
101 +#define AR934X_RESET_EXTERNAL BIT(28)
102 +#define AR934X_RESET_RTC BIT(27)
103 +#define AR934X_RESET_PCIE_EP_INT BIT(26)
104 +#define AR934X_RESET_CHKSUM_ACC BIT(25)
105 +#define AR934X_RESET_FULL_CHIP BIT(24)
106 +#define AR934X_RESET_GE1_MDIO BIT(23)
107 +#define AR934X_RESET_GE0_MDIO BIT(22)
108 +#define AR934X_RESET_CPU_NMI BIT(21)
109 +#define AR934X_RESET_CPU_COLD BIT(20)
110 +#define AR934X_RESET_HOST_RESET_INT BIT(19)
111 +#define AR934X_RESET_PCIE_EP BIT(18)
112 +#define AR934X_RESET_UART1 BIT(17)
113 +#define AR934X_RESET_DDR BIT(16)
114 +#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
115 +#define AR934X_RESET_NANDF BIT(14)
116 +#define AR934X_RESET_GE1_MAC BIT(13)
117 +#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
118 #define AR934X_RESET_USB_PHY_ANALOG BIT(11)
119 +#define AR934X_RESET_HOST_DMA_INT BIT(10)
120 +#define AR934X_RESET_GE0_MAC BIT(9)
121 +#define AR934X_RESET_ETH_SWITCH BIT(8)
122 +#define AR934X_RESET_PCIE_PHY BIT(7)
123 +#define AR934X_RESET_PCIE BIT(6)
124 #define AR934X_RESET_USB_HOST BIT(5)
125 #define AR934X_RESET_USB_PHY BIT(4)
126 #define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
127 +#define AR934X_RESET_LUT BIT(2)
128 +#define AR934X_RESET_MBOX BIT(1)
129 +#define AR934X_RESET_I2S BIT(0)
131 +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
132 +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
133 #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
135 #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
137 #define AR71XX_GPIO_REG_INT_ENABLE 0x24
138 #define AR71XX_GPIO_REG_FUNC 0x28
140 +#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
141 +#define AR934X_GPIO_REG_OUT_FUNC1 0x30
142 +#define AR934X_GPIO_REG_OUT_FUNC2 0x34
143 +#define AR934X_GPIO_REG_OUT_FUNC3 0x38
144 +#define AR934X_GPIO_REG_OUT_FUNC4 0x3c
145 +#define AR934X_GPIO_REG_OUT_FUNC5 0x40
146 +#define AR934X_GPIO_REG_FUNC 0x6c
148 #define AR71XX_GPIO_COUNT 16
149 #define AR724X_GPIO_COUNT 18
150 #define AR913X_GPIO_COUNT 22
151 @@ -525,4 +588,133 @@
152 #define AR934X_GPIO_COUNT 23
153 #define QCA955X_GPIO_COUNT 24
155 +#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
156 +#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
157 +#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
158 +#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
159 +#define AR71XX_GPIO_FUNC_UART_EN BIT(8)
160 +#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
161 +#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
163 +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
164 +#define AR724X_GPIO_FUNC_SPI_EN BIT(18)
165 +#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
166 +#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
167 +#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
168 +#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
169 +#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
170 +#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
171 +#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
172 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
173 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
174 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
175 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
176 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
177 +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
178 +#define AR724X_GPIO_FUNC_UART_EN BIT(1)
179 +#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
181 +#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22)
182 +#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
183 +#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20)
184 +#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19)
185 +#define AR913X_GPIO_FUNC_I2S1_EN BIT(18)
186 +#define AR913X_GPIO_FUNC_I2S0_EN BIT(17)
187 +#define AR913X_GPIO_FUNC_SLIC_EN BIT(16)
188 +#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
189 +#define AR913X_GPIO_FUNC_UART_EN BIT(8)
190 +#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4)
192 +#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
193 +#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
194 +#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
195 +#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
196 +#define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
197 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
198 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
199 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
200 +#define AR933X_GPIO_FUNC_SPI_EN BIT(18)
201 +#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
202 +#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
203 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
204 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
205 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
206 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
207 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
208 +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
209 +#define AR933X_GPIO_FUNC_UART_EN BIT(1)
210 +#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
212 +#define AR934X_GPIO_FUNC_DDR_DQOE_EN BIT(17)
213 +#define AR934X_GPIO_FUNC_SPI_CS_1_EN BIT(14)
214 +#define AR934X_GPIO_FUNC_SPI_CS_0_EN BIT(13)
216 +#define AR934X_GPIO_OUT_GPIO 0x00
221 +#define AR71XX_MII_REG_MII0_CTRL 0x00
222 +#define AR71XX_MII_REG_MII1_CTRL 0x04
224 +#define AR71XX_MII_CTRL_IF_MASK 3
225 +#define AR71XX_MII_CTRL_SPEED_SHIFT 4
226 +#define AR71XX_MII_CTRL_SPEED_MASK 3
227 +#define AR71XX_MII_CTRL_SPEED_10 0
228 +#define AR71XX_MII_CTRL_SPEED_100 1
229 +#define AR71XX_MII_CTRL_SPEED_1000 2
231 +#define AR71XX_MII0_CTRL_IF_GMII 0
232 +#define AR71XX_MII0_CTRL_IF_MII 1
233 +#define AR71XX_MII0_CTRL_IF_RGMII 2
234 +#define AR71XX_MII0_CTRL_IF_RMII 3
236 +#define AR71XX_MII1_CTRL_IF_RGMII 0
237 +#define AR71XX_MII1_CTRL_IF_RMII 1
240 + * AR933X GMAC interface
242 +#define AR933X_GMAC_REG_ETH_CFG 0x00
244 +#define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
245 +#define AR933X_ETH_CFG_MII_GE0 BIT(1)
246 +#define AR933X_ETH_CFG_GMII_GE0 BIT(2)
247 +#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
248 +#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
249 +#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
250 +#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
251 +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
252 +#define AR933X_ETH_CFG_RMII_GE0 BIT(9)
253 +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
254 +#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
257 + * AR934X GMAC Interface
259 +#define AR934X_GMAC_REG_ETH_CFG 0x00
261 +#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
262 +#define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
263 +#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
264 +#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
265 +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
266 +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
267 +#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
268 +#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
269 +#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
270 +#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
271 +#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
272 +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
273 +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
276 + * QCA955X GMAC Interface
279 +#define QCA955X_GMAC_REG_ETH_CFG 0x00
281 +#define QCA955X_ETH_CFG_RGMII_GMAC0 BIT(0)
282 +#define QCA955X_ETH_CFG_SGMII_GMAC0 BIT(6)
284 #endif /* __ASM_MACH_AR71XX_REGS_H */
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