[omap]: switch to 3.12, enable support for AM33xx/OMAP3
[openwrt/svn-archive/archive.git] / target / linux / omap / patches-3.12 / 001-ti_git.patch
1 --- a/arch/arm/boot/dts/am335x-boneblack.dts
2 +++ b/arch/arm/boot/dts/am335x-boneblack.dts
3 @@ -15,3 +15,80 @@
4 regulator-max-microvolt = <1800000>;
5 regulator-always-on;
6 };
7 +
8 +&mmc1 {
9 + vmmc-supply = <&vmmcsd_fixed>;
10 +};
11 +
12 +&mmc2 {
13 + vmmc-supply = <&vmmcsd_fixed>;
14 + pinctrl-names = "default";
15 + pinctrl-0 = <&emmc_pins>;
16 + bus-width = <8>;
17 + ti,non-removable;
18 + status = "okay";
19 +};
20 +
21 +&am33xx_pinmux {
22 + nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins {
23 + pinctrl-single,pins = <
24 + 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
25 + 0xa0 0x08 /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
26 + 0xa4 0x08 /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
27 + 0xa8 0x08 /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
28 + 0xac 0x08 /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
29 + 0xb0 0x08 /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
30 + 0xb4 0x08 /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
31 + 0xb8 0x08 /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
32 + 0xbc 0x08 /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
33 + 0xc0 0x08 /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
34 + 0xc4 0x08 /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
35 + 0xc8 0x08 /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
36 + 0xcc 0x08 /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
37 + 0xd0 0x08 /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
38 + 0xd4 0x08 /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
39 + 0xd8 0x08 /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
40 + 0xdc 0x08 /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
41 + 0xe0 0x00 /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
42 + 0xe4 0x00 /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
43 + 0xe8 0x00 /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
44 + 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
45 + >;
46 + };
47 + nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins {
48 + pinctrl-single,pins = <
49 + 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
50 + >;
51 + };
52 +};
53 +
54 +&i2c0 {
55 + hdmi1: hdmi@70 {
56 + compatible = "nxp,tda998x";
57 + reg = <0x70>;
58 + };
59 +};
60 +
61 +&lcdc {
62 + pinctrl-names = "default", "off";
63 + pinctrl-0 = <&nxp_hdmi_bonelt_pins>;
64 + pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;
65 + status = "okay";
66 + hdmi = <&hdmi1>;
67 + display-timings {
68 + 640x480P60 {
69 + clock-frequency = <25200000>;
70 + hactive = <640>;
71 + vactive = <480>;
72 + hfront-porch = <16>;
73 + hback-porch = <48>;
74 + hsync-len = <96>;
75 + vback-porch = <31>;
76 + vfront-porch = <11>;
77 + vsync-len = <2>;
78 + hsync-active = <0>;
79 + vsync-active = <0>;
80 + };
81 + };
82 +};
83 +
84 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi
85 +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
86 @@ -107,6 +107,27 @@
87 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
88 >;
89 };
90 +
91 + mmc1_pins: pinmux_mmc1_pins {
92 + pinctrl-single,pins = <
93 + 0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */
94 + >;
95 + };
96 +
97 + emmc_pins: pinmux_emmc_pins {
98 + pinctrl-single,pins = <
99 + 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
100 + 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
101 + 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
102 + 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
103 + 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
104 + 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
105 + 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
106 + 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
107 + 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
108 + 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
109 + >;
110 + };
111 };
112
113 ocp {
114 @@ -183,15 +204,24 @@
115 led@4 {
116 label = "beaglebone:green:usr2";
117 gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
118 + linux,default-trigger = "cpu0";
119 default-state = "off";
120 };
121
122 led@5 {
123 label = "beaglebone:green:usr3";
124 gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
125 + linux,default-trigger = "mmc1";
126 default-state = "off";
127 };
128 };
129 +
130 + vmmcsd_fixed: fixedregulator@0 {
131 + compatible = "regulator-fixed";
132 + regulator-name = "vmmcsd_fixed";
133 + regulator-min-microvolt = <3300000>;
134 + regulator-max-microvolt = <3300000>;
135 + };
136 };
137
138 /include/ "tps65217.dtsi"
139 @@ -260,3 +290,12 @@
140 pinctrl-0 = <&davinci_mdio_default>;
141 pinctrl-1 = <&davinci_mdio_sleep>;
142 };
143 +
144 +&mmc1 {
145 + status = "okay";
146 + bus-width = <0x4>;
147 + pinctrl-names = "default";
148 + pinctrl-0 = <&mmc1_pins>;
149 + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
150 + cd-inverted;
151 +};
152 --- a/arch/arm/boot/dts/am335x-bone.dts
153 +++ b/arch/arm/boot/dts/am335x-bone.dts
154 @@ -9,3 +9,13 @@
155
156 #include "am33xx.dtsi"
157 #include "am335x-bone-common.dtsi"
158 +
159 +&ldo3_reg {
160 + regulator-min-microvolt = <1800000>;
161 + regulator-max-microvolt = <3300000>;
162 + regulator-always-on;
163 +};
164 +
165 +&mmc1 {
166 + vmmc-supply = <&ldo3_reg>;
167 +};
168 --- a/arch/arm/boot/dts/am335x-evm.dts
169 +++ b/arch/arm/boot/dts/am335x-evm.dts
170 @@ -149,6 +149,54 @@
171 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
172 >;
173 };
174 +
175 + mmc1_pins: pinmux_mmc1_pins {
176 + pinctrl-single,pins = <
177 + 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
178 + >;
179 + };
180 +
181 + lcd_pins_s0: lcd_pins_s0 {
182 + pinctrl-single,pins = <
183 + 0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */
184 + 0x24 0x01 /* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */
185 + 0x28 0x01 /* gpmc_ad10.lcd_data18, OUTPUT | MODE1 */
186 + 0x2c 0x01 /* gpmc_ad11.lcd_data19, OUTPUT | MODE1 */
187 + 0x30 0x01 /* gpmc_ad12.lcd_data20, OUTPUT | MODE1 */
188 + 0x34 0x01 /* gpmc_ad13.lcd_data21, OUTPUT | MODE1 */
189 + 0x38 0x01 /* gpmc_ad14.lcd_data22, OUTPUT | MODE1 */
190 + 0x3c 0x01 /* gpmc_ad15.lcd_data23, OUTPUT | MODE1 */
191 + 0xa0 0x00 /* lcd_data0.lcd_data0, OUTPUT | MODE0 */
192 + 0xa4 0x00 /* lcd_data1.lcd_data1, OUTPUT | MODE0 */
193 + 0xa8 0x00 /* lcd_data2.lcd_data2, OUTPUT | MODE0 */
194 + 0xac 0x00 /* lcd_data3.lcd_data3, OUTPUT | MODE0 */
195 + 0xb0 0x00 /* lcd_data4.lcd_data4, OUTPUT | MODE0 */
196 + 0xb4 0x00 /* lcd_data5.lcd_data5, OUTPUT | MODE0 */
197 + 0xb8 0x00 /* lcd_data6.lcd_data6, OUTPUT | MODE0 */
198 + 0xbc 0x00 /* lcd_data7.lcd_data7, OUTPUT | MODE0 */
199 + 0xc0 0x00 /* lcd_data8.lcd_data8, OUTPUT | MODE0 */
200 + 0xc4 0x00 /* lcd_data9.lcd_data9, OUTPUT | MODE0 */
201 + 0xc8 0x00 /* lcd_data10.lcd_data10, OUTPUT | MODE0 */
202 + 0xcc 0x00 /* lcd_data11.lcd_data11, OUTPUT | MODE0 */
203 + 0xd0 0x00 /* lcd_data12.lcd_data12, OUTPUT | MODE0 */
204 + 0xd4 0x00 /* lcd_data13.lcd_data13, OUTPUT | MODE0 */
205 + 0xd8 0x00 /* lcd_data14.lcd_data14, OUTPUT | MODE0 */
206 + 0xdc 0x00 /* lcd_data15.lcd_data15, OUTPUT | MODE0 */
207 + 0xe0 0x00 /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */
208 + 0xe4 0x00 /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */
209 + 0xe8 0x00 /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */
210 + 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */
211 + >;
212 + };
213 +
214 + am335x_evm_audio_pins: am335x_evm_audio_pins {
215 + pinctrl-single,pins = <
216 + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rx_dv.mcasp1_aclkx */
217 + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_txd3.mcasp1_fsx */
218 + 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
219 + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
220 + >;
221 + };
222 };
223
224 ocp {
225 @@ -244,6 +292,18 @@
226 compatible = "ti,tmp275";
227 reg = <0x48>;
228 };
229 +
230 + tlv320aic3106: tlv320aic3106@1b {
231 + compatible = "ti,tlv320aic3106";
232 + reg = <0x1b>;
233 + status = "okay";
234 +
235 + /* Regulators */
236 + AVDD-supply = <&vaux2_reg>;
237 + IOVDD-supply = <&vaux2_reg>;
238 + DRVDD-supply = <&vaux2_reg>;
239 + DVDD-supply = <&vbat>;
240 + };
241 };
242
243 elm: elm@48080000 {
244 @@ -268,8 +328,7 @@
245 nand@0,0 {
246 reg = <0 0 0>; /* CS0, offset 0 */
247 nand-bus-width = <8>;
248 - ti,nand-ecc-opt = "bch8";
249 - gpmc,device-nand = "true";
250 + ti,nand-ecc-opt= "bch8";
251 gpmc,device-width = <1>;
252 gpmc,sync-clk-ps = <0>;
253 gpmc,cs-on-ns = <0>;
254 @@ -293,53 +352,78 @@
255 gpmc,wait-monitoring-ns = <0>;
256 gpmc,wr-access-ns = <40>;
257 gpmc,wr-data-mux-bus-ns = <0>;
258 -
259 #address-cells = <1>;
260 #size-cells = <1>;
261 - elm_id = <&elm>;
262 -
263 + ti,elm-id = <&elm>;
264 /* MTD partition table */
265 partition@0 {
266 label = "SPL1";
267 reg = <0x00000000 0x000020000>;
268 };
269 -
270 partition@1 {
271 label = "SPL2";
272 reg = <0x00020000 0x00020000>;
273 };
274 -
275 partition@2 {
276 label = "SPL3";
277 reg = <0x00040000 0x00020000>;
278 };
279 -
280 partition@3 {
281 label = "SPL4";
282 reg = <0x00060000 0x00020000>;
283 };
284 -
285 partition@4 {
286 label = "U-boot";
287 reg = <0x00080000 0x001e0000>;
288 };
289 -
290 partition@5 {
291 label = "environment";
292 reg = <0x00260000 0x00020000>;
293 };
294 -
295 partition@6 {
296 label = "Kernel";
297 reg = <0x00280000 0x00500000>;
298 };
299 -
300 partition@7 {
301 label = "File-System";
302 reg = <0x00780000 0x0F880000>;
303 };
304 };
305 };
306 +
307 + lcdc: lcdc@0x4830e000 {
308 + pinctrl-names = "default";
309 + pinctrl-0 = <&lcd_pins_s0>;
310 + status = "okay";
311 + display-timings {
312 + 800x480p62 {
313 + clock-frequency = <30000000>;
314 + hactive = <800>;
315 + vactive = <480>;
316 + hfront-porch = <39>;
317 + hback-porch = <39>;
318 + hsync-len = <47>;
319 + vback-porch = <29>;
320 + vfront-porch = <13>;
321 + vsync-len = <2>;
322 + hsync-active = <1>;
323 + vsync-active = <1>;
324 + };
325 + };
326 + };
327 +
328 + sound {
329 + compatible = "ti,da830-evm-audio";
330 + ti,model = "AM335x-EVM";
331 + ti,audio-codec = <&tlv320aic3106>;
332 + ti,mcasp-controller = <&mcasp1>;
333 + ti,codec-clock-rate = <12000000>;
334 + ti,audio-routing =
335 + "Headphone Jack", "HPLOUT",
336 + "Headphone Jack", "HPROUT",
337 + "LINE1L", "Line In",
338 + "LINE1R", "Line In";
339 + };
340 };
341
342 vbat: fixedregulator@0 {
343 @@ -403,10 +487,63 @@
344 brightness-levels = <0 51 53 56 62 75 101 152 255>;
345 default-brightness-level = <8>;
346 };
347 +
348 + panel {
349 + compatible = "ti,tilcdc,panel";
350 + status = "okay";
351 + pinctrl-names = "default";
352 + pinctrl-0 = <&lcd_pins_s0>;
353 + panel-info {
354 + ac-bias = <255>;
355 + ac-bias-intrpt = <0>;
356 + dma-burst-sz = <16>;
357 + bpp = <32>;
358 + fdd = <0x80>;
359 + sync-edge = <0>;
360 + sync-ctrl = <1>;
361 + raster-order = <0>;
362 + fifo-th = <0>;
363 + };
364 +
365 + display-timings {
366 + 800x480p62 {
367 + clock-frequency = <30000000>;
368 + hactive = <800>;
369 + vactive = <480>;
370 + hfront-porch = <39>;
371 + hback-porch = <39>;
372 + hsync-len = <47>;
373 + vback-porch = <29>;
374 + vfront-porch = <13>;
375 + vsync-len = <2>;
376 + hsync-active = <1>;
377 + vsync-active = <1>;
378 + };
379 + };
380 + };
381 };
382
383 #include "tps65910.dtsi"
384
385 +&mcasp1 {
386 + pinctrl-names = "default";
387 + pinctrl-0 = <&am335x_evm_audio_pins>;
388 +
389 + status = "okay";
390 +
391 + op-mode = <0>; /* MCASP_IIS_MODE */
392 + tdm-slots = <2>;
393 + /* 16 serializer */
394 + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
395 + 0 0 1 2
396 + 0 0 0 0
397 + 0 0 0 0
398 + 0 0 0 0
399 + >;
400 + tx-num-evt = <1>;
401 + rx-num-evt = <1>;
402 +};
403 +
404 &tps {
405 vcc1-supply = <&vbat>;
406 vcc2-supply = <&vbat>;
407 @@ -477,6 +614,8 @@
408 };
409
410 vmmc_reg: regulator@12 {
411 + regulator-min-microvolt = <1800000>;
412 + regulator-max-microvolt = <3300000>;
413 regulator-always-on;
414 };
415 };
416 @@ -509,7 +648,7 @@
417 tsc {
418 ti,wires = <4>;
419 ti,x-plate-resistance = <200>;
420 - ti,coordiante-readouts = <5>;
421 + ti,coordinate-readouts = <5>;
422 ti,wire-config = <0x00 0x11 0x22 0x33>;
423 };
424
425 @@ -517,3 +656,12 @@
426 ti,adc-channels = <4 5 6 7>;
427 };
428 };
429 +
430 +&mmc1 {
431 + status = "okay";
432 + vmmc-supply = <&vmmc_reg>;
433 + bus-width = <4>;
434 + pinctrl-names = "default";
435 + pinctrl-0 = <&mmc1_pins>;
436 + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
437 +};
438 --- /dev/null
439 +++ b/arch/arm/boot/dts/am335x-evm-profile2.dts
440 @@ -0,0 +1,296 @@
441 +/*
442 + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
443 + *
444 + * This program is free software; you can redistribute it and/or modify
445 + * it under the terms of the GNU General Public License version 2 as
446 + * published by the Free Software Foundation.
447 + */
448 +/dts-v1/;
449 +
450 +#include "am33xx.dtsi"
451 +
452 +/ {
453 + model = "TI AM335x EVM";
454 + compatible = "ti,am335x-evm", "ti,am33xx";
455 +
456 + cpus {
457 + cpu@0 {
458 + cpu0-supply = <&vdd1_reg>;
459 + };
460 + };
461 +
462 + memory {
463 + device_type = "memory";
464 + reg = <0x80000000 0x10000000>; /* 256 MB */
465 + };
466 +
467 + am33xx_pinmux: pinmux@44e10800 {
468 + pinctrl-names = "default";
469 + pinctrl-0 = <&matrix_keypad_s0 &clkout2_pin>;
470 +
471 + matrix_keypad_s0: matrix_keypad_s0 {
472 + pinctrl-single,pins = <
473 + 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
474 + 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
475 + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
476 + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
477 + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
478 + >;
479 + };
480 +
481 + i2c0_pins: pinmux_i2c0_pins {
482 + pinctrl-single,pins = <
483 + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
484 + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
485 + >;
486 + };
487 +
488 + spi0_pins: pinmux_spi0_pins {
489 + pinctrl-single,pins = <
490 + 0x150 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_clk.spi0_clk */
491 + 0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */
492 + 0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
493 + 0x15c (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
494 + >;
495 + };
496 +
497 + uart0_pins: pinmux_uart0_pins {
498 + pinctrl-single,pins = <
499 + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
500 + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
501 + >;
502 + };
503 +
504 + clkout2_pin: pinmux_clkout2_pin {
505 + pinctrl-single,pins = <
506 + 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
507 + >;
508 + };
509 +
510 + cpsw_default: cpsw_default {
511 + pinctrl-single,pins = <
512 + /* Slave 1 */
513 + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
514 + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
515 + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
516 + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
517 + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
518 + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
519 + 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
520 + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
521 + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
522 + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
523 + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
524 + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
525 + >;
526 + };
527 +
528 + cpsw_sleep: cpsw_sleep {
529 + pinctrl-single,pins = <
530 + /* Slave 1 reset value */
531 + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
532 + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
533 + 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
534 + 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
535 + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
536 + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
537 + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
538 + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
539 + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
540 + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
541 + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
542 + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
543 + >;
544 + };
545 +
546 + davinci_mdio_default: davinci_mdio_default {
547 + pinctrl-single,pins = <
548 + /* MDIO */
549 + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
550 + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
551 + >;
552 + };
553 +
554 + davinci_mdio_sleep: davinci_mdio_sleep {
555 + pinctrl-single,pins = <
556 + /* MDIO reset value */
557 + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
558 + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
559 + >;
560 + };
561 + };
562 +
563 + ocp {
564 + uart0: serial@44e09000 {
565 + pinctrl-names = "default";
566 + pinctrl-0 = <&uart0_pins>;
567 +
568 + status = "okay";
569 + };
570 +
571 + i2c0: i2c@44e0b000 {
572 + pinctrl-names = "default";
573 + pinctrl-0 = <&i2c0_pins>;
574 +
575 + status = "okay";
576 + clock-frequency = <400000>;
577 +
578 + tps: tps@2d {
579 + reg = <0x2d>;
580 + };
581 + };
582 +
583 + spi0: spi@48030000 {
584 + pinctrl-names = "default";
585 + pinctrl-0 = <&spi0_pins>;
586 +
587 + status = "okay";
588 + m25p80@0 {
589 + compatible = "w25q64";
590 + spi-max-frequency = <24000000>;
591 + reg = <0x0>;
592 + };
593 + };
594 + };
595 +
596 + vbat: fixedregulator@0 {
597 + compatible = "regulator-fixed";
598 + regulator-name = "vbat";
599 + regulator-min-microvolt = <5000000>;
600 + regulator-max-microvolt = <5000000>;
601 + regulator-boot-on;
602 + };
603 +
604 + lis3_reg: fixedregulator@1 {
605 + compatible = "regulator-fixed";
606 + regulator-name = "lis3_reg";
607 + regulator-boot-on;
608 + };
609 +
610 + matrix_keypad: matrix_keypad@0 {
611 + compatible = "gpio-matrix-keypad";
612 + debounce-delay-ms = <5>;
613 + col-scan-delay-us = <2>;
614 +
615 + row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */
616 + &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */
617 + &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */
618 +
619 + col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */
620 + &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */
621 +
622 + linux,keymap = <0x0000008b /* MENU */
623 + 0x0100009e /* BACK */
624 + 0x02000069 /* LEFT */
625 + 0x0001006a /* RIGHT */
626 + 0x0101001c /* ENTER */
627 + 0x0201006c>; /* DOWN */
628 + };
629 +};
630 +
631 +#include "tps65910.dtsi"
632 +
633 +&tps {
634 + vcc1-supply = <&vbat>;
635 + vcc2-supply = <&vbat>;
636 + vcc3-supply = <&vbat>;
637 + vcc4-supply = <&vbat>;
638 + vcc5-supply = <&vbat>;
639 + vcc6-supply = <&vbat>;
640 + vcc7-supply = <&vbat>;
641 + vccio-supply = <&vbat>;
642 +
643 + regulators {
644 + vrtc_reg: regulator@0 {
645 + regulator-always-on;
646 + };
647 +
648 + vio_reg: regulator@1 {
649 + regulator-always-on;
650 + };
651 +
652 + vdd1_reg: regulator@2 {
653 + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
654 + regulator-name = "vdd_mpu";
655 + regulator-min-microvolt = <912500>;
656 + regulator-max-microvolt = <1312500>;
657 + regulator-boot-on;
658 + regulator-always-on;
659 + };
660 +
661 + vdd2_reg: regulator@3 {
662 + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
663 + regulator-name = "vdd_core";
664 + regulator-min-microvolt = <912500>;
665 + regulator-max-microvolt = <1150000>;
666 + regulator-boot-on;
667 + regulator-always-on;
668 + };
669 +
670 + vdd3_reg: regulator@4 {
671 + regulator-always-on;
672 + };
673 +
674 + vdig1_reg: regulator@5 {
675 + regulator-always-on;
676 + };
677 +
678 + vdig2_reg: regulator@6 {
679 + regulator-always-on;
680 + };
681 +
682 + vpll_reg: regulator@7 {
683 + regulator-always-on;
684 + };
685 +
686 + vdac_reg: regulator@8 {
687 + regulator-always-on;
688 + };
689 +
690 + vaux1_reg: regulator@9 {
691 + regulator-always-on;
692 + };
693 +
694 + vaux2_reg: regulator@10 {
695 + regulator-always-on;
696 + };
697 +
698 + vaux33_reg: regulator@11 {
699 + regulator-always-on;
700 + };
701 +
702 + vmmc_reg: regulator@12 {
703 + regulator-min-microvolt = <1800000>;
704 + regulator-max-microvolt = <3300000>;
705 + regulator-always-on;
706 + };
707 + };
708 +};
709 +
710 +&mac {
711 + pinctrl-names = "default", "sleep";
712 + pinctrl-0 = <&cpsw_default>;
713 + pinctrl-1 = <&cpsw_sleep>;
714 +};
715 +
716 +&davinci_mdio {
717 + pinctrl-names = "default", "sleep";
718 + pinctrl-0 = <&davinci_mdio_default>;
719 + pinctrl-1 = <&davinci_mdio_sleep>;
720 +};
721 +
722 +&cpsw_emac0 {
723 + phy_id = <&davinci_mdio>, <0>;
724 + phy-mode = "rgmii-txid";
725 +};
726 +
727 +&cpsw_emac1 {
728 + phy_id = <&davinci_mdio>, <1>;
729 + phy-mode = "rgmii-txid";
730 +};
731 +
732 +&mmc1 {
733 + status = "okay";
734 + vmmc-supply = <&vmmc_reg>;
735 + bus-width = <4>;
736 +};
737 --- a/arch/arm/boot/dts/am335x-evmsk.dts
738 +++ b/arch/arm/boot/dts/am335x-evmsk.dts
739 @@ -35,6 +35,39 @@
740 pinctrl-names = "default";
741 pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
742
743 + lcd_pins_s0: lcd_pins_s0 {
744 + pinctrl-single,pins = <
745 + 0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */
746 + 0x24 0x01 /* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */
747 + 0x28 0x01 /* gpmc_ad10.lcd_data18, OUTPUT | MODE1 */
748 + 0x2c 0x01 /* gpmc_ad11.lcd_data19, OUTPUT | MODE1 */
749 + 0x30 0x01 /* gpmc_ad12.lcd_data20, OUTPUT | MODE1 */
750 + 0x34 0x01 /* gpmc_ad13.lcd_data21, OUTPUT | MODE1 */
751 + 0x38 0x01 /* gpmc_ad14.lcd_data22, OUTPUT | MODE1 */
752 + 0x3c 0x01 /* gpmc_ad15.lcd_data23, OUTPUT | MODE1 */
753 + 0xa0 0x00 /* lcd_data0.lcd_data0, OUTPUT | MODE0 */
754 + 0xa4 0x00 /* lcd_data1.lcd_data1, OUTPUT | MODE0 */
755 + 0xa8 0x00 /* lcd_data2.lcd_data2, OUTPUT | MODE0 */
756 + 0xac 0x00 /* lcd_data3.lcd_data3, OUTPUT | MODE0 */
757 + 0xb0 0x00 /* lcd_data4.lcd_data4, OUTPUT | MODE0 */
758 + 0xb4 0x00 /* lcd_data5.lcd_data5, OUTPUT | MODE0 */
759 + 0xb8 0x00 /* lcd_data6.lcd_data6, OUTPUT | MODE0 */
760 + 0xbc 0x00 /* lcd_data7.lcd_data7, OUTPUT | MODE0 */
761 + 0xc0 0x00 /* lcd_data8.lcd_data8, OUTPUT | MODE0 */
762 + 0xc4 0x00 /* lcd_data9.lcd_data9, OUTPUT | MODE0 */
763 + 0xc8 0x00 /* lcd_data10.lcd_data10, OUTPUT | MODE0 */
764 + 0xcc 0x00 /* lcd_data11.lcd_data11, OUTPUT | MODE0 */
765 + 0xd0 0x00 /* lcd_data12.lcd_data12, OUTPUT | MODE0 */
766 + 0xd4 0x00 /* lcd_data13.lcd_data13, OUTPUT | MODE0 */
767 + 0xd8 0x00 /* lcd_data14.lcd_data14, OUTPUT | MODE0 */
768 + 0xdc 0x00 /* lcd_data15.lcd_data15, OUTPUT | MODE0 */
769 + 0xe0 0x00 /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */
770 + 0xe4 0x00 /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */
771 + 0xe8 0x00 /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */
772 + 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */
773 + >;
774 + };
775 +
776 user_leds_s0: user_leds_s0 {
777 pinctrl-single,pins = <
778 0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
779 @@ -158,6 +191,21 @@
780 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
781 >;
782 };
783 +
784 + mmc1_pins: pinmux_mmc1_pins {
785 + pinctrl-single,pins = <
786 + 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
787 + >;
788 + };
789 +
790 + mcasp1_pins: mcasp1_pins {
791 + pinctrl-single,pins = <
792 + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
793 + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
794 + 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
795 + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
796 + >;
797 + };
798 };
799
800 ocp {
801 @@ -206,6 +254,18 @@
802 st,max-limit-y = <550>;
803 st,max-limit-z = <750>;
804 };
805 +
806 + tlv320aic3106: tlv320aic3106@1b {
807 + compatible = "ti,tlv320aic3106";
808 + reg = <0x1b>;
809 + status = "okay";
810 +
811 + /* Regulators */
812 + AVDD-supply = <&vaux2_reg>;
813 + IOVDD-supply = <&vaux2_reg>;
814 + DRVDD-supply = <&vaux2_reg>;
815 + DVDD-supply = <&vbat>;
816 + };
817 };
818
819 musb: usb@47400000 {
820 @@ -219,9 +279,22 @@
821 status = "okay";
822 };
823
824 + usb-phy@47401b00 {
825 + status = "okay";
826 + };
827 +
828 usb@47401000 {
829 status = "okay";
830 };
831 +
832 + usb@47401800 {
833 + status = "okay";
834 + dr_mode = "host";
835 + };
836 +
837 + dma-controller@07402000 {
838 + status = "okay";
839 + };
840 };
841
842 epwmss2: epwmss@48304000 {
843 @@ -233,6 +306,38 @@
844 pinctrl-0 = <&ecap2_pins>;
845 };
846 };
847 +
848 + lcdc: lcdc@0x4830e000 {
849 + pinctrl-names = "default";
850 + pinctrl-0 = <&lcd_pins_s0>;
851 + status = "okay";
852 + display-timings {
853 + 480x272 {
854 + hactive = <480>;
855 + vactive = <272>;
856 + hback-porch = <43>;
857 + hfront-porch = <8>;
858 + hsync-len = <4>;
859 + vback-porch = <12>;
860 + vfront-porch = <4>;
861 + vsync-len = <10>;
862 + clock-frequency = <9000000>;
863 + hsync-active = <0>;
864 + vsync-active = <0>;
865 + };
866 + };
867 + };
868 +
869 + sound {
870 + compatible = "ti,da830-evm-audio";
871 + ti,model = "AM335x-EVMSK";
872 + ti,audio-codec = <&tlv320aic3106>;
873 + ti,mcasp-controller = <&mcasp1>;
874 + ti,codec-clock-rate = <24576000>;
875 + ti,audio-routing =
876 + "Headphone Jack", "HPLOUT",
877 + "Headphone Jack", "HPROUT";
878 + };
879 };
880
881 vbat: fixedregulator@0 {
882 @@ -393,6 +498,8 @@
883 };
884
885 vmmc_reg: regulator@12 {
886 + regulator-min-microvolt = <1800000>;
887 + regulator-max-microvolt = <3300000>;
888 regulator-always-on;
889 };
890 };
891 @@ -419,3 +526,45 @@
892 phy_id = <&davinci_mdio>, <1>;
893 phy-mode = "rgmii-txid";
894 };
895 +
896 +&tscadc {
897 + status = "okay";
898 + tsc {
899 + ti,wires = <4>;
900 + ti,x-plate-resistance = <200>;
901 + ti,coordinate-readouts = <5>;
902 + ti,wire-config = <0x00 0x11 0x22 0x33>;
903 + };
904 +};
905 +
906 +&gpio0 {
907 + ti,no-reset;
908 +};
909 +
910 +&mmc1 {
911 + status = "okay";
912 + vmmc-supply = <&vmmc_reg>;
913 + bus-width = <4>;
914 + pinctrl-names = "default";
915 + pinctrl-0 = <&mmc1_pins>;
916 + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
917 +};
918 +
919 +&mcasp1 {
920 + pinctrl-names = "default";
921 + pinctrl-0 = <&mcasp1_pins>;
922 +
923 + status = "okay";
924 +
925 + op-mode = <0>; /* MCASP_IIS_MODE */
926 + tdm-slots = <2>;
927 + /* 16 serializer */
928 + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
929 + 0 0 1 2
930 + 0 0 0 0
931 + 0 0 0 0
932 + 0 0 0 0
933 + >;
934 + tx-num-evt = <1>;
935 + rx-num-evt = <1>;
936 +};
937 --- /dev/null
938 +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
939 @@ -0,0 +1,661 @@
940 +/*
941 + * Device Tree Source for AM33xx clock data
942 + *
943 + * Copyright (C) 2013 Texas Instruments, Inc.
944 + *
945 + * This program is free software; you can redistribute it and/or modify
946 + * it under the terms of the GNU General Public License version 2 as
947 + * published by the Free Software Foundation.
948 + */
949 +
950 +clk_32768_ck: clk_32768_ck {
951 + #clock-cells = <0>;
952 + compatible = "fixed-clock";
953 + clock-frequency = <32768>;
954 +};
955 +
956 +clk_rc32k_ck: clk_rc32k_ck {
957 + #clock-cells = <0>;
958 + compatible = "fixed-clock";
959 + clock-frequency = <32000>;
960 +};
961 +
962 +virt_19200000_ck: virt_19200000_ck {
963 + #clock-cells = <0>;
964 + compatible = "fixed-clock";
965 + clock-frequency = <19200000>;
966 +};
967 +
968 +virt_24000000_ck: virt_24000000_ck {
969 + #clock-cells = <0>;
970 + compatible = "fixed-clock";
971 + clock-frequency = <24000000>;
972 +};
973 +
974 +virt_25000000_ck: virt_25000000_ck {
975 + #clock-cells = <0>;
976 + compatible = "fixed-clock";
977 + clock-frequency = <25000000>;
978 +};
979 +
980 +virt_26000000_ck: virt_26000000_ck {
981 + #clock-cells = <0>;
982 + compatible = "fixed-clock";
983 + clock-frequency = <26000000>;
984 +};
985 +
986 +sys_clkin_ck: sys_clkin_ck@44e10040 {
987 + #clock-cells = <0>;
988 + compatible = "mux-clock";
989 + clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
990 + bit-shift = <22>;
991 + reg = <0x44e10040 0x4>;
992 + bit-mask = <0x3>;
993 +};
994 +
995 +tclkin_ck: tclkin_ck {
996 + #clock-cells = <0>;
997 + compatible = "fixed-clock";
998 + clock-frequency = <12000000>;
999 +};
1000 +
1001 +dpll_core_ck: dpll_core_ck@44e00490 {
1002 + #clock-cells = <0>;
1003 + compatible = "ti,omap4-dpll-core-clock";
1004 + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
1005 + reg = <0x44e00490 0x4>, <0x44e0045c 0x4>, <0x44e00468 0x4>;
1006 + reg-names = "control", "idlest", "mult-div1";
1007 +};
1008 +
1009 +dpll_core_x2_ck: dpll_core_x2_ck {
1010 + #clock-cells = <0>;
1011 + compatible = "ti,omap4-dpll-x2-clock";
1012 + clocks = <&dpll_core_ck>;
1013 +};
1014 +
1015 +dpll_core_m4_ck: dpll_core_m4_ck@44e00480 {
1016 + #clock-cells = <0>;
1017 + compatible = "divider-clock";
1018 + clocks = <&dpll_core_x2_ck>;
1019 + reg = <0x44e00480 0x4>;
1020 + bit-mask = <0x1f>;
1021 + index-starts-at-one;
1022 +};
1023 +
1024 +dpll_core_m5_ck: dpll_core_m5_ck@44e00484 {
1025 + #clock-cells = <0>;
1026 + compatible = "divider-clock";
1027 + clocks = <&dpll_core_x2_ck>;
1028 + reg = <0x44e00484 0x4>;
1029 + bit-mask = <0x1f>;
1030 + index-starts-at-one;
1031 +};
1032 +
1033 +dpll_core_m6_ck: dpll_core_m6_ck@44e004d8 {
1034 + #clock-cells = <0>;
1035 + compatible = "divider-clock";
1036 + clocks = <&dpll_core_x2_ck>;
1037 + reg = <0x44e004d8 0x4>;
1038 + bit-mask = <0x1f>;
1039 + index-starts-at-one;
1040 +};
1041 +
1042 +dpll_mpu_ck: dpll_mpu_ck@44e00488 {
1043 + #clock-cells = <0>;
1044 + compatible = "ti,omap4-dpll-clock";
1045 + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
1046 + reg = <0x44e00488 0x4>, <0x44e00420 0x4>, <0x44e0042c 0x4>;
1047 + reg-names = "control", "idlest", "mult-div1";
1048 +};
1049 +
1050 +dpll_mpu_m2_ck: dpll_mpu_m2_ck@44e004a8 {
1051 + #clock-cells = <0>;
1052 + compatible = "divider-clock";
1053 + clocks = <&dpll_mpu_ck>;
1054 + reg = <0x44e004a8 0x4>;
1055 + bit-mask = <0x1f>;
1056 + index-starts-at-one;
1057 +};
1058 +
1059 +dpll_ddr_ck: dpll_ddr_ck@44e00494 {
1060 + #clock-cells = <0>;
1061 + compatible = "ti,omap4-dpll-no-gate-clock";
1062 + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
1063 + reg = <0x44e00494 0x4>, <0x44e00434 0x4>, <0x44e00440 0x4>;
1064 + reg-names = "control", "idlest", "mult-div1";
1065 +};
1066 +
1067 +dpll_ddr_m2_ck: dpll_ddr_m2_ck@44e004a0 {
1068 + #clock-cells = <0>;
1069 + compatible = "divider-clock";
1070 + clocks = <&dpll_ddr_ck>;
1071 + reg = <0x44e004a0 0x4>;
1072 + bit-mask = <0x1f>;
1073 + index-starts-at-one;
1074 +};
1075 +
1076 +dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
1077 + #clock-cells = <0>;
1078 + compatible = "fixed-factor-clock";
1079 + clocks = <&dpll_ddr_m2_ck>;
1080 + clock-mult = <1>;
1081 + clock-div = <2>;
1082 +};
1083 +
1084 +dpll_disp_ck: dpll_disp_ck@44e00498 {
1085 + #clock-cells = <0>;
1086 + compatible = "ti,omap4-dpll-no-gate-clock";
1087 + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
1088 + reg = <0x44e00498 0x4>, <0x44e00448 0x4>, <0x44e00454 0x4>;
1089 + reg-names = "control", "idlest", "mult-div1";
1090 +};
1091 +
1092 +dpll_disp_m2_ck: dpll_disp_m2_ck@44e004a4 {
1093 + #clock-cells = <0>;
1094 + compatible = "divider-clock";
1095 + clocks = <&dpll_disp_ck>;
1096 + reg = <0x44e004a4 0x4>;
1097 + bit-mask = <0x1f>;
1098 + index-starts-at-one;
1099 + set-rate-parent;
1100 +};
1101 +
1102 +dpll_per_ck: dpll_per_ck@44e0048c {
1103 + #clock-cells = <0>;
1104 + compatible = "ti,omap4-dpll-no-gate-j-type-clock";
1105 + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
1106 + reg = <0x44e0048c 0x4>, <0x44e00470 0x4>, <0x44e0049c 0x4>;
1107 + reg-names = "control", "idlest", "mult-div1";
1108 +};
1109 +
1110 +dpll_per_m2_ck: dpll_per_m2_ck@44e004ac {
1111 + #clock-cells = <0>;
1112 + compatible = "divider-clock";
1113 + clocks = <&dpll_per_ck>;
1114 + reg = <0x44e004ac 0x4>;
1115 + bit-mask = <0x1f>;
1116 + index-starts-at-one;
1117 +};
1118 +
1119 +dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
1120 + #clock-cells = <0>;
1121 + compatible = "fixed-factor-clock";
1122 + clocks = <&dpll_per_m2_ck>;
1123 + clock-mult = <1>;
1124 + clock-div = <4>;
1125 +};
1126 +
1127 +dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
1128 + #clock-cells = <0>;
1129 + compatible = "fixed-factor-clock";
1130 + clocks = <&dpll_per_m2_ck>;
1131 + clock-mult = <1>;
1132 + clock-div = <4>;
1133 +};
1134 +
1135 +adc_tsc_fck: adc_tsc_fck {
1136 + #clock-cells = <0>;
1137 + compatible = "fixed-factor-clock";
1138 + clocks = <&sys_clkin_ck>;
1139 + clock-mult = <1>;
1140 + clock-div = <1>;
1141 +};
1142 +
1143 +cefuse_fck: cefuse_fck@44e00a20 {
1144 + #clock-cells = <0>;
1145 + compatible = "gate-clock";
1146 + clocks = <&sys_clkin_ck>;
1147 + bit-shift = <1>;
1148 + reg = <0x44e00a20 0x4>;
1149 +};
1150 +
1151 +clk_24mhz: clk_24mhz {
1152 + #clock-cells = <0>;
1153 + compatible = "fixed-factor-clock";
1154 + clocks = <&dpll_per_m2_ck>;
1155 + clock-mult = <1>;
1156 + clock-div = <8>;
1157 +};
1158 +
1159 +clkdiv32k_ck: clkdiv32k_ck {
1160 + #clock-cells = <0>;
1161 + compatible = "fixed-factor-clock";
1162 + clocks = <&clk_24mhz>;
1163 + clock-mult = <1>;
1164 + clock-div = <732>;
1165 +};
1166 +
1167 +clkdiv32k_ick: clkdiv32k_ick@44e0014c {
1168 + #clock-cells = <0>;
1169 + compatible = "ti,gate-clock";
1170 + clocks = <&clkdiv32k_ck>;
1171 + reg = <0x44e0014c 0x4>;
1172 + bit-shift = <1>;
1173 +};
1174 +
1175 +dcan0_fck: dcan0_fck {
1176 + #clock-cells = <0>;
1177 + compatible = "fixed-factor-clock";
1178 + clocks = <&sys_clkin_ck>;
1179 + clock-mult = <1>;
1180 + clock-div = <1>;
1181 +};
1182 +
1183 +dcan1_fck: dcan1_fck {
1184 + #clock-cells = <0>;
1185 + compatible = "fixed-factor-clock";
1186 + clocks = <&sys_clkin_ck>;
1187 + clock-mult = <1>;
1188 + clock-div = <1>;
1189 +};
1190 +
1191 +l3_gclk: l3_gclk {
1192 + #clock-cells = <0>;
1193 + compatible = "fixed-factor-clock";
1194 + clocks = <&dpll_core_m4_ck>;
1195 + clock-mult = <1>;
1196 + clock-div = <1>;
1197 +};
1198 +
1199 +pruss_ocp_gclk: pruss_ocp_gclk@44e00530 {
1200 + #clock-cells = <0>;
1201 + compatible = "mux-clock";
1202 + clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
1203 + reg = <0x44e00530 0x4>;
1204 + bit-mask = <0x1>;
1205 +};
1206 +
1207 +mcasp0_fck: mcasp0_fck {
1208 + #clock-cells = <0>;
1209 + compatible = "fixed-factor-clock";
1210 + clocks = <&sys_clkin_ck>;
1211 + clock-mult = <1>;
1212 + clock-div = <1>;
1213 +};
1214 +
1215 +mcasp1_fck: mcasp1_fck {
1216 + #clock-cells = <0>;
1217 + compatible = "fixed-factor-clock";
1218 + clocks = <&sys_clkin_ck>;
1219 + clock-mult = <1>;
1220 + clock-div = <1>;
1221 +};
1222 +
1223 +mmu_fck: mmu_fck@44e00914 {
1224 + #clock-cells = <0>;
1225 + compatible = "gate-clock";
1226 + clocks = <&dpll_core_m4_ck>;
1227 + bit-shift = <1>;
1228 + reg = <0x44e00914 0x4>;
1229 +};
1230 +
1231 +smartreflex0_fck: smartreflex0_fck {
1232 + #clock-cells = <0>;
1233 + compatible = "fixed-factor-clock";
1234 + clocks = <&sys_clkin_ck>;
1235 + clock-mult = <1>;
1236 + clock-div = <1>;
1237 +};
1238 +
1239 +smartreflex1_fck: smartreflex1_fck {
1240 + #clock-cells = <0>;
1241 + compatible = "fixed-factor-clock";
1242 + clocks = <&sys_clkin_ck>;
1243 + clock-mult = <1>;
1244 + clock-div = <1>;
1245 +};
1246 +
1247 +sha0_fck: sha0_fck {
1248 + #clock-cells = <0>;
1249 + compatible = "fixed-factor-clock";
1250 + clocks = <&sys_clkin_ck>;
1251 + clock-mult = <1>;
1252 + clock-div = <1>;
1253 +};
1254 +
1255 +rng_fck: rng_fck {
1256 + #clock-cells = <0>;
1257 + compatible = "fixed-factor-clock";
1258 + clocks = <&sys_clkin_ck>;
1259 + clock-mult = <1>;
1260 + clock-div = <1>;
1261 +};
1262 +
1263 +aes0_fck: aes0_fck {
1264 + #clock-cells = <0>;
1265 + compatible = "fixed-factor-clock";
1266 + clocks = <&sys_clkin_ck>;
1267 + clock-mult = <1>;
1268 + clock-div = <1>;
1269 +};
1270 +
1271 +timer1_fck: timer1_fck@44e00528 {
1272 + #clock-cells = <0>;
1273 + compatible = "mux-clock";
1274 + clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
1275 + reg = <0x44e00528 0x4>;
1276 + bit-mask = <0x7>;
1277 +};
1278 +
1279 +timer2_fck: timer2_fck@44e00508 {
1280 + #clock-cells = <0>;
1281 + compatible = "mux-clock";
1282 + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
1283 + reg = <0x44e00508 0x4>;
1284 + bit-mask = <0x3>;
1285 +};
1286 +
1287 +timer3_fck: timer3_fck@44e0050c {
1288 + #clock-cells = <0>;
1289 + compatible = "mux-clock";
1290 + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
1291 + reg = <0x44e0050c 0x4>;
1292 + bit-mask = <0x3>;
1293 +};
1294 +
1295 +timer4_fck: timer4_fck@44e00510 {
1296 + #clock-cells = <0>;
1297 + compatible = "mux-clock";
1298 + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
1299 + reg = <0x44e00510 0x4>;
1300 + bit-mask = <0x3>;
1301 +};
1302 +
1303 +timer5_fck: timer5_fck@44e00518 {
1304 + #clock-cells = <0>;
1305 + compatible = "mux-clock";
1306 + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
1307 + reg = <0x44e00518 0x4>;
1308 + bit-mask = <0x3>;
1309 +};
1310 +
1311 +timer6_fck: timer6_fck@44e0051c {
1312 + #clock-cells = <0>;
1313 + compatible = "mux-clock";
1314 + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
1315 + reg = <0x44e0051c 0x4>;
1316 + bit-mask = <0x3>;
1317 +};
1318 +
1319 +timer7_fck: timer7_fck@44e00504 {
1320 + #clock-cells = <0>;
1321 + compatible = "mux-clock";
1322 + clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
1323 + reg = <0x44e00504 0x4>;
1324 + bit-mask = <0x3>;
1325 +};
1326 +
1327 +usbotg_fck: usbotg_fck@44e0047c {
1328 + #clock-cells = <0>;
1329 + compatible = "gate-clock";
1330 + clocks = <&dpll_per_ck>;
1331 + bit-shift = <8>;
1332 + reg = <0x44e0047c 0x4>;
1333 +};
1334 +
1335 +dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
1336 + #clock-cells = <0>;
1337 + compatible = "fixed-factor-clock";
1338 + clocks = <&dpll_core_m4_ck>;
1339 + clock-mult = <1>;
1340 + clock-div = <2>;
1341 +};
1342 +
1343 +ieee5000_fck: ieee5000_fck@44e000e4 {
1344 + #clock-cells = <0>;
1345 + compatible = "gate-clock";
1346 + clocks = <&dpll_core_m4_div2_ck>;
1347 + bit-shift = <1>;
1348 + reg = <0x44e000e4 0x4>;
1349 +};
1350 +
1351 +wdt1_fck: wdt1_fck@44e00538 {
1352 + #clock-cells = <0>;
1353 + compatible = "mux-clock";
1354 + clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
1355 + reg = <0x44e00538 0x4>;
1356 + bit-mask = <0x3>;
1357 +};
1358 +
1359 +l4_rtc_gclk: l4_rtc_gclk {
1360 + #clock-cells = <0>;
1361 + compatible = "fixed-factor-clock";
1362 + clocks = <&dpll_core_m4_ck>;
1363 + clock-mult = <1>;
1364 + clock-div = <2>;
1365 +};
1366 +
1367 +l4hs_gclk: l4hs_gclk {
1368 + #clock-cells = <0>;
1369 + compatible = "fixed-factor-clock";
1370 + clocks = <&dpll_core_m4_ck>;
1371 + clock-mult = <1>;
1372 + clock-div = <1>;
1373 +};
1374 +
1375 +l3s_gclk: l3s_gclk {
1376 + #clock-cells = <0>;
1377 + compatible = "fixed-factor-clock";
1378 + clocks = <&dpll_core_m4_div2_ck>;
1379 + clock-mult = <1>;
1380 + clock-div = <1>;
1381 +};
1382 +
1383 +l4fw_gclk: l4fw_gclk {
1384 + #clock-cells = <0>;
1385 + compatible = "fixed-factor-clock";
1386 + clocks = <&dpll_core_m4_div2_ck>;
1387 + clock-mult = <1>;
1388 + clock-div = <1>;
1389 +};
1390 +
1391 +l4ls_gclk: l4ls_gclk {
1392 + #clock-cells = <0>;
1393 + compatible = "fixed-factor-clock";
1394 + clocks = <&dpll_core_m4_div2_ck>;
1395 + clock-mult = <1>;
1396 + clock-div = <1>;
1397 +};
1398 +
1399 +sysclk_div_ck: sysclk_div_ck {
1400 + #clock-cells = <0>;
1401 + compatible = "fixed-factor-clock";
1402 + clocks = <&dpll_core_m4_ck>;
1403 + clock-mult = <1>;
1404 + clock-div = <1>;
1405 +};
1406 +
1407 +cpsw_125mhz_gclk: cpsw_125mhz_gclk {
1408 + #clock-cells = <0>;
1409 + compatible = "fixed-factor-clock";
1410 + clocks = <&dpll_core_m5_ck>;
1411 + clock-mult = <1>;
1412 + clock-div = <2>;
1413 +};
1414 +
1415 +cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@44e00520 {
1416 + #clock-cells = <0>;
1417 + compatible = "mux-clock";
1418 + clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
1419 + reg = <0x44e00520 0x4>;
1420 + bit-mask = <0x1>;
1421 +};
1422 +
1423 +gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@44e0053c {
1424 + #clock-cells = <0>;
1425 + compatible = "mux-clock";
1426 + clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
1427 + reg = <0x44e0053c 0x4>;
1428 + bit-mask = <0x3>;
1429 +};
1430 +
1431 +gpio0_dbclk: gpio0_dbclk@44e00408 {
1432 + #clock-cells = <0>;
1433 + compatible = "gate-clock";
1434 + clocks = <&gpio0_dbclk_mux_ck>;
1435 + bit-shift = <18>;
1436 + reg = <0x44e00408 0x4>;
1437 +};
1438 +
1439 +gpio1_dbclk: gpio1_dbclk@44e000ac {
1440 + #clock-cells = <0>;
1441 + compatible = "gate-clock";
1442 + clocks = <&clkdiv32k_ick>;
1443 + bit-shift = <18>;
1444 + reg = <0x44e000ac 0x4>;
1445 +};
1446 +
1447 +gpio2_dbclk: gpio2_dbclk@44e000b0 {
1448 + #clock-cells = <0>;
1449 + compatible = "gate-clock";
1450 + clocks = <&clkdiv32k_ick>;
1451 + bit-shift = <18>;
1452 + reg = <0x44e000b0 0x4>;
1453 +};
1454 +
1455 +gpio3_dbclk: gpio3_dbclk@44e000b4 {
1456 + #clock-cells = <0>;
1457 + compatible = "gate-clock";
1458 + clocks = <&clkdiv32k_ick>;
1459 + bit-shift = <18>;
1460 + reg = <0x44e000b4 0x4>;
1461 +};
1462 +
1463 +lcd_gclk: lcd_gclk@44e00534 {
1464 + #clock-cells = <0>;
1465 + compatible = "mux-clock";
1466 + clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
1467 + reg = <0x44e00534 0x4>;
1468 + bit-mask = <0x3>;
1469 + set-rate-parent;
1470 +};
1471 +
1472 +mmc_clk: mmc_clk {
1473 + #clock-cells = <0>;
1474 + compatible = "fixed-factor-clock";
1475 + clocks = <&dpll_per_m2_ck>;
1476 + clock-mult = <1>;
1477 + clock-div = <2>;
1478 +};
1479 +
1480 +gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@44e0052c {
1481 + #clock-cells = <0>;
1482 + compatible = "mux-clock";
1483 + clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
1484 + bit-shift = <1>;
1485 + reg = <0x44e0052c 0x4>;
1486 + bit-mask = <0x1>;
1487 +};
1488 +
1489 +gfx_fck_div_ck: gfx_fck_div_ck@44e0052c {
1490 + #clock-cells = <0>;
1491 + compatible = "divider-clock";
1492 + clocks = <&gfx_fclk_clksel_ck>;
1493 + reg = <0x44e0052c 0x4>;
1494 + table = < 1 0 >, < 2 1 >;
1495 + bit-mask = <0x1>;
1496 +};
1497 +
1498 +sysclkout_pre_ck: sysclkout_pre_ck@44e00700 {
1499 + #clock-cells = <0>;
1500 + compatible = "mux-clock";
1501 + clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
1502 + reg = <0x44e00700 0x4>;
1503 + bit-mask = <0x7>;
1504 +};
1505 +
1506 +clkout2_div_ck: clkout2_div_ck@44e00700 {
1507 + #clock-cells = <0>;
1508 + compatible = "divider-clock";
1509 + clocks = <&sysclkout_pre_ck>;
1510 + bit-shift = <3>;
1511 + reg = <0x44e00700 0x4>;
1512 + table = < 1 0 >, < 2 1 >, < 3 2 >, < 4 3 >, < 5 4 >, < 6 5 >, < 7 6 >, < 8 7 >;
1513 + bit-mask = <0x7>;
1514 +};
1515 +
1516 +dbg_sysclk_ck: dbg_sysclk_ck@44e00414 {
1517 + #clock-cells = <0>;
1518 + compatible = "gate-clock";
1519 + clocks = <&sys_clkin_ck>;
1520 + bit-shift = <19>;
1521 + reg = <0x44e00414 0x4>;
1522 +};
1523 +
1524 +dbg_clka_ck: dbg_clka_ck@44e00414 {
1525 + #clock-cells = <0>;
1526 + compatible = "gate-clock";
1527 + clocks = <&dpll_core_m4_ck>;
1528 + bit-shift = <30>;
1529 + reg = <0x44e00414 0x4>;
1530 +};
1531 +
1532 +stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck@44e00414 {
1533 + #clock-cells = <0>;
1534 + compatible = "mux-clock";
1535 + clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
1536 + bit-shift = <22>;
1537 + reg = <0x44e00414 0x4>;
1538 + bit-mask = <0x3>;
1539 +};
1540 +
1541 +trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck@44e00414 {
1542 + #clock-cells = <0>;
1543 + compatible = "mux-clock";
1544 + clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
1545 + bit-shift = <20>;
1546 + reg = <0x44e00414 0x4>;
1547 + bit-mask = <0x3>;
1548 +};
1549 +
1550 +stm_clk_div_ck: stm_clk_div_ck@44e00414 {
1551 + #clock-cells = <0>;
1552 + compatible = "divider-clock";
1553 + clocks = <&stm_pmd_clock_mux_ck>;
1554 + bit-shift = <27>;
1555 + reg = <0x44e00414 0x4>;
1556 + bit-mask = <0x7>;
1557 + index-power-of-two;
1558 +};
1559 +
1560 +trace_clk_div_ck: trace_clk_div_ck@44e00414 {
1561 + #clock-cells = <0>;
1562 + compatible = "divider-clock";
1563 + clocks = <&trace_pmd_clk_mux_ck>;
1564 + bit-shift = <24>;
1565 + reg = <0x44e00414 0x4>;
1566 + bit-mask = <0x7>;
1567 + index-power-of-two;
1568 +};
1569 +
1570 +clkout2_ck: clkout2_ck@44e00700 {
1571 + #clock-cells = <0>;
1572 + compatible = "gate-clock";
1573 + clocks = <&clkout2_div_ck>;
1574 + bit-shift = <7>;
1575 + reg = <0x44e00700 0x4>;
1576 +};
1577 +
1578 +ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
1579 + #clock-cells = <0>;
1580 + compatible = "gate-clock";
1581 + clocks = <&dpll_per_m2_ck>;
1582 + bit-shift = <0>;
1583 + reg = <0x44e10664 0x4>;
1584 +};
1585 +
1586 +ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
1587 + #clock-cells = <0>;
1588 + compatible = "gate-clock";
1589 + clocks = <&dpll_per_m2_ck>;
1590 + bit-shift = <1>;
1591 + reg = <0x44e10664 0x4>;
1592 +};
1593 +
1594 +ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
1595 + #clock-cells = <0>;
1596 + compatible = "gate-clock";
1597 + clocks = <&dpll_per_m2_ck>;
1598 + bit-shift = <2>;
1599 + reg = <0x44e10664 0x4>;
1600 +};
1601 --- a/arch/arm/boot/dts/am33xx.dtsi
1602 +++ b/arch/arm/boot/dts/am33xx.dtsi
1603 @@ -18,6 +18,9 @@
1604 interrupt-parent = <&intc>;
1605
1606 aliases {
1607 + i2c0 = &i2c0;
1608 + i2c1 = &i2c1;
1609 + i2c2 = &i2c2;
1610 serial0 = &uart0;
1611 serial1 = &uart1;
1612 serial2 = &uart2;
1613 @@ -30,6 +33,8 @@
1614 usb1 = &usb1;
1615 phy0 = &usb0_phy;
1616 phy1 = &usb1_phy;
1617 + ethernet0 = &cpsw_emac0;
1618 + ethernet1 = &cpsw_emac1;
1619 };
1620
1621 cpus {
1622 @@ -53,6 +58,10 @@
1623 275000 1125000
1624 >;
1625 voltage-tolerance = <2>; /* 2 percentage */
1626 +
1627 + clocks = <&dpll_mpu_ck>;
1628 + clock-names = "cpu";
1629 +
1630 clock-latency = <300000>; /* From omap-cpufreq driver */
1631 };
1632 };
1633 @@ -91,6 +100,8 @@
1634 #size-cells = <1>;
1635 ranges;
1636 ti,hwmods = "l3_main";
1637 + clocks = <&l3_gclk>;
1638 + clock-names = "fck";
1639
1640 intc: interrupt-controller@48200000 {
1641 compatible = "ti,omap2-intc";
1642 @@ -100,9 +111,23 @@
1643 reg = <0x48200000 0x1000>;
1644 };
1645
1646 + edma: edma@49000000 {
1647 + compatible = "ti,edma3";
1648 + ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
1649 + reg = <0x49000000 0x10000>,
1650 + <0x44e10f90 0x10>;
1651 + interrupts = <12 13 14>;
1652 + #dma-cells = <1>;
1653 + dma-channels = <64>;
1654 + ti,edma-regions = <4>;
1655 + ti,edma-slots = <256>;
1656 + };
1657 +
1658 gpio0: gpio@44e07000 {
1659 compatible = "ti,omap4-gpio";
1660 ti,hwmods = "gpio1";
1661 + clocks = <&dpll_core_m4_div2_ck>, <&gpio0_dbclk>;
1662 + clock-names = "fck", "dbclk";
1663 gpio-controller;
1664 #gpio-cells = <2>;
1665 interrupt-controller;
1666 @@ -114,6 +139,8 @@
1667 gpio1: gpio@4804c000 {
1668 compatible = "ti,omap4-gpio";
1669 ti,hwmods = "gpio2";
1670 + clocks = <&l4ls_gclk>, <&gpio1_dbclk>;
1671 + clock-names = "fck", "dbclk";
1672 gpio-controller;
1673 #gpio-cells = <2>;
1674 interrupt-controller;
1675 @@ -125,6 +152,8 @@
1676 gpio2: gpio@481ac000 {
1677 compatible = "ti,omap4-gpio";
1678 ti,hwmods = "gpio3";
1679 + clocks = <&l4ls_gclk>, <&gpio2_dbclk>;
1680 + clock-names = "fck", "dbclk";
1681 gpio-controller;
1682 #gpio-cells = <2>;
1683 interrupt-controller;
1684 @@ -136,6 +165,8 @@
1685 gpio3: gpio@481ae000 {
1686 compatible = "ti,omap4-gpio";
1687 ti,hwmods = "gpio4";
1688 + clocks = <&l4ls_gclk>, <&gpio3_dbclk>;
1689 + clock-names = "fck", "dbclk";
1690 gpio-controller;
1691 #gpio-cells = <2>;
1692 interrupt-controller;
1693 @@ -147,6 +178,8 @@
1694 uart0: serial@44e09000 {
1695 compatible = "ti,omap3-uart";
1696 ti,hwmods = "uart1";
1697 + clocks = <&dpll_per_m2_div4_wkupdm_ck>;
1698 + clock-names = "fck";
1699 clock-frequency = <48000000>;
1700 reg = <0x44e09000 0x2000>;
1701 interrupts = <72>;
1702 @@ -156,6 +189,8 @@
1703 uart1: serial@48022000 {
1704 compatible = "ti,omap3-uart";
1705 ti,hwmods = "uart2";
1706 + clocks = <&dpll_per_m2_div4_ck>;
1707 + clock-names = "fck";
1708 clock-frequency = <48000000>;
1709 reg = <0x48022000 0x2000>;
1710 interrupts = <73>;
1711 @@ -165,6 +200,8 @@
1712 uart2: serial@48024000 {
1713 compatible = "ti,omap3-uart";
1714 ti,hwmods = "uart3";
1715 + clocks = <&dpll_per_m2_div4_ck>;
1716 + clock-names = "fck";
1717 clock-frequency = <48000000>;
1718 reg = <0x48024000 0x2000>;
1719 interrupts = <74>;
1720 @@ -174,6 +211,8 @@
1721 uart3: serial@481a6000 {
1722 compatible = "ti,omap3-uart";
1723 ti,hwmods = "uart4";
1724 + clocks = <&dpll_per_m2_div4_ck>;
1725 + clock-names = "fck";
1726 clock-frequency = <48000000>;
1727 reg = <0x481a6000 0x2000>;
1728 interrupts = <44>;
1729 @@ -183,6 +222,8 @@
1730 uart4: serial@481a8000 {
1731 compatible = "ti,omap3-uart";
1732 ti,hwmods = "uart5";
1733 + clocks = <&dpll_per_m2_div4_ck>;
1734 + clock-names = "fck";
1735 clock-frequency = <48000000>;
1736 reg = <0x481a8000 0x2000>;
1737 interrupts = <45>;
1738 @@ -192,6 +233,8 @@
1739 uart5: serial@481aa000 {
1740 compatible = "ti,omap3-uart";
1741 ti,hwmods = "uart6";
1742 + clocks = <&dpll_per_m2_div4_ck>;
1743 + clock-names = "fck";
1744 clock-frequency = <48000000>;
1745 reg = <0x481aa000 0x2000>;
1746 interrupts = <46>;
1747 @@ -203,6 +246,8 @@
1748 #address-cells = <1>;
1749 #size-cells = <0>;
1750 ti,hwmods = "i2c1";
1751 + clocks = <&dpll_per_m2_div4_wkupdm_ck>;
1752 + clock-names = "fck";
1753 reg = <0x44e0b000 0x1000>;
1754 interrupts = <70>;
1755 status = "disabled";
1756 @@ -213,6 +258,8 @@
1757 #address-cells = <1>;
1758 #size-cells = <0>;
1759 ti,hwmods = "i2c2";
1760 + clocks = <&dpll_per_m2_div4_ck>;
1761 + clock-names = "fck";
1762 reg = <0x4802a000 0x1000>;
1763 interrupts = <71>;
1764 status = "disabled";
1765 @@ -223,14 +270,62 @@
1766 #address-cells = <1>;
1767 #size-cells = <0>;
1768 ti,hwmods = "i2c3";
1769 + clocks = <&dpll_per_m2_div4_ck>;
1770 + clock-names = "fck";
1771 reg = <0x4819c000 0x1000>;
1772 interrupts = <30>;
1773 status = "disabled";
1774 };
1775
1776 + mmc1: mmc@48060000 {
1777 + compatible = "ti,omap4-hsmmc";
1778 + ti,hwmods = "mmc1";
1779 + clocks = <&mmc_clk>, <&clkdiv32k_ick>;
1780 + clock-names = "fck", "mmchsdb_fck";
1781 + ti,dual-volt;
1782 + ti,needs-special-reset;
1783 + ti,needs-special-hs-handling;
1784 + dmas = <&edma 24
1785 + &edma 25>;
1786 + dma-names = "tx", "rx";
1787 + interrupts = <64>;
1788 + interrupt-parent = <&intc>;
1789 + reg = <0x48060000 0x1000>;
1790 + status = "disabled";
1791 + };
1792 +
1793 + mmc2: mmc@481d8000 {
1794 + compatible = "ti,omap4-hsmmc";
1795 + ti,hwmods = "mmc2";
1796 + clocks = <&mmc_clk>, <&clkdiv32k_ick>;
1797 + clock-names = "fck", "mmchsdb_fck";
1798 + ti,needs-special-reset;
1799 + dmas = <&edma 2
1800 + &edma 3>;
1801 + dma-names = "tx", "rx";
1802 + interrupts = <28>;
1803 + interrupt-parent = <&intc>;
1804 + reg = <0x481d8000 0x1000>;
1805 + status = "disabled";
1806 + };
1807 +
1808 + mmc3: mmc@47810000 {
1809 + compatible = "ti,omap4-hsmmc";
1810 + ti,hwmods = "mmc3";
1811 + clocks = <&mmc_clk>, <&clkdiv32k_ick>;
1812 + clock-names = "fck", "mmchsdb_fck";
1813 + ti,needs-special-reset;
1814 + interrupts = <29>;
1815 + interrupt-parent = <&intc>;
1816 + reg = <0x47810000 0x1000>;
1817 + status = "disabled";
1818 + };
1819 +
1820 wdt2: wdt@44e35000 {
1821 compatible = "ti,omap3-wdt";
1822 ti,hwmods = "wd_timer2";
1823 + clocks = <&wdt1_fck>;
1824 + clock-names = "fck";
1825 reg = <0x44e35000 0x1000>;
1826 interrupts = <91>;
1827 };
1828 @@ -238,6 +333,8 @@
1829 dcan0: d_can@481cc000 {
1830 compatible = "bosch,d_can";
1831 ti,hwmods = "d_can0";
1832 + clocks = <&dcan0_fck>;
1833 + clock-names = "fck";
1834 reg = <0x481cc000 0x2000
1835 0x44e10644 0x4>;
1836 interrupts = <52>;
1837 @@ -247,17 +344,32 @@
1838 dcan1: d_can@481d0000 {
1839 compatible = "bosch,d_can";
1840 ti,hwmods = "d_can1";
1841 + clocks = <&dcan1_fck>;
1842 + clock-names = "fck";
1843 reg = <0x481d0000 0x2000
1844 0x44e10644 0x4>;
1845 interrupts = <55>;
1846 status = "disabled";
1847 };
1848
1849 + mailbox: mailbox@480C8000 {
1850 + compatible = "ti,omap4-mailbox";
1851 + reg = <0x480C8000 0x200>;
1852 + interrupts = <77>;
1853 + ti,hwmods = "mailbox";
1854 + ti,mbox-num-users = <4>;
1855 + ti,mbox-num-fifos = <8>;
1856 + ti,mbox-names = "wkup_m3";
1857 + ti,mbox-data = <0 0 0 0>;
1858 + };
1859 +
1860 timer1: timer@44e31000 {
1861 compatible = "ti,am335x-timer-1ms";
1862 reg = <0x44e31000 0x400>;
1863 interrupts = <67>;
1864 ti,hwmods = "timer1";
1865 + clocks = <&timer1_fck>;
1866 + clock-names = "fck";
1867 ti,timer-alwon;
1868 };
1869
1870 @@ -266,6 +378,8 @@
1871 reg = <0x48040000 0x400>;
1872 interrupts = <68>;
1873 ti,hwmods = "timer2";
1874 + clocks = <&timer2_fck>;
1875 + clock-names = "fck";
1876 };
1877
1878 timer3: timer@48042000 {
1879 @@ -273,6 +387,8 @@
1880 reg = <0x48042000 0x400>;
1881 interrupts = <69>;
1882 ti,hwmods = "timer3";
1883 + clocks = <&timer3_fck>;
1884 + clock-names = "fck";
1885 };
1886
1887 timer4: timer@48044000 {
1888 @@ -280,6 +396,8 @@
1889 reg = <0x48044000 0x400>;
1890 interrupts = <92>;
1891 ti,hwmods = "timer4";
1892 + clocks = <&timer4_fck>;
1893 + clock-names = "fck";
1894 ti,timer-pwm;
1895 };
1896
1897 @@ -288,6 +406,8 @@
1898 reg = <0x48046000 0x400>;
1899 interrupts = <93>;
1900 ti,hwmods = "timer5";
1901 + clocks = <&timer5_fck>;
1902 + clock-names = "fck";
1903 ti,timer-pwm;
1904 };
1905
1906 @@ -296,6 +416,8 @@
1907 reg = <0x48048000 0x400>;
1908 interrupts = <94>;
1909 ti,hwmods = "timer6";
1910 + clocks = <&timer6_fck>;
1911 + clock-names = "fck";
1912 ti,timer-pwm;
1913 };
1914
1915 @@ -304,6 +426,8 @@
1916 reg = <0x4804a000 0x400>;
1917 interrupts = <95>;
1918 ti,hwmods = "timer7";
1919 + clocks = <&timer7_fck>;
1920 + clock-names = "fck";
1921 ti,timer-pwm;
1922 };
1923
1924 @@ -313,6 +437,8 @@
1925 interrupts = <75
1926 76>;
1927 ti,hwmods = "rtc";
1928 + clocks = <&clk_32768_ck>;
1929 + clock-names = "fck";
1930 };
1931
1932 spi0: spi@48030000 {
1933 @@ -323,6 +449,13 @@
1934 interrupts = <65>;
1935 ti,spi-num-cs = <2>;
1936 ti,hwmods = "spi0";
1937 + clocks = <&dpll_per_m2_div4_ck>;
1938 + clock-names = "fck";
1939 + dmas = <&edma 16
1940 + &edma 17
1941 + &edma 18
1942 + &edma 19>;
1943 + dma-names = "tx0", "rx0", "tx1", "rx1";
1944 status = "disabled";
1945 };
1946
1947 @@ -334,6 +467,13 @@
1948 interrupts = <125>;
1949 ti,spi-num-cs = <2>;
1950 ti,hwmods = "spi1";
1951 + clocks = <&dpll_per_m2_div4_ck>;
1952 + clock-names = "fck";
1953 + dmas = <&edma 42
1954 + &edma 43
1955 + &edma 44
1956 + &edma 45>;
1957 + dma-names = "tx0", "rx0", "tx1", "rx1";
1958 status = "disabled";
1959 };
1960
1961 @@ -345,6 +485,8 @@
1962 #size-cells = <1>;
1963 ti,hwmods = "usb_otg_hs";
1964 status = "disabled";
1965 + clocks = <&usbotg_fck>;
1966 + clock-names = "fck";
1967
1968 ctrl_mod: control@44e10000 {
1969 compatible = "ti,am335x-usb-ctrl-module";
1970 @@ -469,6 +611,8 @@
1971 compatible = "ti,am33xx-pwmss";
1972 reg = <0x48300000 0x10>;
1973 ti,hwmods = "epwmss0";
1974 + clocks = <&l4ls_gclk>;
1975 + clock-names = "fck";
1976 #address-cells = <1>;
1977 #size-cells = <1>;
1978 status = "disabled";
1979 @@ -481,6 +625,8 @@
1980 #pwm-cells = <3>;
1981 reg = <0x48300100 0x80>;
1982 ti,hwmods = "ecap0";
1983 + clocks = <&l4ls_gclk>;
1984 + clock-names = "fck";
1985 status = "disabled";
1986 };
1987
1988 @@ -489,6 +635,8 @@
1989 #pwm-cells = <3>;
1990 reg = <0x48300200 0x80>;
1991 ti,hwmods = "ehrpwm0";
1992 + clocks = <&l4ls_gclk>;
1993 + clock-names = "fck";
1994 status = "disabled";
1995 };
1996 };
1997 @@ -497,6 +645,8 @@
1998 compatible = "ti,am33xx-pwmss";
1999 reg = <0x48302000 0x10>;
2000 ti,hwmods = "epwmss1";
2001 + clocks = <&l4ls_gclk>;
2002 + clock-names = "fck";
2003 #address-cells = <1>;
2004 #size-cells = <1>;
2005 status = "disabled";
2006 @@ -509,6 +659,8 @@
2007 #pwm-cells = <3>;
2008 reg = <0x48302100 0x80>;
2009 ti,hwmods = "ecap1";
2010 + clocks = <&l4ls_gclk>;
2011 + clock-names = "fck";
2012 status = "disabled";
2013 };
2014
2015 @@ -517,6 +669,8 @@
2016 #pwm-cells = <3>;
2017 reg = <0x48302200 0x80>;
2018 ti,hwmods = "ehrpwm1";
2019 + clocks = <&l4ls_gclk>;
2020 + clock-names = "fck";
2021 status = "disabled";
2022 };
2023 };
2024 @@ -525,6 +679,8 @@
2025 compatible = "ti,am33xx-pwmss";
2026 reg = <0x48304000 0x10>;
2027 ti,hwmods = "epwmss2";
2028 + clocks = <&l4ls_gclk>;
2029 + clock-names = "fck";
2030 #address-cells = <1>;
2031 #size-cells = <1>;
2032 status = "disabled";
2033 @@ -537,6 +693,8 @@
2034 #pwm-cells = <3>;
2035 reg = <0x48304100 0x80>;
2036 ti,hwmods = "ecap2";
2037 + clocks = <&l4ls_gclk>;
2038 + clock-names = "fck";
2039 status = "disabled";
2040 };
2041
2042 @@ -545,6 +703,8 @@
2043 #pwm-cells = <3>;
2044 reg = <0x48304200 0x80>;
2045 ti,hwmods = "ehrpwm2";
2046 + clocks = <&l4ls_gclk>;
2047 + clock-names = "fck";
2048 status = "disabled";
2049 };
2050 };
2051 @@ -552,6 +712,8 @@
2052 mac: ethernet@4a100000 {
2053 compatible = "ti,cpsw";
2054 ti,hwmods = "cpgmac0";
2055 + clocks = <&cpsw_125mhz_gclk>;
2056 + clock-names = "fck";
2057 cpdma_channels = <8>;
2058 ale_entries = <1024>;
2059 bd_ram_size = <0x2000>;
2060 @@ -581,6 +743,8 @@
2061 #address-cells = <1>;
2062 #size-cells = <0>;
2063 ti,hwmods = "davinci_mdio";
2064 + clocks = <&cpsw_125mhz_gclk>;
2065 + clock-names = "fck";
2066 bus_freq = <1000000>;
2067 reg = <0x4a101000 0x100>;
2068 };
2069 @@ -594,19 +758,33 @@
2070 /* Filled in by U-Boot */
2071 mac-address = [ 00 00 00 00 00 00 ];
2072 };
2073 +
2074 + phy_sel: cpsw-phy-sel@44e10650 {
2075 + compatible = "ti,am3352-cpsw-phy-sel";
2076 + reg= <0x44e10650 0x4>;
2077 + reg-names = "gmii-sel";
2078 + };
2079 };
2080
2081 ocmcram: ocmcram@40300000 {
2082 compatible = "ti,am3352-ocmcram";
2083 reg = <0x40300000 0x10000>;
2084 ti,hwmods = "ocmcram";
2085 + clocks = <&l3_gclk>;
2086 + clock-names = "fck";
2087 };
2088
2089 wkup_m3: wkup_m3@44d00000 {
2090 compatible = "ti,am3353-wkup-m3";
2091 - reg = <0x44d00000 0x4000 /* M3 UMEM */
2092 - 0x44d80000 0x2000>; /* M3 DMEM */
2093 + reg = <0x44d00000 0x4000
2094 + 0x44d80000 0x2000
2095 + 0x44e11324 0x0024>;
2096 + reg-names = "m3_umem", "m3_dmem", "ipc_regs";
2097 + interrupts = <78>;
2098 ti,hwmods = "wkup_m3";
2099 + ti,no-reset;
2100 + clocks = <&dpll_core_m4_div2_ck>;
2101 + clock-names = "fck";
2102 };
2103
2104 elm: elm@48080000 {
2105 @@ -614,6 +792,8 @@
2106 reg = <0x48080000 0x2000>;
2107 interrupts = <4>;
2108 ti,hwmods = "elm";
2109 + clocks = <&l4ls_gclk>;
2110 + clock-names = "fck";
2111 status = "disabled";
2112 };
2113
2114 @@ -623,6 +803,8 @@
2115 interrupt-parent = <&intc>;
2116 interrupts = <16>;
2117 ti,hwmods = "adc_tsc";
2118 + clocks = <&adc_tsc_fck>;
2119 + clock-names = "fck";
2120 status = "disabled";
2121
2122 tsc {
2123 @@ -637,6 +819,9 @@
2124 gpmc: gpmc@50000000 {
2125 compatible = "ti,am3352-gpmc";
2126 ti,hwmods = "gpmc";
2127 + ti,no-idle;
2128 + clocks = <&l3s_gclk>;
2129 + clock-names = "fck";
2130 reg = <0x50000000 0x2000>;
2131 interrupts = <100>;
2132 gpmc,num-cs = <7>;
2133 @@ -645,5 +830,102 @@
2134 #size-cells = <1>;
2135 status = "disabled";
2136 };
2137 +
2138 + prcm: prcm@44e00000 {
2139 + compatible = "ti,am3352-prcm";
2140 + reg = <0x44e00000 0x1300>;
2141 + #reset-cells = <1>;
2142 + };
2143 +
2144 + sham: sham@53100000 {
2145 + compatible = "ti,omap4-sham";
2146 + ti,hwmods = "sham";
2147 + #address-cells = <1>;
2148 + #size-cells = <0>;
2149 + reg = <0x53100000 0x200>;
2150 + interrupt-parent = <&intc>;
2151 + interrupts = <109>;
2152 + dmas = <&edma 36>;
2153 + dma-names = "rx";
2154 + clocks = <&l3_gclk>;
2155 + clock-names = "fck";
2156 + };
2157 +
2158 + aes: aes@53500000 {
2159 + compatible = "ti,omap4-aes";
2160 + ti,hwmods = "aes";
2161 + #address-cells = <1>;
2162 + #size-cells = <0>;
2163 + reg = <0x53500000 0xa0>;
2164 + interrupt-parent = <&intc>;
2165 + interrupts = <103>;
2166 + dmas = <&edma 6
2167 + &edma 5>;
2168 + dma-names = "tx", "rx";
2169 + clocks = <&aes0_fck>;
2170 + clock-names = "fck";
2171 + };
2172 +
2173 + rng: rng@48310000 {
2174 + compatible = "ti,omap4-rng";
2175 + ti,hwmods = "rng";
2176 + reg = <0x48310000 0x2000>;
2177 + interrupts = <111>;
2178 + clocks = <&rng_fck>;
2179 + clock-names = "fck";
2180 + };
2181 +
2182 + lcdc: lcdc@0x4830e000 {
2183 + compatible = "ti,am33xx-tilcdc";
2184 + reg = <0x4830e000 0x1000>;
2185 + interrupt-parent = <&intc>;
2186 + interrupts = <36>;
2187 + clocks = <&lcd_gclk>;
2188 + clock-names = "fck";
2189 + ti,hwmods = "lcdc";
2190 + status = "disabled";
2191 + };
2192 +
2193 + mcasp0: mcasp@48038000 {
2194 + compatible = "ti,omap2-mcasp-audio";
2195 + ti,hwmods = "mcasp0";
2196 + reg = <0x48038000 0x2000>,
2197 + <0x46400000 0x400000>;
2198 + reg-names = "mpu", "dma";
2199 + interrupts = <80 81>;
2200 + interrupts-names = "tx", "rx";
2201 + status = "disabled";
2202 + dmas = <&edma 8
2203 + &edma 9>;
2204 + dma-names = "tx", "rx";
2205 + };
2206 +
2207 + mcasp1: mcasp@4803C000 {
2208 + compatible = "ti,omap2-mcasp-audio";
2209 + ti,hwmods = "mcasp1";
2210 + reg = <0x4803C000 0x2000>,
2211 + <0x46400000 0x400000>;
2212 + reg-names = "mpu", "dma";
2213 + interrupts = <82 83>;
2214 + interrupts-names = "tx", "rx";
2215 + status = "disabled";
2216 + dmas = <&edma 10
2217 + &edma 11>;
2218 + dma-names = "tx", "rx";
2219 + };
2220 + };
2221 +
2222 + clocks {
2223 + #address-cells = <1>;
2224 + #size-cells = <1>;
2225 + ranges;
2226 + /include/ "am33xx-clocks.dtsi"
2227 };
2228 +
2229 + clockdomains {
2230 + clk_24mhz_clkdm: clk_24mhz_clkdm {
2231 + compatible = "ti,clockdomain";
2232 + clocks = <&clkdiv32k_ick>;
2233 + };
2234 + };
2235 };
2236 --- /dev/null
2237 +++ b/arch/arm/boot/dts/am3517.dtsi
2238 @@ -0,0 +1,116 @@
2239 +/*
2240 + * Device Tree Source for AM3517 SoC
2241 + *
2242 + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
2243 + *
2244 + * This file is licensed under the terms of the GNU General Public License
2245 + * version 2. This program is licensed "as is" without any warranty of any
2246 + * kind, whether express or implied.
2247 + */
2248 +
2249 +#include "omap3.dtsi"
2250 +
2251 +/ {
2252 + cpus {
2253 + cpu@0 {
2254 + /* OMAP343x/OMAP35xx variants OPP1-5 */
2255 + operating-points = <
2256 + /* kHz uV */
2257 + 125000 975000
2258 + 250000 1075000
2259 + 500000 1200000
2260 + 550000 1270000
2261 + 600000 1350000
2262 + >;
2263 + clock-latency = <300000>; /* From legacy driver */
2264 + };
2265 + };
2266 +
2267 + clocks {
2268 + #address-cells = <1>;
2269 + #size-cells = <1>;
2270 + ranges;
2271 + /include/ "am35xx-clocks.dtsi"
2272 + /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
2273 + };
2274 +
2275 + clockdomains {
2276 + dss_clkdm: dss_clkdm {
2277 + compatible = "ti,clockdomain";
2278 + clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
2279 + };
2280 +
2281 + usbhost_clkdm: usbhost_clkdm {
2282 + compatible = "ti,clockdomain";
2283 + clocks = <&usbhost_48m_fck>, <&usbhost_ick>;
2284 + };
2285 +
2286 + core_l4_clkdm: core_l4_clkdm {
2287 + compatible = "ti,clockdomain";
2288 + clocks = <&mmchs1_ick>, <&mmchs2_ick>, <&hdq_fck>,
2289 + <&uart1_ick>, <&mcspi4_fck>, <&i2c3_fck>,
2290 + <&mcspi2_ick>, <&uart2_ick>, <&mcspi3_ick>,
2291 + <&i2c1_fck>, <&hdq_ick>, <&sha12_ick>,
2292 + <&mcbsp5_ick>, <&mcspi3_fck>, <&aes2_ick>,
2293 + <&mcspi1_ick>, <&uart2_fck>, <&mmchs2_fck>,
2294 + <&mmchs1_fck>, <&i2c3_ick>, <&mcspi1_fck>,
2295 + <&mcspi4_ick>, <&omapctrl_ick>, <&mcbsp1_ick>,
2296 + <&mcspi2_fck>, <&gpt10_ick>, <&i2c2_fck>,
2297 + <&i2c2_ick>, <&gpt11_ick>, <&i2c1_ick>,
2298 + <&uart1_fck>;
2299 + };
2300 +
2301 + wkup_clkdm: wkup_clkdm {
2302 + compatible = "ti,clockdomain";
2303 + clocks = <&wdt1_ick>, <&gpt12_ick>, <&gpio1_ick>,
2304 + <&gpt1_ick>, <&omap_32ksync_ick>, <&wdt2_ick>,
2305 + <&wdt2_fck>;
2306 + };
2307 +
2308 + dpll4_clkdm: dpll4_clkdm {
2309 + compatible = "ti,clockdomain";
2310 + clocks = <&dpll4_ck>;
2311 + };
2312 +
2313 + core_l3_clkdm: core_l3_clkdm {
2314 + compatible = "ti,clockdomain";
2315 + clocks = <&sdrc_ick>;
2316 + };
2317 +
2318 + per_clkdm: per_clkdm {
2319 + compatible = "ti,clockdomain";
2320 + clocks = <&gpt2_ick>, <&uart3_fck>, <&gpio3_ick>,
2321 + <&mcbsp2_ick>, <&gpt6_ick>, <&mcbsp4_ick>,
2322 + <&gpt4_ick>, <&mcbsp3_ick>, <&gpt8_ick>,
2323 + <&uart3_ick>, <&gpt5_ick>, <&gpt7_ick>,
2324 + <&gpio2_ick>, <&gpio6_ick>, <&gpt9_ick>,
2325 + <&gpt3_ick>, <&gpio5_ick>, <&wdt3_ick>,
2326 + <&gpio4_ick>, <&wdt3_fck>, <&uart4_ick>;
2327 + };
2328 +
2329 + emu_clkdm: emu_clkdm {
2330 + compatible = "ti,clockdomain";
2331 + clocks = <&emu_src_ck>;
2332 + };
2333 +
2334 + sgx_clkdm: sgx_clkdm {
2335 + compatible = "ti,clockdomain";
2336 + clocks = <&sgx_ick>;
2337 + };
2338 +
2339 + dpll3_clkdm: dpll3_clkdm {
2340 + compatible = "ti,clockdomain";
2341 + clocks = <&dpll3_ck>;
2342 + };
2343 +
2344 + dpll5_clkdm: dpll5_clkdm {
2345 + compatible = "ti,clockdomain";
2346 + clocks = <&dpll5_ck>;
2347 + };
2348 +
2349 + dpll1_clkdm: dpll1_clkdm {
2350 + compatible = "ti,clockdomain";
2351 + clocks = <&dpll1_ck>;
2352 + };
2353 + };
2354 +};
2355 --- a/arch/arm/boot/dts/am3517-evm.dts
2356 +++ b/arch/arm/boot/dts/am3517-evm.dts
2357 @@ -7,7 +7,7 @@
2358 */
2359 /dts-v1/;
2360
2361 -#include "omap34xx.dtsi"
2362 +#include "am3517.dtsi"
2363
2364 / {
2365 model = "TI AM3517 EVM (AM3517/05)";
2366 --- a/arch/arm/boot/dts/am3517_mt_ventoux.dts
2367 +++ b/arch/arm/boot/dts/am3517_mt_ventoux.dts
2368 @@ -7,7 +7,7 @@
2369 */
2370 /dts-v1/;
2371
2372 -#include "omap34xx.dtsi"
2373 +#include "am3517.dtsi"
2374
2375 / {
2376 model = "TeeJet Mt.Ventoux";
2377 --- /dev/null
2378 +++ b/arch/arm/boot/dts/am35xx-clocks.dtsi
2379 @@ -0,0 +1,101 @@
2380 +/*
2381 + * Device Tree Source for AM35xx clock data
2382 + *
2383 + * Copyright (C) 2013 Texas Instruments, Inc.
2384 + *
2385 + * This program is free software; you can redistribute it and/or modify
2386 + * it under the terms of the GNU General Public License version 2 as
2387 + * published by the Free Software Foundation.
2388 + */
2389 +
2390 +ipss_ick: ipss_ick@48004a10 {
2391 + #clock-cells = <0>;
2392 + compatible = "ti,am35xx-interface-clock";
2393 + clocks = <&core_l3_ick>;
2394 + reg = <0x48004a10 0x4>;
2395 + ti,enable-bit = <4>;
2396 +};
2397 +
2398 +rmii_ck: rmii_ck {
2399 + #clock-cells = <0>;
2400 + compatible = "fixed-clock";
2401 + clock-frequency = <50000000>;
2402 +};
2403 +
2404 +pclk_ck: pclk_ck {
2405 + #clock-cells = <0>;
2406 + compatible = "fixed-clock";
2407 + clock-frequency = <27000000>;
2408 +};
2409 +
2410 +emac_ick: emac_ick@4800259c {
2411 + #clock-cells = <0>;
2412 + compatible = "ti,am35xx-gate-clock";
2413 + clocks = <&ipss_ick>;
2414 + reg = <0x4800259c 0x4>;
2415 + ti,enable-bit = <1>;
2416 +};
2417 +
2418 +emac_fck: emac_fck@4800259c {
2419 + #clock-cells = <0>;
2420 + compatible = "gate-clock";
2421 + clocks = <&rmii_ck>;
2422 + reg = <0x4800259c 0x4>;
2423 + bit-shift = <9>;
2424 +};
2425 +
2426 +vpfe_ick: vpfe_ick@4800259c {
2427 + #clock-cells = <0>;
2428 + compatible = "ti,am35xx-gate-clock";
2429 + clocks = <&ipss_ick>;
2430 + reg = <0x4800259c 0x4>;
2431 + ti,enable-bit = <2>;
2432 +};
2433 +
2434 +vpfe_fck: vpfe_fck@4800259c {
2435 + #clock-cells = <0>;
2436 + compatible = "gate-clock";
2437 + clocks = <&pclk_ck>;
2438 + reg = <0x4800259c 0x4>;
2439 + bit-shift = <10>;
2440 +};
2441 +
2442 +hsotgusb_ick: hsotgusb_ick@4800259c {
2443 + #clock-cells = <0>;
2444 + compatible = "ti,am35xx-gate-clock";
2445 + clocks = <&ipss_ick>;
2446 + reg = <0x4800259c 0x4>;
2447 + ti,enable-bit = <0>;
2448 +};
2449 +
2450 +hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@4800259c {
2451 + #clock-cells = <0>;
2452 + compatible = "gate-clock";
2453 + clocks = <&sys_ck>;
2454 + reg = <0x4800259c 0x4>;
2455 + bit-shift = <8>;
2456 +};
2457 +
2458 +hecc_ck: hecc_ck@4800259c {
2459 + #clock-cells = <0>;
2460 + compatible = "ti,am35xx-gate-clock";
2461 + clocks = <&sys_ck>;
2462 + reg = <0x4800259c 0x4>;
2463 + ti,enable-bit = <3>;
2464 +};
2465 +
2466 +uart4_ick_am35xx: uart4_ick_am35xx@48004a10 {
2467 + #clock-cells = <0>;
2468 + compatible = "ti,omap3-interface-clock";
2469 + clocks = <&core_l4_ick>;
2470 + reg = <0x48004a10 0x4>;
2471 + ti,enable-bit = <23>;
2472 +};
2473 +
2474 +uart4_fck_am35xx: uart4_fck_am35xx@48004a00 {
2475 + #clock-cells = <0>;
2476 + compatible = "ti,gate-clock";
2477 + clocks = <&core_48m_fck>;
2478 + reg = <0x48004a00 0x4>;
2479 + ti,enable-bit = <23>;
2480 +};
2481 --- a/arch/arm/boot/dts/am4372.dtsi
2482 +++ b/arch/arm/boot/dts/am4372.dtsi
2483 @@ -8,6 +8,7 @@
2484 * kind, whether express or implied.
2485 */
2486
2487 +#include <dt-bindings/gpio/gpio.h>
2488 #include <dt-bindings/interrupt-controller/arm-gic.h>
2489
2490 #include "skeleton.dtsi"
2491 @@ -18,12 +19,21 @@
2492
2493
2494 aliases {
2495 + i2c0 = &i2c0;
2496 + i2c1 = &i2c1;
2497 + i2c2 = &i2c2;
2498 serial0 = &uart0;
2499 + ethernet0 = &cpsw_emac0;
2500 + ethernet1 = &cpsw_emac1;
2501 };
2502
2503 cpus {
2504 + #address-cells = <1>;
2505 + #size-cells = <0>;
2506 cpu@0 {
2507 compatible = "arm,cortex-a9";
2508 + device_type = "cpu";
2509 + reg = <0>;
2510 };
2511 };
2512
2513 @@ -35,16 +45,124 @@
2514 <0x48240100 0x0100>;
2515 };
2516
2517 + l2-cache-controller@48242000 {
2518 + compatible = "arm,pl310-cache";
2519 + reg = <0x48242000 0x1000>;
2520 + cache-unified;
2521 + cache-level = <2>;
2522 + };
2523 +
2524 + am43xx_pinmux: pinmux@44e10800 {
2525 + compatible = "pinctrl-single";
2526 + reg = <0x44e10800 0x31c>;
2527 + #address-cells = <1>;
2528 + #size-cells = <0>;
2529 + pinctrl-single,register-width = <32>;
2530 + pinctrl-single,function-mask = <0xffffffff>;
2531 + };
2532 +
2533 ocp {
2534 compatible = "simple-bus";
2535 #address-cells = <1>;
2536 #size-cells = <1>;
2537 ranges;
2538 + ti,hwmods = "l3_main";
2539 + clocks = <&l3_gclk>;
2540 + clock-names = "fck";
2541 +
2542 + edma: edma@49000000 {
2543 + compatible = "ti,edma3";
2544 + ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
2545 + reg = <0x49000000 0x10000>,
2546 + <0x44e10f90 0x10>;
2547 + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
2548 + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
2549 + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2550 + #dma-cells = <1>;
2551 + dma-channels = <64>;
2552 + ti,edma-regions = <4>;
2553 + ti,edma-slots = <256>;
2554 + };
2555
2556 uart0: serial@44e09000 {
2557 compatible = "ti,am4372-uart","ti,omap2-uart";
2558 reg = <0x44e09000 0x2000>;
2559 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2560 + ti,hwmods = "uart1";
2561 + clocks = <&dpll_per_m2_div4_wkupdm_ck>;
2562 + clock-names = "fck";
2563 + };
2564 +
2565 + uart1: serial@48022000 {
2566 + compatible = "ti,am4372-uart","ti,omap2-uart";
2567 + reg = <0x48022000 0x2000>;
2568 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
2569 + ti,hwmods = "uart2";
2570 + clocks = <&dpll_per_m2_div4_ck>;
2571 + clock-names = "fck";
2572 + status = "disabled";
2573 + };
2574 +
2575 + uart2: serial@48024000 {
2576 + compatible = "ti,am4372-uart","ti,omap2-uart";
2577 + reg = <0x48024000 0x2000>;
2578 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
2579 + ti,hwmods = "uart3";
2580 + clocks = <&dpll_per_m2_div4_ck>;
2581 + clock-names = "fck";
2582 + status = "disabled";
2583 + };
2584 +
2585 + uart3: serial@481a6000 {
2586 + compatible = "ti,am4372-uart","ti,omap2-uart";
2587 + reg = <0x481a6000 0x2000>;
2588 + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
2589 + ti,hwmods = "uart4";
2590 + clocks = <&dpll_per_m2_div4_ck>;
2591 + clock-names = "fck";
2592 + status = "disabled";
2593 + };
2594 +
2595 + uart4: serial@481a8000 {
2596 + compatible = "ti,am4372-uart","ti,omap2-uart";
2597 + reg = <0x481a8000 0x2000>;
2598 + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2599 + ti,hwmods = "uart5";
2600 + clocks = <&dpll_per_m2_div4_ck>;
2601 + clock-names = "fck";
2602 + status = "disabled";
2603 + };
2604 +
2605 + uart5: serial@481aa000 {
2606 + compatible = "ti,am4372-uart","ti,omap2-uart";
2607 + reg = <0x481aa000 0x2000>;
2608 + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
2609 + ti,hwmods = "uart6";
2610 + clocks = <&dpll_per_m2_div4_ck>;
2611 + clock-names = "fck";
2612 + status = "disabled";
2613 + };
2614 +
2615 + mailbox: mailbox@480C8000 {
2616 + compatible = "ti,omap4-mailbox";
2617 + reg = <0x480C8000 0x200>;
2618 + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
2619 + ti,hwmods = "mailbox";
2620 + ti,mbox-num-users = <4>;
2621 + ti,mbox-num-fifos = <8>;
2622 + ti,mbox-names = "wkup_m3";
2623 + ti,mbox-data = <0 0 0 0>;
2624 + };
2625 +
2626 + qspi: qspi@47900000 {
2627 + compatible = "ti,am4372-qspi";
2628 + reg = <0x47900000 0x100>;
2629 + #address-cells = <1>;
2630 + #size-cells = <0>;
2631 + ti,hwmods = "qspi";
2632 + interrupts = <0 138 0x4>;
2633 + num-cs = <4>;
2634 + mmap_read;
2635 };
2636
2637 timer1: timer@44e31000 {
2638 @@ -52,17 +170,818 @@
2639 reg = <0x44e31000 0x400>;
2640 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
2641 ti,timer-alwon;
2642 + ti,hwmods = "timer1";
2643 + clocks = <&timer1_fck>;
2644 + clock-names = "fck";
2645 };
2646
2647 timer2: timer@48040000 {
2648 compatible = "ti,am4372-timer","ti,am335x-timer";
2649 reg = <0x48040000 0x400>;
2650 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
2651 + ti,hwmods = "timer2";
2652 + clocks = <&timer2_fck>;
2653 + clock-names = "fck";
2654 + };
2655 +
2656 + timer3: timer@48042000 {
2657 + compatible = "ti,am4372-timer","ti,am335x-timer";
2658 + reg = <0x48042000 0x400>;
2659 + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
2660 + ti,hwmods = "timer3";
2661 + clocks = <&timer3_fck>;
2662 + clock-names = "fck";
2663 + status = "disabled";
2664 + };
2665 +
2666 + timer4: timer@48044000 {
2667 + compatible = "ti,am4372-timer","ti,am335x-timer";
2668 + reg = <0x48044000 0x400>;
2669 + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
2670 + ti,timer-pwm;
2671 + ti,hwmods = "timer4";
2672 + clocks = <&timer4_fck>;
2673 + clock-names = "fck";
2674 + status = "disabled";
2675 + };
2676 +
2677 + timer5: timer@48046000 {
2678 + compatible = "ti,am4372-timer","ti,am335x-timer";
2679 + reg = <0x48046000 0x400>;
2680 + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
2681 + ti,timer-pwm;
2682 + ti,hwmods = "timer5";
2683 + clocks = <&timer5_fck>;
2684 + clock-names = "fck";
2685 + status = "disabled";
2686 + };
2687 +
2688 + timer6: timer@48048000 {
2689 + compatible = "ti,am4372-timer","ti,am335x-timer";
2690 + reg = <0x48048000 0x400>;
2691 + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
2692 + ti,timer-pwm;
2693 + ti,hwmods = "timer6";
2694 + clocks = <&timer6_fck>;
2695 + clock-names = "fck";
2696 + status = "disabled";
2697 + };
2698 +
2699 + timer7: timer@4804a000 {
2700 + compatible = "ti,am4372-timer","ti,am335x-timer";
2701 + reg = <0x4804a000 0x400>;
2702 + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2703 + ti,timer-pwm;
2704 + ti,hwmods = "timer7";
2705 + clocks = <&timer7_fck>;
2706 + clock-names = "fck";
2707 + status = "disabled";
2708 + };
2709 +
2710 + timer8: timer@481c1000 {
2711 + compatible = "ti,am4372-timer","ti,am335x-timer";
2712 + reg = <0x481c1000 0x400>;
2713 + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2714 + ti,hwmods = "timer8";
2715 + clocks = <&timer8_fck>;
2716 + clock-names = "fck";
2717 + status = "disabled";
2718 + };
2719 +
2720 + timer9: timer@4833d000 {
2721 + compatible = "ti,am4372-timer","ti,am335x-timer";
2722 + reg = <0x4833d000 0x400>;
2723 + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
2724 + ti,hwmods = "timer9";
2725 + clocks = <&timer9_fck>;
2726 + clock-names = "fck";
2727 + status = "disabled";
2728 + };
2729 +
2730 + timer10: timer@4833f000 {
2731 + compatible = "ti,am4372-timer","ti,am335x-timer";
2732 + reg = <0x4833f000 0x400>;
2733 + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2734 + ti,hwmods = "timer10";
2735 + clocks = <&timer10_fck>;
2736 + clock-names = "fck";
2737 + status = "disabled";
2738 + };
2739 +
2740 + timer11: timer@48341000 {
2741 + compatible = "ti,am4372-timer","ti,am335x-timer";
2742 + reg = <0x48341000 0x400>;
2743 + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
2744 + ti,hwmods = "timer11";
2745 + clocks = <&timer11_fck>;
2746 + clock-names = "fck";
2747 + status = "disabled";
2748 };
2749
2750 counter32k: counter@44e86000 {
2751 compatible = "ti,am4372-counter32k","ti,omap-counter32k";
2752 reg = <0x44e86000 0x40>;
2753 + ti,hwmods = "counter_32k";
2754 + clocks = <&synctimer_32kclk>;
2755 + clock-names = "fck";
2756 + };
2757 +
2758 + rtc: rtc@44e3e000 {
2759 + compatible = "ti,am4372-rtc","ti,da830-rtc";
2760 + reg = <0x44e3e000 0x1000>;
2761 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
2762 + GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
2763 + ti,hwmods = "rtc";
2764 + clocks = <&clk_32768_ck>;
2765 + clock-names = "fck";
2766 + status = "disabled";
2767 + };
2768 +
2769 + wdt@44e35000 {
2770 + compatible = "ti,am4372-wdt","ti,omap3-wdt";
2771 + reg = <0x44e35000 0x1000>;
2772 + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
2773 + ti,hwmods = "wd_timer2";
2774 + clocks = <&wdt1_fck>;
2775 + clock-names = "fck";
2776 + };
2777 +
2778 + gpio0: gpio@44e07000 {
2779 + compatible = "ti,am4372-gpio","ti,omap4-gpio";
2780 + reg = <0x44e07000 0x1000>;
2781 + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2782 + gpio-controller;
2783 + #gpio-cells = <2>;
2784 + interrupt-controller;
2785 + #interrupt-cells = <2>;
2786 + ti,hwmods = "gpio1";
2787 + clocks = <&sys_clkin_ck>, <&gpio0_dbclk>;
2788 + clock-names = "fck", "dbclk";
2789 + status = "disabled";
2790 + };
2791 +
2792 + gpio1: gpio@4804c000 {
2793 + compatible = "ti,am4372-gpio","ti,omap4-gpio";
2794 + reg = <0x4804c000 0x1000>;
2795 + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2796 + gpio-controller;
2797 + #gpio-cells = <2>;
2798 + interrupt-controller;
2799 + #interrupt-cells = <2>;
2800 + ti,hwmods = "gpio2";
2801 + clocks = <&l4ls_gclk>, <&gpio1_dbclk>;
2802 + clock-names = "fck", "dbclk";
2803 + status = "disabled";
2804 + };
2805 +
2806 + gpio2: gpio@481ac000 {
2807 + compatible = "ti,am4372-gpio","ti,omap4-gpio";
2808 + reg = <0x481ac000 0x1000>;
2809 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
2810 + gpio-controller;
2811 + #gpio-cells = <2>;
2812 + interrupt-controller;
2813 + #interrupt-cells = <2>;
2814 + ti,hwmods = "gpio3";
2815 + clocks = <&l4ls_gclk>, <&gpio2_dbclk>;
2816 + clock-names = "fck", "dbclk";
2817 + status = "disabled";
2818 + };
2819 +
2820 + gpio3: gpio@481ae000 {
2821 + compatible = "ti,am4372-gpio","ti,omap4-gpio";
2822 + reg = <0x481ae000 0x1000>;
2823 + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
2824 + gpio-controller;
2825 + #gpio-cells = <2>;
2826 + interrupt-controller;
2827 + #interrupt-cells = <2>;
2828 + ti,hwmods = "gpio4";
2829 + clocks = <&l4ls_gclk>, <&gpio3_dbclk>;
2830 + clock-names = "fck", "dbclk";
2831 + status = "disabled";
2832 + };
2833 +
2834 + gpio4: gpio@48320000 {
2835 + compatible = "ti,am4372-gpio","ti,omap4-gpio";
2836 + reg = <0x48320000 0x1000>;
2837 + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2838 + gpio-controller;
2839 + #gpio-cells = <2>;
2840 + interrupt-controller;
2841 + #interrupt-cells = <2>;
2842 + ti,hwmods = "gpio5";
2843 + clocks = <&l4ls_gclk>, <&gpio4_dbclk>;
2844 + clock-names = "fck", "dbclk";
2845 + status = "disabled";
2846 + };
2847 +
2848 + gpio5: gpio@48322000 {
2849 + compatible = "ti,am4372-gpio","ti,omap4-gpio";
2850 + reg = <0x48322000 0x1000>;
2851 + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2852 + gpio-controller;
2853 + #gpio-cells = <2>;
2854 + interrupt-controller;
2855 + #interrupt-cells = <2>;
2856 + ti,hwmods = "gpio6";
2857 + clocks = <&l4ls_gclk>, <&gpio5_dbclk>;
2858 + clock-names = "fck", "dbclk";
2859 + status = "disabled";
2860 + };
2861 +
2862 + i2c0: i2c@44e0b000 {
2863 + compatible = "ti,am4372-i2c","ti,omap4-i2c";
2864 + reg = <0x44e0b000 0x1000>;
2865 + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
2866 + ti,hwmods = "i2c1";
2867 + clocks = <&dpll_per_m2_div4_wkupdm_ck>;
2868 + clock-names = "fck";
2869 + #address-cells = <1>;
2870 + #size-cells = <0>;
2871 + status = "disabled";
2872 +
2873 + tps: tps@24 {
2874 + reg = <0x24>;
2875 + };
2876 + };
2877 +
2878 + i2c1: i2c@4802a000 {
2879 + compatible = "ti,am4372-i2c","ti,omap4-i2c";
2880 + reg = <0x4802a000 0x1000>;
2881 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
2882 + ti,hwmods = "i2c2";
2883 + clocks = <&dpll_per_m2_div4_ck>;
2884 + clock-names = "fck";
2885 + #address-cells = <1>;
2886 + #size-cells = <0>;
2887 + status = "disabled";
2888 + };
2889 +
2890 + i2c2: i2c@4819c000 {
2891 + compatible = "ti,am4372-i2c","ti,omap4-i2c";
2892 + reg = <0x4819c000 0x1000>;
2893 + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
2894 + ti,hwmods = "i2c3";
2895 + clocks = <&dpll_per_m2_div4_ck>;
2896 + clock-names = "fck";
2897 + #address-cells = <1>;
2898 + #size-cells = <0>;
2899 + status = "disabled";
2900 + };
2901 +
2902 + spi0: spi@48030000 {
2903 + compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
2904 + reg = <0x48030000 0x400>;
2905 + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
2906 + ti,hwmods = "spi0";
2907 + clocks = <&dpll_per_m2_div4_ck>;
2908 + clock-names = "fck";
2909 + #address-cells = <1>;
2910 + #size-cells = <0>;
2911 + status = "disabled";
2912 };
2913 +
2914 + mmc1: mmc@48060000 {
2915 + compatible = "ti,omap4-hsmmc";
2916 + reg = <0x48060000 0x1000>;
2917 + ti,hwmods = "mmc1";
2918 + clocks = <&mmc_clk>, <&clkdiv32k_ick>;
2919 + clock-names = "fck", "mmchsdb_fck";
2920 + ti,dual-volt;
2921 + ti,needs-special-reset;
2922 + dmas = <&edma 24
2923 + &edma 25>;
2924 + dma-names = "tx", "rx";
2925 + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
2926 + status = "disabled";
2927 + };
2928 +
2929 + mmc2: mmc@481d8000 {
2930 + compatible = "ti,omap4-hsmmc";
2931 + reg = <0x481d8000 0x1000>;
2932 + ti,hwmods = "mmc2";
2933 + clocks = <&mmc_clk>, <&clkdiv32k_ick>;
2934 + clock-names = "fck", "mmchsdb_fck";
2935 + ti,needs-special-reset;
2936 + dmas = <&edma 2
2937 + &edma 3>;
2938 + dma-names = "tx", "rx";
2939 + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
2940 + status = "disabled";
2941 + };
2942 +
2943 + mmc3: mmc@47810000 {
2944 + compatible = "ti,omap4-hsmmc";
2945 + reg = <0x47810000 0x1000>;
2946 + ti,hwmods = "mmc3";
2947 + clocks = <&mmc_clk>, <&clkdiv32k_ick>;
2948 + clock-names = "fck", "mmchsdb_fck";
2949 + ti,needs-special-reset;
2950 + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
2951 + status = "disabled";
2952 + };
2953 +
2954 + spi1: spi@481a0000 {
2955 + compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
2956 + reg = <0x481a0000 0x400>;
2957 + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
2958 + ti,hwmods = "spi1";
2959 + clocks = <&dpll_per_m2_div4_ck>;
2960 + clock-names = "fck";
2961 + #address-cells = <1>;
2962 + #size-cells = <0>;
2963 + status = "disabled";
2964 + };
2965 +
2966 + spi2: spi@481a2000 {
2967 + compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
2968 + reg = <0x481a2000 0x400>;
2969 + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
2970 + ti,hwmods = "spi2";
2971 + clocks = <&dpll_per_m2_div4_ck>;
2972 + clock-names = "fck";
2973 + #address-cells = <1>;
2974 + #size-cells = <0>;
2975 + status = "disabled";
2976 + };
2977 +
2978 + spi3: spi@481a4000 {
2979 + compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
2980 + reg = <0x481a4000 0x400>;
2981 + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
2982 + ti,hwmods = "spi3";
2983 + clocks = <&dpll_per_m2_div4_ck>;
2984 + clock-names = "fck";
2985 + #address-cells = <1>;
2986 + #size-cells = <0>;
2987 + status = "disabled";
2988 + };
2989 +
2990 + spi4: spi@48345000 {
2991 + compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
2992 + reg = <0x48345000 0x400>;
2993 + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
2994 + ti,hwmods = "spi4";
2995 + clocks = <&dpll_per_m2_div4_ck>;
2996 + clock-names = "fck";
2997 + #address-cells = <1>;
2998 + #size-cells = <0>;
2999 + status = "disabled";
3000 + };
3001 +
3002 + mac: ethernet@4a100000 {
3003 + compatible = "ti,am4372-cpsw","ti,cpsw";
3004 + reg = <0x4a100000 0x800
3005 + 0x4a101200 0x100>;
3006 + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
3007 + GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
3008 + GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
3009 + GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
3010 + #address-cells = <1>;
3011 + #size-cells = <1>;
3012 + ti,hwmods = "cpgmac0";
3013 + clocks = <&cpsw_125mhz_gclk>;
3014 + clock-names = "fck";
3015 + cpdma_channels = <8>;
3016 + ale_entries = <1024>;
3017 + bd_ram_size = <0x2000>;
3018 + no_bd_ram = <0>;
3019 + rx_descs = <64>;
3020 + mac_control = <0x20>;
3021 + slaves = <2>;
3022 + active_slave = <0>;
3023 + cpts_clock_mult = <0x80000000>;
3024 + cpts_clock_shift = <29>;
3025 + ranges;
3026 + status = "disabled";
3027 +
3028 + davinci_mdio: mdio@4a101000 {
3029 + compatible = "ti,am4372-mdio","ti,davinci_mdio";
3030 + reg = <0x4a101000 0x100>;
3031 + #address-cells = <1>;
3032 + #size-cells = <0>;
3033 + ti,hwmods = "davinci_mdio";
3034 + clocks = <&cpsw_125mhz_gclk>;
3035 + clock-names = "fck";
3036 + bus_freq = <1000000>;
3037 + status = "disabled";
3038 + };
3039 +
3040 + cpsw_emac0: slave@4a100200 {
3041 + /* Filled in by U-Boot */
3042 + mac-address = [ 00 00 00 00 00 00 ];
3043 + };
3044 +
3045 + cpsw_emac1: slave@4a100300 {
3046 + /* Filled in by U-Boot */
3047 + mac-address = [ 00 00 00 00 00 00 ];
3048 + };
3049 +
3050 + phy_sel: cpsw-phy-sel@44e10650 {
3051 + compatible = "ti,am3352-cpsw-phy-sel";
3052 + reg= <0x44e10650 0x4>;
3053 + reg-names = "gmii-sel";
3054 + };
3055 + };
3056 +
3057 + epwmss0: epwmss@48300000 {
3058 + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
3059 + reg = <0x48300000 0x10>;
3060 + #address-cells = <1>;
3061 + #size-cells = <1>;
3062 + ranges;
3063 + ti,hwmods = "epwmss0";
3064 + clocks = <&l4ls_gclk>;
3065 + clock-names = "fck";
3066 + status = "disabled";
3067 +
3068 + ecap0: ecap@48300100 {
3069 + compatible = "ti,am4372-ecap","ti,am33xx-ecap";
3070 + reg = <0x48300100 0x80>;
3071 + ti,hwmods = "ecap0";
3072 + clocks = <&l4ls_gclk>;
3073 + clock-names = "fck";
3074 + status = "disabled";
3075 + };
3076 +
3077 + ehrpwm0: ehrpwm@48300200 {
3078 + compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
3079 + reg = <0x48300200 0x80>;
3080 + ti,hwmods = "ehrpwm0";
3081 + clocks = <&l4ls_gclk>;
3082 + clock-names = "fck";
3083 + status = "disabled";
3084 + };
3085 + };
3086 +
3087 + epwmss1: epwmss@48302000 {
3088 + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
3089 + reg = <0x48302000 0x10>;
3090 + #address-cells = <1>;
3091 + #size-cells = <1>;
3092 + ranges;
3093 + ti,hwmods = "epwmss1";
3094 + clocks = <&l4ls_gclk>;
3095 + clock-names = "fck";
3096 + status = "disabled";
3097 +
3098 + ecap1: ecap@48302100 {
3099 + compatible = "ti,am4372-ecap","ti,am33xx-ecap";
3100 + reg = <0x48302100 0x80>;
3101 + ti,hwmods = "ecap1";
3102 + clocks = <&l4ls_gclk>;
3103 + clock-names = "fck";
3104 + status = "disabled";
3105 + };
3106 +
3107 + ehrpwm1: ehrpwm@48302200 {
3108 + compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
3109 + reg = <0x48302200 0x80>;
3110 + ti,hwmods = "ehrpwm1";
3111 + clocks = <&l4ls_gclk>;
3112 + clock-names = "fck";
3113 + status = "disabled";
3114 + };
3115 + };
3116 +
3117 + epwmss2: epwmss@48304000 {
3118 + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
3119 + reg = <0x48304000 0x10>;
3120 + #address-cells = <1>;
3121 + #size-cells = <1>;
3122 + ranges;
3123 + ti,hwmods = "epwmss2";
3124 + clocks = <&l4ls_gclk>;
3125 + clock-names = "fck";
3126 + status = "disabled";
3127 +
3128 + ecap2: ecap@48304100 {
3129 + compatible = "ti,am4372-ecap","ti,am33xx-ecap";
3130 + reg = <0x48304100 0x80>;
3131 + ti,hwmods = "ecap2";
3132 + clocks = <&l4ls_gclk>;
3133 + clock-names = "fck";
3134 + status = "disabled";
3135 + };
3136 +
3137 + ehrpwm2: ehrpwm@48304200 {
3138 + compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
3139 + reg = <0x48304200 0x80>;
3140 + ti,hwmods = "ehrpwm2";
3141 + clocks = <&l4ls_gclk>;
3142 + clock-names = "fck";
3143 + status = "disabled";
3144 + };
3145 + };
3146 +
3147 + epwmss3: epwmss@48306000 {
3148 + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
3149 + reg = <0x48306000 0x10>;
3150 + #address-cells = <1>;
3151 + #size-cells = <1>;
3152 + ranges;
3153 + ti,hwmods = "epwmss3";
3154 + clocks = <&l4ls_gclk>;
3155 + clock-names = "fck";
3156 + status = "disabled";
3157 +
3158 + ehrpwm3: ehrpwm@48306200 {
3159 + compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
3160 + reg = <0x48306200 0x80>;
3161 + ti,hwmods = "ehrpwm3";
3162 + clocks = <&l4ls_gclk>;
3163 + clock-names = "fck";
3164 + status = "disabled";
3165 + };
3166 + };
3167 +
3168 + epwmss4: epwmss@48308000 {
3169 + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
3170 + reg = <0x48308000 0x10>;
3171 + #address-cells = <1>;
3172 + #size-cells = <1>;
3173 + ranges;
3174 + ti,hwmods = "epwmss4";
3175 + clocks = <&l4ls_gclk>;
3176 + clock-names = "fck";
3177 + status = "disabled";
3178 +
3179 + ehrpwm4: ehrpwm@48308200 {
3180 + compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
3181 + reg = <0x48308200 0x80>;
3182 + ti,hwmods = "ehrpwm4";
3183 + clocks = <&l4ls_gclk>;
3184 + clock-names = "fck";
3185 + status = "disabled";
3186 + };
3187 + };
3188 +
3189 + epwmss5: epwmss@4830a000 {
3190 + compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
3191 + reg = <0x4830a000 0x10>;
3192 + #address-cells = <1>;
3193 + #size-cells = <1>;
3194 + ranges;
3195 + ti,hwmods = "epwmss5";
3196 + clocks = <&l4ls_gclk>;
3197 + clock-names = "fck";
3198 + status = "disabled";
3199 +
3200 + ehrpwm5: ehrpwm@4830a200 {
3201 + compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
3202 + reg = <0x4830a200 0x80>;
3203 + ti,hwmods = "ehrpwm5";
3204 + clocks = <&l4ls_gclk>;
3205 + clock-names = "fck";
3206 + status = "disabled";
3207 + };
3208 + };
3209 +
3210 + wkup_m3: wkup_m3@44d00000 {
3211 + compatible = "ti,am4372-wkup-m3","ti,am3353-wkup-m3";
3212 + reg = <0x44d00000 0x4000 /* M3 UMEM */
3213 + 0x44d80000 0x2000>; /* M3 DMEM */
3214 + ti,hwmods = "wkup_m3";
3215 + clocks = <&sys_clkin_ck>;
3216 + clock-names = "fck";
3217 + status = "disabled";
3218 + };
3219 +
3220 + tscadc: tscadc@44e0d000 {
3221 + compatible = "ti,am4372-tscadc","ti,am3359-tscadc";
3222 + reg = <0x44e0d000 0x1000>;
3223 + ti,hwmods = "adc_tsc";
3224 + clocks = <&adc_tsc_fck>;
3225 + clock-names = "fck";
3226 + status = "disabled";
3227 + };
3228 +
3229 + ocmcram: ocmcram@40300000 {
3230 + compatible = "ti,am4372-ocmcram","ti,am3352-ocmcram";
3231 + reg = <0x40300000 0x40000>;
3232 + ti,hwmods = "ocmcram";
3233 + clocks = <&l3_gclk>;
3234 + clock-names = "fck";
3235 + status = "disabled";
3236 + };
3237 +
3238 + dcan0: d_can@481cc000 {
3239 + compatible = "bosch,d_can";
3240 + ti,hwmods = "d_can0";
3241 + clocks = <&dcan0_fck>;
3242 + clock-names = "fck";
3243 + reg = <0x481cc000 0x2000
3244 + 0x44e10644 0x4>;
3245 + status = "disabled";
3246 + };
3247 +
3248 + dcan1: d_can@481d0000 {
3249 + compatible = "bosch,d_can";
3250 + ti,hwmods = "d_can1";
3251 + clocks = <&dcan1_fck>;
3252 + clock-names = "fck";
3253 + reg = <0x481d0000 0x2000
3254 + 0x44e10644 0x4>;
3255 + status = "disabled";
3256 + };
3257 +
3258 + elm: elm@48080000 {
3259 + compatible = "ti,am4372-elm","ti,am3352-elm";
3260 + reg = <0x48080000 0x2000>;
3261 + ti,hwmods = "elm";
3262 + clocks = <&l4ls_gclk>;
3263 + clock-names = "fck";
3264 + status = "disabled";
3265 + };
3266 +
3267 + gpmc: gpmc@50000000 {
3268 + compatible = "ti,am4372-gpmc","ti,am3352-gpmc";
3269 + ti,hwmods = "gpmc";
3270 + clocks = <&l3s_gclk>;
3271 + clock-names = "fck";
3272 + reg = <0x50000000 0x2000>;
3273 + status = "disabled";
3274 + };
3275 +
3276 + prcm: prcm@44df0000 {
3277 + compatible = "ti,am4372-prcm";
3278 + reg = <0x44df0000 0xa000>;
3279 + #reset-cells = <1>;
3280 + };
3281 +
3282 + rng: rng@48310000 {
3283 + compatible = "ti,omap4-rng";
3284 + ti,hwmods = "rng";
3285 + reg = <0x48310000 0x2000>;
3286 + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
3287 + clocks = <&rng_fck>;
3288 + clock-names = "fck";
3289 + };
3290 +
3291 + sham: sham@53100000 {
3292 + compatible = "ti,omap5-sham";
3293 + ti,hwmods = "sham";
3294 + reg = <0x53100000 0x300>;
3295 + dmas = <&edma 36>;
3296 + dma-names = "rx";
3297 + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
3298 + clocks = <&l3_gclk>;
3299 + clock-names = "fck";
3300 + };
3301 +
3302 + aes: aes@53501000 {
3303 + compatible = "ti,omap4-aes";
3304 + ti,hwmods = "aes";
3305 + reg = <0x53501000 0xa0>;
3306 + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
3307 + dmas = <&edma 6
3308 + &edma 5>;
3309 + dma-names = "tx", "rx";
3310 + clocks = <&aes0_fck>;
3311 + clock-names = "fck";
3312 + };
3313 +
3314 + des: des@53701000 {
3315 + compatible = "ti,omap4-des";
3316 + ti,hwmods = "des";
3317 + reg = <0x53701000 0xa0>;
3318 + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
3319 + dmas = <&edma 34
3320 + &edma 33>;
3321 + dma-names = "tx", "rx";
3322 + clocks = <&l3_gclk>;
3323 + clock-names = "fck";
3324 + };
3325 +
3326 + am43xx_control_usb2phy1: control-phy@44e10620 {
3327 + compatible = "ti,control-phy-am437usb2";
3328 + reg = <0x44e10620 0x4>;
3329 + reg-names = "power";
3330 + };
3331 +
3332 + am43xx_control_usb2phy2: control-phy@0x44e10628 {
3333 + compatible = "ti,control-phy-am437usb2";
3334 + reg = <0x44e10628 0x4>;
3335 + reg-names = "power";
3336 + };
3337 +
3338 + ocp2scp0: ocp2scp@483a8000 {
3339 + compatible = "ti,omap-ocp2scp";
3340 + #address-cells = <1>;
3341 + #size-cells = <1>;
3342 + ranges;
3343 + ti,hwmods = "ocp2scp0";
3344 +
3345 + usb2_phy1: usb2phy1@483a8000 {
3346 + compatible = "ti,am437x-usb2";
3347 + reg = <0x483a8000 0x8000>;
3348 + ctrl-module = <&am43xx_control_usb2phy1>;
3349 + clocks = <&clk_32768_ck>,
3350 + <&usb_otg_ss0_refclk960m>;
3351 + clock-names = "wkupclk",
3352 + "refclk";
3353 + #phy-cells = <0>;
3354 + };
3355 +
3356 + };
3357 +
3358 + ocp2scp1: ocp2scp@483e8000 {
3359 + compatible = "ti,omap-ocp2scp";
3360 + #address-cells = <1>;
3361 + #size-cells = <1>;
3362 + ranges;
3363 + ti,hwmods = "ocp2scp1";
3364 +
3365 + usb2_phy2: usb2phy2@483e8000 {
3366 + compatible = "ti,am437x-usb2";
3367 + reg = <0x483e8000 0x8000>;
3368 + ctrl-module = <&am43xx_control_usb2phy2>;
3369 + clocks = <&clk_32768_ck>,
3370 + <&usb_otg_ss1_refclk960m>;
3371 + clock-names = "wkupclk",
3372 + "refclk";
3373 + #phy-cells = <0>;
3374 + };
3375 +
3376 + };
3377 +
3378 + dwc3_1: omap_dwc3_1@48380000 {
3379 + compatible = "ti,am437x-dwc3";
3380 + ti,hwmods = "usb_otg_ss0";
3381 + reg = <0x48380000 0x10000>;
3382 + interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
3383 + #address-cells = <1>;
3384 + #size-cells = <1>;
3385 + utmi-mode = <1>;
3386 + ranges;
3387 + usb1: usb@48390000 {
3388 + compatible = "synopsys,dwc3";
3389 + reg = <0x48390000 0x17000>;
3390 + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
3391 + phys = <&usb2_phy1>;
3392 + phy-names = "usb2-phy";
3393 + maximum-speed = "high-speed";
3394 + dr_mode = "peripheral";
3395 + };
3396 + };
3397 +
3398 + dwc3_2: omap_dwc3_2@483c0000 {
3399 + compatible = "ti,am437x-dwc3";
3400 + ti,hwmods = "usb_otg_ss1";
3401 + reg = <0x483c0000 0x10000>;
3402 + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
3403 + #address-cells = <1>;
3404 + #size-cells = <1>;
3405 + utmi-mode = <1>;
3406 + ranges;
3407 + usb2: usb@483d0000 {
3408 + compatible = "synopsys,dwc3";
3409 + reg = <0x483d0000 0x17000>;
3410 + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3411 + phys = <&usb2_phy2>;
3412 + phy-names = "usb2-phy";
3413 + maximum-speed = "high-speed";
3414 + dr_mode = "host";
3415 + };
3416 + };
3417 +
3418 + dss: dss@4832A000 {
3419 + compatible = "ti,omap3-dss", "simple-bus";
3420 + reg = <0x4832A000 0x200>;
3421 + ti,hwmods = "dss_core";
3422 + #address-cells = <1>;
3423 + #size-cells = <1>;
3424 + ranges;
3425 +
3426 + dispc@4832A400 {
3427 + compatible = "ti,omap3-dispc";
3428 + reg = <0x4832A400 0x400>;
3429 + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
3430 + ti,hwmods = "dss_dispc";
3431 + };
3432 +
3433 + dpi: encoder@0 {
3434 + compatible = "ti,omap3-dpi";
3435 + };
3436 +
3437 + rfbi: rfbi@4832A800 {
3438 + compatible = "ti,omap3-rfbi";
3439 + reg = <0x4832A800 0x100>;
3440 + ti,hwmods = "dss_rfbi";
3441 + };
3442 +
3443 + };
3444 +
3445 };
3446 +
3447 + clocks {
3448 + #address-cells = <1>;
3449 + #size-cells = <1>;
3450 + ranges;
3451 + /include/ "am43xx-clocks.dtsi"
3452 + };
3453 +
3454 };
3455 +
3456 +/include/ "tps65218.dtsi"
3457 --- /dev/null
3458 +++ b/arch/arm/boot/dts/am437x-gp-evm.dts
3459 @@ -0,0 +1,238 @@
3460 +/*
3461 + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3462 + *
3463 + * This program is free software; you can redistribute it and/or modify
3464 + * it under the terms of the GNU General Public License version 2 as
3465 + * published by the Free Software Foundation.
3466 + */
3467 +
3468 +/* AM437x GP EVM */
3469 +
3470 +/dts-v1/;
3471 +
3472 +#include "am43x-common-evm.dtsi"
3473 +#include <dt-bindings/pinctrl/am43xx.h>
3474 +
3475 +/ {
3476 + model = "TI AM437x gp EVM";
3477 + compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
3478 +
3479 + vmmcsd_fixed: fixedregulator-sd {
3480 + compatible = "regulator-fixed";
3481 + regulator-name = "vmmcsd_fixed";
3482 + regulator-min-microvolt = <3300000>;
3483 + regulator-max-microvolt = <3300000>;
3484 + enable-active-high;
3485 + };
3486 +
3487 + aliases {
3488 + display0 = &lcd0;
3489 + display1 = &hdmi0;
3490 + };
3491 +
3492 + lcd0: display@0 {
3493 + compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
3494 + video-source = <&dpi>;
3495 + data-lines = <24>;
3496 + gpios = <0 /* No Enable GPIO */
3497 + &gpio0 7 GPIO_ACTIVE_LOW>; /* LCD backlight GPIO */
3498 + activelow_backlight; /* LCD backlight is Active low */
3499 + panel-timing {
3500 + clock-frequency = <33000000>;
3501 + hactive = <800>;
3502 + vactive = <480>;
3503 + hfront-porch = <210>;
3504 + hback-porch = <16>;
3505 + hsync-len = <30>;
3506 + vback-porch = <10>;
3507 + vfront-porch = <22>;
3508 + vsync-len = <13>;
3509 + hsync-active = <0>;
3510 + vsync-active = <0>;
3511 + de-active = <1>;
3512 + pixelclk-active = <1>;
3513 + };
3514 + };
3515 +
3516 + hdmi0: connector@1 {
3517 + compatible = "ti,hdmi_connector";
3518 + video-source = <&sii9022>;
3519 + };
3520 +};
3521 +