+++ /dev/null
-From 127797e5cf8a036825007586b914b75897aba554 Mon Sep 17 00:00:00 2001
-From: Kurt Mahan <kmahan@freescale.com>
-Date: Wed, 31 Oct 2007 16:39:31 -0600
-Subject: [PATCH] Add Coldfire Support into existing headers.
-
-Modifications to the various M68k header files to add
-Coldfire processor support.
-
-LTIBName: mcfv4e-coldfire-headers
-Signed-off-by: Kurt Mahan <kmahan@freescale.com>
----
- include/asm-m68k/atomic.h | 23 ++-
- include/asm-m68k/bitops.h | 426 ++++++++++++++++++++++++++++++++++++++++
- include/asm-m68k/bootinfo.h | 13 ++
- include/asm-m68k/byteorder.h | 12 +-
- include/asm-m68k/cacheflush.h | 4 +
- include/asm-m68k/checksum.h | 10 +
- include/asm-m68k/delay.h | 26 +++
- include/asm-m68k/div64.h | 4 +
- include/asm-m68k/elf.h | 2 +-
- include/asm-m68k/fpu.h | 2 +
- include/asm-m68k/io.h | 26 +++-
- include/asm-m68k/irq.h | 5 +-
- include/asm-m68k/machdep.h | 7 +
- include/asm-m68k/mmu_context.h | 84 ++++++++-
- include/asm-m68k/page.h | 20 ++-
- include/asm-m68k/page_offset.h | 7 +-
- include/asm-m68k/pci.h | 99 ++++++----
- include/asm-m68k/pgalloc.h | 4 +-
- include/asm-m68k/pgtable.h | 15 ++
- include/asm-m68k/processor.h | 46 ++++-
- include/asm-m68k/ptrace.h | 11 +
- include/asm-m68k/raw_io.h | 58 ++++++
- include/asm-m68k/segment.h | 10 +
- include/asm-m68k/setup.h | 27 +++
- include/asm-m68k/signal.h | 5 +
- include/asm-m68k/string.h | 2 +
- include/asm-m68k/system.h | 17 ++-
- include/asm-m68k/thread_info.h | 1 +
- include/asm-m68k/tlbflush.h | 16 ++-
- include/asm-m68k/uaccess.h | 4 +
- 30 files changed, 925 insertions(+), 61 deletions(-)
-
---- a/include/asm-m68k/atomic.h
-+++ b/include/asm-m68k/atomic.h
-@@ -2,7 +2,7 @@
- #define __ARCH_M68K_ATOMIC__
-
-
--#include <asm/system.h>
-+#include <asm/system.h> /* local_irq_XXX() */
-
- /*
- * Atomic operations that C can't guarantee us. Useful for
-@@ -21,12 +21,20 @@ typedef struct { int counter; } atomic_t
-
- static inline void atomic_add(int i, atomic_t *v)
- {
-+#ifndef CONFIG_COLDFIRE
- __asm__ __volatile__("addl %1,%0" : "+m" (*v) : "id" (i));
-+#else
-+ __asm__ __volatile__("addl %1,%0" : "=m" (*v) : "d" (i), "m" (*v));
-+#endif
- }
-
- static inline void atomic_sub(int i, atomic_t *v)
- {
-+#ifndef CONFIG_COLDFIRE
- __asm__ __volatile__("subl %1,%0" : "+m" (*v) : "id" (i));
-+#else
-+ __asm__ __volatile__("subl %1,%0" : "=m" (*v) : "d" (i), "m" (*v));
-+#endif
- }
-
- static inline void atomic_inc(atomic_t *v)
-@@ -46,6 +54,14 @@ static inline int atomic_dec_and_test(at
- return c != 0;
- }
-
-+static __inline__ int atomic_dec_and_test_lt(volatile atomic_t *v)
-+{
-+ char c;
-+ __asm__ __volatile__("subql #1,%1; slt %0" : "=d" (c), "=m" (*v)
-+ : "m" (*v));
-+ return c != 0 ;
-+}
-+
- static inline int atomic_inc_and_test(atomic_t *v)
- {
- char c;
-@@ -156,7 +172,12 @@ static inline int atomic_sub_and_test(in
- static inline int atomic_add_negative(int i, atomic_t *v)
- {
- char c;
-+#ifndef CONFIG_COLDFIRE
- __asm__ __volatile__("addl %2,%1; smi %0" : "=d" (c), "+m" (*v): "g" (i));
-+#else
-+ __asm__ __volatile__("addl %2,%1; smi %0" : "=d" (c), "=m" (*v)
-+ : "d" (i) , "m" (*v));
-+#endif
- return c != 0;
- }
-
---- a/include/asm-m68k/bitops.h
-+++ b/include/asm-m68k/bitops.h
-@@ -19,6 +19,7 @@
- *
- * They use the standard big-endian m680x0 bit ordering.
- */
-+#ifndef CONFIG_COLDFIRE
-
- #define test_and_set_bit(nr,vaddr) \
- (__builtin_constant_p(nr) ? \
-@@ -457,4 +458,429 @@ static inline int ext2_find_next_bit(con
-
- #endif /* __KERNEL__ */
-
-+#else /* CONFIG_COLDFIRE */
-+
-+#define test_and_set_bit(nr,vaddr) \
-+ (__builtin_constant_p(nr) ? \
-+ __constant_coldfire_test_and_set_bit(nr, vaddr) : \
-+ __generic_coldfire_test_and_set_bit(nr, vaddr))
-+
-+
-+static __inline__ int __constant_coldfire_test_and_set_bit(int nr,
-+ volatile void *vaddr)
-+{
-+ char retval;
-+ volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
-+
-+ __asm__ __volatile__ ("bset %2,%1; sne %0"
-+ : "=d" (retval), "+QUd" (*p)
-+ : "di" (nr & 7));
-+ return retval;
-+}
-+
-+static __inline__ int __generic_coldfire_test_and_set_bit(int nr,
-+ volatile void *vaddr)
-+{
-+ char retval;
-+
-+ __asm__ __volatile__ ("bset %2,%1; sne %0"
-+ : "=d" (retval), "=m" (((volatile char *)vaddr)[(nr^31) >> 3])
-+ : "d" (nr)
-+ : "memory");
-+ return retval;
-+}
-+#define __test_and_set_bit(nr, vaddr) test_and_set_bit(nr, vaddr)
-+
-+#define set_bit(nr,vaddr) \
-+ (__builtin_constant_p(nr) ? \
-+ __constant_coldfire_set_bit(nr, vaddr) : \
-+ __generic_coldfire_set_bit(nr, vaddr))
-+
-+static __inline__ void __constant_coldfire_set_bit(int nr,
-+ volatile void *vaddr)
-+{
-+ volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
-+ __asm__ __volatile__ ("bset %1,%0"
-+ : "+QUd" (*p) : "di" (nr & 7));
-+}
-+
-+static __inline__ void __generic_coldfire_set_bit(int nr, volatile void *vaddr)
-+{
-+ __asm__ __volatile__ ("bset %1,%0"
-+ : "=m" (((volatile char *)vaddr)[(nr^31) >> 3])
-+ : "d" (nr)
-+ : "memory");
-+}
-+#define __set_bit(nr, vaddr) set_bit(nr, vaddr)
-+
-+#define test_and_clear_bit(nr, vaddr) \
-+ (__builtin_constant_p(nr) ? \
-+ __constant_coldfire_test_and_clear_bit(nr, vaddr) : \
-+ __generic_coldfire_test_and_clear_bit(nr, vaddr))
-+
-+static __inline__ int __constant_coldfire_test_and_clear_bit(int nr,
-+ volatile void *vaddr)
-+{
-+ char retval;
-+ volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
-+
-+ __asm__ __volatile__ ("bclr %2,%1; sne %0"
-+ : "=d" (retval), "+QUd" (*p)
-+ : "id" (nr & 7));
-+
-+ return retval;
-+}
-+
-+static __inline__ int __generic_coldfire_test_and_clear_bit(int nr,
-+ volatile void *vaddr)
-+{
-+ char retval;
-+
-+ __asm__ __volatile__ ("bclr %2,%1; sne %0"
-+ : "=d" (retval), "=m" (((volatile char *)vaddr)[(nr^31) >> 3])
-+ : "d" (nr & 7)
-+ : "memory");
-+
-+ return retval;
-+}
-+#define __test_and_clear_bit(nr, vaddr) test_and_clear_bit(nr, vaddr)
-+
-+/*
-+ * clear_bit() doesn't provide any barrier for the compiler.
-+ */
-+#define smp_mb__before_clear_bit() barrier()
-+#define smp_mb__after_clear_bit() barrier()
-+
-+#define clear_bit(nr,vaddr) \
-+ (__builtin_constant_p(nr) ? \
-+ __constant_coldfire_clear_bit(nr, vaddr) : \
-+ __generic_coldfire_clear_bit(nr, vaddr))
-+
-+static __inline__ void __constant_coldfire_clear_bit(int nr,
-+ volatile void *vaddr)
-+{
-+ volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
-+ __asm__ __volatile__ ("bclr %1,%0"
-+ : "+QUd" (*p) : "id" (nr & 7));
-+}
-+
-+static __inline__ void __generic_coldfire_clear_bit(int nr,
-+ volatile void *vaddr)
-+{
-+ __asm__ __volatile__ ("bclr %1,%0"
-+ : "=m" (((volatile char *)vaddr)[(nr^31) >> 3])
-+ : "d" (nr)
-+ : "memory");
-+}
-+#define __clear_bit(nr, vaddr) clear_bit(nr, vaddr)
-+
-+#define test_and_change_bit(nr, vaddr) \
-+ (__builtin_constant_p(nr) ? \
-+ __constant_coldfire_test_and_change_bit(nr, vaddr) : \
-+ __generic_coldfire_test_and_change_bit(nr, vaddr))
-+
-+static __inline__ int __constant_coldfire_test_and_change_bit(int nr,
-+ volatile void *vaddr)
-+{
-+ char retval;
-+ volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
-+
-+ __asm__ __volatile__ ("bchg %2,%1; sne %0"
-+ : "=d" (retval), "+QUd" (*p)
-+ : "id" (nr & 7));
-+
-+ return retval;
-+}
-+
-+static __inline__ int __generic_coldfire_test_and_change_bit(int nr,
-+ volatile void *vaddr)
-+{
-+ char retval;
-+
-+ __asm__ __volatile__ ("bchg %2,%1; sne %0"
-+ : "=d" (retval), "=m" (((volatile char *)vaddr)[(nr^31) >> 3])
-+ : "id" (nr)
-+ : "memory");
-+
-+ return retval;
-+}
-+#define __test_and_change_bit(nr, vaddr) test_and_change_bit(nr, vaddr)
-+#define __change_bit(nr, vaddr) change_bit(nr, vaddr)
-+
-+#define change_bit(nr,vaddr) \
-+ (__builtin_constant_p(nr) ? \
-+ __constant_coldfire_change_bit(nr, vaddr) : \
-+ __generic_coldfire_change_bit(nr, vaddr))
-+
-+static __inline__ void __constant_coldfire_change_bit(int nr,
-+ volatile void *vaddr)
-+{
-+ volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
-+ __asm__ __volatile__ ("bchg %1,%0"
-+ : "+QUd" (*p) : "id" (nr & 7));
-+}
-+
-+static __inline__ void __generic_coldfire_change_bit(int nr,
-+ volatile void *vaddr)
-+{
-+ __asm__ __volatile__ ("bchg %1,%0"
-+ : "=m" (((volatile char *)vaddr)[(nr^31) >> 3])
-+ : "d" (nr)
-+ : "memory");
-+}
-+
-+static inline int test_bit(int nr, const unsigned long *vaddr)
-+{
-+ return (vaddr[nr >> 5] & (1UL << (nr & 31))) != 0;
-+}
-+
-+static __inline__ unsigned long ffz(unsigned long word)
-+{
-+ unsigned long result = 0;
-+
-+ while (word & 1) {
-+ result++;
-+ word >>= 1;
-+ }
-+ return result;
-+}
-+
-+/* find_next_zero_bit() finds the first zero bit in a bit string of length
-+ * 'size' bits, starting the search at bit 'offset'. This is largely based
-+ * on Linus's ALPHA routines.
-+ */
-+static __inline__ unsigned long find_next_zero_bit(void *addr,
-+ unsigned long size, unsigned long offset)
-+{
-+ unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
-+ unsigned long result = offset & ~31UL;
-+ unsigned long tmp;
-+
-+ if (offset >= size)
-+ return size;
-+ size -= result;
-+ offset &= 31UL;
-+ if (offset) {
-+ tmp = *(p++);
-+ tmp |= ~0UL >> (32-offset);
-+ if (size < 32)
-+ goto found_first;
-+ if (~tmp)
-+ goto found_middle;
-+ size -= 32;
-+ result += 32;
-+ }
-+ while (size & ~31UL) {
-+ tmp = *(p++);
-+ if (~tmp)
-+ goto found_middle;
-+ result += 32;
-+ size -= 32;
-+ }
-+ if (!size)
-+ return result;
-+ tmp = *p;
-+
-+found_first:
-+ tmp |= ~0UL >> size;
-+found_middle:
-+ return result + ffz(tmp);
-+}
-+
-+#define find_first_zero_bit(addr, size) find_next_zero_bit(((void *)addr), \
-+ (size), 0)
-+
-+/* Ported from included/linux/bitops.h */
-+static __inline__ int ffs(int x)
-+{
-+ int r = 1;
-+
-+ if (!x)
-+ return 0;
-+ if (!(x & 0xffff)) {
-+ x >>= 16;
-+ r += 16;
-+ }
-+ if (!(x & 0xff)) {
-+ x >>= 8;
-+ r += 8;
-+ }
-+ if (!(x & 0xf)) {
-+ x >>= 4;
-+ r += 4;
-+ }
-+ if (!(x & 3)) {
-+ x >>= 2;
-+ r += 2;
-+ }
-+ if (!(x & 1)) {
-+ x >>= 1;
-+ r += 1;
-+ }
-+ return r;
-+}
-+#define __ffs(x) (ffs(x) - 1)
-+
-+/* find_next_bit - find the next set bit in a memory region
-+ * (from asm-ppc/bitops.h)
-+ */
-+static __inline__ unsigned long find_next_bit(const unsigned long *addr,
-+ unsigned long size, unsigned long offset)
-+{
-+ unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
-+ unsigned int result = offset & ~31UL;
-+ unsigned int tmp;
-+
-+ if (offset >= size)
-+ return size;
-+ size -= result;
-+ offset &= 31UL;
-+ if (offset) {
-+ tmp = *p++;
-+ tmp &= ~0UL << offset;
-+ if (size < 32)
-+ goto found_first;
-+ if (tmp)
-+ goto found_middle;
-+ size -= 32;
-+ result += 32;
-+ }
-+ while (size >= 32) {
-+ tmp = *p++;
-+ if (tmp != 0)
-+ goto found_middle;
-+ result += 32;
-+ size -= 32;
-+ }
-+ if (!size)
-+ return result;
-+ tmp = *p;
-+
-+found_first:
-+ tmp &= ~0UL >> (32 - size);
-+ if (tmp == 0UL) /* Are any bits set? */
-+ return result + size; /* Nope. */
-+found_middle:
-+ return result + __ffs(tmp);
-+}
-+
-+#define find_first_bit(addr, size) find_next_bit((addr), (size), 0)
-+
-+#ifdef __KERNEL__
-+
-+/* Ported from include/linux/bitops.h */
-+static __inline__ int fls(int x)
-+{
-+ int r = 32;
-+
-+ if (!x)
-+ return 0;
-+ if (!(x & 0xffff0000u)) {
-+ x <<= 16;
-+ r -= 16;
-+ }
-+ if (!(x & 0xff000000u)) {
-+ x <<= 8;
-+ r -= 8;
-+ }
-+ if (!(x & 0xf0000000u)) {
-+ x <<= 4;
-+ r -= 4;
-+ }
-+ if (!(x & 0xc0000000u)) {
-+ x <<= 2;
-+ r -= 2;
-+ }
-+ if (!(x & 0x80000000u)) {
-+ x <<= 1;
-+ r -= 1;
-+ }
-+ return r;
-+}
-+
-+#include <asm-generic/bitops/fls64.h>
-+#include <asm-generic/bitops/sched.h>
-+#include <asm-generic/bitops/hweight.h>
-+
-+#define minix_find_first_zero_bit(addr, size) find_next_zero_bit((addr), \
-+ (size), 0)
-+#define minix_test_and_set_bit(nr, addr) test_and_set_bit((nr), \
-+ (unsigned long *)(addr))
-+#define minix_set_bit(nr, addr) set_bit((nr), \
-+ (unsigned long *)(addr))
-+#define minix_test_and_clear_bit(nr, addr) test_and_clear_bit((nr), \
-+ (unsigned long *)(addr))
-+
-+static inline int minix_test_bit(int nr, const volatile unsigned long *vaddr)
-+{
-+ int *a = (int *)vaddr;
-+ int mask;
-+
-+ a += nr >> 5;
-+ mask = 1 << (nr & 0x1f);
-+ return ((mask & *a) != 0);
-+}
-+
-+#define ext2_set_bit(nr, addr) test_and_set_bit((nr) ^ 24, \
-+ (unsigned long *)(addr))
-+#define ext2_set_bit_atomic(lock, nr, addr) test_and_set_bit((nr) ^ 24, \
-+ (unsigned long *)(addr))
-+#define ext2_clear_bit(nr, addr) test_and_clear_bit((nr) ^ 24, \
-+ (unsigned long *)(addr))
-+#define ext2_clear_bit_atomic(lock, nr, addr) test_and_clear_bit((nr) ^ 24, \
-+ (unsigned long *)(addr))
-+
-+static inline int ext2_test_bit(int nr, const void *vaddr)
-+{
-+ const unsigned char *p = vaddr;
-+ return (p[nr >> 3] & (1U << (nr & 7))) != 0;
-+}
-+
-+static inline int ext2_find_first_zero_bit(const void *vaddr, unsigned size)
-+{
-+ const unsigned long *p = vaddr, *addr = vaddr;
-+ int res;
-+
-+ if (!size)
-+ return 0;
-+
-+ size = (size >> 5) + ((size & 31) > 0);
-+ while (*p++ == ~0UL) {
-+ if (--size == 0)
-+ return (p - addr) << 5;
-+ }
-+
-+ --p;
-+ for (res = 0; res < 32; res++)
-+ if (!ext2_test_bit (res, p))
-+ break;
-+ return (p - addr) * 32 + res;
-+}
-+
-+static inline int ext2_find_next_zero_bit(const void *vaddr, unsigned size,
-+ unsigned offset)
-+{
-+ const unsigned long *addr = vaddr;
-+ const unsigned long *p = addr + (offset >> 5);
-+ int bit = offset & 31UL, res;
-+
-+ if (offset >= size)
-+ return size;
-+
-+ if (bit) {
-+ /* Look for zero in first longword */
-+ for (res = bit; res < 32; res++)
-+ if (!ext2_test_bit (res, p))
-+ return (p - addr) * 32 + res;
-+ p++;
-+ }
-+ /* No zero yet, search remaining full bytes for a zero */
-+ res = ext2_find_first_zero_bit(p, size - 32 * (p - addr));
-+ return (p - addr) * 32 + res;
-+}
-+
-+#endif /* KERNEL */
-+
-+#endif /* CONFIG_COLDFIRE */
-+
- #endif /* _M68K_BITOPS_H */
---- a/include/asm-m68k/bootinfo.h
-+++ b/include/asm-m68k/bootinfo.h
-@@ -49,6 +49,19 @@ struct bi_record {
- #endif /* __ASSEMBLY__ */
-
-
-+#ifndef __ASSEMBLY__
-+
-+struct uboot_record {
-+ unsigned long bd_info;
-+ unsigned long initrd_start;
-+ unsigned long initrd_end;
-+ unsigned long cmd_line_start;
-+ unsigned long cmd_line_stop;
-+};
-+
-+#endif /* __ASSEMBLY__ */
-+
-+
- /*
- * Tag Definitions
- *
---- a/include/asm-m68k/byteorder.h
-+++ b/include/asm-m68k/byteorder.h
-@@ -4,8 +4,15 @@
- #include <asm/types.h>
- #include <linux/compiler.h>
-
--#ifdef __GNUC__
--
-+#if defined(__GNUC__)
-+#if defined(__mcfisaaplus__) || defined(__mcfisac__)
-+static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 val)
-+{
-+ __asm__ ("byterev %0" : "=d" (val) : "0" (val));
-+ return val;
-+}
-+#define __arch__swab32(x) ___arch__swab32(x)
-+#elif !defined(__mcoldfire__)
- static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 val)
- {
- __asm__("rolw #8,%0; swap %0; rolw #8,%0" : "=d" (val) : "0" (val));
-@@ -14,6 +21,7 @@ static __inline__ __attribute_const__ __
- #define __arch__swab32(x) ___arch__swab32(x)
-
- #endif
-+#endif
-
- #if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__)
- # define __BYTEORDER_HAS_U64__
---- a/include/asm-m68k/cacheflush.h
-+++ b/include/asm-m68k/cacheflush.h
-@@ -6,6 +6,9 @@
- /* cache code */
- #define FLUSH_I_AND_D (0x00000808)
- #define FLUSH_I (0x00000008)
-+#ifdef CONFIG_COLDFIRE
-+#include <asm/cf_cacheflush.h>
-+#else /* !CONFIG_COLDFIRE */
-
- /*
- * Cache handling functions
-@@ -153,4 +156,5 @@ static inline void copy_from_user_page(s
- memcpy(dst, src, len);
- }
-
-+#endif /* !CONFIG_COLDFIRE */
- #endif /* _M68K_CACHEFLUSH_H */
---- a/include/asm-m68k/checksum.h
-+++ b/include/asm-m68k/checksum.h
-@@ -34,6 +34,7 @@ extern __wsum csum_partial_copy_nocheck(
- void *dst, int len,
- __wsum sum);
-
-+#ifndef CONFIG_COLDFIRE /* CF has own copy in arch/m68k/lib/checksum.c */
- /*
- * This is a version of ip_compute_csum() optimized for IP headers,
- * which always checksum on 4 octet boundaries.
-@@ -59,6 +60,9 @@ static inline __sum16 ip_fast_csum(const
- : "memory");
- return (__force __sum16)~sum;
- }
-+#else
-+extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl);
-+#endif
-
- /*
- * Fold a partial checksum
-@@ -67,6 +71,11 @@ static inline __sum16 ip_fast_csum(const
- static inline __sum16 csum_fold(__wsum sum)
- {
- unsigned int tmp = (__force u32)sum;
-+#ifdef CONFIG_COLDFIRE
-+ tmp = (tmp & 0xffff) + (tmp >> 16);
-+ tmp = (tmp & 0xffff) + (tmp >> 16);
-+ return (__force __sum16) ~tmp;
-+#else
- __asm__("swap %1\n\t"
- "addw %1, %0\n\t"
- "clrw %1\n\t"
-@@ -74,6 +83,7 @@ static inline __sum16 csum_fold(__wsum s
- : "=&d" (sum), "=&d" (tmp)
- : "0" (sum), "1" (tmp));
- return (__force __sum16)~sum;
-+#endif
- }
-
-
---- a/include/asm-m68k/delay.h
-+++ b/include/asm-m68k/delay.h
-@@ -11,8 +11,25 @@
-
- static inline void __delay(unsigned long loops)
- {
-+#if defined(CONFIG_COLDFIRE)
-+ /* The coldfire runs this loop at significantly different speeds
-+ * depending upon long word alignment or not. We'll pad it to
-+ * long word alignment which is the faster version.
-+ * The 0x4a8e is of course a 'tstl %fp' instruction. This is better
-+ * than using a NOP (0x4e71) instruction because it executes in one
-+ * cycle not three and doesn't allow for an arbitary delay waiting
-+ * for bus cycles to finish. Also fp/a6 isn't likely to cause a
-+ * stall waiting for the register to become valid if such is added
-+ * to the coldfire at some stage.
-+ */
-+ __asm__ __volatile__ (".balignw 4, 0x4a8e\n\t"
-+ "1: subql #1, %0\n\t"
-+ "jcc 1b"
-+ : "=d" (loops) : "0" (loops));
-+#else
- __asm__ __volatile__ ("1: subql #1,%0; jcc 1b"
- : "=d" (loops) : "0" (loops));
-+#endif
- }
-
- extern void __bad_udelay(void);
-@@ -26,12 +43,17 @@ extern void __bad_udelay(void);
- */
- static inline void __const_udelay(unsigned long xloops)
- {
-+#if defined(CONFIG_COLDFIRE)
-+
-+ __delay(((((unsigned long long) xloops * loops_per_jiffy))>>32)*HZ);
-+#else
- unsigned long tmp;
-
- __asm__ ("mulul %2,%0:%1"
- : "=d" (xloops), "=d" (tmp)
- : "d" (xloops), "1" (loops_per_jiffy));
- __delay(xloops * HZ);
-+#endif
- }
-
- static inline void __udelay(unsigned long usecs)
-@@ -46,12 +68,16 @@ static inline void __udelay(unsigned lon
- static inline unsigned long muldiv(unsigned long a, unsigned long b,
- unsigned long c)
- {
-+#if defined(CONFIG_COLDFIRE)
-+ return (long)(((unsigned long long)a * b)/c);
-+#else
- unsigned long tmp;
-
- __asm__ ("mulul %2,%0:%1; divul %3,%0:%1"
- : "=d" (tmp), "=d" (a)
- : "d" (b), "d" (c), "1" (a));
- return a;
-+#endif
- }
-
- #endif /* defined(_M68K_DELAY_H) */
---- a/include/asm-m68k/div64.h
-+++ b/include/asm-m68k/div64.h
-@@ -5,6 +5,7 @@
-
- /* n = n / base; return rem; */
-
-+#ifndef CONFIG_COLDFIRE
- #define do_div(n, base) ({ \
- union { \
- unsigned long n32[2]; \
-@@ -24,6 +25,9 @@
- (n) = __n.n64; \
- __rem; \
- })
-+#else
-+# include <asm-generic/div64.h>
-+#endif
-
- extern uint64_t div64_64(uint64_t dividend, uint64_t divisor);
- #endif /* _M68K_DIV64_H */
---- a/include/asm-m68k/elf.h
-+++ b/include/asm-m68k/elf.h
-@@ -60,7 +60,7 @@ typedef struct user_m68kfp_struct elf_fp
- #define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0
-
- #define USE_ELF_CORE_DUMP
--#ifndef CONFIG_SUN3
-+#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
- #define ELF_EXEC_PAGESIZE 4096
- #else
- #define ELF_EXEC_PAGESIZE 8192
---- a/include/asm-m68k/fpu.h
-+++ b/include/asm-m68k/fpu.h
-@@ -12,6 +12,8 @@
- #define FPSTATESIZE (96/sizeof(unsigned char))
- #elif defined(CONFIG_M68KFPU_EMU)
- #define FPSTATESIZE (28/sizeof(unsigned char))
-+#elif defined(CONFIG_CFV4E)
-+#define FPSTATESIZE (16/sizeof(unsigned char))
- #elif defined(CONFIG_M68060)
- #define FPSTATESIZE (12/sizeof(unsigned char))
- #else
---- a/include/asm-m68k/io.h
-+++ b/include/asm-m68k/io.h
-@@ -397,10 +397,12 @@ static inline void memcpy_toio(volatile
- __builtin_memcpy((void __force *) dst, src, count);
- }
-
--#ifndef CONFIG_SUN3
--#define IO_SPACE_LIMIT 0xffff
--#else
-+#if defined(CONFIG_SUN3)
- #define IO_SPACE_LIMIT 0x0fffffff
-+#elif defined(CONFIG_COLDFIRE)
-+#define IO_SPACE_LIMIT 0xffffffff
-+#else
-+#define IO_SPACE_LIMIT 0xffff
- #endif
-
- #endif /* __KERNEL__ */
-@@ -418,4 +420,22 @@ static inline void memcpy_toio(volatile
- */
- #define xlate_dev_kmem_ptr(p) p
-
-+#ifdef CONFIG_COLDFIRE
-+
-+#define memset_io(a, b, c) memset((void *)(a), (b), (c))
-+#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
-+#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
-+#if !defined(readb)
-+#define readb(addr) \
-+ ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
-+#define readw(addr) \
-+ ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
-+#define readl(addr) \
-+ ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
-+#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b))
-+#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b))
-+#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b))
-+#endif /* readb */
-+#endif /* CONFIG_COLDFIRE */
-+
- #endif /* _IO_H */
---- a/include/asm-m68k/irq.h
-+++ b/include/asm-m68k/irq.h
-@@ -11,7 +11,10 @@
- * Currently the Atari has 72 and the Amiga 24, but if both are
- * supported in the kernel it is better to make room for 72.
- */
--#if defined(CONFIG_VME) || defined(CONFIG_SUN3) || defined(CONFIG_SUN3X)
-+#if defined(CONFIG_COLDFIRE)
-+#define SYS_IRQS 256
-+#define NR_IRQS SYS_IRQS
-+#elif defined(CONFIG_VME) || defined(CONFIG_SUN3) || defined(CONFIG_SUN3X)
- #define NR_IRQS 200
- #elif defined(CONFIG_ATARI) || defined(CONFIG_MAC)
- #define NR_IRQS 72
---- a/include/asm-m68k/machdep.h
-+++ b/include/asm-m68k/machdep.h
-@@ -32,4 +32,11 @@ extern void (*mach_heartbeat) (int);
- extern void (*mach_l2_flush) (int);
- extern void (*mach_beep) (unsigned int, unsigned int);
-
-+#ifdef CONFIG_COLDFIRE
-+extern void __init config_coldfire(void);
-+extern void __init mmu_context_init(void);
-+extern irq_handler_t mach_default_handler;
-+extern void (*mach_tick)(void);
-+#endif
-+
- #endif /* _M68K_MACHDEP_H */
---- a/include/asm-m68k/mmu_context.h
-+++ b/include/asm-m68k/mmu_context.h
-@@ -7,7 +7,7 @@ static inline void enter_lazy_tlb(struct
- {
- }
-
--#ifndef CONFIG_SUN3
-+#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
-
- #include <asm/setup.h>
- #include <asm/page.h>
-@@ -102,7 +102,7 @@ static inline void activate_mm(struct mm
- switch_mm_0460(next_mm);
- }
-
--#else /* CONFIG_SUN3 */
-+#elif defined(CONFIG_SUN3)
- #include <asm/sun3mmu.h>
- #include <linux/sched.h>
-
-@@ -150,5 +150,83 @@ static inline void activate_mm(struct mm
- activate_context(next_mm);
- }
-
--#endif
-+#else /* CONFIG_COLDFIRE */
-+
-+#include <asm/atomic.h>
-+#include <asm/bitops.h>
-+#include <asm/mmu.h>
-+
-+#define NO_CONTEXT 256
-+#define LAST_CONTEXT 255
-+#define FIRST_CONTEXT 1
-+
-+extern void set_context(mm_context_t context, pgd_t *pgd);
-+extern unsigned long context_map[];
-+extern mm_context_t next_mmu_context;
-+
-+extern atomic_t nr_free_contexts;
-+extern struct mm_struct *context_mm[LAST_CONTEXT+1];
-+extern void steal_context(void);
-+
-+static inline void get_mmu_context(struct mm_struct *mm)
-+{
-+ mm_context_t ctx;
-+
-+ if (mm->context != NO_CONTEXT)
-+ return;
-+ while (atomic_dec_and_test_lt(&nr_free_contexts)) {
-+ atomic_inc(&nr_free_contexts);
-+ steal_context();
-+ }
-+ ctx = next_mmu_context;
-+ while (test_and_set_bit(ctx, context_map)) {
-+ ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx);
-+ if (ctx > LAST_CONTEXT)
-+ ctx = 0;
-+ }
-+ next_mmu_context = (ctx + 1) & LAST_CONTEXT;
-+ mm->context = ctx;
-+ context_mm[ctx] = mm;
-+}
-+
-+/*
-+ * Set up the context for a new address space.
-+ */
-+#define init_new_context(tsk, mm) (((mm)->context = NO_CONTEXT), 0)
-+
-+/*
-+ * We're finished using the context for an address space.
-+ */
-+static inline void destroy_context(struct mm_struct *mm)
-+{
-+ if (mm->context != NO_CONTEXT) {
-+ clear_bit(mm->context, context_map);
-+ mm->context = NO_CONTEXT;
-+ atomic_inc(&nr_free_contexts);
-+ }
-+}
-+
-+static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
-+ struct task_struct *tsk)
-+{
-+ get_mmu_context(tsk->mm);
-+ set_context(tsk->mm->context, next->pgd);
-+}
-+
-+/*
-+ * After we have set current->mm to a new value, this activates
-+ * the context for the new mm so we see the new mappings.
-+ */
-+static inline void activate_mm(struct mm_struct *active_mm,
-+ struct mm_struct *mm)
-+{
-+ get_mmu_context(mm);
-+ set_context(mm->context, mm->pgd);
-+}
-+
-+#define deactivate_mm(tsk, mm) do { } while (0)
-+
-+extern void mmu_context_init(void);
-+
-+#endif /* CONFIG_COLDFIRE */
- #endif
---- a/include/asm-m68k/page.h
-+++ b/include/asm-m68k/page.h
-@@ -4,7 +4,7 @@
- #include <linux/const.h>
-
- /* PAGE_SHIFT determines the page size */
--#ifndef CONFIG_SUN3
-+#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
- #define PAGE_SHIFT (12)
- #else
- #define PAGE_SHIFT (13)
-@@ -116,10 +116,23 @@ typedef struct page *pgtable_t;
-
- extern unsigned long m68k_memoffset;
-
--#ifndef CONFIG_SUN3
-+#if !defined(CONFIG_SUN3)
-
- #define WANT_PAGE_VIRTUAL
-
-+#if defined(CONFIG_COLDFIRE)
-+static inline unsigned long ___pa(void *vaddr)
-+{
-+ return (((unsigned long)vaddr & 0x0fffffff) + CONFIG_SDRAM_BASE);
-+}
-+#define __pa(vaddr) ___pa((void *)(vaddr))
-+
-+static inline void *__va(unsigned long paddr)
-+{
-+ return (void *)((paddr & 0x0fffffff) + PAGE_OFFSET);
-+}
-+
-+#else
- static inline unsigned long ___pa(void *vaddr)
- {
- unsigned long paddr;
-@@ -141,6 +154,7 @@ static inline void *__va(unsigned long p
- : "0" (paddr), "i" (m68k_fixup_memoffset));
- return vaddr;
- }
-+#endif
-
- #else /* !CONFIG_SUN3 */
- /* This #define is a horrible hack to suppress lots of warnings. --m */
-@@ -172,6 +186,8 @@ static inline void *__va(unsigned long x
- * memory node, but we have no highmem, so that works for now.
- * TODO: implement (fast) pfn<->pgdat_idx conversion functions, this makes lots
- * of the shifts unnecessary.
-+ *
-+ * PFNs are used to map physical pages. So PFN[0] maps to the base phys addr.
- */
- #define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT)
- #define pfn_to_virt(pfn) __va((pfn) << PAGE_SHIFT)
---- a/include/asm-m68k/page_offset.h
-+++ b/include/asm-m68k/page_offset.h
-@@ -1,8 +1,11 @@
-
- /* This handles the memory map.. */
--#ifndef CONFIG_SUN3
-+#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
- #define PAGE_OFFSET_RAW 0x00000000
--#else
-+#elif defined(CONFIG_SUN3)
- #define PAGE_OFFSET_RAW 0x0E000000
-+#else /* CONFIG_COLDFIRE */
-+#define PAGE_OFFSET_RAW 0xC0000000
-+#define PHYS_OFFSET 0x40000000
- #endif
-
---- a/include/asm-m68k/pci.h
-+++ b/include/asm-m68k/pci.h
-@@ -1,57 +1,86 @@
--#ifndef _ASM_M68K_PCI_H
--#define _ASM_M68K_PCI_H
--
- /*
-- * asm-m68k/pci_m68k.h - m68k specific PCI declarations.
-+ * asm-m68k/pci.h - m68k specific PCI declarations.
- *
-- * Written by Wout Klaren.
-+ * Coldfire Implementation Copyright (c) 2007 Freescale Semiconductor, Inc.
-+ * Kurt Mahan <kmahan@freescale.com>
- */
-+#ifndef _ASM_M68K_PCI_H
-+#define _ASM_M68K_PCI_H
-
--#include <asm/scatterlist.h>
-+#ifdef CONFIG_PCI
-
--struct pci_ops;
-+#include <asm-generic/pci-dma-compat.h>
-
- /*
-- * Structure with hardware dependent information and functions of the
-- * PCI bus.
-+ * The PCI address space does equal the physical memory
-+ * address space. The networking and block device layers use
-+ * this boolean for bounce buffer decisions.
- */
-+#define PCI_DMA_BUS_IS_PHYS (1)
-
--struct pci_bus_info
--{
-- /*
-- * Resources of the PCI bus.
-- */
--
-- struct resource mem_space;
-- struct resource io_space;
-+#define PCIBIOS_MIN_IO 0x00004000
-+#define PCIBIOS_MIN_MEM 0x02000000
-
-- /*
-- * System dependent functions.
-- */
-+#define pcibios_assign_all_busses() 0
-+#define pcibios_scan_all_fns(a, b) 0
-
-- struct pci_ops *m68k_pci_ops;
-+static inline void
-+pcibios_set_master(struct pci_dev *dev)
-+{
-+ /* no special bus mastering setup handling */
-+}
-
-- void (*fixup)(int pci_modify);
-- void (*conf_device)(struct pci_dev *dev);
--};
-+static inline void
-+pcibios_penalize_isa_irq(int irq, int active)
-+{
-+ /* no dynamic PCI IRQ allocation */
-+}
-
--#define pcibios_assign_all_busses() 0
--#define pcibios_scan_all_fns(a, b) 0
-+static inline void
-+pcibios_add_platform_entries(struct pci_dev *dev)
-+{
-+ /* no special handling */
-+}
-
--static inline void pcibios_set_master(struct pci_dev *dev)
-+static inline void
-+pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-+ struct resource *res)
- {
-- /* No special bus mastering setup handling */
-+#ifdef CONFIG_M54455
-+ if ((res->start == 0xa0000000) || (res->start == 0xa8000000)) {
-+ /* HACK! FIX! kludge to fix bridge mapping */
-+ region->start = res->start & 0x0fffffff;
-+ region->end = res->end & 0x0fffffff;
-+ } else {
-+ region->start = res->start;
-+ region->end = res->end;
-+ }
-+#else
-+ region->start = res->start;
-+ region->end = res->end;
-+#endif
- }
-
--static inline void pcibios_penalize_isa_irq(int irq, int active)
-+static inline void
-+pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-+ struct pci_bus_region *region)
- {
-- /* We don't do dynamic PCI IRQ allocation */
-+ res->start = region->start;
-+ res->end = region->end;
- }
-
--/* The PCI address space does equal the physical memory
-- * address space. The networking and block device layers use
-- * this boolean for bounce buffer decisions.
-- */
--#define PCI_DMA_BUS_IS_PHYS (1)
-+static inline struct resource *
-+pcibios_select_root(struct pci_dev *pdev, struct resource *res)
-+{
-+ struct resource *root = NULL;
-+
-+ if (res->flags & IORESOURCE_IO)
-+ root = &ioport_resource;
-+ if (res->flags & IORESOURCE_MEM)
-+ root = &iomem_resource;
-+
-+ return root;
-+}
-
-+#endif /* CONFIG_PCI */
- #endif /* _ASM_M68K_PCI_H */
---- a/include/asm-m68k/pgalloc.h
-+++ b/include/asm-m68k/pgalloc.h
-@@ -8,8 +8,10 @@
- #include <asm/virtconvert.h>
-
-
--#ifdef CONFIG_SUN3
-+#if defined(CONFIG_SUN3)
- #include <asm/sun3_pgalloc.h>
-+#elif defined(CONFIG_COLDFIRE)
-+#include <asm/cf_pgalloc.h>
- #else
- #include <asm/motorola_pgalloc.h>
- #endif
---- a/include/asm-m68k/pgtable.h
-+++ b/include/asm-m68k/pgtable.h
-@@ -40,6 +40,8 @@
- /* PGDIR_SHIFT determines what a third-level page table entry can map */
- #ifdef CONFIG_SUN3
- #define PGDIR_SHIFT 17
-+#elif defined(CONFIG_COLDFIRE)
-+#define PGDIR_SHIFT 22
- #else
- #define PGDIR_SHIFT 25
- #endif
-@@ -54,6 +56,10 @@
- #define PTRS_PER_PTE 16
- #define PTRS_PER_PMD 1
- #define PTRS_PER_PGD 2048
-+#elif defined(CONFIG_COLDFIRE)
-+#define PTRS_PER_PTE 512
-+#define PTRS_PER_PMD 1
-+#define PTRS_PER_PGD 1024
- #else
- #define PTRS_PER_PTE 1024
- #define PTRS_PER_PMD 8
-@@ -66,6 +72,9 @@
- #ifdef CONFIG_SUN3
- #define KMAP_START 0x0DC00000
- #define KMAP_END 0x0E000000
-+#elif defined(CONFIG_COLDFIRE)
-+#define KMAP_START 0xe0000000
-+#define KMAP_END 0xf0000000
- #else
- #define KMAP_START 0xd0000000
- #define KMAP_END 0xf0000000
-@@ -130,6 +139,8 @@ static inline void update_mmu_cache(stru
-
- #ifdef CONFIG_SUN3
- #include <asm/sun3_pgtable.h>
-+#elif defined(CONFIG_COLDFIRE)
-+#include <asm/cf_pgtable.h>
- #else
- #include <asm/motorola_pgtable.h>
- #endif
-@@ -140,6 +151,9 @@ static inline void update_mmu_cache(stru
- /*
- * Macro to mark a page protection value as "uncacheable".
- */
-+#ifdef CONFIG_COLDFIRE
-+# define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | CF_PAGE_NOCACHE))
-+#else /* CONFIG_COLDFIRE */
- #ifdef SUN3_PAGE_NOCACHE
- # define __SUN3_PAGE_NOCACHE SUN3_PAGE_NOCACHE
- #else
-@@ -154,6 +168,7 @@ static inline void update_mmu_cache(stru
- ? (__pgprot((pgprot_val(prot) & _CACHEMASK040) | _PAGE_NOCACHE_S)) \
- : (prot)))
-
-+#endif /* CONFIG_COLDFIRE */
- #endif /* !__ASSEMBLY__ */
-
- /*
---- a/include/asm-m68k/processor.h
-+++ b/include/asm-m68k/processor.h
-@@ -22,24 +22,38 @@ static inline unsigned long rdusp(void)
- {
- unsigned long usp;
-
-+#ifndef CONFIG_COLDFIRE
- __asm__ __volatile__("move %/usp,%0" : "=a" (usp));
-+#else
-+ __asm__ __volatile__("movel %/usp,%0" : "=a" (usp));
-+#endif
- return usp;
- }
-
- static inline void wrusp(unsigned long usp)
- {
-+#ifndef CONFIG_COLDFIRE
- __asm__ __volatile__("move %0,%/usp" : : "a" (usp));
-+#else
-+ __asm__ __volatile__("movel %0,%/usp" : : "a" (usp));
-+#endif
- }
-
- /*
- * User space process size: 3.75GB. This is hardcoded into a few places,
- * so don't change it unless you know what you are doing.
- */
--#ifndef CONFIG_SUN3
-+#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
- #define TASK_SIZE (0xF0000000UL)
-+#elif defined(CONFIG_COLDFIRE)
-+#define TASK_SIZE (0xC0000000UL)
-+#else /* CONFIG_SUN3 */
-+#ifdef __ASSEMBLY__
-+#define TASK_SIZE (0x0E000000)
- #else
- #define TASK_SIZE (0x0E000000UL)
- #endif
-+#endif
-
- #ifdef __KERNEL__
- #define STACK_TOP TASK_SIZE
-@@ -49,9 +63,11 @@ static inline void wrusp(unsigned long u
- /* This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
--#ifndef CONFIG_SUN3
--#define TASK_UNMAPPED_BASE 0xC0000000UL
--#else
-+#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
-+#define TASK_UNMAPPED_BASE 0xC0000000UL
-+#elif defined(CONFIG_COLDFIRE)
-+#define TASK_UNMAPPED_BASE 0x80000000UL
-+#else /* CONFIG_SUN3 */
- #define TASK_UNMAPPED_BASE 0x0A000000UL
- #endif
- #define TASK_UNMAPPED_ALIGN(addr, off) PAGE_ALIGN(addr)
-@@ -60,7 +76,11 @@ struct thread_struct {
- unsigned long ksp; /* kernel stack pointer */
- unsigned long usp; /* user stack pointer */
- unsigned short sr; /* saved status register */
-+#ifndef CONFIG_COLDFIRE
- unsigned short fs; /* saved fs (sfc, dfc) */
-+#else
-+ mm_segment_t fs;
-+#endif
- unsigned long crp[2]; /* cpu root pointer */
- unsigned long esp0; /* points to SR of stack frame */
- unsigned long faddr; /* info about last fault */
-@@ -81,6 +101,7 @@ struct thread_struct {
- /*
- * Do necessary setup to start up a newly executed thread.
- */
-+#ifndef CONFIG_COLDFIRE
- static inline void start_thread(struct pt_regs * regs, unsigned long pc,
- unsigned long usp)
- {
-@@ -91,6 +112,23 @@ static inline void start_thread(struct p
- regs->sr &= ~0x2000;
- wrusp(usp);
- }
-+#else
-+/*
-+ * Do necessary setup to start up a newly executed thread.
-+ *
-+ * pass the data segment into user programs if it exists,
-+ * it can't hurt anything as far as I can tell
-+ */
-+#define start_thread(_regs, _pc, _usp) \
-+do { \
-+ set_fs(USER_DS); /* reads from user space */ \
-+ (_regs)->pc = (_pc); \
-+ if (current->mm) \
-+ (_regs)->d5 = current->mm->start_data; \
-+ (_regs)->sr &= ~0x2000; \
-+ wrusp(_usp); \
-+} while (0)
-+#endif
-
- /* Forward declaration, a strange C thing */
- struct task_struct;
---- a/include/asm-m68k/ptrace.h
-+++ b/include/asm-m68k/ptrace.h
-@@ -38,10 +38,21 @@ struct pt_regs {
- long d0;
- long orig_d0;
- long stkadj;
-+#ifndef CONFIG_COLDFIRE
- unsigned short sr;
- unsigned long pc;
- unsigned format : 4; /* frame format specifier */
- unsigned vector : 12; /* vector offset */
-+#else
-+ unsigned long mmuar;
-+ unsigned long mmusr;
-+ unsigned format : 4; /* frame format specifier */
-+ unsigned fs2 : 2;
-+ unsigned vector: 8;
-+ unsigned fs1 : 2;
-+ unsigned short sr;
-+ unsigned long pc;
-+#endif
- };
-
- /*
---- a/include/asm-m68k/raw_io.h
-+++ b/include/asm-m68k/raw_io.h
-@@ -77,6 +77,7 @@ static inline void raw_outsb(volatile u8
- out_8(port, *buf++);
- }
-
-+#ifndef CONFIG_COLDFIRE
- static inline void raw_insw(volatile u16 __iomem *port, u16 *buf, unsigned int nr)
- {
- unsigned int tmp;
-@@ -342,6 +343,63 @@ static inline void raw_outsw_swapw(volat
- : "d0", "a0", "a1", "d6");
- }
-
-+
-+#else /*CONFIG_COLDFIRE */
-+
-+static inline void raw_insw(volatile u16 *port, u16 *buf, unsigned int nr)
-+{
-+ unsigned int i;
-+
-+ for (i = 0; i < nr; i++)
-+ *buf++ = raw_inw(port);
-+}
-+
-+static inline void raw_outsw(volatile u16 *port, const u16 *buf,
-+ unsigned int nr)
-+{
-+ unsigned int i;
-+
-+ for (i = 0; i < nr; i++, buf++)
-+ raw_outw(*buf, port);
-+}
-+
-+static inline void raw_insl(volatile u32 *port, u32 *buf, unsigned int nr)
-+{
-+ unsigned int i;
-+
-+ for (i = 0; i < nr; i++)
-+ *buf++ = raw_inl(port);
-+}
-+
-+static inline void raw_outsl(volatile u32 *port, const u32 *buf,
-+ unsigned int nr)
-+{
-+ unsigned int i;
-+
-+ for (i = 0; i < nr; i++, buf++)
-+ raw_outl(*buf, port);
-+}
-+
-+static inline void raw_insw_swapw(volatile u16 *port, u16 *buf,
-+ unsigned int nr)
-+{
-+ unsigned int i;
-+
-+ for (i = 0; i < nr; i++)
-+ *buf++ = in_le16(port);
-+
-+}
-+
-+static inline void raw_outsw_swapw(volatile u16 __iomem *port, const u16 *buf,
-+ unsigned int nr)
-+{
-+ unsigned int i;
-+
-+ for (i = 0; i < nr; i++, buf++)
-+ out_le16(port, *buf);
-+}
-+#endif /*CONFIG_COLDFIRE */
-+
- #endif /* __KERNEL__ */
-
- #endif /* _RAW_IO_H */
---- a/include/asm-m68k/segment.h
-+++ b/include/asm-m68k/segment.h
-@@ -29,6 +29,7 @@ typedef struct {
- * Get/set the SFC/DFC registers for MOVES instructions
- */
-
-+#ifndef CONFIG_COLDFIRE
- static inline mm_segment_t get_fs(void)
- {
- mm_segment_t _v;
-@@ -50,6 +51,15 @@ static inline void set_fs(mm_segment_t v
- : /* no outputs */ : "r" (val.seg) : "memory");
- }
-
-+#else /* CONFIG_COLDFIRE */
-+
-+#include <asm/current.h>
-+#define get_fs() (current->thread.fs)
-+#define set_fs(val) (current->thread.fs = (val))
-+#define get_ds() (KERNEL_DS)
-+
-+#endif /* CONFIG_COLDFIRE */
-+
- #define segment_eq(a,b) ((a).seg == (b).seg)
-
- #endif /* __ASSEMBLY__ */
---- a/include/asm-m68k/setup.h
-+++ b/include/asm-m68k/setup.h
-@@ -40,6 +40,7 @@
- #define MACH_HP300 9
- #define MACH_Q40 10
- #define MACH_SUN3X 11
-+#define MACH_CFMMU 12
-
- #define COMMAND_LINE_SIZE 256
-
-@@ -189,6 +190,14 @@ extern unsigned long m68k_machtype;
- # define MACH_TYPE (MACH_SUN3X)
- #endif
-
-+#if !defined(CONFIG_COLDFIRE)
-+# define MACH_IS_COLDFIRE (0)
-+#else
-+# define CONFIG_COLDFIRE_ONLY
-+# define MACH_IS_COLDFIRE (1)
-+# define MACH_TYPE (MACH_CFMMU)
-+#endif
-+
- #ifndef MACH_TYPE
- # define MACH_TYPE (m68k_machtype)
- #endif
-@@ -211,23 +220,31 @@ extern unsigned long m68k_machtype;
- #define CPUB_68030 1
- #define CPUB_68040 2
- #define CPUB_68060 3
-+#define CPUB_CFV4E 4
-
- #define CPU_68020 (1<<CPUB_68020)
- #define CPU_68030 (1<<CPUB_68030)
- #define CPU_68040 (1<<CPUB_68040)
- #define CPU_68060 (1<<CPUB_68060)
-+#define CPU_CFV4E (1<<CPUB_CFV4E)
-
- #define FPUB_68881 0
- #define FPUB_68882 1
- #define FPUB_68040 2 /* Internal FPU */
- #define FPUB_68060 3 /* Internal FPU */
- #define FPUB_SUNFPA 4 /* Sun-3 FPA */
-+#define FPUB_CFV4E 5
-
- #define FPU_68881 (1<<FPUB_68881)
- #define FPU_68882 (1<<FPUB_68882)
- #define FPU_68040 (1<<FPUB_68040)
- #define FPU_68060 (1<<FPUB_68060)
- #define FPU_SUNFPA (1<<FPUB_SUNFPA)
-+#ifndef CONFIG_M54455
-+#define FPU_CFV4E (1<<FPUB_CFV4E)
-+#else
-+#define FPU_CFV4E 0
-+#endif
-
- #define MMUB_68851 0
- #define MMUB_68030 1 /* Internal MMU */
-@@ -235,6 +252,7 @@ extern unsigned long m68k_machtype;
- #define MMUB_68060 3 /* Internal MMU */
- #define MMUB_APOLLO 4 /* Custom Apollo */
- #define MMUB_SUN3 5 /* Custom Sun-3 */
-+#define MMUB_CFV4E 6
-
- #define MMU_68851 (1<<MMUB_68851)
- #define MMU_68030 (1<<MMUB_68030)
-@@ -242,6 +260,7 @@ extern unsigned long m68k_machtype;
- #define MMU_68060 (1<<MMUB_68060)
- #define MMU_SUN3 (1<<MMUB_SUN3)
- #define MMU_APOLLO (1<<MMUB_APOLLO)
-+#define MMU_CFV4E (1<<MMUB_CFV4E)
-
- #ifdef __KERNEL__
-
-@@ -341,6 +360,14 @@ extern int m68k_is040or060;
- # endif
- #endif
-
-+#if !defined(CONFIG_CFV4E)
-+# define CPU_IS_COLDFIRE (0)
-+#else
-+# define CPU_IS_COLDFIRE (1)
-+# define CPU_IS_CFV4E (1)
-+# define MMU_IS_CFV4E (1)
-+#endif
-+
- #define CPU_TYPE (m68k_cputype)
-
- #ifdef CONFIG_M68KFPU_EMU
---- a/include/asm-m68k/signal.h
-+++ b/include/asm-m68k/signal.h
-@@ -150,6 +150,7 @@ typedef struct sigaltstack {
- #ifdef __KERNEL__
- #include <asm/sigcontext.h>
-
-+#ifndef CONFIG_COLDFIRE
- #define __HAVE_ARCH_SIG_BITOPS
-
- static inline void sigaddset(sigset_t *set, int _sig)
-@@ -200,6 +201,10 @@ static inline int sigfindinword(unsigned
-
- struct pt_regs;
- extern void ptrace_signal_deliver(struct pt_regs *regs, void *cookie);
-+#else
-+
-+#define ptrace_signal_deliver(regs, cookie) do { } while (0)
-+#endif /* CONFIG_COLDFIRE */
-
- #endif /* __KERNEL__ */
-
---- a/include/asm-m68k/string.h
-+++ b/include/asm-m68k/string.h
-@@ -93,6 +93,7 @@ static inline char *strchr(const char *s
- return (char *)s - 1;
- }
-
-+#ifndef CONFIG_COLDFIRE
- #define __HAVE_ARCH_STRCMP
- static inline int strcmp(const char *cs, const char *ct)
- {
-@@ -110,6 +111,7 @@ static inline int strcmp(const char *cs,
- : "+a" (cs), "+a" (ct), "=d" (res));
- return res;
- }
-+#endif
-
- #define __HAVE_ARCH_MEMSET
- extern void *memset(void *, int, __kernel_size_t);
---- a/include/asm-m68k/system.h
-+++ b/include/asm-m68k/system.h
-@@ -63,16 +63,25 @@ asmlinkage void resume(void);
- #define smp_read_barrier_depends() ((void)0)
-
- /* interrupt control.. */
--#if 0
--#define local_irq_enable() asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory")
--#else
- #include <linux/hardirq.h>
-+#ifndef CONFIG_COLDFIRE
- #define local_irq_enable() ({ \
- if (MACH_IS_Q40 || !hardirq_count()) \
- asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory"); \
- })
--#endif
- #define local_irq_disable() asm volatile ("oriw #0x0700,%%sr": : : "memory")
-+#else /* CONFIG_COLDFIRE */
-+#define local_irq_enable() \
-+ asm volatile ("move.w %%sr, %%d0\n\t" \
-+ "andil #0xf8ff,%%d0\n\t" \
-+ "move.w %%d0, %%sr\n" \
-+ : : : "cc", "d0", "memory")
-+#define local_irq_disable() \
-+ asm volatile ("move %/sr,%%d0\n\t" \
-+ "ori.l #0x0700,%%d0\n\t" \
-+ "move %%d0,%/sr\n" \
-+ : : : "cc", "%d0", "memory")
-+#endif
- #define local_save_flags(x) asm volatile ("movew %%sr,%0":"=d" (x) : : "memory")
- #define local_irq_restore(x) asm volatile ("movew %0,%%sr": :"d" (x) : "memory")
-
---- a/include/asm-m68k/thread_info.h
-+++ b/include/asm-m68k/thread_info.h
-@@ -58,5 +58,6 @@ struct thread_info {
- #define TIF_DELAYED_TRACE 14 /* single step a syscall */
- #define TIF_SYSCALL_TRACE 15 /* syscall trace active */
- #define TIF_MEMDIE 16
-+#define TIF_FREEZE 17 /* freezing processes */
-
- #endif /* _ASM_M68K_THREAD_INFO_H */
---- a/include/asm-m68k/tlbflush.h
-+++ b/include/asm-m68k/tlbflush.h
-@@ -2,7 +2,7 @@
- #define _M68K_TLBFLUSH_H
-
-
--#ifndef CONFIG_SUN3
-+#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
-
- #include <asm/current.h>
-
-@@ -92,7 +92,12 @@ static inline void flush_tlb_kernel_rang
- flush_tlb_all();
- }
-
--#else
-+static inline void flush_tlb_pgtables(struct mm_struct *mm,
-+ unsigned long start, unsigned long end)
-+{
-+}
-+
-+#elif defined(CONFIG_SUN3)
-
-
- /* Reserved PMEGs. */
-@@ -214,6 +219,13 @@ static inline void flush_tlb_kernel_page
- sun3_put_segmap (addr & ~(SUN3_PMEG_SIZE - 1), SUN3_INVALID_PMEG);
- }
-
-+static inline void flush_tlb_pgtables(struct mm_struct *mm,
-+ unsigned long start, unsigned long end)
-+{
-+}
-+
-+#else /* CONFIG_COLDFIRE */
-+#include <asm/cf_tlbflush.h>
- #endif
-
- #endif /* _M68K_TLBFLUSH_H */
---- a/include/asm-m68k/uaccess.h
-+++ b/include/asm-m68k/uaccess.h
-@@ -1,6 +1,9 @@
- #ifndef __M68K_UACCESS_H
- #define __M68K_UACCESS_H
-
-+#ifdef CONFIG_COLDFIRE
-+#include <asm/cf_uaccess.h>
-+#else
- /*
- * User space memory access functions
- */
-@@ -367,4 +370,5 @@ unsigned long __clear_user(void __user *
-
- #define strlen_user(str) strnlen_user(str, 32767)
-
-+#endif /* CONFIG_COLDFIRE */
- #endif /* _M68K_UACCESS_H */
+++ /dev/null
-From 3da86cd2810e9ba4e4a9e7471a92025172c1c990 Mon Sep 17 00:00:00 2001
-From: Kurt Mahan <kmahan@freescale.com>
-Date: Wed, 31 Oct 2007 16:41:41 -0600
-Subject: [PATCH] Add Coldfire specific header files.
-
-LTIBName: mcfv4e-coldfire-headers2
-Signed-off-by: Kurt Mahan <kmahan@freescale.com>
----
- include/asm-m68k/cf_cacheflush.h | 160 ++++++++++++++++
- include/asm-m68k/cf_entry.h | 146 +++++++++++++++
- include/asm-m68k/cf_pgalloc.h | 99 ++++++++++
- include/asm-m68k/cf_pgtable.h | 357 ++++++++++++++++++++++++++++++++++++
- include/asm-m68k/cf_tlbflush.h | 59 ++++++
- include/asm-m68k/cf_uaccess.h | 376 ++++++++++++++++++++++++++++++++++++++
- include/asm-m68k/cfcache.h | 86 +++++++++
- include/asm-m68k/cfmmu.h | 104 +++++++++++
- include/asm-m68k/coldfire.h | 38 ++++
- include/asm-m68k/coldfire_edma.h | 39 ++++
- include/asm-m68k/mcfqspi.h | 50 +++++
- include/asm-m68k/mcfsim.h | 96 ++++++++++
- include/asm-m68k/mcfuart.h | 180 ++++++++++++++++++
- 13 files changed, 1790 insertions(+), 0 deletions(-)
- create mode 100644 include/asm-m68k/cf_cacheflush.h
- create mode 100644 include/asm-m68k/cf_entry.h
- create mode 100644 include/asm-m68k/cf_pgalloc.h
- create mode 100644 include/asm-m68k/cf_pgtable.h
- create mode 100644 include/asm-m68k/cf_tlbflush.h
- create mode 100644 include/asm-m68k/cf_uaccess.h
- create mode 100644 include/asm-m68k/cfcache.h
- create mode 100644 include/asm-m68k/cfmmu.h
- create mode 100644 include/asm-m68k/coldfire.h
- create mode 100644 include/asm-m68k/coldfire_edma.h
- create mode 100644 include/asm-m68k/mcfqspi.h
- create mode 100644 include/asm-m68k/mcfsim.h
- create mode 100644 include/asm-m68k/mcfuart.h
-
---- /dev/null
-+++ b/include/asm-m68k/cf_cacheflush.h
-@@ -0,0 +1,160 @@
-+#ifndef M68K_CF_CACHEFLUSH_H
-+#define M68K_CF_CACHEFLUSH_H
-+
-+#include <asm/cfcache.h>
-+
-+/*
-+ * Cache handling functions
-+ */
-+
-+#define flush_icache() \
-+({ \
-+ unsigned long set; \
-+ unsigned long start_set; \
-+ unsigned long end_set; \
-+ \
-+ start_set = 0; \
-+ end_set = (unsigned long)LAST_DCACHE_ADDR; \
-+ \
-+ for (set = start_set; set <= end_set; set += (0x10 - 3)) \
-+ asm volatile("cpushl %%ic,(%0)\n" \
-+ "\taddq%.l #1,%0\n" \
-+ "\tcpushl %%ic,(%0)\n" \
-+ "\taddq%.l #1,%0\n" \
-+ "\tcpushl %%ic,(%0)\n" \
-+ "\taddq%.l #1,%0\n" \
-+ "\tcpushl %%ic,(%0)" : : "a" (set)); \
-+})
-+
-+/*
-+ * invalidate the cache for the specified memory range.
-+ * It starts at the physical address specified for
-+ * the given number of bytes.
-+ */
-+extern void cache_clear(unsigned long paddr, int len);
-+/*
-+ * push any dirty cache in the specified memory range.
-+ * It starts at the physical address specified for
-+ * the given number of bytes.
-+ */
-+extern void cache_push(unsigned long paddr, int len);
-+
-+/*
-+ * push and invalidate pages in the specified user virtual
-+ * memory range.
-+ */
-+extern void cache_push_v(unsigned long vaddr, int len);
-+
-+/* This is needed whenever the virtual mapping of the current
-+ process changes. */
-+
-+
-+#define flush_cache_all() do { } while (0)
-+#define flush_cache_mm(mm) do { } while (0)
-+#define flush_cache_range(mm, a, b) do { } while (0)
-+#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
-+
-+#define flush_dcache_range(paddr, len) do { } while (0)
-+
-+/* Push the page at kernel virtual address and clear the icache */
-+/* use cpush %bc instead of cpush %dc, cinv %ic */
-+#define flush_page_to_ram(page) __flush_page_to_ram((void *) page_address(page))
-+extern inline void __flush_page_to_ram(void *address)
-+{
-+ unsigned long set;
-+ unsigned long start_set;
-+ unsigned long end_set;
-+ unsigned long addr = (unsigned long) address;
-+
-+ addr &= ~(PAGE_SIZE - 1); /* round down to page start address */
-+
-+ start_set = addr & _ICACHE_SET_MASK;
-+ end_set = (addr + PAGE_SIZE-1) & _ICACHE_SET_MASK;
-+
-+ if (start_set > end_set) {
-+ /* from the begining to the lowest address */
-+ for (set = 0; set <= end_set; set += (0x10 - 3))
-+ asm volatile("cpushl %%bc,(%0)\n"
-+ "\taddq%.l #1,%0\n"
-+ "\tcpushl %%bc,(%0)\n"
-+ "\taddq%.l #1,%0\n"
-+ "\tcpushl %%bc,(%0)\n"
-+ "\taddq%.l #1,%0\n"
-+ "\tcpushl %%bc,(%0)" : : "a" (set));
-+
-+ /* next loop will finish the cache ie pass the hole */
-+ end_set = LAST_ICACHE_ADDR;
-+ }
-+ for (set = start_set; set <= end_set; set += (0x10 - 3))
-+ asm volatile("cpushl %%bc,(%0)\n"
-+ "\taddq%.l #1,%0\n"
-+ "\tcpushl %%bc,(%0)\n"
-+ "\taddq%.l #1,%0\n"
-+ "\tcpushl %%bc,(%0)\n"
-+ "\taddq%.l #1,%0\n"
-+ "\tcpushl %%bc,(%0)" : : "a" (set));
-+}
-+
-+#define flush_dcache_page(page) do { } while (0)
-+#define flush_icache_page(vma, pg) do { } while (0)
-+#define flush_icache_user_range(adr, len) do { } while (0)
-+/* NL */
-+#define flush_icache_user_page(vma, page, addr, len) do { } while (0)
-+
-+/* Push n pages at kernel virtual address and clear the icache */
-+/* use cpush %bc instead of cpush %dc, cinv %ic */
-+extern inline void flush_icache_range(unsigned long address,
-+ unsigned long endaddr)
-+{
-+ unsigned long set;
-+ unsigned long start_set;
-+ unsigned long end_set;
-+
-+ start_set = address & _ICACHE_SET_MASK;
-+ end_set = endaddr & _ICACHE_SET_MASK;
-+
-+ if (start_set > end_set) {
-+ /* from the begining to the lowest address */
-+ for (set = 0; set <= end_set; set += (0x10 - 3))
-+ asm volatile("cpushl %%ic,(%0)\n"
-+ "\taddq%.l #1,%0\n"
-+ "\tcpushl %%ic,(%0)\n"
-+ "\taddq%.l #1,%0\n"
-+ "\tcpushl %%ic,(%0)\n"
-+ "\taddq%.l #1,%0\n"
-+ "\tcpushl %%ic,(%0)" : : "a" (set));
-+
-+ /* next loop will finish the cache ie pass the hole */
-+ end_set = LAST_ICACHE_ADDR;
-+ }
-+ for (set = start_set; set <= end_set; set += (0x10 - 3))
-+ asm volatile("cpushl %%ic,(%0)\n"
-+ "\taddq%.l #1,%0\n"
-+ "\tcpushl %%ic,(%0)\n"
-+ "\taddq%.l #1,%0\n"
-+ "\tcpushl %%ic,(%0)\n"
-+ "\taddq%.l #1,%0\n"
-+ "\tcpushl %%ic,(%0)" : : "a" (set));
-+}
-+
-+static inline void copy_to_user_page(struct vm_area_struct *vma,
-+ struct page *page, unsigned long vaddr,
-+ void *dst, void *src, int len)
-+{
-+ memcpy(dst, src, len);
-+ flush_icache_user_page(vma, page, vaddr, len);
-+}
-+static inline void copy_from_user_page(struct vm_area_struct *vma,
-+ struct page *page, unsigned long vaddr,
-+ void *dst, void *src, int len)
-+{
-+ memcpy(dst, src, len);
-+}
-+
-+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
-+#define flush_cache_vmap(start, end) flush_cache_all()
-+#define flush_cache_vunmap(start, end) flush_cache_all()
-+#define flush_dcache_mmap_lock(mapping) do { } while (0)
-+#define flush_dcache_mmap_unlock(mapping) do { } while (0)
-+
-+#endif /* M68K_CF_CACHEFLUSH_H */
---- /dev/null
-+++ b/include/asm-m68k/cf_entry.h
-@@ -0,0 +1,146 @@
-+#ifndef __CF_M68K_ENTRY_H
-+#define __CF_M68K_ENTRY_H
-+
-+#include <asm/setup.h>
-+#include <asm/page.h>
-+#include <asm/coldfire.h>
-+#include <asm/cfmmu.h>
-+#include <asm/asm-offsets.h>
-+
-+/*
-+ * Stack layout in 'ret_from_exception':
-+ *
-+ * This allows access to the syscall arguments in registers d1-d5
-+ *
-+ * 0(sp) - d1
-+ * 4(sp) - d2
-+ * 8(sp) - d3
-+ * C(sp) - d4
-+ * 10(sp) - d5
-+ * 14(sp) - a0
-+ * 18(sp) - a1
-+ * 1C(sp) - a2
-+ * 20(sp) - d0
-+ * 24(sp) - orig_d0
-+ * 28(sp) - stack adjustment
-+ * 2C(sp) - sr
-+ * 2E(sp) - pc
-+ * 32(sp) - format & vector
-+ * 36(sp) - MMUSR
-+ * 3A(sp) - MMUAR
-+ */
-+
-+/*
-+ * 97/05/14 Andreas: Register %a2 is now set to the current task throughout
-+ * the whole kernel.
-+ */
-+
-+/* the following macro is used when enabling interrupts */
-+/* portable version */
-+#define ALLOWINT (~0x700)
-+#define MAX_NOINT_IPL 0
-+
-+#ifdef __ASSEMBLY__
-+
-+#define curptr a2
-+
-+LFLUSH_I_AND_D = 0x00000808
-+LSIGTRAP = 5
-+
-+/* process bits for task_struct.ptrace */
-+PT_TRACESYS_OFF = 3
-+PT_TRACESYS_BIT = 1
-+PT_PTRACED_OFF = 3
-+PT_PTRACED_BIT = 0
-+PT_DTRACE_OFF = 3
-+PT_DTRACE_BIT = 2
-+
-+#define SAVE_ALL_INT save_all_int
-+#define SAVE_ALL_SYS save_all_sys
-+#define RESTORE_ALL restore_all
-+/*
-+ * This defines the normal kernel pt-regs layout.
-+ *
-+ * regs a3-a6 and d6-d7 are preserved by C code
-+ * the kernel doesn't mess with usp unless it needs to
-+ */
-+
-+/*
-+ * a -1 in the orig_d0 field signifies
-+ * that the stack frame is NOT for syscall
-+ */
-+.macro save_all_int
-+ movel MMUSR,%sp@-
-+ movel MMUAR,%sp@-
-+ clrl %sp@- | stk_adj
-+ pea -1:w | orig d0
-+ movel %d0,%sp@- | d0
-+ subal #(8*4), %sp
-+ moveml %d1-%d5/%a0-%a1/%curptr,%sp@
-+.endm
-+
-+.macro save_all_sys
-+ movel MMUSR,%sp@-
-+ movel MMUAR,%sp@-
-+ clrl %sp@- | stk_adj
-+ movel %d0,%sp@- | orig d0
-+ movel %d0,%sp@- | d0
-+ subal #(8*4), %sp
-+ moveml %d1-%d5/%a0-%a1/%curptr,%sp@
-+.endm
-+
-+.macro restore_all
-+ moveml %sp@,%a0-%a1/%curptr/%d1-%d5
-+ addal #(8*4), %sp
-+ movel %sp@+,%d0 | d0
-+ addql #4,%sp | orig d0
-+ addl %sp@+,%sp | stk_adj
-+ addql #8,%sp | MMUAR & MMUSR
-+ rte
-+.endm
-+
-+#define SWITCH_STACK_SIZE (6*4+4) /* includes return address */
-+
-+#define SAVE_SWITCH_STACK save_switch_stack
-+#define RESTORE_SWITCH_STACK restore_switch_stack
-+#define GET_CURRENT(tmp) get_current tmp
-+
-+.macro save_switch_stack
-+ subal #(6*4), %sp
-+ moveml %a3-%a6/%d6-%d7,%sp@
-+.endm
-+
-+.macro restore_switch_stack
-+ moveml %sp@,%a3-%a6/%d6-%d7
-+ addal #(6*4), %sp
-+.endm
-+
-+.macro get_current reg=%d0
-+ movel %sp,\reg
-+ andl #-THREAD_SIZE,\reg
-+ movel \reg,%curptr
-+ movel %curptr@,%curptr
-+.endm
-+
-+#else /* C source */
-+
-+#define STR(X) STR1(X)
-+#define STR1(X) #X
-+
-+#define PT_OFF_ORIG_D0 0x24
-+#define PT_OFF_FORMATVEC 0x32
-+#define PT_OFF_SR 0x2C
-+#define SAVE_ALL_INT \
-+ "clrl %%sp@-;" /* stk_adj */ \
-+ "pea -1:w;" /* orig d0 = -1 */ \
-+ "movel %%d0,%%sp@-;" /* d0 */ \
-+ "subal #(8*4),%sp" \
-+ "moveml %%d1-%%d5/%%a0-%%a2,%%sp@"
-+#define GET_CURRENT(tmp) \
-+ "movel %%sp,"#tmp"\n\t" \
-+ "andw #-"STR(THREAD_SIZE)","#tmp"\n\t" \
-+ "movel "#tmp",%%a2\n\t"
-+
-+#endif
-+
-+#endif /* __CF_M68K_ENTRY_H */
---- /dev/null
-+++ b/include/asm-m68k/cf_pgalloc.h
-@@ -0,0 +1,99 @@
-+#ifndef M68K_CF_PGALLOC_H
-+#define M68K_CF_PGALLOC_H
-+
-+#include <asm/coldfire.h>
-+#include <asm/page.h>
-+#include <asm/cf_tlbflush.h>
-+
-+extern inline void pte_free_kernel(pte_t *pte)
-+{
-+ free_page((unsigned long) pte);
-+}
-+
-+extern const char bad_pmd_string[];
-+
-+extern inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
-+ unsigned long address)
-+{
-+ unsigned long page = __get_free_page(GFP_DMA|__GFP_REPEAT);
-+
-+ if (!page)
-+ return NULL;
-+
-+ memset((void *)page, 0, PAGE_SIZE);
-+ return (pte_t *) (page);
-+}
-+
-+extern inline pmd_t *pmd_alloc_kernel(pgd_t *pgd, unsigned long address)
-+{
-+ return (pmd_t *) pgd;
-+}
-+
-+#define pmd_alloc_one_fast(mm, address) ({ BUG(); ((pmd_t *)1); })
-+#define pmd_alloc_one(mm, address) ({ BUG(); ((pmd_t *)2); })
-+
-+#define pte_alloc_one_fast(mm, addr) pte_alloc_one(mm, addr)
-+
-+#define pmd_populate(mm, pmd, page) (pmd_val(*pmd) = \
-+ (unsigned long)(page_address(page)))
-+#define pmd_populate_kernel(mm, pmd, pte) (pmd_val(*pmd) = (unsigned long)(pte))
-+
-+static inline void __pte_free_tlb(struct mmu_gather *tlb, struct page *page)
-+{
-+ __free_page(page);
-+}
-+
-+#define __pmd_free_tlb(tlb, pmd) do { } while (0)
-+
-+static inline struct page *pte_alloc_one(struct mm_struct *mm,
-+ unsigned long address)
-+{
-+ struct page *page = alloc_pages(GFP_DMA|__GFP_REPEAT, 0);
-+ pte_t *pte;
-+
-+ if (!page)
-+ return NULL;
-+
-+ pte = kmap(page);
-+ if (pte) {
-+ clear_page(pte);
-+ __flush_page_to_ram(pte);
-+ flush_tlb_kernel_page(pte);
-+ nocache_page(pte);
-+ }
-+ kunmap(pte);
-+
-+ return page;
-+}
-+
-+extern inline void pte_free(struct page *page)
-+{
-+ __free_page(page);
-+}
-+
-+/*
-+ * In our implementation, each pgd entry contains 1 pmd that is never allocated
-+ * or freed. pgd_present is always 1, so this should never be called. -NL
-+ */
-+#define pmd_free(pmd) BUG()
-+
-+extern inline void pgd_free(pgd_t *pgd)
-+{
-+ free_page((unsigned long) pgd);
-+}
-+
-+extern inline pgd_t *pgd_alloc(struct mm_struct *mm)
-+{
-+ pgd_t *new_pgd;
-+
-+ new_pgd = (pgd_t *)__get_free_page(GFP_DMA | __GFP_NOWARN);
-+ if (!new_pgd)
-+ return NULL;
-+ memcpy(new_pgd, swapper_pg_dir, PAGE_SIZE);
-+ memset(new_pgd, 0, PAGE_OFFSET >> PGDIR_SHIFT);
-+ return new_pgd;
-+}
-+
-+#define pgd_populate(mm, pmd, pte) BUG()
-+
-+#endif /* M68K_CF_PGALLOC_H */
---- /dev/null
-+++ b/include/asm-m68k/cf_pgtable.h
-@@ -0,0 +1,357 @@
-+#ifndef _CF_PGTABLE_H
-+#define _CF_PGTABLE_H
-+
-+#include <asm/cfmmu.h>
-+#include <asm/page.h>
-+
-+#ifndef __ASSEMBLY__
-+#include <asm/virtconvert.h>
-+#include <linux/linkage.h>
-+
-+/* For virtual address to physical address conversion */
-+#define VTOP(addr) __pa(addr)
-+#define PTOV(addr) __va(addr)
-+
-+
-+#endif /* !__ASSEMBLY__ */
-+
-+/* Page protection values within PTE. */
-+
-+/* MMUDR bits, in proper place. */
-+#define CF_PAGE_LOCKED (0x00000002)
-+#define CF_PAGE_EXEC (0x00000004)
-+#define CF_PAGE_WRITABLE (0x00000008)
-+#define CF_PAGE_READABLE (0x00000010)
-+#define CF_PAGE_SYSTEM (0x00000020)
-+#define CF_PAGE_COPYBACK (0x00000040)
-+#define CF_PAGE_NOCACHE (0x00000080)
-+
-+#define CF_CACHEMASK (~0x00000040)
-+#define CF_PAGE_MMUDR_MASK (0x000000fe)
-+
-+#define _PAGE_NOCACHE030 (CF_PAGE_NOCACHE)
-+
-+/* MMUTR bits, need shifting down. */
-+#define CF_PAGE_VALID (0x00000400)
-+#define CF_PAGE_SHARED (0x00000800)
-+
-+#define CF_PAGE_MMUTR_MASK (0x00000c00)
-+#define CF_PAGE_MMUTR_SHIFT (10)
-+#define CF_ASID_MMU_SHIFT (2)
-+
-+/* Fake bits, not implemented in CF, will get masked out before
-+ hitting hardware, and might go away altogether once this port is
-+ complete. */
-+#if PAGE_SHIFT < 13
-+#error COLDFIRE Error: Pages must be at least 8k in size
-+#endif
-+#define CF_PAGE_ACCESSED (0x00001000)
-+#define CF_PAGE_FILE (0x00000200)
-+#define CF_PAGE_DIRTY (0x00000001)
-+
-+#define _PAGE_CACHE040 0x020 /* 68040 cache mode, cachable, copyback */
-+#define _PAGE_NOCACHE_S 0x040 /* 68040 no-cache mode, serialized */
-+#define _PAGE_NOCACHE 0x060 /* 68040 cache mode, non-serialized */
-+#define _PAGE_CACHE040W 0x000 /* 68040 cache mode, cachable, write-through */
-+#define _DESCTYPE_MASK 0x003
-+#define _CACHEMASK040 (~0x060)
-+#define _PAGE_GLOBAL040 0x400 /* 68040 global bit, used for kva descs */
-+
-+
-+/* Externally used page protection values. */
-+#define _PAGE_PRESENT (CF_PAGE_VALID)
-+#define _PAGE_ACCESSED (CF_PAGE_ACCESSED)
-+#define _PAGE_DIRTY (CF_PAGE_DIRTY)
-+#define _PAGE_READWRITE (CF_PAGE_WRITABLE \
-+ | CF_PAGE_READABLE \
-+ | CF_PAGE_SYSTEM \
-+ | CF_PAGE_SHARED)
-+
-+/* Compound page protection values. */
-+#define PAGE_NONE __pgprot(CF_PAGE_VALID \
-+ | CF_PAGE_ACCESSED)
-+
-+#define PAGE_SHARED __pgprot(CF_PAGE_VALID \
-+ | CF_PAGE_ACCESSED \
-+ | CF_PAGE_SHARED)
-+
-+#define PAGE_INIT __pgprot(CF_PAGE_VALID \
-+ | CF_PAGE_WRITABLE \
-+ | CF_PAGE_READABLE \
-+ | CF_PAGE_EXEC \
-+ | CF_PAGE_SYSTEM \
-+ | CF_PAGE_SHARED)
-+
-+#define PAGE_KERNEL __pgprot(CF_PAGE_VALID \
-+ | CF_PAGE_WRITABLE \
-+ | CF_PAGE_READABLE \
-+ | CF_PAGE_EXEC \
-+ | CF_PAGE_SYSTEM \
-+ | CF_PAGE_SHARED \
-+ | CF_PAGE_ACCESSED)
-+
-+#define PAGE_COPY __pgprot(CF_PAGE_VALID \
-+ | CF_PAGE_ACCESSED \
-+ | CF_PAGE_READABLE \
-+ | CF_PAGE_DIRTY)
-+/*
-+ * Page protections for initialising protection_map. See mm/mmap.c
-+ * for use. In general, the bit positions are xwr, and P-items are
-+ * private, the S-items are shared.
-+ */
-+
-+#define __P000 PAGE_NONE
-+#define __P100 __pgprot(CF_PAGE_VALID \
-+ | CF_PAGE_ACCESSED \
-+ | CF_PAGE_EXEC)
-+#define __P010 __pgprot(CF_PAGE_VALID \
-+ | CF_PAGE_WRITABLE \
-+ | CF_PAGE_ACCESSED)
-+#define __P110 __pgprot(CF_PAGE_VALID \
-+ | CF_PAGE_ACCESSED \
-+ | CF_PAGE_WRITABLE \
-+ | CF_PAGE_EXEC)
-+#define __P001 __pgprot(CF_PAGE_VALID \
-+ | CF_PAGE_ACCESSED \
-+ | CF_PAGE_READABLE)
-+#define __P101 __pgprot(CF_PAGE_VALID \
-+ | CF_PAGE_ACCESSED \
-+ | CF_PAGE_READABLE \
-+ | CF_PAGE_EXEC)
-+#define __P011 __pgprot(CF_PAGE_VALID \
-+ | CF_PAGE_READABLE \
-+ | CF_PAGE_WRITABLE \
-+ | CF_PAGE_ACCESSED)
-+#define __P111 __pgprot(CF_PAGE_VALID \
-+ | CF_PAGE_ACCESSED \
-+ | CF_PAGE_WRITABLE \
-+ | CF_PAGE_READABLE \
-+ | CF_PAGE_EXEC)
-+
-+#define __S000 PAGE_NONE
-+#define __S100 __pgprot(CF_PAGE_VALID \
-+ | CF_PAGE_ACCESSED \
-+ | CF_PAGE_SHARED \
-+ | CF_PAGE_EXEC)
-+#define __S010 PAGE_SHARED
-+#define __S110 __pgprot(CF_PAGE_VALID \
-+ | CF_PAGE_ACCESSED \
-+ | CF_PAGE_SHARED \
-+ | CF_PAGE_EXEC)
-+#define __S001 __pgprot(CF_PAGE_VALID \
-+ | CF_PAGE_ACCESSED \
-+ | CF_PAGE_SHARED \
-+ | CF_PAGE_READABLE)
-+#define __S101 __pgprot(CF_PAGE_VALID \
-+ | CF_PAGE_ACCESSED \
-+ | CF_PAGE_SHARED \
-+ | CF_PAGE_READABLE \
-+ | CF_PAGE_EXEC)
-+#define __S011 __pgprot(CF_PAGE_VALID \
-+ | CF_PAGE_ACCESSED \
-+ | CF_PAGE_SHARED \
-+ | CF_PAGE_READABLE)
-+#define __S111 __pgprot(CF_PAGE_VALID \
-+ | CF_PAGE_ACCESSED \
-+ | CF_PAGE_SHARED \
-+ | CF_PAGE_READABLE \
-+ | CF_PAGE_EXEC)
-+
-+#define PTE_MASK PAGE_MASK
-+#define CF_PAGE_CHG_MASK (PTE_MASK | CF_PAGE_ACCESSED | CF_PAGE_DIRTY)
-+
-+#ifndef __ASSEMBLY__
-+
-+/*
-+ * Conversion functions: convert a page and protection to a page entry,
-+ * and a page entry and page directory to the page they refer to.
-+ */
-+#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
-+
-+extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
-+{
-+ pte_val(pte) = (pte_val(pte) & CF_PAGE_CHG_MASK) | pgprot_val(newprot);
-+ return pte;
-+}
-+
-+#define pmd_set(pmdp, ptep) do {} while (0)
-+
-+extern inline void pgd_set(pgd_t *pgdp, pmd_t *pmdp)
-+{
-+ pgd_val(*pgdp) = virt_to_phys(pmdp);
-+}
-+
-+#define __pte_page(pte) \
-+ ((unsigned long) ((pte_val(pte) & CF_PAGE_PGNUM_MASK) + PAGE_OFFSET))
-+#define __pmd_page(pmd) ((unsigned long) (pmd_val(pmd)))
-+
-+extern inline int pte_none(pte_t pte)
-+{
-+ return !pte_val(pte);
-+}
-+extern inline int pte_present(pte_t pte)
-+{
-+ return pte_val(pte) & CF_PAGE_VALID;
-+}
-+extern inline void pte_clear(struct mm_struct *mm, unsigned long addr,
-+ pte_t *ptep)
-+{
-+ pte_val(*ptep) = 0;
-+}
-+
-+#define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT)
-+#define pte_page(pte) virt_to_page(__pte_page(pte))
-+
-+extern inline int pmd_none2(pmd_t *pmd) { return !pmd_val(*pmd); }
-+#define pmd_none(pmd) pmd_none2(&(pmd))
-+extern inline int pmd_bad2(pmd_t *pmd) { return 0; }
-+#define pmd_bad(pmd) pmd_bad2(&(pmd))
-+#define pmd_present(pmd) (!pmd_none2(&(pmd)))
-+extern inline void pmd_clear(pmd_t *pmdp) { pmd_val(*pmdp) = 0; }
-+
-+extern inline int pgd_none(pgd_t pgd) { return 0; }
-+extern inline int pgd_bad(pgd_t pgd) { return 0; }
-+extern inline int pgd_present(pgd_t pgd) { return 1; }
-+extern inline void pgd_clear(pgd_t *pgdp) {}
-+
-+
-+#define pte_ERROR(e) \
-+ printk(KERN_ERR "%s:%d: bad pte %08lx.\n", \
-+ __FILE__, __LINE__, pte_val(e))
-+#define pmd_ERROR(e) \
-+ printk(KERN_ERR "%s:%d: bad pmd %08lx.\n", \
-+ __FILE__, __LINE__, pmd_val(e))
-+#define pgd_ERROR(e) \
-+ printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \
-+ __FILE__, __LINE__, pgd_val(e))
-+
-+
-+/*
-+ * The following only work if pte_present() is true.
-+ * Undefined behaviour if not...
-+ * [we have the full set here even if they don't change from m68k]
-+ */
-+extern inline int pte_read(pte_t pte) \
-+ { return pte_val(pte) & CF_PAGE_READABLE; }
-+extern inline int pte_write(pte_t pte) \
-+ { return pte_val(pte) & CF_PAGE_WRITABLE; }
-+extern inline int pte_exec(pte_t pte) \
-+ { return pte_val(pte) & CF_PAGE_EXEC; }
-+extern inline int pte_dirty(pte_t pte) \
-+ { return pte_val(pte) & CF_PAGE_DIRTY; }
-+extern inline int pte_young(pte_t pte) \
-+ { return pte_val(pte) & CF_PAGE_ACCESSED; }
-+extern inline int pte_file(pte_t pte) \
-+ { return pte_val(pte) & CF_PAGE_FILE; }
-+
-+extern inline pte_t pte_wrprotect(pte_t pte) \
-+ { pte_val(pte) &= ~CF_PAGE_WRITABLE; return pte; }
-+extern inline pte_t pte_rdprotect(pte_t pte) \
-+ { pte_val(pte) &= ~CF_PAGE_READABLE; return pte; }
-+extern inline pte_t pte_exprotect(pte_t pte) \
-+ { pte_val(pte) &= ~CF_PAGE_EXEC; return pte; }
-+extern inline pte_t pte_mkclean(pte_t pte) \
-+ { pte_val(pte) &= ~CF_PAGE_DIRTY; return pte; }
-+extern inline pte_t pte_mkold(pte_t pte) \
-+ { pte_val(pte) &= ~CF_PAGE_ACCESSED; return pte; }
-+extern inline pte_t pte_mkwrite(pte_t pte) \
-+ { pte_val(pte) |= CF_PAGE_WRITABLE; return pte; }
-+extern inline pte_t pte_mkread(pte_t pte) \
-+ { pte_val(pte) |= CF_PAGE_READABLE; return pte; }
-+extern inline pte_t pte_mkexec(pte_t pte) \
-+ { pte_val(pte) |= CF_PAGE_EXEC; return pte; }
-+extern inline pte_t pte_mkdirty(pte_t pte) \
-+ { pte_val(pte) |= CF_PAGE_DIRTY; return pte; }
-+extern inline pte_t pte_mkyoung(pte_t pte) \
-+ { pte_val(pte) |= CF_PAGE_ACCESSED; return pte; }
-+extern inline pte_t pte_mknocache(pte_t pte) \
-+ { pte_val(pte) |= 0x80 | (pte_val(pte) & ~0x40); return pte; }
-+extern inline pte_t pte_mkcache(pte_t pte) \
-+ { pte_val(pte) &= ~CF_PAGE_NOCACHE; return pte; }
-+
-+#define swapper_pg_dir kernel_pg_dir
-+extern pgd_t kernel_pg_dir[PTRS_PER_PGD];
-+
-+/* Find an entry in a pagetable directory. */
-+#define pgd_index(address) ((address) >> PGDIR_SHIFT)
-+
-+#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
-+
-+/* Find an entry in a kernel pagetable directory. */
-+#define pgd_offset_k(address) pgd_offset(&init_mm, address)
-+
-+/* Find an entry in the second-level pagetable. */
-+extern inline pmd_t *pmd_offset(pgd_t *pgd, unsigned long address)
-+{
-+ return (pmd_t *) pgd;
-+}
-+
-+/* Find an entry in the third-level pagetable. */
-+#define __pte_offset(address) ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
-+#define pte_offset_kernel(dir, address) ((pte_t *) __pmd_page(*(dir)) + \
-+ __pte_offset(address))
-+
-+/* Disable caching for page at given kernel virtual address. */
-+static inline void nocache_page(void *vaddr)
-+{
-+ pgd_t *dir;
-+ pmd_t *pmdp;
-+ pte_t *ptep;
-+ unsigned long addr = (unsigned long)vaddr;
-+
-+ dir = pgd_offset_k(addr);
-+ pmdp = pmd_offset(dir, addr);
-+ ptep = pte_offset_kernel(pmdp, addr);
-+ *ptep = pte_mknocache(*ptep);
-+}
-+
-+/* Enable caching for page at given kernel virtual address. */
-+static inline void cache_page(void *vaddr)
-+{
-+ pgd_t *dir;
-+ pmd_t *pmdp;
-+ pte_t *ptep;
-+ unsigned long addr = (unsigned long)vaddr;
-+
-+ dir = pgd_offset_k(addr);
-+ pmdp = pmd_offset(dir, addr);
-+ ptep = pte_offset_kernel(pmdp, addr);
-+ *ptep = pte_mkcache(*ptep);
-+}
-+
-+#define PTE_FILE_MAX_BITS 21
-+#define PTE_FILE_SHIFT 11
-+
-+static inline unsigned long pte_to_pgoff(pte_t pte)
-+{
-+ return pte_val(pte) >> PTE_FILE_SHIFT;
-+}
-+
-+static inline pte_t pgoff_to_pte(unsigned pgoff)
-+{
-+ pte_t pte = __pte((pgoff << PTE_FILE_SHIFT) + CF_PAGE_FILE);
-+ return pte;
-+}
-+
-+/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */
-+#define __swp_entry(type, offset) ((swp_entry_t) { (type) | \
-+ (offset << PTE_FILE_SHIFT) })
-+#define __swp_type(x) ((x).val & 0xFF)
-+#define __swp_offset(x) ((x).val >> PTE_FILE_SHIFT)
-+#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
-+#define __swp_entry_to_pte(x) (__pte((x).val))
-+
-+#define pmd_page(pmd) virt_to_page(__pmd_page(pmd))
-+
-+#define pte_offset_map(pmdp, address) ((pte_t *)__pmd_page(*pmdp) + \
-+ __pte_offset(address))
-+#define pte_offset_map_nested(pmdp, address) pte_offset_map(pmdp, address)
-+#define pte_unmap(pte) kunmap(pte)
-+#define pte_unmap_nested(pte) kunmap(pte)
-+
-+#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
-+#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
-+
-+
-+#endif /* !__ASSEMBLY__ */
-+#endif /* !_CF_PGTABLE_H */
---- /dev/null
-+++ b/include/asm-m68k/cf_tlbflush.h
-@@ -0,0 +1,59 @@
-+#ifndef M68K_CF_TLBFLUSH_H
-+#define M68K_CF_TLBFLUSH_H
-+
-+#include <asm/coldfire.h>
-+
-+/* Flush all userspace mappings. */
-+static inline void flush_tlb_all(void)
-+{
-+ preempt_disable();
-+ *MMUOR = MMUOR_CNL;
-+ preempt_enable();
-+}
-+
-+/* Clear user TLB entries within the context named in mm */
-+static inline void flush_tlb_mm(struct mm_struct *mm)
-+{
-+ preempt_disable();
-+ *MMUOR = MMUOR_CNL;
-+ preempt_enable();
-+}
-+
-+/* Flush a single TLB page. */
-+static inline void flush_tlb_page(struct vm_area_struct *vma,
-+ unsigned long addr)
-+{
-+ preempt_disable();
-+ *MMUOR = MMUOR_CNL;
-+ preempt_enable();
-+}
-+/* Flush a range of pages from TLB. */
-+
-+static inline void flush_tlb_range(struct mm_struct *mm,
-+ unsigned long start, unsigned long end)
-+{
-+ preempt_disable();
-+ *MMUOR = MMUOR_CNL;
-+ preempt_enable();
-+}
-+
-+/* Flush kernel page from TLB. */
-+static inline void flush_tlb_kernel_page(void *addr)
-+{
-+ preempt_disable();
-+ *MMUOR = MMUOR_CNL;
-+ preempt_enable();
-+}
-+
-+static inline void flush_tlb_kernel_range(unsigned long start,
-+ unsigned long end)
-+{
-+ flush_tlb_all();
-+}
-+
-+extern inline void flush_tlb_pgtables(struct mm_struct *mm,
-+ unsigned long start, unsigned long end)
-+{
-+}
-+
-+#endif /* M68K_CF_TLBFLUSH_H */
---- /dev/null
-+++ b/include/asm-m68k/cf_uaccess.h
-@@ -0,0 +1,376 @@
-+#ifndef __M68K_CF_UACCESS_H
-+#define __M68K_CF_UACCESS_H
-+
-+/*
-+ * User space memory access functions
-+ */
-+
-+/* The "moves" command is not available in the CF instruction set. */
-+#include <linux/compiler.h>
-+#include <linux/errno.h>
-+#include <linux/types.h>
-+#include <linux/sched.h>
-+#include <asm/segment.h>
-+
-+#define VERIFY_READ 0
-+#define VERIFY_WRITE 1
-+
-+/* We let the MMU do all checking */
-+#define access_ok(type, addr, size) 1
-+
-+/*
-+ * The exception table consists of pairs of addresses: the first is the
-+ * address of an instruction that is allowed to fault, and the second is
-+ * the address at which the program should continue. No registers are
-+ * modified, so it is entirely up to the continuation code to figure out
-+ * what to do.
-+ *
-+ * All the routines below use bits of fixup code that are out of line
-+ * with the main instruction path. This means when everything is well,
-+ * we don't even have to jump over them. Further, they do not intrude
-+ * on our cache or tlb entries.
-+ */
-+
-+struct exception_table_entry
-+{
-+ unsigned long insn, fixup;
-+};
-+
-+extern int __put_user_bad(void);
-+extern int __get_user_bad(void);
-+
-+#define __put_user_asm(res, x, ptr, bwl, reg, err) \
-+asm volatile ("\n" \
-+ "1: move."#bwl" %2,%1\n" \
-+ "2:\n" \
-+ " .section .fixup,\"ax\"\n" \
-+ " .even\n" \
-+ "10: moveq.l %3,%0\n" \
-+ " jra 2b\n" \
-+ " .previous\n" \
-+ "\n" \
-+ " .section __ex_table,\"a\"\n" \
-+ " .align 4\n" \
-+ " .long 1b,10b\n" \
-+ " .long 2b,10b\n" \
-+ " .previous" \
-+ : "+d" (res), "=m" (*(ptr)) \
-+ : #reg (x), "i" (err))
-+
-+/*
-+ * These are the main single-value transfer routines. They automatically
-+ * use the right size if we just have the right pointer type.
-+ */
-+
-+#define __put_user(x, ptr) \
-+({ \
-+ typeof(*(ptr)) __pu_val = (x); \
-+ int __pu_err = 0; \
-+ __chk_user_ptr(ptr); \
-+ switch (sizeof (*(ptr))) { \
-+ case 1: \
-+ __put_user_asm(__pu_err, __pu_val, ptr, b, d, -EFAULT); \
-+ break; \
-+ case 2: \
-+ __put_user_asm(__pu_err, __pu_val, ptr, w, d, -EFAULT); \
-+ break; \
-+ case 4: \
-+ __put_user_asm(__pu_err, __pu_val, ptr, l, r, -EFAULT); \
-+ break; \
-+ case 8: \
-+ { \
-+ const void __user *__pu_ptr = (ptr); \
-+ asm volatile ("\n" \
-+ "1: move.l %2,(%1)+\n" \
-+ "2: move.l %R2,(%1)\n" \
-+ "3:\n" \
-+ " .section .fixup,\"ax\"\n" \
-+ " .even\n" \
-+ "10: movel %3,%0\n" \
-+ " jra 3b\n" \
-+ " .previous\n" \
-+ "\n" \
-+ " .section __ex_table,\"a\"\n" \
-+ " .align 4\n" \
-+ " .long 1b,10b\n" \
-+ " .long 2b,10b\n" \
-+ " .long 3b,10b\n" \
-+ " .previous" \
-+ : "+d" (__pu_err), "+a" (__pu_ptr) \
-+ : "r" (__pu_val), "i" (-EFAULT) \
-+ : "memory"); \
-+ break; \
-+ } \
-+ default: \
-+ __pu_err = __put_user_bad(); \
-+ break; \
-+ } \
-+ __pu_err; \
-+})
-+#define put_user(x, ptr) __put_user(x, ptr)
-+
-+
-+#define __get_user_asm(res, x, ptr, type, bwl, reg, err) ({ \
-+ type __gu_val; \
-+ asm volatile ("\n" \
-+ "1: move."#bwl" %2,%1\n" \
-+ "2:\n" \
-+ " .section .fixup,\"ax\"\n" \
-+ " .even\n" \
-+ "10: move.l %3,%0\n" \
-+ " subl %1,%1\n" \
-+ " jra 2b\n" \
-+ " .previous\n" \
-+ "\n" \
-+ " .section __ex_table,\"a\"\n" \
-+ " .align 4\n" \
-+ " .long 1b,10b\n" \
-+ " .previous" \
-+ : "+d" (res), "=&" #reg (__gu_val) \
-+ : "m" (*(ptr)), "i" (err)); \
-+ (x) = (typeof(*(ptr)))(unsigned long)__gu_val; \
-+})
-+
-+#define __get_user(x, ptr) \
-+({ \
-+ int __gu_err = 0; \
-+ __chk_user_ptr(ptr); \
-+ switch (sizeof(*(ptr))) { \
-+ case 1: \
-+ __get_user_asm(__gu_err, x, ptr, u8, b, d, -EFAULT); \
-+ break; \
-+ case 2: \
-+ __get_user_asm(__gu_err, x, ptr, u16, w, d, -EFAULT); \
-+ break; \
-+ case 4: \
-+ __get_user_asm(__gu_err, x, ptr, u32, l, r, -EFAULT); \
-+ break; \
-+/* case 8: disabled because gcc-4.1 has a broken typeof \
-+ { \
-+ const void *__gu_ptr = (ptr); \
-+ u64 __gu_val; \
-+ asm volatile ("\n" \
-+ "1: move.l (%2)+,%1\n" \
-+ "2: move.l (%2),%R1\n" \
-+ "3:\n" \
-+ " .section .fixup,\"ax\"\n" \
-+ " .even\n" \
-+ "10: move.l %3,%0\n" \
-+ " subl %1,%1\n" \
-+ " subl %R1,%R1\n" \
-+ " jra 3b\n" \
-+ " .previous\n" \
-+ "\n" \
-+ " .section __ex_table,\"a\"\n" \
-+ " .align 4\n" \
-+ " .long 1b,10b\n" \
-+ " .long 2b,10b\n" \
-+ " .previous" \
-+ : "+d" (__gu_err), "=&r" (__gu_val), \
-+ "+a" (__gu_ptr) \
-+ : "i" (-EFAULT) \
-+ : "memory"); \
-+ (x) = (typeof(*(ptr)))__gu_val; \
-+ break; \
-+ } */ \
-+ default: \
-+ __gu_err = __get_user_bad(); \
-+ break; \
-+ } \
-+ __gu_err; \
-+})
-+#define get_user(x, ptr) __get_user(x, ptr)
-+
-+unsigned long __generic_copy_from_user(void *to, const void __user *from,
-+ unsigned long n);
-+unsigned long __generic_copy_to_user(void __user *to, const void *from,
-+ unsigned long n);
-+
-+#define __constant_copy_from_user_asm(res, to, from, tmp, n, s1, s2, s3)\
-+ asm volatile ("\n" \
-+ "1: move."#s1" (%2)+,%3\n" \
-+ " move."#s1" %3,(%1)+\n" \
-+ "2: move."#s2" (%2)+,%3\n" \
-+ " move."#s2" %3,(%1)+\n" \
-+ " .ifnc \""#s3"\",\"\"\n" \
-+ "3: move."#s3" (%2)+,%3\n" \
-+ " move."#s3" %3,(%1)+\n" \
-+ " .endif\n" \
-+ "4:\n" \
-+ " .section __ex_table,\"a\"\n" \
-+ " .align 4\n" \
-+ " .long 1b,10f\n" \
-+ " .long 2b,20f\n" \
-+ " .ifnc \""#s3"\",\"\"\n" \
-+ " .long 3b,30f\n" \
-+ " .endif\n" \
-+ " .previous\n" \
-+ "\n" \
-+ " .section .fixup,\"ax\"\n" \
-+ " .even\n" \
-+ "10: clr."#s1" (%1)+\n" \
-+ "20: clr."#s2" (%1)+\n" \
-+ " .ifnc \""#s3"\",\"\"\n" \
-+ "30: clr."#s3" (%1)+\n" \
-+ " .endif\n" \
-+ " moveq.l #"#n",%0\n" \
-+ " jra 4b\n" \
-+ " .previous\n" \
-+ : "+d" (res), "+&a" (to), "+a" (from), "=&d" (tmp) \
-+ : : "memory")
-+
-+static __always_inline unsigned long
-+__constant_copy_from_user(void *to, const void __user *from, unsigned long n)
-+{
-+ unsigned long res = 0, tmp;
-+
-+ switch (n) {
-+ case 1:
-+ __get_user_asm(res, *(u8 *)to, (u8 __user *)from, u8, b, d, 1);
-+ break;
-+ case 2:
-+ __get_user_asm(res, *(u16 *)to, (u16 __user *)from, u16, w,
-+ d, 2);
-+ break;
-+ case 3:
-+ __constant_copy_from_user_asm(res, to, from, tmp, 3, w, b,);
-+ break;
-+ case 4:
-+ __get_user_asm(res, *(u32 *)to, (u32 __user *)from, u32, l,
-+ r, 4);
-+ break;
-+ case 5:
-+ __constant_copy_from_user_asm(res, to, from, tmp, 5, l, b,);
-+ break;
-+ case 6:
-+ __constant_copy_from_user_asm(res, to, from, tmp, 6, l, w,);
-+ break;
-+ case 7:
-+ __constant_copy_from_user_asm(res, to, from, tmp, 7, l, w, b);
-+ break;
-+ case 8:
-+ __constant_copy_from_user_asm(res, to, from, tmp, 8, l, l,);
-+ break;
-+ case 9:
-+ __constant_copy_from_user_asm(res, to, from, tmp, 9, l, l, b);
-+ break;
-+ case 10:
-+ __constant_copy_from_user_asm(res, to, from, tmp, 10, l, l, w);
-+ break;
-+ case 12:
-+ __constant_copy_from_user_asm(res, to, from, tmp, 12, l, l, l);
-+ break;
-+ default:
-+ /* we limit the inlined version to 3 moves */
-+ return __generic_copy_from_user(to, from, n);
-+ }
-+
-+ return res;
-+}
-+
-+#define __constant_copy_to_user_asm(res, to, from, tmp, n, s1, s2, s3) \
-+ asm volatile ("\n" \
-+ " move."#s1" (%2)+,%3\n" \
-+ "11: move."#s1" %3,(%1)+\n" \
-+ "12: move."#s2" (%2)+,%3\n" \
-+ "21: move."#s2" %3,(%1)+\n" \
-+ "22:\n" \
-+ " .ifnc \""#s3"\",\"\"\n" \
-+ " move."#s3" (%2)+,%3\n" \
-+ "31: move."#s3" %3,(%1)+\n" \
-+ "32:\n" \
-+ " .endif\n" \
-+ "4:\n" \
-+ "\n" \
-+ " .section __ex_table,\"a\"\n" \
-+ " .align 4\n" \
-+ " .long 11b,5f\n" \
-+ " .long 12b,5f\n" \
-+ " .long 21b,5f\n" \
-+ " .long 22b,5f\n" \
-+ " .ifnc \""#s3"\",\"\"\n" \
-+ " .long 31b,5f\n" \
-+ " .long 32b,5f\n" \
-+ " .endif\n" \
-+ " .previous\n" \
-+ "\n" \
-+ " .section .fixup,\"ax\"\n" \
-+ " .even\n" \
-+ "5: moveq.l #"#n",%0\n" \
-+ " jra 4b\n" \
-+ " .previous\n" \
-+ : "+d" (res), "+a" (to), "+a" (from), "=&d" (tmp) \
-+ : : "memory")
-+
-+static __always_inline unsigned long
-+__constant_copy_to_user(void __user *to, const void *from, unsigned long n)
-+{
-+ unsigned long res = 0, tmp;
-+
-+ switch (n) {
-+ case 1:
-+ __put_user_asm(res, *(u8 *)from, (u8 __user *)to, b, d, 1);
-+ break;
-+ case 2:
-+ __put_user_asm(res, *(u16 *)from, (u16 __user *)to, w, d, 2);
-+ break;
-+ case 3:
-+ __constant_copy_to_user_asm(res, to, from, tmp, 3, w, b,);
-+ break;
-+ case 4:
-+ __put_user_asm(res, *(u32 *)from, (u32 __user *)to, l, r, 4);
-+ break;
-+ case 5:
-+ __constant_copy_to_user_asm(res, to, from, tmp, 5, l, b,);
-+ break;
-+ case 6:
-+ __constant_copy_to_user_asm(res, to, from, tmp, 6, l, w,);
-+ break;
-+ case 7:
-+ __constant_copy_to_user_asm(res, to, from, tmp, 7, l, w, b);
-+ break;
-+ case 8:
-+ __constant_copy_to_user_asm(res, to, from, tmp, 8, l, l,);
-+ break;
-+ case 9:
-+ __constant_copy_to_user_asm(res, to, from, tmp, 9, l, l, b);
-+ break;
-+ case 10:
-+ __constant_copy_to_user_asm(res, to, from, tmp, 10, l, l, w);
-+ break;
-+ case 12:
-+ __constant_copy_to_user_asm(res, to, from, tmp, 12, l, l, l);
-+ break;
-+ default:
-+ /* limit the inlined version to 3 moves */
-+ return __generic_copy_to_user(to, from, n);
-+ }
-+
-+ return res;
-+}
-+
-+#define __copy_from_user(to, from, n) \
-+(__builtin_constant_p(n) ? \
-+ __constant_copy_from_user(to, from, n) : \
-+ __generic_copy_from_user(to, from, n))
-+
-+#define __copy_to_user(to, from, n) \
-+(__builtin_constant_p(n) ? \
-+ __constant_copy_to_user(to, from, n) : \
-+ __generic_copy_to_user(to, from, n))
-+
-+#define __copy_to_user_inatomic __copy_to_user
-+#define __copy_from_user_inatomic __copy_from_user
-+
-+#define copy_from_user(to, from, n) __copy_from_user(to, from, n)
-+#define copy_to_user(to, from, n) __copy_to_user(to, from, n)
-+
-+long strncpy_from_user(char *dst, const char __user *src, long count);
-+long strnlen_user(const char __user *src, long n);
-+unsigned long __clear_user(void __user *to, unsigned long n);
-+
-+#define clear_user __clear_user
-+
-+#define strlen_user(str) strnlen_user(str, 32767)
-+
-+#endif /* _M68K_CF_UACCESS_H */
---- /dev/null
-+++ b/include/asm-m68k/cfcache.h
-@@ -0,0 +1,86 @@
-+/*
-+ * include/asm-m68k/cfcache.h
-+ */
-+#ifndef CF_CFCACHE_H
-+#define CF_CFCACHE_H
-+
-+#define CF_CACR_DEC (0x80000000) /* Data Cache Enable */
-+#define CF_CACR_DW (0x40000000) /* Data default Write-protect */
-+#define CF_CACR_DESB (0x20000000) /* Data Enable Store Buffer */
-+#define CF_CACR_DDPI (0x10000000) /* Data Disable CPUSHL Invalidate */
-+#define CF_CACR_DHLCK (0x08000000) /* 1/2 Data Cache Lock Mode */
-+#define CF_CACR_DDCM_00 (0x00000000) /* Cacheable writethrough imprecise */
-+#define CF_CACR_DDCM_01 (0x02000000) /* Cacheable copyback */
-+#define CF_CACR_DDCM_10 (0x04000000) /* Noncacheable precise */
-+#define CF_CACR_DDCM_11 (0x06000000) /* Noncacheable imprecise */
-+#define CF_CACR_DCINVA (0x01000000) /* Data Cache Invalidate All */
-+#define CF_CACR_IVO (0x00100000) /* Invalidate only */
-+#define CF_CACR_BEC (0x00080000) /* Branch Cache Enable */
-+#define CF_CACR_BCINVA (0x00040000) /* Branch Cache Invalidate All */
-+#define CF_CACR_IEC (0x00008000) /* Instruction Cache Enable */
-+#define CF_CACR_SPA (0x00004000) /* Search by Physical Address */
-+#define CF_CACR_DNFB (0x00002000) /* Default cache-inhibited fill buf */
-+#define CF_CACR_IDPI (0x00001000) /* Instr Disable CPUSHL Invalidate */
-+#define CF_CACR_IHLCK (0x00000800) /* 1/2 Instruction Cache Lock Mode */
-+#define CF_CACR_IDCM (0x00000400) /* Noncacheable Instr default mode */
-+#define CF_CACR_ICINVA (0x00000100) /* Instr Cache Invalidate All */
-+#define CF_CACR_EUSP (0x00000020) /* Switch stacks in user mode */
-+
-+#define DCACHE_LINE_SIZE 0x0010 /* bytes per line */
-+#define DCACHE_WAY_SIZE 0x2000 /* words per cache block */
-+#define CACHE_DISABLE_MODE (CF_CACR_DCINVA+CF_CACR_BCINVA+CF_CACR_ICINVA)
-+#ifdef CONFIG_M5445X_DISABLE_CACHE
-+/* disable cache for testing rev0 silicon */
-+#define CACHE_INITIAL_MODE (CF_CACR_EUSP)
-+#else
-+#define CACHE_INITIAL_MODE (CF_CACR_DEC+CF_CACR_BEC+CF_CACR_IEC+CF_CACR_EUSP)
-+#endif
-+
-+#define _DCACHE_SIZE (2*16384)
-+#define _ICACHE_SIZE (2*16384)
-+
-+#define _SET_SHIFT 4
-+
-+/*
-+ * Masks for cache sizes. Programming note: because the set size is a
-+ * power of two, the mask is also the last address in the set.
-+ * This may need to be #ifdef for other Coldfire processors.
-+ */
-+
-+#define _DCACHE_SET_MASK ((_DCACHE_SIZE/64-1)<<_SET_SHIFT)
-+#define _ICACHE_SET_MASK ((_ICACHE_SIZE/64-1)<<_SET_SHIFT)
-+#define LAST_DCACHE_ADDR _DCACHE_SET_MASK
-+#define LAST_ICACHE_ADDR _ICACHE_SET_MASK
-+
-+
-+#ifndef __ASSEMBLY__
-+
-+extern void DcacheFlushInvalidate(void);
-+
-+extern void DcacheDisable(void);
-+extern void DcacheEnable(void);
-+
-+/******************************************************************************/
-+/*** Unimplemented Cache functionality ***/
-+/******************************************************************************/
-+#define preDcacheInvalidateBlockMark()
-+#define postDcacheInvalidateBlockMark()
-+#define DcacheZeroBlock(p, l) fast_bzero((char *)(p), (long)(l))
-+#define loadDcacheInvalidateBlock() ASSERT(!"Not Implemented on V4e")
-+#define IcacheInvalidateBlock() ASSERT(!"Not Implemented on V4e")
-+
-+/******************************************************************************/
-+/*** Redundant Cache functionality on ColdFire ***/
-+/******************************************************************************/
-+#define DcacheInvalidateBlock(p, l) DcacheFlushInvalidateCacheBlock(p, l)
-+#define DcacheFlushCacheBlock(p, l) DcacheFlushInvalidateCacheBlock(p, l)
-+#define DcacheFlushBlock(p, l) DcacheFlushInvalidateCacheBlock(p, l)
-+
-+extern void DcacheFlushInvalidateCacheBlock(void *start, unsigned long size);
-+extern void FLASHDcacheFlushInvalidate(void);
-+
-+extern void cacr_set(unsigned long x);
-+
-+#endif /* !__ASSEMBLY__ */
-+
-+#endif /* CF_CACHE_H */
---- /dev/null
-+++ b/include/asm-m68k/cfmmu.h
-@@ -0,0 +1,104 @@
-+/*
-+ * Definitions for Coldfire V4e MMU
-+ */
-+#include <asm/movs.h>
-+
-+#ifndef __CF_MMU_H__
-+#define __CF_MMU_H__
-+
-+
-+#define MMU_BASE 0xE1000000
-+
-+
-+#define MMUCR (MMU_BASE+0x00)
-+#define MMUCR_ASMN 1
-+#define MMUCR_ASM (1<<MMUCR_ASMN)
-+#define MMUCR_ENN 0
-+#define MMUCR_EN (1<<MMUCR_ENN)
-+
-+#define MMUOR REG16(MMU_BASE+0x04+0x02)
-+#define MMUOR_AAN 16
-+#define MMUOR_AA (0xffff<<MMUOR_AAN)
-+#define MMUOR_STLBN 8
-+#define MMUOR_STLB (1<<MMUOR_STLBN)
-+#define MMUOR_CAN 7
-+#define MMUOR_CA (1<<MMUOR_CAN)
-+#define MMUOR_CNLN 6
-+#define MMUOR_CNL (1<<MMUOR_CNLN)
-+#define MMUOR_CASN 5
-+#define MMUOR_CAS (1<<MMUOR_CASN)
-+#define MMUOR_ITLBN 4
-+#define MMUOR_ITLB (1<<MMUOR_ITLBN)
-+#define MMUOR_ADRN 3
-+#define MMUOR_ADR (1<<MMUOR_ADRN)
-+#define MMUOR_RWN 2
-+#define MMUOR_RW (1<<MMUOR_RWN)
-+#define MMUOR_ACCN 1
-+#define MMUOR_ACC (1<<MMUOR_ACCN)
-+#define MMUOR_UAAN 0
-+#define MMUOR_UAA (1<<MMUOR_UAAN)
-+
-+#define MMUSR REG32(MMU_BASE+0x08)
-+#define MMUSR_SPFN 5
-+#define MMUSR_SPF (1<<MMUSR_SPFN)
-+#define MMUSR_RFN 4
-+#define MMUSR_RF (1<<MMUSR_RFN)
-+#define MMUSR_WFN 3
-+#define MMUSR_WF (1<<MMUSR_WFN)
-+#define MMUSR_HITN 1
-+#define MMUSR_HIT (1<<MMUSR_HITN)
-+
-+#define MMUAR REG32(MMU_BASE+0x10)
-+#define MMUAR_VPN 1
-+#define MMUAR_VP (0xfffffffe)
-+#define MMUAR_SN 0
-+#define MMUAR_S (1<<MMUAR_SN)
-+
-+#define MMUTR REG32(MMU_BASE+0x14)
-+#define MMUTR_VAN 10
-+#define MMUTR_VA (0xfffffc00)
-+#define MMUTR_IDN 2
-+#define MMUTR_ID (0xff<<MMUTR_IDN)
-+#define MMUTR_SGN 1
-+#define MMUTR_SG (1<<MMUTR_SGN)
-+#define MMUTR_VN 0
-+#define MMUTR_V (1<<MMUTR_VN)
-+
-+#define MMUDR REG32(MMU_BASE+0x18)
-+#define MMUDR_PAN 10
-+#define MMUDR_PA (0xfffffc00)
-+#define MMUDR_SZN 8
-+#define MMUDR_SZ_MASK (0x2<<MMUDR_SZN)
-+#define MMUDR_SZ1M (0<<MMUDR_SZN)
-+#define MMUDR_SZ4K (1<<MMUDR_SZN)
-+#define MMUDR_SZ8K (2<<MMUDR_SZN)
-+#define MMUDR_SZ16M (3<<MMUDR_SZN)
-+#define MMUDR_CMN 6
-+#define MMUDR_INC (2<<MMUDR_CMN)
-+#define MMUDR_IC (0<<MMUDR_CMN)
-+#define MMUDR_DWT (0<<MMUDR_CMN)
-+#define MMUDR_DCB (1<<MMUDR_CMN)
-+#define MMUDR_DNCP (2<<MMUDR_CMN)
-+#define MMUDR_DNCIP (3<<MMUDR_CMN)
-+#define MMUDR_SPN 5
-+#define MMUDR_SP (1<<MMUDR_SPN)
-+#define MMUDR_RN 4
-+#define MMUDR_R (1<<MMUDR_RN)
-+#define MMUDR_WN 3
-+#define MMUDR_W (1<<MMUDR_WN)
-+#define MMUDR_XN 2
-+#define MMUDR_X (1<<MMUDR_XN)
-+#define MMUDR_LKN 1
-+#define MMUDR_LK (1<<MMUDR_LKN)
-+
-+
-+#ifndef __ASSEMBLY__
-+#define CF_PMEGS_NUM 256
-+#define CF_INVALID_CONTEXT 255
-+#define CF_PAGE_PGNUM_MASK (PAGE_MASK)
-+
-+extern int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb,
-+ int extension_word);
-+#endif /* __ASSEMBLY__*/
-+
-+#endif /* !__CF_MMU_H__ */
---- /dev/null
-+++ b/include/asm-m68k/coldfire.h
-@@ -0,0 +1,38 @@
-+#ifndef _COLDFIRE_H_
-+#define _COLDFIRE_H_
-+
-+#define MCF_MBAR 0x0
-+#define MCF_RAMBAR1 0x40000000
-+#define MCF_SRAM 0x80000000
-+#define MCF_CLK CONFIG_MCFCLK
-+#define MCF_BUSCLK (CONFIG_MCFCLK/2)
-+
-+#ifdef __ASSEMBLY__
-+#define REG32
-+#define REG16
-+#define REG08
-+#else /* __ASSEMBLY__ */
-+#define REG32(x) ((volatile unsigned long *)(x))
-+#define REG16(x) ((volatile unsigned short *)(x))
-+#define REG08(x) ((volatile unsigned char *)(x))
-+
-+#define MCF_REG32(x) *(volatile unsigned long *)(MCF_MBAR+(x))
-+#define MCF_REG16(x) *(volatile unsigned short *)(MCF_MBAR+(x))
-+#define MCF_REG08(x) *(volatile unsigned char *)(MCF_MBAR+(x))
-+
-+void cacr_set(unsigned long);
-+unsigned long cacr_get(void);
-+
-+#define coldfire_enable_irq0(irq) MCF_INTC0_CIMR = (irq);
-+
-+#define coldfire_enable_irq1(irq) MCF_INTC1_CIMR = (irq);
-+
-+#define coldfire_disable_irq0(irq) MCF_INTC0_SIMR = (irq);
-+
-+#define coldfire_disable_irq1(irq) MCF_INTC1_SIMR = (irq);
-+
-+#define getiprh() MCF_INTC0_IPRH
-+
-+#endif /* __ASSEMBLY__ */
-+
-+#endif /* _COLDFIRE_H_ */
---- /dev/null
-+++ b/include/asm-m68k/coldfire_edma.h
-@@ -0,0 +1,39 @@
-+#ifndef _LINUX_COLDFIRE_DMA_H
-+#define _LINUX_COLDFIRE_DMA_H
-+
-+#include <linux/interrupt.h>
-+
-+#define EDMA_DRIVER_NAME "ColdFire-eDMA"
-+#define DMA_DEV_MINOR 1
-+
-+#define EDMA_INT_CHANNEL_BASE 8
-+#define EDMA_INT_CONTROLLER_BASE 64
-+#define EDMA_CHANNELS 16
-+
-+#define EDMA_IRQ_LEVEL 5
-+
-+typedef irqreturn_t (*edma_irq_handler)(int, void *);
-+typedef void (*edma_error_handler)(int, void *);
-+
-+void set_edma_params(int channel, u32 source, u32 dest,
-+ u32 attr, u32 soff, u32 nbytes, u32 slast,
-+ u32 citer, u32 biter, u32 doff, u32 dlast_sga);
-+
-+void start_edma_transfer(int channel, int major_int);
-+
-+void stop_edma_transfer(int channel);
-+
-+void confirm_edma_interrupt_handled(int channel);
-+
-+void init_edma(void);
-+
-+int request_edma_channel(int channel,
-+ edma_irq_handler handler,
-+ edma_error_handler error_handler,
-+ void *dev,
-+ spinlock_t *lock,
-+ const char *device_id);
-+
-+int free_edma_channel(int channel, void *dev);
-+
-+#endif
---- /dev/null
-+++ b/include/asm-m68k/mcfqspi.h
-@@ -0,0 +1,50 @@
-+/****************************************************************************/
-+/*
-+ * mcfqspi.h - Master QSPI controller for the ColdFire processors
-+ *
-+ * (C) Copyright 2005, Intec Automation,
-+ * Mike Lavender (mike@steroidmicros)
-+ *
-+
-+ This program is free software; you can redistribute it and/or modify
-+ it under the terms of the GNU General Public License as published by
-+ the Free Software Foundation; either version 2 of the License, or
-+ (at your option) any later version.
-+
-+ This program is distributed in the hope that it will be useful,
-+ but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ GNU General Public License for more details.
-+
-+ You should have received a copy of the GNU General Public License
-+ along with this program; if not, write to the Free Software
-+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
-+/* ------------------------------------------------------------------------- */
-+
-+#ifndef MCFQSPI_H_
-+#define MCFQSPI_H_
-+
-+#define QSPI_CS_INIT 0x01
-+#define QSPI_CS_ASSERT 0x02
-+#define QSPI_CS_DROP 0x04
-+
-+struct coldfire_spi_master {
-+ u16 bus_num;
-+ u16 num_chipselect;
-+ u8 irq_source;
-+ u32 irq_vector;
-+ u32 irq_mask;
-+ u8 irq_lp;
-+ u8 par_val;
-+ void (*cs_control)(u8 cs, u8 command);
-+};
-+
-+
-+struct coldfire_spi_chip {
-+ u8 mode;
-+ u8 bits_per_word;
-+ u8 del_cs_to_clk;
-+ u8 del_after_trans;
-+ u16 void_write_data;
-+};
-+#endif /*MCFQSPI_H_*/
---- /dev/null
-+++ b/include/asm-m68k/mcfsim.h
-@@ -0,0 +1,96 @@
-+/*
-+ * mcfsim.h -- ColdFire System Integration Module support.
-+ *
-+ * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
-+ * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
-+ */
-+
-+#ifndef mcfsim_h
-+#define mcfsim_h
-+
-+#if defined(CONFIG_COLDFIRE)
-+#include <asm/coldfire.h>
-+#endif
-+
-+#if defined(CONFIG_M54455)
-+#include <asm/mcf5445x_intc.h>
-+#include <asm/mcf5445x_gpio.h>
-+#include <asm/mcf5445x_i2c.h>
-+#include <asm/mcf5445x_ccm.h>
-+#include <asm/mcf5445x_pci.h>
-+#include <asm/mcf5445x_pciarb.h>
-+#include <asm/mcf5445x_eport.h>
-+#endif
-+
-+/*
-+ * Define the base address of the SIM within the MBAR address space.
-+ */
-+#define MCFSIM_BASE 0x0 /* Base address of SIM */
-+
-+/*
-+ * Bit definitions for the ICR family of registers.
-+ */
-+#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
-+#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
-+#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
-+#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
-+#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
-+#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
-+#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
-+#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
-+#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
-+
-+#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
-+#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
-+#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
-+#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
-+
-+/*
-+ * Bit definitions for the Interrupt Mask register (IMR).
-+ */
-+#define MCFSIM_IMR_EINT1 0x0002 /* External intr # 1 */
-+#define MCFSIM_IMR_EINT2 0x0004 /* External intr # 2 */
-+#define MCFSIM_IMR_EINT3 0x0008 /* External intr # 3 */
-+#define MCFSIM_IMR_EINT4 0x0010 /* External intr # 4 */
-+#define MCFSIM_IMR_EINT5 0x0020 /* External intr # 5 */
-+#define MCFSIM_IMR_EINT6 0x0040 /* External intr # 6 */
-+#define MCFSIM_IMR_EINT7 0x0080 /* External intr # 7 */
-+
-+#define MCFSIM_IMR_SWD 0x0100 /* Software Watchdog intr */
-+#define MCFSIM_IMR_TIMER1 0x0200 /* TIMER 1 intr */
-+#define MCFSIM_IMR_TIMER2 0x0400 /* TIMER 2 intr */
-+#define MCFSIM_IMR_MBUS 0x0800 /* MBUS intr */
-+#define MCFSIM_IMR_UART1 0x1000 /* UART 1 intr */
-+#define MCFSIM_IMR_UART2 0x2000 /* UART 2 intr */
-+
-+/*
-+ * Mask for all of the SIM devices. Some parts have more or less
-+ * SIM devices. This is a catchall for the sandard set.
-+ */
-+#ifndef MCFSIM_IMR_MASKALL
-+#define MCFSIM_IMR_MASKALL 0x3ffe /* All intr sources */
-+#endif
-+
-+
-+/*
-+ * PIT interrupt settings, if not found in mXXXXsim.h file.
-+ */
-+#ifndef ICR_INTRCONF
-+#define ICR_INTRCONF 0x2b /* PIT1 level 5, priority 3 */
-+#endif
-+#ifndef MCFPIT_IMR
-+#define MCFPIT_IMR MCFINTC_IMRH
-+#endif
-+#ifndef MCFPIT_IMR_IBIT
-+#define MCFPIT_IMR_IBIT (1 << (MCFINT_PIT1 - 32))
-+#endif
-+
-+
-+#ifndef __ASSEMBLY__
-+/*
-+ * Definition for the interrupt auto-vectoring support.
-+ */
-+extern void mcf_autovector(unsigned int vec);
-+#endif /* __ASSEMBLY__ */
-+
-+#endif /* mcfsim_h */
---- /dev/null
-+++ b/include/asm-m68k/mcfuart.h
-@@ -0,0 +1,180 @@
-+/*
-+ * mcfuart.h -- ColdFire internal UART support defines.
-+ *
-+ * Matt Waddel Matt.Waddel@freescale.com
-+ * Copyright Freescale Semiconductor, Inc. 2007
-+ *
-+ * Derived from m68knommu version of this same file (Greg Ungerer & Lineo).
-+ *
-+ */
-+
-+#ifndef mcfuart_h
-+#define mcfuart_h
-+
-+/*
-+ * Define the base address of the UARTS within the MBAR address
-+ * space.
-+ */
-+#if defined(CONFIG_M54455)
-+#include <asm/mcf5445x_intc.h>
-+#define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */
-+#define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */
-+#define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */
-+#define MCFINT_VECBASE 64
-+#define MCFINT_UART0 26
-+#endif
-+
-+
-+/*
-+ * Define the ColdFire UART register set addresses.
-+ */
-+#define MCFUART_UMR 0x00 /* Mode register (r/w) */
-+#define MCFUART_USR 0x04 /* Status register (r) */
-+#define MCFUART_UCSR 0x04 /* Clock Select (w) */
-+#define MCFUART_UCR 0x08 /* Command register (w) */
-+#define MCFUART_URB 0x0c /* Receiver Buffer (r) */
-+#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */
-+#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */
-+#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */
-+#define MCFUART_UISR 0x14 /* Interrup Status (r) */
-+#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */
-+#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */
-+#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */
-+#ifdef CONFIG_M5272
-+#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */
-+#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */
-+#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
-+#else
-+#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */
-+#endif
-+#define MCFUART_UIPR 0x34 /* Input Port (r) */
-+#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */
-+#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */
-+
-+
-+/*
-+ * Define bit flags in Mode Register 1 (MR1).
-+ */
-+#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */
-+#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
-+#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */
-+#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */
-+#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */
-+
-+#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */
-+#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */
-+#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */
-+#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */
-+#define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */
-+
-+#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */
-+#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */
-+#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */
-+#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */
-+
-+/*
-+ * Define bit flags in Mode Register 2 (MR2).
-+ */
-+#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */
-+#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */
-+#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */
-+#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */
-+#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */
-+
-+#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */
-+#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */
-+#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */
-+
-+/*
-+ * Define bit flags in Status Register (USR).
-+ */
-+#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */
-+#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */
-+#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */
-+#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */
-+#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */
-+#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */
-+#define MCFUART_USR_RXFULL 0x02 /* Receiver full */
-+#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */
-+
-+#define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
-+ MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
-+
-+/*
-+ * Define bit flags in Clock Select Register (UCSR).
-+ */
-+#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */
-+#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */
-+#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */
-+
-+#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */
-+#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */
-+#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */
-+
-+/*
-+ * Define bit flags in Command Register (UCR).
-+ */
-+#define MCFUART_UCR_CMDNULL 0x00 /* No command */
-+#define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */
-+#define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */
-+#define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */
-+#define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */
-+#define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */
-+#define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */
-+#define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */
-+
-+#define MCFUART_UCR_TXNULL 0x00 /* No TX command */
-+#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */
-+#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */
-+#define MCFUART_UCR_RXNULL 0x00 /* No RX command */
-+#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */
-+#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */
-+
-+/*
-+ * Define bit flags in Input Port Change Register (UIPCR).
-+ */
-+#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */
-+#define MCFUART_UIPCR_CTS 0x01 /* CTS value */
-+
-+/*
-+ * Define bit flags in Input Port Register (UIP).
-+ */
-+#define MCFUART_UIPR_CTS 0x01 /* CTS value */
-+
-+/*
-+ * Define bit flags in Output Port Registers (UOP).
-+ * Clear bit by writing to UOP0, set by writing to UOP1.
-+ */
-+#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */
-+
-+/*
-+ * Define bit flags in the Auxiliary Control Register (UACR).
-+ */
-+#define MCFUART_UACR_IEC 0x01 /* Input enable control */
-+
-+/*
-+ * Define bit flags in Interrupt Status Register (UISR).
-+ * These same bits are used for the Interrupt Mask Register (UIMR).
-+ */
-+#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */
-+#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */
-+#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */
-+#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */
-+
-+#ifdef CONFIG_M5272
-+/*
-+ * Define bit flags in the Transmitter FIFO Register (UTF).
-+ */
-+#define MCFUART_UTF_TXB 0x1f /* Transmitter data level */
-+#define MCFUART_UTF_FULL 0x20 /* Transmitter fifo full */
-+#define MCFUART_UTF_TXS 0xc0 /* Transmitter status */
-+
-+/*
-+ * Define bit flags in the Receiver FIFO Register (URF).
-+ */
-+#define MCFUART_URF_RXB 0x1f /* Receiver data level */
-+#define MCFUART_URF_FULL 0x20 /* Receiver fifo full */
-+#define MCFUART_URF_RXS 0xc0 /* Receiver status */
-+#endif
-+
-+#endif /* mcfuart_h */
+++ /dev/null
-From fa0f89c9cf9ceecc3feac1d96914c8e91f98d90f Mon Sep 17 00:00:00 2001
-From: Kurt Mahan <kmahan@freescale.com>
-Date: Wed, 31 Oct 2007 16:43:01 -0600
-Subject: [PATCH] Add MCF5445x Specific Header Files.
-
-LTIBName: m5445x-headers
-Signed-off-by: Kurt Mahan <kmahan@freescale.com>
----
- include/asm-m68k/mcf5445x_ccm.h | 161 ++++
- include/asm-m68k/mcf5445x_dspi.h | 402 ++++++++++
- include/asm-m68k/mcf5445x_dtim.h | 87 +++
- include/asm-m68k/mcf5445x_edma.h | 1458 ++++++++++++++++++++++++++++++++++++
- include/asm-m68k/mcf5445x_eport.h | 117 +++
- include/asm-m68k/mcf5445x_fbcs.h | 182 +++++
- include/asm-m68k/mcf5445x_gpio.h | 1257 +++++++++++++++++++++++++++++++
- include/asm-m68k/mcf5445x_i2c.h | 39 +
- include/asm-m68k/mcf5445x_intc.h | 724 ++++++++++++++++++
- include/asm-m68k/mcf5445x_pci.h | 238 ++++++
- include/asm-m68k/mcf5445x_pciarb.h | 40 +
- include/asm-m68k/mcf5445x_sdramc.h | 115 +++
- include/asm-m68k/mcf5445x_ssi.h | 187 +++++
- include/asm-m68k/mcf5445x_usb.h | 49 ++
- 14 files changed, 5056 insertions(+), 0 deletions(-)
- create mode 100644 include/asm-m68k/mcf5445x_ccm.h
- create mode 100644 include/asm-m68k/mcf5445x_dspi.h
- create mode 100644 include/asm-m68k/mcf5445x_dtim.h
- create mode 100644 include/asm-m68k/mcf5445x_edma.h
- create mode 100644 include/asm-m68k/mcf5445x_eport.h
- create mode 100644 include/asm-m68k/mcf5445x_fbcs.h
- create mode 100644 include/asm-m68k/mcf5445x_gpio.h
- create mode 100644 include/asm-m68k/mcf5445x_i2c.h
- create mode 100644 include/asm-m68k/mcf5445x_intc.h
- create mode 100644 include/asm-m68k/mcf5445x_pci.h
- create mode 100644 include/asm-m68k/mcf5445x_pciarb.h
- create mode 100644 include/asm-m68k/mcf5445x_sdramc.h
- create mode 100644 include/asm-m68k/mcf5445x_ssi.h
- create mode 100644 include/asm-m68k/mcf5445x_usb.h
-
---- /dev/null
-+++ b/include/asm-m68k/mcf5445x_ccm.h
-@@ -0,0 +1,161 @@
-+/*
-+ * Matt Waddel Matt.Waddel@freescale.com
-+ *
-+ * Copyright Freescale Semiconductor, Inc. 2007
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+
-+#ifndef __MCF5445X_CCM_H__
-+#define __MCF5445X_CCM_H__
-+
-+/*********************************************************************
-+*
-+* Chip Configuration Module (CCM)
-+*
-+*********************************************************************/
-+
-+/* Register read/write macros */
-+#define MCF_CCM_CCR MCF_REG16(0xFC0A0004) /* Chip Configuration Register (Read-only) (256 or 360 TEPBGA) */
-+#define MCF_CCM_RCON MCF_REG16(0xFC0A0008) /* Reset Configuration (Read-only) (256 or 360 TEPBGA) */
-+#define MCF_CCM_CIR MCF_REG16(0xFC0A000A) /* Chip Identification Register (Read-only) */
-+#define MCF_CCM_MISCCR MCF_REG16(0xFC0A0010) /* Miscellaneous Control Register */
-+#define MCF_CCM_CDR MCF_REG16(0xFC0A0012) /* Clock Divider Register */
-+#define MCF_CCM_UOCSR MCF_REG16(0xFC0A0014) /* USB On-the-Go Controller Status Register */
-+#define MCF_CCM_SBFSR MCF_REG16(0xFC0A0018) /* Serial Boot Facility Status Register (Read Only) */
-+#define MCF_CCM_SBFCR MCF_REG16(0xFC0A0020) /* Serial Boot Facility Control Register */
-+
-+/* Bit definitions and macros for CCR_360 */
-+#define MCF_CCM_CCR_360_PLLMULT2(x) (((x) & 0x0003)) /* 2-Bit PLL clock mode */
-+#define MCF_CCM_CCR_360_PCISLEW (0x0004) /* PCI pad slew rate mode */
-+#define MCF_CCM_CCR_360_PCIMODE (0x0008) /* PCI host/agent mode */
-+#define MCF_CCM_CCR_360_PLLMODE (0x0010) /* PLL Mode */
-+#define MCF_CCM_CCR_360_FBCONFIG(x) (((x) & 0x0007) << 5) /* Flexbus/PCI port size configuration */
-+#define MCF_CCM_CCR_360_PLLMULT3(x) (((x) & 0x0007)) /* 3-Bit PLL Clock Mode */
-+#define MCF_CCM_CCR_360_OSCMODE (0x0008) /* Oscillator Clock Mode */
-+#define MCF_CCM_CCR_360_FBCONFIG_MASK (0x00E0)
-+#define MCF_CCM_CCR_360_PLLMULT2_MASK (0x0003)
-+#define MCF_CCM_CCR_360_PLLMULT3_MASK (0x0007)
-+#define MCF_CCM_CCR_360_FBCONFIG_NM_NP_32 (0x0000)
-+#define MCF_CCM_CCR_360_FBCONFIG_NM_NP_8 (0x0020)
-+#define MCF_CCM_CCR_360_FBCONFIG_NM_NP_16 (0x0040)
-+#define MCF_CCM_CCR_360_FBCONFIG_M_P_16 (0x0060)
-+#define MCF_CCM_CCR_360_FBCONFIG_M_NP_32 (0x0080)
-+#define MCF_CCM_CCR_360_FBCONFIG_M_NP_8 (0x00A0)
-+#define MCF_CCM_CCR_360_FBCONFIG_M_NP_16 (0x00C0)
-+#define MCF_CCM_CCR_360_FBCONFIG_M_P_8 (0x00E0)
-+#define MCF_CCM_CCR_360_PLLMULT2_12X (0x0000)
-+#define MCF_CCM_CCR_360_PLLMULT2_6X (0x0001)
-+#define MCF_CCM_CCR_360_PLLMULT2_16X (0x0002)
-+#define MCF_CCM_CCR_360_PLLMULT2_8X (0x0003)
-+#define MCF_CCM_CCR_360_PLLMULT3_20X (0x0000)
-+#define MCF_CCM_CCR_360_PLLMULT3_10X (0x0001)
-+#define MCF_CCM_CCR_360_PLLMULT3_24X (0x0002)
-+#define MCF_CCM_CCR_360_PLLMULT3_18X (0x0003)
-+#define MCF_CCM_CCR_360_PLLMULT3_12X (0x0004)
-+#define MCF_CCM_CCR_360_PLLMULT3_6X (0x0005)
-+#define MCF_CCM_CCR_360_PLLMULT3_16X (0x0006)
-+#define MCF_CCM_CCR_360_PLLMULT3_8X (0x0007)
-+
-+/* Bit definitions and macros for CCR_256 */
-+#define MCF_CCM_CCR_256_PLLMULT3(x) (((x) & 0x0007)) /* 3-Bit PLL clock mode */
-+#define MCF_CCM_CCR_256_OSCMODE (0x0008) /* Oscillator clock mode */
-+#define MCF_CCM_CCR_256_PLLMODE (0x0010) /* PLL Mode */
-+#define MCF_CCM_CCR_256_FBCONFIG(x) (((x) & 0x0007) << 5) /* Flexbus/PCI port size configuration */
-+#define MCF_CCM_CCR_256_FBCONFIG_MASK (0x00E0)
-+#define MCF_CCM_CCR_256_FBCONFIG_NM_32 (0x0000)
-+#define MCF_CCM_CCR_256_FBCONFIG_NM_8 (0x0020)
-+#define MCF_CCM_CCR_256_FBCONFIG_NM_16 (0x0040)
-+#define MCF_CCM_CCR_256_FBCONFIG_M_32 (0x0080)
-+#define MCF_CCM_CCR_256_FBCONFIG_M_8 (0x00A0)
-+#define MCF_CCM_CCR_256_FBCONFIG_M_16 (0x00C0)
-+#define MCF_CCM_CCR_256_PLLMULT3_MASK (0x0007)
-+#define MCF_CCM_CCR_256_PLLMULT3_20X (0x0000)
-+#define MCF_CCM_CCR_256_PLLMULT3_10X (0x0001)
-+#define MCF_CCM_CCR_256_PLLMULT3_24X (0x0002)
-+#define MCF_CCM_CCR_256_PLLMULT3_18X (0x0003)
-+#define MCF_CCM_CCR_256_PLLMULT3_12X (0x0004)
-+#define MCF_CCM_CCR_256_PLLMULT3_6X (0x0005)
-+#define MCF_CCM_CCR_256_PLLMULT3_16X (0x0006)
-+#define MCF_CCM_CCR_256_PLLMULT3_8X (0x0007)
-+
-+/* Bit definitions and macros for RCON_360 */
-+#define MCF_CCM_RCON_360_PLLMULT(x) (((x)&0x0003)) /* PLL clock mode */
-+#define MCF_CCM_RCON_360_PCISLEW (0x0004) /* PCI pad slew rate mode */
-+#define MCF_CCM_RCON_360_PCIMODE (0x0008) /* PCI host/agent mode */
-+#define MCF_CCM_RCON_360_PLLMODE (0x0010) /* PLL Mode */
-+#define MCF_CCM_RCON_360_FBCONFIG(x) (((x) & 0x0007) << 5) /* Flexbus/PCI port size configuration */
-+
-+/* Bit definitions and macros for RCON_256 */
-+#define MCF_CCM_RCON_256_PLLMULT(x) (((x) & 0x0007)) /* PLL clock mode */
-+#define MCF_CCM_RCON_256_OSCMODE (0x0008) /* Oscillator clock mode */
-+#define MCF_CCM_RCON_256_PLLMODE (0x0010) /* PLL Mode */
-+#define MCF_CCM_RCON_256_FBCONFIG(x) (((x) & 0x0007) << 5) /* Flexbus/PCI port size configuration */
-+
-+/* Bit definitions and macros for CIR */
-+#define MCF_CCM_CIR_PRN(x) (((x) & 0x003F)) /* Part revision number */
-+#define MCF_CCM_CIR_PIN(x) (((x) & 0x03FF) << 6) /* Part identification number */
-+#define MCF_CCM_CIR_PIN_MASK (0xFFC0)
-+#define MCF_CCM_CIR_PRN_MASK (0x003F)
-+#define MCF_CCM_CIR_PIN_MCF54450 (0x4F << 6)
-+#define MCF_CCM_CIR_PIN_MCF54451 (0x4D << 6)
-+#define MCF_CCM_CIR_PIN_MCF54452 (0x4B << 6)
-+#define MCF_CCM_CIR_PIN_MCF54453 (0x49 << 6)
-+#define MCF_CCM_CIR_PIN_MCF54454 (0x4A << 6)
-+#define MCF_CCM_CIR_PIN_MCF54455 (0x48 << 6)
-+
-+/* Bit definitions and macros for MISCCR */
-+#define MCF_CCM_MISCCR_USBSRC (0x0001) /* USB clock source */
-+#define MCF_CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense polarity */
-+#define MCF_CCM_MISCCR_USBPUE (0x0004) /* USB transceiver pull-up enable */
-+#define MCF_CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */
-+#define MCF_CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */
-+#define MCF_CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */
-+#define MCF_CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */
-+#define MCF_CCM_MISCCR_BMT(x) (((x) & 0x0007) << 8) /* Bus monitor timing field */
-+#define MCF_CCM_MISCCR_BME (0x0800) /* Bus monitor external enable bit */
-+#define MCF_CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */
-+#define MCF_CCM_MISCCR_BMT_65536 (0)
-+#define MCF_CCM_MISCCR_BMT_32768 (1)
-+#define MCF_CCM_MISCCR_BMT_16384 (2)
-+#define MCF_CCM_MISCCR_BMT_8192 (3)
-+#define MCF_CCM_MISCCR_BMT_4096 (4)
-+#define MCF_CCM_MISCCR_BMT_2048 (5)
-+#define MCF_CCM_MISCCR_BMT_1024 (6)
-+#define MCF_CCM_MISCCR_BMT_512 (7)
-+#define MCF_CCM_MISCCR_SSIPUS_UP (1)
-+#define MCF_CCM_MISCCR_SSIPUS_DOWN (0)
-+#define MCF_CCM_MISCCR_TIMDMA_TIM (1)
-+#define MCF_CCM_MISCCR_TIMDMA_SSI (0)
-+#define MCF_CCM_MISCCR_SSISRC_CLKIN (0)
-+#define MCF_CCM_MISCCR_SSISRC_PLL (1)
-+#define MCF_CCM_MISCCR_USBOC_ACTHI (0)
-+#define MCF_CCM_MISCCR_USBOV_ACTLO (1)
-+#define MCF_CCM_MISCCR_USBSRC_CLKIN (0)
-+#define MCF_CCM_MISCCR_USBSRC_PLL (1)
-+
-+/* Bit definitions and macros for CDR */
-+#define MCF_CCM_CDR_SSIDIV(x) (((x) & 0x00FF)) /* SSI oversampling clock divider */
-+#define MCF_CCM_CDR_LPDIV(x) (((x) & 0x000F) << 8) /* Low power clock divider */
-+
-+/* Bit definitions and macros for UOCSR */
-+#define MCF_CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down enable */
-+#define MCF_CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt enable */
-+#define MCF_CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */
-+#define MCF_CCM_UOCSR_PWRFLT (0x0008) /* VBUS power fault */
-+#define MCF_CCM_UOCSR_SEND (0x0010) /* Session end */
-+#define MCF_CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */
-+#define MCF_CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */
-+#define MCF_CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */
-+#define MCF_CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (read-only) */
-+#define MCF_CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor enabled (read-only) */
-+#define MCF_CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (read-only) */
-+#define MCF_CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (read-only) */
-+#define MCF_CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (read-only) */
-+
-+/********************************************************************/
-+
-+#endif /* __MCF5445X_CCM_H__ */
---- /dev/null
-+++ b/include/asm-m68k/mcf5445x_dspi.h
-@@ -0,0 +1,402 @@
-+/*
-+ * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
-+ *
-+ * Copyright Freescale Semiconductor, Inc. 2007
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+
-+#ifndef __MCF5445X_DSPI_H__
-+#define __MCF5445X_DSPI_H__
-+
-+/*********************************************************************
-+*
-+* DMA Serial Peripheral Interface (DSPI)
-+*
-+*********************************************************************/
-+
-+/* Register read/write macros */
-+#define MCF_DSPI_DMCR MCF_REG32(0xFC05C000) /* DSPI Module Configuration Register */
-+#define MCF_DSPI_DTCR MCF_REG32(0xFC05C008) /* DSPI Transfer Count Register */
-+#define MCF_DSPI_DCTAR0 MCF_REG32(0xFC05C00C) /* DSPI Clock and Transfer Attributes Register */
-+#define MCF_DSPI_DCTAR1 MCF_REG32(0xFC05C010) /* DSPI Clock and Transfer Attributes Register */
-+#define MCF_DSPI_DCTAR2 MCF_REG32(0xFC05C014) /* DSPI Clock and Transfer Attributes Register */
-+#define MCF_DSPI_DCTAR3 MCF_REG32(0xFC05C018) /* DSPI Clock and Transfer Attributes Register */
-+#define MCF_DSPI_DCTAR4 MCF_REG32(0xFC05C01C) /* DSPI Clock and Transfer Attributes Register */
-+#define MCF_DSPI_DCTAR5 MCF_REG32(0xFC05C020) /* DSPI Clock and Transfer Attributes Register */
-+#define MCF_DSPI_DCTAR6 MCF_REG32(0xFC05C024) /* DSPI Clock and Transfer Attributes Register */
-+#define MCF_DSPI_DCTAR7 MCF_REG32(0xFC05C028) /* DSPI Clock and Transfer Attributes Register */
-+#define MCF_DSPI_DSR MCF_REG32(0xFC05C02C) /* DSPI Status Register */
-+#define MCF_DSPI_DRSER MCF_REG32(0xFC05C030) /* DSPI DMA/Interrupt Request Select and Enable Register */
-+#define MCF_DSPI_DTFR MCF_REG32(0xFC05C034) /* DSPI Transmit FIFO Register */
-+#define MCF_DSPI_DRFR MCF_REG32(0xFC05C038) /* DSPI Receive FIFO Register */
-+#define MCF_DSPI_DTFDR0 MCF_REG32(0xFC05C03C) /* DSPI Transmit FIFO Debugging Registers */
-+#define MCF_DSPI_DTFDR1 MCF_REG32(0xFC05C040) /* DSPI Transmit FIFO Debugging Registers */
-+#define MCF_DSPI_DTFDR2 MCF_REG32(0xFC05C044) /* DSPI Transmit FIFO Debugging Registers */
-+#define MCF_DSPI_DTFDR3 MCF_REG32(0xFC05C048) /* DSPI Transmit FIFO Debugging Registers */
-+#define MCF_DSPI_DRFDR0 MCF_REG32(0xFC05C07C) /* DSPI Receive FIFO Debugging Registers */
-+#define MCF_DSPI_DRFDR1 MCF_REG32(0xFC05C080) /* DSPI Receive FIFO Debugging Registers */
-+#define MCF_DSPI_DRFDR2 MCF_REG32(0xFC05C084) /* DSPI Receive FIFO Debugging Registers */
-+#define MCF_DSPI_DRFDR3 MCF_REG32(0xFC05C088) /* DSPI Receive FIFO Debugging Registers */
-+
-+/* Parameterized register read/write macros for multiple registers */
-+#define MCF_DSPI_DCTAR(x) MCF_REG32(0xFC05C00C+((x)*0x004)) /* DSPI Clock and Transfer Attributes Register */
-+#define MCF_DSPI_DTFDR(x) MCF_REG32(0xFC05C03C+((x)*0x004)) /* DSPI Transmit FIFO Debugging Registers */
-+#define MCF_DSPI_DRFDR(x) MCF_REG32(0xFC05C07C+((x)*0x004)) /* DSPI Receive FIFO Debugging Registers */
-+
-+/* Bit definitions and macros for DMCR */
-+#define MCF_DSPI_DMCR_HALT (0x00000001) /* Halt -- stops and starts DSPI transfers */
-+#define MCF_DSPI_DMCR_SMPLPT(x) (((x)&0x00000003)<<8) /* Sample point selection */
-+#define MCF_DSPI_DMCR_CLRRXF (0x00000400) /* Clear receive FIFO */
-+#define MCF_DSPI_DMCR_CLRTXF (0x00000800) /* Clear transmit FIFO */
-+#define MCF_DSPI_DMCR_DISRXF (0x00001000) /* Disable receive FIFO */
-+#define MCF_DSPI_DMCR_DISTXF (0x00002000) /* Disable transmit FIFO */
-+#define MCF_DSPI_DMCR_MDIS (0x00004000) /* Module Disable */
-+#define MCF_DSPI_DMCR_PCSIS0 (0x00010000) /* Peripheral chip-select 0 inactive state */
-+#define MCF_DSPI_DMCR_PCSIS1 (0x00020000) /* Peripheral chip-select 1 inactive state */
-+#define MCF_DSPI_DMCR_PCSIS2 (0x00040000) /* Peripheral chip-select 2 inactive state */
-+#define MCF_DSPI_DMCR_PCSIS3 (0x00080000) /* Peripheral chip-select 3 inactive state */
-+#define MCF_DSPI_DMCR_PCSIS4 (0x00100000) /* Peripheral chip-select 4 inactive state */
-+#define MCF_DSPI_DMCR_PCSIS5 (0x00200000) /* Peripheral chip-select 5 inactive state */
-+#define MCF_DSPI_DMCR_PCSIS6 (0x00400000) /* Peripheral chip-select 6 inactive state */
-+#define MCF_DSPI_DMCR_PCSIS7 (0x00800000) /* Peripheral chip-select 7 inactive state */
-+#define MCF_DSPI_DMCR_ROOE (0x01000000) /* Receive FIFO overflow overwrite enable */
-+#define MCF_DSPI_DMCR_PCSSE (0x02000000) /* Peripheral chip select strobe enable */
-+#define MCF_DSPI_DMCR_MTFE (0x04000000) /* Modified timing format enable */
-+#define MCF_DSPI_DMCR_FRZ (0x08000000) /* Freeze */
-+#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28) /* DSPI configuration */
-+#define MCF_DSPI_DMCR_CONT_SCKE (0x40000000) /* Continuous SCK enable */
-+#define MCF_DSPI_DMCR_MSTR (0x80000000) /* Master/Slave mode select */
-+#define MCF_DSPI_DMCR_DCONF_SPI (0x00000000)
-+#define MCF_DSPI_DMCR_PCSIS7_LOW (0x00000000)
-+#define MCF_DSPI_DMCR_PCSIS7_HIGH (0x00800000)
-+#define MCF_DSPI_DMCR_PCSIS6_LOW (0x00000000)
-+#define MCF_DSPI_DMCR_PCSIS6_HIGH (0x00400000)
-+#define MCF_DSPI_DMCR_PCSIS5_LOW (0x00000000)
-+#define MCF_DSPI_DMCR_PCSIS5_HIGH (0x00200000)
-+#define MCF_DSPI_DMCR_PCSIS4_LOW (0x00000000)
-+#define MCF_DSPI_DMCR_PCSIS4_HIGH (0x00100000)
-+#define MCF_DSPI_DMCR_PCSIS3_LOW (0x00000000)
-+#define MCF_DSPI_DMCR_PCSIS3_HIGH (0x00080000)
-+#define MCF_DSPI_DMCR_PCSIS2_LOW (0x00000000)
-+#define MCF_DSPI_DMCR_PCSIS2_HIGH (0x00040000)
-+#define MCF_DSPI_DMCR_PCSIS1_LOW (0x00000000)
-+#define MCF_DSPI_DMCR_PCSIS1_HIGH (0x00020000)
-+#define MCF_DSPI_DMCR_PCSIS0_LOW (0x00000000)
-+#define MCF_DSPI_DMCR_PCSIS0_HIGH (0x00010000)
-+
-+/* Bit definitions and macros for DTCR */
-+#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16) /* SPI transfer count */
-+
-+/* Bit definitions and macros for DCTAR group */
-+#define MCF_DSPI_DCTAR_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
-+#define MCF_DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
-+#define MCF_DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
-+#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
-+#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
-+#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
-+#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
-+#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
-+#define MCF_DSPI_DCTAR_LSBFE (0x01000000) /* LSB first enable */
-+#define MCF_DSPI_DCTAR_CPHA (0x02000000) /* Clock phase */
-+#define MCF_DSPI_DCTAR_CPOL (0x04000000) /* Clock polarity */
-+#define MCF_DSPI_DCTAR_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
-+#define MCF_DSPI_DCTAR_DBR (0x80000000) /* Double baud rate */
-+#define MCF_DSPI_DCTAR_CPOL_LOW (0x00000000)
-+#define MCF_DSPI_DCTAR_CPOL_HIGH (0x04000000)
-+#define MCF_DSPI_DCTAR_CPHA_LATCH_RISING (0x00000000)
-+#define MCF_DSPI_DCTAR_CPHA_LATCH_FALLING (0x02000000)
-+#define MCF_DSPI_DCTAR_PCSSCK_1CLK (0x00000000)
-+#define MCF_DSPI_DCTAR_PCSSCK_3CLK (0x00400000)
-+#define MCF_DSPI_DCTAR_PCSSCK_5CLK (0x00800000)
-+#define MCF_DSPI_DCTAR_PCSSCK_7CLK (0x00C00000)
-+#define MCF_DSPI_DCTAR_PASC_1CLK (0x00000000)
-+#define MCF_DSPI_DCTAR_PASC_3CLK (0x00100000)
-+#define MCF_DSPI_DCTAR_PASC_5CLK (0x00200000)
-+#define MCF_DSPI_DCTAR_PASC_7CLK (0x00300000)
-+#define MCF_DSPI_DCTAR_PDT_1CLK (0x00000000)
-+#define MCF_DSPI_DCTAR_PDT_3CLK (0x00040000)
-+#define MCF_DSPI_DCTAR_PDT_5CLK (0x00080000)
-+#define MCF_DSPI_DCTAR_PDT_7CLK (0x000C0000)
-+#define MCF_DSPI_DCTAR_PBR_2CLK (0x00000000)
-+#define MCF_DSPI_DCTAR_PBR_3CLK (0x00010000)
-+#define MCF_DSPI_DCTAR_PBR_5CLK (0x00020000)
-+#define MCF_DSPI_DCTAR_PBR_7CLK (0x00030000)
-+
-+/* Bit definitions and macros for DCTAR0 */
-+#define MCF_DSPI_DCTAR0_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
-+#define MCF_DSPI_DCTAR0_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
-+#define MCF_DSPI_DCTAR0_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
-+#define MCF_DSPI_DCTAR0_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
-+#define MCF_DSPI_DCTAR0_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
-+#define MCF_DSPI_DCTAR0_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
-+#define MCF_DSPI_DCTAR0_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
-+#define MCF_DSPI_DCTAR0_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
-+#define MCF_DSPI_DCTAR0_LSBFE (0x01000000) /* LSB first enable */
-+#define MCF_DSPI_DCTAR0_CPHA (0x02000000) /* Clock phase */
-+#define MCF_DSPI_DCTAR0_CPOL (0x04000000) /* Clock polarity */
-+#define MCF_DSPI_DCTAR0_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
-+#define MCF_DSPI_DCTAR0_DBR (0x80000000) /* Double baud rate */
-+#define MCF_DSPI_DCTAR0_CPOL_LOW (0x00000000)
-+#define MCF_DSPI_DCTAR0_CPOL_HIGH (0x04000000)
-+#define MCF_DSPI_DCTAR0_CPHA_LATCH_RISING (0x00000000)
-+#define MCF_DSPI_DCTAR0_CPHA_LATCH_FALLING (0x02000000)
-+#define MCF_DSPI_DCTAR0_PCSSCK_1CLK (0x00000000)
-+#define MCF_DSPI_DCTAR0_PCSSCK_3CLK (0x00400000)
-+#define MCF_DSPI_DCTAR0_PCSSCK_5CLK (0x00800000)
-+#define MCF_DSPI_DCTAR0_PCSSCK_7CLK (0x00C00000)
-+#define MCF_DSPI_DCTAR0_PASC_1CLK (0x00000000)
-+#define MCF_DSPI_DCTAR0_PASC_3CLK (0x00100000)
-+#define MCF_DSPI_DCTAR0_PASC_5CLK (0x00200000)
-+#define MCF_DSPI_DCTAR0_PASC_7CLK (0x00300000)
-+#define MCF_DSPI_DCTAR0_PDT_1CLK (0x00000000)
-+#define MCF_DSPI_DCTAR0_PDT_3CLK (0x00040000)
-+#define MCF_DSPI_DCTAR0_PDT_5CLK (0x00080000)
-+#define MCF_DSPI_DCTAR0_PDT_7CLK (0x000C0000)
-+#define MCF_DSPI_DCTAR0_PBR_2CLK (0x00000000)
-+#define MCF_DSPI_DCTAR0_PBR_3CLK (0x00010000)
-+#define MCF_DSPI_DCTAR0_PBR_5CLK (0x00020000)
-+#define MCF_DSPI_DCTAR0_PBR_7CLK (0x00030000)
-+
-+/* Bit definitions and macros for DCTAR1 */
-+#define MCF_DSPI_DCTAR1_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
-+#define MCF_DSPI_DCTAR1_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
-+#define MCF_DSPI_DCTAR1_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
-+#define MCF_DSPI_DCTAR1_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
-+#define MCF_DSPI_DCTAR1_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
-+#define MCF_DSPI_DCTAR1_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
-+#define MCF_DSPI_DCTAR1_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
-+#define MCF_DSPI_DCTAR1_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
-+#define MCF_DSPI_DCTAR1_LSBFE (0x01000000) /* LSB first enable */
-+#define MCF_DSPI_DCTAR1_CPHA (0x02000000) /* Clock phase */
-+#define MCF_DSPI_DCTAR1_CPOL (0x04000000) /* Clock polarity */
-+#define MCF_DSPI_DCTAR1_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
-+#define MCF_DSPI_DCTAR1_DBR (0x80000000) /* Double baud rate */
-+
-+/* Bit definitions and macros for DCTAR2 */
-+#define MCF_DSPI_DCTAR2_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
-+#define MCF_DSPI_DCTAR2_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
-+#define MCF_DSPI_DCTAR2_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
-+#define MCF_DSPI_DCTAR2_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
-+#define MCF_DSPI_DCTAR2_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
-+#define MCF_DSPI_DCTAR2_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
-+#define MCF_DSPI_DCTAR2_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
-+#define MCF_DSPI_DCTAR2_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
-+#define MCF_DSPI_DCTAR2_LSBFE (0x01000000) /* LSB first enable */
-+#define MCF_DSPI_DCTAR2_CPHA (0x02000000) /* Clock phase */
-+#define MCF_DSPI_DCTAR2_CPOL (0x04000000) /* Clock polarity */
-+#define MCF_DSPI_DCTAR2_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
-+#define MCF_DSPI_DCTAR2_DBR (0x80000000) /* Double baud rate */
-+
-+/* Bit definitions and macros for DCTAR3 */
-+#define MCF_DSPI_DCTAR3_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
-+#define MCF_DSPI_DCTAR3_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
-+#define MCF_DSPI_DCTAR3_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
-+#define MCF_DSPI_DCTAR3_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
-+#define MCF_DSPI_DCTAR3_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
-+#define MCF_DSPI_DCTAR3_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
-+#define MCF_DSPI_DCTAR3_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
-+#define MCF_DSPI_DCTAR3_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
-+#define MCF_DSPI_DCTAR3_LSBFE (0x01000000) /* LSB first enable */
-+#define MCF_DSPI_DCTAR3_CPHA (0x02000000) /* Clock phase */
-+#define MCF_DSPI_DCTAR3_CPOL (0x04000000) /* Clock polarity */
-+#define MCF_DSPI_DCTAR3_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
-+#define MCF_DSPI_DCTAR3_DBR (0x80000000) /* Double baud rate */
-+
-+/* Bit definitions and macros for DCTAR4 */
-+#define MCF_DSPI_DCTAR4_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
-+#define MCF_DSPI_DCTAR4_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
-+#define MCF_DSPI_DCTAR4_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
-+#define MCF_DSPI_DCTAR4_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
-+#define MCF_DSPI_DCTAR4_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
-+#define MCF_DSPI_DCTAR4_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
-+#define MCF_DSPI_DCTAR4_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
-+#define MCF_DSPI_DCTAR4_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
-+#define MCF_DSPI_DCTAR4_LSBFE (0x01000000) /* LSB first enable */
-+#define MCF_DSPI_DCTAR4_CPHA (0x02000000) /* Clock phase */
-+#define MCF_DSPI_DCTAR4_CPOL (0x04000000) /* Clock polarity */
-+#define MCF_DSPI_DCTAR4_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
-+#define MCF_DSPI_DCTAR4_DBR (0x80000000) /* Double baud rate */
-+
-+/* Bit definitions and macros for DCTAR5 */
-+#define MCF_DSPI_DCTAR5_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
-+#define MCF_DSPI_DCTAR5_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
-+#define MCF_DSPI_DCTAR5_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
-+#define MCF_DSPI_DCTAR5_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
-+#define MCF_DSPI_DCTAR5_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
-+#define MCF_DSPI_DCTAR5_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
-+#define MCF_DSPI_DCTAR5_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
-+#define MCF_DSPI_DCTAR5_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
-+#define MCF_DSPI_DCTAR5_LSBFE (0x01000000) /* LSB first enable */
-+#define MCF_DSPI_DCTAR5_CPHA (0x02000000) /* Clock phase */
-+#define MCF_DSPI_DCTAR5_CPOL (0x04000000) /* Clock polarity */
-+#define MCF_DSPI_DCTAR5_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
-+#define MCF_DSPI_DCTAR5_DBR (0x80000000) /* Double baud rate */
-+
-+/* Bit definitions and macros for DCTAR6 */
-+#define MCF_DSPI_DCTAR6_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
-+#define MCF_DSPI_DCTAR6_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
-+#define MCF_DSPI_DCTAR6_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
-+#define MCF_DSPI_DCTAR6_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
-+#define MCF_DSPI_DCTAR6_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
-+#define MCF_DSPI_DCTAR6_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
-+#define MCF_DSPI_DCTAR6_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
-+#define MCF_DSPI_DCTAR6_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
-+#define MCF_DSPI_DCTAR6_LSBFE (0x01000000) /* LSB first enable */
-+#define MCF_DSPI_DCTAR6_CPHA (0x02000000) /* Clock phase */
-+#define MCF_DSPI_DCTAR6_CPOL (0x04000000) /* Clock polarity */
-+#define MCF_DSPI_DCTAR6_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
-+#define MCF_DSPI_DCTAR6_DBR (0x80000000) /* Double baud rate */
-+
-+/* Bit definitions and macros for DCTAR7 */
-+#define MCF_DSPI_DCTAR7_BR(x) (((x)&0x0000000F)) /* Baud rate scaler */
-+#define MCF_DSPI_DCTAR7_DT(x) (((x)&0x0000000F)<<4) /* Delay after transfer scaler */
-+#define MCF_DSPI_DCTAR7_ASC(x) (((x)&0x0000000F)<<8) /* After SCK delay scaler */
-+#define MCF_DSPI_DCTAR7_CSSCK(x) (((x)&0x0000000F)<<12) /* PCS to SCK delay scaler */
-+#define MCF_DSPI_DCTAR7_PBR(x) (((x)&0x00000003)<<16) /* Baud rate prescaler */
-+#define MCF_DSPI_DCTAR7_PDT(x) (((x)&0x00000003)<<18) /* Delay after transfer prescaler */
-+#define MCF_DSPI_DCTAR7_PASC(x) (((x)&0x00000003)<<20) /* After SCK delay prescaler */
-+#define MCF_DSPI_DCTAR7_PCSSCK(x) (((x)&0x00000003)<<22) /* PCS to SCK delay prescaler */
-+#define MCF_DSPI_DCTAR7_LSBFE (0x01000000) /* LSB first enable */
-+#define MCF_DSPI_DCTAR7_CPHA (0x02000000) /* Clock phase */
-+#define MCF_DSPI_DCTAR7_CPOL (0x04000000) /* Clock polarity */
-+#define MCF_DSPI_DCTAR7_FMSZ(x) (((x)&0x0000000F)<<27) /* Frame size */
-+#define MCF_DSPI_DCTAR7_DBR (0x80000000) /* Double baud rate */
-+
-+/* Bit definitions and macros for DSR */
-+#define MCF_DSPI_DSR_RXPTR(x) (((x)&0x0000000F)) /* Receive next pointer */
-+#define MCF_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4) /* Receive FIFO counter */
-+#define MCF_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8) /* Transmit next pointer */
-+#define MCF_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12) /* Transmit FIFO counter */
-+#define MCF_DSPI_DSR_RFDF (0x00020000) /* Receive FIFO drain flag */
-+#define MCF_DSPI_DSR_RFOF (0x00080000) /* Receive FIFO overflow flag */
-+#define MCF_DSPI_DSR_TFFF (0x02000000) /* Transmit FIFO fill flag */
-+#define MCF_DSPI_DSR_TFUF (0x08000000) /* Transmit FIFO underflow flag */
-+#define MCF_DSPI_DSR_EOQF (0x10000000) /* End of queue flag */
-+#define MCF_DSPI_DSR_TXRXS (0x40000000) /* Tx and Rx status (enabled | disabled) */
-+#define MCF_DSPI_DSR_TCF (0x80000000) /* Transfer complete flag */
-+
-+/* Bit definitions and macros for DRSER */
-+#define MCF_DSPI_DRSER_RFDFS (0x00010000) /* Receive FIFO drain DMA or interrupt select */
-+#define MCF_DSPI_DRSER_RFDFE (0x00020000) /* Receive FIFO drain request enable */
-+#define MCF_DSPI_DRSER_RFOFE (0x00080000) /* Receive FIFO overflow request enable */
-+#define MCF_DSPI_DRSER_TFFFS (0x01000000) /* Transmit FIFO fill DMA or interrupt select */
-+#define MCF_DSPI_DRSER_TFFFE (0x02000000) /* Transmit FIFO fill request enable */
-+#define MCF_DSPI_DRSER_TFUFE (0x08000000) /* Transmit FIFO underflow request enable */
-+#define MCF_DSPI_DRSER_EOQFE (0x10000000) /* DSPI finished request enable */
-+#define MCF_DSPI_DRSER_TCFE (0x80000000) /* Transmission complete request enable */
-+
-+/* Bit definitions and macros for DTFR */
-+#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)) /* Transmit data */
-+#define MCF_DSPI_DTFR_PCS0 (0x00010000) /* Peripheral chip select 0 */
-+#define MCF_DSPI_DTFR_PCS1 (0x00020000) /* Peripheral chip select 1 */
-+#define MCF_DSPI_DTFR_PCS2 (0x00040000) /* Peripheral chip select 2 */
-+#define MCF_DSPI_DTFR_PCS3 (0x00080000) /* Peripheral chip select 3 */
-+#define MCF_DSPI_DTFR_PCS4 (0x00100000) /* Peripheral chip select 4 */
-+#define MCF_DSPI_DTFR_PCS5 (0x00200000) /* Peripheral chip select 5 */
-+#define MCF_DSPI_DTFR_PCS6 (0x00400000) /* Peripheral chip select 6 */
-+#define MCF_DSPI_DTFR_PCS7 (0x00800000) /* Peripheral chip select 7 */
-+#define MCF_DSPI_DTFR_CTCNT (0x04000000) /* Clear SPI transfer counter */
-+#define MCF_DSPI_DTFR_EOQ (0x08000000) /* End of queue */
-+#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28) /* Clock and transfer attributes select */
-+#define MCF_DSPI_DTFR_CONT (0x80000000) /* Continuous peripheral chip-select enable */
-+
-+/* Bit definitions and macros for DRFR */
-+#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)) /* Receive data */
-+
-+/* Bit definitions and macros for DTFDR group */
-+#define MCF_DSPI_DTFDR_TXDATA(x) (((x)&0x0000FFFF)) /* Transmit data */
-+#define MCF_DSPI_DTFDR_PCS0 (0x00010000) /* Peripheral chip select 0 */
-+#define MCF_DSPI_DTFDR_PCS1 (0x00020000) /* Peripheral chip select 1 */
-+#define MCF_DSPI_DTFDR_PCS2 (0x00040000) /* Peripheral chip select 2 */
-+#define MCF_DSPI_DTFDR_PCS3 (0x00080000) /* Peripheral chip select 3 */
-+#define MCF_DSPI_DTFDR_PCS4 (0x00100000) /* Peripheral chip select 4 */
-+#define MCF_DSPI_DTFDR_PCS5 (0x00200000) /* Peripheral chip select 5 */
-+#define MCF_DSPI_DTFDR_PCS6 (0x00400000) /* Peripheral chip select 6 */
-+#define MCF_DSPI_DTFDR_PCS7 (0x00800000) /* Peripheral chip select 7 */
-+#define MCF_DSPI_DTFDR_CTCNT (0x04000000) /* Clear SPI transfer counter */
-+#define MCF_DSPI_DTFDR_EOQ (0x08000000) /* End of queue */
-+#define MCF_DSPI_DTFDR_CTAS(x) (((x)&0x00000007)<<28) /* Clock and transfer attributes select */
-+#define MCF_DSPI_DTFDR_CONT (0x80000000) /* Continuous peripheral chip-select enable */
-+
-+/* Bit definitions and macros for DTFDR0 */
-+#define MCF_DSPI_DTFDR0_TXDATA(x) (((x)&0x0000FFFF)) /* Transmit data */
-+#define MCF_DSPI_DTFDR0_PCS0 (0x00010000) /* Peripheral chip select 0 */
-+#define MCF_DSPI_DTFDR0_PCS1 (0x00020000) /* Peripheral chip select 1 */
-+#define MCF_DSPI_DTFDR0_PCS2 (0x00040000) /* Peripheral chip select 2 */
-+#define MCF_DSPI_DTFDR0_PCS3 (0x00080000) /* Peripheral chip select 3 */
-+#define MCF_DSPI_DTFDR0_PCS4 (0x00100000) /* Peripheral chip select 4 */
-+#define MCF_DSPI_DTFDR0_PCS5 (0x00200000) /* Peripheral chip select 5 */
-+#define MCF_DSPI_DTFDR0_PCS6 (0x00400000) /* Peripheral chip select 6 */
-+#define MCF_DSPI_DTFDR0_PCS7 (0x00800000) /* Peripheral chip select 7 */
-+#define MCF_DSPI_DTFDR0_CTCNT (0x04000000) /* Clear SPI transfer counter */
-+#define MCF_DSPI_DTFDR0_EOQ (0x08000000) /* End of queue */
-+#define MCF_DSPI_DTFDR0_CTAS(x) (((x)&0x00000007)<<28) /* Clock and transfer attributes select */
-+#define MCF_DSPI_DTFDR0_CONT (0x80000000) /* Continuous peripheral chip-select enable */
-+
-+/* Bit definitions and macros for DTFDR1 */
-+#define MCF_DSPI_DTFDR1_TXDATA(x) (((x)&0x0000FFFF)) /* Transmit data */
-+#define MCF_DSPI_DTFDR1_PCS0 (0x00010000) /* Peripheral chip select 0 */
-+#define MCF_DSPI_DTFDR1_PCS1 (0x00020000) /* Peripheral chip select 1 */
-+#define MCF_DSPI_DTFDR1_PCS2 (0x00040000) /* Peripheral chip select 2 */
-+#define MCF_DSPI_DTFDR1_PCS3 (0x00080000) /* Peripheral chip select 3 */
-+#define MCF_DSPI_DTFDR1_PCS4 (0x00100000) /* Peripheral chip select 4 */
-+#define MCF_DSPI_DTFDR1_PCS5 (0x00200000) /* Peripheral chip select 5 */
-+#define MCF_DSPI_DTFDR1_PCS6 (0x00400000) /* Peripheral chip select 6 */
-+#define MCF_DSPI_DTFDR1_PCS7 (0x00800000) /* Peripheral chip select 7 */
-+#define MCF_DSPI_DTFDR1_CTCNT (0x04000000) /* Clear SPI transfer counter */
-+#define MCF_DSPI_DTFDR1_EOQ (0x08000000) /* End of queue */
-+#define MCF_DSPI_DTFDR1_CTAS(x) (((x)&0x00000007)<<28) /* Clock and transfer attributes select */
-+#define MCF_DSPI_DTFDR1_CONT (0x80000000) /* Continuous peripheral chip-select enable */
-+
-+/* Bit definitions and macros for DTFDR2 */
-+#define MCF_DSPI_DTFDR2_TXDATA(x) (((x)&0x0000FFFF)) /* Transmit data */
-+#define MCF_DSPI_DTFDR2_PCS0 (0x00010000) /* Peripheral chip select 0 */
-+#define MCF_DSPI_DTFDR2_PCS1 (0x00020000) /* Peripheral chip select 1 */
-+#define MCF_DSPI_DTFDR2_PCS2 (0x00040000) /* Peripheral chip select 2 */
-+#define MCF_DSPI_DTFDR2_PCS3 (0x00080000) /* Peripheral chip select 3 */
-+#define MCF_DSPI_DTFDR2_PCS4 (0x00100000) /* Peripheral chip select 4 */
-+#define MCF_DSPI_DTFDR2_PCS5 (0x00200000) /* Peripheral chip select 5 */
-+#define MCF_DSPI_DTFDR2_PCS6 (0x00400000) /* Peripheral chip select 6 */
-+#define MCF_DSPI_DTFDR2_PCS7 (0x00800000) /* Peripheral chip select 7 */
-+#define MCF_DSPI_DTFDR2_CTCNT (0x04000000) /* Clear SPI transfer counter */
-+#define MCF_DSPI_DTFDR2_EOQ (0x08000000) /* End of queue */
-+#define MCF_DSPI_DTFDR2_CTAS(x) (((x)&0x00000007)<<28) /* Clock and transfer attributes select */
-+#define MCF_DSPI_DTFDR2_CONT (0x80000000) /* Continuous peripheral chip-select enable */
-+
-+/* Bit definitions and macros for DTFDR3 */
-+#define MCF_DSPI_DTFDR3_TXDATA(x) (((x)&0x0000FFFF)) /* Transmit data */
-+#define MCF_DSPI_DTFDR3_PCS0 (0x00010000) /* Peripheral chip select 0 */
-+#define MCF_DSPI_DTFDR3_PCS1 (0x00020000) /* Peripheral chip select 1 */
-+#define MCF_DSPI_DTFDR3_PCS2 (0x00040000) /* Peripheral chip select 2 */
-+#define MCF_DSPI_DTFDR3_PCS3 (0x00080000) /* Peripheral chip select 3 */
-+#define MCF_DSPI_DTFDR3_PCS4 (0x00100000) /* Peripheral chip select 4 */
-+#define MCF_DSPI_DTFDR3_PCS5 (0x00200000) /* Peripheral chip select 5 */
-+#define MCF_DSPI_DTFDR3_PCS6 (0x00400000) /* Peripheral chip select 6 */
-+#define MCF_DSPI_DTFDR3_PCS7 (0x00800000) /* Peripheral chip select 7 */
-+#define MCF_DSPI_DTFDR3_CTCNT (0x04000000) /* Clear SPI transfer counter */
-+#define MCF_DSPI_DTFDR3_EOQ (0x08000000) /* End of queue */
-+#define MCF_DSPI_DTFDR3_CTAS(x) (((x)&0x00000007)<<28) /* Clock and transfer attributes select */
-+#define MCF_DSPI_DTFDR3_CONT (0x80000000) /* Continuous peripheral chip-select enable */
-+
-+/* Bit definitions and macros for DRFDR group */
-+#define MCF_DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF)) /* Receive data */
-+
-+/* Bit definitions and macros for DRFDR0 */
-+#define MCF_DSPI_DRFDR0_RXDATA(x) (((x)&0x0000FFFF)) /* Receive data */
-+
-+/* Bit definitions and macros for DRFDR1 */
-+#define MCF_DSPI_DRFDR1_RXDATA(x) (((x)&0x0000FFFF)) /* Receive data */
-+
-+/* Bit definitions and macros for DRFDR2 */
-+#define MCF_DSPI_DRFDR2_RXDATA(x) (((x)&0x0000FFFF)) /* Receive data */
-+
-+/* Bit definitions and macros for DRFDR3 */
-+#define MCF_DSPI_DRFDR3_RXDATA(x) (((x)&0x0000FFFF)) /* Receive data */
-+
-+/********************************************************************/
-+
-+#endif /* __MCF5445X_DSPI_H__ */
---- /dev/null
-+++ b/include/asm-m68k/mcf5445x_dtim.h
-@@ -0,0 +1,87 @@
-+/*
-+ * Matt Waddel Matt.Waddel@freescale.com
-+ *
-+ * Copyright Freescale Semiconductor, Inc. 2007
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+
-+#ifndef __MCF5445X_DTIM_H__
-+#define __MCF5445X_DTIM_H__
-+
-+/*********************************************************************
-+*
-+* DMA Timers (DTIM)
-+*
-+*********************************************************************/
-+/* Register read/write macros */
-+#define MCF_DTIM0_DTMR 0xFC070000 /* DMA Timer Mode Register */
-+#define MCF_DTIM0_DTXMR 0xFC070002 /* DMA Timer Extended Mode Register */
-+#define MCF_DTIM0_DTER 0xFC070003 /* DMA Timer Event Register */
-+#define MCF_DTIM0_DTRR 0xFC070004 /* DMA Timer Reference Register */
-+#define MCF_DTIM0_DTCR 0xFC070008 /* DMA Timer Capture Register */
-+#define MCF_DTIM0_DTCN 0xFC07000C /* DMA Timer Counter Register */
-+#define MCF_DTIM1_DTMR 0xFC074000 /* DMA Timer Mode Register */
-+#define MCF_DTIM1_DTXMR 0xFC074002 /* DMA Timer Extended Mode Register */
-+#define MCF_DTIM1_DTER 0xFC074003 /* DMA Timer Event Register */
-+#define MCF_DTIM1_DTRR 0xFC074004 /* DMA Timer Reference Register */
-+#define MCF_DTIM1_DTCR 0xFC074008 /* DMA Timer Capture Register */
-+#define MCF_DTIM1_DTCN 0xFC07400C /* DMA Timer Counter Register */
-+#define MCF_DTIM2_DTMR 0xFC078000 /* DMA Timer Mode Register */
-+#define MCF_DTIM2_DTXMR 0xFC078002 /* DMA Timer Extended Mode Register */
-+#define MCF_DTIM2_DTER 0xFC078003 /* DMA Timer Event Register */
-+#define MCF_DTIM2_DTRR 0xFC078004 /* DMA Timer Reference Register */
-+#define MCF_DTIM2_DTCR 0xFC078008 /* DMA Timer Capture Register */
-+#define MCF_DTIM2_DTCN 0xFC07800C /* DMA Timer Counter Register */
-+#define MCF_DTIM3_DTMR 0xFC07C000 /* DMA Timer Mode Register */
-+#define MCF_DTIM3_DTXMR 0xFC07C002 /* DMA Timer Extended Mode Register */
-+#define MCF_DTIM3_DTER 0xFC07C003 /* DMA Timer Event Register */
-+#define MCF_DTIM3_DTRR 0xFC07C004 /* DMA Timer Reference Register */
-+#define MCF_DTIM3_DTCR 0xFC07C008 /* DMA Timer Capture Register */
-+#define MCF_DTIM3_DTCN 0xFC07C00C /* DMA Timer Counter Register */
-+
-+/* Parameterized register read/write macros for multiple modules */
-+#define MCF_DTIM_DTMR(x) 0xFC070000+((x)*0x4000) /* DMA Timer Mode Register */
-+#define MCF_DTIM_DTXMR(x) 0xFC070002+((x)*0x4000) /* DMA Timer Extended Mode Register */
-+#define MCF_DTIM_DTER(x) 0xFC070003+((x)*0x4000) /* DMA Timer Event Register */
-+#define MCF_DTIM_DTRR(x) 0xFC070004+((x)*0x4000) /* DMA Timer Reference Register */
-+#define MCF_DTIM_DTCR(x) 0xFC070008+((x)*0x4000) /* DMA Timer Capture Register */
-+#define MCF_DTIM_DTCN(x) 0xFC07000C+((x)*0x4000) /* DMA Timer Counter Register */
-+
-+/* Bit definitions and macros for DTMR */
-+#define MCF_DTIM_DTMR_RST (0x0001) /* Reset */
-+#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */
-+#define MCF_DTIM_DTMR_FRR (0x0008) /* Free run/restart */
-+#define MCF_DTIM_DTMR_ORRI (0x0010) /* Output reference request/interrupt enable */
-+#define MCF_DTIM_DTMR_OM (0x0020) /* Output Mode */
-+#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */
-+#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */
-+#define MCF_DTIM_DTMR_RST_EN (0x0001)
-+#define MCF_DTIM_DTMR_RST_RST (0x0000)
-+#define MCF_DTIM_DTMR_CE_ANY (0x00C0)
-+#define MCF_DTIM_DTMR_CE_FALL (0x0080)
-+#define MCF_DTIM_DTMR_CE_RISE (0x0040)
-+#define MCF_DTIM_DTMR_CE_NONE (0x0000)
-+#define MCF_DTIM_DTMR_CLK_DTIN (0x0006)
-+#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004)
-+#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002)
-+#define MCF_DTIM_DTMR_CLK_STOP (0x0000)
-+
-+/* Bit definitions and macros for DTXMR */
-+#define MCF_DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */
-+#define MCF_DTIM_DTXMR_DMAEN (0x80) /* DMA request */
-+
-+/* Bit definitions and macros for DTER */
-+#define MCF_DTIM_DTER_CAP (0x01) /* Capture event */
-+#define MCF_DTIM_DTER_REF (0x02) /* Output reference event */
-+
-+/* Interrupts used for system timers */
-+#define MCFSIM_ICR_TIMER1 (0xFC048040+32)
-+#define MCFSIM_ICR_TIMER2 (0xFC048040+33)
-+
-+/********************************************************************/
-+
-+#endif /* __MCF5445X_DTIM_H__ */
---- /dev/null
-+++ b/include/asm-m68k/mcf5445x_edma.h
-@@ -0,0 +1,1458 @@
-+/*
-+ * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
-+ *
-+ * Copyright Freescale Semiconductor, Inc. 2007
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+#ifndef __MCF5445X_EDMA_H__
-+#define __MCF5445X_EDMA_H__
-+
-+/*********************************************************************
-+*
-+* Enhanced DMA (EDMA)
-+*
-+*********************************************************************/
-+
-+/* Register read/write macros */
-+#define MCF_EDMA_CR MCF_REG32(0xFC044000)
-+#define MCF_EDMA_ES MCF_REG32(0xFC044004)
-+#define MCF_EDMA_ERQ MCF_REG16(0xFC04400E)
-+#define MCF_EDMA_EEI MCF_REG16(0xFC044016)
-+#define MCF_EDMA_SERQ MCF_REG08(0xFC044018)
-+#define MCF_EDMA_CERQ MCF_REG08(0xFC044019)
-+#define MCF_EDMA_SEEI MCF_REG08(0xFC04401A)
-+#define MCF_EDMA_CEEI MCF_REG08(0xFC04401B)
-+#define MCF_EDMA_CINT MCF_REG08(0xFC04401C)
-+#define MCF_EDMA_CERR MCF_REG08(0xFC04401D)
-+#define MCF_EDMA_SSRT MCF_REG08(0xFC04401E)
-+#define MCF_EDMA_CDNE MCF_REG08(0xFC04401F)
-+#define MCF_EDMA_INTR MCF_REG16(0xFC044026)
-+#define MCF_EDMA_ERR MCF_REG16(0xFC04402E)
-+#define MCF_EDMA_DCHPRI0 MCF_REG08(0xFC044100)
-+#define MCF_EDMA_DCHPRI1 MCF_REG08(0xFC044101)
-+#define MCF_EDMA_DCHPRI2 MCF_REG08(0xFC044102)
-+#define MCF_EDMA_DCHPRI3 MCF_REG08(0xFC044103)
-+#define MCF_EDMA_DCHPRI4 MCF_REG08(0xFC044104)
-+#define MCF_EDMA_DCHPRI5 MCF_REG08(0xFC044105)
-+#define MCF_EDMA_DCHPRI6 MCF_REG08(0xFC044106)
-+#define MCF_EDMA_DCHPRI7 MCF_REG08(0xFC044107)
-+#define MCF_EDMA_DCHPRI8 MCF_REG08(0xFC044108)
-+#define MCF_EDMA_DCHPRI9 MCF_REG08(0xFC044109)
-+#define MCF_EDMA_DCHPRI10 MCF_REG08(0xFC04410A)
-+#define MCF_EDMA_DCHPRI11 MCF_REG08(0xFC04410B)
-+#define MCF_EDMA_DCHPRI12 MCF_REG08(0xFC04410C)
-+#define MCF_EDMA_DCHPRI13 MCF_REG08(0xFC04410D)
-+#define MCF_EDMA_DCHPRI14 MCF_REG08(0xFC04410E)
-+#define MCF_EDMA_DCHPRI15 MCF_REG08(0xFC04410F)
-+#define MCF_EDMA_TCD0_SADDR MCF_REG32(0xFC045000)
-+#define MCF_EDMA_TCD0_ATTR MCF_REG16(0xFC045004)
-+#define MCF_EDMA_TCD0_SOFF MCF_REG16(0xFC045006)
-+#define MCF_EDMA_TCD0_NBYTES MCF_REG32(0xFC045008)
-+#define MCF_EDMA_TCD0_SLAST MCF_REG32(0xFC04500C)
-+#define MCF_EDMA_TCD0_DADDR MCF_REG32(0xFC045010)
-+#define MCF_EDMA_TCD0_CITER_ELINK MCF_REG16(0xFC045014)
-+#define MCF_EDMA_TCD0_CITER MCF_REG16(0xFC045014)
-+#define MCF_EDMA_TCD0_DOFF MCF_REG16(0xFC045016)
-+#define MCF_EDMA_TCD0_DLAST_SGA MCF_REG32(0xFC045018)
-+#define MCF_EDMA_TCD0_BITER_ELINK MCF_REG16(0xFC04501C)
-+#define MCF_EDMA_TCD0_BITER MCF_REG16(0xFC04501C)
-+#define MCF_EDMA_TCD0_CSR MCF_REG16(0xFC04501E)
-+#define MCF_EDMA_TCD1_SADDR MCF_REG32(0xFC045020)
-+#define MCF_EDMA_TCD1_ATTR MCF_REG16(0xFC045024)
-+#define MCF_EDMA_TCD1_SOFF MCF_REG16(0xFC045026)
-+#define MCF_EDMA_TCD1_NBYTES MCF_REG32(0xFC045028)
-+#define MCF_EDMA_TCD1_SLAST MCF_REG32(0xFC04502C)
-+#define MCF_EDMA_TCD1_DADDR MCF_REG32(0xFC045030)
-+#define MCF_EDMA_TCD1_CITER_ELINK MCF_REG16(0xFC045034)
-+#define MCF_EDMA_TCD1_CITER MCF_REG16(0xFC045034)
-+#define MCF_EDMA_TCD1_DOFF MCF_REG16(0xFC045036)
-+#define MCF_EDMA_TCD1_DLAST_SGA MCF_REG32(0xFC045038)
-+#define MCF_EDMA_TCD1_BITER MCF_REG16(0xFC04503C)
-+#define MCF_EDMA_TCD1_BITER_ELINK MCF_REG16(0xFC04503C)
-+#define MCF_EDMA_TCD1_CSR MCF_REG16(0xFC04503E)
-+#define MCF_EDMA_TCD2_SADDR MCF_REG32(0xFC045040)
-+#define MCF_EDMA_TCD2_ATTR MCF_REG16(0xFC045044)
-+#define MCF_EDMA_TCD2_SOFF MCF_REG16(0xFC045046)
-+#define MCF_EDMA_TCD2_NBYTES MCF_REG32(0xFC045048)
-+#define MCF_EDMA_TCD2_SLAST MCF_REG32(0xFC04504C)
-+#define MCF_EDMA_TCD2_DADDR MCF_REG32(0xFC045050)
-+#define MCF_EDMA_TCD2_CITER MCF_REG16(0xFC045054)
-+#define MCF_EDMA_TCD2_CITER_ELINK MCF_REG16(0xFC045054)
-+#define MCF_EDMA_TCD2_DOFF MCF_REG16(0xFC045056)
-+#define MCF_EDMA_TCD2_DLAST_SGA MCF_REG32(0xFC045058)
-+#define MCF_EDMA_TCD2_BITER_ELINK MCF_REG16(0xFC04505C)
-+#define MCF_EDMA_TCD2_BITER MCF_REG16(0xFC04505C)
-+#define MCF_EDMA_TCD2_CSR MCF_REG16(0xFC04505E)
-+#define MCF_EDMA_TCD3_SADDR MCF_REG32(0xFC045060)
-+#define MCF_EDMA_TCD3_ATTR MCF_REG16(0xFC045064)
-+#define MCF_EDMA_TCD3_SOFF MCF_REG16(0xFC045066)
-+#define MCF_EDMA_TCD3_NBYTES MCF_REG32(0xFC045068)
-+#define MCF_EDMA_TCD3_SLAST MCF_REG32(0xFC04506C)
-+#define MCF_EDMA_TCD3_DADDR MCF_REG32(0xFC045070)
-+#define MCF_EDMA_TCD3_CITER MCF_REG16(0xFC045074)
-+#define MCF_EDMA_TCD3_CITER_ELINK MCF_REG16(0xFC045074)
-+#define MCF_EDMA_TCD3_DOFF MCF_REG16(0xFC045076)
-+#define MCF_EDMA_TCD3_DLAST_SGA MCF_REG32(0xFC045078)
-+#define MCF_EDMA_TCD3_BITER_ELINK MCF_REG16(0xFC04507C)
-+#define MCF_EDMA_TCD3_BITER MCF_REG16(0xFC04507C)
-+#define MCF_EDMA_TCD3_CSR MCF_REG16(0xFC04507E)
-+#define MCF_EDMA_TCD4_SADDR MCF_REG32(0xFC045080)
-+#define MCF_EDMA_TCD4_ATTR MCF_REG16(0xFC045084)
-+#define MCF_EDMA_TCD4_SOFF MCF_REG16(0xFC045086)
-+#define MCF_EDMA_TCD4_NBYTES MCF_REG32(0xFC045088)
-+#define MCF_EDMA_TCD4_SLAST MCF_REG32(0xFC04508C)
-+#define MCF_EDMA_TCD4_DADDR MCF_REG32(0xFC045090)
-+#define MCF_EDMA_TCD4_CITER MCF_REG16(0xFC045094)
-+#define MCF_EDMA_TCD4_CITER_ELINK MCF_REG16(0xFC045094)
-+#define MCF_EDMA_TCD4_DOFF MCF_REG16(0xFC045096)
-+#define MCF_EDMA_TCD4_DLAST_SGA MCF_REG32(0xFC045098)
-+#define MCF_EDMA_TCD4_BITER MCF_REG16(0xFC04509C)
-+#define MCF_EDMA_TCD4_BITER_ELINK MCF_REG16(0xFC04509C)
-+#define MCF_EDMA_TCD4_CSR MCF_REG16(0xFC04509E)
-+#define MCF_EDMA_TCD5_SADDR MCF_REG32(0xFC0450A0)
-+#define MCF_EDMA_TCD5_ATTR MCF_REG16(0xFC0450A4)
-+#define MCF_EDMA_TCD5_SOFF MCF_REG16(0xFC0450A6)
-+#define MCF_EDMA_TCD5_NBYTES MCF_REG32(0xFC0450A8)
-+#define MCF_EDMA_TCD5_SLAST MCF_REG32(0xFC0450AC)
-+#define MCF_EDMA_TCD5_DADDR MCF_REG32(0xFC0450B0)
-+#define MCF_EDMA_TCD5_CITER MCF_REG16(0xFC0450B4)
-+#define MCF_EDMA_TCD5_CITER_ELINK MCF_REG16(0xFC0450B4)
-+#define MCF_EDMA_TCD5_DOFF MCF_REG16(0xFC0450B6)
-+#define MCF_EDMA_TCD5_DLAST_SGA MCF_REG32(0xFC0450B8)
-+#define MCF_EDMA_TCD5_BITER_ELINK MCF_REG16(0xFC0450BC)
-+#define MCF_EDMA_TCD5_BITER MCF_REG16(0xFC0450BC)
-+#define MCF_EDMA_TCD5_CSR MCF_REG16(0xFC0450BE)
-+#define MCF_EDMA_TCD6_SADDR MCF_REG32(0xFC0450C0)
-+#define MCF_EDMA_TCD6_ATTR MCF_REG16(0xFC0450C4)
-+#define MCF_EDMA_TCD6_SOFF MCF_REG16(0xFC0450C6)
-+#define MCF_EDMA_TCD6_NBYTES MCF_REG32(0xFC0450C8)
-+#define MCF_EDMA_TCD6_SLAST MCF_REG32(0xFC0450CC)
-+#define MCF_EDMA_TCD6_DADDR MCF_REG32(0xFC0450D0)
-+#define MCF_EDMA_TCD6_CITER MCF_REG16(0xFC0450D4)
-+#define MCF_EDMA_TCD6_CITER_ELINK MCF_REG16(0xFC0450D4)
-+#define MCF_EDMA_TCD6_DOFF MCF_REG16(0xFC0450D6)
-+#define MCF_EDMA_TCD6_DLAST_SGA MCF_REG32(0xFC0450D8)
-+#define MCF_EDMA_TCD6_BITER_ELINK MCF_REG16(0xFC0450DC)
-+#define MCF_EDMA_TCD6_BITER MCF_REG16(0xFC0450DC)
-+#define MCF_EDMA_TCD6_CSR MCF_REG16(0xFC0450DE)
-+#define MCF_EDMA_TCD7_SADDR MCF_REG32(0xFC0450E0)
-+#define MCF_EDMA_TCD7_ATTR MCF_REG16(0xFC0450E4)
-+#define MCF_EDMA_TCD7_SOFF MCF_REG16(0xFC0450E6)
-+#define MCF_EDMA_TCD7_NBYTES MCF_REG32(0xFC0450E8)
-+#define MCF_EDMA_TCD7_SLAST MCF_REG32(0xFC0450EC)
-+#define MCF_EDMA_TCD7_DADDR MCF_REG32(0xFC0450F0)
-+#define MCF_EDMA_TCD7_CITER MCF_REG16(0xFC0450F4)
-+#define MCF_EDMA_TCD7_CITER_ELINK MCF_REG16(0xFC0450F4)
-+#define MCF_EDMA_TCD7_DOFF MCF_REG16(0xFC0450F6)
-+#define MCF_EDMA_TCD7_DLAST_SGA MCF_REG32(0xFC0450F8)
-+#define MCF_EDMA_TCD7_BITER_ELINK MCF_REG16(0xFC0450FC)
-+#define MCF_EDMA_TCD7_BITER MCF_REG16(0xFC0450FC)
-+#define MCF_EDMA_TCD7_CSR MCF_REG16(0xFC0450FE)
-+#define MCF_EDMA_TCD8_SADDR MCF_REG32(0xFC045100)
-+#define MCF_EDMA_TCD8_ATTR MCF_REG16(0xFC045104)
-+#define MCF_EDMA_TCD8_SOFF MCF_REG16(0xFC045106)
-+#define MCF_EDMA_TCD8_NBYTES MCF_REG32(0xFC045108)
-+#define MCF_EDMA_TCD8_SLAST MCF_REG32(0xFC04510C)
-+#define MCF_EDMA_TCD8_DADDR MCF_REG32(0xFC045110)
-+#define MCF_EDMA_TCD8_CITER MCF_REG16(0xFC045114)
-+#define MCF_EDMA_TCD8_CITER_ELINK MCF_REG16(0xFC045114)
-+#define MCF_EDMA_TCD8_DOFF MCF_REG16(0xFC045116)
-+#define MCF_EDMA_TCD8_DLAST_SGA MCF_REG32(0xFC045118)
-+#define MCF_EDMA_TCD8_BITER_ELINK MCF_REG16(0xFC04511C)
-+#define MCF_EDMA_TCD8_BITER MCF_REG16(0xFC04511C)
-+#define MCF_EDMA_TCD8_CSR MCF_REG16(0xFC04511E)
-+#define MCF_EDMA_TCD9_SADDR MCF_REG32(0xFC045120)
-+#define MCF_EDMA_TCD9_ATTR MCF_REG16(0xFC045124)
-+#define MCF_EDMA_TCD9_SOFF MCF_REG16(0xFC045126)
-+#define MCF_EDMA_TCD9_NBYTES MCF_REG32(0xFC045128)
-+#define MCF_EDMA_TCD9_SLAST MCF_REG32(0xFC04512C)
-+#define MCF_EDMA_TCD9_DADDR MCF_REG32(0xFC045130)
-+#define MCF_EDMA_TCD9_CITER_ELINK MCF_REG16(0xFC045134)
-+#define MCF_EDMA_TCD9_CITER MCF_REG16(0xFC045134)
-+#define MCF_EDMA_TCD9_DOFF MCF_REG16(0xFC045136)
-+#define MCF_EDMA_TCD9_DLAST_SGA MCF_REG32(0xFC045138)
-+#define MCF_EDMA_TCD9_BITER_ELINK MCF_REG16(0xFC04513C)
-+#define MCF_EDMA_TCD9_BITER MCF_REG16(0xFC04513C)
-+#define MCF_EDMA_TCD9_CSR MCF_REG16(0xFC04513E)
-+#define MCF_EDMA_TCD10_SADDR MCF_REG32(0xFC045140)
-+#define MCF_EDMA_TCD10_ATTR MCF_REG16(0xFC045144)
-+#define MCF_EDMA_TCD10_SOFF MCF_REG16(0xFC045146)
-+#define MCF_EDMA_TCD10_NBYTES MCF_REG32(0xFC045148)
-+#define MCF_EDMA_TCD10_SLAST MCF_REG32(0xFC04514C)
-+#define MCF_EDMA_TCD10_DADDR MCF_REG32(0xFC045150)
-+#define MCF_EDMA_TCD10_CITER_ELINK MCF_REG16(0xFC045154)
-+#define MCF_EDMA_TCD10_CITER MCF_REG16(0xFC045154)
-+#define MCF_EDMA_TCD10_DOFF MCF_REG16(0xFC045156)
-+#define MCF_EDMA_TCD10_DLAST_SGA MCF_REG32(0xFC045158)
-+#define MCF_EDMA_TCD10_BITER MCF_REG16(0xFC04515C)
-+#define MCF_EDMA_TCD10_BITER_ELINK MCF_REG16(0xFC04515C)
-+#define MCF_EDMA_TCD10_CSR MCF_REG16(0xFC04515E)
-+#define MCF_EDMA_TCD11_SADDR MCF_REG32(0xFC045160)
-+#define MCF_EDMA_TCD11_ATTR MCF_REG16(0xFC045164)
-+#define MCF_EDMA_TCD11_SOFF MCF_REG16(0xFC045166)
-+#define MCF_EDMA_TCD11_NBYTES MCF_REG32(0xFC045168)
-+#define MCF_EDMA_TCD11_SLAST MCF_REG32(0xFC04516C)
-+#define MCF_EDMA_TCD11_DADDR MCF_REG32(0xFC045170)
-+#define MCF_EDMA_TCD11_CITER MCF_REG16(0xFC045174)
-+#define MCF_EDMA_TCD11_CITER_ELINK MCF_REG16(0xFC045174)
-+#define MCF_EDMA_TCD11_DOFF MCF_REG16(0xFC045176)
-+#define MCF_EDMA_TCD11_DLAST_SGA MCF_REG32(0xFC045178)
-+#define MCF_EDMA_TCD11_BITER MCF_REG16(0xFC04517C)
-+#define MCF_EDMA_TCD11_BITER_ELINK MCF_REG16(0xFC04517C)
-+#define MCF_EDMA_TCD11_CSR MCF_REG16(0xFC04517E)
-+#define MCF_EDMA_TCD12_SADDR MCF_REG32(0xFC045180)
-+#define MCF_EDMA_TCD12_ATTR MCF_REG16(0xFC045184)
-+#define MCF_EDMA_TCD12_SOFF MCF_REG16(0xFC045186)
-+#define MCF_EDMA_TCD12_NBYTES MCF_REG32(0xFC045188)
-+#define MCF_EDMA_TCD12_SLAST MCF_REG32(0xFC04518C)
-+#define MCF_EDMA_TCD12_DADDR MCF_REG32(0xFC045190)
-+#define MCF_EDMA_TCD12_CITER MCF_REG16(0xFC045194)
-+#define MCF_EDMA_TCD12_CITER_ELINK MCF_REG16(0xFC045194)
-+#define MCF_EDMA_TCD12_DOFF MCF_REG16(0xFC045196)
-+#define MCF_EDMA_TCD12_DLAST_SGA MCF_REG32(0xFC045198)
-+#define MCF_EDMA_TCD12_BITER MCF_REG16(0xFC04519C)
-+#define MCF_EDMA_TCD12_BITER_ELINK MCF_REG16(0xFC04519C)
-+#define MCF_EDMA_TCD12_CSR MCF_REG16(0xFC04519E)
-+#define MCF_EDMA_TCD13_SADDR MCF_REG32(0xFC0451A0)
-+#define MCF_EDMA_TCD13_ATTR MCF_REG16(0xFC0451A4)
-+#define MCF_EDMA_TCD13_SOFF MCF_REG16(0xFC0451A6)
-+#define MCF_EDMA_TCD13_NBYTES MCF_REG32(0xFC0451A8)
-+#define MCF_EDMA_TCD13_SLAST MCF_REG32(0xFC0451AC)
-+#define MCF_EDMA_TCD13_DADDR MCF_REG32(0xFC0451B0)
-+#define MCF_EDMA_TCD13_CITER_ELINK MCF_REG16(0xFC0451B4)
-+#define MCF_EDMA_TCD13_CITER MCF_REG16(0xFC0451B4)
-+#define MCF_EDMA_TCD13_DOFF MCF_REG16(0xFC0451B6)
-+#define MCF_EDMA_TCD13_DLAST_SGA MCF_REG32(0xFC0451B8)
-+#define MCF_EDMA_TCD13_BITER_ELINK MCF_REG16(0xFC0451BC)
-+#define MCF_EDMA_TCD13_BITER MCF_REG16(0xFC0451BC)
-+#define MCF_EDMA_TCD13_CSR MCF_REG16(0xFC0451BE)
-+#define MCF_EDMA_TCD14_SADDR MCF_REG32(0xFC0451C0)
-+#define MCF_EDMA_TCD14_ATTR MCF_REG16(0xFC0451C4)
-+#define MCF_EDMA_TCD14_SOFF MCF_REG16(0xFC0451C6)
-+#define MCF_EDMA_TCD14_NBYTES MCF_REG32(0xFC0451C8)
-+#define MCF_EDMA_TCD14_SLAST MCF_REG32(0xFC0451CC)
-+#define MCF_EDMA_TCD14_DADDR MCF_REG32(0xFC0451D0)
-+#define MCF_EDMA_TCD14_CITER MCF_REG16(0xFC0451D4)
-+#define MCF_EDMA_TCD14_CITER_ELINK MCF_REG16(0xFC0451D4)
-+#define MCF_EDMA_TCD14_DOFF MCF_REG16(0xFC0451D6)
-+#define MCF_EDMA_TCD14_DLAST_SGA MCF_REG32(0xFC0451D8)
-+#define MCF_EDMA_TCD14_BITER_ELINK MCF_REG16(0xFC0451DC)
-+#define MCF_EDMA_TCD14_BITER MCF_REG16(0xFC0451DC)
-+#define MCF_EDMA_TCD14_CSR MCF_REG16(0xFC0451DE)
-+#define MCF_EDMA_TCD15_SADDR MCF_REG32(0xFC0451E0)
-+#define MCF_EDMA_TCD15_ATTR MCF_REG16(0xFC0451E4)
-+#define MCF_EDMA_TCD15_SOFF MCF_REG16(0xFC0451E6)
-+#define MCF_EDMA_TCD15_NBYTES MCF_REG32(0xFC0451E8)
-+#define MCF_EDMA_TCD15_SLAST MCF_REG32(0xFC0451EC)
-+#define MCF_EDMA_TCD15_DADDR MCF_REG32(0xFC0451F0)
-+#define MCF_EDMA_TCD15_CITER_ELINK MCF_REG16(0xFC0451F4)
-+#define MCF_EDMA_TCD15_CITER MCF_REG16(0xFC0451F4)
-+#define MCF_EDMA_TCD15_DOFF MCF_REG16(0xFC0451F6)
-+#define MCF_EDMA_TCD15_DLAST_SGA MCF_REG32(0xFC0451F8)
-+#define MCF_EDMA_TCD15_BITER MCF_REG16(0xFC0451FC)
-+#define MCF_EDMA_TCD15_BITER_ELINK MCF_REG16(0xFC0451FC)
-+#define MCF_EDMA_TCD15_CSR MCF_REG16(0xFC0451FE)
-+
-+/* Parameterized register read/write macros for multiple registers */
-+#define MCF_EDMA_DCHPRI(x) MCF_REG08(0xFC044100+((x)*0x001))
-+#define MCF_EDMA_TCD_SADDR(x) MCF_REG32(0xFC045000+((x)*0x020))
-+#define MCF_EDMA_TCD_ATTR(x) MCF_REG16(0xFC045004+((x)*0x020))
-+#define MCF_EDMA_TCD_SOFF(x) MCF_REG16(0xFC045006+((x)*0x020))
-+#define MCF_EDMA_TCD_NBYTES(x) MCF_REG32(0xFC045008+((x)*0x020))
-+#define MCF_EDMA_TCD_SLAST(x) MCF_REG32(0xFC04500C+((x)*0x020))
-+#define MCF_EDMA_TCD_DADDR(x) MCF_REG32(0xFC045010+((x)*0x020))
-+#define MCF_EDMA_TCD_CITER_ELINK(x) MCF_REG16(0xFC045014+((x)*0x020))
-+#define MCF_EDMA_TCD_CITER(x) MCF_REG16(0xFC045014+((x)*0x020))
-+#define MCF_EDMA_TCD_DOFF(x) MCF_REG16(0xFC045016+((x)*0x020))
-+#define MCF_EDMA_TCD_DLAST_SGA(x) MCF_REG32(0xFC045018+((x)*0x020))
-+#define MCF_EDMA_TCD_BITER_ELINK(x) MCF_REG16(0xFC04501C+((x)*0x020))
-+#define MCF_EDMA_TCD_BITER(x) MCF_REG16(0xFC04501C+((x)*0x020))
-+#define MCF_EDMA_TCD_CSR(x) MCF_REG16(0xFC04501e +((x)*0x020))
-+
-+/* Bit definitions and macros for CR */
-+#define MCF_EDMA_CR_EDBG (0x00000002)
-+#define MCF_EDMA_CR_ERCA (0x00000004)
-+
-+/* Bit definitions and macros for ES */
-+#define MCF_EDMA_ES_DBE (0x00000001)
-+#define MCF_EDMA_ES_SBE (0x00000002)
-+#define MCF_EDMA_ES_SGE (0x00000004)
-+#define MCF_EDMA_ES_NCE (0x00000008)
-+#define MCF_EDMA_ES_DOE (0x00000010)
-+#define MCF_EDMA_ES_DAE (0x00000020)
-+#define MCF_EDMA_ES_SOE (0x00000040)
-+#define MCF_EDMA_ES_SAE (0x00000080)
-+#define MCF_EDMA_ES_ERRCHN(x) (((x)&0x0000000F)<<8)
-+#define MCF_EDMA_ES_CPE (0x00004000)
-+#define MCF_EDMA_ES_VLD (0x80000000)
-+
-+/* Bit definitions and macros for ERQ */
-+#define MCF_EDMA_ERQ_ERQ0 (0x0001)
-+#define MCF_EDMA_ERQ_ERQ1 (0x0002)
-+#define MCF_EDMA_ERQ_ERQ2 (0x0004)
-+#define MCF_EDMA_ERQ_ERQ3 (0x0008)
-+#define MCF_EDMA_ERQ_ERQ4 (0x0010)
-+#define MCF_EDMA_ERQ_ERQ5 (0x0020)
-+#define MCF_EDMA_ERQ_ERQ6 (0x0040)
-+#define MCF_EDMA_ERQ_ERQ7 (0x0080)
-+#define MCF_EDMA_ERQ_ERQ8 (0x0100)
-+#define MCF_EDMA_ERQ_ERQ9 (0x0200)
-+#define MCF_EDMA_ERQ_ERQ10 (0x0400)
-+#define MCF_EDMA_ERQ_ERQ11 (0x0800)
-+#define MCF_EDMA_ERQ_ERQ12 (0x1000)
-+#define MCF_EDMA_ERQ_ERQ13 (0x2000)
-+#define MCF_EDMA_ERQ_ERQ14 (0x4000)
-+#define MCF_EDMA_ERQ_ERQ15 (0x8000)
-+
-+/* Bit definitions and macros for EEI */
-+#define MCF_EDMA_EEI_EEI0 (0x0001)
-+#define MCF_EDMA_EEI_EEI1 (0x0002)
-+#define MCF_EDMA_EEI_EEI2 (0x0004)
-+#define MCF_EDMA_EEI_EEI3 (0x0008)
-+#define MCF_EDMA_EEI_EEI4 (0x0010)
-+#define MCF_EDMA_EEI_EEI5 (0x0020)
-+#define MCF_EDMA_EEI_EEI6 (0x0040)
-+#define MCF_EDMA_EEI_EEI7 (0x0080)
-+#define MCF_EDMA_EEI_EEI8 (0x0100)
-+#define MCF_EDMA_EEI_EEI9 (0x0200)
-+#define MCF_EDMA_EEI_EEI10 (0x0400)
-+#define MCF_EDMA_EEI_EEI11 (0x0800)
-+#define MCF_EDMA_EEI_EEI12 (0x1000)
-+#define MCF_EDMA_EEI_EEI13 (0x2000)
-+#define MCF_EDMA_EEI_EEI14 (0x4000)
-+#define MCF_EDMA_EEI_EEI15 (0x8000)
-+
-+/* Bit definitions and macros for SERQ */
-+#define MCF_EDMA_SERQ_SERQ(x) (((x)&0x0F))
-+#define MCF_EDMA_SERQ_SAER (0x40)
-+
-+/* Bit definitions and macros for CERQ */
-+#define MCF_EDMA_CERQ_CERQ(x) (((x)&0x0F))
-+#define MCF_EDMA_CERQ_CAER (0x40)
-+
-+/* Bit definitions and macros for SEEI */
-+#define MCF_EDMA_SEEI_SEEI(x) (((x)&0x0F))
-+#define MCF_EDMA_SEEI_SAEE (0x40)
-+
-+/* Bit definitions and macros for CEEI */
-+#define MCF_EDMA_CEEI_CEEI(x) (((x)&0x0F))
-+#define MCF_EDMA_CEEI_CAEE (0x40)
-+
-+/* Bit definitions and macros for CINT */
-+#define MCF_EDMA_CINT_CINT(x) (((x)&0x0F))
-+#define MCF_EDMA_CINT_CAIR (0x40)
-+
-+/* Bit definitions and macros for CERR */
-+#define MCF_EDMA_CERR_CERR(x) (((x)&0x0F))
-+#define MCF_EDMA_CERR_CAER (0x40)
-+
-+/* Bit definitions and macros for SSRT */
-+#define MCF_EDMA_SSRT_SSRT(x) (((x)&0x0F))
-+#define MCF_EDMA_SSRT_SAST (0x40)
-+
-+/* Bit definitions and macros for CDNE */
-+#define MCF_EDMA_CDNE_CDNE(x) (((x)&0x0F))
-+#define MCF_EDMA_CDNE_CADN (0x40)
-+
-+/* Bit definitions and macros for INTR */
-+#define MCF_EDMA_INTR_INT0 (0x0001)
-+#define MCF_EDMA_INTR_INT1 (0x0002)
-+#define MCF_EDMA_INTR_INT2 (0x0004)
-+#define MCF_EDMA_INTR_INT3 (0x0008)
-+#define MCF_EDMA_INTR_INT4 (0x0010)
-+#define MCF_EDMA_INTR_INT5 (0x0020)
-+#define MCF_EDMA_INTR_INT6 (0x0040)
-+#define MCF_EDMA_INTR_INT7 (0x0080)
-+#define MCF_EDMA_INTR_INT8 (0x0100)
-+#define MCF_EDMA_INTR_INT9 (0x0200)
-+#define MCF_EDMA_INTR_INT10 (0x0400)
-+#define MCF_EDMA_INTR_INT11 (0x0800)
-+#define MCF_EDMA_INTR_INT12 (0x1000)
-+#define MCF_EDMA_INTR_INT13 (0x2000)
-+#define MCF_EDMA_INTR_INT14 (0x4000)
-+#define MCF_EDMA_INTR_INT15 (0x8000)
-+
-+/* Bit definitions and macros for ERR */
-+#define MCF_EDMA_ERR_ERR0 (0x0001)
-+#define MCF_EDMA_ERR_ERR1 (0x0002)
-+#define MCF_EDMA_ERR_ERR2 (0x0004)
-+#define MCF_EDMA_ERR_ERR3 (0x0008)
-+#define MCF_EDMA_ERR_ERR4 (0x0010)
-+#define MCF_EDMA_ERR_ERR5 (0x0020)
-+#define MCF_EDMA_ERR_ERR6 (0x0040)
-+#define MCF_EDMA_ERR_ERR7 (0x0080)
-+#define MCF_EDMA_ERR_ERR8 (0x0100)
-+#define MCF_EDMA_ERR_ERR9 (0x0200)
-+#define MCF_EDMA_ERR_ERR10 (0x0400)
-+#define MCF_EDMA_ERR_ERR11 (0x0800)
-+#define MCF_EDMA_ERR_ERR12 (0x1000)
-+#define MCF_EDMA_ERR_ERR13 (0x2000)
-+#define MCF_EDMA_ERR_ERR14 (0x4000)
-+#define MCF_EDMA_ERR_ERR15 (0x8000)
-+
-+/* Bit definitions and macros for DCHPRI group */
-+#define MCF_EDMA_DCHPRI_CHPRI(x) (((x)&0x0F))
-+#define MCF_EDMA_DCHPRI_ECP (0x80)
-+
-+/* Bit definitions and macros for DCHPRI0 */
-+#define MCF_EDMA_DCHPRI0_CHPRI(x) (((x)&0x0F))
-+#define MCF_EDMA_DCHPRI0_ECP (0x80)
-+
-+/* Bit definitions and macros for DCHPRI1 */
-+#define MCF_EDMA_DCHPRI1_CHPRI(x) (((x)&0x0F))
-+#define MCF_EDMA_DCHPRI1_ECP (0x80)
-+
-+/* Bit definitions and macros for DCHPRI2 */
-+#define MCF_EDMA_DCHPRI2_CHPRI(x) (((x)&0x0F))
-+#define MCF_EDMA_DCHPRI2_ECP (0x80)
-+
-+/* Bit definitions and macros for DCHPRI3 */
-+#define MCF_EDMA_DCHPRI3_CHPRI(x) (((x)&0x0F))
-+#define MCF_EDMA_DCHPRI3_ECP (0x80)
-+
-+/* Bit definitions and macros for DCHPRI4 */
-+#define MCF_EDMA_DCHPRI4_CHPRI(x) (((x)&0x0F))
-+#define MCF_EDMA_DCHPRI4_ECP (0x80)
-+
-+/* Bit definitions and macros for DCHPRI5 */
-+#define MCF_EDMA_DCHPRI5_CHPRI(x) (((x)&0x0F))
-+#define MCF_EDMA_DCHPRI5_ECP (0x80)
-+
-+/* Bit definitions and macros for DCHPRI6 */
-+#define MCF_EDMA_DCHPRI6_CHPRI(x) (((x)&0x0F))
-+#define MCF_EDMA_DCHPRI6_ECP (0x80)
-+
-+/* Bit definitions and macros for DCHPRI7 */
-+#define MCF_EDMA_DCHPRI7_CHPRI(x) (((x)&0x0F))
-+#define MCF_EDMA_DCHPRI7_ECP (0x80)
-+
-+/* Bit definitions and macros for DCHPRI8 */
-+#define MCF_EDMA_DCHPRI8_CHPRI(x) (((x)&0x0F))
-+#define MCF_EDMA_DCHPRI8_ECP (0x80)
-+
-+/* Bit definitions and macros for DCHPRI9 */
-+#define MCF_EDMA_DCHPRI9_CHPRI(x) (((x)&0x0F))
-+#define MCF_EDMA_DCHPRI9_ECP (0x80)
-+
-+/* Bit definitions and macros for DCHPRI10 */
-+#define MCF_EDMA_DCHPRI10_CHPRI(x) (((x)&0x0F))
-+#define MCF_EDMA_DCHPRI10_ECP (0x80)
-+
-+/* Bit definitions and macros for DCHPRI11 */
-+#define MCF_EDMA_DCHPRI11_CHPRI(x) (((x)&0x0F))
-+#define MCF_EDMA_DCHPRI11_ECP (0x80)
-+
-+/* Bit definitions and macros for DCHPRI12 */
-+#define MCF_EDMA_DCHPRI12_CHPRI(x) (((x)&0x0F))
-+#define MCF_EDMA_DCHPRI12_ECP (0x80)
-+
-+/* Bit definitions and macros for DCHPRI13 */
-+#define MCF_EDMA_DCHPRI13_CHPRI(x) (((x)&0x0F))
-+#define MCF_EDMA_DCHPRI13_ECP (0x80)
-+
-+/* Bit definitions and macros for DCHPRI14 */
-+#define MCF_EDMA_DCHPRI14_CHPRI(x) (((x)&0x0F))
-+#define MCF_EDMA_DCHPRI14_ECP (0x80)
-+
-+/* Bit definitions and macros for DCHPRI15 */
-+#define MCF_EDMA_DCHPRI15_CHPRI(x) (((x)&0x0F))
-+#define MCF_EDMA_DCHPRI15_ECP (0x80)
-+
-+/* Bit definitions and macros for TCD_SADDR group */
-+#define MCF_EDMA_TCD_SADDR_SADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD0_SADDR */
-+#define MCF_EDMA_TCD0_SADDR_SADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD_ATTR group */
-+#define MCF_EDMA_TCD_ATTR_DSIZE(x) (((x)&0x0007))
-+#define MCF_EDMA_TCD_ATTR_DMOD(x) (((x)&0x001F)<<3)
-+#define MCF_EDMA_TCD_ATTR_SSIZE(x) (((x)&0x0007)<<8)
-+#define MCF_EDMA_TCD_ATTR_SMOD(x) (((x)&0x001F)<<11)
-+#define MCF_EDMA_TCD_ATTR_SSIZE_8BIT (0x0000)
-+#define MCF_EDMA_TCD_ATTR_SSIZE_16BIT (0x0100)
-+#define MCF_EDMA_TCD_ATTR_SSIZE_32BIT (0x0200)
-+#define MCF_EDMA_TCD_ATTR_SSIZE_16BYTE (0x0400)
-+#define MCF_EDMA_TCD_ATTR_DSIZE_8BIT (0x0000)
-+#define MCF_EDMA_TCD_ATTR_DSIZE_16BIT (0x0001)
-+#define MCF_EDMA_TCD_ATTR_DSIZE_32BIT (0x0002)
-+#define MCF_EDMA_TCD_ATTR_DSIZE_16BYTE (0x0004)
-+
-+/* Bit definitions and macros for TCD0_ATTR */
-+#define MCF_EDMA_TCD0_ATTR_DSIZE(x) (((x)&0x0007))
-+#define MCF_EDMA_TCD0_ATTR_DMOD(x) (((x)&0x001F)<<3)
-+#define MCF_EDMA_TCD0_ATTR_SSIZE(x) (((x)&0x0007)<<8)
-+#define MCF_EDMA_TCD0_ATTR_SMOD(x) (((x)&0x001F)<<11)
-+#define MCF_EDMA_TCD0_ATTR_SSIZE_8BIT (0x0000)
-+#define MCF_EDMA_TCD0_ATTR_SSIZE_16BIT (0x0100)
-+#define MCF_EDMA_TCD0_ATTR_SSIZE_32BIT (0x0200)
-+#define MCF_EDMA_TCD0_ATTR_SSIZE_16BYTE (0x0400)
-+#define MCF_EDMA_TCD0_ATTR_DSIZE_8BIT (0x0000)
-+#define MCF_EDMA_TCD0_ATTR_DSIZE_16BIT (0x0001)
-+#define MCF_EDMA_TCD0_ATTR_DSIZE_32BIT (0x0002)
-+#define MCF_EDMA_TCD0_ATTR_DSIZE_16BYTE (0x0004)
-+
-+/* Bit definitions and macros for TCD_SOFF group */
-+#define MCF_EDMA_TCD_SOFF_SOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD0_SOFF */
-+#define MCF_EDMA_TCD0_SOFF_SOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD_NBYTES group */
-+#define MCF_EDMA_TCD_NBYTES_NBYTES(x) (x)
-+
-+/* Bit definitions and macros for TCD0_NBYTES */
-+#define MCF_EDMA_TCD0_NBYTES_NBYTES(x) (x)
-+
-+/* Bit definitions and macros for TCD_SLAST group */
-+#define MCF_EDMA_TCD_SLAST_SLAST(x) (x)
-+
-+/* Bit definitions and macros for TCD0_SLAST */
-+#define MCF_EDMA_TCD0_SLAST_SLAST(x) (x)
-+
-+/* Bit definitions and macros for TCD_DADDR group */
-+#define MCF_EDMA_TCD_DADDR_DADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD0_DADDR */
-+#define MCF_EDMA_TCD0_DADDR_DADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD_CITER_ELINK group */
-+#define MCF_EDMA_TCD_CITER_ELINK_CITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD_CITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD0_CITER_ELINK */
-+#define MCF_EDMA_TCD0_CITER_ELINK_CITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD0_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD0_CITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD_CITER group */
-+#define MCF_EDMA_TCD_CITER_CITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD_CITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD0_CITER */
-+#define MCF_EDMA_TCD0_CITER_CITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD0_CITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD_DOFF group */
-+#define MCF_EDMA_TCD_DOFF_DOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD0_DOFF */
-+#define MCF_EDMA_TCD0_DOFF_DOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD_DLAST_SGA group */
-+#define MCF_EDMA_TCD_DLAST_SGA_DLAST_SGA(x) (x)
-+
-+/* Bit definitions and macros for TCD0_DLAST_SGA */
-+#define MCF_EDMA_TCD0_DLAST_SGA_DLAST_SGA(x) (x)
-+
-+/* Bit definitions and macros for TCD_BITER_ELINK group */
-+#define MCF_EDMA_TCD_BITER_ELINK_BITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD_BITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD0_BITER_ELINK */
-+#define MCF_EDMA_TCD0_BITER_ELINK_BITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD0_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD0_BITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD_BITER group */
-+#define MCF_EDMA_TCD_BITER_BITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD_BITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD0_BITER */
-+#define MCF_EDMA_TCD0_BITER_BITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD0_BITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD_CSR group */
-+#define MCF_EDMA_TCD_CSR_START (0x0001)
-+#define MCF_EDMA_TCD_CSR_INT_MAJOR (0x0002)
-+#define MCF_EDMA_TCD_CSR_INT_HALF (0x0004)
-+#define MCF_EDMA_TCD_CSR_D_REQ (0x0008)
-+#define MCF_EDMA_TCD_CSR_E_SG (0x0010)
-+#define MCF_EDMA_TCD_CSR_E_LINK (0x0020)
-+#define MCF_EDMA_TCD_CSR_ACTIVE (0x0040)
-+#define MCF_EDMA_TCD_CSR_DONE (0x0080)
-+#define MCF_EDMA_TCD_CSR_LINKCH(x) (((x)&0x003F)<<8)
-+#define MCF_EDMA_TCD_CSR_BWC(x) (((x)&0x0003)<<14)
-+#define MCF_EDMA_TCD_CSR_BWC_NO_STALL (0x0000)
-+#define MCF_EDMA_TCD_CSR_BWC_4CYC_STALL (0x8000)
-+#define MCF_EDMA_TCD_CSR_BWC_8CYC_STALL (0xC000)
-+
-+/* Bit definitions and macros for TCD0_CSR */
-+#define MCF_EDMA_TCD0_CSR_START (0x0001)
-+#define MCF_EDMA_TCD0_CSR_INT_MAJOR (0x0002)
-+#define MCF_EDMA_TCD0_CSR_INT_HALF (0x0004)
-+#define MCF_EDMA_TCD0_CSR_D_REQ (0x0008)
-+#define MCF_EDMA_TCD0_CSR_E_SG (0x0010)
-+#define MCF_EDMA_TCD0_CSR_E_LINK (0x0020)
-+#define MCF_EDMA_TCD0_CSR_ACTIVE (0x0040)
-+#define MCF_EDMA_TCD0_CSR_DONE (0x0080)
-+#define MCF_EDMA_TCD0_CSR_LINKCH(x) (((x)&0x003F)<<8)
-+#define MCF_EDMA_TCD0_CSR_BWC(x) (((x)&0x0003)<<14)
-+#define MCF_EDMA_TCD0_CSR_BWC_NO_STALL (0x0000)
-+#define MCF_EDMA_TCD0_CSR_BWC_4CYC_STALL (0x8000)
-+#define MCF_EDMA_TCD0_CSR_BWC_8CYC_STALL (0xC000)
-+
-+/* Bit definitions and macros for TCD1_SADDR */
-+#define MCF_EDMA_TCD1_SADDR_SADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD1_ATTR */
-+#define MCF_EDMA_TCD1_ATTR_DSIZE(x) (((x)&0x0007))
-+#define MCF_EDMA_TCD1_ATTR_DMOD(x) (((x)&0x001F)<<3)
-+#define MCF_EDMA_TCD1_ATTR_SSIZE(x) (((x)&0x0007)<<8)
-+#define MCF_EDMA_TCD1_ATTR_SMOD(x) (((x)&0x001F)<<11)
-+
-+/* Bit definitions and macros for TCD1_SOFF */
-+#define MCF_EDMA_TCD1_SOFF_SOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD1_NBYTES */
-+#define MCF_EDMA_TCD1_NBYTES_NBYTES(x) (x)
-+
-+/* Bit definitions and macros for TCD1_SLAST */
-+#define MCF_EDMA_TCD1_SLAST_SLAST(x) (x)
-+
-+/* Bit definitions and macros for TCD1_DADDR */
-+#define MCF_EDMA_TCD1_DADDR_DADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD1_CITER_ELINK */
-+#define MCF_EDMA_TCD1_CITER_ELINK_CITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD1_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD1_CITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD1_CITER */
-+#define MCF_EDMA_TCD1_CITER_CITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD1_CITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD1_DOFF */
-+#define MCF_EDMA_TCD1_DOFF_DOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD1_DLAST_SGA */
-+#define MCF_EDMA_TCD1_DLAST_SGA_DLAST_SGA(x) (x)
-+
-+/* Bit definitions and macros for TCD1_BITER */
-+#define MCF_EDMA_TCD1_BITER_BITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD1_BITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD1_BITER_ELINK */
-+#define MCF_EDMA_TCD1_BITER_ELINK_BITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD1_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD1_BITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD1_CSR */
-+#define MCF_EDMA_TCD1_CSR_START (0x0001)
-+#define MCF_EDMA_TCD1_CSR_INT_MAJOR (0x0002)
-+#define MCF_EDMA_TCD1_CSR_INT_HALF (0x0004)
-+#define MCF_EDMA_TCD1_CSR_D_REQ (0x0008)
-+#define MCF_EDMA_TCD1_CSR_E_SG (0x0010)
-+#define MCF_EDMA_TCD1_CSR_E_LINK (0x0020)
-+#define MCF_EDMA_TCD1_CSR_ACTIVE (0x0040)
-+#define MCF_EDMA_TCD1_CSR_DONE (0x0080)
-+#define MCF_EDMA_TCD1_CSR_LINKCH(x) (((x)&0x003F)<<8)
-+#define MCF_EDMA_TCD1_CSR_BWC(x) (((x)&0x0003)<<14)
-+
-+/* Bit definitions and macros for TCD2_SADDR */
-+#define MCF_EDMA_TCD2_SADDR_SADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD2_ATTR */
-+#define MCF_EDMA_TCD2_ATTR_DSIZE(x) (((x)&0x0007))
-+#define MCF_EDMA_TCD2_ATTR_DMOD(x) (((x)&0x001F)<<3)
-+#define MCF_EDMA_TCD2_ATTR_SSIZE(x) (((x)&0x0007)<<8)
-+#define MCF_EDMA_TCD2_ATTR_SMOD(x) (((x)&0x001F)<<11)
-+
-+/* Bit definitions and macros for TCD2_SOFF */
-+#define MCF_EDMA_TCD2_SOFF_SOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD2_NBYTES */
-+#define MCF_EDMA_TCD2_NBYTES_NBYTES(x) (x)
-+
-+/* Bit definitions and macros for TCD2_SLAST */
-+#define MCF_EDMA_TCD2_SLAST_SLAST(x) (x)
-+
-+/* Bit definitions and macros for TCD2_DADDR */
-+#define MCF_EDMA_TCD2_DADDR_DADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD2_CITER */
-+#define MCF_EDMA_TCD2_CITER_CITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD2_CITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD2_CITER_ELINK */
-+#define MCF_EDMA_TCD2_CITER_ELINK_CITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD2_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD2_CITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD2_DOFF */
-+#define MCF_EDMA_TCD2_DOFF_DOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD2_DLAST_SGA */
-+#define MCF_EDMA_TCD2_DLAST_SGA_DLAST_SGA(x) (x)
-+
-+/* Bit definitions and macros for TCD2_BITER_ELINK */
-+#define MCF_EDMA_TCD2_BITER_ELINK_BITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD2_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD2_BITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD2_BITER */
-+#define MCF_EDMA_TCD2_BITER_BITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD2_BITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD2_CSR */
-+#define MCF_EDMA_TCD2_CSR_START (0x0001)
-+#define MCF_EDMA_TCD2_CSR_INT_MAJOR (0x0002)
-+#define MCF_EDMA_TCD2_CSR_INT_HALF (0x0004)
-+#define MCF_EDMA_TCD2_CSR_D_REQ (0x0008)
-+#define MCF_EDMA_TCD2_CSR_E_SG (0x0010)
-+#define MCF_EDMA_TCD2_CSR_E_LINK (0x0020)
-+#define MCF_EDMA_TCD2_CSR_ACTIVE (0x0040)
-+#define MCF_EDMA_TCD2_CSR_DONE (0x0080)
-+#define MCF_EDMA_TCD2_CSR_LINKCH(x) (((x)&0x003F)<<8)
-+#define MCF_EDMA_TCD2_CSR_BWC(x) (((x)&0x0003)<<14)
-+
-+/* Bit definitions and macros for TCD3_SADDR */
-+#define MCF_EDMA_TCD3_SADDR_SADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD3_ATTR */
-+#define MCF_EDMA_TCD3_ATTR_DSIZE(x) (((x)&0x0007))
-+#define MCF_EDMA_TCD3_ATTR_DMOD(x) (((x)&0x001F)<<3)
-+#define MCF_EDMA_TCD3_ATTR_SSIZE(x) (((x)&0x0007)<<8)
-+#define MCF_EDMA_TCD3_ATTR_SMOD(x) (((x)&0x001F)<<11)
-+
-+/* Bit definitions and macros for TCD3_SOFF */
-+#define MCF_EDMA_TCD3_SOFF_SOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD3_NBYTES */
-+#define MCF_EDMA_TCD3_NBYTES_NBYTES(x) (x)
-+
-+/* Bit definitions and macros for TCD3_SLAST */
-+#define MCF_EDMA_TCD3_SLAST_SLAST(x) (x)
-+
-+/* Bit definitions and macros for TCD3_DADDR */
-+#define MCF_EDMA_TCD3_DADDR_DADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD3_CITER */
-+#define MCF_EDMA_TCD3_CITER_CITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD3_CITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD3_CITER_ELINK */
-+#define MCF_EDMA_TCD3_CITER_ELINK_CITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD3_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD3_CITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD3_DOFF */
-+#define MCF_EDMA_TCD3_DOFF_DOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD3_DLAST_SGA */
-+#define MCF_EDMA_TCD3_DLAST_SGA_DLAST_SGA(x) (x)
-+
-+/* Bit definitions and macros for TCD3_BITER_ELINK */
-+#define MCF_EDMA_TCD3_BITER_ELINK_BITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD3_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD3_BITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD3_BITER */
-+#define MCF_EDMA_TCD3_BITER_BITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD3_BITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD3_CSR */
-+#define MCF_EDMA_TCD3_CSR_START (0x0001)
-+#define MCF_EDMA_TCD3_CSR_INT_MAJOR (0x0002)
-+#define MCF_EDMA_TCD3_CSR_INT_HALF (0x0004)
-+#define MCF_EDMA_TCD3_CSR_D_REQ (0x0008)
-+#define MCF_EDMA_TCD3_CSR_E_SG (0x0010)
-+#define MCF_EDMA_TCD3_CSR_E_LINK (0x0020)
-+#define MCF_EDMA_TCD3_CSR_ACTIVE (0x0040)
-+#define MCF_EDMA_TCD3_CSR_DONE (0x0080)
-+#define MCF_EDMA_TCD3_CSR_LINKCH(x) (((x)&0x003F)<<8)
-+#define MCF_EDMA_TCD3_CSR_BWC(x) (((x)&0x0003)<<14)
-+
-+/* Bit definitions and macros for TCD4_SADDR */
-+#define MCF_EDMA_TCD4_SADDR_SADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD4_ATTR */
-+#define MCF_EDMA_TCD4_ATTR_DSIZE(x) (((x)&0x0007))
-+#define MCF_EDMA_TCD4_ATTR_DMOD(x) (((x)&0x001F)<<3)
-+#define MCF_EDMA_TCD4_ATTR_SSIZE(x) (((x)&0x0007)<<8)
-+#define MCF_EDMA_TCD4_ATTR_SMOD(x) (((x)&0x001F)<<11)
-+
-+/* Bit definitions and macros for TCD4_SOFF */
-+#define MCF_EDMA_TCD4_SOFF_SOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD4_NBYTES */
-+#define MCF_EDMA_TCD4_NBYTES_NBYTES(x) (x)
-+
-+/* Bit definitions and macros for TCD4_SLAST */
-+#define MCF_EDMA_TCD4_SLAST_SLAST(x) (x)
-+
-+/* Bit definitions and macros for TCD4_DADDR */
-+#define MCF_EDMA_TCD4_DADDR_DADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD4_CITER */
-+#define MCF_EDMA_TCD4_CITER_CITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD4_CITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD4_CITER_ELINK */
-+#define MCF_EDMA_TCD4_CITER_ELINK_CITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD4_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD4_CITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD4_DOFF */
-+#define MCF_EDMA_TCD4_DOFF_DOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD4_DLAST_SGA */
-+#define MCF_EDMA_TCD4_DLAST_SGA_DLAST_SGA(x) (x)
-+
-+/* Bit definitions and macros for TCD4_BITER */
-+#define MCF_EDMA_TCD4_BITER_BITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD4_BITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD4_BITER_ELINK */
-+#define MCF_EDMA_TCD4_BITER_ELINK_BITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD4_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD4_BITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD4_CSR */
-+#define MCF_EDMA_TCD4_CSR_START (0x0001)
-+#define MCF_EDMA_TCD4_CSR_INT_MAJOR (0x0002)
-+#define MCF_EDMA_TCD4_CSR_INT_HALF (0x0004)
-+#define MCF_EDMA_TCD4_CSR_D_REQ (0x0008)
-+#define MCF_EDMA_TCD4_CSR_E_SG (0x0010)
-+#define MCF_EDMA_TCD4_CSR_E_LINK (0x0020)
-+#define MCF_EDMA_TCD4_CSR_ACTIVE (0x0040)
-+#define MCF_EDMA_TCD4_CSR_DONE (0x0080)
-+#define MCF_EDMA_TCD4_CSR_LINKCH(x) (((x)&0x003F)<<8)
-+#define MCF_EDMA_TCD4_CSR_BWC(x) (((x)&0x0003)<<14)
-+
-+/* Bit definitions and macros for TCD5_SADDR */
-+#define MCF_EDMA_TCD5_SADDR_SADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD5_ATTR */
-+#define MCF_EDMA_TCD5_ATTR_DSIZE(x) (((x)&0x0007))
-+#define MCF_EDMA_TCD5_ATTR_DMOD(x) (((x)&0x001F)<<3)
-+#define MCF_EDMA_TCD5_ATTR_SSIZE(x) (((x)&0x0007)<<8)
-+#define MCF_EDMA_TCD5_ATTR_SMOD(x) (((x)&0x001F)<<11)
-+
-+/* Bit definitions and macros for TCD5_SOFF */
-+#define MCF_EDMA_TCD5_SOFF_SOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD5_NBYTES */
-+#define MCF_EDMA_TCD5_NBYTES_NBYTES(x) (x)
-+
-+/* Bit definitions and macros for TCD5_SLAST */
-+#define MCF_EDMA_TCD5_SLAST_SLAST(x) (x)
-+
-+/* Bit definitions and macros for TCD5_DADDR */
-+#define MCF_EDMA_TCD5_DADDR_DADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD5_CITER */
-+#define MCF_EDMA_TCD5_CITER_CITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD5_CITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD5_CITER_ELINK */
-+#define MCF_EDMA_TCD5_CITER_ELINK_CITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD5_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD5_CITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD5_DOFF */
-+#define MCF_EDMA_TCD5_DOFF_DOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD5_DLAST_SGA */
-+#define MCF_EDMA_TCD5_DLAST_SGA_DLAST_SGA(x) (x)
-+
-+/* Bit definitions and macros for TCD5_BITER_ELINK */
-+#define MCF_EDMA_TCD5_BITER_ELINK_BITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD5_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD5_BITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD5_BITER */
-+#define MCF_EDMA_TCD5_BITER_BITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD5_BITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD5_CSR */
-+#define MCF_EDMA_TCD5_CSR_START (0x0001)
-+#define MCF_EDMA_TCD5_CSR_INT_MAJOR (0x0002)
-+#define MCF_EDMA_TCD5_CSR_INT_HALF (0x0004)
-+#define MCF_EDMA_TCD5_CSR_D_REQ (0x0008)
-+#define MCF_EDMA_TCD5_CSR_E_SG (0x0010)
-+#define MCF_EDMA_TCD5_CSR_E_LINK (0x0020)
-+#define MCF_EDMA_TCD5_CSR_ACTIVE (0x0040)
-+#define MCF_EDMA_TCD5_CSR_DONE (0x0080)
-+#define MCF_EDMA_TCD5_CSR_LINKCH(x) (((x)&0x003F)<<8)
-+#define MCF_EDMA_TCD5_CSR_BWC(x) (((x)&0x0003)<<14)
-+
-+/* Bit definitions and macros for TCD6_SADDR */
-+#define MCF_EDMA_TCD6_SADDR_SADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD6_ATTR */
-+#define MCF_EDMA_TCD6_ATTR_DSIZE(x) (((x)&0x0007))
-+#define MCF_EDMA_TCD6_ATTR_DMOD(x) (((x)&0x001F)<<3)
-+#define MCF_EDMA_TCD6_ATTR_SSIZE(x) (((x)&0x0007)<<8)
-+#define MCF_EDMA_TCD6_ATTR_SMOD(x) (((x)&0x001F)<<11)
-+
-+/* Bit definitions and macros for TCD6_SOFF */
-+#define MCF_EDMA_TCD6_SOFF_SOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD6_NBYTES */
-+#define MCF_EDMA_TCD6_NBYTES_NBYTES(x) (x)
-+
-+/* Bit definitions and macros for TCD6_SLAST */
-+#define MCF_EDMA_TCD6_SLAST_SLAST(x) (x)
-+
-+/* Bit definitions and macros for TCD6_DADDR */
-+#define MCF_EDMA_TCD6_DADDR_DADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD6_CITER */
-+#define MCF_EDMA_TCD6_CITER_CITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD6_CITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD6_CITER_ELINK */
-+#define MCF_EDMA_TCD6_CITER_ELINK_CITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD6_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD6_CITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD6_DOFF */
-+#define MCF_EDMA_TCD6_DOFF_DOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD6_DLAST_SGA */
-+#define MCF_EDMA_TCD6_DLAST_SGA_DLAST_SGA(x) (x)
-+
-+/* Bit definitions and macros for TCD6_BITER_ELINK */
-+#define MCF_EDMA_TCD6_BITER_ELINK_BITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD6_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD6_BITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD6_BITER */
-+#define MCF_EDMA_TCD6_BITER_BITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD6_BITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD6_CSR */
-+#define MCF_EDMA_TCD6_CSR_START (0x0001)
-+#define MCF_EDMA_TCD6_CSR_INT_MAJOR (0x0002)
-+#define MCF_EDMA_TCD6_CSR_INT_HALF (0x0004)
-+#define MCF_EDMA_TCD6_CSR_D_REQ (0x0008)
-+#define MCF_EDMA_TCD6_CSR_E_SG (0x0010)
-+#define MCF_EDMA_TCD6_CSR_E_LINK (0x0020)
-+#define MCF_EDMA_TCD6_CSR_ACTIVE (0x0040)
-+#define MCF_EDMA_TCD6_CSR_DONE (0x0080)
-+#define MCF_EDMA_TCD6_CSR_LINKCH(x) (((x)&0x003F)<<8)
-+#define MCF_EDMA_TCD6_CSR_BWC(x) (((x)&0x0003)<<14)
-+
-+/* Bit definitions and macros for TCD7_SADDR */
-+#define MCF_EDMA_TCD7_SADDR_SADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD7_ATTR */
-+#define MCF_EDMA_TCD7_ATTR_DSIZE(x) (((x)&0x0007))
-+#define MCF_EDMA_TCD7_ATTR_DMOD(x) (((x)&0x001F)<<3)
-+#define MCF_EDMA_TCD7_ATTR_SSIZE(x) (((x)&0x0007)<<8)
-+#define MCF_EDMA_TCD7_ATTR_SMOD(x) (((x)&0x001F)<<11)
-+
-+/* Bit definitions and macros for TCD7_SOFF */
-+#define MCF_EDMA_TCD7_SOFF_SOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD7_NBYTES */
-+#define MCF_EDMA_TCD7_NBYTES_NBYTES(x) (x)
-+
-+/* Bit definitions and macros for TCD7_SLAST */
-+#define MCF_EDMA_TCD7_SLAST_SLAST(x) (x)
-+
-+/* Bit definitions and macros for TCD7_DADDR */
-+#define MCF_EDMA_TCD7_DADDR_DADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD7_CITER */
-+#define MCF_EDMA_TCD7_CITER_CITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD7_CITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD7_CITER_ELINK */
-+#define MCF_EDMA_TCD7_CITER_ELINK_CITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD7_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD7_CITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD7_DOFF */
-+#define MCF_EDMA_TCD7_DOFF_DOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD7_DLAST_SGA */
-+#define MCF_EDMA_TCD7_DLAST_SGA_DLAST_SGA(x) (x)
-+
-+/* Bit definitions and macros for TCD7_BITER_ELINK */
-+#define MCF_EDMA_TCD7_BITER_ELINK_BITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD7_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD7_BITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD7_BITER */
-+#define MCF_EDMA_TCD7_BITER_BITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD7_BITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD7_CSR */
-+#define MCF_EDMA_TCD7_CSR_START (0x0001)
-+#define MCF_EDMA_TCD7_CSR_INT_MAJOR (0x0002)
-+#define MCF_EDMA_TCD7_CSR_INT_HALF (0x0004)
-+#define MCF_EDMA_TCD7_CSR_D_REQ (0x0008)
-+#define MCF_EDMA_TCD7_CSR_E_SG (0x0010)
-+#define MCF_EDMA_TCD7_CSR_E_LINK (0x0020)
-+#define MCF_EDMA_TCD7_CSR_ACTIVE (0x0040)
-+#define MCF_EDMA_TCD7_CSR_DONE (0x0080)
-+#define MCF_EDMA_TCD7_CSR_LINKCH(x) (((x)&0x003F)<<8)
-+#define MCF_EDMA_TCD7_CSR_BWC(x) (((x)&0x0003)<<14)
-+
-+/* Bit definitions and macros for TCD8_SADDR */
-+#define MCF_EDMA_TCD8_SADDR_SADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD8_ATTR */
-+#define MCF_EDMA_TCD8_ATTR_DSIZE(x) (((x)&0x0007))
-+#define MCF_EDMA_TCD8_ATTR_DMOD(x) (((x)&0x001F)<<3)
-+#define MCF_EDMA_TCD8_ATTR_SSIZE(x) (((x)&0x0007)<<8)
-+#define MCF_EDMA_TCD8_ATTR_SMOD(x) (((x)&0x001F)<<11)
-+
-+/* Bit definitions and macros for TCD8_SOFF */
-+#define MCF_EDMA_TCD8_SOFF_SOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD8_NBYTES */
-+#define MCF_EDMA_TCD8_NBYTES_NBYTES(x) (x)
-+
-+/* Bit definitions and macros for TCD8_SLAST */
-+#define MCF_EDMA_TCD8_SLAST_SLAST(x) (x)
-+
-+/* Bit definitions and macros for TCD8_DADDR */
-+#define MCF_EDMA_TCD8_DADDR_DADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD8_CITER */
-+#define MCF_EDMA_TCD8_CITER_CITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD8_CITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD8_CITER_ELINK */
-+#define MCF_EDMA_TCD8_CITER_ELINK_CITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD8_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD8_CITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD8_DOFF */
-+#define MCF_EDMA_TCD8_DOFF_DOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD8_DLAST_SGA */
-+#define MCF_EDMA_TCD8_DLAST_SGA_DLAST_SGA(x) (x)
-+
-+/* Bit definitions and macros for TCD8_BITER_ELINK */
-+#define MCF_EDMA_TCD8_BITER_ELINK_BITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD8_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD8_BITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD8_BITER */
-+#define MCF_EDMA_TCD8_BITER_BITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD8_BITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD8_CSR */
-+#define MCF_EDMA_TCD8_CSR_START (0x0001)
-+#define MCF_EDMA_TCD8_CSR_INT_MAJOR (0x0002)
-+#define MCF_EDMA_TCD8_CSR_INT_HALF (0x0004)
-+#define MCF_EDMA_TCD8_CSR_D_REQ (0x0008)
-+#define MCF_EDMA_TCD8_CSR_E_SG (0x0010)
-+#define MCF_EDMA_TCD8_CSR_E_LINK (0x0020)
-+#define MCF_EDMA_TCD8_CSR_ACTIVE (0x0040)
-+#define MCF_EDMA_TCD8_CSR_DONE (0x0080)
-+#define MCF_EDMA_TCD8_CSR_LINKCH(x) (((x)&0x003F)<<8)
-+#define MCF_EDMA_TCD8_CSR_BWC(x) (((x)&0x0003)<<14)
-+
-+/* Bit definitions and macros for TCD9_SADDR */
-+#define MCF_EDMA_TCD9_SADDR_SADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD9_ATTR */
-+#define MCF_EDMA_TCD9_ATTR_DSIZE(x) (((x)&0x0007))
-+#define MCF_EDMA_TCD9_ATTR_DMOD(x) (((x)&0x001F)<<3)
-+#define MCF_EDMA_TCD9_ATTR_SSIZE(x) (((x)&0x0007)<<8)
-+#define MCF_EDMA_TCD9_ATTR_SMOD(x) (((x)&0x001F)<<11)
-+
-+/* Bit definitions and macros for TCD9_SOFF */
-+#define MCF_EDMA_TCD9_SOFF_SOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD9_NBYTES */
-+#define MCF_EDMA_TCD9_NBYTES_NBYTES(x) (x)
-+
-+/* Bit definitions and macros for TCD9_SLAST */
-+#define MCF_EDMA_TCD9_SLAST_SLAST(x) (x)
-+
-+/* Bit definitions and macros for TCD9_DADDR */
-+#define MCF_EDMA_TCD9_DADDR_DADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD9_CITER_ELINK */
-+#define MCF_EDMA_TCD9_CITER_ELINK_CITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD9_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD9_CITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD9_CITER */
-+#define MCF_EDMA_TCD9_CITER_CITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD9_CITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD9_DOFF */
-+#define MCF_EDMA_TCD9_DOFF_DOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD9_DLAST_SGA */
-+#define MCF_EDMA_TCD9_DLAST_SGA_DLAST_SGA(x) (x)
-+
-+/* Bit definitions and macros for TCD9_BITER_ELINK */
-+#define MCF_EDMA_TCD9_BITER_ELINK_BITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD9_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD9_BITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD9_BITER */
-+#define MCF_EDMA_TCD9_BITER_BITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD9_BITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD9_CSR */
-+#define MCF_EDMA_TCD9_CSR_START (0x0001)
-+#define MCF_EDMA_TCD9_CSR_INT_MAJOR (0x0002)
-+#define MCF_EDMA_TCD9_CSR_INT_HALF (0x0004)
-+#define MCF_EDMA_TCD9_CSR_D_REQ (0x0008)
-+#define MCF_EDMA_TCD9_CSR_E_SG (0x0010)
-+#define MCF_EDMA_TCD9_CSR_E_LINK (0x0020)
-+#define MCF_EDMA_TCD9_CSR_ACTIVE (0x0040)
-+#define MCF_EDMA_TCD9_CSR_DONE (0x0080)
-+#define MCF_EDMA_TCD9_CSR_LINKCH(x) (((x)&0x003F)<<8)
-+#define MCF_EDMA_TCD9_CSR_BWC(x) (((x)&0x0003)<<14)
-+
-+/* Bit definitions and macros for TCD10_SADDR */
-+#define MCF_EDMA_TCD10_SADDR_SADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD10_ATTR */
-+#define MCF_EDMA_TCD10_ATTR_DSIZE(x) (((x)&0x0007))
-+#define MCF_EDMA_TCD10_ATTR_DMOD(x) (((x)&0x001F)<<3)
-+#define MCF_EDMA_TCD10_ATTR_SSIZE(x) (((x)&0x0007)<<8)
-+#define MCF_EDMA_TCD10_ATTR_SMOD(x) (((x)&0x001F)<<11)
-+
-+/* Bit definitions and macros for TCD10_SOFF */
-+#define MCF_EDMA_TCD10_SOFF_SOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD10_NBYTES */
-+#define MCF_EDMA_TCD10_NBYTES_NBYTES(x) (x)
-+
-+/* Bit definitions and macros for TCD10_SLAST */
-+#define MCF_EDMA_TCD10_SLAST_SLAST(x) (x)
-+
-+/* Bit definitions and macros for TCD10_DADDR */
-+#define MCF_EDMA_TCD10_DADDR_DADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD10_CITER_ELINK */
-+#define MCF_EDMA_TCD10_CITER_ELINK_CITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD10_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD10_CITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD10_CITER */
-+#define MCF_EDMA_TCD10_CITER_CITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD10_CITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD10_DOFF */
-+#define MCF_EDMA_TCD10_DOFF_DOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD10_DLAST_SGA */
-+#define MCF_EDMA_TCD10_DLAST_SGA_DLAST_SGA(x) (x)
-+
-+/* Bit definitions and macros for TCD10_BITER */
-+#define MCF_EDMA_TCD10_BITER_BITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD10_BITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD10_BITER_ELINK */
-+#define MCF_EDMA_TCD10_BITER_ELINK_BITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD10_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD10_BITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD10_CSR */
-+#define MCF_EDMA_TCD10_CSR_START (0x0001)
-+#define MCF_EDMA_TCD10_CSR_INT_MAJOR (0x0002)
-+#define MCF_EDMA_TCD10_CSR_INT_HALF (0x0004)
-+#define MCF_EDMA_TCD10_CSR_D_REQ (0x0008)
-+#define MCF_EDMA_TCD10_CSR_E_SG (0x0010)
-+#define MCF_EDMA_TCD10_CSR_E_LINK (0x0020)
-+#define MCF_EDMA_TCD10_CSR_ACTIVE (0x0040)
-+#define MCF_EDMA_TCD10_CSR_DONE (0x0080)
-+#define MCF_EDMA_TCD10_CSR_LINKCH(x) (((x)&0x003F)<<8)
-+#define MCF_EDMA_TCD10_CSR_BWC(x) (((x)&0x0003)<<14)
-+
-+/* Bit definitions and macros for TCD11_SADDR */
-+#define MCF_EDMA_TCD11_SADDR_SADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD11_ATTR */
-+#define MCF_EDMA_TCD11_ATTR_DSIZE(x) (((x)&0x0007))
-+#define MCF_EDMA_TCD11_ATTR_DMOD(x) (((x)&0x001F)<<3)
-+#define MCF_EDMA_TCD11_ATTR_SSIZE(x) (((x)&0x0007)<<8)
-+#define MCF_EDMA_TCD11_ATTR_SMOD(x) (((x)&0x001F)<<11)
-+
-+/* Bit definitions and macros for TCD11_SOFF */
-+#define MCF_EDMA_TCD11_SOFF_SOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD11_NBYTES */
-+#define MCF_EDMA_TCD11_NBYTES_NBYTES(x) (x)
-+
-+/* Bit definitions and macros for TCD11_SLAST */
-+#define MCF_EDMA_TCD11_SLAST_SLAST(x) (x)
-+
-+/* Bit definitions and macros for TCD11_DADDR */
-+#define MCF_EDMA_TCD11_DADDR_DADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD11_CITER */
-+#define MCF_EDMA_TCD11_CITER_CITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD11_CITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD11_CITER_ELINK */
-+#define MCF_EDMA_TCD11_CITER_ELINK_CITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD11_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD11_CITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD11_DOFF */
-+#define MCF_EDMA_TCD11_DOFF_DOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD11_DLAST_SGA */
-+#define MCF_EDMA_TCD11_DLAST_SGA_DLAST_SGA(x) (x)
-+
-+/* Bit definitions and macros for TCD11_BITER */
-+#define MCF_EDMA_TCD11_BITER_BITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD11_BITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD11_BITER_ELINK */
-+#define MCF_EDMA_TCD11_BITER_ELINK_BITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD11_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD11_BITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD11_CSR */
-+#define MCF_EDMA_TCD11_CSR_START (0x0001)
-+#define MCF_EDMA_TCD11_CSR_INT_MAJOR (0x0002)
-+#define MCF_EDMA_TCD11_CSR_INT_HALF (0x0004)
-+#define MCF_EDMA_TCD11_CSR_D_REQ (0x0008)
-+#define MCF_EDMA_TCD11_CSR_E_SG (0x0010)
-+#define MCF_EDMA_TCD11_CSR_E_LINK (0x0020)
-+#define MCF_EDMA_TCD11_CSR_ACTIVE (0x0040)
-+#define MCF_EDMA_TCD11_CSR_DONE (0x0080)
-+#define MCF_EDMA_TCD11_CSR_LINKCH(x) (((x)&0x003F)<<8)
-+#define MCF_EDMA_TCD11_CSR_BWC(x) (((x)&0x0003)<<14)
-+
-+/* Bit definitions and macros for TCD12_SADDR */
-+#define MCF_EDMA_TCD12_SADDR_SADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD12_ATTR */
-+#define MCF_EDMA_TCD12_ATTR_DSIZE(x) (((x)&0x0007))
-+#define MCF_EDMA_TCD12_ATTR_DMOD(x) (((x)&0x001F)<<3)
-+#define MCF_EDMA_TCD12_ATTR_SSIZE(x) (((x)&0x0007)<<8)
-+#define MCF_EDMA_TCD12_ATTR_SMOD(x) (((x)&0x001F)<<11)
-+
-+/* Bit definitions and macros for TCD12_SOFF */
-+#define MCF_EDMA_TCD12_SOFF_SOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD12_NBYTES */
-+#define MCF_EDMA_TCD12_NBYTES_NBYTES(x) (x)
-+
-+/* Bit definitions and macros for TCD12_SLAST */
-+#define MCF_EDMA_TCD12_SLAST_SLAST(x) (x)
-+
-+/* Bit definitions and macros for TCD12_DADDR */
-+#define MCF_EDMA_TCD12_DADDR_DADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD12_CITER */
-+#define MCF_EDMA_TCD12_CITER_CITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD12_CITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD12_CITER_ELINK */
-+#define MCF_EDMA_TCD12_CITER_ELINK_CITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD12_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD12_CITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD12_DOFF */
-+#define MCF_EDMA_TCD12_DOFF_DOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD12_DLAST_SGA */
-+#define MCF_EDMA_TCD12_DLAST_SGA_DLAST_SGA(x) (x)
-+
-+/* Bit definitions and macros for TCD12_BITER */
-+#define MCF_EDMA_TCD12_BITER_BITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD12_BITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD12_BITER_ELINK */
-+#define MCF_EDMA_TCD12_BITER_ELINK_BITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD12_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD12_BITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD12_CSR */
-+#define MCF_EDMA_TCD12_CSR_START (0x0001)
-+#define MCF_EDMA_TCD12_CSR_INT_MAJOR (0x0002)
-+#define MCF_EDMA_TCD12_CSR_INT_HALF (0x0004)
-+#define MCF_EDMA_TCD12_CSR_D_REQ (0x0008)
-+#define MCF_EDMA_TCD12_CSR_E_SG (0x0010)
-+#define MCF_EDMA_TCD12_CSR_E_LINK (0x0020)
-+#define MCF_EDMA_TCD12_CSR_ACTIVE (0x0040)
-+#define MCF_EDMA_TCD12_CSR_DONE (0x0080)
-+#define MCF_EDMA_TCD12_CSR_LINKCH(x) (((x)&0x003F)<<8)
-+#define MCF_EDMA_TCD12_CSR_BWC(x) (((x)&0x0003)<<14)
-+
-+/* Bit definitions and macros for TCD13_SADDR */
-+#define MCF_EDMA_TCD13_SADDR_SADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD13_ATTR */
-+#define MCF_EDMA_TCD13_ATTR_DSIZE(x) (((x)&0x0007))
-+#define MCF_EDMA_TCD13_ATTR_DMOD(x) (((x)&0x001F)<<3)
-+#define MCF_EDMA_TCD13_ATTR_SSIZE(x) (((x)&0x0007)<<8)
-+#define MCF_EDMA_TCD13_ATTR_SMOD(x) (((x)&0x001F)<<11)
-+
-+/* Bit definitions and macros for TCD13_SOFF */
-+#define MCF_EDMA_TCD13_SOFF_SOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD13_NBYTES */
-+#define MCF_EDMA_TCD13_NBYTES_NBYTES(x) (x)
-+
-+/* Bit definitions and macros for TCD13_SLAST */
-+#define MCF_EDMA_TCD13_SLAST_SLAST(x) (x)
-+
-+/* Bit definitions and macros for TCD13_DADDR */
-+#define MCF_EDMA_TCD13_DADDR_DADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD13_CITER_ELINK */
-+#define MCF_EDMA_TCD13_CITER_ELINK_CITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD13_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD13_CITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD13_CITER */
-+#define MCF_EDMA_TCD13_CITER_CITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD13_CITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD13_DOFF */
-+#define MCF_EDMA_TCD13_DOFF_DOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD13_DLAST_SGA */
-+#define MCF_EDMA_TCD13_DLAST_SGA_DLAST_SGA(x) (x)
-+
-+/* Bit definitions and macros for TCD13_BITER_ELINK */
-+#define MCF_EDMA_TCD13_BITER_ELINK_BITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD13_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD13_BITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD13_BITER */
-+#define MCF_EDMA_TCD13_BITER_BITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD13_BITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD13_CSR */
-+#define MCF_EDMA_TCD13_CSR_START (0x0001)
-+#define MCF_EDMA_TCD13_CSR_INT_MAJOR (0x0002)
-+#define MCF_EDMA_TCD13_CSR_INT_HALF (0x0004)
-+#define MCF_EDMA_TCD13_CSR_D_REQ (0x0008)
-+#define MCF_EDMA_TCD13_CSR_E_SG (0x0010)
-+#define MCF_EDMA_TCD13_CSR_E_LINK (0x0020)
-+#define MCF_EDMA_TCD13_CSR_ACTIVE (0x0040)
-+#define MCF_EDMA_TCD13_CSR_DONE (0x0080)
-+#define MCF_EDMA_TCD13_CSR_LINKCH(x) (((x)&0x003F)<<8)
-+#define MCF_EDMA_TCD13_CSR_BWC(x) (((x)&0x0003)<<14)
-+
-+/* Bit definitions and macros for TCD14_SADDR */
-+#define MCF_EDMA_TCD14_SADDR_SADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD14_ATTR */
-+#define MCF_EDMA_TCD14_ATTR_DSIZE(x) (((x)&0x0007))
-+#define MCF_EDMA_TCD14_ATTR_DMOD(x) (((x)&0x001F)<<3)
-+#define MCF_EDMA_TCD14_ATTR_SSIZE(x) (((x)&0x0007)<<8)
-+#define MCF_EDMA_TCD14_ATTR_SMOD(x) (((x)&0x001F)<<11)
-+
-+/* Bit definitions and macros for TCD14_SOFF */
-+#define MCF_EDMA_TCD14_SOFF_SOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD14_NBYTES */
-+#define MCF_EDMA_TCD14_NBYTES_NBYTES(x) (x)
-+
-+/* Bit definitions and macros for TCD14_SLAST */
-+#define MCF_EDMA_TCD14_SLAST_SLAST(x) (x)
-+
-+/* Bit definitions and macros for TCD14_DADDR */
-+#define MCF_EDMA_TCD14_DADDR_DADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD14_CITER */
-+#define MCF_EDMA_TCD14_CITER_CITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD14_CITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD14_CITER_ELINK */
-+#define MCF_EDMA_TCD14_CITER_ELINK_CITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD14_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD14_CITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD14_DOFF */
-+#define MCF_EDMA_TCD14_DOFF_DOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD14_DLAST_SGA */
-+#define MCF_EDMA_TCD14_DLAST_SGA_DLAST_SGA(x) (x)
-+
-+/* Bit definitions and macros for TCD14_BITER_ELINK */
-+#define MCF_EDMA_TCD14_BITER_ELINK_BITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD14_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD14_BITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD14_BITER */
-+#define MCF_EDMA_TCD14_BITER_BITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD14_BITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD14_CSR */
-+#define MCF_EDMA_TCD14_CSR_START (0x0001)
-+#define MCF_EDMA_TCD14_CSR_INT_MAJOR (0x0002)
-+#define MCF_EDMA_TCD14_CSR_INT_HALF (0x0004)
-+#define MCF_EDMA_TCD14_CSR_D_REQ (0x0008)
-+#define MCF_EDMA_TCD14_CSR_E_SG (0x0010)
-+#define MCF_EDMA_TCD14_CSR_E_LINK (0x0020)
-+#define MCF_EDMA_TCD14_CSR_ACTIVE (0x0040)
-+#define MCF_EDMA_TCD14_CSR_DONE (0x0080)
-+#define MCF_EDMA_TCD14_CSR_LINKCH(x) (((x)&0x003F)<<8)
-+#define MCF_EDMA_TCD14_CSR_BWC(x) (((x)&0x0003)<<14)
-+
-+/* Bit definitions and macros for TCD15_SADDR */
-+#define MCF_EDMA_TCD15_SADDR_SADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD15_ATTR */
-+#define MCF_EDMA_TCD15_ATTR_DSIZE(x) (((x)&0x0007))
-+#define MCF_EDMA_TCD15_ATTR_DMOD(x) (((x)&0x001F)<<3)
-+#define MCF_EDMA_TCD15_ATTR_SSIZE(x) (((x)&0x0007)<<8)
-+#define MCF_EDMA_TCD15_ATTR_SMOD(x) (((x)&0x001F)<<11)
-+
-+/* Bit definitions and macros for TCD15_SOFF */
-+#define MCF_EDMA_TCD15_SOFF_SOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD15_NBYTES */
-+#define MCF_EDMA_TCD15_NBYTES_NBYTES(x) (x)
-+
-+/* Bit definitions and macros for TCD15_SLAST */
-+#define MCF_EDMA_TCD15_SLAST_SLAST(x) (x)
-+
-+/* Bit definitions and macros for TCD15_DADDR */
-+#define MCF_EDMA_TCD15_DADDR_DADDR(x) (x)
-+
-+/* Bit definitions and macros for TCD15_CITER_ELINK */
-+#define MCF_EDMA_TCD15_CITER_ELINK_CITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD15_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD15_CITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD15_CITER */
-+#define MCF_EDMA_TCD15_CITER_CITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD15_CITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD15_DOFF */
-+#define MCF_EDMA_TCD15_DOFF_DOFF(x) (x)
-+
-+/* Bit definitions and macros for TCD15_DLAST_SGA */
-+#define MCF_EDMA_TCD15_DLAST_SGA_DLAST_SGA(x) (x)
-+
-+/* Bit definitions and macros for TCD15_BITER */
-+#define MCF_EDMA_TCD15_BITER_BITER(x) (((x)&0x7FFF))
-+#define MCF_EDMA_TCD15_BITER_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD15_BITER_ELINK */
-+#define MCF_EDMA_TCD15_BITER_ELINK_BITER(x) (((x)&0x01FF))
-+#define MCF_EDMA_TCD15_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
-+#define MCF_EDMA_TCD15_BITER_ELINK_E_LINK (0x8000)
-+
-+/* Bit definitions and macros for TCD15_CSR */
-+#define MCF_EDMA_TCD15_CSR_START (0x0001)
-+#define MCF_EDMA_TCD15_CSR_INT_MAJOR (0x0002)
-+#define MCF_EDMA_TCD15_CSR_INT_HALF (0x0004)
-+#define MCF_EDMA_TCD15_CSR_D_REQ (0x0008)
-+#define MCF_EDMA_TCD15_CSR_E_SG (0x0010)
-+#define MCF_EDMA_TCD15_CSR_E_LINK (0x0020)
-+#define MCF_EDMA_TCD15_CSR_ACTIVE (0x0040)
-+#define MCF_EDMA_TCD15_CSR_DONE (0x0080)
-+#define MCF_EDMA_TCD15_CSR_LINKCH(x) (((x)&0x003F)<<8)
-+#define MCF_EDMA_TCD15_CSR_BWC(x) (((x)&0x0003)<<14)
-+
-+/********************************************************************/
-+
-+#endif /* __MCF5445X_EDMA_H__ */
---- /dev/null
-+++ b/include/asm-m68k/mcf5445x_eport.h
-@@ -0,0 +1,117 @@
-+/*
-+ * Kurt Mahan kmahan@freescale.com
-+ *
-+ * Copyright Freescale Semiconductor, Inc. 2007
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+
-+#ifndef __MCF5445X_EPORT_H__
-+#define __MCF5445X_EPORT_H__
-+
-+/*********************************************************************
-+*
-+* Edge Port Module (EPORT)
-+*
-+*********************************************************************/
-+
-+/* Register read/write macros */
-+#define MCF_EPORT_EPPAR MCF_REG16(0xFC094000)
-+#define MCF_EPORT_EPDDR MCF_REG08(0xFC094002)
-+#define MCF_EPORT_EPIER MCF_REG08(0xFC094003)
-+#define MCF_EPORT_EPDR MCF_REG08(0xFC094004)
-+#define MCF_EPORT_EPPDR MCF_REG08(0xFC094005)
-+#define MCF_EPORT_EPFR MCF_REG08(0xFC094006)
-+
-+/* Bit definitions and macros for EPPAR */
-+#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
-+#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
-+#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
-+#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
-+#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
-+#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
-+#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
-+#define MCF_EPORT_EPPAR_LEVEL (0)
-+#define MCF_EPORT_EPPAR_RISING (1)
-+#define MCF_EPORT_EPPAR_FALLING (2)
-+#define MCF_EPORT_EPPAR_BOTH (3)
-+#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000)
-+#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
-+#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
-+#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
-+#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000)
-+#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
-+#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
-+#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
-+#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000)
-+#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400)
-+#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800)
-+#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00)
-+#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000)
-+#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100)
-+#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200)
-+#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300)
-+#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000)
-+#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040)
-+#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080)
-+#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0)
-+#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000)
-+#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010)
-+#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020)
-+#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030)
-+#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000)
-+#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004)
-+#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008)
-+#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C)
-+
-+/* Bit definitions and macros for EPDDR */
-+#define MCF_EPORT_EPDDR_EPDD1 (0x02)
-+#define MCF_EPORT_EPDDR_EPDD2 (0x04)
-+#define MCF_EPORT_EPDDR_EPDD3 (0x08)
-+#define MCF_EPORT_EPDDR_EPDD4 (0x10)
-+#define MCF_EPORT_EPDDR_EPDD5 (0x20)
-+#define MCF_EPORT_EPDDR_EPDD6 (0x40)
-+#define MCF_EPORT_EPDDR_EPDD7 (0x80)
-+
-+/* Bit definitions and macros for EPIER */
-+#define MCF_EPORT_EPIER_EPIE1 (0x02)
-+#define MCF_EPORT_EPIER_EPIE2 (0x04)
-+#define MCF_EPORT_EPIER_EPIE3 (0x08)
-+#define MCF_EPORT_EPIER_EPIE4 (0x10)
-+#define MCF_EPORT_EPIER_EPIE5 (0x20)
-+#define MCF_EPORT_EPIER_EPIE6 (0x40)
-+#define MCF_EPORT_EPIER_EPIE7 (0x80)
-+
-+/* Bit definitions and macros for EPDR */
-+#define MCF_EPORT_EPDR_EPD1 (0x02)
-+#define MCF_EPORT_EPDR_EPD2 (0x04)
-+#define MCF_EPORT_EPDR_EPD3 (0x08)
-+#define MCF_EPORT_EPDR_EPD4 (0x10)
-+#define MCF_EPORT_EPDR_EPD5 (0x20)
-+#define MCF_EPORT_EPDR_EPD6 (0x40)
-+#define MCF_EPORT_EPDR_EPD7 (0x80)
-+
-+/* Bit definitions and macros for EPPDR */
-+#define MCF_EPORT_EPPDR_EPPD1 (0x02)
-+#define MCF_EPORT_EPPDR_EPPD2 (0x04)
-+#define MCF_EPORT_EPPDR_EPPD3 (0x08)
-+#define MCF_EPORT_EPPDR_EPPD4 (0x10)
-+#define MCF_EPORT_EPPDR_EPPD5 (0x20)
-+#define MCF_EPORT_EPPDR_EPPD6 (0x40)
-+#define MCF_EPORT_EPPDR_EPPD7 (0x80)
-+
-+/* Bit definitions and macros for EPFR */
-+#define MCF_EPORT_EPFR_EPF1 (0x02)
-+#define MCF_EPORT_EPFR_EPF2 (0x04)
-+#define MCF_EPORT_EPFR_EPF3 (0x08)
-+#define MCF_EPORT_EPFR_EPF4 (0x10)
-+#define MCF_EPORT_EPFR_EPF5 (0x20)
-+#define MCF_EPORT_EPFR_EPF6 (0x40)
-+#define MCF_EPORT_EPFR_EPF7 (0x80)
-+
-+/********************************************************************/
-+
-+#endif /* __MCF5445X_EPORT_H__ */
---- /dev/null
-+++ b/include/asm-m68k/mcf5445x_fbcs.h
-@@ -0,0 +1,182 @@
-+/*
-+ * Matt Waddel Matt.Waddel@freescale.com
-+ *
-+ * Copyright Freescale Semiconductor, Inc. 2007
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+
-+#ifndef __MCF5445X_FBCS_H__
-+#define __MCF5445X_FBCS_H__
-+
-+/*********************************************************************
-+*
-+* FlexBus Chip Selects (FBCS)
-+*
-+*********************************************************************/
-+
-+/* Register read/write macros */
-+#define MCF_FBCS_CSAR0 MCF_REG32(0xFC008000) /* Chip-select Addr Register */
-+#define MCF_FBCS_CSMR0 MCF_REG32(0xFC008004) /* Chip-select Mask Register */
-+#define MCF_FBCS_CSCR0 MCF_REG32(0xFC008008) /* Chip-select Cntl Register */
-+#define MCF_FBCS_CSAR1 MCF_REG32(0xFC00800C) /* Chip-select Addr Register */
-+#define MCF_FBCS_CSMR1 MCF_REG32(0xFC008010) /* Chip-select Mask Register */
-+#define MCF_FBCS_CSCR1 MCF_REG32(0xFC008014) /* Chip-select Cntl Register */
-+#define MCF_FBCS_CSAR2 MCF_REG32(0xFC008018) /* Chip-select Addr Register */
-+#define MCF_FBCS_CSMR2 MCF_REG32(0xFC00801C) /* Chip-select Mask Register */
-+#define MCF_FBCS_CSCR2 MCF_REG32(0xFC008020) /* Chip-select Cntl Register */
-+#define MCF_FBCS_CSAR3 MCF_REG32(0xFC008024) /* Chip-select Addr Register */
-+#define MCF_FBCS_CSMR3 MCF_REG32(0xFC008028) /* Chip-select Mask Register */
-+#define MCF_FBCS_CSCR3 MCF_REG32(0xFC00802C) /* Chip-select Cntl Register */
-+
-+/* Parameterized register read/write macros for multiple registers */
-+#define MCF_FBCS_CSAR(x) MCF_REG32(0xFC008000+((x)*0x00C)) /* Chip-select Addr Register */
-+#define MCF_FBCS_CSMR(x) MCF_REG32(0xFC008004+((x)*0x00C)) /* Chip-select Mask Register */
-+#define MCF_FBCS_CSCR(x) MCF_REG32(0xFC008008+((x)*0x00C)) /* Chip-select Cntl Register */
-+
-+/* Bit definitions and macros for CSAR group */
-+#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
-+
-+/* Bit definitions and macros for CSAR0 */
-+#define MCF_FBCS_CSAR0_BA(x) ((x)&0xFFFF0000)
-+
-+/* Bit definitions and macros for CSMR group */
-+#define MCF_FBCS_CSMR_V (0x00000001) /* Valid bit */
-+#define MCF_FBCS_CSMR_WP (0x00000100) /* Write protect */
-+#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) /* Base addr mask */
-+#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
-+#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
-+#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
-+#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
-+#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
-+#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000)
-+#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000)
-+#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000)
-+#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000)
-+#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000)
-+#define MCF_FBCS_CSMR_BAM_8M (0x007F0000)
-+#define MCF_FBCS_CSMR_BAM_4M (0x003F0000)
-+#define MCF_FBCS_CSMR_BAM_2M (0x001F0000)
-+#define MCF_FBCS_CSMR_BAM_1M (0x000F0000)
-+#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000)
-+#define MCF_FBCS_CSMR_BAM_512K (0x00070000)
-+#define MCF_FBCS_CSMR_BAM_256K (0x00030000)
-+#define MCF_FBCS_CSMR_BAM_128K (0x00010000)
-+#define MCF_FBCS_CSMR_BAM_64K (0x00000000)
-+
-+/* Bit definitions and macros for CSMR0 */
-+#define MCF_FBCS_CSMR0_V (0x00000001) /* Valid bit */
-+#define MCF_FBCS_CSMR0_WP (0x00000100) /* Write protect */
-+#define MCF_FBCS_CSMR0_BAM(x) (((x)&0x0000FFFF)<<16) /* Base addr mask */
-+#define MCF_FBCS_CSMR0_BAM_4G (0xFFFF0000)
-+#define MCF_FBCS_CSMR0_BAM_2G (0x7FFF0000)
-+#define MCF_FBCS_CSMR0_BAM_1G (0x3FFF0000)
-+#define MCF_FBCS_CSMR0_BAM_1024M (0x3FFF0000)
-+#define MCF_FBCS_CSMR0_BAM_512M (0x1FFF0000)
-+#define MCF_FBCS_CSMR0_BAM_256M (0x0FFF0000)
-+#define MCF_FBCS_CSMR0_BAM_128M (0x07FF0000)
-+#define MCF_FBCS_CSMR0_BAM_64M (0x03FF0000)
-+#define MCF_FBCS_CSMR0_BAM_32M (0x01FF0000)
-+#define MCF_FBCS_CSMR0_BAM_16M (0x00FF0000)
-+#define MCF_FBCS_CSMR0_BAM_8M (0x007F0000)
-+#define MCF_FBCS_CSMR0_BAM_4M (0x003F0000)
-+#define MCF_FBCS_CSMR0_BAM_2M (0x001F0000)
-+#define MCF_FBCS_CSMR0_BAM_1M (0x000F0000)
-+#define MCF_FBCS_CSMR0_BAM_1024K (0x000F0000)
-+#define MCF_FBCS_CSMR0_BAM_512K (0x00070000)
-+#define MCF_FBCS_CSMR0_BAM_256K (0x00030000)
-+#define MCF_FBCS_CSMR0_BAM_128K (0x00010000)
-+#define MCF_FBCS_CSMR0_BAM_64K (0x00000000)
-+
-+/* Bit definitions and macros for CSCR group */
-+#define MCF_FBCS_CSCR_BSTW (0x00000008) /* Burst-write enable */
-+#define MCF_FBCS_CSCR_BSTR (0x00000010) /* Burst-read enable */
-+#define MCF_FBCS_CSCR_BEM (0x00000020) /* Byte-enable mode */
-+#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) /* Port size */
-+#define MCF_FBCS_CSCR_AA (0x00000100) /* Auto-acknowledge */
-+#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
-+#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */
-+#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */
-+#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
-+#define MCF_FBCS_CSCR_SWSEN (0x00800000) /* Secondary wait state enable */
-+#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */
-+#define MCF_FBCS_CSCR_PS_8 (0x00000040)
-+#define MCF_FBCS_CSCR_PS_16 (0x00000080)
-+#define MCF_FBCS_CSCR_PS_32 (0x00000000)
-+
-+/* Bit definitions and macros for CSCR0 */
-+#define MCF_FBCS_CSCR0_BSTW (0x00000008) /* Burst-write enable */
-+#define MCF_FBCS_CSCR0_BSTR (0x00000010) /* Burst-read enable */
-+#define MCF_FBCS_CSCR0_BEM (0x00000020) /* Byte-enable mode */
-+#define MCF_FBCS_CSCR0_PS(x) (((x)&0x00000003)<<6) /* Port size */
-+#define MCF_FBCS_CSCR0_AA (0x00000100) /* Auto-acknowledge */
-+#define MCF_FBCS_CSCR0_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
-+#define MCF_FBCS_CSCR0_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */
-+#define MCF_FBCS_CSCR0_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */
-+#define MCF_FBCS_CSCR0_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
-+#define MCF_FBCS_CSCR0_SWSEN (0x00800000) /* Secondary wait state enable */
-+#define MCF_FBCS_CSCR0_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */
-+#define MCF_FBCS_CSCR0_PS_8 (0x00000040)
-+#define MCF_FBCS_CSCR0_PS_16 (0x00000080)
-+#define MCF_FBCS_CSCR0_PS_32 (0x00000000)
-+
-+/* Bit definitions and macros for CSMR1 */
-+#define MCF_FBCS_CSMR1_V (0x00000001) /* Valid bit */
-+#define MCF_FBCS_CSMR1_WP (0x00000100) /* Write protect */
-+#define MCF_FBCS_CSMR1_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
-+
-+/* Bit definitions and macros for CSCR1 */
-+#define MCF_FBCS_CSCR1_BSTW (0x00000008) /* Burst-write enable */
-+#define MCF_FBCS_CSCR1_BSTR (0x00000010) /* Burst-read enable */
-+#define MCF_FBCS_CSCR1_BEM (0x00000020) /* Byte-enable mode */
-+#define MCF_FBCS_CSCR1_PS(x) (((x)&0x00000003)<<6) /* Port size */
-+#define MCF_FBCS_CSCR1_AA (0x00000100) /* Auto-acknowledge */
-+#define MCF_FBCS_CSCR1_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
-+#define MCF_FBCS_CSCR1_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */
-+#define MCF_FBCS_CSCR1_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */
-+#define MCF_FBCS_CSCR1_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
-+#define MCF_FBCS_CSCR1_SWSEN (0x00800000) /* Secondary wait state enable */
-+#define MCF_FBCS_CSCR1_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */
-+
-+/* Bit definitions and macros for CSMR2 */
-+#define MCF_FBCS_CSMR2_V (0x00000001) /* Valid bit */
-+#define MCF_FBCS_CSMR2_WP (0x00000100) /* Write protect */
-+#define MCF_FBCS_CSMR2_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
-+
-+/* Bit definitions and macros for CSCR2 */
-+#define MCF_FBCS_CSCR2_BSTW (0x00000008) /* Burst-write enable */
-+#define MCF_FBCS_CSCR2_BSTR (0x00000010) /* Burst-read enable */
-+#define MCF_FBCS_CSCR2_BEM (0x00000020) /* Byte-enable mode */
-+#define MCF_FBCS_CSCR2_PS(x) (((x)&0x00000003)<<6) /* Port size */
-+#define MCF_FBCS_CSCR2_AA (0x00000100) /* Auto-acknowledge */
-+#define MCF_FBCS_CSCR2_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
-+#define MCF_FBCS_CSCR2_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */
-+#define MCF_FBCS_CSCR2_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */
-+#define MCF_FBCS_CSCR2_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
-+#define MCF_FBCS_CSCR2_SWSEN (0x00800000) /* Secondary wait state enable */
-+#define MCF_FBCS_CSCR2_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */
-+
-+/* Bit definitions and macros for CSMR3 */
-+#define MCF_FBCS_CSMR3_V (0x00000001) /* Valid bit */
-+#define MCF_FBCS_CSMR3_WP (0x00000100) /* Write protect */
-+#define MCF_FBCS_CSMR3_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
-+
-+/* Bit definitions and macros for CSCR3 */
-+#define MCF_FBCS_CSCR3_BSTW (0x00000008) /* Burst-write enable */
-+#define MCF_FBCS_CSCR3_BSTR (0x00000010) /* Burst-read enable */
-+#define MCF_FBCS_CSCR3_BEM (0x00000020) /* Byte-enable mode */
-+#define MCF_FBCS_CSCR3_PS(x) (((x)&0x00000003)<<6) /* Port size */
-+#define MCF_FBCS_CSCR3_AA (0x00000100) /* Auto-acknowledge */
-+#define MCF_FBCS_CSCR3_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
-+#define MCF_FBCS_CSCR3_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */
-+#define MCF_FBCS_CSCR3_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */
-+#define MCF_FBCS_CSCR3_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
-+#define MCF_FBCS_CSCR3_SWSEN (0x00800000) /* Secondary wait state enable */
-+#define MCF_FBCS_CSCR3_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */
-+
-+/********************************************************************/
-+
-+#endif /* __MCF5445X_FBCS_H__ */
---- /dev/null
-+++ b/include/asm-m68k/mcf5445x_gpio.h
-@@ -0,0 +1,1257 @@
-+/*
-+ * Matt Waddel Matt.Waddel@freescale.com
-+ *
-+ * Copyright Freescale Semiconductor, Inc. 2007
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+
-+#ifndef __MCF5445X_GPIO_H__
-+#define __MCF5445X_GPIO_H__
-+
-+/*********************************************************************
-+*
-+* General Purpose I/O Module (GPIO)
-+*
-+*********************************************************************/
-+
-+/* Register read/write macros */
-+#define MCF_GPIO_PODR_FEC0H MCF_REG08(0xFC0A4000) /* FEC0 High Port Output Data Register */
-+#define MCF_GPIO_PODR_FEC0L MCF_REG08(0xFC0A4001) /* FEC0 Low Port Output Data Register */
-+#define MCF_GPIO_PODR_SSI MCF_REG08(0xFC0A4002) /* SSI Port Output Data Register */
-+#define MCF_GPIO_PODR_FBCTL MCF_REG08(0xFC0A4003) /* Flexbus Control Port Output Data Register */
-+#define MCF_GPIO_PODR_BE MCF_REG08(0xFC0A4004) /* Flexbus Byte Enable Port Output Data Register */
-+#define MCF_GPIO_PODR_CS MCF_REG08(0xFC0A4005) /* Flexbus Chip-Select Port Output Data Register */
-+#define MCF_GPIO_PODR_DMA MCF_REG08(0xFC0A4006) /* DMA Port Output Data Register */
-+#define MCF_GPIO_PODR_FECI2C MCF_REG08(0xFC0A4007) /* FEC1 / I2C Port Output Data Register */
-+#define MCF_GPIO_PODR_UART MCF_REG08(0xFC0A4009) /* UART Port Output Data Register */
-+#define MCF_GPIO_PODR_DSPI MCF_REG08(0xFC0A400A) /* DSPI Port Output Data Register */
-+#define MCF_GPIO_PODR_TIMER MCF_REG08(0xFC0A400B) /* Timer Port Output Data Register */
-+#define MCF_GPIO_PODR_PCI MCF_REG08(0xFC0A400C) /* PCI Port Output Data Register */
-+#define MCF_GPIO_PODR_USB MCF_REG08(0xFC0A400D) /* USB Port Output Data Register */
-+#define MCF_GPIO_PODR_ATAH MCF_REG08(0xFC0A400E) /* ATA High Port Output Data Register */
-+#define MCF_GPIO_PODR_ATAL MCF_REG08(0xFC0A400F) /* ATA Low Port Output Data Register */
-+#define MCF_GPIO_PODR_FEC1H MCF_REG08(0xFC0A4010) /* FEC1 High Port Output Data Register */
-+#define MCF_GPIO_PODR_FEC1L MCF_REG08(0xFC0A4011) /* FEC1 Low Port Output Data Register */
-+#define MCF_GPIO_PODR_FBADH MCF_REG08(0xFC0A4014) /* Flexbus AD High Port Output Data Register */
-+#define MCF_GPIO_PODR_FBADMH MCF_REG08(0xFC0A4015) /* Flexbus AD Med-High Port Output Data Register */
-+#define MCF_GPIO_PODR_FBADML MCF_REG08(0xFC0A4016) /* Flexbus AD Med-Low Port Output Data Register */
-+#define MCF_GPIO_PODR_FBADL MCF_REG08(0xFC0A4017) /* Flexbus AD Low Port Output Data Register */
-+#define MCF_GPIO_PDDR_FEC0H MCF_REG08(0xFC0A4018) /* FEC0 High Port Data Direction Register */
-+#define MCF_GPIO_PDDR_FEC0L MCF_REG08(0xFC0A4019) /* FEC0 Low Port Data Direction Register */
-+#define MCF_GPIO_PDDR_SSI MCF_REG08(0xFC0A401A) /* SSI Port Data Direction Register */
-+#define MCF_GPIO_PDDR_FBCTL MCF_REG08(0xFC0A401B) /* Flexbus Control Port Data Direction Register */
-+#define MCF_GPIO_PDDR_BE MCF_REG08(0xFC0A401C) /* Flexbus Byte Enable Port Data Direction Register */
-+#define MCF_GPIO_PDDR_CS MCF_REG08(0xFC0A401D) /* Flexbus Chip-Select Port Data Direction Register */
-+#define MCF_GPIO_PDDR_DMA MCF_REG08(0xFC0A401E) /* DMA Port Data Direction Register */
-+#define MCF_GPIO_PDDR_FECI2C MCF_REG08(0xFC0A401F) /* FEC1 / I2C Port Data Direction Register */
-+#define MCF_GPIO_PDDR_UART MCF_REG08(0xFC0A4021) /* UART Port Data Direction Register */
-+#define MCF_GPIO_PDDR_DSPI MCF_REG08(0xFC0A4022) /* DSPI Port Data Direction Register */
-+#define MCF_GPIO_PDDR_TIMER MCF_REG08(0xFC0A4023) /* Timer Port Data Direction Register */
-+#define MCF_GPIO_PDDR_PCI MCF_REG08(0xFC0A4024) /* PCI Port Data Direction Register */
-+#define MCF_GPIO_PDDR_USB MCF_REG08(0xFC0A4025) /* USB Port Data Direction Register */
-+#define MCF_GPIO_PDDR_ATAH MCF_REG08(0xFC0A4026) /* ATA High Port Data Direction Register */
-+#define MCF_GPIO_PDDR_ATAL MCF_REG08(0xFC0A4027) /* ATA Low Port Data Direction Register */
-+#define MCF_GPIO_PDDR_FEC1H MCF_REG08(0xFC0A4028) /* FEC1 High Port Data Direction Register */
-+#define MCF_GPIO_PDDR_FEC1L MCF_REG08(0xFC0A4029) /* FEC1 Low Port Data Direction Register */
-+#define MCF_GPIO_PDDR_FBADH MCF_REG08(0xFC0A402C) /* Flexbus AD High Port Data Direction Register */
-+#define MCF_GPIO_PDDR_FBADMH MCF_REG08(0xFC0A402D) /* Flexbus AD Med-High Port Data Direction Register */
-+#define MCF_GPIO_PDDR_FBADML MCF_REG08(0xFC0A402E) /* Flexbus AD Med-Low Port Data Direction Register */
-+#define MCF_GPIO_PDDR_FBADL MCF_REG08(0xFC0A402F) /* Flexbus AD Low Port Data Direction Register */
-+#define MCF_GPIO_PPDSDR_FEC0H MCF_REG08(0xFC0A4030) /* FEC0 High Port Pin Data/Set Data Register */
-+#define MCF_GPIO_PPDSDR_FEC0L MCF_REG08(0xFC0A4031) /* FEC0 Low Port Clear Output Data Register */
-+#define MCF_GPIO_PPDSDR_SSI MCF_REG08(0xFC0A4032) /* SSI Port Pin Data/Set Data Register */
-+#define MCF_GPIO_PPDSDR_FBCTL MCF_REG08(0xFC0A4033) /* Flexbus Control Port Pin Data/Set Data Register */
-+#define MCF_GPIO_PPDSDR_BE MCF_REG08(0xFC0A4034) /* Flexbus Byte Enable Port Pin Data/Set Data Register */
-+#define MCF_GPIO_PPDSDR_CS MCF_REG08(0xFC0A4035) /* Flexbus Chip-Select Port Pin Data/Set Data Register */
-+#define MCF_GPIO_PPDSDR_DMA MCF_REG08(0xFC0A4036) /* DMA Port Pin Data/Set Data Register */
-+#define MCF_GPIO_PPDSDR_FECI2C MCF_REG08(0xFC0A4037) /* FEC1 / I2C Port Pin Data/Set Data Register */
-+#define MCF_GPIO_PPDSDR_UART MCF_REG08(0xFC0A4039) /* UART Port Pin Data/Set Data Register */
-+#define MCF_GPIO_PPDSDR_DSPI MCF_REG08(0xFC0A403A) /* DSPI Port Pin Data/Set Data Register */
-+#define MCF_GPIO_PPDSDR_TIMER MCF_REG08(0xFC0A403B) /* FTimer Port Pin Data/Set Data Register */
-+#define MCF_GPIO_PPDSDR_PCI MCF_REG08(0xFC0A403C) /* PCI Port Pin Data/Set Data Register */
-+#define MCF_GPIO_PPDSDR_USB MCF_REG08(0xFC0A403D) /* USB Port Pin Data/Set Data Register */
-+#define MCF_GPIO_PPDSDR_ATAH MCF_REG08(0xFC0A403E) /* ATA High Port Pin Data/Set Data Register */
-+#define MCF_GPIO_PPDSDR_ATAL MCF_REG08(0xFC0A403F) /* ATA Low Port Pin Data/Set Data Register */
-+#define MCF_GPIO_PPDSDR_FEC1H MCF_REG08(0xFC0A4040) /* FEC1 High Port Pin Data/Set Data Register */
-+#define MCF_GPIO_PPDSDR_FEC1L MCF_REG08(0xFC0A4041) /* FEC1 Low Port Pin Data/Set Data Register */
-+#define MCF_GPIO_PPDSDR_FBADH MCF_REG08(0xFC0A4044) /* Flexbus AD High Port Pin Data/Set Data Register */
-+#define MCF_GPIO_PPDSDR_FBADMH MCF_REG08(0xFC0A4045) /* Flexbus AD Med-High Port Pin Data/Set Data Register */
-+#define MCF_GPIO_PPDSDR_FBADML MCF_REG08(0xFC0A4046) /* Flexbus AD Med-Low Port Pin Data/Set Data Register */
-+#define MCF_GPIO_PPDSDR_FBADL MCF_REG08(0xFC0A4047) /* Flexbus AD Low Port Pin Data/Set Data Register */
-+#define MCF_GPIO_PCLRR_FEC0H MCF_REG08(0xFC0A4048) /* FEC0 High Port Clear Output Data Register */
-+#define MCF_GPIO_PCLRR_FEC0L MCF_REG08(0xFC0A4049) /* FEC0 Low Port Pin Data/Set Data Register */
-+#define MCF_GPIO_PCLRR_SSI MCF_REG08(0xFC0A404A) /* SSI Port Clear Output Data Register */
-+#define MCF_GPIO_PCLRR_FBCTL MCF_REG08(0xFC0A404B) /* Flexbus Control Port Clear Output Data Register */
-+#define MCF_GPIO_PCLRR_BE MCF_REG08(0xFC0A404C) /* Flexbus Byte Enable Port Clear Output Data Register */
-+#define MCF_GPIO_PCLRR_CS MCF_REG08(0xFC0A404D) /* Flexbus Chip-Select Port Clear Output Data Register */
-+#define MCF_GPIO_PCLRR_DMA MCF_REG08(0xFC0A404E) /* DMA Port Clear Output Data Register */
-+#define MCF_GPIO_PCLRR_FECI2C MCF_REG08(0xFC0A404F) /* FEC1 / I2C Port Clear Output Data Register */
-+#define MCF_GPIO_PCLRR_UART MCF_REG08(0xFC0A4051) /* UART Port Clear Output Data Register */
-+#define MCF_GPIO_PCLRR_DSPI MCF_REG08(0xFC0A4052) /* DSPI Port Clear Output Data Register */
-+#define MCF_GPIO_PCLRR_TIMER MCF_REG08(0xFC0A4053) /* Timer Port Clear Output Data Register */
-+#define MCF_GPIO_PCLRR_PCI MCF_REG08(0xFC0A4054) /* PCI Port Clear Output Data Register */
-+#define MCF_GPIO_PCLRR_USB MCF_REG08(0xFC0A4055) /* USB Port Clear Output Data Register */
-+#define MCF_GPIO_PCLRR_ATAH MCF_REG08(0xFC0A4056) /* ATA High Port Clear Output Data Register */
-+#define MCF_GPIO_PCLRR_ATAL MCF_REG08(0xFC0A4057) /* ATA Low Port Clear Output Data Register */
-+#define MCF_GPIO_PCLRR_FEC1H MCF_REG08(0xFC0A4058) /* FEC1 High Port Clear Output Data Register */
-+#define MCF_GPIO_PCLRR_FEC1L MCF_REG08(0xFC0A4059) /* FEC1 Low Port Clear Output Data Register */
-+#define MCF_GPIO_PCLRR_FBADH MCF_REG08(0xFC0A405C) /* Flexbus AD High Port Clear Output Data Register */
-+#define MCF_GPIO_PCLRR_FBADMH MCF_REG08(0xFC0A405D) /* Flexbus AD Med-High Port Clear Output Data Register */
-+#define MCF_GPIO_PCLRR_FBADML MCF_REG08(0xFC0A405E) /* Flexbus AD Med-Low Port Clear Output Data Register */
-+#define MCF_GPIO_PCLRR_FBADL MCF_REG08(0xFC0A405F) /* Flexbus AD Low Port Clear Output Data Register */
-+#define MCF_GPIO_PAR_FEC MCF_REG08(0xFC0A4060) /* FEC Pin Assignment Register */
-+#define MCF_GPIO_PAR_DMA MCF_REG08(0xFC0A4061) /* DMA Pin Assignment Register */
-+#define MCF_GPIO_PAR_FBCTL MCF_REG08(0xFC0A4062) /* Flexbus Control Pin Assignment Register */
-+#define MCF_GPIO_PAR_DSPI MCF_REG08(0xFC0A4063) /* DSPI Pin Assignment Register */
-+#define MCF_GPIO_PAR_BE MCF_REG08(0xFC0A4064) /* Flexbus Byte-Enable Pin Assignment Register */
-+#define MCF_GPIO_PAR_CS MCF_REG08(0xFC0A4065) /* Flexbus Chip-Select Pin Assignment Register */
-+#define MCF_GPIO_PAR_TIMER MCF_REG08(0xFC0A4066) /* Time Pin Assignment Register */
-+#define MCF_GPIO_PAR_USB MCF_REG08(0xFC0A4067) /* USB Pin Assignment Register */
-+#define MCF_GPIO_PAR_UART MCF_REG08(0xFC0A4069) /* UART Pin Assignment Register */
-+#define MCF_GPIO_PAR_FECI2C MCF_REG16(0xFC0A406A) /* FEC / I2C Pin Assignment Register */
-+#define MCF_GPIO_PAR_SSI MCF_REG16(0xFC0A406C) /* SSI Pin Assignment Register */
-+#define MCF_GPIO_PAR_ATA MCF_REG16(0xFC0A406E) /* ATA Pin Assignment Register */
-+#define MCF_GPIO_PAR_IRQ MCF_REG08(0xFC0A4070) /* IRQ Pin Assignment Register */
-+#define MCF_GPIO_PAR_PCI MCF_REG16(0xFC0A4072) /* PCI Pin Assignment Register */
-+#define MCF_GPIO_MSCR_SDRAM MCF_REG08(0xFC0A4074) /* SDRAM Mode Select Control Register */
-+#define MCF_GPIO_MSCR_PCI MCF_REG08(0xFC0A4075) /* PCI Mode Select Control Register */
-+#define MCF_GPIO_DSCR_I2C MCF_REG08(0xFC0A4078) /* I2C Drive Strength Control Register */
-+#define MCF_GPIO_DSCR_FLEXBUS MCF_REG08(0xFC0A4079) /* FLEXBUS Drive Strength Control Register */
-+#define MCF_GPIO_DSCR_FEC MCF_REG08(0xFC0A407A) /* FEC Drive Strength Control Register */
-+#define MCF_GPIO_DSCR_UART MCF_REG08(0xFC0A407B) /* UART Drive Strength Control Register */
-+#define MCF_GPIO_DSCR_DSPI MCF_REG08(0xFC0A407C) /* DSPI Drive Strength Control Register */
-+#define MCF_GPIO_DSCR_TIMER MCF_REG08(0xFC0A407D) /* TIMER Drive Strength Control Register */
-+#define MCF_GPIO_DSCR_SSI MCF_REG08(0xFC0A407E) /* SSI Drive Strength Control Register */
-+#define MCF_GPIO_DSCR_DMA MCF_REG08(0xFC0A407F) /* DMA Drive Strength Control Register */
-+#define MCF_GPIO_DSCR_DEBUG MCF_REG08(0xFC0A4080) /* DEBUG Drive Strength Control Register */
-+#define MCF_GPIO_DSCR_RESET MCF_REG08(0xFC0A4081) /* RESET Drive Strength Control Register */
-+#define MCF_GPIO_DSCR_IRQ MCF_REG08(0xFC0A4082) /* IRQ Drive Strength Control Register */
-+#define MCF_GPIO_DSCR_USB MCF_REG08(0xFC0A4083) /* USB Drive Strength Control Register */
-+#define MCF_GPIO_DSCR_ATA MCF_REG08(0xFC0A4084) /* ATA Drive Strength Control Register */
-+
-+/* Bit definitions and macros for PODR_FEC0H */
-+#define MCF_GPIO_PODR_FEC0H_PODR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */
-+#define MCF_GPIO_PODR_FEC0H_PODR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */
-+#define MCF_GPIO_PODR_FEC0H_PODR2 (0x04) /* FEC0_RXDV/FEC0_RMII_CRS_DV */
-+#define MCF_GPIO_PODR_FEC0H_PODR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */
-+#define MCF_GPIO_PODR_FEC0H_PODR4 (0x10) /* FEC0_COL / ULPI_DATA7 */
-+#define MCF_GPIO_PODR_FEC0H_PODR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */
-+#define MCF_GPIO_PODR_FEC0H_PODR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */
-+#define MCF_GPIO_PODR_FEC0H_PODR7 (0x80) /* FEC0_TXCLK / FEC0_RMII_REF_CLK */
-+
-+/* Bit definitions and macros for PODR_FEC0L */
-+#define MCF_GPIO_PODR_FEC0L_PODR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */
-+#define MCF_GPIO_PODR_FEC0L_PODR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */
-+#define MCF_GPIO_PODR_FEC0L_PODR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */
-+#define MCF_GPIO_PODR_FEC0L_PODR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */
-+#define MCF_GPIO_PODR_FEC0L_PODR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */
-+#define MCF_GPIO_PODR_FEC0L_PODR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */
-+#define MCF_GPIO_PODR_FEC0L_PODR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */
-+#define MCF_GPIO_PODR_FEC0L_PODR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */
-+
-+/* Bit definitions and macros for PODR_SSI */
-+#define MCF_GPIO_PODR_SSI_PODR0 (0x01) /* SSI_TXD / U1TXD */
-+#define MCF_GPIO_PODR_SSI_PODR1 (0x02) /* SSI_RXD / U1RXD */
-+#define MCF_GPIO_PODR_SSI_PODR2 (0x04) /* SSI_FS / U1RTS */
-+#define MCF_GPIO_PODR_SSI_PODR3 (0x08) /* SSI_BCLK / U1CTS */
-+#define MCF_GPIO_PODR_SSI_PODR4 (0x10) /* SSI_MCLK */
-+
-+/* Bit definitions and macros for PODR_FBCTL */
-+#define MCF_GPIO_PODR_FBCTL_PODR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */
-+#define MCF_GPIO_PODR_FBCTL_PODR1 (0x02) /* FB_RW */
-+#define MCF_GPIO_PODR_FBCTL_PODR2 (0x04) /* FB_TA */
-+#define MCF_GPIO_PODR_FBCTL_PODR3 (0x08) /* FB_OE */
-+
-+/* Bit definitions and macros for PODR_BE */
-+#define MCF_GPIO_PODR_BE_PODR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */
-+#define MCF_GPIO_PODR_BE_PODR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */
-+#define MCF_GPIO_PODR_BE_PODR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */
-+#define MCF_GPIO_PODR_BE_PODR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */
-+
-+/* Bit definitions and macros for PODR_CS */
-+#define MCF_GPIO_PODR_CS_PODR1 (0x02) /* FB_CS1 */
-+#define MCF_GPIO_PODR_CS_PODR2 (0x04) /* FB_CS2 */
-+#define MCF_GPIO_PODR_CS_PODR3 (0x08) /* FB_CS3 */
-+
-+/* Bit definitions and macros for PODR_DMA */
-+#define MCF_GPIO_PODR_DMA_PODR0 (0x01) /* DREQ0 */
-+#define MCF_GPIO_PODR_DMA_PODR1 (0x02) /* DACK0 / DSPI_PCS3 */
-+#define MCF_GPIO_PODR_DMA_PODR2 (0x04) /* DREQ1 / USB_CLKIN */
-+#define MCF_GPIO_PODR_DMA_PODR3 (0x08) /* DACK1 / ULPI_DIR */
-+
-+/* Bit definitions and macros for PODR_FECI2C */
-+#define MCF_GPIO_PODR_FECI2C_PODR0 (0x01) /* I2C_SDA / U2RXD */
-+#define MCF_GPIO_PODR_FECI2C_PODR1 (0x02) /* I2C_SCL / U2TXD */
-+#define MCF_GPIO_PODR_FECI2C_PODR2 (0x04) /* FEC0_MDIO */
-+#define MCF_GPIO_PODR_FECI2C_PODR3 (0x08) /* FEC0_MDC */
-+#define MCF_GPIO_PODR_FECI2C_PODR4 (0x10) /* FEC1_MDIO / ATA_DIOW */
-+#define MCF_GPIO_PODR_FECI2C_PODR5 (0x20) /* FEC1_MDC / ATA_DIOR */
-+
-+/* Bit definitions and macros for PODR_UART */
-+#define MCF_GPIO_PODR_UART_PODR0 (0x01) /* U1TXD */
-+#define MCF_GPIO_PODR_UART_PODR1 (0x02) /* U1RXD */
-+#define MCF_GPIO_PODR_UART_PODR2 (0x04) /* U1RTS */
-+#define MCF_GPIO_PODR_UART_PODR3 (0x08) /* U0CTS */
-+#define MCF_GPIO_PODR_UART_PODR4 (0x10) /* U1TXD */
-+#define MCF_GPIO_PODR_UART_PODR5 (0x20) /* U1RXD */
-+#define MCF_GPIO_PODR_UART_PODR6 (0x40) /* U1RTS */
-+#define MCF_GPIO_PODR_UART_PODR7 (0x80) /* U1CTS */
-+
-+/* Bit definitions and macros for PODR_DSPI */
-+#define MCF_GPIO_PODR_DSPI_PODR0 (0x01) /* DSPI_SOUT / SBF_DO */
-+#define MCF_GPIO_PODR_DSPI_PODR1 (0x02) /* DSPI_SIN / SBF_DI */
-+#define MCF_GPIO_PODR_DSPI_PODR2 (0x04) /* DSPI_SCK / SBF_CK */
-+#define MCF_GPIO_PODR_DSPI_PODR3 (0x08) /* DSPI_PCS0/SS */
-+#define MCF_GPIO_PODR_DSPI_PODR4 (0x10) /* DSPI_PCS1 / SBF_CS */
-+#define MCF_GPIO_PODR_DSPI_PODR5 (0x20) /* DSPI_PCS2 */
-+#define MCF_GPIO_PODR_DSPI_PODR6 (0x40) /* DSPI_PCS5/SS */
-+
-+/* Bit definitions and macros for PODR_TIMER */
-+#define MCF_GPIO_PODR_TIMER_PODR0 (0x01) /* T0IN / T0OUT / U2RTS */
-+#define MCF_GPIO_PODR_TIMER_PODR1 (0x02) /* T1IN / T1OUT / U2CTS */
-+#define MCF_GPIO_PODR_TIMER_PODR2 (0x04) /* T2IN / T2OUT / U2TXD */
-+#define MCF_GPIO_PODR_TIMER_PODR3 (0x08) /* T3IN / T3OUT / U2RXD */
-+
-+/* Bit definitions and macros for PODR_PCI */
-+#define MCF_GPIO_PODR_PCI_PODR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */
-+#define MCF_GPIO_PODR_PCI_PODR1 (0x02) /* PCI_REQ1 */
-+#define MCF_GPIO_PODR_PCI_PODR2 (0x04) /* PCI_REQ2 */
-+#define MCF_GPIO_PODR_PCI_PODR3 (0x08) /* PCI_REQ3 / ATA_INTR */
-+#define MCF_GPIO_PODR_PCI_PODR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */
-+#define MCF_GPIO_PODR_PCI_PODR5 (0x20) /* PCI_GNT1 / */
-+#define MCF_GPIO_PODR_PCI_PODR6 (0x40) /* PCI_GNT2 / */
-+#define MCF_GPIO_PODR_PCI_PODR7 (0x80) /* PCI_GNT3 / ATA_DMACK */
-+
-+/* Bit definitions and macros for PODR_USB */
-+#define MCF_GPIO_PODR_USB_PODR0 (0x01) /* USB_VBUS_OC / ULPI_STP */
-+#define MCF_GPIO_PODR_USB_PODR1 (0x02) /* USB_VBUS_EN / USB_PULLUP / ULPI_NXT */
-+
-+/* Bit definitions and macros for PODR_ATAH */
-+#define MCF_GPIO_PODR_ATAH_PODR0 (0x01) /* ATA_DA0 */
-+#define MCF_GPIO_PODR_ATAH_PODR1 (0x02) /* ATA_DA1 */
-+#define MCF_GPIO_PODR_ATAH_PODR2 (0x04) /* ATA_DA2 */
-+#define MCF_GPIO_PODR_ATAH_PODR3 (0x08) /* ATA_CS0 */
-+#define MCF_GPIO_PODR_ATAH_PODR4 (0x10) /* ATA_CS1 */
-+#define MCF_GPIO_PODR_ATAH_PODR5 (0x20) /* ATA_BUFFER_EN */
-+
-+/* Bit definitions and macros for PODR_ATAL */
-+#define MCF_GPIO_PODR_ATAL_PODR0 (0x01) /* ATA_IORDY */
-+#define MCF_GPIO_PODR_ATAL_PODR1 (0x02) /* ATA_DMARQ */
-+#define MCF_GPIO_PODR_ATAL_PODR2 (0x04) /* ATA_RESET */
-+
-+/* Bit definitions and macros for PODR_FEC1H */
-+#define MCF_GPIO_PODR_FEC1H_PODR0 (0x01) /* FEC1_CRS / ATA_DATA6 */
-+#define MCF_GPIO_PODR_FEC1H_PODR1 (0x02) /* FEC1_RXD0 / FEC1_RMII_RXD0 / ATA_DATA13 */
-+#define MCF_GPIO_PODR_FEC1H_PODR2 (0x04) /* FEC1_RXDV / FEC1_RMII_CRS_DV / ATA_DATA15 */
-+#define MCF_GPIO_PODR_FEC1H_PODR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */
-+#define MCF_GPIO_PODR_FEC1H_PODR4 (0x10) /* FEC1_COL / ATA_DATA7 */
-+#define MCF_GPIO_PODR_FEC1H_PODR5 (0x20) /* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */
-+#define MCF_GPIO_PODR_FEC1H_PODR6 (0x40) /* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */
-+#define MCF_GPIO_PODR_FEC1H_PODR7 (0x80) /* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */
-+
-+/* Bit definitions and macros for PODR_FEC1L */
-+#define MCF_GPIO_PODR_FEC1L_PODR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER / ATA_DATA12 */
-+#define MCF_GPIO_PODR_FEC1L_PODR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1 / ATA_DATA14 */
-+#define MCF_GPIO_PODR_FEC1L_PODR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */
-+#define MCF_GPIO_PODR_FEC1L_PODR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */
-+#define MCF_GPIO_PODR_FEC1L_PODR4 (0x10) /* FEC1_TXER / ATA_DATA0 */
-+#define MCF_GPIO_PODR_FEC1L_PODR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1 / ATA_DATA10 */
-+#define MCF_GPIO_PODR_FEC1L_PODR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */
-+#define MCF_GPIO_PODR_FEC1L_PODR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */
-+
-+/* Bit definitions and macros for PODR_FBADH */
-+#define MCF_GPIO_PODR_FBADH_PODR0 (0x01) /* FB_AD24 */
-+#define MCF_GPIO_PODR_FBADH_PODR1 (0x02) /* FB_AD25 */
-+#define MCF_GPIO_PODR_FBADH_PODR2 (0x04) /* FB_AD26 */
-+#define MCF_GPIO_PODR_FBADH_PODR3 (0x08) /* FB_AD27 */
-+#define MCF_GPIO_PODR_FBADH_PODR4 (0x10) /* FB_AD28 */
-+#define MCF_GPIO_PODR_FBADH_PODR5 (0x20) /* FB_AD29 */
-+#define MCF_GPIO_PODR_FBADH_PODR6 (0x40) /* FB_AD30 */
-+#define MCF_GPIO_PODR_FBADH_PODR7 (0x80) /* FB_AD31 */
-+
-+/* Bit definitions and macros for PODR_FBADMH */
-+#define MCF_GPIO_PODR_FBADMH_PODR0 (0x01) /* FB_AD16 */
-+#define MCF_GPIO_PODR_FBADMH_PODR1 (0x02) /* FB_AD17 */
-+#define MCF_GPIO_PODR_FBADMH_PODR2 (0x04) /* FB_AD18 */
-+#define MCF_GPIO_PODR_FBADMH_PODR3 (0x08) /* FB_AD19 */
-+#define MCF_GPIO_PODR_FBADMH_PODR4 (0x10) /* FB_AD20 */
-+#define MCF_GPIO_PODR_FBADMH_PODR5 (0x20) /* FB_AD21 */
-+#define MCF_GPIO_PODR_FBADMH_PODR6 (0x40) /* FB_AD22 */
-+#define MCF_GPIO_PODR_FBADMH_PODR7 (0x80) /* FB_AD23 */
-+
-+/* Bit definitions and macros for PODR_FBADML */
-+#define MCF_GPIO_PODR_FBADML_PODR0 (0x01) /* FB_AD8 */
-+#define MCF_GPIO_PODR_FBADML_PODR1 (0x02) /* FB_AD9 */
-+#define MCF_GPIO_PODR_FBADML_PODR2 (0x04) /* FB_AD10 */
-+#define MCF_GPIO_PODR_FBADML_PODR3 (0x08) /* FB_AD11 */
-+#define MCF_GPIO_PODR_FBADML_PODR4 (0x10) /* FB_AD12 */
-+#define MCF_GPIO_PODR_FBADML_PODR5 (0x20) /* FB_AD13 */
-+#define MCF_GPIO_PODR_FBADML_PODR6 (0x40) /* FB_AD14 */
-+#define MCF_GPIO_PODR_FBADML_PODR7 (0x80) /* FB_AD15 */
-+
-+/* Bit definitions and macros for PODR_FBADL */
-+#define MCF_GPIO_PODR_FBADL_PODR0 (0x01) /* FB_AD0 */
-+#define MCF_GPIO_PODR_FBADL_PODR1 (0x02) /* FB_AD1 */
-+#define MCF_GPIO_PODR_FBADL_PODR2 (0x04) /* FB_AD2 */
-+#define MCF_GPIO_PODR_FBADL_PODR3 (0x08) /* FB_AD3 */
-+#define MCF_GPIO_PODR_FBADL_PODR4 (0x10) /* FB_AD4 */
-+#define MCF_GPIO_PODR_FBADL_PODR5 (0x20) /* FB_AD5 */
-+#define MCF_GPIO_PODR_FBADL_PODR6 (0x40) /* FB_AD6 */
-+#define MCF_GPIO_PODR_FBADL_PODR7 (0x80) /* FB_AD7 */
-+
-+/* Bit definitions and macros for PDDR_FEC0H */
-+#define MCF_GPIO_PDDR_FEC0H_PDDR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */
-+#define MCF_GPIO_PDDR_FEC0H_PDDR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */
-+#define MCF_GPIO_PDDR_FEC0H_PDDR2 (0x04) /* FEC0_RXDV/FEC0_RMII_CRS_DV */
-+#define MCF_GPIO_PDDR_FEC0H_PDDR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */
-+#define MCF_GPIO_PDDR_FEC0H_PDDR4 (0x10) /* FEC0_COL / ULPI_DATA7 */
-+#define MCF_GPIO_PDDR_FEC0H_PDDR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */
-+#define MCF_GPIO_PDDR_FEC0H_PDDR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */
-+#define MCF_GPIO_PDDR_FEC0H_PDDR7 (0x80) /* FEC0_TXCLK / FEC0_RMII_REF_CLK */
-+
-+/* Bit definitions and macros for PDDR_FEC0L */
-+#define MCF_GPIO_PDDR_FEC0L_PDDR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */
-+#define MCF_GPIO_PDDR_FEC0L_PDDR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */
-+#define MCF_GPIO_PDDR_FEC0L_PDDR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */
-+#define MCF_GPIO_PDDR_FEC0L_PDDR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */
-+#define MCF_GPIO_PDDR_FEC0L_PDDR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */
-+#define MCF_GPIO_PDDR_FEC0L_PDDR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */
-+#define MCF_GPIO_PDDR_FEC0L_PDDR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */
-+#define MCF_GPIO_PDDR_FEC0L_PDDR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */
-+
-+/* Bit definitions and macros for PDDR_SSI */
-+#define MCF_GPIO_PDDR_SSI_PDDR0 (0x01) /* SSI_TXD / U1TXD */
-+#define MCF_GPIO_PDDR_SSI_PDDR1 (0x02) /* SSI_RXD / U1RXD */
-+#define MCF_GPIO_PDDR_SSI_PDDR2 (0x04) /* SSI_FS / U1RTS */
-+#define MCF_GPIO_PDDR_SSI_PDDR3 (0x08) /* SSI_BCLK / U1CTS */
-+#define MCF_GPIO_PDDR_SSI_PDDR4 (0x10) /* SSI_MCLK */
-+
-+/* Bit definitions and macros for PDDR_FBCTL */
-+#define MCF_GPIO_PDDR_FBCTL_PDDR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */
-+#define MCF_GPIO_PDDR_FBCTL_PDDR1 (0x02) /* FB_RW */
-+#define MCF_GPIO_PDDR_FBCTL_PDDR2 (0x04) /* FB_TA */
-+#define MCF_GPIO_PDDR_FBCTL_PDDR3 (0x08) /* FB_OE */
-+
-+/* Bit definitions and macros for PDDR_BE */
-+#define MCF_GPIO_PDDR_BE_PDDR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */
-+#define MCF_GPIO_PDDR_BE_PDDR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */
-+#define MCF_GPIO_PDDR_BE_PDDR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */
-+#define MCF_GPIO_PDDR_BE_PDDR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */
-+
-+/* Bit definitions and macros for PDDR_CS */
-+#define MCF_GPIO_PDDR_CS_PDDR1 (0x02) /* FB_CS1 */
-+#define MCF_GPIO_PDDR_CS_PDDR2 (0x04) /* FB_CS2 */
-+#define MCF_GPIO_PDDR_CS_PDDR3 (0x08) /* FB_CS3 */
-+
-+/* Bit definitions and macros for PDDR_DMA */
-+#define MCF_GPIO_PDDR_DMA_PDDR0 (0x01) /* DREQ0 */
-+#define MCF_GPIO_PDDR_DMA_PDDR1 (0x02) /* DACK0 / DSPI_PCS3 */
-+#define MCF_GPIO_PDDR_DMA_PDDR2 (0x04) /* DREQ1 / USB_CLKIN */
-+#define MCF_GPIO_PDDR_DMA_PDDR3 (0x08) /* DACK1 / ULPI_DIR */
-+
-+/* Bit definitions and macros for PDDR_FECI2C */
-+#define MCF_GPIO_PDDR_FECI2C_PDDR0 (0x01) /* I2C_SDA / U2RXD */
-+#define MCF_GPIO_PDDR_FECI2C_PDDR1 (0x02) /* I2C_SCL / U2TXD */
-+#define MCF_GPIO_PDDR_FECI2C_PDDR2 (0x04) /* FEC0_MDIO */
-+#define MCF_GPIO_PDDR_FECI2C_PDDR3 (0x08) /* FEC0_MDC */
-+#define MCF_GPIO_PDDR_FECI2C_PDDR4 (0x10) /* FEC1_MDIO / ATA_DIOW */
-+#define MCF_GPIO_PDDR_FECI2C_PDDR5 (0x20) /* FEC1_MDC / ATA_DIOR */
-+
-+/* Bit definitions and macros for PDDR_UART */
-+#define MCF_GPIO_PDDR_UART_PDDR0 (0x01) /* U1TXD */
-+#define MCF_GPIO_PDDR_UART_PDDR1 (0x02) /* U1RXD */
-+#define MCF_GPIO_PDDR_UART_PDDR2 (0x04) /* U1RTS */
-+#define MCF_GPIO_PDDR_UART_PDDR3 (0x08) /* U0CTS */
-+#define MCF_GPIO_PDDR_UART_PDDR4 (0x10) /* U1TXD */
-+#define MCF_GPIO_PDDR_UART_PDDR5 (0x20) /* U1RXD */
-+#define MCF_GPIO_PDDR_UART_PDDR6 (0x40) /* U1RTS */
-+#define MCF_GPIO_PDDR_UART_PDDR7 (0x80) /* U1CTS */
-+
-+/* Bit definitions and macros for PDDR_DSPI */
-+#define MCF_GPIO_PDDR_DSPI_PDDR0 (0x01) /* DSPI_SOUT / SBF_DO */
-+#define MCF_GPIO_PDDR_DSPI_PDDR1 (0x02) /* DSPI_SIN / SBF_DI */
-+#define MCF_GPIO_PDDR_DSPI_PDDR2 (0x04) /* DSPI_SCK / SBF_CK */
-+#define MCF_GPIO_PDDR_DSPI_PDDR3 (0x08) /* DSPI_PCS0/SS */
-+#define MCF_GPIO_PDDR_DSPI_PDDR4 (0x10) /* DSPI_PCS1 / SBF_CS */
-+#define MCF_GPIO_PDDR_DSPI_PDDR5 (0x20) /* DSPI_PCS2 */
-+#define MCF_GPIO_PDDR_DSPI_PDDR6 (0x40) /* DSPI_PCS5/SS */
-+
-+/* Bit definitions and macros for PDDR_TIMER */
-+#define MCF_GPIO_PDDR_TIMER_PDDR0 (0x01) /* T0IN / T0OUT / U2RTS */
-+#define MCF_GPIO_PDDR_TIMER_PDDR1 (0x02) /* T1IN / T1OUT / U2CTS */
-+#define MCF_GPIO_PDDR_TIMER_PDDR2 (0x04) /* T2IN / T2OUT / U2TXD */
-+#define MCF_GPIO_PDDR_TIMER_PDDR3 (0x08) /* T3IN / T3OUT / U2RXD */
-+
-+/* Bit definitions and macros for PDDR_PCI */
-+#define MCF_GPIO_PDDR_PCI_PDDR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */
-+#define MCF_GPIO_PDDR_PCI_PDDR1 (0x02) /* PCI_REQ1 */
-+#define MCF_GPIO_PDDR_PCI_PDDR2 (0x04) /* PCI_REQ2 */
-+#define MCF_GPIO_PDDR_PCI_PDDR3 (0x08) /* PCI_REQ3 / ATA_INTR */
-+#define MCF_GPIO_PDDR_PCI_PDDR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */
-+#define MCF_GPIO_PDDR_PCI_PDDR5 (0x20) /* PCI_GNT1 / */
-+#define MCF_GPIO_PDDR_PCI_PDDR6 (0x40) /* PCI_GNT2 / */
-+#define MCF_GPIO_PDDR_PCI_PDDR7 (0x80) /* PCI_GNT3 / ATA_DMACK */
-+
-+/* Bit definitions and macros for PDDR_USB */
-+#define MCF_GPIO_PDDR_USB_PDDR0 (0x01) /* USB_VBUS_OC / ULPI_STP */
-+#define MCF_GPIO_PDDR_USB_PDDR1 (0x02) /* USB_VBUS_EN / USB_PULLUP / ULPI_NXT */
-+
-+/* Bit definitions and macros for PDDR_ATAH */
-+#define MCF_GPIO_PDDR_ATAH_PDDR0 (0x01) /* ATA_DA0 */
-+#define MCF_GPIO_PDDR_ATAH_PDDR1 (0x02) /* ATA_DA1 */
-+#define MCF_GPIO_PDDR_ATAH_PDDR2 (0x04) /* ATA_DA2 */
-+#define MCF_GPIO_PDDR_ATAH_PDDR3 (0x08) /* ATA_CS0 */
-+#define MCF_GPIO_PDDR_ATAH_PDDR4 (0x10) /* ATA_CS1 */
-+#define MCF_GPIO_PDDR_ATAH_PDDR5 (0x20) /* ATA_BUFFER_EN */
-+
-+/* Bit definitions and macros for PDDR_ATAL */
-+#define MCF_GPIO_PDDR_ATAL_PDDR0 (0x01) /* ATA_IORDY */
-+#define MCF_GPIO_PDDR_ATAL_PDDR1 (0x02) /* ATA_DMARQ */
-+#define MCF_GPIO_PDDR_ATAL_PDDR2 (0x04) /* ATA_RESET */
-+
-+/* Bit definitions and macros for PDDR_FEC1H */
-+#define MCF_GPIO_PDDR_FEC1H_PDDR0 (0x01) /* FEC1_CRS / ATA_DATA6 */
-+#define MCF_GPIO_PDDR_FEC1H_PDDR1 (0x02) /* FEC1_RXD0 / FEC1_RMII_RXD0 / ATA_DATA13 */
-+#define MCF_GPIO_PDDR_FEC1H_PDDR2 (0x04) /* FEC1_RXDV / FEC1_RMII_CRS_DV / ATA_DATA15 */
-+#define MCF_GPIO_PDDR_FEC1H_PDDR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */
-+#define MCF_GPIO_PDDR_FEC1H_PDDR4 (0x10) /* FEC1_COL / ATA_DATA7 */
-+#define MCF_GPIO_PDDR_FEC1H_PDDR5 (0x20) /* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */
-+#define MCF_GPIO_PDDR_FEC1H_PDDR6 (0x40) /* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */
-+#define MCF_GPIO_PDDR_FEC1H_PDDR7 (0x80) /* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */
-+
-+/* Bit definitions and macros for PDDR_FEC1L */
-+#define MCF_GPIO_PDDR_FEC1L_PDDR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER / ATA_DATA12 */
-+#define MCF_GPIO_PDDR_FEC1L_PDDR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1 / ATA_DATA14 */
-+#define MCF_GPIO_PDDR_FEC1L_PDDR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */
-+#define MCF_GPIO_PDDR_FEC1L_PDDR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */
-+#define MCF_GPIO_PDDR_FEC1L_PDDR4 (0x10) /* FEC1_TXER / ATA_DATA0 */
-+#define MCF_GPIO_PDDR_FEC1L_PDDR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1 / ATA_DATA10 */
-+#define MCF_GPIO_PDDR_FEC1L_PDDR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */
-+#define MCF_GPIO_PDDR_FEC1L_PDDR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */
-+
-+/* Bit definitions and macros for PDDR_FBADH */
-+#define MCF_GPIO_PDDR_FBADH_PDDR0 (0x01) /* FB_AD24 */
-+#define MCF_GPIO_PDDR_FBADH_PDDR1 (0x02) /* FB_AD25 */
-+#define MCF_GPIO_PDDR_FBADH_PDDR2 (0x04) /* FB_AD26 */
-+#define MCF_GPIO_PDDR_FBADH_PDDR3 (0x08) /* FB_AD27 */
-+#define MCF_GPIO_PDDR_FBADH_PDDR4 (0x10) /* FB_AD28 */
-+#define MCF_GPIO_PDDR_FBADH_PDDR5 (0x20) /* FB_AD29 */
-+#define MCF_GPIO_PDDR_FBADH_PDDR6 (0x40) /* FB_AD30 */
-+#define MCF_GPIO_PDDR_FBADH_PDDR7 (0x80) /* FB_AD31 */
-+
-+/* Bit definitions and macros for PDDR_FBADMH */
-+#define MCF_GPIO_PDDR_FBADMH_PDDR0 (0x01) /* FB_AD16 */
-+#define MCF_GPIO_PDDR_FBADMH_PDDR1 (0x02) /* FB_AD17 */
-+#define MCF_GPIO_PDDR_FBADMH_PDDR2 (0x04) /* FB_AD18 */
-+#define MCF_GPIO_PDDR_FBADMH_PDDR3 (0x08) /* FB_AD19 */
-+#define MCF_GPIO_PDDR_FBADMH_PDDR4 (0x10) /* FB_AD20 */
-+#define MCF_GPIO_PDDR_FBADMH_PDDR5 (0x20) /* FB_AD21 */
-+#define MCF_GPIO_PDDR_FBADMH_PDDR6 (0x40) /* FB_AD22 */
-+#define MCF_GPIO_PDDR_FBADMH_PDDR7 (0x80) /* FB_AD23 */
-+
-+/* Bit definitions and macros for PDDR_FBADML */
-+#define MCF_GPIO_PDDR_FBADML_PDDR0 (0x01) /* FB_AD8 */
-+#define MCF_GPIO_PDDR_FBADML_PDDR1 (0x02) /* FB_AD9 */
-+#define MCF_GPIO_PDDR_FBADML_PDDR2 (0x04) /* FB_AD10 */
-+#define MCF_GPIO_PDDR_FBADML_PDDR3 (0x08) /* FB_AD11 */
-+#define MCF_GPIO_PDDR_FBADML_PDDR4 (0x10) /* FB_AD12 */
-+#define MCF_GPIO_PDDR_FBADML_PDDR5 (0x20) /* FB_AD13 */
-+#define MCF_GPIO_PDDR_FBADML_PDDR6 (0x40) /* FB_AD14 */
-+#define MCF_GPIO_PDDR_FBADML_PDDR7 (0x80) /* FB_AD15 */
-+
-+/* Bit definitions and macros for PDDR_FBADL */
-+#define MCF_GPIO_PDDR_FBADL_PDDR0 (0x01) /* FB_AD0 */
-+#define MCF_GPIO_PDDR_FBADL_PDDR1 (0x02) /* FB_AD1 */
-+#define MCF_GPIO_PDDR_FBADL_PDDR2 (0x04) /* FB_AD2 */
-+#define MCF_GPIO_PDDR_FBADL_PDDR3 (0x08) /* FB_AD3 */
-+#define MCF_GPIO_PDDR_FBADL_PDDR4 (0x10) /* FB_AD4 */
-+#define MCF_GPIO_PDDR_FBADL_PDDR5 (0x20) /* FB_AD5 */
-+#define MCF_GPIO_PDDR_FBADL_PDDR6 (0x40) /* FB_AD6 */
-+#define MCF_GPIO_PDDR_FBADL_PDDR7 (0x80) /* FB_AD7 */
-+
-+/* Bit definitions and macros for PPDSDR_FEC0H */
-+#define MCF_GPIO_PPDSDR_FEC0H_PPDR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */
-+#define MCF_GPIO_PPDSDR_FEC0H_PPDR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */
-+#define MCF_GPIO_PPDSDR_FEC0H_PPDR2 (0x04) /* FEC0_RXDV / FEC0_RMII_CRS_DV */
-+#define MCF_GPIO_PPDSDR_FEC0H_PPDR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */
-+#define MCF_GPIO_PPDSDR_FEC0H_PPDR4 (0x10) /* FEC0_COL / ULPI_DATA7 */
-+#define MCF_GPIO_PPDSDR_FEC0H_PPDR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */
-+#define MCF_GPIO_PPDSDR_FEC0H_PPDR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */
-+#define MCF_GPIO_PPDSDR_FEC0H_PPDR7 (0x80) /* FEC0_TXCLK / FEC0_RMII_REF_CLK */
-+
-+/* Bit definitions and macros for PPDSDR_FEC0L */
-+#define MCF_GPIO_PPDSDR_FEC0L_PCLRR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */
-+#define MCF_GPIO_PPDSDR_FEC0L_PCLRR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */
-+#define MCF_GPIO_PPDSDR_FEC0L_PCLRR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */
-+#define MCF_GPIO_PPDSDR_FEC0L_PCLRR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */
-+#define MCF_GPIO_PPDSDR_FEC0L_PCLRR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */
-+#define MCF_GPIO_PPDSDR_FEC0L_PCLRR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */
-+#define MCF_GPIO_PPDSDR_FEC0L_PCLRR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */
-+#define MCF_GPIO_PPDSDR_FEC0L_PCLRR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */
-+
-+/* Bit definitions and macros for PPDSDR_SSI */
-+#define MCF_GPIO_PPDSDR_SSI_PPDR0 (0x01) /* SSI_TXD / U1TXD */
-+#define MCF_GPIO_PPDSDR_SSI_PPDR1 (0x02) /* SSI_RXD / U1RXD */
-+#define MCF_GPIO_PPDSDR_SSI_PPDR2 (0x04) /* SSI_FS / U1RTS */
-+#define MCF_GPIO_PPDSDR_SSI_PPDR3 (0x08) /* SSI_BCLK / U1CTS */
-+#define MCF_GPIO_PPDSDR_SSI_PPDR4 (0x10) /* SSI_MCLK */
-+
-+/* Bit definitions and macros for PPDSDR_FBCTL */
-+#define MCF_GPIO_PPDSDR_FBCTL_PPDR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */
-+#define MCF_GPIO_PPDSDR_FBCTL_PPDR1 (0x02) /* FB_RW */
-+#define MCF_GPIO_PPDSDR_FBCTL_PPDR2 (0x04) /* FB_TA */
-+#define MCF_GPIO_PPDSDR_FBCTL_PPDR3 (0x08) /* FB_OE */
-+
-+/* Bit definitions and macros for PPDSDR_BE */
-+#define MCF_GPIO_PPDSDR_BE_PPDR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */
-+#define MCF_GPIO_PPDSDR_BE_PPDR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */
-+#define MCF_GPIO_PPDSDR_BE_PPDR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */
-+#define MCF_GPIO_PPDSDR_BE_PPDR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */
-+
-+/* Bit definitions and macros for PPDSDR_CS */
-+#define MCF_GPIO_PPDSDR_CS_PPDR1 (0x02) /* FB_CS1 */
-+#define MCF_GPIO_PPDSDR_CS_PPDR2 (0x04) /* FB_CS2 */
-+#define MCF_GPIO_PPDSDR_CS_PPDR3 (0x08) /* FB_CS3 */
-+
-+/* Bit definitions and macros for PPDSDR_DMA */
-+#define MCF_GPIO_PPDSDR_DMA_PPDR0 (0x01) /* DREQ0 */
-+#define MCF_GPIO_PPDSDR_DMA_PPDR1 (0x02) /* DACK0 / DSPI_PCS3 */
-+#define MCF_GPIO_PPDSDR_DMA_PPDR2 (0x04) /* DREQ1 / USB_CLKIN */
-+#define MCF_GPIO_PPDSDR_DMA_PPDR3 (0x08) /* DACK1 / ULPI_DIR */
-+
-+/* Bit definitions and macros for PPDSDR_FECI2C */
-+#define MCF_GPIO_PPDSDR_FECI2C_PPDR0 (0x01) /* I2C_SDA / U2RXD */
-+#define MCF_GPIO_PPDSDR_FECI2C_PPDR1 (0x02) /* I2C_SCL / U2TXD */
-+#define MCF_GPIO_PPDSDR_FECI2C_PPDR2 (0x04) /* FEC0_MDIO */
-+#define MCF_GPIO_PPDSDR_FECI2C_PPDR3 (0x08) /* FEC0_MDC */
-+#define MCF_GPIO_PPDSDR_FECI2C_PPDR4 (0x10) /* FEC1_MDIO / ATA_DIOW */
-+#define MCF_GPIO_PPDSDR_FECI2C_PPDR5 (0x20) /* FEC1_MDC / ATA_DIOR */
-+
-+/* Bit definitions and macros for PPDSDR_UART */
-+#define MCF_GPIO_PPDSDR_UART_PPDR0 (0x01) /* U1TXD */
-+#define MCF_GPIO_PPDSDR_UART_PPDR1 (0x02) /* U1RXD */
-+#define MCF_GPIO_PPDSDR_UART_PPDR2 (0x04) /* U1RTS */
-+#define MCF_GPIO_PPDSDR_UART_PPDR3 (0x08) /* U0CTS */
-+#define MCF_GPIO_PPDSDR_UART_PPDR4 (0x10) /* U1TXD */
-+#define MCF_GPIO_PPDSDR_UART_PPDR5 (0x20) /* U1RXD */
-+#define MCF_GPIO_PPDSDR_UART_PPDR6 (0x40) /* U1RTS */
-+#define MCF_GPIO_PPDSDR_UART_PPDR7 (0x80) /* U1CTS */
-+
-+/* Bit definitions and macros for PPDSDR_DSPI */
-+#define MCF_GPIO_PPDSDR_DSPI_PPDR0 (0x01) /* DSPI_SOUT / SBF_DO */
-+#define MCF_GPIO_PPDSDR_DSPI_PPDR1 (0x02) /* DSPI_SIN / SBF_DI */
-+#define MCF_GPIO_PPDSDR_DSPI_PPDR2 (0x04) /* DSPI_SCK / SBF_CK */
-+#define MCF_GPIO_PPDSDR_DSPI_PPDR3 (0x08) /* DSPI_PCS0/SS */
-+#define MCF_GPIO_PPDSDR_DSPI_PPDR4 (0x10) /* DSPI_PCS1 / SBF_CS */
-+#define MCF_GPIO_PPDSDR_DSPI_PPDR5 (0x20) /* DSPI_PCS2 */
-+#define MCF_GPIO_PPDSDR_DSPI_PPDR6 (0x40) /* DSPI_PCS5/SS */
-+
-+/* Bit definitions and macros for PPDSDR_TIMER */
-+#define MCF_GPIO_PPDSDR_TIMER_PPDR0 (0x01) /* T0IN / T0OUT / U2RTS */
-+#define MCF_GPIO_PPDSDR_TIMER_PPDR1 (0x02) /* T1IN / T1OUT / U2CTS */
-+#define MCF_GPIO_PPDSDR_TIMER_PPDR2 (0x04) /* T2IN / T2OUT / U2TXD */
-+#define MCF_GPIO_PPDSDR_TIMER_PPDR3 (0x08) /* T3IN / T3OUT / U2RXD */
-+
-+/* Bit definitions and macros for PPDSDR_PCI */
-+#define MCF_GPIO_PPDSDR_PCI_PPDR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */
-+#define MCF_GPIO_PPDSDR_PCI_PPDR1 (0x02) /* PCI_REQ1 */
-+#define MCF_GPIO_PPDSDR_PCI_PPDR2 (0x04) /* PCI_REQ2 */
-+#define MCF_GPIO_PPDSDR_PCI_PPDR3 (0x08) /* PCI_REQ3 / ATA_INTR */
-+#define MCF_GPIO_PPDSDR_PCI_PPDR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */
-+#define MCF_GPIO_PPDSDR_PCI_PPDR5 (0x20) /* PCI_GNT1 / */
-+#define MCF_GPIO_PPDSDR_PCI_PPDR6 (0x40) /* PCI_GNT2 / */
-+#define MCF_GPIO_PPDSDR_PCI_PPDR7 (0x80) /* PCI_GNT3 / ATA_DMACK */
-+
-+/* Bit definitions and macros for PPDSDR_USB */
-+#define MCF_GPIO_PPDSDR_USB_PPDR0 (0x01) /* USB_VBUS_OC / ULPI_STP */
-+#define MCF_GPIO_PPDSDR_USB_PPDR1 (0x02) /* USB_VBUS_EN / USB_PULLUP / ULPI_NXT */
-+
-+/* Bit definitions and macros for PPDSDR_ATAH */
-+#define MCF_GPIO_PPDSDR_ATAH_PPDR0 (0x01) /* ATA_DA0 */
-+#define MCF_GPIO_PPDSDR_ATAH_PPDR1 (0x02) /* ATA_DA1 */
-+#define MCF_GPIO_PPDSDR_ATAH_PPDR2 (0x04) /* ATA_DA2 */
-+#define MCF_GPIO_PPDSDR_ATAH_PPDR3 (0x08) /* ATA_CS0 */
-+#define MCF_GPIO_PPDSDR_ATAH_PPDR4 (0x10) /* ATA_CS1 */
-+#define MCF_GPIO_PPDSDR_ATAH_PPDR5 (0x20) /* ATA_BUFFER_EN */
-+
-+/* Bit definitions and macros for PPDSDR_ATAL */
-+#define MCF_GPIO_PPDSDR_ATAL_PPDR0 (0x01) /* ATA_IORDY */
-+#define MCF_GPIO_PPDSDR_ATAL_PPDR1 (0x02) /* ATA_DMARQ */
-+#define MCF_GPIO_PPDSDR_ATAL_PPDR2 (0x04) /* ATA_RESET */
-+
-+/* Bit definitions and macros for PPDSDR_FEC1H */
-+#define MCF_GPIO_PPDSDR_FEC1H_PPDR0 (0x01) /* FEC1_CRS / ATA_DATA6 */
-+#define MCF_GPIO_PPDSDR_FEC1H_PPDR1 (0x02) /* FEC1_RXD0 / FEC1_RMII_RXD0 / ATA_DATA13 */
-+#define MCF_GPIO_PPDSDR_FEC1H_PPDR2 (0x04) /* FEC1_RXDV / FEC1_RMII_CRS_DV / ATA_DATA15 */
-+#define MCF_GPIO_PPDSDR_FEC1H_PPDR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */
-+#define MCF_GPIO_PPDSDR_FEC1H_PPDR4 (0x10) /* FEC1_COL / ATA_DATA7 */
-+#define MCF_GPIO_PPDSDR_FEC1H_PPDR5 (0x20) /* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */
-+#define MCF_GPIO_PPDSDR_FEC1H_PPDR6 (0x40) /* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */
-+#define MCF_GPIO_PPDSDR_FEC1H_PPDR7 (0x80) /* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */
-+
-+/* Bit definitions and macros for PPDSDR_FEC1L */
-+#define MCF_GPIO_PPDSDR_FEC1L_PPDR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER / ATA_DATA12 */
-+#define MCF_GPIO_PPDSDR_FEC1L_PPDR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1 / ATA_DATA14 */
-+#define MCF_GPIO_PPDSDR_FEC1L_PPDR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */
-+#define MCF_GPIO_PPDSDR_FEC1L_PPDR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */
-+#define MCF_GPIO_PPDSDR_FEC1L_PPDR4 (0x10) /* FEC1_TXER / ATA_DATA0 */
-+#define MCF_GPIO_PPDSDR_FEC1L_PPDR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1 / ATA_DATA10 */
-+#define MCF_GPIO_PPDSDR_FEC1L_PPDR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */
-+#define MCF_GPIO_PPDSDR_FEC1L_PPDR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */
-+
-+/* Bit definitions and macros for PPDSDR_FBADH */
-+#define MCF_GPIO_PPDSDR_FBADH_PPDR0 (0x01) /* FB_AD24 */
-+#define MCF_GPIO_PPDSDR_FBADH_PPDR1 (0x02) /* FB_AD25 */
-+#define MCF_GPIO_PPDSDR_FBADH_PPDR2 (0x04) /* FB_AD26 */
-+#define MCF_GPIO_PPDSDR_FBADH_PPDR3 (0x08) /* FB_AD27 */
-+#define MCF_GPIO_PPDSDR_FBADH_PPDR4 (0x10) /* FB_AD28 */
-+#define MCF_GPIO_PPDSDR_FBADH_PPDR5 (0x20) /* FB_AD29 */
-+#define MCF_GPIO_PPDSDR_FBADH_PPDR6 (0x40) /* FB_AD30 */
-+#define MCF_GPIO_PPDSDR_FBADH_PPDR7 (0x80) /* FB_AD31 */
-+
-+/* Bit definitions and macros for PPDSDR_FBADMH */
-+#define MCF_GPIO_PPDSDR_FBADMH_PPDR0 (0x01) /* FB_AD16 */
-+#define MCF_GPIO_PPDSDR_FBADMH_PPDR1 (0x02) /* FB_AD17 */
-+#define MCF_GPIO_PPDSDR_FBADMH_PPDR2 (0x04) /* FB_AD18 */
-+#define MCF_GPIO_PPDSDR_FBADMH_PPDR3 (0x08) /* FB_AD19 */
-+#define MCF_GPIO_PPDSDR_FBADMH_PPDR4 (0x10) /* FB_AD20 */
-+#define MCF_GPIO_PPDSDR_FBADMH_PPDR5 (0x20) /* FB_AD21 */
-+#define MCF_GPIO_PPDSDR_FBADMH_PPDR6 (0x40) /* FB_AD22 */
-+#define MCF_GPIO_PPDSDR_FBADMH_PPDR7 (0x80) /* FB_AD23 */
-+
-+/* Bit definitions and macros for PPDSDR_FBADML */
-+#define MCF_GPIO_PPDSDR_FBADML_PPDR0 (0x01) /* FB_AD8 */
-+#define MCF_GPIO_PPDSDR_FBADML_PPDR1 (0x02) /* FB_AD9 */
-+#define MCF_GPIO_PPDSDR_FBADML_PPDR2 (0x04) /* FB_AD10 */
-+#define MCF_GPIO_PPDSDR_FBADML_PPDR3 (0x08) /* FB_AD11 */
-+#define MCF_GPIO_PPDSDR_FBADML_PPDR4 (0x10) /* FB_AD12 */
-+#define MCF_GPIO_PPDSDR_FBADML_PPDR5 (0x20) /* FB_AD13 */
-+#define MCF_GPIO_PPDSDR_FBADML_PPDR6 (0x40) /* FB_AD14 */
-+#define MCF_GPIO_PPDSDR_FBADML_PPDR7 (0x80) /* FB_AD15 */
-+
-+/* Bit definitions and macros for PPDSDR_FBADL */
-+#define MCF_GPIO_PPDSDR_FBADL_PPDR0 (0x01) /* FB_AD0 */
-+#define MCF_GPIO_PPDSDR_FBADL_PPDR1 (0x02) /* FB_AD1 */
-+#define MCF_GPIO_PPDSDR_FBADL_PPDR2 (0x04) /* FB_AD2 */
-+#define MCF_GPIO_PPDSDR_FBADL_PPDR3 (0x08) /* FB_AD3 */
-+#define MCF_GPIO_PPDSDR_FBADL_PPDR4 (0x10) /* FB_AD4 */
-+#define MCF_GPIO_PPDSDR_FBADL_PPDR5 (0x20) /* FB_AD5 */
-+#define MCF_GPIO_PPDSDR_FBADL_PPDR6 (0x40) /* FB_AD6 */
-+#define MCF_GPIO_PPDSDR_FBADL_PPDR7 (0x80) /* FB_AD7 */
-+
-+/* Bit definitions and macros for PCLRR_FEC0H */
-+#define MCF_GPIO_PCLRR_FEC0H_PCLRR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */
-+#define MCF_GPIO_PCLRR_FEC0H_PCLRR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */
-+#define MCF_GPIO_PCLRR_FEC0H_PCLRR2 (0x04) /* FEC0_RXDV/FEC0_RMII_CRS_DV */
-+#define MCF_GPIO_PCLRR_FEC0H_PCLRR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */
-+#define MCF_GPIO_PCLRR_FEC0H_PCLRR4 (0x10) /* FEC0_COL / ULPI_DATA7 */
-+#define MCF_GPIO_PCLRR_FEC0H_PCLRR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */
-+#define MCF_GPIO_PCLRR_FEC0H_PCLRR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */
-+#define MCF_GPIO_PCLRR_FEC0H_PCLRR7 (0x80) /* FEC0_TXCLK / FEC0_RMII_REF_CLK */
-+
-+/* Bit definitions and macros for PCLRR_FEC0L */
-+#define MCF_GPIO_PCLRR_FEC0L_PPDR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */
-+#define MCF_GPIO_PCLRR_FEC0L_PPDR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */
-+#define MCF_GPIO_PCLRR_FEC0L_PPDR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */
-+#define MCF_GPIO_PCLRR_FEC0L_PPDR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */
-+#define MCF_GPIO_PCLRR_FEC0L_PPDR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */
-+#define MCF_GPIO_PCLRR_FEC0L_PPDR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */
-+#define MCF_GPIO_PCLRR_FEC0L_PPDR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */
-+#define MCF_GPIO_PCLRR_FEC0L_PPDR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */
-+
-+/* Bit definitions and macros for PCLRR_SSI */
-+#define MCF_GPIO_PCLRR_SSI_PCLRR0 (0x01) /* SSI_TXD / U1TXD */
-+#define MCF_GPIO_PCLRR_SSI_PCLRR1 (0x02) /* SSI_RXD / U1RXD */
-+#define MCF_GPIO_PCLRR_SSI_PCLRR2 (0x04) /* SSI_FS / U1RTS */
-+#define MCF_GPIO_PCLRR_SSI_PCLRR3 (0x08) /* SSI_BCLK / U1CTS */
-+#define MCF_GPIO_PCLRR_SSI_PCLRR4 (0x10) /* SSI_MCLK */
-+
-+/* Bit definitions and macros for PCLRR_FBCTL */
-+#define MCF_GPIO_PCLRR_FBCTL_PCLRR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */
-+#define MCF_GPIO_PCLRR_FBCTL_PCLRR1 (0x02) /* FB_RW */
-+#define MCF_GPIO_PCLRR_FBCTL_PCLRR2 (0x04) /* FB_TA */
-+#define MCF_GPIO_PCLRR_FBCTL_PCLRR3 (0x08) /* FB_OE */
-+
-+/* Bit definitions and macros for PCLRR_BE */
-+#define MCF_GPIO_PCLRR_BE_PCLRR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */
-+#define MCF_GPIO_PCLRR_BE_PCLRR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */
-+#define MCF_GPIO_PCLRR_BE_PCLRR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */
-+#define MCF_GPIO_PCLRR_BE_PCLRR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */
-+
-+/* Bit definitions and macros for PCLRR_CS */
-+#define MCF_GPIO_PCLRR_CS_PCLRR1 (0x02) /* FB_CS1 */
-+#define MCF_GPIO_PCLRR_CS_PCLRR2 (0x04) /* FB_CS2 */
-+#define MCF_GPIO_PCLRR_CS_PCLRR3 (0x08) /* FB_CS3 */
-+
-+/* Bit definitions and macros for PCLRR_DMA */
-+#define MCF_GPIO_PCLRR_DMA_PCLRR0 (0x01) /* DREQ0 */
-+#define MCF_GPIO_PCLRR_DMA_PCLRR1 (0x02) /* DACK0 / DSPI_PCS3 */
-+#define MCF_GPIO_PCLRR_DMA_PCLRR2 (0x04) /* DREQ1 / USB_CLKIN */
-+#define MCF_GPIO_PCLRR_DMA_PCLRR3 (0x08) /* DACK1 / ULPI_DIR */
-+
-+/* Bit definitions and macros for PCLRR_FECI2C */
-+#define MCF_GPIO_PCLRR_FECI2C_PCLRR0 (0x01) /* I2C_SDA / U2RXD */
-+#define MCF_GPIO_PCLRR_FECI2C_PCLRR1 (0x02) /* I2C_SCL / U2TXD */
-+#define MCF_GPIO_PCLRR_FECI2C_PCLRR2 (0x04) /* FEC0_MDIO */
-+#define MCF_GPIO_PCLRR_FECI2C_PCLRR3 (0x08) /* FEC0_MDC */
-+#define MCF_GPIO_PCLRR_FECI2C_PCLRR4 (0x10) /* FEC1_MDIO / ATA_DIOW */
-+#define MCF_GPIO_PCLRR_FECI2C_PCLRR5 (0x20) /* FEC1_MDC / ATA_DIOR */
-+
-+/* Bit definitions and macros for PCLRR_UART */
-+#define MCF_GPIO_PCLRR_UART_PCLRR0 (0x01) /* U1TXD */
-+#define MCF_GPIO_PCLRR_UART_PCLRR1 (0x02) /* U1RXD */
-+#define MCF_GPIO_PCLRR_UART_PCLRR2 (0x04) /* U1RTS */
-+#define MCF_GPIO_PCLRR_UART_PCLRR3 (0x08) /* U0CTS */
-+#define MCF_GPIO_PCLRR_UART_PCLRR4 (0x10) /* U1TXD */
-+#define MCF_GPIO_PCLRR_UART_PCLRR5 (0x20) /* U1RXD */
-+#define MCF_GPIO_PCLRR_UART_PCLRR6 (0x40) /* U1RTS */
-+#define MCF_GPIO_PCLRR_UART_PCLRR7 (0x80) /* U1CTS */
-+
-+/* Bit definitions and macros for PCLRR_DSPI */
-+#define MCF_GPIO_PCLRR_DSPI_PCLRR0 (0x01) /* DSPI_SOUT / SBF_DO */
-+#define MCF_GPIO_PCLRR_DSPI_PCLRR1 (0x02) /* DSPI_SIN / SBF_DI */
-+#define MCF_GPIO_PCLRR_DSPI_PCLRR2 (0x04) /* DSPI_SCK / SBF_CK */
-+#define MCF_GPIO_PCLRR_DSPI_PCLRR3 (0x08) /* DSPI_PCS0/SS */
-+#define MCF_GPIO_PCLRR_DSPI_PCLRR4 (0x10) /* DSPI_PCS1 / SBF_CS */
-+#define MCF_GPIO_PCLRR_DSPI_PCLRR5 (0x20) /* DSPI_PCS2 */
-+#define MCF_GPIO_PCLRR_DSPI_PCLRR6 (0x40) /* DSPI_PCS5/SS */
-+
-+/* Bit definitions and macros for PCLRR_TIMER */
-+#define MCF_GPIO_PCLRR_TIMER_PCLRR0 (0x01) /* T0IN / T0OUT / U2RTS */
-+#define MCF_GPIO_PCLRR_TIMER_PCLRR1 (0x02) /* T1IN / T1OUT / U2CTS */
-+#define MCF_GPIO_PCLRR_TIMER_PCLRR2 (0x04) /* T2IN / T2OUT / U2TXD */
-+#define MCF_GPIO_PCLRR_TIMER_PCLRR3 (0x08) /* T3IN / T3OUT / U2RXD */
-+
-+/* Bit definitions and macros for PCLRR_PCI */
-+#define MCF_GPIO_PCLRR_PCI_PCLRR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */
-+#define MCF_GPIO_PCLRR_PCI_PCLRR1 (0x02) /* PCI_REQ1 */
-+#define MCF_GPIO_PCLRR_PCI_PCLRR2 (0x04) /* PCI_REQ2 */
-+#define MCF_GPIO_PCLRR_PCI_PCLRR3 (0x08) /* PCI_REQ3 / ATA_INTR */
-+#define MCF_GPIO_PCLRR_PCI_PCLRR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */
-+#define MCF_GPIO_PCLRR_PCI_PCLRR5 (0x20) /* PCI_GNT1 / */
-+#define MCF_GPIO_PCLRR_PCI_PCLRR6 (0x40) /* PCI_GNT2 / */
-+#define MCF_GPIO_PCLRR_PCI_PCLRR7 (0x80) /* PCI_GNT3 / ATA_DMACK */
-+
-+/* Bit definitions and macros for PCLRR_USB */
-+#define MCF_GPIO_PCLRR_USB_PCLRR0 (0x01) /* USB_VBUS_OC / ULPI_STP */
-+#define MCF_GPIO_PCLRR_USB_PCLRR1 (0x02) /* USB_VBUS_EN / USB_PULLUP / ULPI_NXT */
-+
-+/* Bit definitions and macros for PCLRR_ATAH */
-+#define MCF_GPIO_PCLRR_ATAH_PCLRR0 (0x01) /* ATA_DA0 */
-+#define MCF_GPIO_PCLRR_ATAH_PCLRR1 (0x02) /* ATA_DA1 */
-+#define MCF_GPIO_PCLRR_ATAH_PCLRR2 (0x04) /* ATA_DA2 */
-+#define MCF_GPIO_PCLRR_ATAH_PCLRR3 (0x08) /* ATA_CS0 */
-+#define MCF_GPIO_PCLRR_ATAH_PCLRR4 (0x10) /* ATA_CS1 */
-+#define MCF_GPIO_PCLRR_ATAH_PCLRR5 (0x20) /* ATA_BUFFER_EN */
-+
-+/* Bit definitions and macros for PCLRR_ATAL */
-+#define MCF_GPIO_PCLRR_ATAL_PCLRR0 (0x01) /* ATA_IORDY */
-+#define MCF_GPIO_PCLRR_ATAL_PCLRR1 (0x02) /* ATA_DMARQ */
-+#define MCF_GPIO_PCLRR_ATAL_PCLRR2 (0x04) /* ATA_RESET */
-+
-+/* Bit definitions and macros for PCLRR_FEC1H */
-+#define MCF_GPIO_PCLRR_FEC1H_PCLRR0 (0x01) /* FEC1_CRS / ATA_DATA6 */
-+#define MCF_GPIO_PCLRR_FEC1H_PCLRR1 (0x02) /* FEC1_RXD0 / FEC1_RMII_RXD0 / ATA_DATA13 */
-+#define MCF_GPIO_PCLRR_FEC1H_PCLRR2 (0x04) /* FEC1_RXDV / FEC1_RMII_CRS_DV / ATA_DATA15 */
-+#define MCF_GPIO_PCLRR_FEC1H_PCLRR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */
-+#define MCF_GPIO_PCLRR_FEC1H_PCLRR4 (0x10) /* FEC1_COL / ATA_DATA7 */
-+#define MCF_GPIO_PCLRR_FEC1H_PCLRR5 (0x20) /* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */
-+#define MCF_GPIO_PCLRR_FEC1H_PCLRR6 (0x40) /* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */
-+#define MCF_GPIO_PCLRR_FEC1H_PCLRR7 (0x80) /* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */
-+
-+/* Bit definitions and macros for PCLRR_FEC1L */
-+#define MCF_GPIO_PCLRR_FEC1L_PCLRR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER / ATA_DATA12 */
-+#define MCF_GPIO_PCLRR_FEC1L_PCLRR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1 / ATA_DATA14 */
-+#define MCF_GPIO_PCLRR_FEC1L_PCLRR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */
-+#define MCF_GPIO_PCLRR_FEC1L_PCLRR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */
-+#define MCF_GPIO_PCLRR_FEC1L_PCLRR4 (0x10) /* FEC1_TXER / ATA_DATA0 */
-+#define MCF_GPIO_PCLRR_FEC1L_PCLRR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1 / ATA_DATA10 */
-+#define MCF_GPIO_PCLRR_FEC1L_PCLRR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */
-+#define MCF_GPIO_PCLRR_FEC1L_PCLRR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */
-+
-+/* Bit definitions and macros for PCLRR_FBADH */
-+#define MCF_GPIO_PCLRR_FBADH_PCLRR0 (0x01) /* FB_AD24 */
-+#define MCF_GPIO_PCLRR_FBADH_PCLRR1 (0x02) /* FB_AD25 */
-+#define MCF_GPIO_PCLRR_FBADH_PCLRR2 (0x04) /* FB_AD26 */
-+#define MCF_GPIO_PCLRR_FBADH_PCLRR3 (0x08) /* FB_AD27 */
-+#define MCF_GPIO_PCLRR_FBADH_PCLRR4 (0x10) /* FB_AD28 */
-+#define MCF_GPIO_PCLRR_FBADH_PCLRR5 (0x20) /* FB_AD29 */
-+#define MCF_GPIO_PCLRR_FBADH_PCLRR6 (0x40) /* FB_AD30 */
-+#define MCF_GPIO_PCLRR_FBADH_PCLRR7 (0x80) /* FB_AD31 */
-+
-+/* Bit definitions and macros for PCLRR_FBADMH */
-+#define MCF_GPIO_PCLRR_FBADMH_PCLRR0 (0x01) /* FB_AD16 */
-+#define MCF_GPIO_PCLRR_FBADMH_PCLRR1 (0x02) /* FB_AD17 */
-+#define MCF_GPIO_PCLRR_FBADMH_PCLRR2 (0x04) /* FB_AD18 */
-+#define MCF_GPIO_PCLRR_FBADMH_PCLRR3 (0x08) /* FB_AD19 */
-+#define MCF_GPIO_PCLRR_FBADMH_PCLRR4 (0x10) /* FB_AD20 */
-+#define MCF_GPIO_PCLRR_FBADMH_PCLRR5 (0x20) /* FB_AD21 */
-+#define MCF_GPIO_PCLRR_FBADMH_PCLRR6 (0x40) /* FB_AD22 */
-+#define MCF_GPIO_PCLRR_FBADMH_PCLRR7 (0x80) /* FB_AD23 */
-+
-+/* Bit definitions and macros for PCLRR_FBADML */
-+#define MCF_GPIO_PCLRR_FBADML_PCLRR0 (0x01) /* FB_AD8 */
-+#define MCF_GPIO_PCLRR_FBADML_PCLRR1 (0x02) /* FB_AD9 */
-+#define MCF_GPIO_PCLRR_FBADML_PCLRR2 (0x04) /* FB_AD10 */
-+#define MCF_GPIO_PCLRR_FBADML_PCLRR3 (0x08) /* FB_AD11 */
-+#define MCF_GPIO_PCLRR_FBADML_PCLRR4 (0x10) /* FB_AD12 */
-+#define MCF_GPIO_PCLRR_FBADML_PCLRR5 (0x20) /* FB_AD13 */
-+#define MCF_GPIO_PCLRR_FBADML_PCLRR6 (0x40) /* FB_AD14 */
-+#define MCF_GPIO_PCLRR_FBADML_PCLRR7 (0x80) /* FB_AD15 */
-+
-+/* Bit definitions and macros for PCLRR_FBADL */
-+#define MCF_GPIO_PCLRR_FBADL_PCLRR0 (0x01) /* FB_AD0 */
-+#define MCF_GPIO_PCLRR_FBADL_PCLRR1 (0x02) /* FB_AD1 */
-+#define MCF_GPIO_PCLRR_FBADL_PCLRR2 (0x04) /* FB_AD2 */
-+#define MCF_GPIO_PCLRR_FBADL_PCLRR3 (0x08) /* FB_AD3 */
-+#define MCF_GPIO_PCLRR_FBADL_PCLRR4 (0x10) /* FB_AD4 */
-+#define MCF_GPIO_PCLRR_FBADL_PCLRR5 (0x20) /* FB_AD5 */
-+#define MCF_GPIO_PCLRR_FBADL_PCLRR6 (0x40) /* FB_AD6 */
-+#define MCF_GPIO_PCLRR_FBADL_PCLRR7 (0x80) /* FB_AD7 */
-+
-+/* Bit definitions and macros for PAR_FEC */
-+#define MCF_GPIO_PAR_FEC_FEC0(x) (((x)&0x07))
-+#define MCF_GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4)
-+#define MCF_GPIO_PAR_FEC_FEC1_MASK (0x8F)
-+#define MCF_GPIO_PAR_FEC_FEC1_MII (0x70)
-+#define MCF_GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30)
-+#define MCF_GPIO_PAR_FEC_FEC1_RMII_ATA (0x20)
-+#define MCF_GPIO_PAR_FEC_FEC1_ATA (0x10)
-+#define MCF_GPIO_PAR_FEC_FEC1_GPIO (0x00)
-+#define MCF_GPIO_PAR_FEC_FEC0_MASK (0xF8)
-+#define MCF_GPIO_PAR_FEC_FEC0_MII (0x07)
-+#define MCF_GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03)
-+#define MCF_GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02)
-+#define MCF_GPIO_PAR_FEC_FEC0_ULPI (0x01)
-+#define MCF_GPIO_PAR_FEC_FEC0_GPIO (0x00)
-+
-+/* Bit definitions and macros for PAR_DMA */
-+#define MCF_GPIO_PAR_DMA_DREQ0 (0x01)
-+#define MCF_GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2)
-+#define MCF_GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4)
-+#define MCF_GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6)
-+#define MCF_GPIO_PAR_DMA_DACK1_MASK (0x3F)
-+#define MCF_GPIO_PAR_DMA_DACK1_DACK1 (0xC0)
-+#define MCF_GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40)
-+#define MCF_GPIO_PAR_DMA_DACK1_GPIO (0x00)
-+#define MCF_GPIO_PAR_DMA_DREQ1_MASK (0xCF)
-+#define MCF_GPIO_PAR_DMA_DREQ1_DREQ1 (0x30)
-+#define MCF_GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10)
-+#define MCF_GPIO_PAR_DMA_DREQ1_GPIO (0x00)
-+#define MCF_GPIO_PAR_DMA_DACK0_MASK (0xF3)
-+#define MCF_GPIO_PAR_DMA_DACK0_DACK1 (0x0C)
-+#define MCF_GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04)
-+#define MCF_GPIO_PAR_DMA_DACK0_GPIO (0x00)
-+#define MCF_GPIO_PAR_DMA_DREQ0_DREQ0 (0x01)
-+#define MCF_GPIO_PAR_DMA_DREQ0_GPIO (0x00)
-+
-+/* Bit definitions and macros for PAR_FBCTL */
-+#define MCF_GPIO_PAR_FBCTL_TS(x) (((x)&0x03)<<3)
-+#define MCF_GPIO_PAR_FBCTL_RW (0x20)
-+#define MCF_GPIO_PAR_FBCTL_TA (0x40)
-+#define MCF_GPIO_PAR_FBCTL_OE (0x80)
-+#define MCF_GPIO_PAR_FBCTL_OE_OE (0x80)
-+#define MCF_GPIO_PAR_FBCTL_OE_GPIO (0x00)
-+#define MCF_GPIO_PAR_FBCTL_TA_TA (0x40)
-+#define MCF_GPIO_PAR_FBCTL_TA_GPIO (0x00)
-+#define MCF_GPIO_PAR_FBCTL_RW_RW (0x20)
-+#define MCF_GPIO_PAR_FBCTL_RW_GPIO (0x00)
-+#define MCF_GPIO_PAR_FBCTL_TS_MASK (0xE7)
-+#define MCF_GPIO_PAR_FBCTL_TS_TS (0x18)
-+#define MCF_GPIO_PAR_FBCTL_TS_ALE (0x10)
-+#define MCF_GPIO_PAR_FBCTL_TS_TBST (0x08)
-+#define MCF_GPIO_PAR_FBCTL_TS_GPIO (0x80)
-+
-+/* Bit definitions and macros for PAR_DSPI */
-+#define MCF_GPIO_PAR_DSPI_SCK (0x01)
-+#define MCF_GPIO_PAR_DSPI_SOUT (0x02)
-+#define MCF_GPIO_PAR_DSPI_SIN (0x04)
-+#define MCF_GPIO_PAR_DSPI_PCS0 (0x08)
-+#define MCF_GPIO_PAR_DSPI_PCS1 (0x10)
-+#define MCF_GPIO_PAR_DSPI_PCS2 (0x20)
-+#define MCF_GPIO_PAR_DSPI_PCS5 (0x40)
-+#define MCF_GPIO_PAR_DSPI_PCS5_PCS5 (0x40)
-+#define MCF_GPIO_PAR_DSPI_PCS5_GPIO (0x00)
-+#define MCF_GPIO_PAR_DSPI_PCS2_PCS2 (0x20)
-+#define MCF_GPIO_PAR_DSPI_PCS2_GPIO (0x00)
-+#define MCF_GPIO_PAR_DSPI_PCS1_PCS1 (0x10)
-+#define MCF_GPIO_PAR_DSPI_PCS1_GPIO (0x00)
-+#define MCF_GPIO_PAR_DSPI_PCS0_PCS0 (0x08)
-+#define MCF_GPIO_PAR_DSPI_PCS0_GPIO (0x00)
-+#define MCF_GPIO_PAR_DSPI_SIN_SIN (0x04)
-+#define MCF_GPIO_PAR_DSPI_SIN_GPIO (0x00)
-+#define MCF_GPIO_PAR_DSPI_SOUT_SOUT (0x02)
-+#define MCF_GPIO_PAR_DSPI_SOUT_GPIO (0x00)
-+#define MCF_GPIO_PAR_DSPI_SCK_SCK (0x01)
-+#define MCF_GPIO_PAR_DSPI_SCK_GPIO (0x00)
-+
-+/* Bit definitions and macros for PAR_BE */
-+#define MCF_GPIO_PAR_BE_BE0 (0x01)
-+#define MCF_GPIO_PAR_BE_BE1 (0x04)
-+#define MCF_GPIO_PAR_BE_BE2(x) (((x)&0x03)<<4)
-+#define MCF_GPIO_PAR_BE_BE3(x) (((x)&0x03)<<6)
-+#define MCF_GPIO_PAR_BE_BE3_MASK (0x3F)
-+#define MCF_GPIO_PAR_BE_BE3_BE3 (0xC0)
-+#define MCF_GPIO_PAR_BE_BE3_TSIZ1 (0x80)
-+#define MCF_GPIO_PAR_BE_BE3_GPIO (0x00)
-+#define MCF_GPIO_PAR_BE_BE2_MASK (0xCF)
-+#define MCF_GPIO_PAR_BE_BE2_BE2 (0x30)
-+#define MCF_GPIO_PAR_BE_BE2_TSIZ0 (0x20)
-+#define MCF_GPIO_PAR_BE_BE2_GPIO (0x00)
-+#define MCF_GPIO_PAR_BE_BE1_BE1 (0x04)
-+#define MCF_GPIO_PAR_BE_BE1_GPIO (0x00)
-+#define MCF_GPIO_PAR_BE_BE0_BE0 (0x01)
-+#define MCF_GPIO_PAR_BE_BE0_GPIO (0x00)
-+
-+/* Bit definitions and macros for PAR_CS */
-+#define MCF_GPIO_PAR_CS_CS1 (0x02)
-+#define MCF_GPIO_PAR_CS_CS2 (0x04)
-+#define MCF_GPIO_PAR_CS_CS3 (0x08)
-+#define MCF_GPIO_PAR_CS_CS3_CS3 (0x08)
-+#define MCF_GPIO_PAR_CS_CS3_GPIO (0x00)
-+#define MCF_GPIO_PAR_CS_CS2_CS2 (0x04)
-+#define MCF_GPIO_PAR_CS_CS2_GPIO (0x00)
-+#define MCF_GPIO_PAR_CS_CS1_CS1 (0x02)
-+#define MCF_GPIO_PAR_CS_CS1_GPIO (0x00)
-+
-+/* Bit definitions and macros for PAR_TIMER */
-+#define MCF_GPIO_PAR_TIMER_T0IN(x) (((x)&0x03))
-+#define MCF_GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2)
-+#define MCF_GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4)
-+#define MCF_GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6)
-+#define MCF_GPIO_PAR_TIMER_T3IN_MASK (0x3F)
-+#define MCF_GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
-+#define MCF_GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
-+#define MCF_GPIO_PAR_TIMER_T3IN_U2RXD (0x40)
-+#define MCF_GPIO_PAR_TIMER_T3IN_GPIO (0x00)
-+#define MCF_GPIO_PAR_TIMER_T2IN_MASK (0xCF)
-+#define MCF_GPIO_PAR_TIMER_T2IN_T2IN (0x30)
-+#define MCF_GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
-+#define MCF_GPIO_PAR_TIMER_T2IN_U2TXD (0x10)
-+#define MCF_GPIO_PAR_TIMER_T2IN_GPIO (0x00)
-+#define MCF_GPIO_PAR_TIMER_T1IN_MASK (0xF3)
-+#define MCF_GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
-+#define MCF_GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
-+#define MCF_GPIO_PAR_TIMER_T1IN_U2CTS (0x04)
-+#define MCF_GPIO_PAR_TIMER_T1IN_GPIO (0x00)
-+#define MCF_GPIO_PAR_TIMER_T0IN_MASK (0xFC)
-+#define MCF_GPIO_PAR_TIMER_T0IN_T0IN (0x03)
-+#define MCF_GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
-+#define MCF_GPIO_PAR_TIMER_T0IN_U2RTS (0x01)
-+#define MCF_GPIO_PAR_TIMER_T0IN_GPIO (0x00)
-+
-+/* Bit definitions and macros for PAR_USB */
-+#define MCF_GPIO_PAR_USB_VBUSOC(x) (((x)&0x03))
-+#define MCF_GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2)
-+#define MCF_GPIO_PAR_USB_VBUSEN_MASK (0xF3)
-+#define MCF_GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C)
-+#define MCF_GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08)
-+#define MCF_GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04)
-+#define MCF_GPIO_PAR_USB_VBUSEN_GPIO (0x00)
-+#define MCF_GPIO_PAR_USB_VBUSOC_MASK (0xFC)
-+#define MCF_GPIO_PAR_USB_VBUSOC_VBUSOC (0x03)
-+#define MCF_GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01)
-+#define MCF_GPIO_PAR_USB_VBUSOC_GPIO (0x00)
-+
-+/* Bit definitions and macros for PAR_UART */
-+#define MCF_GPIO_PAR_UART_U0TXD (0x01)
-+#define MCF_GPIO_PAR_UART_U0RXD (0x02)
-+#define MCF_GPIO_PAR_UART_U0RTS (0x04)
-+#define MCF_GPIO_PAR_UART_U0CTS (0x08)
-+#define MCF_GPIO_PAR_UART_U1TXD (0x10)
-+#define MCF_GPIO_PAR_UART_U1RXD (0x20)
-+#define MCF_GPIO_PAR_UART_U1RTS (0x40)
-+#define MCF_GPIO_PAR_UART_U1CTS (0x80)
-+#define MCF_GPIO_PAR_UART_U1CTS_U1CTS (0x80)
-+#define MCF_GPIO_PAR_UART_U1CTS_GPIO (0x00)
-+#define MCF_GPIO_PAR_UART_U1RTS_U1RTS (0x40)
-+#define MCF_GPIO_PAR_UART_U1RTS_GPIO (0x00)
-+#define MCF_GPIO_PAR_UART_U1RXD_U1RXD (0x20)
-+#define MCF_GPIO_PAR_UART_U1RXD_GPIO (0x00)
-+#define MCF_GPIO_PAR_UART_U1TXD_U1TXD (0x10)
-+#define MCF_GPIO_PAR_UART_U1TXD_GPIO (0x00)
-+#define MCF_GPIO_PAR_UART_U0CTS_U0CTS (0x08)
-+#define MCF_GPIO_PAR_UART_U0CTS_GPIO (0x00)
-+#define MCF_GPIO_PAR_UART_U0RTS_U0RTS (0x04)
-+#define MCF_GPIO_PAR_UART_U0RTS_GPIO (0x00)
-+#define MCF_GPIO_PAR_UART_U0RXD_U0RXD (0x02)
-+#define MCF_GPIO_PAR_UART_U0RXD_GPIO (0x00)
-+#define MCF_GPIO_PAR_UART_U0TXD_U0TXD (0x01)
-+#define MCF_GPIO_PAR_UART_U0TXD_GPIO (0x00)
-+
-+/* Bit definitions and macros for PAR_FECI2C */
-+#define MCF_GPIO_PAR_FECI2C_SDA(x) (((x)&0x0003))
-+#define MCF_GPIO_PAR_FECI2C_SCL(x) (((x)&0x0003)<<2)
-+#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x0003))
-+#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x0003)<<2)
-+#define MCF_GPIO_PAR_FECI2C_MDIO0 (0x0010)
-+#define MCF_GPIO_PAR_FECI2C_MDC0 (0x0040)
-+#define MCF_GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8)
-+#define MCF_GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10)
-+#define MCF_GPIO_PAR_FECI2C_MDC1_MASK (0xF3FF)
-+#define MCF_GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00)
-+#define MCF_GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800)
-+#define MCF_GPIO_PAR_FECI2C_MDC1_GPIO (0x0000)
-+#define MCF_GPIO_PAR_FECI2C_MDIO1_MASK (0xFCFF)
-+#define MCF_GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300)
-+#define MCF_GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200)
-+#define MCF_GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000)
-+#define MCF_GPIO_PAR_FECI2C_MDC0_MDC0 (0x0040)
-+#define MCF_GPIO_PAR_FECI2C_MDC0_GPIO (0x0000)
-+#define MCF_GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010)
-+#define MCF_GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000)
-+#define MCF_GPIO_PAR_FECI2C_SCL_MASK (0xFFF3)
-+#define MCF_GPIO_PAR_FECI2C_SCL_SCL (0x000C)
-+#define MCF_GPIO_PAR_FECI2C_SCL_U2TXD (0x0004)
-+#define MCF_GPIO_PAR_FECI2C_SCL_GPIO (0x0000)
-+#define MCF_GPIO_PAR_FECI2C_SDA_MASK (0xFFFC)
-+#define MCF_GPIO_PAR_FECI2C_SDA_SDA (0x0003)
-+#define MCF_GPIO_PAR_FECI2C_SDA_U2RXD (0x0001)
-+#define MCF_GPIO_PAR_FECI2C_SDA_GPIO (0x0000)
-+
-+/* Bit definitions and macros for PAR_SSI */
-+#define MCF_GPIO_PAR_SSI_MCLK (0x0001)
-+#define MCF_GPIO_PAR_SSI_STXD(x) (((x)&0x0003)<<2)
-+#define MCF_GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4)
-+#define MCF_GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6)
-+#define MCF_GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8)
-+#define MCF_GPIO_PAR_SSI_BCLK_MASK (0xFCFF)
-+#define MCF_GPIO_PAR_SSI_BCLK_BCLK (0x0300)
-+#define MCF_GPIO_PAR_SSI_BCLK_U1CTS (0x0200)
-+#define MCF_GPIO_PAR_SSI_BCLK_GPIO (0x0000)
-+#define MCF_GPIO_PAR_SSI_FS_MASK (0xFF3F)
-+#define MCF_GPIO_PAR_SSI_FS_FS (0x00C0)
-+#define MCF_GPIO_PAR_SSI_FS_U1RTS (0x0080)
-+#define MCF_GPIO_PAR_SSI_FS_GPIO (0x0000)
-+#define MCF_GPIO_PAR_SSI_SRXD_MASK (0xFFCF)
-+#define MCF_GPIO_PAR_SSI_SRXD_SRXD (0x0030)
-+#define MCF_GPIO_PAR_SSI_SRXD_U1RXD (0x0020)
-+#define MCF_GPIO_PAR_SSI_SRXD_GPIO (0x0000)
-+#define MCF_GPIO_PAR_SSI_STXD_MASK (0xFFF3)
-+#define MCF_GPIO_PAR_SSI_STXD_STXD (0x000C)
-+#define MCF_GPIO_PAR_SSI_STXD_U1TXD (0x0008)
-+#define MCF_GPIO_PAR_SSI_STXD_GPIO (0x0000)
-+#define MCF_GPIO_PAR_SSI_MCLK_MCLK (0x0001)
-+#define MCF_GPIO_PAR_SSI_MCLK_GPIO (0x0000)
-+
-+/* Bit definitions and macros for PAR_ATA */
-+#define MCF_GPIO_PAR_ATA_IORDY (0x0001)
-+#define MCF_GPIO_PAR_ATA_DMARQ (0x0002)
-+#define MCF_GPIO_PAR_ATA_RESET (0x0004)
-+#define MCF_GPIO_PAR_ATA_DA0 (0x0020)
-+#define MCF_GPIO_PAR_ATA_DA1 (0x0040)
-+#define MCF_GPIO_PAR_ATA_DA2 (0x0080)
-+#define MCF_GPIO_PAR_ATA_CS0 (0x0100)
-+#define MCF_GPIO_PAR_ATA_CS1 (0x0200)
-+#define MCF_GPIO_PAR_ATA_BUFEN (0x0400)
-+#define MCF_GPIO_PAR_ATA_BUFEN_BUFEN (0x0400)
-+#define MCF_GPIO_PAR_ATA_BUFEN_GPIO (0x0000)
-+#define MCF_GPIO_PAR_ATA_CS1_CS1 (0x0200)
-+#define MCF_GPIO_PAR_ATA_CS1_GPIO (0x0000)
-+#define MCF_GPIO_PAR_ATA_CS0_CS0 (0x0100)
-+#define MCF_GPIO_PAR_ATA_CS0_GPIO (0x0000)
-+#define MCF_GPIO_PAR_ATA_DA2_DA2 (0x0080)
-+#define MCF_GPIO_PAR_ATA_DA2_GPIO (0x0000)
-+#define MCF_GPIO_PAR_ATA_DA1_DA1 (0x0040)
-+#define MCF_GPIO_PAR_ATA_DA1_GPIO (0x0000)
-+#define MCF_GPIO_PAR_ATA_DA0_DA0 (0x0020)
-+#define MCF_GPIO_PAR_ATA_DA0_GPIO (0x0000)
-+#define MCF_GPIO_PAR_ATA_RESET_RESET (0x0004)
-+#define MCF_GPIO_PAR_ATA_RESET_GPIO (0x0000)
-+#define MCF_GPIO_PAR_ATA_DMARQ_DMARQ (0x0002)
-+#define MCF_GPIO_PAR_ATA_DMARQ_GPIO (0x0000)
-+#define MCF_GPIO_PAR_ATA_IORDY_IORDY (0x0001)
-+#define MCF_GPIO_PAR_ATA_IORDY_GPIO (0x0000)
-+
-+/* Bit definitions and macros for PAR_IRQ */
-+#define MCF_GPIO_PAR_IRQ_IRQ1 (0x02)
-+#define MCF_GPIO_PAR_IRQ_IRQ4 (0x10)
-+#define MCF_GPIO_PAR_IRQ_IRQ4_IRQ4 (0x10)
-+#define MCF_GPIO_PAR_IRQ_IRQ4_GPIO (0x00)
-+#define MCF_GPIO_PAR_IRQ_IRQ1_IRQ1 (0x02)
-+#define MCF_GPIO_PAR_IRQ_IRQ1_GPIO (0x00)
-+
-+/* Bit definitions and macros for PAR_PCI */
-+#define MCF_GPIO_PAR_PCI_REQ0 (0x0001)
-+#define MCF_GPIO_PAR_PCI_REQ1 (0x0004)
-+#define MCF_GPIO_PAR_PCI_REQ2 (0x0010)
-+#define MCF_GPIO_PAR_PCI_REQ3(x) (((x)&0x0003)<<6)
-+#define MCF_GPIO_PAR_PCI_GNT0 (0x0100)
-+#define MCF_GPIO_PAR_PCI_GNT1 (0x0400)
-+#define MCF_GPIO_PAR_PCI_GNT2 (0x1000)
-+#define MCF_GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14)
-+#define MCF_GPIO_PAR_PCI_GNT3_MASK (0x3FFF)
-+#define MCF_GPIO_PAR_PCI_GNT3_GNT3 (0xC000)
-+#define MCF_GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000)
-+#define MCF_GPIO_PAR_PCI_GNT3_GPIO (0x0000)
-+#define MCF_GPIO_PAR_PCI_GNT2_GNT2 (0x1000)
-+#define MCF_GPIO_PAR_PCI_GNT2_GPIO (0x0000)
-+#define MCF_GPIO_PAR_PCI_GNT1_GNT1 (0x0400)
-+#define MCF_GPIO_PAR_PCI_GNT1_GPIO (0x0000)
-+#define MCF_GPIO_PAR_PCI_GNT0_GNT0 (0x0100)
-+#define MCF_GPIO_PAR_PCI_GNT0_GPIO (0x0000)
-+#define MCF_GPIO_PAR_PCI_REQ3_MASK (0xFF3F)
-+#define MCF_GPIO_PAR_PCI_REQ3_REQ3 (0x00C0)
-+#define MCF_GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080)
-+#define MCF_GPIO_PAR_PCI_REQ3_GPIO (0x0000)
-+#define MCF_GPIO_PAR_PCI_REQ2_REQ2 (0x0010)
-+#define MCF_GPIO_PAR_PCI_REQ2_GPIO (0x0000)
-+#define MCF_GPIO_PAR_PCI_REQ1_REQ1 (0x0040)
-+#define MCF_GPIO_PAR_PCI_REQ1_GPIO (0x0000)
-+#define MCF_GPIO_PAR_PCI_REQ0_REQ0 (0x0001)
-+#define MCF_GPIO_PAR_PCI_REQ0_GPIO (0x0000)
-+
-+/* Bit definitions and macros for MSCR_SDRAM */
-+#define MCF_GPIO_MSCR_SDRAM_SDCTL(x) (((x)&0x03))
-+#define MCF_GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2)
-+#define MCF_GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4)
-+#define MCF_GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6)
-+#define MCF_GPIO_MSCR_SDRAM_SDDATA_MASK (0x3F)
-+#define MCF_GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0)
-+#define MCF_GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80)
-+#define MCF_GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40)
-+#define MCF_GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00)
-+#define MCF_GPIO_MSCR_SDRAM_SDDQS_MASK (0xCF)
-+#define MCF_GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30)
-+#define MCF_GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20)
-+#define MCF_GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10)
-+#define MCF_GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00)
-+#define MCF_GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3)
-+#define MCF_GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C)
-+#define MCF_GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08)
-+#define MCF_GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04)
-+#define MCF_GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00)
-+#define MCF_GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC)
-+#define MCF_GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03)
-+#define MCF_GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02)
-+#define MCF_GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01)
-+#define MCF_GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR (0x00)
-+
-+/* Bit definitions and macros for MSCR_PCI */
-+#define MCF_GPIO_MSCR_PCI_PCI (0x01)
-+#define MCF_GPIO_MSCR_PCI_PCI_HI_66MHZ (0x01)
-+#define MCF_GPIO_MSCR_PCI_PCI_LO_33MHZ (0x00)
-+
-+/* Bit definitions and macros for DSCR_I2C */
-+#define MCF_GPIO_DSCR_I2C_I2C(x) (((x)&0x03))
-+#define MCF_GPIO_DSCR_I2C_I2C_LOAD_50PF (0x03)
-+#define MCF_GPIO_DSCR_I2C_I2C_LOAD_30PF (0x02)
-+#define MCF_GPIO_DSCR_I2C_I2C_LOAD_20PF (0x01)
-+#define MCF_GPIO_DSCR_I2C_I2C_LOAD_10PF (0x00)
-+
-+/* Bit definitions and macros for DSCR_FLEXBUS */
-+#define MCF_GPIO_DSCR_FLEXBUS_FBADL(x) (((x)&0x03))
-+#define MCF_GPIO_DSCR_FLEXBUS_FBADH(x) (((x)&0x03)<<2)
-+#define MCF_GPIO_DSCR_FLEXBUS_FBCTL(x) (((x)&0x03)<<4)
-+#define MCF_GPIO_DSCR_FLEXBUS_FBCLK(x) (((x)&0x03)<<6)
-+#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF (0xC0)
-+#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30P (0x80)
-+#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF (0x40)
-+#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF (0x00)
-+#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF (0x30)
-+#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF (0x20)
-+#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF (0x10)
-+#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF (0x00)
-+#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF (0x0C)
-+#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF (0x08)
-+#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF (0x04)
-+#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF (0x00)
-+#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF (0x03)
-+#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF (0x02)
-+#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF (0x01)
-+#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF (0x00)
-+
-+/* Bit definitions and macros for DSCR_FEC */
-+#define MCF_GPIO_DSCR_FEC_FEC0(x) (((x)&0x03))
-+#define MCF_GPIO_DSCR_FEC_FEC1(x) (((x)&0x03)<<2)
-+#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_50PF (0x0C)
-+#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_30PF (0x08)
-+#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_20PF (0x04)
-+#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_10PF (0x00)
-+#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_50PF (0x03)
-+#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_30PF (0x02)
-+#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_20PF (0x01)
-+#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_10PF (0x00)
-+
-+/* Bit definitions and macros for DSCR_UART */
-+#define MCF_GPIO_DSCR_UART_UART0(x) (((x)&0x03))
-+#define MCF_GPIO_DSCR_UART_UART1(x) (((x)&0x03)<<2)
-+#define MCF_GPIO_DSCR_UART_UART1_LOAD_50PF (0x0C)
-+#define MCF_GPIO_DSCR_UART_UART1_LOAD_30PF (0x08)
-+#define MCF_GPIO_DSCR_UART_UART1_LOAD_20PF (0x04)
-+#define MCF_GPIO_DSCR_UART_UART1_LOAD_10PF (0x00)
-+#define MCF_GPIO_DSCR_UART_UART0_LOAD_50PF (0x03)
-+#define MCF_GPIO_DSCR_UART_UART0_LOAD_30PF (0x02)
-+#define MCF_GPIO_DSCR_UART_UART0_LOAD_20PF (0x01)
-+#define MCF_GPIO_DSCR_UART_UART0_LOAD_10PF (0x00)
-+
-+/* Bit definitions and macros for DSCR_DSPI */
-+#define MCF_GPIO_DSCR_DSPI_DSPI(x) (((x)&0x03))
-+#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_50PF (0x03)
-+#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_30PF (0x02)
-+#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_20PF (0x01)
-+#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_10PF (0x00)
-+
-+/* Bit definitions and macros for DSCR_TIMER */
-+#define MCF_GPIO_DSCR_TIMER_TIMER(x) (((x)&0x03))
-+#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_50PF (0x03)
-+#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_30PF (0x02)
-+#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_20PF (0x01)
-+#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_10PF (0x00)
-+
-+/* Bit definitions and macros for DSCR_SSI */
-+#define MCF_GPIO_DSCR_SSI_SSI(x) (((x)&0x03))
-+#define MCF_GPIO_DSCR_SSI_SSI_LOAD_50PF (0x03)
-+#define MCF_GPIO_DSCR_SSI_SSI_LOAD_30PF (0x02)
-+#define MCF_GPIO_DSCR_SSI_SSI_LOAD_20PF (0x01)
-+#define MCF_GPIO_DSCR_SSI_SSI_LOAD_10PF (0x00)
-+
-+/* Bit definitions and macros for DSCR_DMA */
-+#define MCF_GPIO_DSCR_DMA_DMA(x) (((x)&0x03))
-+#define MCF_GPIO_DSCR_DMA_DMA_LOAD_50PF (0x03)
-+#define MCF_GPIO_DSCR_DMA_DMA_LOAD_30PF (0x02)
-+#define MCF_GPIO_DSCR_DMA_DMA_LOAD_20PF (0x01)
-+#define MCF_GPIO_DSCR_DMA_DMA_LOAD_10PF (0x00)
-+
-+/* Bit definitions and macros for DSCR_DEBUG */
-+#define MCF_GPIO_DSCR_DEBUG_DEBUG(x) (((x)&0x03))
-+#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF (0x03)
-+#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF (0x02)
-+#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF (0x01)
-+#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF (0x00)
-+
-+/* Bit definitions and macros for DSCR_RESET */
-+#define MCF_GPIO_DSCR_RESET_RESET(x) (((x)&0x03))
-+#define MCF_GPIO_DSCR_RESET_RESET_LOAD_50PF (0x03)
-+#define MCF_GPIO_DSCR_RESET_RESET_LOAD_30PF (0x02)
-+#define MCF_GPIO_DSCR_RESET_RESET_LOAD_20PF (0x01)
-+#define MCF_GPIO_DSCR_RESET_RESET_LOAD_10PF (0x00)
-+
-+/* Bit definitions and macros for DSCR_IRQ */
-+#define MCF_GPIO_DSCR_IRQ_IRQ(x) (((x)&0x03))
-+#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_50PF (0x03)
-+#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_30PF (0x02)
-+#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_20PF (0x01)
-+#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_10PF (0x00)
-+
-+/* Bit definitions and macros for DSCR_USB */
-+#define MCF_GPIO_DSCR_USB_USB(x) (((x)&0x03))
-+#define MCF_GPIO_DSCR_USB_USB_LOAD_50PF (0x03)
-+#define MCF_GPIO_DSCR_USB_USB_LOAD_30PF (0x02)
-+#define MCF_GPIO_DSCR_USB_USB_LOAD_20PF (0x01)
-+#define MCF_GPIO_DSCR_USB_USB_LOAD_10PF (0x00)
-+
-+/* Bit definitions and macros for DSCR_ATA */
-+#define MCF_GPIO_DSCR_ATA_ATA(x) (((x)&0x03))
-+#define MCF_GPIO_DSCR_ATA_ATA_LOAD_50PF (0x03)
-+#define MCF_GPIO_DSCR_ATA_ATA_LOAD_30PF (0x02)
-+#define MCF_GPIO_DSCR_ATA_ATA_LOAD_20PF (0x01)
-+#define MCF_GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00)
-+
-+/********************************************************************/
-+
-+#endif /* __MCF5445X_GPIO_H__ */
---- /dev/null
-+++ b/include/asm-m68k/mcf5445x_i2c.h
-@@ -0,0 +1,39 @@
-+/*
-+ * Matt Waddel Matt.Waddel@freescale.com
-+ *
-+ * Copyright Freescale Semiconductor, Inc. 2007
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+
-+#ifndef __MCF5445X_I2C_H__
-+#define __MCF5445X_I2C_H__
-+
-+/*********************************************************************
-+*
-+* I2C Module (I2C)
-+*
-+*********************************************************************/
-+
-+/* Register read/write macros */
-+#define MCF_I2C_I2ADR (volatile u8 *)(0xFC058000)
-+#define MCF_I2C_I2FDR (volatile u8 *)(0xFC058004)
-+#define MCF_I2C_I2CR (volatile u8 *)(0xFC058008)
-+#define MCF_I2C_I2SR (volatile u8 *)(0xFC05800C)
-+#define MCF_I2C_I2DR (volatile u8 *)(0xFC058010)
-+
-+/* Bit definitions and macros for I2AR */
-+#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1)
-+
-+/* Bit definitions and macros for I2FDR */
-+#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F))
-+
-+/* Bit definitions and macros for I2DR */
-+#define MCF_I2C_I2DR_DATA(x) (x)
-+
-+/********************************************************************/
-+
-+#endif /* __MCF5445X_I2C_H__ */
---- /dev/null
-+++ b/include/asm-m68k/mcf5445x_intc.h
-@@ -0,0 +1,724 @@
-+/*
-+ * Matt Waddel Matt.Waddel@freescale.com
-+ *
-+ * Copyright Freescale Semiconductor, Inc. 2007
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+
-+#ifndef __MCF5445X_INTC_H__
-+#define __MCF5445X_INTC_H__
-+
-+/*********************************************************************
-+*
-+* Interrupt Controller (INTC)
-+*
-+*********************************************************************/
-+
-+/* Register read/write macros */
-+#define MCF_INTC0_IPRH MCF_REG32(0xFC048000)
-+#define MCF_INTC0_IPRL MCF_REG32(0xFC048004)
-+#define MCF_INTC0_IMRH MCF_REG32(0xFC048008)
-+#define MCF_INTC0_IMRL MCF_REG32(0xFC04800C)
-+#define MCF_INTC0_INTFRCH MCF_REG32(0xFC048010)
-+#define MCF_INTC0_INTFRCL MCF_REG32(0xFC048014)
-+#define MCF_INTC0_ICONFIG MCF_REG16(0xFC04801A)
-+#define MCF_INTC0_SIMR MCF_REG08(0xFC04801C)
-+#define MCF_INTC0_CIMR MCF_REG08(0xFC04801D)
-+#define MCF_INTC0_CLMASK MCF_REG08(0xFC04801E)
-+#define MCF_INTC0_SLMASK MCF_REG08(0xFC04801F)
-+#define MCF_INTC0_ICR1 MCF_REG08(0xFC048041)
-+#define MCF_INTC0_ICR2 MCF_REG08(0xFC048042)
-+#define MCF_INTC0_ICR3 MCF_REG08(0xFC048043)
-+#define MCF_INTC0_ICR4 MCF_REG08(0xFC048044)
-+#define MCF_INTC0_ICR5 MCF_REG08(0xFC048045)
-+#define MCF_INTC0_ICR6 MCF_REG08(0xFC048046)
-+#define MCF_INTC0_ICR7 MCF_REG08(0xFC048047)
-+#define MCF_INTC0_ICR8 MCF_REG08(0xFC048048)
-+#define MCF_INTC0_ICR9 MCF_REG08(0xFC048049)
-+#define MCF_INTC0_ICR10 MCF_REG08(0xFC04804A)
-+#define MCF_INTC0_ICR11 MCF_REG08(0xFC04804B)
-+#define MCF_INTC0_ICR12 MCF_REG08(0xFC04804C)
-+#define MCF_INTC0_ICR13 MCF_REG08(0xFC04804D)
-+#define MCF_INTC0_ICR14 MCF_REG08(0xFC04804E)
-+#define MCF_INTC0_ICR15 MCF_REG08(0xFC04804F)
-+#define MCF_INTC0_ICR16 MCF_REG08(0xFC048050)
-+#define MCF_INTC0_ICR17 MCF_REG08(0xFC048051)
-+#define MCF_INTC0_ICR18 MCF_REG08(0xFC048052)
-+#define MCF_INTC0_ICR19 MCF_REG08(0xFC048053)
-+#define MCF_INTC0_ICR20 MCF_REG08(0xFC048054)
-+#define MCF_INTC0_ICR21 MCF_REG08(0xFC048055)
-+#define MCF_INTC0_ICR22 MCF_REG08(0xFC048056)
-+#define MCF_INTC0_ICR23 MCF_REG08(0xFC048057)
-+#define MCF_INTC0_ICR24 MCF_REG08(0xFC048058)
-+#define MCF_INTC0_ICR25 MCF_REG08(0xFC048059)
-+#define MCF_INTC0_ICR26 MCF_REG08(0xFC04805A)
-+#define MCF_INTC0_ICR27 MCF_REG08(0xFC04805B)
-+#define MCF_INTC0_ICR28 MCF_REG08(0xFC04805C)
-+#define MCF_INTC0_ICR29 MCF_REG08(0xFC04805D)
-+#define MCF_INTC0_ICR30 MCF_REG08(0xFC04805E)
-+#define MCF_INTC0_ICR31 MCF_REG08(0xFC04805F)
-+#define MCF_INTC0_ICR32 MCF_REG08(0xFC048060)
-+#define MCF_INTC0_ICR33 MCF_REG08(0xFC048061)
-+#define MCF_INTC0_ICR34 MCF_REG08(0xFC048062)
-+#define MCF_INTC0_ICR35 MCF_REG08(0xFC048063)
-+#define MCF_INTC0_ICR36 MCF_REG08(0xFC048064)
-+#define MCF_INTC0_ICR37 MCF_REG08(0xFC048065)
-+#define MCF_INTC0_ICR38 MCF_REG08(0xFC048066)
-+#define MCF_INTC0_ICR39 MCF_REG08(0xFC048067)
-+#define MCF_INTC0_ICR40 MCF_REG08(0xFC048068)
-+#define MCF_INTC0_ICR41 MCF_REG08(0xFC048069)
-+#define MCF_INTC0_ICR42 MCF_REG08(0xFC04806A)
-+#define MCF_INTC0_ICR43 MCF_REG08(0xFC04806B)
-+#define MCF_INTC0_ICR44 MCF_REG08(0xFC04806C)
-+#define MCF_INTC0_ICR45 MCF_REG08(0xFC04806D)
-+#define MCF_INTC0_ICR46 MCF_REG08(0xFC04806E)
-+#define MCF_INTC0_ICR47 MCF_REG08(0xFC04806F)
-+#define MCF_INTC0_ICR48 MCF_REG08(0xFC048070)
-+#define MCF_INTC0_ICR49 MCF_REG08(0xFC048071)
-+#define MCF_INTC0_ICR50 MCF_REG08(0xFC048072)
-+#define MCF_INTC0_ICR51 MCF_REG08(0xFC048073)
-+#define MCF_INTC0_ICR52 MCF_REG08(0xFC048074)
-+#define MCF_INTC0_ICR53 MCF_REG08(0xFC048075)
-+#define MCF_INTC0_ICR54 MCF_REG08(0xFC048076)
-+#define MCF_INTC0_ICR55 MCF_REG08(0xFC048077)
-+#define MCF_INTC0_ICR56 MCF_REG08(0xFC048078)
-+#define MCF_INTC0_ICR57 MCF_REG08(0xFC048079)
-+#define MCF_INTC0_ICR58 MCF_REG08(0xFC04807A)
-+#define MCF_INTC0_ICR59 MCF_REG08(0xFC04807B)
-+#define MCF_INTC0_ICR60 MCF_REG08(0xFC04807C)
-+#define MCF_INTC0_ICR61 MCF_REG08(0xFC04807D)
-+#define MCF_INTC0_ICR62 MCF_REG08(0xFC04807E)
-+#define MCF_INTC0_ICR63 MCF_REG08(0xFC04807F)
-+#define MCF_INTC0_SWIACK MCF_REG08(0xFC0480E0)
-+#define MCF_INTC0_L1IACK MCF_REG08(0xFC0480E4)
-+#define MCF_INTC0_L2IACK MCF_REG08(0xFC0480E8)
-+#define MCF_INTC0_L3IACK MCF_REG08(0xFC0480EC)
-+#define MCF_INTC0_L4IACK MCF_REG08(0xFC0480F0)
-+#define MCF_INTC0_L5IACK MCF_REG08(0xFC0480F4)
-+#define MCF_INTC0_L6IACK MCF_REG08(0xFC0480F8)
-+#define MCF_INTC0_L7IACK MCF_REG08(0xFC0480FC)
-+#define MCF_INTC1_IPRH MCF_REG32(0xFC04C000)
-+#define MCF_INTC1_IPRL MCF_REG32(0xFC04C004)
-+#define MCF_INTC1_IMRH MCF_REG32(0xFC04C008)
-+#define MCF_INTC1_IMRL MCF_REG32(0xFC04C00C)
-+#define MCF_INTC1_INTFRCH MCF_REG32(0xFC04C010)
-+#define MCF_INTC1_INTFRCL MCF_REG32(0xFC04C014)
-+#define MCF_INTC1_ICONFIG MCF_REG16(0xFC04C01A)
-+#define MCF_INTC1_SIMR MCF_REG08(0xFC04C01C)
-+#define MCF_INTC1_CIMR MCF_REG08(0xFC04C01D)
-+#define MCF_INTC1_CLMASK MCF_REG08(0xFC04C01E)
-+#define MCF_INTC1_SLMASK MCF_REG08(0xFC04C01F)
-+#define MCF_INTC1_ICR1 MCF_REG08(0xFC04C041)
-+#define MCF_INTC1_ICR2 MCF_REG08(0xFC04C042)
-+#define MCF_INTC1_ICR3 MCF_REG08(0xFC04C043)
-+#define MCF_INTC1_ICR4 MCF_REG08(0xFC04C044)
-+#define MCF_INTC1_ICR5 MCF_REG08(0xFC04C045)
-+#define MCF_INTC1_ICR6 MCF_REG08(0xFC04C046)
-+#define MCF_INTC1_ICR7 MCF_REG08(0xFC04C047)
-+#define MCF_INTC1_ICR8 MCF_REG08(0xFC04C048)
-+#define MCF_INTC1_ICR9 MCF_REG08(0xFC04C049)
-+#define MCF_INTC1_ICR10 MCF_REG08(0xFC04C04A)
-+#define MCF_INTC1_ICR11 MCF_REG08(0xFC04C04B)
-+#define MCF_INTC1_ICR12 MCF_REG08(0xFC04C04C)
-+#define MCF_INTC1_ICR13 MCF_REG08(0xFC04C04D)
-+#define MCF_INTC1_ICR14 MCF_REG08(0xFC04C04E)
-+#define MCF_INTC1_ICR15 MCF_REG08(0xFC04C04F)
-+#define MCF_INTC1_ICR16 MCF_REG08(0xFC04C050)
-+#define MCF_INTC1_ICR17 MCF_REG08(0xFC04C051)
-+#define MCF_INTC1_ICR18 MCF_REG08(0xFC04C052)
-+#define MCF_INTC1_ICR19 MCF_REG08(0xFC04C053)
-+#define MCF_INTC1_ICR20 MCF_REG08(0xFC04C054)
-+#define MCF_INTC1_ICR21 MCF_REG08(0xFC04C055)
-+#define MCF_INTC1_ICR22 MCF_REG08(0xFC04C056)
-+#define MCF_INTC1_ICR23 MCF_REG08(0xFC04C057)
-+#define MCF_INTC1_ICR24 MCF_REG08(0xFC04C058)
-+#define MCF_INTC1_ICR25 MCF_REG08(0xFC04C059)
-+#define MCF_INTC1_ICR26 MCF_REG08(0xFC04C05A)
-+#define MCF_INTC1_ICR27 MCF_REG08(0xFC04C05B)
-+#define MCF_INTC1_ICR28 MCF_REG08(0xFC04C05C)
-+#define MCF_INTC1_ICR29 MCF_REG08(0xFC04C05D)
-+#define MCF_INTC1_ICR30 MCF_REG08(0xFC04C05E)
-+#define MCF_INTC1_ICR31 MCF_REG08(0xFC04C05F)
-+#define MCF_INTC1_ICR32 MCF_REG08(0xFC04C060)
-+#define MCF_INTC1_ICR33 MCF_REG08(0xFC04C061)
-+#define MCF_INTC1_ICR34 MCF_REG08(0xFC04C062)
-+#define MCF_INTC1_ICR35 MCF_REG08(0xFC04C063)
-+#define MCF_INTC1_ICR36 MCF_REG08(0xFC04C064)
-+#define MCF_INTC1_ICR37 MCF_REG08(0xFC04C065)
-+#define MCF_INTC1_ICR38 MCF_REG08(0xFC04C066)
-+#define MCF_INTC1_ICR39 MCF_REG08(0xFC04C067)
-+#define MCF_INTC1_ICR40 MCF_REG08(0xFC04C068)
-+#define MCF_INTC1_ICR41 MCF_REG08(0xFC04C069)
-+#define MCF_INTC1_ICR42 MCF_REG08(0xFC04C06A)
-+#define MCF_INTC1_ICR43 MCF_REG08(0xFC04C06B)
-+#define MCF_INTC1_ICR44 MCF_REG08(0xFC04C06C)
-+#define MCF_INTC1_ICR45 MCF_REG08(0xFC04C06D)
-+#define MCF_INTC1_ICR46 MCF_REG08(0xFC04C06E)
-+#define MCF_INTC1_ICR47 MCF_REG08(0xFC04C06F)
-+#define MCF_INTC1_ICR48 MCF_REG08(0xFC04C070)
-+#define MCF_INTC1_ICR49 MCF_REG08(0xFC04C071)
-+#define MCF_INTC1_ICR50 MCF_REG08(0xFC04C072)
-+#define MCF_INTC1_ICR51 MCF_REG08(0xFC04C073)
-+#define MCF_INTC1_ICR52 MCF_REG08(0xFC04C074)
-+#define MCF_INTC1_ICR53 MCF_REG08(0xFC04C075)
-+#define MCF_INTC1_ICR54 MCF_REG08(0xFC04C076)
-+#define MCF_INTC1_ICR55 MCF_REG08(0xFC04C077)
-+#define MCF_INTC1_ICR56 MCF_REG08(0xFC04C078)
-+#define MCF_INTC1_ICR57 MCF_REG08(0xFC04C079)
-+#define MCF_INTC1_ICR58 MCF_REG08(0xFC04C07A)
-+#define MCF_INTC1_ICR59 MCF_REG08(0xFC04C07B)
-+#define MCF_INTC1_ICR60 MCF_REG08(0xFC04C07C)
-+#define MCF_INTC1_ICR61 MCF_REG08(0xFC04C07D)
-+#define MCF_INTC1_ICR62 MCF_REG08(0xFC04C07E)
-+#define MCF_INTC1_ICR63 MCF_REG08(0xFC04C07F)
-+#define MCF_INTC1_SWIACK MCF_REG08(0xFC04C0E0)
-+#define MCF_INTC1_L1IACK MCF_REG08(0xFC04C0E4)
-+#define MCF_INTC1_L2IACK MCF_REG08(0xFC04C0E8)
-+#define MCF_INTC1_L3IACK MCF_REG08(0xFC04C0EC)
-+#define MCF_INTC1_L4IACK MCF_REG08(0xFC04C0F0)
-+#define MCF_INTC1_L5IACK MCF_REG08(0xFC04C0F4)
-+#define MCF_INTC1_L6IACK MCF_REG08(0xFC04C0F8
-+#define MCF_INTC1_L7IACK MCF_REG08(0xFC04C0FC)
-+
-+/* Parameterized register read/write macros for multiple registers */
-+#define MCF_INTC0_ICR(x) MCF_REG08(0xFC048041+((x-1)*0x001))
-+#define MCF_INTC0_LIACK(x) MCF_REG08(0xFC0480E4+((x-1)*0x004))
-+#define MCF_INTC1_ICR(x) MCF_REG08(0xFC04C041+((x-1)*0x001))
-+#define MCF_INTC1_LIACK(x) MCF_REG08(0xFC04C0E4+((x-1)*0x004))
-+
-+/* Parameterized register read/write macros for multiple modules */
-+#define MCF_INTC_IPRH(x) MCF_REG32(0xFC048000+((x)*0x4000))
-+#define MCF_INTC_IPRL(x) MCF_REG32(0xFC048004+((x)*0x4000))
-+#define MCF_INTC_IMRH(x) MCF_REG32(0xFC048008+((x)*0x4000))
-+#define MCF_INTC_IMRL(x) MCF_REG32(0xFC04800C+((x)*0x4000))
-+#define MCF_INTC_INTFRCH(x) MCF_REG32(0xFC048010+((x)*0x4000))
-+#define MCF_INTC_INTFRCL(x) MCF_REG32(0xFC048014+((x)*0x4000))
-+#define MCF_INTC_ICONFIG(x) MCF_REG16(0xFC04801A+((x)*0x4000))
-+#define MCF_INTC_SIMR(x) MCF_REG08(0xFC04801C+((x)*0x4000))
-+#define MCF_INTC_CIMR(x) MCF_REG08(0xFC04801D+((x)*0x4000))
-+#define MCF_INTC_CLMASK(x) MCF_REG08(0xFC04801E+((x)*0x4000))
-+#define MCF_INTC_SLMASK(x) MCF_REG08(0xFC04801F+((x)*0x4000))
-+#define MCF_INTC_ICR1(x) MCF_REG08(0xFC048041+((x)*0x4000))
-+#define MCF_INTC_ICR2(x) MCF_REG08(0xFC048042+((x)*0x4000))
-+#define MCF_INTC_ICR3(x) MCF_REG08(0xFC048043+((x)*0x4000))
-+#define MCF_INTC_ICR4(x) MCF_REG08(0xFC048044+((x)*0x4000))
-+#define MCF_INTC_ICR5(x) MCF_REG08(0xFC048045+((x)*0x4000))
-+#define MCF_INTC_ICR6(x) MCF_REG08(0xFC048046+((x)*0x4000))
-+#define MCF_INTC_ICR7(x) MCF_REG08(0xFC048047+((x)*0x4000))
-+#define MCF_INTC_ICR8(x) MCF_REG08(0xFC048048+((x)*0x4000))
-+#define MCF_INTC_ICR9(x) MCF_REG08(0xFC048049+((x)*0x4000))
-+#define MCF_INTC_ICR10(x) MCF_REG08(0xFC04804A+((x)*0x4000))
-+#define MCF_INTC_ICR11(x) MCF_REG08(0xFC04804B+((x)*0x4000))
-+#define MCF_INTC_ICR12(x) MCF_REG08(0xFC04804C+((x)*0x4000))
-+#define MCF_INTC_ICR13(x) MCF_REG08(0xFC04804D+((x)*0x4000))
-+#define MCF_INTC_ICR14(x) MCF_REG08(0xFC04804E+((x)*0x4000))
-+#define MCF_INTC_ICR15(x) MCF_REG08(0xFC04804F+((x)*0x4000))
-+#define MCF_INTC_ICR16(x) MCF_REG08(0xFC048050+((x)*0x4000))
-+#define MCF_INTC_ICR17(x) MCF_REG08(0xFC048051+((x)*0x4000))
-+#define MCF_INTC_ICR18(x) MCF_REG08(0xFC048052+((x)*0x4000))
-+#define MCF_INTC_ICR19(x) MCF_REG08(0xFC048053+((x)*0x4000))
-+#define MCF_INTC_ICR20(x) MCF_REG08(0xFC048054+((x)*0x4000))
-+#define MCF_INTC_ICR21(x) MCF_REG08(0xFC048055+((x)*0x4000))
-+#define MCF_INTC_ICR22(x) MCF_REG08(0xFC048056+((x)*0x4000))
-+#define MCF_INTC_ICR23(x) MCF_REG08(0xFC048057+((x)*0x4000))
-+#define MCF_INTC_ICR24(x) MCF_REG08(0xFC048058+((x)*0x4000))
-+#define MCF_INTC_ICR25(x) MCF_REG08(0xFC048059+((x)*0x4000))
-+#define MCF_INTC_ICR26(x) MCF_REG08(0xFC04805A+((x)*0x4000))
-+#define MCF_INTC_ICR27(x) MCF_REG08(0xFC04805B+((x)*0x4000))
-+#define MCF_INTC_ICR28(x) MCF_REG08(0xFC04805C+((x)*0x4000))
-+#define MCF_INTC_ICR29(x) MCF_REG08(0xFC04805D+((x)*0x4000))
-+#define MCF_INTC_ICR30(x) MCF_REG08(0xFC04805E+((x)*0x4000))
-+#define MCF_INTC_ICR31(x) MCF_REG08(0xFC04805F+((x)*0x4000))
-+#define MCF_INTC_ICR32(x) MCF_REG08(0xFC048060+((x)*0x4000))
-+#define MCF_INTC_ICR33(x) MCF_REG08(0xFC048061+((x)*0x4000))
-+#define MCF_INTC_ICR34(x) MCF_REG08(0xFC048062+((x)*0x4000))
-+#define MCF_INTC_ICR35(x) MCF_REG08(0xFC048063+((x)*0x4000))
-+#define MCF_INTC_ICR36(x) MCF_REG08(0xFC048064+((x)*0x4000))
-+#define MCF_INTC_ICR37(x) MCF_REG08(0xFC048065+((x)*0x4000))
-+#define MCF_INTC_ICR38(x) MCF_REG08(0xFC048066+((x)*0x4000))
-+#define MCF_INTC_ICR39(x) MCF_REG08(0xFC048067+((x)*0x4000))
-+#define MCF_INTC_ICR40(x) MCF_REG08(0xFC048068+((x)*0x4000))
-+#define MCF_INTC_ICR41(x) MCF_REG08(0xFC048069+((x)*0x4000))
-+#define MCF_INTC_ICR42(x) MCF_REG08(0xFC04806A+((x)*0x4000))
-+#define MCF_INTC_ICR43(x) MCF_REG08(0xFC04806B+((x)*0x4000))
-+#define MCF_INTC_ICR44(x) MCF_REG08(0xFC04806C+((x)*0x4000))
-+#define MCF_INTC_ICR45(x) MCF_REG08(0xFC04806D+((x)*0x4000))
-+#define MCF_INTC_ICR46(x) MCF_REG08(0xFC04806E+((x)*0x4000))
-+#define MCF_INTC_ICR47(x) MCF_REG08(0xFC04806F+((x)*0x4000))
-+#define MCF_INTC_ICR48(x) MCF_REG08(0xFC048070+((x)*0x4000))
-+#define MCF_INTC_ICR49(x) MCF_REG08(0xFC048071+((x)*0x4000))
-+#define MCF_INTC_ICR50(x) MCF_REG08(0xFC048072+((x)*0x4000))
-+#define MCF_INTC_ICR51(x) MCF_REG08(0xFC048073+((x)*0x4000))
-+#define MCF_INTC_ICR52(x) MCF_REG08(0xFC048074+((x)*0x4000))
-+#define MCF_INTC_ICR53(x) MCF_REG08(0xFC048075+((x)*0x4000))
-+#define MCF_INTC_ICR54(x) MCF_REG08(0xFC048076+((x)*0x4000))
-+#define MCF_INTC_ICR55(x) MCF_REG08(0xFC048077+((x)*0x4000))
-+#define MCF_INTC_ICR56(x) MCF_REG08(0xFC048078+((x)*0x4000))
-+#define MCF_INTC_ICR57(x) MCF_REG08(0xFC048079+((x)*0x4000))
-+#define MCF_INTC_ICR58(x) MCF_REG08(0xFC04807A+((x)*0x4000))
-+#define MCF_INTC_ICR59(x) MCF_REG08(0xFC04807B+((x)*0x4000))
-+#define MCF_INTC_ICR60(x) MCF_REG08(0xFC04807C+((x)*0x4000))
-+#define MCF_INTC_ICR61(x) MCF_REG08(0xFC04807D+((x)*0x4000))
-+#define MCF_INTC_ICR62(x) MCF_REG08(0xFC04807E+((x)*0x4000))
-+#define MCF_INTC_ICR63(x) MCF_REG08(0xFC04807F+((x)*0x4000))
-+#define MCF_INTC_SWIACK(x) MCF_REG08(0xFC0480E0+((x)*0x4000))
-+#define MCF_INTC_L1IACK(x) MCF_REG08(0xFC0480E4+((x)*0x4000))
-+#define MCF_INTC_L2IACK(x) MCF_REG08(0xFC0480E8+((x)*0x4000))
-+#define MCF_INTC_L3IACK(x) MCF_REG08(0xFC0480EC+((x)*0x4000))
-+#define MCF_INTC_L4IACK(x) MCF_REG08(0xFC0480F0+((x)*0x4000))
-+#define MCF_INTC_L5IACK(x) MCF_REG08(0xFC0480F4+((x)*0x4000))
-+#define MCF_INTC_L6IACK(x) MCF_REG08(0xFC0480F8+((x)*0x4000))
-+#define MCF_INTC_L7IACK(x) MCF_REG08(0xFC0480FC+((x)*0x4000))
-+
-+/* Bit definitions and macros for IPRH */
-+#define MCF_INTC_IPRH_INT32 (0x00000001)
-+#define MCF_INTC_IPRH_INT33 (0x00000002)
-+#define MCF_INTC_IPRH_INT34 (0x00000004)
-+#define MCF_INTC_IPRH_INT35 (0x00000008)
-+#define MCF_INTC_IPRH_INT36 (0x00000010)
-+#define MCF_INTC_IPRH_INT37 (0x00000020)
-+#define MCF_INTC_IPRH_INT38 (0x00000040)
-+#define MCF_INTC_IPRH_INT39 (0x00000080)
-+#define MCF_INTC_IPRH_INT40 (0x00000100)
-+#define MCF_INTC_IPRH_INT41 (0x00000200)
-+#define MCF_INTC_IPRH_INT42 (0x00000400)
-+#define MCF_INTC_IPRH_INT43 (0x00000800)
-+#define MCF_INTC_IPRH_INT44 (0x00001000)
-+#define MCF_INTC_IPRH_INT45 (0x00002000)
-+#define MCF_INTC_IPRH_INT46 (0x00004000)
-+#define MCF_INTC_IPRH_INT47 (0x00008000)
-+#define MCF_INTC_IPRH_INT48 (0x00010000)
-+#define MCF_INTC_IPRH_INT49 (0x00020000)
-+#define MCF_INTC_IPRH_INT50 (0x00040000)
-+#define MCF_INTC_IPRH_INT51 (0x00080000)
-+#define MCF_INTC_IPRH_INT52 (0x00100000)
-+#define MCF_INTC_IPRH_INT53 (0x00200000)
-+#define MCF_INTC_IPRH_INT54 (0x00400000)
-+#define MCF_INTC_IPRH_INT55 (0x00800000)
-+#define MCF_INTC_IPRH_INT56 (0x01000000)
-+#define MCF_INTC_IPRH_INT57 (0x02000000)
-+#define MCF_INTC_IPRH_INT58 (0x04000000)
-+#define MCF_INTC_IPRH_INT59 (0x08000000)
-+#define MCF_INTC_IPRH_INT60 (0x10000000)
-+#define MCF_INTC_IPRH_INT61 (0x20000000)
-+#define MCF_INTC_IPRH_INT62 (0x40000000)
-+#define MCF_INTC_IPRH_INT63 (0x80000000)
-+
-+/* Bit definitions and macros for IPRL */
-+#define MCF_INTC_IPRL_INT0 (0x00000001)
-+#define MCF_INTC_IPRL_INT1 (0x00000002)
-+#define MCF_INTC_IPRL_INT2 (0x00000004)
-+#define MCF_INTC_IPRL_INT3 (0x00000008)
-+#define MCF_INTC_IPRL_INT4 (0x00000010)
-+#define MCF_INTC_IPRL_INT5 (0x00000020)
-+#define MCF_INTC_IPRL_INT6 (0x00000040)
-+#define MCF_INTC_IPRL_INT7 (0x00000080)
-+#define MCF_INTC_IPRL_INT8 (0x00000100)
-+#define MCF_INTC_IPRL_INT9 (0x00000200)
-+#define MCF_INTC_IPRL_INT10 (0x00000400)
-+#define MCF_INTC_IPRL_INT11 (0x00000800)
-+#define MCF_INTC_IPRL_INT12 (0x00001000)
-+#define MCF_INTC_IPRL_INT13 (0x00002000)
-+#define MCF_INTC_IPRL_INT14 (0x00004000)
-+#define MCF_INTC_IPRL_INT15 (0x00008000)
-+#define MCF_INTC_IPRL_INT16 (0x00010000)
-+#define MCF_INTC_IPRL_INT17 (0x00020000)
-+#define MCF_INTC_IPRL_INT18 (0x00040000)
-+#define MCF_INTC_IPRL_INT19 (0x00080000)
-+#define MCF_INTC_IPRL_INT20 (0x00100000)
-+#define MCF_INTC_IPRL_INT21 (0x00200000)
-+#define MCF_INTC_IPRL_INT22 (0x00400000)
-+#define MCF_INTC_IPRL_INT23 (0x00800000)
-+#define MCF_INTC_IPRL_INT24 (0x01000000)
-+#define MCF_INTC_IPRL_INT25 (0x02000000)
-+#define MCF_INTC_IPRL_INT26 (0x04000000)
-+#define MCF_INTC_IPRL_INT27 (0x08000000)
-+#define MCF_INTC_IPRL_INT28 (0x10000000)
-+#define MCF_INTC_IPRL_INT29 (0x20000000)
-+#define MCF_INTC_IPRL_INT30 (0x40000000)
-+#define MCF_INTC_IPRL_INT31 (0x80000000)
-+
-+/* Bit definitions and macros for IMRH */
-+#define MCF_INTC_IMRH_INT_MASK32 (0x00000001)
-+#define MCF_INTC_IMRH_INT_MASK33 (0x00000002)
-+#define MCF_INTC_IMRH_INT_MASK34 (0x00000004)
-+#define MCF_INTC_IMRH_INT_MASK35 (0x00000008)
-+#define MCF_INTC_IMRH_INT_MASK36 (0x00000010)
-+#define MCF_INTC_IMRH_INT_MASK37 (0x00000020)
-+#define MCF_INTC_IMRH_INT_MASK38 (0x00000040)
-+#define MCF_INTC_IMRH_INT_MASK39 (0x00000080)
-+#define MCF_INTC_IMRH_INT_MASK40 (0x00000100)
-+#define MCF_INTC_IMRH_INT_MASK41 (0x00000200)
-+#define MCF_INTC_IMRH_INT_MASK42 (0x00000400)
-+#define MCF_INTC_IMRH_INT_MASK43 (0x00000800)
-+#define MCF_INTC_IMRH_INT_MASK44 (0x00001000)
-+#define MCF_INTC_IMRH_INT_MASK45 (0x00002000)
-+#define MCF_INTC_IMRH_INT_MASK46 (0x00004000)
-+#define MCF_INTC_IMRH_INT_MASK47 (0x00008000)
-+#define MCF_INTC_IMRH_INT_MASK48 (0x00010000)
-+#define MCF_INTC_IMRH_INT_MASK49 (0x00020000)
-+#define MCF_INTC_IMRH_INT_MASK50 (0x00040000)
-+#define MCF_INTC_IMRH_INT_MASK51 (0x00080000)
-+#define MCF_INTC_IMRH_INT_MASK52 (0x00100000)
-+#define MCF_INTC_IMRH_INT_MASK53 (0x00200000)
-+#define MCF_INTC_IMRH_INT_MASK54 (0x00400000)
-+#define MCF_INTC_IMRH_INT_MASK55 (0x00800000)
-+#define MCF_INTC_IMRH_INT_MASK56 (0x01000000)
-+#define MCF_INTC_IMRH_INT_MASK57 (0x02000000)
-+#define MCF_INTC_IMRH_INT_MASK58 (0x04000000)
-+#define MCF_INTC_IMRH_INT_MASK59 (0x08000000)
-+#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
-+#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
-+#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
-+#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
-+
-+/* Bit definitions and macros for IMRL */
-+#define MCF_INTC_IMRL_INT_MASK0 (0x00000001)
-+#define MCF_INTC_IMRL_INT_MASK1 (0x00000002)
-+#define MCF_INTC_IMRL_INT_MASK2 (0x00000004)
-+#define MCF_INTC_IMRL_INT_MASK3 (0x00000008)
-+#define MCF_INTC_IMRL_INT_MASK4 (0x00000010)
-+#define MCF_INTC_IMRL_INT_MASK5 (0x00000020)
-+#define MCF_INTC_IMRL_INT_MASK6 (0x00000040)
-+#define MCF_INTC_IMRL_INT_MASK7 (0x00000080)
-+#define MCF_INTC_IMRL_INT_MASK8 (0x00000100)
-+#define MCF_INTC_IMRL_INT_MASK9 (0x00000200)
-+#define MCF_INTC_IMRL_INT_MASK10 (0x00000400)
-+#define MCF_INTC_IMRL_INT_MASK11 (0x00000800)
-+#define MCF_INTC_IMRL_INT_MASK12 (0x00001000)
-+#define MCF_INTC_IMRL_INT_MASK13 (0x00002000)
-+#define MCF_INTC_IMRL_INT_MASK14 (0x00004000)
-+#define MCF_INTC_IMRL_INT_MASK15 (0x00008000)
-+#define MCF_INTC_IMRL_INT_MASK16 (0x00010000)
-+#define MCF_INTC_IMRL_INT_MASK17 (0x00020000)
-+#define MCF_INTC_IMRL_INT_MASK18 (0x00040000)
-+#define MCF_INTC_IMRL_INT_MASK19 (0x00080000)
-+#define MCF_INTC_IMRL_INT_MASK20 (0x00100000)
-+#define MCF_INTC_IMRL_INT_MASK21 (0x00200000)
-+#define MCF_INTC_IMRL_INT_MASK22 (0x00400000)
-+#define MCF_INTC_IMRL_INT_MASK23 (0x00800000)
-+#define MCF_INTC_IMRL_INT_MASK24 (0x01000000)
-+#define MCF_INTC_IMRL_INT_MASK25 (0x02000000)
-+#define MCF_INTC_IMRL_INT_MASK26 (0x04000000)
-+#define MCF_INTC_IMRL_INT_MASK27 (0x08000000)
-+#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
-+#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
-+#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
-+#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
-+
-+/* Bit definitions and macros for INTFRCH */
-+#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001)
-+#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002)
-+#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004)
-+#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008)
-+#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010)
-+#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020)
-+#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040)
-+#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080)
-+#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100)
-+#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200)
-+#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400)
-+#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800)
-+#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000)
-+#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000)
-+#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000)
-+#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000)
-+#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000)
-+#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000)
-+#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000)
-+#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000)
-+#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000)
-+#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000)
-+#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000)
-+#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000)
-+#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000)
-+#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000)
-+#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000)
-+#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000)
-+#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
-+#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
-+#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
-+#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
-+
-+/* Bit definitions and macros for INTFRCL */
-+#define MCF_INTC_INTFRCL_INTFRC0 (0x00000001)
-+#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002)
-+#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004)
-+#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008)
-+#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010)
-+#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020)
-+#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040)
-+#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080)
-+#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100)
-+#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200)
-+#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400)
-+#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800)
-+#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000)
-+#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000)
-+#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000)
-+#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000)
-+#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000)
-+#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000)
-+#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000)
-+#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000)
-+#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000)
-+#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000)
-+#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000)
-+#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000)
-+#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000)
-+#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000)
-+#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000)
-+#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000)
-+#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
-+#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
-+#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
-+#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
-+
-+/* Bit definitions and macros for ICONFIG */
-+#define MCF_INTC_ICONFIG_EMASK (0x0020)
-+#define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200)
-+#define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400)
-+#define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800)
-+#define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000)
-+#define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000)
-+#define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000)
-+#define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000)
-+
-+/* Bit definitions and macros for SIMR */
-+#define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F))
-+
-+/* Bit definitions and macros for CIMR */
-+#define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F))
-+
-+/* Bit definitions and macros for CLMASK */
-+#define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F))
-+
-+/* Bit definitions and macros for SLMASK */
-+#define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F))
-+
-+/* Bit definitions and macros for ICR group */
-+#define MCF_INTC_ICR_IL(x) (((x)&0x07))
-+
-+/* Bit definitions and macros for ICR1 */
-+#define MCF_INTC_ICR1_IL(x) (((x)&0x07))
-+
-+/* Bit definitions and macros for ICR2 */
-+#define MCF_INTC_ICR2_IL(x) (((x)&0x07))
-+
-+/* Bit definitions and macros for ICR3 */
-+#define MCF_INTC_ICR3_IL(x) (((x)&0x07))
-+
-+/* Bit definitions and macros for ICR4 */
-+#define MCF_INTC_ICR4_IL(x) (((x)&0x07))
-+
-+/* Bit definitions and macros for ICR5 */
-+#define MCF_INTC_ICR5_IL(x) (((x)&0x07))
-+
-+/* Bit definitions and macros for ICR6 */
-+#define MCF_INTC_ICR6_IL(x) (((x)&0x07))
-+
-+/* Bit definitions and macros for ICR7 */
-+#define MCF_INTC_ICR7_IL(x) (((x)&0x07))
-+
-+/* Bit definitions and macros for ICR8 */
-+#define MCF_INTC_ICR8_IL(x) (((x)&0x07))
-+
-+/* Bit definitions and macros for ICR9 */
-+#define MCF_INTC_ICR9_IL(x) (((x)&0x07))
-+
-+/* Bit definitions and macros for ICR10 */
-+#define MCF_INTC_ICR10_IL(x) (((x)&0x07))
-+
-+/* Bit definitions and macros for ICR11 */
-+#define MCF_INTC_ICR11_IL(x) (((x)&0x07))
-+
-+/* Bit definitions and macros for ICR12 */
-+#define MCF_INTC_ICR12_IL(x) (((x)&0x07))
-+
-+/* Bit definitions and macros for ICR13 */
-+#define MCF_INTC_ICR13_IL(x) (((x)&0x07))
-+
-+/* Bit definitions and macros for ICR14 */
-+#define MCF_INTC_ICR14_IL(x) (((x)&0x07))
-+
projects / openwrt / svn-archive / archive.git / commitdiff