package/boot/uboot-mediatek/patches/437-add-cmcc_rax3000m.patch

   1 --- /dev/null
   2 +++ b/configs/mt7981_cmcc_rax3000m-emmc_defconfig
   3 @@ -0,0 +1,175 @@
   4 +CONFIG_ARM=y
   5 +CONFIG_POSITION_INDEPENDENT=y
   6 +CONFIG_ARCH_MEDIATEK=y
   7 +CONFIG_TARGET_MT7981=y
   8 +CONFIG_TEXT_BASE=0x41e00000
   9 +CONFIG_SYS_MALLOC_F_LEN=0x4000
  10 +CONFIG_SYS_HAS_NONCACHED_MEMORY=y
  11 +CONFIG_NR_DRAM_BANKS=1
  12 +CONFIG_DEFAULT_DEVICE_TREE="mt7981-cmcc-rax3000m-emmc"
  13 +CONFIG_DEFAULT_ENV_FILE="cmcc_rax3000m-emmc_env"
  14 +CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981-cmcc-rax3000m-emmc.dtb"
  15 +CONFIG_OF_LIBFDT_OVERLAY=y
  16 +CONFIG_DEBUG_UART_BASE=0x11002000
  17 +CONFIG_DEBUG_UART_CLOCK=40000000
  18 +CONFIG_DEBUG_UART=y
  19 +CONFIG_SYS_LOAD_ADDR=0x46000000
  20 +CONFIG_SMBIOS_PRODUCT_NAME=""
  21 +CONFIG_AUTOBOOT_KEYED=y
  22 +CONFIG_BOOTDELAY=30
  23 +CONFIG_AUTOBOOT_MENU_SHOW=y
  24 +CONFIG_CFB_CONSOLE_ANSI=y
  25 +CONFIG_BOARD_LATE_INIT=y
  26 +CONFIG_BUTTON=y
  27 +CONFIG_BUTTON_GPIO=y
  28 +CONFIG_GPIO_HOG=y
  29 +CONFIG_CMD_ENV_FLAGS=y
  30 +CONFIG_FIT=y
  31 +CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
  32 +CONFIG_LED=y
  33 +CONFIG_LED_BLINK=y
  34 +CONFIG_LED_GPIO=y
  35 +CONFIG_LOGLEVEL=7
  36 +CONFIG_LOG=y
  37 +CONFIG_SYS_PROMPT="MT7981> "
  38 +CONFIG_CMD_BOOTMENU=y
  39 +CONFIG_CMD_BOOTP=y
  40 +CONFIG_CMD_BUTTON=y
  41 +CONFIG_CMD_CACHE=y
  42 +CONFIG_CMD_CDP=y
  43 +CONFIG_CMD_CPU=y
  44 +CONFIG_CMD_DHCP=y
  45 +CONFIG_CMD_DM=y
  46 +CONFIG_CMD_DNS=y
  47 +CONFIG_CMD_ECHO=y
  48 +CONFIG_CMD_ENV_READMEM=y
  49 +CONFIG_CMD_ERASEENV=y
  50 +CONFIG_CMD_EXT4=y
  51 +CONFIG_CMD_FAT=y
  52 +CONFIG_CMD_FDT=y
  53 +CONFIG_CMD_FS_GENERIC=y
  54 +CONFIG_CMD_FS_UUID=y
  55 +CONFIG_CMD_GPIO=y
  56 +CONFIG_CMD_GPT=y
  57 +CONFIG_CMD_HASH=y
  58 +CONFIG_CMD_ITEST=y
  59 +CONFIG_CMD_LED=y
  60 +CONFIG_CMD_LICENSE=y
  61 +CONFIG_CMD_LINK_LOCAL=y
  62 +# CONFIG_CMD_MBR is not set
  63 +CONFIG_CMD_MMC=y
  64 +CONFIG_CMD_PCI=y
  65 +CONFIG_CMD_PSTORE=y
  66 +CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
  67 +CONFIG_CMD_SF_TEST=y
  68 +CONFIG_CMD_PING=y
  69 +CONFIG_CMD_PXE=y
  70 +CONFIG_CMD_PWM=y
  71 +CONFIG_CMD_SMC=y
  72 +CONFIG_CMD_TFTPBOOT=y
  73 +CONFIG_CMD_TFTPSRV=y
  74 +CONFIG_CMD_ASKENV=y
  75 +CONFIG_CMD_PART=y
  76 +CONFIG_CMD_RARP=y
  77 +CONFIG_CMD_SETEXPR=y
  78 +CONFIG_CMD_SLEEP=y
  79 +CONFIG_CMD_SNTP=y
  80 +CONFIG_CMD_SOURCE=y
  81 +CONFIG_CMD_STRINGS=y
  82 +CONFIG_CMD_USB=y
  83 +CONFIG_CMD_UUID=y
  84 +CONFIG_DISPLAY_CPUINFO=y
  85 +CONFIG_DM_MMC=y
  86 +CONFIG_DM_REGULATOR=y
  87 +CONFIG_DM_REGULATOR_FIXED=y
  88 +CONFIG_DM_REGULATOR_GPIO=y
  89 +CONFIG_DM_USB=y
  90 +CONFIG_DM_PWM=y
  91 +CONFIG_PWM_MTK=y
  92 +CONFIG_HUSH_PARSER=y
  93 +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
  94 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  95 +CONFIG_VERSION_VARIABLE=y
  96 +CONFIG_PARTITION_UUIDS=y
  97 +CONFIG_NETCONSOLE=y
  98 +CONFIG_REGMAP=y
  99 +CONFIG_SYSCON=y
 100 +CONFIG_CLK=y
 101 +CONFIG_DM_GPIO=y
 102 +CONFIG_DM_SCSI=y
 103 +CONFIG_AHCI=y
 104 +CONFIG_AHCI_PCI=y
 105 +CONFIG_SCSI_AHCI=y
 106 +CONFIG_SCSI=y
 107 +CONFIG_CMD_SCSI=y
 108 +CONFIG_PHY=y
 109 +CONFIG_PHY_MTK_TPHY=y
 110 +CONFIG_PHY_FIXED=y
 111 +CONFIG_MTK_AHCI=y
 112 +CONFIG_DM_ETH=y
 113 +CONFIG_MEDIATEK_ETH=y
 114 +CONFIG_PCI=y
 115 +CONFIG_DM_PCI=y
 116 +CONFIG_PCIE_MEDIATEK=y
 117 +CONFIG_PINCTRL=y
 118 +CONFIG_PINCONF=y
 119 +CONFIG_PINCTRL_MT7622=y
 120 +CONFIG_POWER_DOMAIN=y
 121 +CONFIG_PRE_CONSOLE_BUFFER=y
 122 +CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
 123 +CONFIG_MTK_POWER_DOMAIN=y
 124 +CONFIG_RAM=y
 125 +CONFIG_DM_SERIAL=y
 126 +CONFIG_MTK_SERIAL=y
 127 +CONFIG_MMC=y
 128 +CONFIG_MMC_DEFAULT_DEV=1
 129 +CONFIG_MMC_HS200_SUPPORT=y
 130 +CONFIG_MMC_MTK=y
 131 +CONFIG_MMC_SUPPORTS_TUNING=y
 132 +CONFIG_SUPPORT_EMMC_BOOT=y
 133 +CONFIG_SPI=y
 134 +CONFIG_SYSRESET_WATCHDOG=y
 135 +CONFIG_WDT_MTK=y
 136 +CONFIG_LZO=y
 137 +CONFIG_ZSTD=y
 138 +CONFIG_HEXDUMP=y
 139 +CONFIG_RANDOM_UUID=y
 140 +CONFIG_REGEX=y
 141 +CONFIG_USB=y
 142 +CONFIG_USB_HOST=y
 143 +CONFIG_USB_XHCI_HCD=y
 144 +CONFIG_USB_XHCI_MTK=y
 145 +CONFIG_USB_STORAGE=y
 146 +CONFIG_OF_EMBED=y
 147 +CONFIG_ENV_OVERWRITE=y
 148 +CONFIG_ENV_IS_IN_MMC=y
 149 +CONFIG_ENV_OFFSET=0x400000
 150 +CONFIG_ENV_OFFSET_REDUND=0x440000
 151 +CONFIG_ENV_SIZE=0x40000
 152 +CONFIG_ENV_SIZE_REDUND=0x40000
 153 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 154 +CONFIG_NET_RANDOM_ETHADDR=y
 155 +CONFIG_REGMAP=y
 156 +CONFIG_SYSCON=y
 157 +CONFIG_CLK=y
 158 +CONFIG_SUPPORT_EMMC_BOOT=y
 159 +CONFIG_PHY_FIXED=y
 160 +CONFIG_DM_ETH=y
 161 +CONFIG_MEDIATEK_ETH=y
 162 +CONFIG_PINCTRL=y
 163 +CONFIG_PINCONF=y
 164 +CONFIG_PINCTRL_MT7981=y
 165 +CONFIG_POWER_DOMAIN=y
 166 +CONFIG_MTK_POWER_DOMAIN=y
 167 +CONFIG_DM_REGULATOR=y
 168 +CONFIG_DM_REGULATOR_FIXED=y
 169 +CONFIG_DM_SERIAL=y
 170 +CONFIG_MTK_SERIAL=y
 171 +CONFIG_HEXDUMP=y
 172 +CONFIG_USE_DEFAULT_ENV_FILE=y
 173 +CONFIG_CMD_SF=y
 174 +CONFIG_LMB_MAX_REGIONS=64
 175 +CONFIG_USE_IPADDR=y
 176 +CONFIG_IPADDR="192.168.1.1"
 177 +CONFIG_USE_SERVERIP=y
 178 +CONFIG_SERVERIP="192.168.1.254"
 179 --- /dev/null
 180 +++ b/configs/mt7981_cmcc_rax3000m-nand_defconfig
 181 @@ -0,0 +1,175 @@
 182 +CONFIG_ARM=y
 183 +CONFIG_POSITION_INDEPENDENT=y
 184 +CONFIG_ARCH_MEDIATEK=y
 185 +CONFIG_TARGET_MT7981=y
 186 +CONFIG_TEXT_BASE=0x41e00000
 187 +CONFIG_SYS_MALLOC_F_LEN=0x4000
 188 +CONFIG_SYS_HAS_NONCACHED_MEMORY=y
 189 +CONFIG_NR_DRAM_BANKS=1
 190 +CONFIG_DEFAULT_DEVICE_TREE="mt7981-cmcc-rax3000m-nand"
 191 +CONFIG_DEFAULT_ENV_FILE="cmcc_rax3000m-nand_env"
 192 +CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981-cmcc-rax3000m-nand.dtb"
 193 +CONFIG_OF_LIBFDT_OVERLAY=y
 194 +CONFIG_DEBUG_UART_BASE=0x11002000
 195 +CONFIG_DEBUG_UART_CLOCK=40000000
 196 +CONFIG_DEBUG_UART=y
 197 +CONFIG_SYS_LOAD_ADDR=0x46000000
 198 +CONFIG_SMBIOS_PRODUCT_NAME=""
 199 +CONFIG_AUTOBOOT_KEYED=y
 200 +CONFIG_BOOTDELAY=30
 201 +CONFIG_AUTOBOOT_MENU_SHOW=y
 202 +CONFIG_CFB_CONSOLE_ANSI=y
 203 +CONFIG_BOARD_LATE_INIT=y
 204 +CONFIG_BUTTON=y
 205 +CONFIG_BUTTON_GPIO=y
 206 +CONFIG_GPIO_HOG=y
 207 +CONFIG_CMD_ENV_FLAGS=y
 208 +CONFIG_FIT=y
 209 +CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
 210 +CONFIG_LED=y
 211 +CONFIG_LED_BLINK=y
 212 +CONFIG_LED_GPIO=y
 213 +CONFIG_LOGLEVEL=7
 214 +CONFIG_LOG=y
 215 +CONFIG_SYS_PROMPT="MT7981> "
 216 +CONFIG_CMD_BOOTMENU=y
 217 +CONFIG_CMD_BOOTP=y
 218 +CONFIG_CMD_BUTTON=y
 219 +CONFIG_CMD_CACHE=y
 220 +CONFIG_CMD_CDP=y
 221 +CONFIG_CMD_CPU=y
 222 +CONFIG_CMD_DHCP=y
 223 +CONFIG_CMD_DM=y
 224 +CONFIG_CMD_DNS=y
 225 +CONFIG_CMD_ECHO=y
 226 +CONFIG_CMD_ENV_READMEM=y
 227 +CONFIG_CMD_ERASEENV=y
 228 +CONFIG_CMD_EXT4=y
 229 +CONFIG_CMD_FAT=y
 230 +CONFIG_CMD_FDT=y
 231 +CONFIG_CMD_FS_GENERIC=y
 232 +CONFIG_CMD_FS_UUID=y
 233 +CONFIG_CMD_GPIO=y
 234 +CONFIG_CMD_GPT=y
 235 +CONFIG_CMD_HASH=y
 236 +CONFIG_CMD_ITEST=y
 237 +CONFIG_CMD_LED=y
 238 +CONFIG_CMD_LICENSE=y
 239 +CONFIG_CMD_LINK_LOCAL=y
 240 +# CONFIG_CMD_MBR is not set
 241 +CONFIG_CMD_PCI=y
 242 +CONFIG_CMD_PSTORE=y
 243 +CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
 244 +CONFIG_CMD_SF_TEST=y
 245 +CONFIG_CMD_PING=y
 246 +CONFIG_CMD_PXE=y
 247 +CONFIG_CMD_PWM=y
 248 +CONFIG_CMD_SMC=y
 249 +CONFIG_CMD_TFTPBOOT=y
 250 +CONFIG_CMD_TFTPSRV=y
 251 +CONFIG_CMD_UBI=y
 252 +CONFIG_CMD_UBI_RENAME=y
 253 +CONFIG_CMD_UBIFS=y
 254 +CONFIG_CMD_ASKENV=y
 255 +CONFIG_CMD_PART=y
 256 +CONFIG_CMD_RARP=y
 257 +CONFIG_CMD_SETEXPR=y
 258 +CONFIG_CMD_SLEEP=y
 259 +CONFIG_CMD_SNTP=y
 260 +CONFIG_CMD_SOURCE=y
 261 +CONFIG_CMD_STRINGS=y
 262 +CONFIG_CMD_UUID=y
 263 +CONFIG_DISPLAY_CPUINFO=y
 264 +CONFIG_DM_MTD=y
 265 +CONFIG_DM_REGULATOR=y
 266 +CONFIG_DM_REGULATOR_FIXED=y
 267 +CONFIG_DM_REGULATOR_GPIO=y
 268 +CONFIG_DM_PWM=y
 269 +CONFIG_PWM_MTK=y
 270 +CONFIG_HUSH_PARSER=y
 271 +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 272 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 273 +CONFIG_VERSION_VARIABLE=y
 274 +CONFIG_PARTITION_UUIDS=y
 275 +CONFIG_NETCONSOLE=y
 276 +CONFIG_REGMAP=y
 277 +CONFIG_SYSCON=y
 278 +CONFIG_CLK=y
 279 +CONFIG_DM_GPIO=y
 280 +CONFIG_DM_SCSI=y
 281 +CONFIG_AHCI=y
 282 +CONFIG_AHCI_PCI=y
 283 +CONFIG_SCSI_AHCI=y
 284 +CONFIG_SCSI=y
 285 +CONFIG_CMD_SCSI=y
 286 +CONFIG_PHY=y
 287 +CONFIG_PHY_MTK_TPHY=y
 288 +CONFIG_PHY_FIXED=y
 289 +CONFIG_MTK_AHCI=y
 290 +CONFIG_DM_ETH=y
 291 +CONFIG_MEDIATEK_ETH=y
 292 +CONFIG_PCI=y
 293 +# CONFIG_MMC is not set
 294 +# CONFIG_DM_MMC is not set
 295 +CONFIG_MTD=y
 296 +CONFIG_MTD_UBI_FASTMAP=y
 297 +CONFIG_DM_PCI=y
 298 +CONFIG_PCIE_MEDIATEK=y
 299 +CONFIG_PINCTRL=y
 300 +CONFIG_PINCONF=y
 301 +CONFIG_PINCTRL_MT7622=y
 302 +CONFIG_POWER_DOMAIN=y
 303 +CONFIG_PRE_CONSOLE_BUFFER=y
 304 +CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
 305 +CONFIG_MTK_POWER_DOMAIN=y
 306 +CONFIG_RAM=y
 307 +CONFIG_DM_SERIAL=y
 308 +CONFIG_MTK_SERIAL=y
 309 +CONFIG_SPI=y
 310 +CONFIG_DM_SPI=y
 311 +CONFIG_MTK_SPI_NAND=y
 312 +CONFIG_MTK_SPI_NAND_MTD=y
 313 +CONFIG_SYSRESET_WATCHDOG=y
 314 +CONFIG_WDT_MTK=y
 315 +CONFIG_LZO=y
 316 +CONFIG_ZSTD=y
 317 +CONFIG_HEXDUMP=y
 318 +CONFIG_RANDOM_UUID=y
 319 +CONFIG_REGEX=y
 320 +CONFIG_OF_EMBED=y
 321 +CONFIG_ENV_OVERWRITE=y
 322 +CONFIG_ENV_IS_IN_UBI=y
 323 +CONFIG_ENV_UBI_PART="ubi"
 324 +CONFIG_ENV_SIZE=0x1f000
 325 +CONFIG_ENV_SIZE_REDUND=0x1f000
 326 +CONFIG_ENV_UBI_VOLUME="ubootenv"
 327 +CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
 328 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 329 +CONFIG_NET_RANDOM_ETHADDR=y
 330 +CONFIG_REGMAP=y
 331 +CONFIG_SYSCON=y
 332 +CONFIG_CLK=y
 333 +CONFIG_PHY_FIXED=y
 334 +CONFIG_DM_ETH=y
 335 +CONFIG_MEDIATEK_ETH=y
 336 +CONFIG_PINCTRL=y
 337 +CONFIG_PINCONF=y
 338 +CONFIG_PINCTRL_MT7981=y
 339 +CONFIG_POWER_DOMAIN=y
 340 +CONFIG_MTK_POWER_DOMAIN=y
 341 +CONFIG_DM_REGULATOR=y
 342 +CONFIG_DM_REGULATOR_FIXED=y
 343 +CONFIG_DM_SERIAL=y
 344 +CONFIG_MTK_SERIAL=y
 345 +CONFIG_HEXDUMP=y
 346 +CONFIG_USE_DEFAULT_ENV_FILE=y
 347 +CONFIG_MTD_SPI_NAND=y
 348 +CONFIG_MTK_SPIM=y
 349 +CONFIG_CMD_MTD=y
 350 +CONFIG_CMD_NAND=y
 351 +CONFIG_CMD_NAND_TRIMFFS=y
 352 +CONFIG_LMB_MAX_REGIONS=64
 353 +CONFIG_USE_IPADDR=y
 354 +CONFIG_IPADDR="192.168.1.1"
 355 +CONFIG_USE_SERVERIP=y
 356 +CONFIG_SERVERIP="192.168.1.254"
 357 --- /dev/null
 358 +++ b/arch/arm/dts/mt7981-cmcc-rax3000m.dtsi
 359 @@ -0,0 +1,85 @@
 360 +// SPDX-License-Identifier: GPL-2.0-only
 361 +/*
 362 + * Copyright (c) 2022 MediaTek Inc.
 363 + * Author: Sam Shih <sam.shih@mediatek.com>
 364 + */
 365 +
 366 +/dts-v1/;
 367 +#include "mt7981.dtsi"
 368 +#include <dt-bindings/gpio/gpio.h>
 369 +#include <dt-bindings/input/linux-event-codes.h>
 370 +
 371 +/ {
 372 +       #address-cells = <1>;
 373 +       #size-cells = <1>;
 374 +       model = "CMCC RAX3000M";
 375 +       compatible = "mediatek,mt7981", "mediatek,mt7981-rfb";
 376 +
 377 +       chosen {
 378 +               stdout-path = &uart0;
 379 +               tick-timer = &timer0;
 380 +       };
 381 +
 382 +       memory@40000000 {
 383 +               device_type = "memory";
 384 +               reg = <0x40000000 0x20000000>;
 385 +       };
 386 +
 387 +       keys {
 388 +               compatible = "gpio-keys";
 389 +
 390 +               button-reset {
 391 +                       label = "reset";
 392 +                       linux,code = <KEY_RESTART>;
 393 +                       gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
 394 +               };
 395 +
 396 +               button-mesh {
 397 +                       label = "mesh";
 398 +                       linux,code = <BTN_9>;
 399 +                       linux,input-type = <EV_SW>;
 400 +                       gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 401 +               };
 402 +       };
 403 +
 404 +       leds {
 405 +               compatible = "gpio-leds";
 406 +
 407 +               led-0 {
 408 +                       label = "green:status";
 409 +                       gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
 410 +               };
 411 +
 412 +               led-1 {
 413 +                       label = "blue:status";
 414 +                       gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 415 +               };
 416 +
 417 +               led-2 {
 418 +                       label = "red:status";
 419 +                       gpios = <&gpio 35 GPIO_ACTIVE_LOW>;
 420 +               };
 421 +       };
 422 +};
 423 +
 424 +&eth {
 425 +       status = "okay";
 426 +       mediatek,gmac-id = <0>;
 427 +       phy-mode = "2500base-x";
 428 +       mediatek,switch = "mt7531";
 429 +       reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
 430 +
 431 +       fixed-link {
 432 +               speed = <2500>;
 433 +               full-duplex;
 434 +       };
 435 +};
 436 +
 437 +&uart0 {
 438 +       mediatek,force-highspeed;
 439 +       status = "okay";
 440 +};
 441 +
 442 +&watchdog {
 443 +       status = "disabled";
 444 +};
 445 --- /dev/null
 446 +++ b/arch/arm/dts/mt7981-cmcc-rax3000m-emmc.dts
 447 @@ -0,0 +1,53 @@
 448 +// SPDX-License-Identifier: GPL-2.0-only
 449 +
 450 +/dts-v1/;
 451 +#include "mt7981-cmcc-rax3000m.dtsi"
 452 +
 453 +/ {
 454 +       reg_3p3v: regulator-3p3v {
 455 +               compatible = "regulator-fixed";
 456 +               regulator-name = "fixed-3.3V";
 457 +               regulator-min-microvolt = <3300000>;
 458 +               regulator-max-microvolt = <3300000>;
 459 +               regulator-boot-on;
 460 +               regulator-always-on;
 461 +       };
 462 +};
 463 +
 464 +&mmc0 {
 465 +       pinctrl-names = "default";
 466 +       pinctrl-0 = <&mmc0_pins_default>;
 467 +       max-frequency = <26000000>;
 468 +       bus-width = <8>;
 469 +       cap-mmc-hw-reset;
 470 +       vmmc-supply = <&reg_3p3v>;
 471 +       non-removable;
 472 +       status = "okay";
 473 +};
 474 +
 475 +&pinctrl {
 476 +       mmc0_pins_default: mmc0default {
 477 +               mux {
 478 +                       function = "flash";
 479 +                       groups =  "emmc_45";
 480 +               };
 481 +               conf-cmd-dat {
 482 +                       pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
 483 +                               "SPI0_CS",  "SPI0_HOLD", "SPI0_WP",
 484 +                               "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
 485 +                       input-enable;
 486 +                       drive-strength = <MTK_DRIVE_4mA>;
 487 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 488 +               };
 489 +               conf-clk {
 490 +                       pins = "SPI1_CS";
 491 +                       drive-strength = <MTK_DRIVE_6mA>;
 492 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 493 +               };
 494 +               conf-rst {
 495 +                       pins = "PWM0";
 496 +                       drive-strength = <MTK_DRIVE_4mA>;
 497 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 498 +               };
 499 +       };
 500 +};
 501 --- /dev/null
 502 +++ b/arch/arm/dts/mt7981-cmcc-rax3000m-nand.dts
 503 @@ -0,0 +1,77 @@
 504 +// SPDX-License-Identifier: GPL-2.0-only
 505 +
 506 +/dts-v1/;
 507 +#include "mt7981-cmcc-rax3000m.dtsi"
 508 +
 509 +&pinctrl {
 510 +       spi_flash_pins: spi0-pins-func-1 {
 511 +               mux {
 512 +                       function = "flash";
 513 +                       groups = "spi0", "spi0_wp_hold";
 514 +               };
 515 +
 516 +               conf-pu {
 517 +                       pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
 518 +                       drive-strength = <MTK_DRIVE_8mA>;
 519 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_00>;
 520 +               };
 521 +
 522 +               conf-pd {
 523 +                       pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
 524 +                       drive-strength = <MTK_DRIVE_8mA>;
 525 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
 526 +               };
 527 +       };
 528 +};
 529 +
 530 +&spi0 {
 531 +       #address-cells = <1>;
 532 +       #size-cells = <0>;
 533 +       pinctrl-names = "default";
 534 +       pinctrl-0 = <&spi_flash_pins>;
 535 +       status = "okay";
 536 +       must_tx;
 537 +       enhance_timing;
 538 +       dma_ext;
 539 +       ipm_design;
 540 +       support_quad;
 541 +       tick_dly = <2>;
 542 +       sample_sel = <0>;
 543 +
 544 +       spi_nand@0 {
 545 +               compatible = "spi-nand";
 546 +               reg = <0>;
 547 +               spi-max-frequency = <52000000>;
 548 +
 549 +               partitions {
 550 +                       compatible = "fixed-partitions";
 551 +                       #address-cells = <1>;
 552 +                       #size-cells = <1>;
 553 +
 554 +                       partition@0 {
 555 +                               label = "bl2";
 556 +                               reg = <0x0 0x100000>;
 557 +                       };
 558 +
 559 +                       partition@100000 {
 560 +                               label = "orig-env";
 561 +                               reg = <0x100000 0x80000>;
 562 +                       };
 563 +
 564 +                       partition@160000 {
 565 +                               label = "factory";
 566 +                               reg = <0x180000 0x200000>;
 567 +                       };
 568 +
 569 +                       partition@380000 {
 570 +                               label = "fip";
 571 +                               reg = <0x380000 0x200000>;
 572 +                       };
 573 +
 574 +                       partition@580000 {
 575 +                               label = "ubi";
 576 +                               reg = <0x580000 0x7200000>;
 577 +                       };
 578 +               };
 579 +       };
 580 +};
 581 --- /dev/null
 582 +++ b/cmcc_rax3000m-emmc_env
 583 @@ -0,0 +1,55 @@
 584 +ipaddr=192.168.1.1
 585 +serverip=192.168.1.254
 586 +loadaddr=0x46000000
 587 +console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
 588 +bootargs=root=/dev/mmcblk0p65
 589 +bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi
 590 +bootconf=config-1#mt7981b-cmcc-rax3000m-emmc
 591 +bootdelay=0
 592 +bootfile=openwrt-mediatek-filogic-cmcc_rax3000m-initramfs-recovery.itb
 593 +bootfile_bl2=openwrt-mediatek-filogic-cmcc_rax3000m-emmc-preloader.bin
 594 +bootfile_fip=openwrt-mediatek-filogic-cmcc_rax3000m-emmc-bl31-uboot.fip
 595 +bootfile_upg=openwrt-mediatek-filogic-cmcc_rax3000m-squashfs-sysupgrade.itb
 596 +bootled_pwr=red:status
 597 +bootled_rec=blue:status
 598 +bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
 599 +bootmenu_default=0
 600 +bootmenu_delay=0
 601 +bootmenu_title=      \e[0;34m( ( ( \e[1;39mOpenWrt\e[0;34m ) ) )  \e[0;36m[eMMC]\e[0m
 602 +bootmenu_0=Initialize environment.=run _firstboot
 603 +bootmenu_0d=Run default boot command.=run boot_default
 604 +bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
 605 +bootmenu_2=Boot production system from eMMC.=run boot_production ; run bootmenu_confirm_return
 606 +bootmenu_3=Boot recovery system from eMMC.=run boot_recovery ; run bootmenu_confirm_return
 607 +bootmenu_4=Load production system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
 608 +bootmenu_5=Load recovery system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
 609 +bootmenu_6=\e[31mLoad BL31+U-Boot FIP via TFTP then write to eMMC.\e[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return
 610 +bootmenu_7=\e[31mLoad BL2 preloader via TFTP then write to eMMC.\e[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return
 611 +bootmenu_8=Reboot.=reset
 612 +bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset
 613 +boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
 614 +boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
 615 +boot_production=led $bootled_pwr on ; run emmc_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off
 616 +boot_recovery=led $bootled_rec on ; run emmc_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off
 617 +boot_emmc=run boot_production ; run boot_recovery
 618 +boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
 619 +boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run emmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
 620 +boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run emmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
 621 +boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run emmc_write_fip
 622 +boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run emmc_write_bl2
 623 +boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
 624 +mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size
 625 +mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200
 626 +part_default=production
 627 +part_recovery=recovery
 628 +reset_factory=eraseenv && reset
 629 +emmc_read_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol
 630 +emmc_read_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol
 631 +emmc_write_bl2=mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $fileaddr 0x0 0x400 ; mmc partconf 0 1 1 0
 632 +emmc_write_fip=mmc erase 0x3400 0x2000 && mmc write $fileaddr 0x3400 0x2000 && mmc erase 0x2000 0x800
 633 +emmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol
 634 +emmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol
 635 +_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv
 636 +_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
 637 +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
 638 +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       \e[33m$ver\e[0m"
 639 --- /dev/null
 640 +++ b/cmcc_rax3000m-nand_env
 641 @@ -0,0 +1,56 @@
 642 +ipaddr=192.168.1.1
 643 +serverip=192.168.1.254
 644 +loadaddr=0x46000000
 645 +console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
 646 +bootconf=config-1#mt7981b-cmcc-rax3000m-nand
 647 +bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi
 648 +bootdelay=0
 649 +bootfile=openwrt-mediatek-filogic-cmcc_rax3000m-initramfs-recovery.itb
 650 +bootfile_bl2=openwrt-mediatek-filogic-cmcc_rax3000m-nand-preloader.bin
 651 +bootfile_fip=openwrt-mediatek-filogic-cmcc_rax3000m-nand-bl31-uboot.fip
 652 +bootfile_upg=openwrt-mediatek-filogic-cmcc_rax3000m-squashfs-sysupgrade.itb
 653 +bootled_pwr=red:status
 654 +bootled_rec=blue:status
 655 +bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
 656 +bootmenu_default=0
 657 +bootmenu_delay=0
 658 +bootmenu_title=      \e[0;34m( ( ( \e[1;39mOpenWrt\e[0;34m ) ) )  \e[0;36m[SPI-NAND]\e[0m
 659 +bootmenu_0=Initialize environment.=run _firstboot
 660 +bootmenu_0d=Run default boot command.=run boot_default
 661 +bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
 662 +bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return
 663 +bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return
 664 +bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
 665 +bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
 666 +bootmenu_6=\e[31mLoad BL31+U-Boot FIP via TFTP then write to NAND.\e[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return
 667 +bootmenu_7=\e[31mLoad BL2 preloader via TFTP then write to NAND.\e[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return
 668 +bootmenu_8=Reboot.=reset
 669 +bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset
 670 +boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
 671 +boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
 672 +boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off
 673 +boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off
 674 +boot_ubi=run boot_production ; run boot_recovery ; run boot_tftp_forever
 675 +boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
 676 +boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
 677 +boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
 678 +boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
 679 +boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory
 680 +boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2
 681 +part_default=production
 682 +part_recovery=recovery
 683 +reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800
 684 +mtd_write_fip=mtd erase fip && mtd write fip $loadaddr
 685 +mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr
 686 +ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 || run ubi_format
 687 +ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset
 688 +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
 689 +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs
 690 +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery
 691 +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
 692 +ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize
 693 +ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize
 694 +_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv
 695 +_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
 696 +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
 697 +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       \e[33m$ver\e[0m"