ipq807x: sax1v1k: fix sysupgrade not touching rootfs_data
[openwrt/openwrt.git] / target / linux / ath79 / dts / ar9344_watchguard_ap200.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include <dt-bindings/leds/common.h>
4
5 #include "ar9344_senao_ap-dual.dtsi"
6
7 / {
8 compatible = "watchguard,ap200", "qca,ar9344";
9 model = "WatchGuard AP200";
10
11 aliases {
12 led-boot = &led_power_amber;
13 led-failsafe = &led_power_amber;
14 led-running = &led_power_green;
15 led-upgrade = &led_power_amber;
16 };
17
18 leds {
19 compatible = "gpio-leds";
20
21 led_power_amber: power_amber {
22 function = LED_FUNCTION_POWER;
23 color = <LED_COLOR_ID_AMBER>;
24 gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
25 };
26
27 led_power_green: power_green {
28 function = LED_FUNCTION_POWER;
29 color = <LED_COLOR_ID_GREEN>;
30 gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
31 default-state = "on";
32 };
33
34 lan_data {
35 label = "orange:lan_data";
36 gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
37 };
38
39 lan_link {
40 label = "green:lan_link";
41 gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
42 };
43
44 wifi_amber {
45 label = "amber:wifi";
46 gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
47 linux,default-trigger = "phy1tpt";
48 };
49
50 wifi_green {
51 label = "green:wifi";
52 gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
53 linux,default-trigger = "phy0tpt";
54 };
55 };
56 };
57
58 &ref {
59 clock-frequency = <25000000>;
60 };
61
62 &eth0 {
63 nvmem-cells = <&macaddr_art_0 (-2)>;
64 nvmem-cell-names = "mac-address";
65 };
66
67 &pcie {
68 wifi@0,0 {
69 nvmem-cells = <&macaddr_art_0 (-1)>, <&calibration_art_5000>;
70 nvmem-cell-names = "mac-address", "calibration";
71 };
72 };
73
74 &wmac {
75 nvmem-cells = <&macaddr_art_0 (-2)>, <&calibration_art_1000>;
76 nvmem-cell-names = "mac-address", "calibration";
77 };
78
79 &art {
80 nvmem-layout {
81 compatible = "fixed-layout";
82 #address-cells = <1>;
83 #size-cells = <1>;
84
85 macaddr_art_0: macaddr@0 {
86 compatible = "mac-base";
87 reg = <0x0 0x6>;
88 #nvmem-cell-cells = <1>;
89 };
90
91 calibration_art_1000: calibration@1000 {
92 reg = <0x1000 0x440>;
93 };
94
95 calibration_art_5000: calibration@5000 {
96 reg = <0x5000 0x440>;
97 };
98 };
99 };