1 From fea7cfb83d1a2782e39cd101dd44ed2548539de5 Mon Sep 17 00:00:00 2001
2 From: Luo Jie <quic_luoj@quicinc.com>
3 Date: Sun, 16 Jul 2023 16:49:22 +0800
4 Subject: [PATCH 4/6] net: phy: at803x: support qca8081 1G chip type
6 The qca8081 1G chip version does not support 2.5 capability, which
7 is distinguished from qca8081 2.5G chip according to the bit0 of
8 register mmd7.0x901d, the 1G version chip also has the same PHY ID
9 as the normal qca8081 2.5G chip.
11 Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
12 Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
13 Signed-off-by: David S. Miller <davem@davemloft.net>
15 drivers/net/phy/at803x.c | 15 +++++++++++++++
16 1 file changed, 15 insertions(+)
18 --- a/drivers/net/phy/at803x.c
19 +++ b/drivers/net/phy/at803x.c
21 #define QCA808X_CDT_STATUS_STAT_OPEN 2
22 #define QCA808X_CDT_STATUS_STAT_SHORT 3
24 +/* QCA808X 1G chip type */
25 +#define QCA808X_PHY_MMD7_CHIP_TYPE 0x901d
26 +#define QCA808X_PHY_CHIP_TYPE_1G BIT(0)
28 MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
29 MODULE_AUTHOR("Matus Ujhelyi");
30 MODULE_LICENSE("GPL");
31 @@ -2005,6 +2009,17 @@ static int qca808x_get_features(struct p
33 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
35 + /* As for the qca8081 1G version chip, the 2500baseT ability is also
36 + * existed in the bit0 of MMD1.21, we need to remove it manually if
37 + * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d.
39 + ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
43 + if (QCA808X_PHY_CHIP_TYPE_1G & ret)
44 + linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);