2 * B53 switch driver main logic
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21 #include <linux/delay.h>
22 #include <linux/export.h>
23 #include <linux/gpio.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/switch.h>
27 #include <linux/phy.h>
29 #include <linux/of_net.h>
30 #include <linux/platform_data/b53.h>
35 /* buffer size needed for displaying all MIBs with max'd values */
36 #define B53_BUF_SIZE 1188
44 /* BCM5365 MIB counters */
45 static const struct b53_mib_desc b53_mibs_65
[] = {
46 { 8, 0x00, "TxOctets" },
47 { 4, 0x08, "TxDropPkts" },
48 { 4, 0x10, "TxBroadcastPkts" },
49 { 4, 0x14, "TxMulticastPkts" },
50 { 4, 0x18, "TxUnicastPkts" },
51 { 4, 0x1c, "TxCollisions" },
52 { 4, 0x20, "TxSingleCollision" },
53 { 4, 0x24, "TxMultipleCollision" },
54 { 4, 0x28, "TxDeferredTransmit" },
55 { 4, 0x2c, "TxLateCollision" },
56 { 4, 0x30, "TxExcessiveCollision" },
57 { 4, 0x38, "TxPausePkts" },
58 { 8, 0x44, "RxOctets" },
59 { 4, 0x4c, "RxUndersizePkts" },
60 { 4, 0x50, "RxPausePkts" },
61 { 4, 0x54, "Pkts64Octets" },
62 { 4, 0x58, "Pkts65to127Octets" },
63 { 4, 0x5c, "Pkts128to255Octets" },
64 { 4, 0x60, "Pkts256to511Octets" },
65 { 4, 0x64, "Pkts512to1023Octets" },
66 { 4, 0x68, "Pkts1024to1522Octets" },
67 { 4, 0x6c, "RxOversizePkts" },
68 { 4, 0x70, "RxJabbers" },
69 { 4, 0x74, "RxAlignmentErrors" },
70 { 4, 0x78, "RxFCSErrors" },
71 { 8, 0x7c, "RxGoodOctets" },
72 { 4, 0x84, "RxDropPkts" },
73 { 4, 0x88, "RxUnicastPkts" },
74 { 4, 0x8c, "RxMulticastPkts" },
75 { 4, 0x90, "RxBroadcastPkts" },
76 { 4, 0x94, "RxSAChanges" },
77 { 4, 0x98, "RxFragments" },
81 #define B63XX_MIB_TXB_ID 0 /* TxOctets */
82 #define B63XX_MIB_RXB_ID 14 /* RxOctets */
84 /* BCM63xx MIB counters */
85 static const struct b53_mib_desc b53_mibs_63xx
[] = {
86 { 8, 0x00, "TxOctets" },
87 { 4, 0x08, "TxDropPkts" },
88 { 4, 0x0c, "TxQoSPkts" },
89 { 4, 0x10, "TxBroadcastPkts" },
90 { 4, 0x14, "TxMulticastPkts" },
91 { 4, 0x18, "TxUnicastPkts" },
92 { 4, 0x1c, "TxCollisions" },
93 { 4, 0x20, "TxSingleCollision" },
94 { 4, 0x24, "TxMultipleCollision" },
95 { 4, 0x28, "TxDeferredTransmit" },
96 { 4, 0x2c, "TxLateCollision" },
97 { 4, 0x30, "TxExcessiveCollision" },
98 { 4, 0x38, "TxPausePkts" },
99 { 8, 0x3c, "TxQoSOctets" },
100 { 8, 0x44, "RxOctets" },
101 { 4, 0x4c, "RxUndersizePkts" },
102 { 4, 0x50, "RxPausePkts" },
103 { 4, 0x54, "Pkts64Octets" },
104 { 4, 0x58, "Pkts65to127Octets" },
105 { 4, 0x5c, "Pkts128to255Octets" },
106 { 4, 0x60, "Pkts256to511Octets" },
107 { 4, 0x64, "Pkts512to1023Octets" },
108 { 4, 0x68, "Pkts1024to1522Octets" },
109 { 4, 0x6c, "RxOversizePkts" },
110 { 4, 0x70, "RxJabbers" },
111 { 4, 0x74, "RxAlignmentErrors" },
112 { 4, 0x78, "RxFCSErrors" },
113 { 8, 0x7c, "RxGoodOctets" },
114 { 4, 0x84, "RxDropPkts" },
115 { 4, 0x88, "RxUnicastPkts" },
116 { 4, 0x8c, "RxMulticastPkts" },
117 { 4, 0x90, "RxBroadcastPkts" },
118 { 4, 0x94, "RxSAChanges" },
119 { 4, 0x98, "RxFragments" },
120 { 4, 0xa0, "RxSymbolErrors" },
121 { 4, 0xa4, "RxQoSPkts" },
122 { 8, 0xa8, "RxQoSOctets" },
123 { 4, 0xb0, "Pkts1523to2047Octets" },
124 { 4, 0xb4, "Pkts2048to4095Octets" },
125 { 4, 0xb8, "Pkts4096to8191Octets" },
126 { 4, 0xbc, "Pkts8192to9728Octets" },
127 { 4, 0xc0, "RxDiscarded" },
131 #define B53XX_MIB_TXB_ID 0 /* TxOctets */
132 #define B53XX_MIB_RXB_ID 12 /* RxOctets */
135 static const struct b53_mib_desc b53_mibs
[] = {
136 { 8, 0x00, "TxOctets" },
137 { 4, 0x08, "TxDropPkts" },
138 { 4, 0x10, "TxBroadcastPkts" },
139 { 4, 0x14, "TxMulticastPkts" },
140 { 4, 0x18, "TxUnicastPkts" },
141 { 4, 0x1c, "TxCollisions" },
142 { 4, 0x20, "TxSingleCollision" },
143 { 4, 0x24, "TxMultipleCollision" },
144 { 4, 0x28, "TxDeferredTransmit" },
145 { 4, 0x2c, "TxLateCollision" },
146 { 4, 0x30, "TxExcessiveCollision" },
147 { 4, 0x38, "TxPausePkts" },
148 { 8, 0x50, "RxOctets" },
149 { 4, 0x58, "RxUndersizePkts" },
150 { 4, 0x5c, "RxPausePkts" },
151 { 4, 0x60, "Pkts64Octets" },
152 { 4, 0x64, "Pkts65to127Octets" },
153 { 4, 0x68, "Pkts128to255Octets" },
154 { 4, 0x6c, "Pkts256to511Octets" },
155 { 4, 0x70, "Pkts512to1023Octets" },
156 { 4, 0x74, "Pkts1024to1522Octets" },
157 { 4, 0x78, "RxOversizePkts" },
158 { 4, 0x7c, "RxJabbers" },
159 { 4, 0x80, "RxAlignmentErrors" },
160 { 4, 0x84, "RxFCSErrors" },
161 { 8, 0x88, "RxGoodOctets" },
162 { 4, 0x90, "RxDropPkts" },
163 { 4, 0x94, "RxUnicastPkts" },
164 { 4, 0x98, "RxMulticastPkts" },
165 { 4, 0x9c, "RxBroadcastPkts" },
166 { 4, 0xa0, "RxSAChanges" },
167 { 4, 0xa4, "RxFragments" },
168 { 4, 0xa8, "RxJumboPkts" },
169 { 4, 0xac, "RxSymbolErrors" },
170 { 4, 0xc0, "RxDiscarded" },
174 static int b53_do_vlan_op(struct b53_device
*dev
, u8 op
)
178 b53_write8(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[0], VTA_START_CMD
| op
);
180 for (i
= 0; i
< 10; i
++) {
183 b53_read8(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[0], &vta
);
184 if (!(vta
& VTA_START_CMD
))
187 usleep_range(100, 200);
193 static void b53_set_vlan_entry(struct b53_device
*dev
, u16 vid
, u16 members
,
200 entry
= ((untag
& VA_UNTAG_MASK_25
) << VA_UNTAG_S_25
) |
202 if (dev
->core_rev
>= 3)
203 entry
|= VA_VALID_25_R4
| vid
<< VA_VID_HIGH_S
;
205 entry
|= VA_VALID_25
;
208 b53_write32(dev
, B53_VLAN_PAGE
, B53_VLAN_WRITE_25
, entry
);
209 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_25
, vid
|
210 VTA_RW_STATE_WR
| VTA_RW_OP_EN
);
211 } else if (is5365(dev
)) {
215 entry
= ((untag
& VA_UNTAG_MASK_65
) << VA_UNTAG_S_65
) |
216 members
| VA_VALID_65
;
218 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_WRITE_65
, entry
);
219 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_65
, vid
|
220 VTA_RW_STATE_WR
| VTA_RW_OP_EN
);
222 b53_write16(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[1], vid
);
223 b53_write32(dev
, B53_ARLIO_PAGE
, dev
->vta_regs
[2],
224 (untag
<< VTE_UNTAG_S
) | members
);
226 b53_do_vlan_op(dev
, VTA_CMD_WRITE
);
230 void b53_set_forwarding(struct b53_device
*dev
, int enable
)
234 b53_read8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, &mgmt
);
237 mgmt
|= SM_SW_FWD_EN
;
239 mgmt
&= ~SM_SW_FWD_EN
;
241 b53_write8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, mgmt
);
244 static void b53_enable_vlan(struct b53_device
*dev
, int enable
)
246 u8 mgmt
, vc0
, vc1
, vc4
= 0, vc5
;
248 b53_read8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, &mgmt
);
249 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL0
, &vc0
);
250 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL1
, &vc1
);
252 if (is5325(dev
) || is5365(dev
)) {
253 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_25
, &vc4
);
254 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5_25
, &vc5
);
255 } else if (is63xx(dev
)) {
256 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_63XX
, &vc4
);
257 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5_63XX
, &vc5
);
259 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4
, &vc4
);
260 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5
, &vc5
);
263 mgmt
&= ~SM_SW_FWD_MODE
;
266 vc0
|= VC0_VLAN_EN
| VC0_VID_CHK_EN
| VC0_VID_HASH_VID
;
267 vc1
|= VC1_RX_MCST_UNTAG_EN
| VC1_RX_MCST_FWD_EN
;
268 vc4
&= ~VC4_ING_VID_CHECK_MASK
;
269 vc4
|= VC4_ING_VID_VIO_DROP
<< VC4_ING_VID_CHECK_S
;
270 vc5
|= VC5_DROP_VTABLE_MISS
;
273 vc0
&= ~VC0_RESERVED_1
;
275 if (is5325(dev
) || is5365(dev
))
276 vc1
|= VC1_RX_MCST_TAG_EN
;
278 if (!is5325(dev
) && !is5365(dev
)) {
279 if (dev
->allow_vid_4095
)
280 vc5
|= VC5_VID_FFF_EN
;
282 vc5
&= ~VC5_VID_FFF_EN
;
285 vc0
&= ~(VC0_VLAN_EN
| VC0_VID_CHK_EN
| VC0_VID_HASH_VID
);
286 vc1
&= ~(VC1_RX_MCST_UNTAG_EN
| VC1_RX_MCST_FWD_EN
);
287 vc4
&= ~VC4_ING_VID_CHECK_MASK
;
288 vc5
&= ~VC5_DROP_VTABLE_MISS
;
290 if (is5325(dev
) || is5365(dev
))
291 vc4
|= VC4_ING_VID_VIO_FWD
<< VC4_ING_VID_CHECK_S
;
293 vc4
|= VC4_ING_VID_VIO_TO_IMP
<< VC4_ING_VID_CHECK_S
;
295 if (is5325(dev
) || is5365(dev
))
296 vc1
&= ~VC1_RX_MCST_TAG_EN
;
298 if (!is5325(dev
) && !is5365(dev
))
299 vc5
&= ~VC5_VID_FFF_EN
;
302 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL0
, vc0
);
303 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL1
, vc1
);
305 if (is5325(dev
) || is5365(dev
)) {
306 /* enable the high 8 bit vid check on 5325 */
307 if (is5325(dev
) && enable
)
308 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL3
,
311 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL3
, 0);
313 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_25
, vc4
);
314 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5_25
, vc5
);
315 } else if (is63xx(dev
)) {
316 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL3_63XX
, 0);
317 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_63XX
, vc4
);
318 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5_63XX
, vc5
);
320 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL3
, 0);
321 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4
, vc4
);
322 b53_write8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL5
, vc5
);
325 b53_write8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, mgmt
);
328 static int b53_set_jumbo(struct b53_device
*dev
, int enable
, int allow_10_100
)
331 u16 max_size
= JMS_MIN_SIZE
;
333 if (is5325(dev
) || is5365(dev
))
337 port_mask
= dev
->enabled_ports
;
338 max_size
= JMS_MAX_SIZE
;
340 port_mask
|= JPM_10_100_JUMBO_EN
;
343 b53_write32(dev
, B53_JUMBO_PAGE
, dev
->jumbo_pm_reg
, port_mask
);
344 return b53_write16(dev
, B53_JUMBO_PAGE
, dev
->jumbo_size_reg
, max_size
);
347 static int b53_flush_arl(struct b53_device
*dev
)
351 b53_write8(dev
, B53_CTRL_PAGE
, B53_FAST_AGE_CTRL
,
352 FAST_AGE_DONE
| FAST_AGE_DYNAMIC
| FAST_AGE_STATIC
);
354 for (i
= 0; i
< 10; i
++) {
357 b53_read8(dev
, B53_CTRL_PAGE
, B53_FAST_AGE_CTRL
,
360 if (!(fast_age_ctrl
& FAST_AGE_DONE
))
366 pr_warn("time out while flushing ARL\n");
371 static void b53_enable_ports(struct b53_device
*dev
)
375 b53_for_each_port(dev
, i
) {
380 * prevent leaking packets between wan and lan in unmanaged
381 * mode through port vlans.
383 if (dev
->enable_vlan
|| is_cpu_port(dev
, i
))
385 else if (is531x5(dev
) || is5301x(dev
))
386 /* BCM53115 may use a different port as cpu port */
387 pvlan_mask
= BIT(dev
->sw_dev
.cpu_port
);
389 pvlan_mask
= BIT(B53_CPU_PORT
);
391 /* BCM5325 CPU port is at 8 */
392 if ((is5325(dev
) || is5365(dev
)) && i
== B53_CPU_PORT_25
)
395 if (dev
->chip_id
== BCM5398_DEVICE_ID
&& (i
== 6 || i
== 7))
396 /* disable unused ports 6 & 7 */
397 port_ctrl
= PORT_CTRL_RX_DISABLE
| PORT_CTRL_TX_DISABLE
;
398 else if (i
== B53_CPU_PORT
)
399 port_ctrl
= PORT_CTRL_RX_BCST_EN
|
400 PORT_CTRL_RX_MCST_EN
|
401 PORT_CTRL_RX_UCST_EN
;
405 b53_write16(dev
, B53_PVLAN_PAGE
, B53_PVLAN_PORT_MASK(i
),
408 /* port state is handled by bcm63xx_enet driver */
409 if (!is63xx(dev
) && !(is5301x(dev
) && i
== 6))
410 b53_write8(dev
, B53_CTRL_PAGE
, B53_PORT_CTRL(i
),
415 static void b53_enable_mib(struct b53_device
*dev
)
419 b53_read8(dev
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, &gc
);
421 gc
&= ~(GC_RESET_MIB
| GC_MIB_AC_EN
);
423 b53_write8(dev
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, gc
);
426 static int b53_apply(struct b53_device
*dev
)
430 /* clear all vlan entries */
431 if (is5325(dev
) || is5365(dev
)) {
432 for (i
= 1; i
< dev
->sw_dev
.vlans
; i
++)
433 b53_set_vlan_entry(dev
, i
, 0, 0);
435 b53_do_vlan_op(dev
, VTA_CMD_CLEAR
);
438 b53_enable_vlan(dev
, dev
->enable_vlan
);
440 /* fill VLAN table */
441 if (dev
->enable_vlan
) {
442 for (i
= 0; i
< dev
->sw_dev
.vlans
; i
++) {
443 struct b53_vlan
*vlan
= &dev
->vlans
[i
];
448 b53_set_vlan_entry(dev
, i
, vlan
->members
, vlan
->untag
);
451 b53_for_each_port(dev
, i
)
452 b53_write16(dev
, B53_VLAN_PAGE
,
453 B53_VLAN_PORT_DEF_TAG(i
),
456 b53_for_each_port(dev
, i
)
457 b53_write16(dev
, B53_VLAN_PAGE
,
458 B53_VLAN_PORT_DEF_TAG(i
), 1);
462 b53_enable_ports(dev
);
464 if (!is5325(dev
) && !is5365(dev
))
465 b53_set_jumbo(dev
, dev
->enable_jumbo
, 1);
470 static void b53_switch_reset_gpio(struct b53_device
*dev
)
472 int gpio
= dev
->reset_gpio
;
478 * Reset sequence: RESET low(50ms)->high(20ms)
480 gpio_set_value(gpio
, 0);
483 gpio_set_value(gpio
, 1);
486 dev
->current_page
= 0xff;
489 static int b53_configure_ports_of(struct b53_device
*dev
)
491 struct device_node
*dn
, *pn
;
494 dn
= of_get_child_by_name(dev_of_node(dev
->dev
), "ports");
496 for_each_available_child_of_node(dn
, pn
) {
497 struct device_node
*fixed_link
;
499 if (of_property_read_u32(pn
, "reg", &port_num
))
502 if (port_num
> B53_CPU_PORT
)
505 fixed_link
= of_get_child_by_name(pn
, "fixed-link");
508 u8 po
= GMII_PO_LINK
;
509 phy_interface_t mode
;
511 of_get_phy_mode(pn
, &mode
);
513 if (!of_property_read_u32(fixed_link
, "speed", &spd
)) {
516 po
|= GMII_PO_SPEED_10M
;
519 po
|= GMII_PO_SPEED_100M
;
522 if (is_imp_port(dev
, port_num
))
523 po
|= PORT_OVERRIDE_SPEED_2000M
;
525 po
|= GMII_PO_SPEED_2000M
;
528 po
|= GMII_PO_SPEED_1000M
;
533 if (of_property_read_bool(fixed_link
, "full-duplex"))
534 po
|= PORT_OVERRIDE_FULL_DUPLEX
;
535 if (of_property_read_bool(fixed_link
, "pause"))
536 po
|= GMII_PO_RX_FLOW
;
537 if (of_property_read_bool(fixed_link
, "asym-pause"))
538 po
|= GMII_PO_TX_FLOW
;
540 if (is_imp_port(dev
, port_num
)) {
541 po
|= PORT_OVERRIDE_EN
;
544 mode
== PHY_INTERFACE_MODE_REVMII
)
545 po
|= PORT_OVERRIDE_RV_MII_25
;
547 b53_write8(dev
, B53_CTRL_PAGE
,
548 B53_PORT_OVERRIDE_CTRL
, po
);
551 mode
== PHY_INTERFACE_MODE_REVMII
) {
552 b53_read8(dev
, B53_CTRL_PAGE
,
553 B53_PORT_OVERRIDE_CTRL
, &po
);
554 if (!(po
& PORT_OVERRIDE_RV_MII_25
))
555 pr_err("Failed to enable reverse MII mode\n");
560 b53_write8(dev
, B53_CTRL_PAGE
,
561 B53_GMII_PORT_OVERRIDE_CTRL(port_num
),
570 static int b53_configure_ports(struct b53_device
*dev
)
572 u8 cpu_port
= dev
->sw_dev
.cpu_port
;
574 /* configure MII port if necessary */
576 u8 mii_port_override
;
578 b53_read8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
580 /* reverse mii needs to be enabled */
581 if (!(mii_port_override
& PORT_OVERRIDE_RV_MII_25
)) {
582 b53_write8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
583 mii_port_override
| PORT_OVERRIDE_RV_MII_25
);
584 b53_read8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
587 if (!(mii_port_override
& PORT_OVERRIDE_RV_MII_25
)) {
588 pr_err("Failed to enable reverse MII mode\n");
592 } else if (is531x5(dev
) && cpu_port
== B53_CPU_PORT
) {
593 u8 mii_port_override
;
595 b53_read8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
597 b53_write8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
598 mii_port_override
| PORT_OVERRIDE_EN
|
601 /* BCM47189 has another interface connected to the port 5 */
602 if (dev
->enabled_ports
& BIT(5)) {
603 u8 po_reg
= B53_GMII_PORT_OVERRIDE_CTRL(5);
606 b53_read8(dev
, B53_CTRL_PAGE
, po_reg
, &gmii_po
);
607 gmii_po
|= GMII_PO_LINK
|
611 b53_write8(dev
, B53_CTRL_PAGE
, po_reg
, gmii_po
);
613 } else if (is5301x(dev
)) {
615 u8 mii_port_override
;
617 b53_read8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
619 mii_port_override
|= PORT_OVERRIDE_LINK
|
620 PORT_OVERRIDE_RX_FLOW
|
621 PORT_OVERRIDE_TX_FLOW
|
622 PORT_OVERRIDE_SPEED_2000M
|
624 b53_write8(dev
, B53_CTRL_PAGE
, B53_PORT_OVERRIDE_CTRL
,
627 /* TODO: Ports 5 & 7 require some extra handling */
629 u8 po_reg
= B53_GMII_PORT_OVERRIDE_CTRL(cpu_port
);
632 b53_read8(dev
, B53_CTRL_PAGE
, po_reg
, &gmii_po
);
633 gmii_po
|= GMII_PO_LINK
|
638 b53_write8(dev
, B53_CTRL_PAGE
, po_reg
, gmii_po
);
645 static int b53_switch_reset(struct b53_device
*dev
)
650 b53_switch_reset_gpio(dev
);
653 b53_write8(dev
, B53_CTRL_PAGE
, B53_SOFTRESET
, 0x83);
654 b53_write8(dev
, B53_CTRL_PAGE
, B53_SOFTRESET
, 0x00);
657 b53_read8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, &mgmt
);
659 if (!(mgmt
& SM_SW_FWD_EN
)) {
660 mgmt
&= ~SM_SW_FWD_MODE
;
661 mgmt
|= SM_SW_FWD_EN
;
663 b53_write8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, mgmt
);
664 b53_read8(dev
, B53_CTRL_PAGE
, B53_SWITCH_MODE
, &mgmt
);
666 if (!(mgmt
& SM_SW_FWD_EN
)) {
667 pr_err("Failed to enable switch!\n");
672 /* enable all ports */
673 b53_enable_ports(dev
);
675 if (dev
->dev
->of_node
)
676 ret
= b53_configure_ports_of(dev
);
678 ret
= b53_configure_ports(dev
);
685 return b53_flush_arl(dev
);
689 * Swconfig glue functions
692 static int b53_global_get_vlan_enable(struct switch_dev
*dev
,
693 const struct switch_attr
*attr
,
694 struct switch_val
*val
)
696 struct b53_device
*priv
= sw_to_b53(dev
);
698 val
->value
.i
= priv
->enable_vlan
;
703 static int b53_global_set_vlan_enable(struct switch_dev
*dev
,
704 const struct switch_attr
*attr
,
705 struct switch_val
*val
)
707 struct b53_device
*priv
= sw_to_b53(dev
);
709 priv
->enable_vlan
= val
->value
.i
;
714 static int b53_global_get_jumbo_enable(struct switch_dev
*dev
,
715 const struct switch_attr
*attr
,
716 struct switch_val
*val
)
718 struct b53_device
*priv
= sw_to_b53(dev
);
720 val
->value
.i
= priv
->enable_jumbo
;
725 static int b53_global_set_jumbo_enable(struct switch_dev
*dev
,
726 const struct switch_attr
*attr
,
727 struct switch_val
*val
)
729 struct b53_device
*priv
= sw_to_b53(dev
);
731 priv
->enable_jumbo
= val
->value
.i
;
736 static int b53_global_get_4095_enable(struct switch_dev
*dev
,
737 const struct switch_attr
*attr
,
738 struct switch_val
*val
)
740 struct b53_device
*priv
= sw_to_b53(dev
);
742 val
->value
.i
= priv
->allow_vid_4095
;
747 static int b53_global_set_4095_enable(struct switch_dev
*dev
,
748 const struct switch_attr
*attr
,
749 struct switch_val
*val
)
751 struct b53_device
*priv
= sw_to_b53(dev
);
753 priv
->allow_vid_4095
= val
->value
.i
;
758 static int b53_global_get_ports(struct switch_dev
*dev
,
759 const struct switch_attr
*attr
,
760 struct switch_val
*val
)
762 struct b53_device
*priv
= sw_to_b53(dev
);
764 val
->len
= snprintf(priv
->buf
, B53_BUF_SIZE
, "0x%04x",
765 priv
->enabled_ports
);
766 val
->value
.s
= priv
->buf
;
771 static int b53_port_get_pvid(struct switch_dev
*dev
, int port
, int *val
)
773 struct b53_device
*priv
= sw_to_b53(dev
);
775 *val
= priv
->ports
[port
].pvid
;
780 static int b53_port_set_pvid(struct switch_dev
*dev
, int port
, int val
)
782 struct b53_device
*priv
= sw_to_b53(dev
);
784 if (val
> 15 && is5325(priv
))
786 if (val
== 4095 && !priv
->allow_vid_4095
)
789 priv
->ports
[port
].pvid
= val
;
794 static int b53_vlan_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
796 struct b53_device
*priv
= sw_to_b53(dev
);
797 struct switch_port
*port
= &val
->value
.ports
[0];
798 struct b53_vlan
*vlan
= &priv
->vlans
[val
->port_vlan
];
806 for (i
= 0; i
< dev
->ports
; i
++) {
807 if (!(vlan
->members
& BIT(i
)))
811 if (!(vlan
->untag
& BIT(i
)))
812 port
->flags
= BIT(SWITCH_PORT_FLAG_TAGGED
);
824 static int b53_vlan_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
826 struct b53_device
*priv
= sw_to_b53(dev
);
827 struct switch_port
*port
;
828 struct b53_vlan
*vlan
= &priv
->vlans
[val
->port_vlan
];
831 /* only BCM5325 and BCM5365 supports VID 0 */
832 if (val
->port_vlan
== 0 && !is5325(priv
) && !is5365(priv
))
835 /* VLAN 4095 needs special handling */
836 if (val
->port_vlan
== 4095 && !priv
->allow_vid_4095
)
839 port
= &val
->value
.ports
[0];
842 for (i
= 0; i
< val
->len
; i
++, port
++) {
843 vlan
->members
|= BIT(port
->id
);
845 if (!(port
->flags
& BIT(SWITCH_PORT_FLAG_TAGGED
))) {
846 vlan
->untag
|= BIT(port
->id
);
847 priv
->ports
[port
->id
].pvid
= val
->port_vlan
;
851 /* ignore disabled ports */
852 vlan
->members
&= priv
->enabled_ports
;
853 vlan
->untag
&= priv
->enabled_ports
;
858 static int b53_port_get_link(struct switch_dev
*dev
, int port
,
859 struct switch_port_link
*link
)
861 struct b53_device
*priv
= sw_to_b53(dev
);
863 if (is_cpu_port(priv
, port
)) {
866 link
->speed
= is5325(priv
) || is5365(priv
) ?
867 SWITCH_PORT_SPEED_100
: SWITCH_PORT_SPEED_1000
;
869 } else if (priv
->enabled_ports
& BIT(port
)) {
873 b53_read16(priv
, B53_STAT_PAGE
, B53_LINK_STAT
, &lnk
);
874 b53_read16(priv
, B53_STAT_PAGE
, priv
->duplex_reg
, &duplex
);
876 lnk
= (lnk
>> port
) & 1;
877 duplex
= (duplex
>> port
) & 1;
879 if (is5325(priv
) || is5365(priv
)) {
882 b53_read16(priv
, B53_STAT_PAGE
, B53_SPEED_STAT
, &tmp
);
883 speed
= SPEED_PORT_FE(tmp
, port
);
885 b53_read32(priv
, B53_STAT_PAGE
, B53_SPEED_STAT
, &speed
);
886 speed
= SPEED_PORT_GE(speed
, port
);
891 link
->duplex
= duplex
;
894 link
->speed
= SWITCH_PORT_SPEED_10
;
896 case SPEED_STAT_100M
:
897 link
->speed
= SWITCH_PORT_SPEED_100
;
899 case SPEED_STAT_1000M
:
900 link
->speed
= SWITCH_PORT_SPEED_1000
;
914 static int b53_port_set_link(struct switch_dev
*sw_dev
, int port
,
915 struct switch_port_link
*link
)
917 struct b53_device
*dev
= sw_to_b53(sw_dev
);
920 * TODO: BCM63XX requires special handling as it can have external phys
921 * and ports might be GE or only FE
926 if (port
== sw_dev
->cpu_port
)
929 if (!(BIT(port
) & dev
->enabled_ports
))
932 if (link
->speed
== SWITCH_PORT_SPEED_1000
&&
933 (is5325(dev
) || is5365(dev
)))
936 if (link
->speed
== SWITCH_PORT_SPEED_1000
&& !link
->duplex
)
939 return switch_generic_set_link(sw_dev
, port
, link
);
942 static int b53_phy_read16(struct switch_dev
*dev
, int addr
, u8 reg
, u16
*value
)
944 struct b53_device
*priv
= sw_to_b53(dev
);
946 if (priv
->ops
->phy_read16
)
947 return priv
->ops
->phy_read16(priv
, addr
, reg
, value
);
949 return b53_read16(priv
, B53_PORT_MII_PAGE(addr
), reg
, value
);
952 static int b53_phy_write16(struct switch_dev
*dev
, int addr
, u8 reg
, u16 value
)
954 struct b53_device
*priv
= sw_to_b53(dev
);
956 if (priv
->ops
->phy_write16
)
957 return priv
->ops
->phy_write16(priv
, addr
, reg
, value
);
959 return b53_write16(priv
, B53_PORT_MII_PAGE(addr
), reg
, value
);
962 static int b53_global_reset_switch(struct switch_dev
*dev
)
964 struct b53_device
*priv
= sw_to_b53(dev
);
967 priv
->enable_vlan
= 0;
968 priv
->enable_jumbo
= 0;
969 priv
->allow_vid_4095
= 0;
971 memset(priv
->vlans
, 0, sizeof(*priv
->vlans
) * dev
->vlans
);
972 memset(priv
->ports
, 0, sizeof(*priv
->ports
) * dev
->ports
);
974 return b53_switch_reset(priv
);
977 static int b53_global_apply_config(struct switch_dev
*dev
)
979 struct b53_device
*priv
= sw_to_b53(dev
);
981 /* disable switching */
982 b53_set_forwarding(priv
, 0);
986 /* enable switching */
987 b53_set_forwarding(priv
, 1);
993 static int b53_global_reset_mib(struct switch_dev
*dev
,
994 const struct switch_attr
*attr
,
995 struct switch_val
*val
)
997 struct b53_device
*priv
= sw_to_b53(dev
);
1000 b53_read8(priv
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, &gc
);
1002 b53_write8(priv
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, gc
| GC_RESET_MIB
);
1004 b53_write8(priv
, B53_MGMT_PAGE
, B53_GLOBAL_CONFIG
, gc
& ~GC_RESET_MIB
);
1010 static int b53_port_get_mib(struct switch_dev
*sw_dev
,
1011 const struct switch_attr
*attr
,
1012 struct switch_val
*val
)
1014 struct b53_device
*dev
= sw_to_b53(sw_dev
);
1015 const struct b53_mib_desc
*mibs
;
1016 int port
= val
->port_vlan
;
1019 if (!(BIT(port
) & dev
->enabled_ports
))
1027 } else if (is63xx(dev
)) {
1028 mibs
= b53_mibs_63xx
;
1035 for (; mibs
->size
> 0; mibs
++) {
1038 if (mibs
->size
== 8) {
1039 b53_read64(dev
, B53_MIB_PAGE(port
), mibs
->offset
, &val
);
1043 b53_read32(dev
, B53_MIB_PAGE(port
), mibs
->offset
,
1048 len
+= snprintf(dev
->buf
+ len
, B53_BUF_SIZE
- len
,
1049 "%-20s: %llu\n", mibs
->name
, val
);
1053 val
->value
.s
= dev
->buf
;
1058 static int b53_port_get_stats(struct switch_dev
*sw_dev
, int port
,
1059 struct switch_port_stats
*stats
)
1061 struct b53_device
*dev
= sw_to_b53(sw_dev
);
1062 const struct b53_mib_desc
*mibs
;
1066 if (!(BIT(port
) & dev
->enabled_ports
))
1069 txb_id
= B53XX_MIB_TXB_ID
;
1070 rxb_id
= B53XX_MIB_RXB_ID
;
1077 } else if (is63xx(dev
)) {
1078 mibs
= b53_mibs_63xx
;
1079 txb_id
= B63XX_MIB_TXB_ID
;
1080 rxb_id
= B63XX_MIB_RXB_ID
;
1087 if (mibs
->size
== 8) {
1088 b53_read64(dev
, B53_MIB_PAGE(port
), mibs
[txb_id
].offset
, &txb
);
1089 b53_read64(dev
, B53_MIB_PAGE(port
), mibs
[rxb_id
].offset
, &rxb
);
1093 b53_read32(dev
, B53_MIB_PAGE(port
), mibs
[txb_id
].offset
, &val32
);
1096 b53_read32(dev
, B53_MIB_PAGE(port
), mibs
[rxb_id
].offset
, &val32
);
1100 stats
->tx_bytes
= txb
;
1101 stats
->rx_bytes
= rxb
;
1106 static struct switch_attr b53_global_ops_25
[] = {
1108 .type
= SWITCH_TYPE_INT
,
1109 .name
= "enable_vlan",
1110 .description
= "Enable VLAN mode",
1111 .set
= b53_global_set_vlan_enable
,
1112 .get
= b53_global_get_vlan_enable
,
1116 .type
= SWITCH_TYPE_STRING
,
1118 .description
= "Available ports (as bitmask)",
1119 .get
= b53_global_get_ports
,
1123 static struct switch_attr b53_global_ops_65
[] = {
1125 .type
= SWITCH_TYPE_INT
,
1126 .name
= "enable_vlan",
1127 .description
= "Enable VLAN mode",
1128 .set
= b53_global_set_vlan_enable
,
1129 .get
= b53_global_get_vlan_enable
,
1133 .type
= SWITCH_TYPE_STRING
,
1135 .description
= "Available ports (as bitmask)",
1136 .get
= b53_global_get_ports
,
1139 .type
= SWITCH_TYPE_INT
,
1140 .name
= "reset_mib",
1141 .description
= "Reset MIB counters",
1142 .set
= b53_global_reset_mib
,
1146 static struct switch_attr b53_global_ops
[] = {
1148 .type
= SWITCH_TYPE_INT
,
1149 .name
= "enable_vlan",
1150 .description
= "Enable VLAN mode",
1151 .set
= b53_global_set_vlan_enable
,
1152 .get
= b53_global_get_vlan_enable
,
1156 .type
= SWITCH_TYPE_STRING
,
1158 .description
= "Available Ports (as bitmask)",
1159 .get
= b53_global_get_ports
,
1162 .type
= SWITCH_TYPE_INT
,
1163 .name
= "reset_mib",
1164 .description
= "Reset MIB counters",
1165 .set
= b53_global_reset_mib
,
1168 .type
= SWITCH_TYPE_INT
,
1169 .name
= "enable_jumbo",
1170 .description
= "Enable Jumbo Frames",
1171 .set
= b53_global_set_jumbo_enable
,
1172 .get
= b53_global_get_jumbo_enable
,
1176 .type
= SWITCH_TYPE_INT
,
1177 .name
= "allow_vid_4095",
1178 .description
= "Allow VID 4095",
1179 .set
= b53_global_set_4095_enable
,
1180 .get
= b53_global_get_4095_enable
,
1185 static struct switch_attr b53_port_ops
[] = {
1187 .type
= SWITCH_TYPE_STRING
,
1189 .description
= "Get port's MIB counters",
1190 .get
= b53_port_get_mib
,
1194 static struct switch_attr b53_no_ops
[] = {
1197 static const struct switch_dev_ops b53_switch_ops_25
= {
1199 .attr
= b53_global_ops_25
,
1200 .n_attr
= ARRAY_SIZE(b53_global_ops_25
),
1204 .n_attr
= ARRAY_SIZE(b53_no_ops
),
1208 .n_attr
= ARRAY_SIZE(b53_no_ops
),
1211 .get_vlan_ports
= b53_vlan_get_ports
,
1212 .set_vlan_ports
= b53_vlan_set_ports
,
1213 .get_port_pvid
= b53_port_get_pvid
,
1214 .set_port_pvid
= b53_port_set_pvid
,
1215 .apply_config
= b53_global_apply_config
,
1216 .reset_switch
= b53_global_reset_switch
,
1217 .get_port_link
= b53_port_get_link
,
1218 .set_port_link
= b53_port_set_link
,
1219 .get_port_stats
= b53_port_get_stats
,
1220 .phy_read16
= b53_phy_read16
,
1221 .phy_write16
= b53_phy_write16
,
1224 static const struct switch_dev_ops b53_switch_ops_65
= {
1226 .attr
= b53_global_ops_65
,
1227 .n_attr
= ARRAY_SIZE(b53_global_ops_65
),
1230 .attr
= b53_port_ops
,
1231 .n_attr
= ARRAY_SIZE(b53_port_ops
),
1235 .n_attr
= ARRAY_SIZE(b53_no_ops
),
1238 .get_vlan_ports
= b53_vlan_get_ports
,
1239 .set_vlan_ports
= b53_vlan_set_ports
,
1240 .get_port_pvid
= b53_port_get_pvid
,
1241 .set_port_pvid
= b53_port_set_pvid
,
1242 .apply_config
= b53_global_apply_config
,
1243 .reset_switch
= b53_global_reset_switch
,
1244 .get_port_link
= b53_port_get_link
,
1245 .set_port_link
= b53_port_set_link
,
1246 .get_port_stats
= b53_port_get_stats
,
1247 .phy_read16
= b53_phy_read16
,
1248 .phy_write16
= b53_phy_write16
,
1251 static const struct switch_dev_ops b53_switch_ops
= {
1253 .attr
= b53_global_ops
,
1254 .n_attr
= ARRAY_SIZE(b53_global_ops
),
1257 .attr
= b53_port_ops
,
1258 .n_attr
= ARRAY_SIZE(b53_port_ops
),
1262 .n_attr
= ARRAY_SIZE(b53_no_ops
),
1265 .get_vlan_ports
= b53_vlan_get_ports
,
1266 .set_vlan_ports
= b53_vlan_set_ports
,
1267 .get_port_pvid
= b53_port_get_pvid
,
1268 .set_port_pvid
= b53_port_set_pvid
,
1269 .apply_config
= b53_global_apply_config
,
1270 .reset_switch
= b53_global_reset_switch
,
1271 .get_port_link
= b53_port_get_link
,
1272 .set_port_link
= b53_port_set_link
,
1273 .get_port_stats
= b53_port_get_stats
,
1274 .phy_read16
= b53_phy_read16
,
1275 .phy_write16
= b53_phy_write16
,
1278 struct b53_chip_data
{
1280 const char *dev_name
;
1289 const struct switch_dev_ops
*sw_ops
;
1292 #define B53_VTA_REGS \
1293 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1294 #define B53_VTA_REGS_9798 \
1295 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1296 #define B53_VTA_REGS_63XX \
1297 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1299 static const struct b53_chip_data b53_switch_chips
[] = {
1301 .chip_id
= BCM5325_DEVICE_ID
,
1302 .dev_name
= "BCM5325",
1305 .enabled_ports
= 0x1f,
1306 .cpu_port
= B53_CPU_PORT_25
,
1307 .duplex_reg
= B53_DUPLEX_STAT_FE
,
1308 .sw_ops
= &b53_switch_ops_25
,
1311 .chip_id
= BCM5365_DEVICE_ID
,
1312 .dev_name
= "BCM5365",
1315 .enabled_ports
= 0x1f,
1316 .cpu_port
= B53_CPU_PORT_25
,
1317 .duplex_reg
= B53_DUPLEX_STAT_FE
,
1318 .sw_ops
= &b53_switch_ops_65
,
1321 .chip_id
= BCM5395_DEVICE_ID
,
1322 .dev_name
= "BCM5395",
1325 .enabled_ports
= 0x1f,
1326 .cpu_port
= B53_CPU_PORT
,
1327 .vta_regs
= B53_VTA_REGS
,
1328 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1329 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1330 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1331 .sw_ops
= &b53_switch_ops
,
1334 .chip_id
= BCM5397_DEVICE_ID
,
1335 .dev_name
= "BCM5397",
1338 .enabled_ports
= 0x1f,
1339 .cpu_port
= B53_CPU_PORT
,
1340 .vta_regs
= B53_VTA_REGS_9798
,
1341 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1342 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1343 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1344 .sw_ops
= &b53_switch_ops
,
1347 .chip_id
= BCM5398_DEVICE_ID
,
1348 .dev_name
= "BCM5398",
1351 .enabled_ports
= 0x7f,
1352 .cpu_port
= B53_CPU_PORT
,
1353 .vta_regs
= B53_VTA_REGS_9798
,
1354 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1355 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1356 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1357 .sw_ops
= &b53_switch_ops
,
1360 .chip_id
= BCM53115_DEVICE_ID
,
1361 .dev_name
= "BCM53115",
1362 .alias
= "bcm53115",
1364 .enabled_ports
= 0x1f,
1365 .vta_regs
= B53_VTA_REGS
,
1366 .cpu_port
= B53_CPU_PORT
,
1367 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1368 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1369 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1370 .sw_ops
= &b53_switch_ops
,
1373 .chip_id
= BCM53125_DEVICE_ID
,
1374 .dev_name
= "BCM53125",
1375 .alias
= "bcm53125",
1377 .enabled_ports
= 0x1f,
1378 .cpu_port
= B53_CPU_PORT
,
1379 .vta_regs
= B53_VTA_REGS
,
1380 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1381 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1382 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1383 .sw_ops
= &b53_switch_ops
,
1386 .chip_id
= BCM53128_DEVICE_ID
,
1387 .dev_name
= "BCM53128",
1388 .alias
= "bcm53128",
1390 .enabled_ports
= 0x1ff,
1391 .cpu_port
= B53_CPU_PORT
,
1392 .vta_regs
= B53_VTA_REGS
,
1393 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1394 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1395 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1396 .sw_ops
= &b53_switch_ops
,
1399 .chip_id
= BCM63XX_DEVICE_ID
,
1400 .dev_name
= "BCM63xx",
1403 .enabled_ports
= 0, /* pdata must provide them */
1404 .cpu_port
= B53_CPU_PORT
,
1405 .vta_regs
= B53_VTA_REGS_63XX
,
1406 .duplex_reg
= B53_DUPLEX_STAT_63XX
,
1407 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK_63XX
,
1408 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE_63XX
,
1409 .sw_ops
= &b53_switch_ops
,
1412 .chip_id
= BCM53010_DEVICE_ID
,
1413 .dev_name
= "BCM53010",
1414 .alias
= "bcm53011",
1416 .enabled_ports
= 0x1f,
1417 .cpu_port
= B53_CPU_PORT_25
, /* TODO: auto detect */
1418 .vta_regs
= B53_VTA_REGS
,
1419 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1420 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1421 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1422 .sw_ops
= &b53_switch_ops
,
1425 .chip_id
= BCM53011_DEVICE_ID
,
1426 .dev_name
= "BCM53011",
1427 .alias
= "bcm53011",
1429 .enabled_ports
= 0x1bf,
1430 .cpu_port
= B53_CPU_PORT_25
, /* TODO: auto detect */
1431 .vta_regs
= B53_VTA_REGS
,
1432 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1433 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1434 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1435 .sw_ops
= &b53_switch_ops
,
1438 .chip_id
= BCM53012_DEVICE_ID
,
1439 .dev_name
= "BCM53012",
1440 .alias
= "bcm53011",
1442 .enabled_ports
= 0x1bf,
1443 .cpu_port
= B53_CPU_PORT_25
, /* TODO: auto detect */
1444 .vta_regs
= B53_VTA_REGS
,
1445 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1446 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1447 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1448 .sw_ops
= &b53_switch_ops
,
1451 .chip_id
= BCM53018_DEVICE_ID
,
1452 .dev_name
= "BCM53018",
1453 .alias
= "bcm53018",
1455 .enabled_ports
= 0x1f,
1456 .cpu_port
= B53_CPU_PORT_25
, /* TODO: auto detect */
1457 .vta_regs
= B53_VTA_REGS
,
1458 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1459 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1460 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1461 .sw_ops
= &b53_switch_ops
,
1464 .chip_id
= BCM53019_DEVICE_ID
,
1465 .dev_name
= "BCM53019",
1466 .alias
= "bcm53019",
1468 .enabled_ports
= 0x1f,
1469 .cpu_port
= B53_CPU_PORT_25
, /* TODO: auto detect */
1470 .vta_regs
= B53_VTA_REGS
,
1471 .duplex_reg
= B53_DUPLEX_STAT_GE
,
1472 .jumbo_pm_reg
= B53_JUMBO_PORT_MASK
,
1473 .jumbo_size_reg
= B53_JUMBO_MAX_SIZE
,
1474 .sw_ops
= &b53_switch_ops
,
1478 static int b53_switch_init_of(struct b53_device
*dev
)
1480 struct device_node
*dn
, *pn
;
1485 dn
= of_get_child_by_name(dev_of_node(dev
->dev
), "ports");
1489 for_each_available_child_of_node(dn
, pn
) {
1493 if (of_property_read_u32(pn
, "reg", &port_num
))
1496 if (port_num
> B53_CPU_PORT
)
1499 ports
|= BIT(port_num
);
1501 label
= of_get_property(pn
, "label", &len
);
1502 if (label
&& !strcmp(label
, "cpu"))
1503 dev
->sw_dev
.cpu_port
= port_num
;
1506 dev
->enabled_ports
= ports
;
1508 if (!of_property_read_string(dev_of_node(dev
->dev
), "lede,alias",
1510 dev
->sw_dev
.alias
= devm_kstrdup(dev
->dev
, alias
, GFP_KERNEL
);
1515 static int b53_switch_init(struct b53_device
*dev
)
1517 struct switch_dev
*sw_dev
= &dev
->sw_dev
;
1521 for (i
= 0; i
< ARRAY_SIZE(b53_switch_chips
); i
++) {
1522 const struct b53_chip_data
*chip
= &b53_switch_chips
[i
];
1524 if (chip
->chip_id
== dev
->chip_id
) {
1525 sw_dev
->name
= chip
->dev_name
;
1527 sw_dev
->alias
= chip
->alias
;
1528 if (!dev
->enabled_ports
)
1529 dev
->enabled_ports
= chip
->enabled_ports
;
1530 dev
->duplex_reg
= chip
->duplex_reg
;
1531 dev
->vta_regs
[0] = chip
->vta_regs
[0];
1532 dev
->vta_regs
[1] = chip
->vta_regs
[1];
1533 dev
->vta_regs
[2] = chip
->vta_regs
[2];
1534 dev
->jumbo_pm_reg
= chip
->jumbo_pm_reg
;
1535 sw_dev
->ops
= chip
->sw_ops
;
1536 sw_dev
->cpu_port
= chip
->cpu_port
;
1537 sw_dev
->vlans
= chip
->vlans
;
1545 /* check which BCM5325x version we have */
1549 b53_read8(dev
, B53_VLAN_PAGE
, B53_VLAN_CTRL4_25
, &vc4
);
1551 /* check reserved bits */
1557 /* BCM5325F - do not use port 4 */
1558 dev
->enabled_ports
&= ~BIT(4);
1561 /* On the BCM47XX SoCs this is the supported internal switch.*/
1562 #ifndef CONFIG_BCM47XX
1569 } else if (dev
->chip_id
== BCM53115_DEVICE_ID
) {
1572 b53_read48(dev
, B53_STAT_PAGE
, B53_STRAP_VALUE
, &strap_value
);
1573 /* use second IMP port if GMII is enabled */
1574 if (strap_value
& SV_GMII_CTRL_115
)
1575 sw_dev
->cpu_port
= 5;
1578 if (dev_of_node(dev
->dev
)) {
1579 ret
= b53_switch_init_of(dev
);
1584 dev
->enabled_ports
|= BIT(sw_dev
->cpu_port
);
1585 sw_dev
->ports
= fls(dev
->enabled_ports
);
1587 dev
->ports
= devm_kzalloc(dev
->dev
,
1588 sizeof(struct b53_port
) * sw_dev
->ports
,
1593 dev
->vlans
= devm_kzalloc(dev
->dev
,
1594 sizeof(struct b53_vlan
) * sw_dev
->vlans
,
1599 dev
->buf
= devm_kzalloc(dev
->dev
, B53_BUF_SIZE
, GFP_KERNEL
);
1603 dev
->reset_gpio
= b53_switch_get_reset_gpio(dev
);
1604 if (dev
->reset_gpio
>= 0) {
1605 ret
= devm_gpio_request_one(dev
->dev
, dev
->reset_gpio
,
1606 GPIOF_OUT_INIT_HIGH
, "robo_reset");
1611 return b53_switch_reset(dev
);
1614 struct b53_device
*b53_swconfig_switch_alloc(struct device
*base
, struct b53_io_ops
*ops
,
1617 struct b53_device
*dev
;
1619 dev
= devm_kzalloc(base
, sizeof(*dev
), GFP_KERNEL
);
1626 mutex_init(&dev
->reg_mutex
);
1630 EXPORT_SYMBOL(b53_swconfig_switch_alloc
);
1632 int b53_swconfig_switch_detect(struct b53_device
*dev
)
1639 ret
= b53_read8(dev
, B53_MGMT_PAGE
, B53_DEVICE_ID
, &id8
);
1646 * BCM5325 and BCM5365 do not have this register so reads
1647 * return 0. But the read operation did succeed, so assume
1648 * this is one of them.
1650 * Next check if we can write to the 5325's VTA register; for
1651 * 5365 it is read only.
1654 b53_write16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_25
, 0xf);
1655 b53_read16(dev
, B53_VLAN_PAGE
, B53_VLAN_TABLE_ACCESS_25
, &tmp
);
1658 dev
->chip_id
= BCM5325_DEVICE_ID
;
1660 dev
->chip_id
= BCM5365_DEVICE_ID
;
1662 case BCM5395_DEVICE_ID
:
1663 case BCM5397_DEVICE_ID
:
1664 case BCM5398_DEVICE_ID
:
1668 ret
= b53_read32(dev
, B53_MGMT_PAGE
, B53_DEVICE_ID
, &id32
);
1673 case BCM53115_DEVICE_ID
:
1674 case BCM53125_DEVICE_ID
:
1675 case BCM53128_DEVICE_ID
:
1676 case BCM53010_DEVICE_ID
:
1677 case BCM53011_DEVICE_ID
:
1678 case BCM53012_DEVICE_ID
:
1679 case BCM53018_DEVICE_ID
:
1680 case BCM53019_DEVICE_ID
:
1681 dev
->chip_id
= id32
;
1684 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1690 if (dev
->chip_id
== BCM5325_DEVICE_ID
)
1691 return b53_read8(dev
, B53_STAT_PAGE
, B53_REV_ID_25
,
1694 return b53_read8(dev
, B53_MGMT_PAGE
, B53_REV_ID
,
1697 EXPORT_SYMBOL(b53_swconfig_switch_detect
);
1699 int b53_swconfig_switch_register(struct b53_device
*dev
)
1704 dev
->chip_id
= dev
->pdata
->chip_id
;
1705 dev
->enabled_ports
= dev
->pdata
->enabled_ports
;
1706 dev
->sw_dev
.alias
= dev
->pdata
->alias
;
1709 if (!dev
->chip_id
&& b53_swconfig_switch_detect(dev
))
1712 ret
= b53_switch_init(dev
);
1716 pr_info("found switch: %s, rev %i\n", dev
->sw_dev
.name
, dev
->core_rev
);
1718 return register_switch(&dev
->sw_dev
, NULL
);
1720 EXPORT_SYMBOL(b53_swconfig_switch_register
);
1722 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1723 MODULE_DESCRIPTION("B53 switch library");
1724 MODULE_LICENSE("Dual BSD/GPL");