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kernel: generic: refresh patches
[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / rtl8367b.c
1 /*
2 * Platform driver for the Realtek RTL8367R-VB ethernet switches
3 *
4 * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/device.h>
15 #include <linux/of.h>
16 #include <linux/of_platform.h>
17 #include <linux/delay.h>
18 #include <linux/skbuff.h>
19 #include <linux/rtl8367.h>
20
21 #include "rtl8366_smi.h"
22
23 #define RTL8367B_RESET_DELAY 1000 /* msecs*/
24
25 #define RTL8367B_PHY_ADDR_MAX 8
26 #define RTL8367B_PHY_REG_MAX 31
27
28 #define RTL8367B_VID_MASK 0x3fff
29 #define RTL8367B_FID_MASK 0xf
30 #define RTL8367B_UNTAG_MASK 0xff
31 #define RTL8367B_MEMBER_MASK 0xff
32
33 #define RTL8367B_PORT_MISC_CFG_REG(_p) (0x000e + 0x20 * (_p))
34 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT 4
35 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_MASK 0x3
36 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_ORIGINAL 0
37 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_KEEP 1
38 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_PRI 2
39 #define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_REAL 3
40
41 #define RTL8367B_BYPASS_LINE_RATE_REG 0x03f7
42
43 #define RTL8367B_TA_CTRL_REG 0x0500 /*GOOD*/
44 #define RTL8367B_TA_CTRL_SPA_SHIFT 8
45 #define RTL8367B_TA_CTRL_SPA_MASK 0x7
46 #define RTL8367B_TA_CTRL_METHOD BIT(4)/*GOOD*/
47 #define RTL8367B_TA_CTRL_CMD_SHIFT 3
48 #define RTL8367B_TA_CTRL_CMD_READ 0
49 #define RTL8367B_TA_CTRL_CMD_WRITE 1
50 #define RTL8367B_TA_CTRL_TABLE_SHIFT 0 /*GOOD*/
51 #define RTL8367B_TA_CTRL_TABLE_ACLRULE 1
52 #define RTL8367B_TA_CTRL_TABLE_ACLACT 2
53 #define RTL8367B_TA_CTRL_TABLE_CVLAN 3
54 #define RTL8367B_TA_CTRL_TABLE_L2 4
55 #define RTL8367B_TA_CTRL_CVLAN_READ \
56 ((RTL8367B_TA_CTRL_CMD_READ << RTL8367B_TA_CTRL_CMD_SHIFT) | \
57 RTL8367B_TA_CTRL_TABLE_CVLAN)
58 #define RTL8367B_TA_CTRL_CVLAN_WRITE \
59 ((RTL8367B_TA_CTRL_CMD_WRITE << RTL8367B_TA_CTRL_CMD_SHIFT) | \
60 RTL8367B_TA_CTRL_TABLE_CVLAN)
61
62 #define RTL8367B_TA_ADDR_REG 0x0501/*GOOD*/
63 #define RTL8367B_TA_ADDR_MASK 0x3fff/*GOOD*/
64
65 #define RTL8367B_TA_LUT_REG 0x0502/*GOOD*/
66
67 #define RTL8367B_TA_WRDATA_REG(_x) (0x0510 + (_x))/*GOOD*/
68 #define RTL8367B_TA_VLAN_NUM_WORDS 2
69 #define RTL8367B_TA_VLAN_VID_MASK RTL8367B_VID_MASK
70 #define RTL8367B_TA_VLAN0_MEMBER_SHIFT 0
71 #define RTL8367B_TA_VLAN0_MEMBER_MASK RTL8367B_MEMBER_MASK
72 #define RTL8367B_TA_VLAN0_UNTAG_SHIFT 8
73 #define RTL8367B_TA_VLAN0_UNTAG_MASK RTL8367B_MEMBER_MASK
74 #define RTL8367B_TA_VLAN1_FID_SHIFT 0
75 #define RTL8367B_TA_VLAN1_FID_MASK RTL8367B_FID_MASK
76
77 #define RTL8367B_TA_RDDATA_REG(_x) (0x0520 + (_x))/*GOOD*/
78
79 #define RTL8367B_VLAN_PVID_CTRL_REG(_p) (0x0700 + (_p) / 2) /*GOOD*/
80 #define RTL8367B_VLAN_PVID_CTRL_MASK 0x1f /*GOOD*/
81 #define RTL8367B_VLAN_PVID_CTRL_SHIFT(_p) (8 * ((_p) % 2)) /*GOOD*/
82
83 #define RTL8367B_VLAN_MC_BASE(_x) (0x0728 + (_x) * 4) /*GOOD*/
84 #define RTL8367B_VLAN_MC_NUM_WORDS 4 /*GOOD*/
85 #define RTL8367B_VLAN_MC0_MEMBER_SHIFT 0/*GOOD*/
86 #define RTL8367B_VLAN_MC0_MEMBER_MASK RTL8367B_MEMBER_MASK/*GOOD*/
87 #define RTL8367B_VLAN_MC1_FID_SHIFT 0/*GOOD*/
88 #define RTL8367B_VLAN_MC1_FID_MASK RTL8367B_FID_MASK/*GOOD*/
89 #define RTL8367B_VLAN_MC3_EVID_SHIFT 0/*GOOD*/
90 #define RTL8367B_VLAN_MC3_EVID_MASK RTL8367B_VID_MASK/*GOOD*/
91
92 #define RTL8367B_VLAN_CTRL_REG 0x07a8 /*GOOD*/
93 #define RTL8367B_VLAN_CTRL_ENABLE BIT(0)
94
95 #define RTL8367B_VLAN_INGRESS_REG 0x07a9 /*GOOD*/
96
97 #define RTL8367B_PORT_ISOLATION_REG(_p) (0x08a2 + (_p)) /*GOOD*/
98
99 #define RTL8367B_MIB_COUNTER_REG(_x) (0x1000 + (_x)) /*GOOD*/
100 #define RTL8367B_MIB_COUNTER_PORT_OFFSET 0x007c /*GOOD*/
101
102 #define RTL8367B_MIB_ADDRESS_REG 0x1004 /*GOOD*/
103
104 #define RTL8367B_MIB_CTRL0_REG(_x) (0x1005 + (_x)) /*GOOD*/
105 #define RTL8367B_MIB_CTRL0_GLOBAL_RESET_MASK BIT(11) /*GOOD*/
106 #define RTL8367B_MIB_CTRL0_QM_RESET_MASK BIT(10) /*GOOD*/
107 #define RTL8367B_MIB_CTRL0_PORT_RESET_MASK(_p) BIT(2 + (_p)) /*GOOD*/
108 #define RTL8367B_MIB_CTRL0_RESET_MASK BIT(1) /*GOOD*/
109 #define RTL8367B_MIB_CTRL0_BUSY_MASK BIT(0) /*GOOD*/
110
111 #define RTL8367B_SWC0_REG 0x1200/*GOOD*/
112 #define RTL8367B_SWC0_MAX_LENGTH_SHIFT 13/*GOOD*/
113 #define RTL8367B_SWC0_MAX_LENGTH(_x) ((_x) << 13) /*GOOD*/
114 #define RTL8367B_SWC0_MAX_LENGTH_MASK RTL8367B_SWC0_MAX_LENGTH(0x3)
115 #define RTL8367B_SWC0_MAX_LENGTH_1522 RTL8367B_SWC0_MAX_LENGTH(0)
116 #define RTL8367B_SWC0_MAX_LENGTH_1536 RTL8367B_SWC0_MAX_LENGTH(1)
117 #define RTL8367B_SWC0_MAX_LENGTH_1552 RTL8367B_SWC0_MAX_LENGTH(2)
118 #define RTL8367B_SWC0_MAX_LENGTH_16000 RTL8367B_SWC0_MAX_LENGTH(3)
119
120 #define RTL8367B_CHIP_NUMBER_REG 0x1300/*GOOD*/
121
122 #define RTL8367B_CHIP_VER_REG 0x1301/*GOOD*/
123 #define RTL8367B_CHIP_VER_RLVID_SHIFT 12/*GOOD*/
124 #define RTL8367B_CHIP_VER_RLVID_MASK 0xf/*GOOD*/
125 #define RTL8367B_CHIP_VER_MCID_SHIFT 8/*GOOD*/
126 #define RTL8367B_CHIP_VER_MCID_MASK 0xf/*GOOD*/
127 #define RTL8367B_CHIP_VER_BOID_SHIFT 4/*GOOD*/
128 #define RTL8367B_CHIP_VER_BOID_MASK 0xf/*GOOD*/
129 #define RTL8367B_CHIP_VER_AFE_SHIFT 0/*GOOD*/
130 #define RTL8367B_CHIP_VER_AFE_MASK 0x1/*GOOD*/
131
132 #define RTL8367B_CHIP_MODE_REG 0x1302
133 #define RTL8367B_CHIP_MODE_MASK 0x7
134
135 #define RTL8367B_CHIP_DEBUG0_REG 0x1303
136 #define RTL8367B_DEBUG0_SEL33(_x) BIT(8 + (_x))
137 #define RTL8367B_DEBUG0_DRI_OTHER BIT(7)
138 #define RTL8367B_DEBUG0_DRI_RG(_x) BIT(5 + (_x))
139 #define RTL8367B_DEBUG0_DRI(_x) BIT(3 + (_x))
140 #define RTL8367B_DEBUG0_SLR_OTHER BIT(2)
141 #define RTL8367B_DEBUG0_SLR(_x) BIT(_x)
142
143 #define RTL8367B_CHIP_DEBUG1_REG 0x1304
144 #define RTL8367B_DEBUG1_DN_MASK(_x) \
145 GENMASK(6 + (_x)*8, 4 + (_x)*8)
146 #define RTL8367B_DEBUG1_DN_SHIFT(_x) (4 + (_x) * 8)
147 #define RTL8367B_DEBUG1_DP_MASK(_x) \
148 GENMASK(2 + (_x) * 8, (_x) * 8)
149 #define RTL8367B_DEBUG1_DP_SHIFT(_x) ((_x) * 8)
150
151 #define RTL8367B_CHIP_DEBUG2_REG 0x13e2
152 #define RTL8367B_DEBUG2_RG2_DN_MASK GENMASK(8, 6)
153 #define RTL8367B_DEBUG2_RG2_DN_SHIFT 6
154 #define RTL8367B_DEBUG2_RG2_DP_MASK GENMASK(5, 3)
155 #define RTL8367B_DEBUG2_RG2_DP_SHIFT 3
156 #define RTL8367B_DEBUG2_DRI_EXT2_RG BIT(2)
157 #define RTL8367B_DEBUG2_DRI_EXT2 BIT(1)
158 #define RTL8367B_DEBUG2_SLR_EXT2 BIT(0)
159
160 #define RTL8367B_DIS_REG 0x1305
161 #define RTL8367B_DIS_SKIP_MII_RXER(_x) BIT(12 + (_x))
162 #define RTL8367B_DIS_RGMII_SHIFT(_x) (4 * (_x))
163 #define RTL8367B_DIS_RGMII_MASK 0x7
164
165 #define RTL8367B_DIS2_REG 0x13c3
166 #define RTL8367B_DIS2_SKIP_MII_RXER_SHIFT 4
167 #define RTL8367B_DIS2_SKIP_MII_RXER 0x10
168 #define RTL8367B_DIS2_RGMII_SHIFT 0
169 #define RTL8367B_DIS2_RGMII_MASK 0xf
170
171 #define RTL8367B_EXT_RGMXF_REG(_x) \
172 ((_x) == 2 ? 0x13c5 : 0x1306 + (_x))
173 #define RTL8367B_EXT_RGMXF_DUMMY0_SHIFT 5
174 #define RTL8367B_EXT_RGMXF_DUMMY0_MASK 0x7ff
175 #define RTL8367B_EXT_RGMXF_TXDELAY_SHIFT 3
176 #define RTL8367B_EXT_RGMXF_TXDELAY_MASK 1
177 #define RTL8367B_EXT_RGMXF_RXDELAY_MASK 0x7
178
179 #define RTL8367B_DI_FORCE_REG(_x) \
180 ((_x) == 2 ? 0x13c4 : 0x1310 + (_x))
181 #define RTL8367B_DI_FORCE_MODE BIT(12)
182 #define RTL8367B_DI_FORCE_NWAY BIT(7)
183 #define RTL8367B_DI_FORCE_TXPAUSE BIT(6)
184 #define RTL8367B_DI_FORCE_RXPAUSE BIT(5)
185 #define RTL8367B_DI_FORCE_LINK BIT(4)
186 #define RTL8367B_DI_FORCE_DUPLEX BIT(2)
187 #define RTL8367B_DI_FORCE_SPEED_MASK 3
188 #define RTL8367B_DI_FORCE_SPEED_10 0
189 #define RTL8367B_DI_FORCE_SPEED_100 1
190 #define RTL8367B_DI_FORCE_SPEED_1000 2
191
192 #define RTL8367B_MAC_FORCE_REG(_x) (0x1312 + (_x))
193
194 #define RTL8367B_CHIP_RESET_REG 0x1322 /*GOOD*/
195 #define RTL8367B_CHIP_RESET_SW BIT(1) /*GOOD*/
196 #define RTL8367B_CHIP_RESET_HW BIT(0) /*GOOD*/
197
198 #define RTL8367B_PORT_STATUS_REG(_p) (0x1352 + (_p)) /*GOOD*/
199 #define RTL8367B_PORT_STATUS_EN_1000_SPI BIT(11) /*GOOD*/
200 #define RTL8367B_PORT_STATUS_EN_100_SPI BIT(10)/*GOOD*/
201 #define RTL8367B_PORT_STATUS_NWAY_FAULT BIT(9)/*GOOD*/
202 #define RTL8367B_PORT_STATUS_LINK_MASTER BIT(8)/*GOOD*/
203 #define RTL8367B_PORT_STATUS_NWAY BIT(7)/*GOOD*/
204 #define RTL8367B_PORT_STATUS_TXPAUSE BIT(6)/*GOOD*/
205 #define RTL8367B_PORT_STATUS_RXPAUSE BIT(5)/*GOOD*/
206 #define RTL8367B_PORT_STATUS_LINK BIT(4)/*GOOD*/
207 #define RTL8367B_PORT_STATUS_DUPLEX BIT(2)/*GOOD*/
208 #define RTL8367B_PORT_STATUS_SPEED_MASK 0x0003/*GOOD*/
209 #define RTL8367B_PORT_STATUS_SPEED_10 0/*GOOD*/
210 #define RTL8367B_PORT_STATUS_SPEED_100 1/*GOOD*/
211 #define RTL8367B_PORT_STATUS_SPEED_1000 2/*GOOD*/
212
213 #define RTL8367B_RTL_MAGIC_ID_REG 0x13c2
214 #define RTL8367B_RTL_MAGIC_ID_VAL 0x0249
215
216 #define RTL8367B_IA_CTRL_REG 0x1f00
217 #define RTL8367B_IA_CTRL_RW(_x) ((_x) << 1)
218 #define RTL8367B_IA_CTRL_RW_READ RTL8367B_IA_CTRL_RW(0)
219 #define RTL8367B_IA_CTRL_RW_WRITE RTL8367B_IA_CTRL_RW(1)
220 #define RTL8367B_IA_CTRL_CMD_MASK BIT(0)
221
222 #define RTL8367B_IA_STATUS_REG 0x1f01
223 #define RTL8367B_IA_STATUS_PHY_BUSY BIT(2)
224 #define RTL8367B_IA_STATUS_SDS_BUSY BIT(1)
225 #define RTL8367B_IA_STATUS_MDX_BUSY BIT(0)
226
227 #define RTL8367B_IA_ADDRESS_REG 0x1f02
228 #define RTL8367B_IA_WRITE_DATA_REG 0x1f03
229 #define RTL8367B_IA_READ_DATA_REG 0x1f04
230
231 #define RTL8367B_INTERNAL_PHY_REG(_a, _r) (0x2000 + 32 * (_a) + (_r))
232
233 #define RTL8367B_NUM_MIB_COUNTERS 58
234
235 #define RTL8367B_CPU_PORT_NUM 5
236 #define RTL8367B_NUM_PORTS 8
237 #define RTL8367B_NUM_VLANS 32
238 #define RTL8367B_NUM_VIDS 4096
239 #define RTL8367B_PRIORITYMAX 7
240 #define RTL8367B_FIDMAX 7
241
242 #define RTL8367B_PORT_0 BIT(0)
243 #define RTL8367B_PORT_1 BIT(1)
244 #define RTL8367B_PORT_2 BIT(2)
245 #define RTL8367B_PORT_3 BIT(3)
246 #define RTL8367B_PORT_4 BIT(4)
247 #define RTL8367B_PORT_E0 BIT(5) /* External port 0 */
248 #define RTL8367B_PORT_E1 BIT(6) /* External port 1 */
249 #define RTL8367B_PORT_E2 BIT(7) /* External port 2 */
250
251 #define RTL8367B_PORTS_ALL \
252 (RTL8367B_PORT_0 | RTL8367B_PORT_1 | RTL8367B_PORT_2 | \
253 RTL8367B_PORT_3 | RTL8367B_PORT_4 | RTL8367B_PORT_E0 | \
254 RTL8367B_PORT_E1 | RTL8367B_PORT_E2)
255
256 #define RTL8367B_PORTS_ALL_BUT_CPU \
257 (RTL8367B_PORT_0 | RTL8367B_PORT_1 | RTL8367B_PORT_2 | \
258 RTL8367B_PORT_3 | RTL8367B_PORT_4 | RTL8367B_PORT_E1 | \
259 RTL8367B_PORT_E2)
260
261 struct rtl8367b_initval {
262 u16 reg;
263 u16 val;
264 };
265
266 #define RTL8367B_MIB_RXB_ID 0 /* IfInOctets */
267 #define RTL8367B_MIB_TXB_ID 28 /* IfOutOctets */
268
269 static struct rtl8366_mib_counter
270 rtl8367b_mib_counters[RTL8367B_NUM_MIB_COUNTERS] = {
271 {0, 0, 4, "ifInOctets" },
272 {0, 4, 2, "dot3StatsFCSErrors" },
273 {0, 6, 2, "dot3StatsSymbolErrors" },
274 {0, 8, 2, "dot3InPauseFrames" },
275 {0, 10, 2, "dot3ControlInUnknownOpcodes" },
276 {0, 12, 2, "etherStatsFragments" },
277 {0, 14, 2, "etherStatsJabbers" },
278 {0, 16, 2, "ifInUcastPkts" },
279 {0, 18, 2, "etherStatsDropEvents" },
280 {0, 20, 2, "ifInMulticastPkts" },
281 {0, 22, 2, "ifInBroadcastPkts" },
282 {0, 24, 2, "inMldChecksumError" },
283 {0, 26, 2, "inIgmpChecksumError" },
284 {0, 28, 2, "inMldSpecificQuery" },
285 {0, 30, 2, "inMldGeneralQuery" },
286 {0, 32, 2, "inIgmpSpecificQuery" },
287 {0, 34, 2, "inIgmpGeneralQuery" },
288 {0, 36, 2, "inMldLeaves" },
289 {0, 38, 2, "inIgmpLeaves" },
290
291 {0, 40, 4, "etherStatsOctets" },
292 {0, 44, 2, "etherStatsUnderSizePkts" },
293 {0, 46, 2, "etherOversizeStats" },
294 {0, 48, 2, "etherStatsPkts64Octets" },
295 {0, 50, 2, "etherStatsPkts65to127Octets" },
296 {0, 52, 2, "etherStatsPkts128to255Octets" },
297 {0, 54, 2, "etherStatsPkts256to511Octets" },
298 {0, 56, 2, "etherStatsPkts512to1023Octets" },
299 {0, 58, 2, "etherStatsPkts1024to1518Octets" },
300
301 {0, 60, 4, "ifOutOctets" },
302 {0, 64, 2, "dot3StatsSingleCollisionFrames" },
303 {0, 66, 2, "dot3StatMultipleCollisionFrames" },
304 {0, 68, 2, "dot3sDeferredTransmissions" },
305 {0, 70, 2, "dot3StatsLateCollisions" },
306 {0, 72, 2, "etherStatsCollisions" },
307 {0, 74, 2, "dot3StatsExcessiveCollisions" },
308 {0, 76, 2, "dot3OutPauseFrames" },
309 {0, 78, 2, "ifOutDiscards" },
310 {0, 80, 2, "dot1dTpPortInDiscards" },
311 {0, 82, 2, "ifOutUcastPkts" },
312 {0, 84, 2, "ifOutMulticastPkts" },
313 {0, 86, 2, "ifOutBroadcastPkts" },
314 {0, 88, 2, "outOampduPkts" },
315 {0, 90, 2, "inOampduPkts" },
316 {0, 92, 2, "inIgmpJoinsSuccess" },
317 {0, 94, 2, "inIgmpJoinsFail" },
318 {0, 96, 2, "inMldJoinsSuccess" },
319 {0, 98, 2, "inMldJoinsFail" },
320 {0, 100, 2, "inReportSuppressionDrop" },
321 {0, 102, 2, "inLeaveSuppressionDrop" },
322 {0, 104, 2, "outIgmpReports" },
323 {0, 106, 2, "outIgmpLeaves" },
324 {0, 108, 2, "outIgmpGeneralQuery" },
325 {0, 110, 2, "outIgmpSpecificQuery" },
326 {0, 112, 2, "outMldReports" },
327 {0, 114, 2, "outMldLeaves" },
328 {0, 116, 2, "outMldGeneralQuery" },
329 {0, 118, 2, "outMldSpecificQuery" },
330 {0, 120, 2, "inKnownMulticastPkts" },
331 };
332
333 #define REG_RD(_smi, _reg, _val) \
334 do { \
335 err = rtl8366_smi_read_reg(_smi, _reg, _val); \
336 if (err) \
337 return err; \
338 } while (0)
339
340 #define REG_WR(_smi, _reg, _val) \
341 do { \
342 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
343 if (err) \
344 return err; \
345 } while (0)
346
347 #define REG_RMW(_smi, _reg, _mask, _val) \
348 do { \
349 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
350 if (err) \
351 return err; \
352 } while (0)
353
354 static const struct rtl8367b_initval rtl8367r_vb_initvals_0[] = {
355 {0x1B03, 0x0876}, {0x1200, 0x7FC4}, {0x0301, 0x0026}, {0x1722, 0x0E14},
356 {0x205F, 0x0002}, {0x2059, 0x1A00}, {0x205F, 0x0000}, {0x207F, 0x0002},
357 {0x2077, 0x0000}, {0x2078, 0x0000}, {0x2079, 0x0000}, {0x207A, 0x0000},
358 {0x207B, 0x0000}, {0x207F, 0x0000}, {0x205F, 0x0002}, {0x2053, 0x0000},
359 {0x2054, 0x0000}, {0x2055, 0x0000}, {0x2056, 0x0000}, {0x2057, 0x0000},
360 {0x205F, 0x0000}, {0x12A4, 0x110A}, {0x12A6, 0x150A}, {0x13F1, 0x0013},
361 {0x13F4, 0x0010}, {0x13F5, 0x0000}, {0x0018, 0x0F00}, {0x0038, 0x0F00},
362 {0x0058, 0x0F00}, {0x0078, 0x0F00}, {0x0098, 0x0F00}, {0x12B6, 0x0C02},
363 {0x12B7, 0x030F}, {0x12B8, 0x11FF}, {0x12BC, 0x0004}, {0x1362, 0x0115},
364 {0x1363, 0x0002}, {0x1363, 0x0000}, {0x133F, 0x0030}, {0x133E, 0x000E},
365 {0x221F, 0x0007}, {0x221E, 0x002D}, {0x2218, 0xF030}, {0x221F, 0x0007},
366 {0x221E, 0x0023}, {0x2216, 0x0005}, {0x2215, 0x00B9}, {0x2219, 0x0044},
367 {0x2215, 0x00BA}, {0x2219, 0x0020}, {0x2215, 0x00BB}, {0x2219, 0x00C1},
368 {0x2215, 0x0148}, {0x2219, 0x0096}, {0x2215, 0x016E}, {0x2219, 0x0026},
369 {0x2216, 0x0000}, {0x2216, 0x0000}, {0x221E, 0x002D}, {0x2218, 0xF010},
370 {0x221F, 0x0007}, {0x221E, 0x0020}, {0x2215, 0x0D00}, {0x221F, 0x0000},
371 {0x221F, 0x0000}, {0x2217, 0x2160}, {0x221F, 0x0001}, {0x2210, 0xF25E},
372 {0x221F, 0x0007}, {0x221E, 0x0042}, {0x2215, 0x0F00}, {0x2215, 0x0F00},
373 {0x2216, 0x7408}, {0x2215, 0x0E00}, {0x2215, 0x0F00}, {0x2215, 0x0F01},
374 {0x2216, 0x4000}, {0x2215, 0x0E01}, {0x2215, 0x0F01}, {0x2215, 0x0F02},
375 {0x2216, 0x9400}, {0x2215, 0x0E02}, {0x2215, 0x0F02}, {0x2215, 0x0F03},
376 {0x2216, 0x7408}, {0x2215, 0x0E03}, {0x2215, 0x0F03}, {0x2215, 0x0F04},
377 {0x2216, 0x4008}, {0x2215, 0x0E04}, {0x2215, 0x0F04}, {0x2215, 0x0F05},
378 {0x2216, 0x9400}, {0x2215, 0x0E05}, {0x2215, 0x0F05}, {0x2215, 0x0F06},
379 {0x2216, 0x0803}, {0x2215, 0x0E06}, {0x2215, 0x0F06}, {0x2215, 0x0D00},
380 {0x2215, 0x0100}, {0x221F, 0x0001}, {0x2210, 0xF05E}, {0x221F, 0x0000},
381 {0x2217, 0x2100}, {0x221F, 0x0000}, {0x220D, 0x0003}, {0x220E, 0x0015},
382 {0x220D, 0x4003}, {0x220E, 0x0006}, {0x221F, 0x0000}, {0x2200, 0x1340},
383 {0x133F, 0x0010}, {0x12A0, 0x0058}, {0x12A1, 0x0058}, {0x133E, 0x000E},
384 {0x133F, 0x0030}, {0x221F, 0x0000}, {0x2210, 0x0166}, {0x221F, 0x0000},
385 {0x133E, 0x000E}, {0x133F, 0x0010}, {0x133F, 0x0030}, {0x133E, 0x000E},
386 {0x221F, 0x0005}, {0x2205, 0xFFF6}, {0x2206, 0x0080}, {0x2205, 0x8B6E},
387 {0x2206, 0x0000}, {0x220F, 0x0100}, {0x2205, 0x8000}, {0x2206, 0x0280},
388 {0x2206, 0x28F7}, {0x2206, 0x00E0}, {0x2206, 0xFFF7}, {0x2206, 0xA080},
389 {0x2206, 0x02AE}, {0x2206, 0xF602}, {0x2206, 0x0153}, {0x2206, 0x0201},
390 {0x2206, 0x6602}, {0x2206, 0x80B9}, {0x2206, 0xE08B}, {0x2206, 0x8CE1},
391 {0x2206, 0x8B8D}, {0x2206, 0x1E01}, {0x2206, 0xE18B}, {0x2206, 0x8E1E},
392 {0x2206, 0x01A0}, {0x2206, 0x00E7}, {0x2206, 0xAEDB}, {0x2206, 0xEEE0},
393 {0x2206, 0x120E}, {0x2206, 0xEEE0}, {0x2206, 0x1300}, {0x2206, 0xEEE0},
394 {0x2206, 0x2001}, {0x2206, 0xEEE0}, {0x2206, 0x2166}, {0x2206, 0xEEE0},
395 {0x2206, 0xC463}, {0x2206, 0xEEE0}, {0x2206, 0xC5E8}, {0x2206, 0xEEE0},
396 {0x2206, 0xC699}, {0x2206, 0xEEE0}, {0x2206, 0xC7C2}, {0x2206, 0xEEE0},
397 {0x2206, 0xC801}, {0x2206, 0xEEE0}, {0x2206, 0xC913}, {0x2206, 0xEEE0},
398 {0x2206, 0xCA30}, {0x2206, 0xEEE0}, {0x2206, 0xCB3E}, {0x2206, 0xEEE0},
399 {0x2206, 0xDCE1}, {0x2206, 0xEEE0}, {0x2206, 0xDD00}, {0x2206, 0xEEE2},
400 {0x2206, 0x0001}, {0x2206, 0xEEE2}, {0x2206, 0x0100}, {0x2206, 0xEEE4},
401 {0x2206, 0x8860}, {0x2206, 0xEEE4}, {0x2206, 0x8902}, {0x2206, 0xEEE4},
402 {0x2206, 0x8C00}, {0x2206, 0xEEE4}, {0x2206, 0x8D30}, {0x2206, 0xEEEA},
403 {0x2206, 0x1480}, {0x2206, 0xEEEA}, {0x2206, 0x1503}, {0x2206, 0xEEEA},
404 {0x2206, 0xC600}, {0x2206, 0xEEEA}, {0x2206, 0xC706}, {0x2206, 0xEE85},
405 {0x2206, 0xEE00}, {0x2206, 0xEE85}, {0x2206, 0xEF00}, {0x2206, 0xEE8B},
406 {0x2206, 0x6750}, {0x2206, 0xEE8B}, {0x2206, 0x6632}, {0x2206, 0xEE8A},
407 {0x2206, 0xD448}, {0x2206, 0xEE8A}, {0x2206, 0xD548}, {0x2206, 0xEE8A},
408 {0x2206, 0xD649}, {0x2206, 0xEE8A}, {0x2206, 0xD7F8}, {0x2206, 0xEE8B},
409 {0x2206, 0x85E2}, {0x2206, 0xEE8B}, {0x2206, 0x8700}, {0x2206, 0xEEFF},
410 {0x2206, 0xF600}, {0x2206, 0xEEFF}, {0x2206, 0xF7FC}, {0x2206, 0x04F8},
411 {0x2206, 0xE08B}, {0x2206, 0x8EAD}, {0x2206, 0x2023}, {0x2206, 0xF620},
412 {0x2206, 0xE48B}, {0x2206, 0x8E02}, {0x2206, 0x2877}, {0x2206, 0x0225},
413 {0x2206, 0xC702}, {0x2206, 0x26A1}, {0x2206, 0x0281}, {0x2206, 0xB302},
414 {0x2206, 0x8496}, {0x2206, 0x0202}, {0x2206, 0xA102}, {0x2206, 0x27F1},
415 {0x2206, 0x0228}, {0x2206, 0xF902}, {0x2206, 0x2AA0}, {0x2206, 0x0282},
416 {0x2206, 0xB8E0}, {0x2206, 0x8B8E}, {0x2206, 0xAD21}, {0x2206, 0x08F6},
417 {0x2206, 0x21E4}, {0x2206, 0x8B8E}, {0x2206, 0x0202}, {0x2206, 0x80E0},
418 {0x2206, 0x8B8E}, {0x2206, 0xAD22}, {0x2206, 0x05F6}, {0x2206, 0x22E4},
419 {0x2206, 0x8B8E}, {0x2206, 0xE08B}, {0x2206, 0x8EAD}, {0x2206, 0x2305},
420 {0x2206, 0xF623}, {0x2206, 0xE48B}, {0x2206, 0x8EE0}, {0x2206, 0x8B8E},
421 {0x2206, 0xAD24}, {0x2206, 0x08F6}, {0x2206, 0x24E4}, {0x2206, 0x8B8E},
422 {0x2206, 0x0227}, {0x2206, 0x6AE0}, {0x2206, 0x8B8E}, {0x2206, 0xAD25},
423 {0x2206, 0x05F6}, {0x2206, 0x25E4}, {0x2206, 0x8B8E}, {0x2206, 0xE08B},
424 {0x2206, 0x8EAD}, {0x2206, 0x260B}, {0x2206, 0xF626}, {0x2206, 0xE48B},
425 {0x2206, 0x8E02}, {0x2206, 0x830D}, {0x2206, 0x021D}, {0x2206, 0x6BE0},
426 {0x2206, 0x8B8E}, {0x2206, 0xAD27}, {0x2206, 0x05F6}, {0x2206, 0x27E4},
427 {0x2206, 0x8B8E}, {0x2206, 0x0281}, {0x2206, 0x4402}, {0x2206, 0x045C},
428 {0x2206, 0xFC04}, {0x2206, 0xF8E0}, {0x2206, 0x8B83}, {0x2206, 0xAD23},
429 {0x2206, 0x30E0}, {0x2206, 0xE022}, {0x2206, 0xE1E0}, {0x2206, 0x2359},
430 {0x2206, 0x02E0}, {0x2206, 0x85EF}, {0x2206, 0xE585}, {0x2206, 0xEFAC},
431 {0x2206, 0x2907}, {0x2206, 0x1F01}, {0x2206, 0x9E51}, {0x2206, 0xAD29},
432 {0x2206, 0x20E0}, {0x2206, 0x8B83}, {0x2206, 0xAD21}, {0x2206, 0x06E1},
433 {0x2206, 0x8B84}, {0x2206, 0xAD28}, {0x2206, 0x42E0}, {0x2206, 0x8B85},
434 {0x2206, 0xAD21}, {0x2206, 0x06E1}, {0x2206, 0x8B84}, {0x2206, 0xAD29},
435 {0x2206, 0x36BF}, {0x2206, 0x34BF}, {0x2206, 0x022C}, {0x2206, 0x31AE},
436 {0x2206, 0x2EE0}, {0x2206, 0x8B83}, {0x2206, 0xAD21}, {0x2206, 0x10E0},
437 {0x2206, 0x8B84}, {0x2206, 0xF620}, {0x2206, 0xE48B}, {0x2206, 0x84EE},
438 {0x2206, 0x8ADA}, {0x2206, 0x00EE}, {0x2206, 0x8ADB}, {0x2206, 0x00E0},
439 {0x2206, 0x8B85}, {0x2206, 0xAD21}, {0x2206, 0x0CE0}, {0x2206, 0x8B84},
440 {0x2206, 0xF621}, {0x2206, 0xE48B}, {0x2206, 0x84EE}, {0x2206, 0x8B72},
441 {0x2206, 0xFFBF}, {0x2206, 0x34C2}, {0x2206, 0x022C}, {0x2206, 0x31FC},
442 {0x2206, 0x04F8}, {0x2206, 0xFAEF}, {0x2206, 0x69E0}, {0x2206, 0x8B85},
443 {0x2206, 0xAD21}, {0x2206, 0x42E0}, {0x2206, 0xE022}, {0x2206, 0xE1E0},
444 {0x2206, 0x2358}, {0x2206, 0xC059}, {0x2206, 0x021E}, {0x2206, 0x01E1},
445 {0x2206, 0x8B72}, {0x2206, 0x1F10}, {0x2206, 0x9E2F}, {0x2206, 0xE48B},
446 {0x2206, 0x72AD}, {0x2206, 0x2123}, {0x2206, 0xE18B}, {0x2206, 0x84F7},
447 {0x2206, 0x29E5}, {0x2206, 0x8B84}, {0x2206, 0xAC27}, {0x2206, 0x10AC},
448 {0x2206, 0x2605}, {0x2206, 0x0205}, {0x2206, 0x23AE}, {0x2206, 0x1602},
449 {0x2206, 0x0535}, {0x2206, 0x0282}, {0x2206, 0x30AE}, {0x2206, 0x0E02},
450 {0x2206, 0x056A}, {0x2206, 0x0282}, {0x2206, 0x75AE}, {0x2206, 0x0602},
451 {0x2206, 0x04DC}, {0x2206, 0x0282}, {0x2206, 0x04EF}, {0x2206, 0x96FE},
452 {0x2206, 0xFC04}, {0x2206, 0xF8F9}, {0x2206, 0xE08B}, {0x2206, 0x87AD},
453 {0x2206, 0x2321}, {0x2206, 0xE0EA}, {0x2206, 0x14E1}, {0x2206, 0xEA15},
454 {0x2206, 0xAD26}, {0x2206, 0x18F6}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
455 {0x2206, 0xE5EA}, {0x2206, 0x15F6}, {0x2206, 0x26E4}, {0x2206, 0xEA14},
456 {0x2206, 0xE5EA}, {0x2206, 0x15F7}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
457 {0x2206, 0xE5EA}, {0x2206, 0x15FD}, {0x2206, 0xFC04}, {0x2206, 0xF8F9},
458 {0x2206, 0xE08B}, {0x2206, 0x87AD}, {0x2206, 0x233A}, {0x2206, 0xAD22},
459 {0x2206, 0x37E0}, {0x2206, 0xE020}, {0x2206, 0xE1E0}, {0x2206, 0x21AC},
460 {0x2206, 0x212E}, {0x2206, 0xE0EA}, {0x2206, 0x14E1}, {0x2206, 0xEA15},
461 {0x2206, 0xF627}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
462 {0x2206, 0xE2EA}, {0x2206, 0x12E3}, {0x2206, 0xEA13}, {0x2206, 0x5A8F},
463 {0x2206, 0x6A20}, {0x2206, 0xE6EA}, {0x2206, 0x12E7}, {0x2206, 0xEA13},
464 {0x2206, 0xF726}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
465 {0x2206, 0xF727}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},
466 {0x2206, 0xFDFC}, {0x2206, 0x04F8}, {0x2206, 0xF9E0}, {0x2206, 0x8B87},
467 {0x2206, 0xAD23}, {0x2206, 0x38AD}, {0x2206, 0x2135}, {0x2206, 0xE0E0},
468 {0x2206, 0x20E1}, {0x2206, 0xE021}, {0x2206, 0xAC21}, {0x2206, 0x2CE0},
469 {0x2206, 0xEA14}, {0x2206, 0xE1EA}, {0x2206, 0x15F6}, {0x2206, 0x27E4},
470 {0x2206, 0xEA14}, {0x2206, 0xE5EA}, {0x2206, 0x15E2}, {0x2206, 0xEA12},
471 {0x2206, 0xE3EA}, {0x2206, 0x135A}, {0x2206, 0x8FE6}, {0x2206, 0xEA12},
472 {0x2206, 0xE7EA}, {0x2206, 0x13F7}, {0x2206, 0x26E4}, {0x2206, 0xEA14},
473 {0x2206, 0xE5EA}, {0x2206, 0x15F7}, {0x2206, 0x27E4}, {0x2206, 0xEA14},
474 {0x2206, 0xE5EA}, {0x2206, 0x15FD}, {0x2206, 0xFC04}, {0x2206, 0xF8FA},
475 {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AD}, {0x2206, 0x2146},
476 {0x2206, 0xE0E0}, {0x2206, 0x22E1}, {0x2206, 0xE023}, {0x2206, 0x58C0},
477 {0x2206, 0x5902}, {0x2206, 0x1E01}, {0x2206, 0xE18B}, {0x2206, 0x651F},
478 {0x2206, 0x109E}, {0x2206, 0x33E4}, {0x2206, 0x8B65}, {0x2206, 0xAD21},
479 {0x2206, 0x22AD}, {0x2206, 0x272A}, {0x2206, 0xD400}, {0x2206, 0x01BF},
480 {0x2206, 0x34F2}, {0x2206, 0x022C}, {0x2206, 0xA2BF}, {0x2206, 0x34F5},
481 {0x2206, 0x022C}, {0x2206, 0xE0E0}, {0x2206, 0x8B67}, {0x2206, 0x1B10},
482 {0x2206, 0xAA14}, {0x2206, 0xE18B}, {0x2206, 0x660D}, {0x2206, 0x1459},
483 {0x2206, 0x0FAE}, {0x2206, 0x05E1}, {0x2206, 0x8B66}, {0x2206, 0x590F},
484 {0x2206, 0xBF85}, {0x2206, 0x6102}, {0x2206, 0x2CA2}, {0x2206, 0xEF96},
485 {0x2206, 0xFEFC}, {0x2206, 0x04F8}, {0x2206, 0xF9FA}, {0x2206, 0xFBEF},
486 {0x2206, 0x79E2}, {0x2206, 0x8AD2}, {0x2206, 0xAC19}, {0x2206, 0x2DE0},
487 {0x2206, 0xE036}, {0x2206, 0xE1E0}, {0x2206, 0x37EF}, {0x2206, 0x311F},
488 {0x2206, 0x325B}, {0x2206, 0x019E}, {0x2206, 0x1F7A}, {0x2206, 0x0159},
489 {0x2206, 0x019F}, {0x2206, 0x0ABF}, {0x2206, 0x348E}, {0x2206, 0x022C},
490 {0x2206, 0x31F6}, {0x2206, 0x06AE}, {0x2206, 0x0FF6}, {0x2206, 0x0302},
491 {0x2206, 0x0470}, {0x2206, 0xF703}, {0x2206, 0xF706}, {0x2206, 0xBF34},
492 {0x2206, 0x9302}, {0x2206, 0x2C31}, {0x2206, 0xAC1A}, {0x2206, 0x25E0},
493 {0x2206, 0xE022}, {0x2206, 0xE1E0}, {0x2206, 0x23EF}, {0x2206, 0x300D},
494 {0x2206, 0x311F}, {0x2206, 0x325B}, {0x2206, 0x029E}, {0x2206, 0x157A},
495 {0x2206, 0x0258}, {0x2206, 0xC4A0}, {0x2206, 0x0408}, {0x2206, 0xBF34},
496 {0x2206, 0x9E02}, {0x2206, 0x2C31}, {0x2206, 0xAE06}, {0x2206, 0xBF34},
497 {0x2206, 0x9C02}, {0x2206, 0x2C31}, {0x2206, 0xAC1B}, {0x2206, 0x4AE0},
498 {0x2206, 0xE012}, {0x2206, 0xE1E0}, {0x2206, 0x13EF}, {0x2206, 0x300D},
499 {0x2206, 0x331F}, {0x2206, 0x325B}, {0x2206, 0x1C9E}, {0x2206, 0x3AEF},
500 {0x2206, 0x325B}, {0x2206, 0x1C9F}, {0x2206, 0x09BF}, {0x2206, 0x3498},
501 {0x2206, 0x022C}, {0x2206, 0x3102}, {0x2206, 0x83C5}, {0x2206, 0x5A03},
502 {0x2206, 0x0D03}, {0x2206, 0x581C}, {0x2206, 0x1E20}, {0x2206, 0x0207},
503 {0x2206, 0xA0A0}, {0x2206, 0x000E}, {0x2206, 0x0284}, {0x2206, 0x17AD},
504 {0x2206, 0x1817}, {0x2206, 0xBF34}, {0x2206, 0x9A02}, {0x2206, 0x2C31},
505 {0x2206, 0xAE0F}, {0x2206, 0xBF34}, {0x2206, 0xC802}, {0x2206, 0x2C31},
506 {0x2206, 0xBF34}, {0x2206, 0xC502}, {0x2206, 0x2C31}, {0x2206, 0x0284},
507 {0x2206, 0x52E6}, {0x2206, 0x8AD2}, {0x2206, 0xEF97}, {0x2206, 0xFFFE},
508 {0x2206, 0xFDFC}, {0x2206, 0x04F8}, {0x2206, 0xBF34}, {0x2206, 0xDA02},
509 {0x2206, 0x2CE0}, {0x2206, 0xE58A}, {0x2206, 0xD3BF}, {0x2206, 0x34D4},
510 {0x2206, 0x022C}, {0x2206, 0xE00C}, {0x2206, 0x1159}, {0x2206, 0x02E0},
511 {0x2206, 0x8AD3}, {0x2206, 0x1E01}, {0x2206, 0xE48A}, {0x2206, 0xD3D1},
512 {0x2206, 0x00BF}, {0x2206, 0x34DA}, {0x2206, 0x022C}, {0x2206, 0xA2D1},
513 {0x2206, 0x01BF}, {0x2206, 0x34D4}, {0x2206, 0x022C}, {0x2206, 0xA2BF},
514 {0x2206, 0x34CB}, {0x2206, 0x022C}, {0x2206, 0xE0E5}, {0x2206, 0x8ACE},
515 {0x2206, 0xBF85}, {0x2206, 0x6702}, {0x2206, 0x2CE0}, {0x2206, 0xE58A},
516 {0x2206, 0xCFBF}, {0x2206, 0x8564}, {0x2206, 0x022C}, {0x2206, 0xE0E5},
517 {0x2206, 0x8AD0}, {0x2206, 0xBF85}, {0x2206, 0x6A02}, {0x2206, 0x2CE0},
518 {0x2206, 0xE58A}, {0x2206, 0xD1FC}, {0x2206, 0x04F8}, {0x2206, 0xE18A},
519 {0x2206, 0xD1BF}, {0x2206, 0x856A}, {0x2206, 0x022C}, {0x2206, 0xA2E1},
520 {0x2206, 0x8AD0}, {0x2206, 0xBF85}, {0x2206, 0x6402}, {0x2206, 0x2CA2},
521 {0x2206, 0xE18A}, {0x2206, 0xCFBF}, {0x2206, 0x8567}, {0x2206, 0x022C},
522 {0x2206, 0xA2E1}, {0x2206, 0x8ACE}, {0x2206, 0xBF34}, {0x2206, 0xCB02},
523 {0x2206, 0x2CA2}, {0x2206, 0xE18A}, {0x2206, 0xD3BF}, {0x2206, 0x34DA},
524 {0x2206, 0x022C}, {0x2206, 0xA2E1}, {0x2206, 0x8AD3}, {0x2206, 0x0D11},
525 {0x2206, 0xBF34}, {0x2206, 0xD402}, {0x2206, 0x2CA2}, {0x2206, 0xFC04},
526 {0x2206, 0xF9A0}, {0x2206, 0x0405}, {0x2206, 0xE38A}, {0x2206, 0xD4AE},
527 {0x2206, 0x13A0}, {0x2206, 0x0805}, {0x2206, 0xE38A}, {0x2206, 0xD5AE},
528 {0x2206, 0x0BA0}, {0x2206, 0x0C05}, {0x2206, 0xE38A}, {0x2206, 0xD6AE},
529 {0x2206, 0x03E3}, {0x2206, 0x8AD7}, {0x2206, 0xEF13}, {0x2206, 0xBF34},
530 {0x2206, 0xCB02}, {0x2206, 0x2CA2}, {0x2206, 0xEF13}, {0x2206, 0x0D11},
531 {0x2206, 0xBF85}, {0x2206, 0x6702}, {0x2206, 0x2CA2}, {0x2206, 0xEF13},
532 {0x2206, 0x0D14}, {0x2206, 0xBF85}, {0x2206, 0x6402}, {0x2206, 0x2CA2},
533 {0x2206, 0xEF13}, {0x2206, 0x0D17}, {0x2206, 0xBF85}, {0x2206, 0x6A02},
534 {0x2206, 0x2CA2}, {0x2206, 0xFD04}, {0x2206, 0xF8E0}, {0x2206, 0x8B85},
535 {0x2206, 0xAD27}, {0x2206, 0x2DE0}, {0x2206, 0xE036}, {0x2206, 0xE1E0},
536 {0x2206, 0x37E1}, {0x2206, 0x8B73}, {0x2206, 0x1F10}, {0x2206, 0x9E20},
537 {0x2206, 0xE48B}, {0x2206, 0x73AC}, {0x2206, 0x200B}, {0x2206, 0xAC21},
538 {0x2206, 0x0DAC}, {0x2206, 0x250F}, {0x2206, 0xAC27}, {0x2206, 0x0EAE},
539 {0x2206, 0x0F02}, {0x2206, 0x84CC}, {0x2206, 0xAE0A}, {0x2206, 0x0284},
540 {0x2206, 0xD1AE}, {0x2206, 0x05AE}, {0x2206, 0x0302}, {0x2206, 0x84D8},
541 {0x2206, 0xFC04}, {0x2206, 0xEE8B}, {0x2206, 0x6800}, {0x2206, 0x0402},
542 {0x2206, 0x84E5}, {0x2206, 0x0285}, {0x2206, 0x2804}, {0x2206, 0x0285},
543 {0x2206, 0x4904}, {0x2206, 0xEE8B}, {0x2206, 0x6800}, {0x2206, 0xEE8B},
544 {0x2206, 0x6902}, {0x2206, 0x04F8}, {0x2206, 0xF9E0}, {0x2206, 0x8B85},
545 {0x2206, 0xAD26}, {0x2206, 0x38D0}, {0x2206, 0x0B02}, {0x2206, 0x2B4D},
546 {0x2206, 0x5882}, {0x2206, 0x7882}, {0x2206, 0x9F2D}, {0x2206, 0xE08B},
547 {0x2206, 0x68E1}, {0x2206, 0x8B69}, {0x2206, 0x1F10}, {0x2206, 0x9EC8},
548 {0x2206, 0x10E4}, {0x2206, 0x8B68}, {0x2206, 0xE0E0}, {0x2206, 0x00E1},
549 {0x2206, 0xE001}, {0x2206, 0xF727}, {0x2206, 0xE4E0}, {0x2206, 0x00E5},
550 {0x2206, 0xE001}, {0x2206, 0xE2E0}, {0x2206, 0x20E3}, {0x2206, 0xE021},
551 {0x2206, 0xAD30}, {0x2206, 0xF7F6}, {0x2206, 0x27E4}, {0x2206, 0xE000},
552 {0x2206, 0xE5E0}, {0x2206, 0x01FD}, {0x2206, 0xFC04}, {0x2206, 0xF8FA},
553 {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AD}, {0x2206, 0x2212},
554 {0x2206, 0xE0E0}, {0x2206, 0x14E1}, {0x2206, 0xE015}, {0x2206, 0xAD26},
555 {0x2206, 0x9CE1}, {0x2206, 0x85E0}, {0x2206, 0xBF85}, {0x2206, 0x6D02},
556 {0x2206, 0x2CA2}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x04F8},
557 {0x2206, 0xFAEF}, {0x2206, 0x69E0}, {0x2206, 0x8B86}, {0x2206, 0xAD22},
558 {0x2206, 0x09E1}, {0x2206, 0x85E1}, {0x2206, 0xBF85}, {0x2206, 0x6D02},
559 {0x2206, 0x2CA2}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x0464},
560 {0x2206, 0xE48C}, {0x2206, 0xFDE4}, {0x2206, 0x80CA}, {0x2206, 0xE480},
561 {0x2206, 0x66E0}, {0x2206, 0x8E70}, {0x2206, 0xE076}, {0x2205, 0xE142},
562 {0x2206, 0x0701}, {0x2205, 0xE140}, {0x2206, 0x0405}, {0x220F, 0x0000},
563 {0x221F, 0x0000}, {0x2200, 0x1340}, {0x133E, 0x000E}, {0x133F, 0x0010},
564 {0x13EB, 0x11BB}
565 };
566
567 static const struct rtl8367b_initval rtl8367r_vb_initvals_1[] = {
568 {0x1B03, 0x0876}, {0x1200, 0x7FC4}, {0x1305, 0xC000}, {0x121E, 0x03CA},
569 {0x1233, 0x0352}, {0x1234, 0x0064}, {0x1237, 0x0096}, {0x1238, 0x0078},
570 {0x1239, 0x0084}, {0x123A, 0x0030}, {0x205F, 0x0002}, {0x2059, 0x1A00},
571 {0x205F, 0x0000}, {0x207F, 0x0002}, {0x2077, 0x0000}, {0x2078, 0x0000},
572 {0x2079, 0x0000}, {0x207A, 0x0000}, {0x207B, 0x0000}, {0x207F, 0x0000},
573 {0x205F, 0x0002}, {0x2053, 0x0000}, {0x2054, 0x0000}, {0x2055, 0x0000},
574 {0x2056, 0x0000}, {0x2057, 0x0000}, {0x205F, 0x0000}, {0x133F, 0x0030},
575 {0x133E, 0x000E}, {0x221F, 0x0005}, {0x2205, 0x8B86}, {0x2206, 0x800E},
576 {0x221F, 0x0000}, {0x133F, 0x0010}, {0x12A3, 0x2200}, {0x6107, 0xE58B},
577 {0x6103, 0xA970}, {0x0018, 0x0F00}, {0x0038, 0x0F00}, {0x0058, 0x0F00},
578 {0x0078, 0x0F00}, {0x0098, 0x0F00}, {0x133F, 0x0030}, {0x133E, 0x000E},
579 {0x221F, 0x0005}, {0x2205, 0x8B6E}, {0x2206, 0x0000}, {0x220F, 0x0100},
580 {0x2205, 0xFFF6}, {0x2206, 0x0080}, {0x2205, 0x8000}, {0x2206, 0x0280},
581 {0x2206, 0x2BF7}, {0x2206, 0x00E0}, {0x2206, 0xFFF7}, {0x2206, 0xA080},
582 {0x2206, 0x02AE}, {0x2206, 0xF602}, {0x2206, 0x0153}, {0x2206, 0x0201},
583 {0x2206, 0x6602}, {0x2206, 0x8044}, {0x2206, 0x0201}, {0x2206, 0x7CE0},
584 {0x2206, 0x8B8C}, {0x2206, 0xE18B}, {0x2206, 0x8D1E}, {0x2206, 0x01E1},
585 {0x2206, 0x8B8E}, {0x2206, 0x1E01}, {0x2206, 0xA000}, {0x2206, 0xE4AE},
586 {0x2206, 0xD8EE}, {0x2206, 0x85C0}, {0x2206, 0x00EE}, {0x2206, 0x85C1},
587 {0x2206, 0x00EE}, {0x2206, 0x8AFC}, {0x2206, 0x07EE}, {0x2206, 0x8AFD},
588 {0x2206, 0x73EE}, {0x2206, 0xFFF6}, {0x2206, 0x00EE}, {0x2206, 0xFFF7},
589 {0x2206, 0xFC04}, {0x2206, 0xF8E0}, {0x2206, 0x8B8E}, {0x2206, 0xAD20},
590 {0x2206, 0x0302}, {0x2206, 0x8050}, {0x2206, 0xFC04}, {0x2206, 0xF8F9},
591 {0x2206, 0xE08B}, {0x2206, 0x85AD}, {0x2206, 0x2548}, {0x2206, 0xE08A},
592 {0x2206, 0xE4E1}, {0x2206, 0x8AE5}, {0x2206, 0x7C00}, {0x2206, 0x009E},
593 {0x2206, 0x35EE}, {0x2206, 0x8AE4}, {0x2206, 0x00EE}, {0x2206, 0x8AE5},
594 {0x2206, 0x00E0}, {0x2206, 0x8AFC}, {0x2206, 0xE18A}, {0x2206, 0xFDE2},
595 {0x2206, 0x85C0}, {0x2206, 0xE385}, {0x2206, 0xC102}, {0x2206, 0x2DAC},
596 {0x2206, 0xAD20}, {0x2206, 0x12EE}, {0x2206, 0x8AE4}, {0x2206, 0x03EE},
597 {0x2206, 0x8AE5}, {0x2206, 0xB7EE}, {0x2206, 0x85C0}, {0x2206, 0x00EE},
598 {0x2206, 0x85C1}, {0x2206, 0x00AE}, {0x2206, 0x1115}, {0x2206, 0xE685},
599 {0x2206, 0xC0E7}, {0x2206, 0x85C1}, {0x2206, 0xAE08}, {0x2206, 0xEE85},
600 {0x2206, 0xC000}, {0x2206, 0xEE85}, {0x2206, 0xC100}, {0x2206, 0xFDFC},
601 {0x2206, 0x0400}, {0x2205, 0xE142}, {0x2206, 0x0701}, {0x2205, 0xE140},
602 {0x2206, 0x0405}, {0x220F, 0x0000}, {0x221F, 0x0000}, {0x133E, 0x000E},
603 {0x133F, 0x0010}, {0x13EB, 0x11BB}, {0x207F, 0x0002}, {0x2073, 0x1D22},
604 {0x207F, 0x0000}, {0x133F, 0x0030}, {0x133E, 0x000E}, {0x2200, 0x1340},
605 {0x133E, 0x000E}, {0x133F, 0x0010},
606 };
607
608 static const struct rtl8367b_initval rtl8367c_initvals[] = {
609 {0x13c2, 0x0000}, {0x0018, 0x0f00}, {0x0038, 0x0f00}, {0x0058, 0x0f00},
610 {0x0078, 0x0f00}, {0x0098, 0x0f00}, {0x1d15, 0x0a69}, {0x2000, 0x1340},
611 {0x2020, 0x1340}, {0x2040, 0x1340}, {0x2060, 0x1340}, {0x2080, 0x1340},
612 {0x13eb, 0x15bb}, {0x1303, 0x06d6}, {0x1304, 0x0700}, {0x13E2, 0x003F},
613 {0x13F9, 0x0090}, {0x121e, 0x03CA}, {0x1233, 0x0352}, {0x1237, 0x00a0},
614 {0x123a, 0x0030}, {0x1239, 0x0084}, {0x0301, 0x1000}, {0x1349, 0x001F},
615 {0x18e0, 0x4004}, {0x122b, 0x641c}, {0x1305, 0xc000}, {0x1200, 0x7fcb},
616 {0x0884, 0x0003}, {0x06eb, 0x0001}, {0x00cf, 0xffff}, {0x00d0, 0x0007},
617 {0x00ce, 0x48b0}, {0x00ce, 0x48b0}, {0x0398, 0xffff}, {0x0399, 0x0007},
618 {0x0300, 0x0001}, {0x03fa, 0x0007}, {0x08c8, 0x00c0}, {0x0a30, 0x020e},
619 {0x0800, 0x0000}, {0x0802, 0x0000}, {0x09da, 0x0017}, {0x1d32, 0x0002},
620 };
621
622 static int rtl8367b_write_initvals(struct rtl8366_smi *smi,
623 const struct rtl8367b_initval *initvals,
624 int count)
625 {
626 int err;
627 int i;
628
629 for (i = 0; i < count; i++)
630 REG_WR(smi, initvals[i].reg, initvals[i].val);
631
632 return 0;
633 }
634
635 static int rtl8367b_read_phy_reg(struct rtl8366_smi *smi,
636 u32 phy_addr, u32 phy_reg, u32 *val)
637 {
638 int timeout;
639 u32 data;
640 int err;
641
642 if (phy_addr > RTL8367B_PHY_ADDR_MAX)
643 return -EINVAL;
644
645 if (phy_reg > RTL8367B_PHY_REG_MAX)
646 return -EINVAL;
647
648 REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
649 if (data & RTL8367B_IA_STATUS_PHY_BUSY)
650 return -ETIMEDOUT;
651
652 /* prepare address */
653 REG_WR(smi, RTL8367B_IA_ADDRESS_REG,
654 RTL8367B_INTERNAL_PHY_REG(phy_addr, phy_reg));
655
656 /* send read command */
657 REG_WR(smi, RTL8367B_IA_CTRL_REG,
658 RTL8367B_IA_CTRL_CMD_MASK | RTL8367B_IA_CTRL_RW_READ);
659
660 timeout = 5;
661 do {
662 REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
663 if ((data & RTL8367B_IA_STATUS_PHY_BUSY) == 0)
664 break;
665
666 if (timeout--) {
667 dev_err(smi->parent, "phy read timed out\n");
668 return -ETIMEDOUT;
669 }
670
671 udelay(1);
672 } while (1);
673
674 /* read data */
675 REG_RD(smi, RTL8367B_IA_READ_DATA_REG, val);
676
677 dev_dbg(smi->parent, "phy_read: addr:%02x, reg:%02x, val:%04x\n",
678 phy_addr, phy_reg, *val);
679 return 0;
680 }
681
682 static int rtl8367b_write_phy_reg(struct rtl8366_smi *smi,
683 u32 phy_addr, u32 phy_reg, u32 val)
684 {
685 int timeout;
686 u32 data;
687 int err;
688
689 dev_dbg(smi->parent, "phy_write: addr:%02x, reg:%02x, val:%04x\n",
690 phy_addr, phy_reg, val);
691
692 if (phy_addr > RTL8367B_PHY_ADDR_MAX)
693 return -EINVAL;
694
695 if (phy_reg > RTL8367B_PHY_REG_MAX)
696 return -EINVAL;
697
698 REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
699 if (data & RTL8367B_IA_STATUS_PHY_BUSY)
700 return -ETIMEDOUT;
701
702 /* preapre data */
703 REG_WR(smi, RTL8367B_IA_WRITE_DATA_REG, val);
704
705 /* prepare address */
706 REG_WR(smi, RTL8367B_IA_ADDRESS_REG,
707 RTL8367B_INTERNAL_PHY_REG(phy_addr, phy_reg));
708
709 /* send write command */
710 REG_WR(smi, RTL8367B_IA_CTRL_REG,
711 RTL8367B_IA_CTRL_CMD_MASK | RTL8367B_IA_CTRL_RW_WRITE);
712
713 timeout = 5;
714 do {
715 REG_RD(smi, RTL8367B_IA_STATUS_REG, &data);
716 if ((data & RTL8367B_IA_STATUS_PHY_BUSY) == 0)
717 break;
718
719 if (timeout--) {
720 dev_err(smi->parent, "phy write timed out\n");
721 return -ETIMEDOUT;
722 }
723
724 udelay(1);
725 } while (1);
726
727 return 0;
728 }
729
730 static int rtl8367b_init_regs(struct rtl8366_smi *smi)
731 {
732 const struct rtl8367b_initval *initvals;
733 u32 chip_num;
734 u32 chip_ver;
735 u32 rlvid;
736 int count;
737 int err;
738
739 REG_WR(smi, RTL8367B_RTL_MAGIC_ID_REG, RTL8367B_RTL_MAGIC_ID_VAL);
740 REG_RD(smi, RTL8367B_CHIP_NUMBER_REG, &chip_num);
741 REG_RD(smi, RTL8367B_CHIP_VER_REG, &chip_ver);
742
743 if ((chip_ver == 0x0020 || chip_ver == 0x00A0) && chip_num == 0x6367) {
744 initvals = rtl8367c_initvals;
745 count = ARRAY_SIZE(rtl8367c_initvals);
746 } else {
747 rlvid = (chip_ver >> RTL8367B_CHIP_VER_RLVID_SHIFT) &
748 RTL8367B_CHIP_VER_RLVID_MASK;
749 switch (rlvid) {
750 case 0:
751 initvals = rtl8367r_vb_initvals_0;
752 count = ARRAY_SIZE(rtl8367r_vb_initvals_0);
753 break;
754 case 1:
755 initvals = rtl8367r_vb_initvals_1;
756 count = ARRAY_SIZE(rtl8367r_vb_initvals_1);
757 break;
758 default:
759 dev_err(smi->parent, "unknow rlvid %u\n", rlvid);
760 return -ENODEV;
761 }
762 }
763
764 /* TODO: disable RLTP */
765
766 return rtl8367b_write_initvals(smi, initvals, count);
767 }
768
769 static int rtl8367b_reset_chip(struct rtl8366_smi *smi)
770 {
771 int timeout = 10;
772 int err;
773 u32 data;
774
775 REG_WR(smi, RTL8367B_CHIP_RESET_REG, RTL8367B_CHIP_RESET_HW);
776 msleep(RTL8367B_RESET_DELAY);
777
778 do {
779 REG_RD(smi, RTL8367B_CHIP_RESET_REG, &data);
780 if (!(data & RTL8367B_CHIP_RESET_HW))
781 break;
782
783 msleep(1);
784 } while (--timeout);
785
786 if (!timeout) {
787 dev_err(smi->parent, "chip reset timed out\n");
788 return -ETIMEDOUT;
789 }
790
791 return 0;
792 }
793
794 static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id,
795 enum rtl8367_extif_mode mode)
796 {
797 int err;
798
799 /* set port mode */
800 switch (mode) {
801 case RTL8367_EXTIF_MODE_RGMII:
802 REG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG,
803 RTL8367B_DEBUG0_SEL33(id),
804 RTL8367B_DEBUG0_SEL33(id));
805 if (id <= 1) {
806 REG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG,
807 RTL8367B_DEBUG0_DRI(id) |
808 RTL8367B_DEBUG0_DRI_RG(id) |
809 RTL8367B_DEBUG0_SLR(id),
810 RTL8367B_DEBUG0_DRI_RG(id) |
811 RTL8367B_DEBUG0_SLR(id));
812 REG_RMW(smi, RTL8367B_CHIP_DEBUG1_REG,
813 RTL8367B_DEBUG1_DN_MASK(id) |
814 RTL8367B_DEBUG1_DP_MASK(id),
815 (7 << RTL8367B_DEBUG1_DN_SHIFT(id)) |
816 (7 << RTL8367B_DEBUG1_DP_SHIFT(id)));
817 } else {
818 REG_RMW(smi, RTL8367B_CHIP_DEBUG2_REG,
819 RTL8367B_DEBUG2_DRI_EXT2 |
820 RTL8367B_DEBUG2_DRI_EXT2_RG |
821 RTL8367B_DEBUG2_SLR_EXT2 |
822 RTL8367B_DEBUG2_RG2_DN_MASK |
823 RTL8367B_DEBUG2_RG2_DP_MASK,
824 RTL8367B_DEBUG2_DRI_EXT2_RG |
825 RTL8367B_DEBUG2_SLR_EXT2 |
826 (7 << RTL8367B_DEBUG2_RG2_DN_SHIFT) |
827 (7 << RTL8367B_DEBUG2_RG2_DP_SHIFT));
828 }
829 break;
830
831 case RTL8367_EXTIF_MODE_TMII_MAC:
832 case RTL8367_EXTIF_MODE_TMII_PHY:
833 REG_RMW(smi, RTL8367B_BYPASS_LINE_RATE_REG, BIT(id), BIT(id));
834 break;
835
836 case RTL8367_EXTIF_MODE_GMII:
837 REG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG,
838 RTL8367B_DEBUG0_SEL33(id),
839 RTL8367B_DEBUG0_SEL33(id));
840 REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), BIT(6));
841 break;
842
843 case RTL8367_EXTIF_MODE_MII_MAC:
844 case RTL8367_EXTIF_MODE_MII_PHY:
845 case RTL8367_EXTIF_MODE_DISABLED:
846 REG_RMW(smi, RTL8367B_BYPASS_LINE_RATE_REG, BIT(id), 0);
847 REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), 0);
848 break;
849
850 default:
851 dev_err(smi->parent,
852 "invalid mode for external interface %d\n", id);
853 return -EINVAL;
854 }
855
856 if (id <= 1)
857 REG_RMW(smi, RTL8367B_DIS_REG,
858 RTL8367B_DIS_RGMII_MASK << RTL8367B_DIS_RGMII_SHIFT(id),
859 mode << RTL8367B_DIS_RGMII_SHIFT(id));
860 else
861 REG_RMW(smi, RTL8367B_DIS2_REG,
862 RTL8367B_DIS2_RGMII_MASK << RTL8367B_DIS2_RGMII_SHIFT,
863 mode << RTL8367B_DIS2_RGMII_SHIFT);
864
865 return 0;
866 }
867
868 static int rtl8367b_extif_set_force(struct rtl8366_smi *smi, int id,
869 struct rtl8367_port_ability *pa)
870 {
871 u32 mask;
872 u32 val;
873 int err;
874
875 mask = (RTL8367B_DI_FORCE_MODE |
876 RTL8367B_DI_FORCE_NWAY |
877 RTL8367B_DI_FORCE_TXPAUSE |
878 RTL8367B_DI_FORCE_RXPAUSE |
879 RTL8367B_DI_FORCE_LINK |
880 RTL8367B_DI_FORCE_DUPLEX |
881 RTL8367B_DI_FORCE_SPEED_MASK);
882
883 val = pa->speed;
884 val |= pa->force_mode ? RTL8367B_DI_FORCE_MODE : 0;
885 val |= pa->nway ? RTL8367B_DI_FORCE_NWAY : 0;
886 val |= pa->txpause ? RTL8367B_DI_FORCE_TXPAUSE : 0;
887 val |= pa->rxpause ? RTL8367B_DI_FORCE_RXPAUSE : 0;
888 val |= pa->link ? RTL8367B_DI_FORCE_LINK : 0;
889 val |= pa->duplex ? RTL8367B_DI_FORCE_DUPLEX : 0;
890
891 REG_RMW(smi, RTL8367B_DI_FORCE_REG(id), mask, val);
892
893 return 0;
894 }
895
896 static int rtl8367b_extif_set_rgmii_delay(struct rtl8366_smi *smi, int id,
897 unsigned txdelay, unsigned rxdelay)
898 {
899 u32 mask;
900 u32 val;
901 int err;
902
903 mask = (RTL8367B_EXT_RGMXF_RXDELAY_MASK |
904 (RTL8367B_EXT_RGMXF_TXDELAY_MASK <<
905 RTL8367B_EXT_RGMXF_TXDELAY_SHIFT));
906
907 val = rxdelay;
908 val |= txdelay << RTL8367B_EXT_RGMXF_TXDELAY_SHIFT;
909
910 REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), mask, val);
911
912 return 0;
913 }
914
915 static int rtl8367b_extif_init(struct rtl8366_smi *smi, int id,
916 struct rtl8367_extif_config *cfg)
917 {
918 enum rtl8367_extif_mode mode;
919 int err;
920
921 mode = (cfg) ? cfg->mode : RTL8367_EXTIF_MODE_DISABLED;
922
923 err = rtl8367b_extif_set_mode(smi, id, mode);
924 if (err)
925 return err;
926
927 if (mode != RTL8367_EXTIF_MODE_DISABLED) {
928 err = rtl8367b_extif_set_force(smi, id, &cfg->ability);
929 if (err)
930 return err;
931
932 err = rtl8367b_extif_set_rgmii_delay(smi, id, cfg->txdelay,
933 cfg->rxdelay);
934 if (err)
935 return err;
936 }
937
938 return 0;
939 }
940
941 #ifdef CONFIG_OF
942 static int rtl8367b_extif_init_of(struct rtl8366_smi *smi, int id,
943 const char *name)
944 {
945 struct rtl8367_extif_config *cfg;
946 const __be32 *prop;
947 int size;
948 int err;
949
950 prop = of_get_property(smi->parent->of_node, name, &size);
951 if (!prop)
952 return rtl8367b_extif_init(smi, id, NULL);
953
954 if (size != (9 * sizeof(*prop))) {
955 dev_err(smi->parent, "%s property is invalid\n", name);
956 return -EINVAL;
957 }
958
959 cfg = kzalloc(sizeof(struct rtl8367_extif_config), GFP_KERNEL);
960 if (!cfg)
961 return -ENOMEM;
962
963 cfg->txdelay = be32_to_cpup(prop++);
964 cfg->rxdelay = be32_to_cpup(prop++);
965 cfg->mode = be32_to_cpup(prop++);
966 cfg->ability.force_mode = be32_to_cpup(prop++);
967 cfg->ability.txpause = be32_to_cpup(prop++);
968 cfg->ability.rxpause = be32_to_cpup(prop++);
969 cfg->ability.link = be32_to_cpup(prop++);
970 cfg->ability.duplex = be32_to_cpup(prop++);
971 cfg->ability.speed = be32_to_cpup(prop++);
972
973 err = rtl8367b_extif_init(smi, id, cfg);
974 kfree(cfg);
975
976 return err;
977 }
978 #else
979 static int rtl8367b_extif_init_of(struct rtl8366_smi *smi, int id,
980 const char *name)
981 {
982 return -EINVAL;
983 }
984 #endif
985
986 static int rtl8367b_setup(struct rtl8366_smi *smi)
987 {
988 struct rtl8367_platform_data *pdata;
989 int err;
990 int i;
991
992 pdata = smi->parent->platform_data;
993
994 err = rtl8367b_init_regs(smi);
995 if (err)
996 return err;
997
998 /* initialize external interfaces */
999 if (smi->parent->of_node) {
1000 err = rtl8367b_extif_init_of(smi, 0, "realtek,extif0");
1001 if (err)
1002 return err;
1003
1004 err = rtl8367b_extif_init_of(smi, 1, "realtek,extif1");
1005 if (err)
1006 return err;
1007
1008 err = rtl8367b_extif_init_of(smi, 2, "realtek,extif2");
1009 if (err)
1010 return err;
1011 } else {
1012 err = rtl8367b_extif_init(smi, 0, pdata->extif0_cfg);
1013 if (err)
1014 return err;
1015
1016 err = rtl8367b_extif_init(smi, 1, pdata->extif1_cfg);
1017 if (err)
1018 return err;
1019 }
1020
1021 /* set maximum packet length to 1536 bytes */
1022 REG_RMW(smi, RTL8367B_SWC0_REG, RTL8367B_SWC0_MAX_LENGTH_MASK,
1023 RTL8367B_SWC0_MAX_LENGTH_1536);
1024
1025 /*
1026 * discard VLAN tagged packets if the port is not a member of
1027 * the VLAN with which the packets is associated.
1028 */
1029 REG_WR(smi, RTL8367B_VLAN_INGRESS_REG, RTL8367B_PORTS_ALL);
1030
1031 /*
1032 * Setup egress tag mode for each port.
1033 */
1034 for (i = 0; i < RTL8367B_NUM_PORTS; i++)
1035 REG_RMW(smi,
1036 RTL8367B_PORT_MISC_CFG_REG(i),
1037 RTL8367B_PORT_MISC_CFG_EGRESS_MODE_MASK <<
1038 RTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT,
1039 RTL8367B_PORT_MISC_CFG_EGRESS_MODE_ORIGINAL <<
1040 RTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT);
1041
1042 return 0;
1043 }
1044
1045 static int rtl8367b_get_mib_counter(struct rtl8366_smi *smi, int counter,
1046 int port, unsigned long long *val)
1047 {
1048 struct rtl8366_mib_counter *mib;
1049 int offset;
1050 int i;
1051 int err;
1052 u32 addr, data;
1053 u64 mibvalue;
1054
1055 if (port > RTL8367B_NUM_PORTS ||
1056 counter >= RTL8367B_NUM_MIB_COUNTERS)
1057 return -EINVAL;
1058
1059 mib = &rtl8367b_mib_counters[counter];
1060 addr = RTL8367B_MIB_COUNTER_PORT_OFFSET * port + mib->offset;
1061
1062 /*
1063 * Writing access counter address first
1064 * then ASIC will prepare 64bits counter wait for being retrived
1065 */
1066 REG_WR(smi, RTL8367B_MIB_ADDRESS_REG, addr >> 2);
1067
1068 /* read MIB control register */
1069 REG_RD(smi, RTL8367B_MIB_CTRL0_REG(0), &data);
1070
1071 if (data & RTL8367B_MIB_CTRL0_BUSY_MASK)
1072 return -EBUSY;
1073
1074 if (data & RTL8367B_MIB_CTRL0_RESET_MASK)
1075 return -EIO;
1076
1077 if (mib->length == 4)
1078 offset = 3;
1079 else
1080 offset = (mib->offset + 1) % 4;
1081
1082 mibvalue = 0;
1083 for (i = 0; i < mib->length; i++) {
1084 REG_RD(smi, RTL8367B_MIB_COUNTER_REG(offset - i), &data);
1085 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
1086 }
1087
1088 *val = mibvalue;
1089 return 0;
1090 }
1091
1092 static int rtl8367b_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
1093 struct rtl8366_vlan_4k *vlan4k)
1094 {
1095 u32 data[RTL8367B_TA_VLAN_NUM_WORDS];
1096 int err;
1097 int i;
1098
1099 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
1100
1101 if (vid >= RTL8367B_NUM_VIDS)
1102 return -EINVAL;
1103
1104 /* write VID */
1105 REG_WR(smi, RTL8367B_TA_ADDR_REG, vid);
1106
1107 /* write table access control word */
1108 REG_WR(smi, RTL8367B_TA_CTRL_REG, RTL8367B_TA_CTRL_CVLAN_READ);
1109
1110 for (i = 0; i < ARRAY_SIZE(data); i++)
1111 REG_RD(smi, RTL8367B_TA_RDDATA_REG(i), &data[i]);
1112
1113 vlan4k->vid = vid;
1114 vlan4k->member = (data[0] >> RTL8367B_TA_VLAN0_MEMBER_SHIFT) &
1115 RTL8367B_TA_VLAN0_MEMBER_MASK;
1116 vlan4k->untag = (data[0] >> RTL8367B_TA_VLAN0_UNTAG_SHIFT) &
1117 RTL8367B_TA_VLAN0_UNTAG_MASK;
1118 vlan4k->fid = (data[1] >> RTL8367B_TA_VLAN1_FID_SHIFT) &
1119 RTL8367B_TA_VLAN1_FID_MASK;
1120
1121 return 0;
1122 }
1123
1124 static int rtl8367b_set_vlan_4k(struct rtl8366_smi *smi,
1125 const struct rtl8366_vlan_4k *vlan4k)
1126 {
1127 u32 data[RTL8367B_TA_VLAN_NUM_WORDS];
1128 int err;
1129 int i;
1130
1131 if (vlan4k->vid >= RTL8367B_NUM_VIDS ||
1132 vlan4k->member > RTL8367B_TA_VLAN0_MEMBER_MASK ||
1133 vlan4k->untag > RTL8367B_UNTAG_MASK ||
1134 vlan4k->fid > RTL8367B_FIDMAX)
1135 return -EINVAL;
1136
1137 memset(data, 0, sizeof(data));
1138
1139 data[0] = (vlan4k->member & RTL8367B_TA_VLAN0_MEMBER_MASK) <<
1140 RTL8367B_TA_VLAN0_MEMBER_SHIFT;
1141 data[0] |= (vlan4k->untag & RTL8367B_TA_VLAN0_UNTAG_MASK) <<
1142 RTL8367B_TA_VLAN0_UNTAG_SHIFT;
1143 data[1] = (vlan4k->fid & RTL8367B_TA_VLAN1_FID_MASK) <<
1144 RTL8367B_TA_VLAN1_FID_SHIFT;
1145
1146 for (i = 0; i < ARRAY_SIZE(data); i++)
1147 REG_WR(smi, RTL8367B_TA_WRDATA_REG(i), data[i]);
1148
1149 /* write VID */
1150 REG_WR(smi, RTL8367B_TA_ADDR_REG,
1151 vlan4k->vid & RTL8367B_TA_VLAN_VID_MASK);
1152
1153 /* write table access control word */
1154 REG_WR(smi, RTL8367B_TA_CTRL_REG, RTL8367B_TA_CTRL_CVLAN_WRITE);
1155
1156 return 0;
1157 }
1158
1159 static int rtl8367b_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
1160 struct rtl8366_vlan_mc *vlanmc)
1161 {
1162 u32 data[RTL8367B_VLAN_MC_NUM_WORDS];
1163 int err;
1164 int i;
1165
1166 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
1167
1168 if (index >= RTL8367B_NUM_VLANS)
1169 return -EINVAL;
1170
1171 for (i = 0; i < ARRAY_SIZE(data); i++)
1172 REG_RD(smi, RTL8367B_VLAN_MC_BASE(index) + i, &data[i]);
1173
1174 vlanmc->member = (data[0] >> RTL8367B_VLAN_MC0_MEMBER_SHIFT) &
1175 RTL8367B_VLAN_MC0_MEMBER_MASK;
1176 vlanmc->fid = (data[1] >> RTL8367B_VLAN_MC1_FID_SHIFT) &
1177 RTL8367B_VLAN_MC1_FID_MASK;
1178 vlanmc->vid = (data[3] >> RTL8367B_VLAN_MC3_EVID_SHIFT) &
1179 RTL8367B_VLAN_MC3_EVID_MASK;
1180
1181 return 0;
1182 }
1183
1184 static int rtl8367b_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
1185 const struct rtl8366_vlan_mc *vlanmc)
1186 {
1187 u32 data[RTL8367B_VLAN_MC_NUM_WORDS];
1188 int err;
1189 int i;
1190
1191 if (index >= RTL8367B_NUM_VLANS ||
1192 vlanmc->vid >= RTL8367B_NUM_VIDS ||
1193 vlanmc->priority > RTL8367B_PRIORITYMAX ||
1194 vlanmc->member > RTL8367B_VLAN_MC0_MEMBER_MASK ||
1195 vlanmc->untag > RTL8367B_UNTAG_MASK ||
1196 vlanmc->fid > RTL8367B_FIDMAX)
1197 return -EINVAL;
1198
1199 data[0] = (vlanmc->member & RTL8367B_VLAN_MC0_MEMBER_MASK) <<
1200 RTL8367B_VLAN_MC0_MEMBER_SHIFT;
1201 data[1] = (vlanmc->fid & RTL8367B_VLAN_MC1_FID_MASK) <<
1202 RTL8367B_VLAN_MC1_FID_SHIFT;
1203 data[2] = 0;
1204 data[3] = (vlanmc->vid & RTL8367B_VLAN_MC3_EVID_MASK) <<
1205 RTL8367B_VLAN_MC3_EVID_SHIFT;
1206
1207 for (i = 0; i < ARRAY_SIZE(data); i++)
1208 REG_WR(smi, RTL8367B_VLAN_MC_BASE(index) + i, data[i]);
1209
1210 return 0;
1211 }
1212
1213 static int rtl8367b_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
1214 {
1215 u32 data;
1216 int err;
1217
1218 if (port >= RTL8367B_NUM_PORTS)
1219 return -EINVAL;
1220
1221 REG_RD(smi, RTL8367B_VLAN_PVID_CTRL_REG(port), &data);
1222
1223 *val = (data >> RTL8367B_VLAN_PVID_CTRL_SHIFT(port)) &
1224 RTL8367B_VLAN_PVID_CTRL_MASK;
1225
1226 return 0;
1227 }
1228
1229 static int rtl8367b_set_mc_index(struct rtl8366_smi *smi, int port, int index)
1230 {
1231 if (port >= RTL8367B_NUM_PORTS || index >= RTL8367B_NUM_VLANS)
1232 return -EINVAL;
1233
1234 return rtl8366_smi_rmwr(smi, RTL8367B_VLAN_PVID_CTRL_REG(port),
1235 RTL8367B_VLAN_PVID_CTRL_MASK <<
1236 RTL8367B_VLAN_PVID_CTRL_SHIFT(port),
1237 (index & RTL8367B_VLAN_PVID_CTRL_MASK) <<
1238 RTL8367B_VLAN_PVID_CTRL_SHIFT(port));
1239 }
1240
1241 static int rtl8367b_enable_vlan(struct rtl8366_smi *smi, int enable)
1242 {
1243 return rtl8366_smi_rmwr(smi, RTL8367B_VLAN_CTRL_REG,
1244 RTL8367B_VLAN_CTRL_ENABLE,
1245 (enable) ? RTL8367B_VLAN_CTRL_ENABLE : 0);
1246 }
1247
1248 static int rtl8367b_enable_vlan4k(struct rtl8366_smi *smi, int enable)
1249 {
1250 return 0;
1251 }
1252
1253 static int rtl8367b_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
1254 {
1255 unsigned max = RTL8367B_NUM_VLANS;
1256
1257 if (smi->vlan4k_enabled)
1258 max = RTL8367B_NUM_VIDS - 1;
1259
1260 if (vlan == 0 || vlan >= max)
1261 return 0;
1262
1263 return 1;
1264 }
1265
1266 static int rtl8367b_enable_port(struct rtl8366_smi *smi, int port, int enable)
1267 {
1268 int err;
1269
1270 REG_WR(smi, RTL8367B_PORT_ISOLATION_REG(port),
1271 (enable) ? RTL8367B_PORTS_ALL : 0);
1272
1273 return 0;
1274 }
1275
1276 static int rtl8367b_sw_reset_mibs(struct switch_dev *dev,
1277 const struct switch_attr *attr,
1278 struct switch_val *val)
1279 {
1280 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1281
1282 return rtl8366_smi_rmwr(smi, RTL8367B_MIB_CTRL0_REG(0), 0,
1283 RTL8367B_MIB_CTRL0_GLOBAL_RESET_MASK);
1284 }
1285
1286 static int rtl8367b_sw_get_port_link(struct switch_dev *dev,
1287 int port,
1288 struct switch_port_link *link)
1289 {
1290 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1291 u32 data = 0;
1292 u32 speed;
1293
1294 if (port >= RTL8367B_NUM_PORTS)
1295 return -EINVAL;
1296
1297 rtl8366_smi_read_reg(smi, RTL8367B_PORT_STATUS_REG(port), &data);
1298
1299 link->link = !!(data & RTL8367B_PORT_STATUS_LINK);
1300 if (!link->link)
1301 return 0;
1302
1303 link->duplex = !!(data & RTL8367B_PORT_STATUS_DUPLEX);
1304 link->rx_flow = !!(data & RTL8367B_PORT_STATUS_RXPAUSE);
1305 link->tx_flow = !!(data & RTL8367B_PORT_STATUS_TXPAUSE);
1306 link->aneg = !!(data & RTL8367B_PORT_STATUS_NWAY);
1307
1308 speed = (data & RTL8367B_PORT_STATUS_SPEED_MASK);
1309 switch (speed) {
1310 case 0:
1311 link->speed = SWITCH_PORT_SPEED_10;
1312 break;
1313 case 1:
1314 link->speed = SWITCH_PORT_SPEED_100;
1315 break;
1316 case 2:
1317 link->speed = SWITCH_PORT_SPEED_1000;
1318 break;
1319 default:
1320 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
1321 break;
1322 }
1323
1324 return 0;
1325 }
1326
1327 static int rtl8367b_sw_get_max_length(struct switch_dev *dev,
1328 const struct switch_attr *attr,
1329 struct switch_val *val)
1330 {
1331 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1332 u32 data;
1333
1334 rtl8366_smi_read_reg(smi, RTL8367B_SWC0_REG, &data);
1335 val->value.i = (data & RTL8367B_SWC0_MAX_LENGTH_MASK) >>
1336 RTL8367B_SWC0_MAX_LENGTH_SHIFT;
1337
1338 return 0;
1339 }
1340
1341 static int rtl8367b_sw_set_max_length(struct switch_dev *dev,
1342 const struct switch_attr *attr,
1343 struct switch_val *val)
1344 {
1345 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1346 u32 max_len;
1347
1348 switch (val->value.i) {
1349 case 0:
1350 max_len = RTL8367B_SWC0_MAX_LENGTH_1522;
1351 break;
1352 case 1:
1353 max_len = RTL8367B_SWC0_MAX_LENGTH_1536;
1354 break;
1355 case 2:
1356 max_len = RTL8367B_SWC0_MAX_LENGTH_1552;
1357 break;
1358 case 3:
1359 max_len = RTL8367B_SWC0_MAX_LENGTH_16000;
1360 break;
1361 default:
1362 return -EINVAL;
1363 }
1364
1365 return rtl8366_smi_rmwr(smi, RTL8367B_SWC0_REG,
1366 RTL8367B_SWC0_MAX_LENGTH_MASK, max_len);
1367 }
1368
1369
1370 static int rtl8367b_sw_reset_port_mibs(struct switch_dev *dev,
1371 const struct switch_attr *attr,
1372 struct switch_val *val)
1373 {
1374 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1375 int port;
1376
1377 port = val->port_vlan;
1378 if (port >= RTL8367B_NUM_PORTS)
1379 return -EINVAL;
1380
1381 return rtl8366_smi_rmwr(smi, RTL8367B_MIB_CTRL0_REG(port / 8), 0,
1382 RTL8367B_MIB_CTRL0_PORT_RESET_MASK(port % 8));
1383 }
1384
1385 static int rtl8367b_sw_get_port_stats(struct switch_dev *dev, int port,
1386 struct switch_port_stats *stats)
1387 {
1388 return (rtl8366_sw_get_port_stats(dev, port, stats,
1389 RTL8367B_MIB_TXB_ID, RTL8367B_MIB_RXB_ID));
1390 }
1391
1392 static struct switch_attr rtl8367b_globals[] = {
1393 {
1394 .type = SWITCH_TYPE_INT,
1395 .name = "enable_vlan",
1396 .description = "Enable VLAN mode",
1397 .set = rtl8366_sw_set_vlan_enable,
1398 .get = rtl8366_sw_get_vlan_enable,
1399 .max = 1,
1400 .ofs = 1
1401 }, {
1402 .type = SWITCH_TYPE_INT,
1403 .name = "enable_vlan4k",
1404 .description = "Enable VLAN 4K mode",
1405 .set = rtl8366_sw_set_vlan_enable,
1406 .get = rtl8366_sw_get_vlan_enable,
1407 .max = 1,
1408 .ofs = 2
1409 }, {
1410 .type = SWITCH_TYPE_NOVAL,
1411 .name = "reset_mibs",
1412 .description = "Reset all MIB counters",
1413 .set = rtl8367b_sw_reset_mibs,
1414 }, {
1415 .type = SWITCH_TYPE_INT,
1416 .name = "max_length",
1417 .description = "Get/Set the maximum length of valid packets"
1418 "(0:1522, 1:1536, 2:1552, 3:16000)",
1419 .set = rtl8367b_sw_set_max_length,
1420 .get = rtl8367b_sw_get_max_length,
1421 .max = 3,
1422 }
1423 };
1424
1425 static struct switch_attr rtl8367b_port[] = {
1426 {
1427 .type = SWITCH_TYPE_NOVAL,
1428 .name = "reset_mib",
1429 .description = "Reset single port MIB counters",
1430 .set = rtl8367b_sw_reset_port_mibs,
1431 }, {
1432 .type = SWITCH_TYPE_STRING,
1433 .name = "mib",
1434 .description = "Get MIB counters for port",
1435 .max = 33,
1436 .set = NULL,
1437 .get = rtl8366_sw_get_port_mib,
1438 },
1439 };
1440
1441 static struct switch_attr rtl8367b_vlan[] = {
1442 {
1443 .type = SWITCH_TYPE_STRING,
1444 .name = "info",
1445 .description = "Get vlan information",
1446 .max = 1,
1447 .set = NULL,
1448 .get = rtl8366_sw_get_vlan_info,
1449 },
1450 };
1451
1452 static const struct switch_dev_ops rtl8367b_sw_ops = {
1453 .attr_global = {
1454 .attr = rtl8367b_globals,
1455 .n_attr = ARRAY_SIZE(rtl8367b_globals),
1456 },
1457 .attr_port = {
1458 .attr = rtl8367b_port,
1459 .n_attr = ARRAY_SIZE(rtl8367b_port),
1460 },
1461 .attr_vlan = {
1462 .attr = rtl8367b_vlan,
1463 .n_attr = ARRAY_SIZE(rtl8367b_vlan),
1464 },
1465
1466 .get_vlan_ports = rtl8366_sw_get_vlan_ports,
1467 .set_vlan_ports = rtl8366_sw_set_vlan_ports,
1468 .get_port_pvid = rtl8366_sw_get_port_pvid,
1469 .set_port_pvid = rtl8366_sw_set_port_pvid,
1470 .reset_switch = rtl8366_sw_reset_switch,
1471 .get_port_link = rtl8367b_sw_get_port_link,
1472 .get_port_stats = rtl8367b_sw_get_port_stats,
1473 };
1474
1475 static int rtl8367b_switch_init(struct rtl8366_smi *smi)
1476 {
1477 struct switch_dev *dev = &smi->sw_dev;
1478 int err;
1479
1480 dev->name = "RTL8367B";
1481 dev->cpu_port = smi->cpu_port;
1482 dev->ports = RTL8367B_NUM_PORTS;
1483 dev->vlans = RTL8367B_NUM_VIDS;
1484 dev->ops = &rtl8367b_sw_ops;
1485 dev->alias = dev_name(smi->parent);
1486
1487 err = register_switch(dev, NULL);
1488 if (err)
1489 dev_err(smi->parent, "switch registration failed\n");
1490
1491 return err;
1492 }
1493
1494 static void rtl8367b_switch_cleanup(struct rtl8366_smi *smi)
1495 {
1496 unregister_switch(&smi->sw_dev);
1497 }
1498
1499 static int rtl8367b_mii_read(struct mii_bus *bus, int addr, int reg)
1500 {
1501 struct rtl8366_smi *smi = bus->priv;
1502 u32 val = 0;
1503 int err;
1504
1505 err = rtl8367b_read_phy_reg(smi, addr, reg, &val);
1506 if (err)
1507 return 0xffff;
1508
1509 return val;
1510 }
1511
1512 static int rtl8367b_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1513 {
1514 struct rtl8366_smi *smi = bus->priv;
1515 u32 t;
1516 int err;
1517
1518 err = rtl8367b_write_phy_reg(smi, addr, reg, val);
1519 if (err)
1520 return err;
1521
1522 /* flush write */
1523 (void) rtl8367b_read_phy_reg(smi, addr, reg, &t);
1524
1525 return err;
1526 }
1527
1528 static int rtl8367b_detect(struct rtl8366_smi *smi)
1529 {
1530 const char *chip_name = NULL;
1531 u32 chip_num;
1532 u32 chip_ver;
1533 u32 chip_mode;
1534 int ret;
1535
1536 /* TODO: improve chip detection */
1537 rtl8366_smi_write_reg(smi, RTL8367B_RTL_MAGIC_ID_REG,
1538 RTL8367B_RTL_MAGIC_ID_VAL);
1539
1540 ret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_NUMBER_REG, &chip_num);
1541 if (ret) {
1542 dev_err(smi->parent, "unable to read %s register\n",
1543 "chip number");
1544 return ret;
1545 }
1546
1547 ret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_VER_REG, &chip_ver);
1548 if (ret) {
1549 dev_err(smi->parent, "unable to read %s register\n",
1550 "chip version");
1551 return ret;
1552 }
1553
1554 ret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_MODE_REG, &chip_mode);
1555 if (ret) {
1556 dev_err(smi->parent, "unable to read %s register\n",
1557 "chip mode");
1558 return ret;
1559 }
1560
1561 switch (chip_ver) {
1562 case 0x0020:
1563 if (chip_num == 0x6367)
1564 chip_name = "8367RB-VB";
1565 break;
1566 case 0x00A0:
1567 if (chip_num == 0x6367)
1568 chip_name = "8367S";
1569 break;
1570 case 0x1000:
1571 chip_name = "8367RB";
1572 break;
1573 case 0x1010:
1574 chip_name = "8367R-VB";
1575 }
1576
1577 if (!chip_name) {
1578 dev_err(smi->parent,
1579 "unknown chip num:%04x ver:%04x, mode:%04x\n",
1580 chip_num, chip_ver, chip_mode);
1581 return -ENODEV;
1582 }
1583
1584 dev_info(smi->parent, "RTL%s chip found\n", chip_name);
1585
1586 return 0;
1587 }
1588
1589 static struct rtl8366_smi_ops rtl8367b_smi_ops = {
1590 .detect = rtl8367b_detect,
1591 .reset_chip = rtl8367b_reset_chip,
1592 .setup = rtl8367b_setup,
1593
1594 .mii_read = rtl8367b_mii_read,
1595 .mii_write = rtl8367b_mii_write,
1596
1597 .get_vlan_mc = rtl8367b_get_vlan_mc,
1598 .set_vlan_mc = rtl8367b_set_vlan_mc,
1599 .get_vlan_4k = rtl8367b_get_vlan_4k,
1600 .set_vlan_4k = rtl8367b_set_vlan_4k,
1601 .get_mc_index = rtl8367b_get_mc_index,
1602 .set_mc_index = rtl8367b_set_mc_index,
1603 .get_mib_counter = rtl8367b_get_mib_counter,
1604 .is_vlan_valid = rtl8367b_is_vlan_valid,
1605 .enable_vlan = rtl8367b_enable_vlan,
1606 .enable_vlan4k = rtl8367b_enable_vlan4k,
1607 .enable_port = rtl8367b_enable_port,
1608 };
1609
1610 static int rtl8367b_probe(struct platform_device *pdev)
1611 {
1612 struct rtl8366_smi *smi;
1613 int err;
1614
1615 smi = rtl8366_smi_probe(pdev);
1616 if (IS_ERR(smi))
1617 return PTR_ERR(smi);
1618
1619 smi->clk_delay = 1500;
1620 smi->cmd_read = 0xb9;
1621 smi->cmd_write = 0xb8;
1622 smi->ops = &rtl8367b_smi_ops;
1623 smi->num_ports = RTL8367B_NUM_PORTS;
1624 if (of_property_read_u32(pdev->dev.of_node, "cpu_port", &smi->cpu_port)
1625 || smi->cpu_port >= smi->num_ports)
1626 smi->cpu_port = RTL8367B_CPU_PORT_NUM;
1627 smi->num_vlan_mc = RTL8367B_NUM_VLANS;
1628 smi->mib_counters = rtl8367b_mib_counters;
1629 smi->num_mib_counters = ARRAY_SIZE(rtl8367b_mib_counters);
1630
1631 err = rtl8366_smi_init(smi);
1632 if (err)
1633 goto err_free_smi;
1634
1635 platform_set_drvdata(pdev, smi);
1636
1637 err = rtl8367b_switch_init(smi);
1638 if (err)
1639 goto err_clear_drvdata;
1640
1641 return 0;
1642
1643 err_clear_drvdata:
1644 platform_set_drvdata(pdev, NULL);
1645 rtl8366_smi_cleanup(smi);
1646 err_free_smi:
1647 kfree(smi);
1648 return err;
1649 }
1650
1651 static int rtl8367b_remove(struct platform_device *pdev)
1652 {
1653 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1654
1655 if (smi) {
1656 rtl8367b_switch_cleanup(smi);
1657 platform_set_drvdata(pdev, NULL);
1658 rtl8366_smi_cleanup(smi);
1659 kfree(smi);
1660 }
1661
1662 return 0;
1663 }
1664
1665 static void rtl8367b_shutdown(struct platform_device *pdev)
1666 {
1667 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1668
1669 if (smi)
1670 rtl8367b_reset_chip(smi);
1671 }
1672
1673 #ifdef CONFIG_OF
1674 static const struct of_device_id rtl8367b_match[] = {
1675 { .compatible = "realtek,rtl8367b" },
1676 {},
1677 };
1678 MODULE_DEVICE_TABLE(of, rtl8367b_match);
1679 #endif
1680
1681 static struct platform_driver rtl8367b_driver = {
1682 .driver = {
1683 .name = RTL8367B_DRIVER_NAME,
1684 .owner = THIS_MODULE,
1685 #ifdef CONFIG_OF
1686 .of_match_table = of_match_ptr(rtl8367b_match),
1687 #endif
1688 },
1689 .probe = rtl8367b_probe,
1690 .remove = rtl8367b_remove,
1691 .shutdown = rtl8367b_shutdown,
1692 };
1693
1694 module_platform_driver(rtl8367b_driver);
1695
1696 MODULE_DESCRIPTION("Realtek RTL8367B ethernet switch driver");
1697 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1698 MODULE_LICENSE("GPL v2");
1699 MODULE_ALIAS("platform:" RTL8367B_DRIVER_NAME);
1700
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