target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.h

   1 /*   This program is free software; you can redistribute it and/or modify
   2  *   it under the terms of the GNU General Public License as published by
   3  *   the Free Software Foundation; version 2 of the License
   4  *
   5  *   This program is distributed in the hope that it will be useful,
   6  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   7  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   8  *   GNU General Public License for more details.
   9  *
  10  *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  11  *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
  12  *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  13  */
  14
  15 #include <linux/reset.h>
  16
  17 #ifndef _RALINK_GSW_MT7620_H__
  18 #define _RALINK_GSW_MT7620_H__
  19
  20 #define GSW_REG_PHY_TIMEOUT     (5 * HZ)
  21
  22 #define MT7620A_GSW_REG_PIAC    0x7004
  23
  24 #define GSW_NUM_VLANS           16
  25 #define GSW_NUM_VIDS            4096
  26 #define GSW_NUM_PORTS           7
  27 #define GSW_PORT6               6
  28
  29 #define GSW_MDIO_ACCESS         BIT(31)
  30 #define GSW_MDIO_READ           BIT(19)
  31 #define GSW_MDIO_WRITE          BIT(18)
  32 #define GSW_MDIO_START          BIT(16)
  33 #define GSW_MDIO_ADDR_SHIFT     20
  34 #define GSW_MDIO_REG_SHIFT      25
  35
  36 #define GSW_REG_MIB_CNT_EN      0x4000
  37
  38 #define GSW_REG_PORT_PMCR(x)    (0x3000 + (x * 0x100))
  39 #define GSW_REG_PORT_STATUS(x)  (0x3008 + (x * 0x100))
  40 #define GSW_REG_SMACCR0         0x3fE4
  41 #define GSW_REG_SMACCR1         0x3fE8
  42 #define GSW_REG_CKGCR           0x3ff0
  43
  44 #define GSW_REG_IMR             0x7008
  45 #define GSW_REG_ISR             0x700c
  46 #define GSW_REG_GPC1            0x7014
  47 #define GSW_REG_GPC2            0x701c
  48
  49 #define GSW_REG_GPCx_TXDELAY    BIT(3)
  50 #define GSW_REG_GPCx_RXDELAY    BIT(2)
  51
  52 #define GSW_REG_MAC_P0_MCR      0x100
  53 #define GSW_REG_MAC_P1_MCR      0x200
  54
  55 // Global MAC control register
  56 #define GSW_REG_GMACCR          0x30E0
  57
  58 #define SYSC_REG_CHIP_REV_ID    0x0c
  59 #define SYSC_REG_CFG1           0x14
  60 #define PCIE_RC_MODE            BIT(8)
  61 #define SYSC_PAD_RGMII2_MDIO    0x58
  62 #define SYSC_GPIO_MODE          0x60
  63
  64 #define PORT_IRQ_ST_CHG         0x7f
  65
  66 #define ESW_PHY_POLLING         0x7000
  67
  68 #define PMCR_IPG                BIT(18)
  69 #define PMCR_MAC_MODE           BIT(16)
  70 #define PMCR_FORCE              BIT(15)
  71 #define PMCR_TX_EN              BIT(14)
  72 #define PMCR_RX_EN              BIT(13)
  73 #define PMCR_BACKOFF            BIT(9)
  74 #define PMCR_BACKPRES           BIT(8)
  75 #define PMCR_RX_FC              BIT(5)
  76 #define PMCR_TX_FC              BIT(4)
  77 #define PMCR_SPEED(_x)          (_x << 2)
  78 #define PMCR_DUPLEX             BIT(1)
  79 #define PMCR_LINK               BIT(0)
  80
  81 #define PHY_AN_EN               BIT(31)
  82 #define PHY_PRE_EN              BIT(30)
  83 #define PMY_MDC_CONF(_x)        ((_x & 0x3f) << 24)
  84
  85
  86 enum {
  87         /* Global attributes. */
  88         GSW_ATTR_ENABLE_VLAN,
  89         /* Port attributes. */
  90         GSW_ATTR_PORT_UNTAG,
  91 };
  92
  93 struct mt7620_gsw {
  94         struct device           *dev;
  95         struct reset_control    *rst_ephy;
  96         void __iomem            *base;
  97         int                     irq;
  98         bool                    ephy_disable;
  99         bool                    port4_ephy;
 100         unsigned long int       autopoll;
 101         u16                     ephy_base;
 102 };
 103
 104 void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg);
 105 u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg);
 106 int mtk_gsw_init(struct fe_priv *priv);
 107
 108 int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
 109 int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
 110 void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
 111 int mt7620_has_carrier(struct fe_priv *priv);
 112 void mt7620_print_link_state(struct fe_priv *priv, int port, int link,
 113                              int speed, int duplex);
 114
 115 void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val);
 116 u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg);
 117
 118 u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr,
 119                              u32 phy_register, u32 write_data);
 120 u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg);
 121 void mt7620_handle_carrier(struct fe_priv *priv);
 122
 123 #endif