layerscape: add 64b/32b target for ls1012ardb device
[openwrt/openwrt.git] / package / boot / uboot-layerscape / patches / 0025-armv8-ls1012ardb-Add-qspi-SECURE-BOOT-target.patch
1 From 93a1095c7da7291ffb12116de9122d431b9f6113 Mon Sep 17 00:00:00 2001
2 From: Sumit Garg <sumit.garg@nxp.com>
3 Date: Fri, 6 May 2016 11:11:58 -0400
4 Subject: [PATCH 25/93] armv8: ls1012ardb: Add qspi SECURE BOOT target
5
6 Add qspi SECURE BOOT target to enable chain of trust. Also enable
7 sec_init in boot sequence.
8
9 Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
10 Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
11 ---
12 arch/arm/include/asm/arch-fsl-layerscape/config.h | 7 +++++++
13 arch/arm/include/asm/fsl_secure_boot.h | 7 ++++++-
14 board/freescale/ls1012ardb/ls1012ardb.c | 5 +++++
15 configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 10 ++++++++++
16 include/configs/ls1012ardb.h | 2 ++
17 5 files changed, 30 insertions(+), 1 deletion(-)
18 create mode 100644 configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
19
20 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
21 index 6ea4e8e..679be6c 100644
22 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
23 +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
24 @@ -237,6 +237,13 @@
25
26 #define CONFIG_SYS_FSL_ERRATUM_A009798
27
28 +#define CONFIG_SYS_FSL_SFP_VER_3_2
29 +#define CONFIG_SYS_FSL_SEC_MON_BE
30 +#define CONFIG_SYS_FSL_SEC_BE
31 +#define CONFIG_SYS_FSL_SFP_BE
32 +#define CONFIG_SYS_FSL_SRK_LE
33 +#define CONFIG_KEY_REVOCATION
34 +
35 #else
36 #error SoC not defined
37 #endif
38 diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
39 index c7f8b3e..c973255 100644
40 --- a/arch/arm/include/asm/fsl_secure_boot.h
41 +++ b/arch/arm/include/asm/fsl_secure_boot.h
42 @@ -50,7 +50,7 @@
43 #endif
44
45 #if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) ||\
46 - defined(CONFIG_LS2085A)
47 + defined(CONFIG_LS2085A) || defined(CONFIG_LS1012A)
48 /* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit
49 * Similiarly for LS2080 and LS2085
50 */
51 @@ -81,6 +81,11 @@
52 #define CONFIG_BS_ADDR_FLASH 0x583900000
53 #define CONFIG_BS_HDR_ADDR_RAM 0xa3920000
54 #define CONFIG_BS_ADDR_RAM 0xa3900000
55 +#elif defined(CONFIG_LS1012A)
56 +#define CONFIG_BS_HDR_ADDR_FLASH 0x400c0000
57 +#define CONFIG_BS_ADDR_FLASH 0x40060000
58 +#define CONFIG_BS_HDR_ADDR_RAM 0xa0060000
59 +#define CONFIG_BS_ADDR_RAM 0xa0060000
60 #else
61 #define CONFIG_BS_HDR_ADDR_FLASH 0x600a0000
62 #define CONFIG_BS_ADDR_FLASH 0x60060000
63 diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
64 index f7b9bce..347b8c8 100644
65 --- a/board/freescale/ls1012ardb/ls1012ardb.c
66 +++ b/board/freescale/ls1012ardb/ls1012ardb.c
67 @@ -20,6 +20,7 @@
68 #include <environment.h>
69 #include <fsl_mmdc.h>
70 #include <netdev.h>
71 +#include <fsl_sec.h>
72
73 DECLARE_GLOBAL_DATA_PTR;
74
75 @@ -191,6 +192,10 @@ int board_init(void)
76 enable_layerscape_ns_access();
77 #endif
78
79 +#ifdef CONFIG_FSL_CAAM
80 + sec_init();
81 +#endif
82 +
83 return 0;
84 }
85
86 diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
87 new file mode 100644
88 index 0000000..92a95a8
89 --- /dev/null
90 +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
91 @@ -0,0 +1,10 @@
92 +CONFIG_ARM=y
93 +CONFIG_TARGET_LS1012ARDB=y
94 +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT,SECURE_BOOT"
95 +# CONFIG_CMD_IMLS is not set
96 +CONFIG_SYS_NS16550=y
97 +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
98 +CONFIG_OF_CONTROL=y
99 +CONFIG_DM=y
100 +CONFIG_SPI_FLASH=y
101 +CONFIG_DM_SPI=y
102 diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
103 index af3d33f..b40e02b 100644
104 --- a/include/configs/ls1012ardb.h
105 +++ b/include/configs/ls1012ardb.h
106 @@ -73,4 +73,6 @@
107 #define CONFIG_SYS_MEMTEST_START 0x80000000
108 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
109
110 +#define CONFIG_FSL_CAAM /* Enable CAAM */
111 +
112 #endif /* __LS1012ARDB_H__ */
113 --
114 1.7.9.5
115