target/linux/ar71xx/files/arch/mips/ar71xx/mach-pb42.c

   1 /*
   2  *  Atheros PB42 board support
   3  *
   4  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms of the GNU General Public License version 2 as published
   9  *  by the Free Software Foundation.
  10  */
  11
  12 #include <asm/mach-ar71xx/ar71xx.h>
  13
  14 #include "machtype.h"
  15 #include "devices.h"
  16 #include "dev-m25p80.h"
  17 #include "dev-gpio-buttons.h"
  18 #include "dev-pb42-pci.h"
  19 #include "dev-usb.h"
  20
  21 #define PB42_KEYS_POLL_INTERVAL         20      /* msecs */
  22 #define PB42_KEYS_DEBOUNCE_INTERVAL     (3 * PB42_KEYS_POLL_INTERVAL)
  23
  24 #define PB42_GPIO_BTN_SW4       8
  25 #define PB42_GPIO_BTN_SW5       3
  26
  27 static struct gpio_keys_button pb42_gpio_keys[] __initdata = {
  28         {
  29                 .desc           = "sw4",
  30                 .type           = EV_KEY,
  31                 .code           = BTN_0,
  32                 .debounce_interval = PB42_KEYS_DEBOUNCE_INTERVAL,
  33                 .gpio           = PB42_GPIO_BTN_SW4,
  34                 .active_low     = 1,
  35         }, {
  36                 .desc           = "sw5",
  37                 .type           = EV_KEY,
  38                 .code           = BTN_1,
  39                 .debounce_interval = PB42_KEYS_DEBOUNCE_INTERVAL,
  40                 .gpio           = PB42_GPIO_BTN_SW5,
  41                 .active_low     = 1,
  42         }
  43 };
  44
  45 #define PB42_WAN_PHYMASK        BIT(20)
  46 #define PB42_LAN_PHYMASK        (BIT(16) | BIT(17) | BIT(18) | BIT(19))
  47 #define PB42_MDIO_PHYMASK       (PB42_LAN_PHYMASK | PB42_WAN_PHYMASK)
  48
  49 static void __init pb42_init(void)
  50 {
  51         ar71xx_add_device_m25p80(NULL);
  52
  53         ar71xx_add_device_mdio(~PB42_MDIO_PHYMASK);
  54
  55         ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 0);
  56         ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  57         ar71xx_eth0_data.phy_mask = PB42_WAN_PHYMASK;
  58
  59         ar71xx_init_mac(ar71xx_eth1_data.mac_addr, ar71xx_mac_base, 1);
  60         ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  61         ar71xx_eth1_data.speed = SPEED_100;
  62         ar71xx_eth1_data.duplex = DUPLEX_FULL;
  63
  64         ar71xx_add_device_eth(0);
  65         ar71xx_add_device_eth(1);
  66
  67         ar71xx_register_gpio_keys_polled(-1, PB42_KEYS_POLL_INTERVAL,
  68                                          ARRAY_SIZE(pb42_gpio_keys),
  69                                          pb42_gpio_keys);
  70
  71         pb42_pci_init();
  72 }
  73
  74 MIPS_MACHINE(AR71XX_MACH_PB42, "PB42", "Atheros PB42", pb42_init);