target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h

   1 /*
   2  *  Atheros AR71xx built-in ethernet mac driver
   3  *
   4  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Based on Atheros' AG7100 driver
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #ifndef __AG71XX_H
  15 #define __AG71XX_H
  16
  17 #include <linux/kernel.h>
  18 #include <linux/version.h>
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/types.h>
  22 #include <linux/random.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/ethtool.h>
  27 #include <linux/etherdevice.h>
  28 #include <linux/if_vlan.h>
  29 #include <linux/phy.h>
  30 #include <linux/skbuff.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/workqueue.h>
  33
  34 #include <linux/bitops.h>
  35
  36 #include <asm/mach-ath79/ar71xx_regs.h>
  37 #include <asm/mach-ath79/ath79.h>
  38 #include <asm/mach-ath79/ag71xx_platform.h>
  39
  40 #define AG71XX_DRV_NAME         "ag71xx"
  41 #define AG71XX_DRV_VERSION      "0.5.35"
  42
  43 #define AG71XX_NAPI_WEIGHT      64
  44 #define AG71XX_OOM_REFILL       (1 + HZ/10)
  45
  46 #define AG71XX_INT_ERR  (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
  47 #define AG71XX_INT_TX   (AG71XX_INT_TX_PS)
  48 #define AG71XX_INT_RX   (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
  49
  50 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
  51 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
  52
  53 #define AG71XX_TX_MTU_LEN       1540
  54 #define AG71XX_RX_PKT_SIZE      \
  55         (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
  56
  57 #define AG71XX_TX_RING_SIZE_DEFAULT     64
  58 #define AG71XX_RX_RING_SIZE_DEFAULT     128
  59
  60 #define AG71XX_TX_RING_SIZE_MAX         256
  61 #define AG71XX_RX_RING_SIZE_MAX         256
  62
  63 #ifdef CONFIG_AG71XX_DEBUG
  64 #define DBG(fmt, args...)       pr_debug(fmt, ## args)
  65 #else
  66 #define DBG(fmt, args...)       do {} while (0)
  67 #endif
  68
  69 #define ag71xx_assert(_cond)                                            \
  70 do {                                                                    \
  71         if (_cond)                                                      \
  72                 break;                                                  \
  73         printk("%s,%d: assertion failed\n", __FILE__, __LINE__);        \
  74         BUG();                                                          \
  75 } while (0)
  76
  77 struct ag71xx_desc {
  78         u32     data;
  79         u32     ctrl;
  80 #define DESC_EMPTY      BIT(31)
  81 #define DESC_MORE       BIT(24)
  82 #define DESC_PKTLEN_M   0xfff
  83         u32     next;
  84         u32     pad;
  85 } __attribute__((aligned(4)));
  86
  87 struct ag71xx_buf {
  88         struct sk_buff          *skb;
  89         struct ag71xx_desc      *desc;
  90         dma_addr_t              dma_addr;
  91         unsigned long           timestamp;
  92 };
  93
  94 struct ag71xx_ring {
  95         struct ag71xx_buf       *buf;
  96         u8                      *descs_cpu;
  97         dma_addr_t              descs_dma;
  98         unsigned int            desc_size;
  99         unsigned int            curr;
 100         unsigned int            dirty;
 101         unsigned int            size;
 102 };
 103
 104 struct ag71xx_mdio {
 105         struct mii_bus          *mii_bus;
 106         int                     mii_irq[PHY_MAX_ADDR];
 107         void __iomem            *mdio_base;
 108         struct ag71xx_mdio_platform_data *pdata;
 109 };
 110
 111 struct ag71xx_int_stats {
 112         unsigned long           rx_pr;
 113         unsigned long           rx_be;
 114         unsigned long           rx_of;
 115         unsigned long           tx_ps;
 116         unsigned long           tx_be;
 117         unsigned long           tx_ur;
 118         unsigned long           total;
 119 };
 120
 121 struct ag71xx_napi_stats {
 122         unsigned long           napi_calls;
 123         unsigned long           rx_count;
 124         unsigned long           rx_packets;
 125         unsigned long           rx_packets_max;
 126         unsigned long           tx_count;
 127         unsigned long           tx_packets;
 128         unsigned long           tx_packets_max;
 129
 130         unsigned long           rx[AG71XX_NAPI_WEIGHT + 1];
 131         unsigned long           tx[AG71XX_NAPI_WEIGHT + 1];
 132 };
 133
 134 struct ag71xx_debug {
 135         struct dentry           *debugfs_dir;
 136
 137         struct ag71xx_int_stats int_stats;
 138         struct ag71xx_napi_stats napi_stats;
 139 };
 140
 141 struct ag71xx {
 142         void __iomem            *mac_base;
 143
 144         spinlock_t              lock;
 145         struct platform_device  *pdev;
 146         struct net_device       *dev;
 147         struct napi_struct      napi;
 148         u32                     msg_enable;
 149
 150         struct ag71xx_desc      *stop_desc;
 151         dma_addr_t              stop_desc_dma;
 152
 153         struct ag71xx_ring      rx_ring;
 154         struct ag71xx_ring      tx_ring;
 155
 156         struct mii_bus          *mii_bus;
 157         struct phy_device       *phy_dev;
 158         void                    *phy_priv;
 159
 160         unsigned int            link;
 161         unsigned int            speed;
 162         int                     duplex;
 163
 164         struct work_struct      restart_work;
 165         struct delayed_work     link_work;
 166         struct timer_list       oom_timer;
 167
 168 #ifdef CONFIG_AG71XX_DEBUG_FS
 169         struct ag71xx_debug     debug;
 170 #endif
 171 };
 172
 173 extern struct ethtool_ops ag71xx_ethtool_ops;
 174 void ag71xx_link_adjust(struct ag71xx *ag);
 175
 176 int ag71xx_mdio_driver_init(void) __init;
 177 void ag71xx_mdio_driver_exit(void);
 178
 179 int ag71xx_phy_connect(struct ag71xx *ag);
 180 void ag71xx_phy_disconnect(struct ag71xx *ag);
 181 void ag71xx_phy_start(struct ag71xx *ag);
 182 void ag71xx_phy_stop(struct ag71xx *ag);
 183
 184 static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
 185 {
 186         return ag->pdev->dev.platform_data;
 187 }
 188
 189 static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
 190 {
 191         return (desc->ctrl & DESC_EMPTY) != 0;
 192 }
 193
 194 static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 195 {
 196         return desc->ctrl & DESC_PKTLEN_M;
 197 }
 198
 199 /* Register offsets */
 200 #define AG71XX_REG_MAC_CFG1     0x0000
 201 #define AG71XX_REG_MAC_CFG2     0x0004
 202 #define AG71XX_REG_MAC_IPG      0x0008
 203 #define AG71XX_REG_MAC_HDX      0x000c
 204 #define AG71XX_REG_MAC_MFL      0x0010
 205 #define AG71XX_REG_MII_CFG      0x0020
 206 #define AG71XX_REG_MII_CMD      0x0024
 207 #define AG71XX_REG_MII_ADDR     0x0028
 208 #define AG71XX_REG_MII_CTRL     0x002c
 209 #define AG71XX_REG_MII_STATUS   0x0030
 210 #define AG71XX_REG_MII_IND      0x0034
 211 #define AG71XX_REG_MAC_IFCTL    0x0038
 212 #define AG71XX_REG_MAC_ADDR1    0x0040
 213 #define AG71XX_REG_MAC_ADDR2    0x0044
 214 #define AG71XX_REG_FIFO_CFG0    0x0048
 215 #define AG71XX_REG_FIFO_CFG1    0x004c
 216 #define AG71XX_REG_FIFO_CFG2    0x0050
 217 #define AG71XX_REG_FIFO_CFG3    0x0054
 218 #define AG71XX_REG_FIFO_CFG4    0x0058
 219 #define AG71XX_REG_FIFO_CFG5    0x005c
 220 #define AG71XX_REG_FIFO_RAM0    0x0060
 221 #define AG71XX_REG_FIFO_RAM1    0x0064
 222 #define AG71XX_REG_FIFO_RAM2    0x0068
 223 #define AG71XX_REG_FIFO_RAM3    0x006c
 224 #define AG71XX_REG_FIFO_RAM4    0x0070
 225 #define AG71XX_REG_FIFO_RAM5    0x0074
 226 #define AG71XX_REG_FIFO_RAM6    0x0078
 227 #define AG71XX_REG_FIFO_RAM7    0x007c
 228
 229 #define AG71XX_REG_TX_CTRL      0x0180
 230 #define AG71XX_REG_TX_DESC      0x0184
 231 #define AG71XX_REG_TX_STATUS    0x0188
 232 #define AG71XX_REG_RX_CTRL      0x018c
 233 #define AG71XX_REG_RX_DESC      0x0190
 234 #define AG71XX_REG_RX_STATUS    0x0194
 235 #define AG71XX_REG_INT_ENABLE   0x0198
 236 #define AG71XX_REG_INT_STATUS   0x019c
 237
 238 #define AG71XX_REG_FIFO_DEPTH   0x01a8
 239 #define AG71XX_REG_RX_SM        0x01b0
 240 #define AG71XX_REG_TX_SM        0x01b4
 241
 242 #define MAC_CFG1_TXE            BIT(0)  /* Tx Enable */
 243 #define MAC_CFG1_STX            BIT(1)  /* Synchronize Tx Enable */
 244 #define MAC_CFG1_RXE            BIT(2)  /* Rx Enable */
 245 #define MAC_CFG1_SRX            BIT(3)  /* Synchronize Rx Enable */
 246 #define MAC_CFG1_TFC            BIT(4)  /* Tx Flow Control Enable */
 247 #define MAC_CFG1_RFC            BIT(5)  /* Rx Flow Control Enable */
 248 #define MAC_CFG1_LB             BIT(8)  /* Loopback mode */
 249 #define MAC_CFG1_SR             BIT(31) /* Soft Reset */
 250
 251 #define MAC_CFG2_FDX            BIT(0)
 252 #define MAC_CFG2_CRC_EN         BIT(1)
 253 #define MAC_CFG2_PAD_CRC_EN     BIT(2)
 254 #define MAC_CFG2_LEN_CHECK      BIT(4)
 255 #define MAC_CFG2_HUGE_FRAME_EN  BIT(5)
 256 #define MAC_CFG2_IF_1000        BIT(9)
 257 #define MAC_CFG2_IF_10_100      BIT(8)
 258
 259 #define FIFO_CFG0_WTM           BIT(0)  /* Watermark Module */
 260 #define FIFO_CFG0_RXS           BIT(1)  /* Rx System Module */
 261 #define FIFO_CFG0_RXF           BIT(2)  /* Rx Fabric Module */
 262 #define FIFO_CFG0_TXS           BIT(3)  /* Tx System Module */
 263 #define FIFO_CFG0_TXF           BIT(4)  /* Tx Fabric Module */
 264 #define FIFO_CFG0_ALL   (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
 265                         | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
 266
 267 #define FIFO_CFG0_ENABLE_SHIFT  8
 268
 269 #define FIFO_CFG4_DE            BIT(0)  /* Drop Event */
 270 #define FIFO_CFG4_DV            BIT(1)  /* RX_DV Event */
 271 #define FIFO_CFG4_FC            BIT(2)  /* False Carrier */
 272 #define FIFO_CFG4_CE            BIT(3)  /* Code Error */
 273 #define FIFO_CFG4_CR            BIT(4)  /* CRC error */
 274 #define FIFO_CFG4_LM            BIT(5)  /* Length Mismatch */
 275 #define FIFO_CFG4_LO            BIT(6)  /* Length out of range */
 276 #define FIFO_CFG4_OK            BIT(7)  /* Packet is OK */
 277 #define FIFO_CFG4_MC            BIT(8)  /* Multicast Packet */
 278 #define FIFO_CFG4_BC            BIT(9)  /* Broadcast Packet */
 279 #define FIFO_CFG4_DR            BIT(10) /* Dribble */
 280 #define FIFO_CFG4_LE            BIT(11) /* Long Event */
 281 #define FIFO_CFG4_CF            BIT(12) /* Control Frame */
 282 #define FIFO_CFG4_PF            BIT(13) /* Pause Frame */
 283 #define FIFO_CFG4_UO            BIT(14) /* Unsupported Opcode */
 284 #define FIFO_CFG4_VT            BIT(15) /* VLAN tag detected */
 285 #define FIFO_CFG4_FT            BIT(16) /* Frame Truncated */
 286 #define FIFO_CFG4_UC            BIT(17) /* Unicast Packet */
 287
 288 #define FIFO_CFG5_DE            BIT(0)  /* Drop Event */
 289 #define FIFO_CFG5_DV            BIT(1)  /* RX_DV Event */
 290 #define FIFO_CFG5_FC            BIT(2)  /* False Carrier */
 291 #define FIFO_CFG5_CE            BIT(3)  /* Code Error */
 292 #define FIFO_CFG5_LM            BIT(4)  /* Length Mismatch */
 293 #define FIFO_CFG5_LO            BIT(5)  /* Length Out of Range */
 294 #define FIFO_CFG5_OK            BIT(6)  /* Packet is OK */
 295 #define FIFO_CFG5_MC            BIT(7)  /* Multicast Packet */
 296 #define FIFO_CFG5_BC            BIT(8)  /* Broadcast Packet */
 297 #define FIFO_CFG5_DR            BIT(9)  /* Dribble */
 298 #define FIFO_CFG5_CF            BIT(10) /* Control Frame */
 299 #define FIFO_CFG5_PF            BIT(11) /* Pause Frame */
 300 #define FIFO_CFG5_UO            BIT(12) /* Unsupported Opcode */
 301 #define FIFO_CFG5_VT            BIT(13) /* VLAN tag detected */
 302 #define FIFO_CFG5_LE            BIT(14) /* Long Event */
 303 #define FIFO_CFG5_FT            BIT(15) /* Frame Truncated */
 304 #define FIFO_CFG5_16            BIT(16) /* unknown */
 305 #define FIFO_CFG5_17            BIT(17) /* unknown */
 306 #define FIFO_CFG5_SF            BIT(18) /* Short Frame */
 307 #define FIFO_CFG5_BM            BIT(19) /* Byte Mode */
 308
 309 #define AG71XX_INT_TX_PS        BIT(0)
 310 #define AG71XX_INT_TX_UR        BIT(1)
 311 #define AG71XX_INT_TX_BE        BIT(3)
 312 #define AG71XX_INT_RX_PR        BIT(4)
 313 #define AG71XX_INT_RX_OF        BIT(6)
 314 #define AG71XX_INT_RX_BE        BIT(7)
 315
 316 #define MAC_IFCTL_SPEED         BIT(16)
 317
 318 #define MII_CFG_CLK_DIV_4       0
 319 #define MII_CFG_CLK_DIV_6       2
 320 #define MII_CFG_CLK_DIV_8       3
 321 #define MII_CFG_CLK_DIV_10      4
 322 #define MII_CFG_CLK_DIV_14      5
 323 #define MII_CFG_CLK_DIV_20      6
 324 #define MII_CFG_CLK_DIV_28      7
 325 #define MII_CFG_CLK_DIV_34      8
 326 #define MII_CFG_CLK_DIV_42      9
 327 #define MII_CFG_CLK_DIV_50      10
 328 #define MII_CFG_CLK_DIV_58      11
 329 #define MII_CFG_CLK_DIV_66      12
 330 #define MII_CFG_CLK_DIV_74      13
 331 #define MII_CFG_CLK_DIV_82      14
 332 #define MII_CFG_CLK_DIV_98      15
 333 #define MII_CFG_RESET           BIT(31)
 334
 335 #define MII_CMD_WRITE           0x0
 336 #define MII_CMD_READ            0x1
 337 #define MII_ADDR_SHIFT          8
 338 #define MII_IND_BUSY            BIT(0)
 339 #define MII_IND_INVALID         BIT(2)
 340
 341 #define TX_CTRL_TXE             BIT(0)  /* Tx Enable */
 342
 343 #define TX_STATUS_PS            BIT(0)  /* Packet Sent */
 344 #define TX_STATUS_UR            BIT(1)  /* Tx Underrun */
 345 #define TX_STATUS_BE            BIT(3)  /* Bus Error */
 346
 347 #define RX_CTRL_RXE             BIT(0)  /* Rx Enable */
 348
 349 #define RX_STATUS_PR            BIT(0)  /* Packet Received */
 350 #define RX_STATUS_OF            BIT(2)  /* Rx Overflow */
 351 #define RX_STATUS_BE            BIT(3)  /* Bus Error */
 352
 353 static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg)
 354 {
 355         switch (reg) {
 356         case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
 357         case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_TX_SM:
 358         case AG71XX_REG_MII_CFG:
 359                 break;
 360
 361         default:
 362                 BUG();
 363         }
 364 }
 365
 366 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
 367 {
 368         ag71xx_check_reg_offset(ag, reg);
 369
 370         __raw_writel(value, ag->mac_base + reg);
 371         /* flush write */
 372         (void) __raw_readl(ag->mac_base + reg);
 373 }
 374
 375 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
 376 {
 377         ag71xx_check_reg_offset(ag, reg);
 378
 379         return __raw_readl(ag->mac_base + reg);
 380 }
 381
 382 static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
 383 {
 384         void __iomem *r;
 385
 386         ag71xx_check_reg_offset(ag, reg);
 387
 388         r = ag->mac_base + reg;
 389         __raw_writel(__raw_readl(r) | mask, r);
 390         /* flush write */
 391         (void)__raw_readl(r);
 392 }
 393
 394 static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
 395 {
 396         void __iomem *r;
 397
 398         ag71xx_check_reg_offset(ag, reg);
 399
 400         r = ag->mac_base + reg;
 401         __raw_writel(__raw_readl(r) & ~mask, r);
 402         /* flush write */
 403         (void) __raw_readl(r);
 404 }
 405
 406 static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
 407 {
 408         ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
 409 }
 410
 411 static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
 412 {
 413         ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
 414 }
 415
 416 #ifdef CONFIG_AG71XX_AR8216_SUPPORT
 417 void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
 418 int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb,
 419                                 int pktlen);
 420 static inline int ag71xx_has_ar8216(struct ag71xx *ag)
 421 {
 422         return ag71xx_get_pdata(ag)->has_ar8216;
 423 }
 424 #else
 425 static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
 426                                            struct sk_buff *skb)
 427 {
 428 }
 429
 430 static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
 431                                               struct sk_buff *skb,
 432                                               int pktlen)
 433 {
 434         return 0;
 435 }
 436 static inline int ag71xx_has_ar8216(struct ag71xx *ag)
 437 {
 438         return 0;
 439 }
 440 #endif
 441
 442 #ifdef CONFIG_AG71XX_DEBUG_FS
 443 int ag71xx_debugfs_root_init(void);
 444 void ag71xx_debugfs_root_exit(void);
 445 int ag71xx_debugfs_init(struct ag71xx *ag);
 446 void ag71xx_debugfs_exit(struct ag71xx *ag);
 447 void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status);
 448 void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx);
 449 #else
 450 static inline int ag71xx_debugfs_root_init(void) { return 0; }
 451 static inline void ag71xx_debugfs_root_exit(void) {}
 452 static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; }
 453 static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {}
 454 static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag,
 455                                                    u32 status) {}
 456 static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag,
 457                                                     int rx, int tx) {}
 458 #endif /* CONFIG_AG71XX_DEBUG_FS */
 459
 460 void ag71xx_ar7240_start(struct ag71xx *ag);
 461 void ag71xx_ar7240_stop(struct ag71xx *ag);
 462 int ag71xx_ar7240_init(struct ag71xx *ag);
 463 void ag71xx_ar7240_cleanup(struct ag71xx *ag);
 464
 465 int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg);
 466 void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val);
 467
 468 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
 469                       unsigned reg_addr);
 470 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
 471                        unsigned reg_addr, u16 reg_val);
 472
 473 #endif /* _AG71XX_H */