ath79: Add support for OpenMesh OM5P
[openwrt/openwrt.git] / target / linux / ath79 / dts / ar7161_siemens_ws-ap3610.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "ar7100.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 compatible = "siemens,ws-ap3610", "qca,ar7161";
10 model = "Siemens WS-AP3610";
11
12 aliases {
13 led-boot = &led_power_green;
14 led-failsafe = &led_power_red;
15 led-running = &led_power_green;
16 led-upgrade = &led_power_red;
17 label-mac-device = &eth0;
18 };
19
20 extosc: ref {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-output-names = "ref";
24 clock-frequency = <40000000>;
25 };
26
27 leds {
28 compatible = "gpio-leds";
29
30 led_power_green: led_power_green {
31 label = "green:power";
32 gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
33 };
34
35 led_power_red: led_power_red {
36 label = "red:power";
37 gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
38 };
39
40 led_wlan5_blue {
41 label = "blue:wlan5";
42 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
43 linux,default-trigger = "phy0tpt";
44 };
45
46 led_wlan5_green {
47 label = "green:wlan5";
48 gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
49 };
50
51 led_wlan2_blue {
52 label = "blue:wlan2";
53 gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
54 linux,default-trigger = "phy1tpt";
55 };
56
57 led_wlan2_green {
58 label = "green:wlan2";
59 gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
60 };
61 };
62
63 keys {
64 compatible = "gpio-keys";
65
66 reset {
67 label = "reset";
68 linux,code = <KEY_RESTART>;
69 gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
70 };
71 };
72 };
73
74 &pcie0 {
75 status = "okay";
76 };
77
78 &uart {
79 status = "okay";
80 };
81
82 &mdio0 {
83 status = "okay";
84
85 phy0: ethernet-phy@0 {
86 /*
87 * When the compatible-is missing, PHY autodetection
88 * is performed, but the PHY-ID reads all 0xff.
89 *
90 * Linux does not create the device in this case,
91 * and the reset is never even de-asserted.
92 */
93 compatible = "ethernet-phy-id0143.bca2",
94 "ethernet-phy-ieee802.3-c22";
95 reg = <0>;
96
97 resets = <&rst 8>;
98 reset-names = "phy";
99 reset-assert-us = <10000>;
100 reset-deassert-us = <10000>;
101 };
102 };
103
104 &eth0 {
105 status = "okay";
106
107 phy-mode = "rgmii-id";
108 phy-handle = <&phy0>;
109 };
110
111 &spi {
112 status = "okay";
113
114 flash@0 {
115 compatible = "jedec,spi-nor";
116 reg = <0>;
117 spi-max-frequency = <25000000>;
118
119 partitions {
120 compatible = "fixed-partitions";
121 #address-cells = <1>;
122 #size-cells = <1>;
123
124 partition@0 {
125 label = "u-boot";
126 reg = <0x0 0x40000>;
127 read-only;
128 };
129
130 partition@40000 {
131 label = "u-boot-bak";
132 reg = <0x40000 0x40000>;
133 read-only;
134 };
135
136 partition@80000 {
137 compatible = "denx,uimage";
138 label = "firmware";
139 reg = <0x80000 0xe00000>;
140 };
141
142 partition@e80000 {
143 label = "cfg1";
144 reg = <0xe80000 0x40000>;
145 read-only;
146 };
147
148 partition@ec0000 {
149 label = "cfg2";
150 reg = <0xec0000 0x40000>;
151 read-only;
152 };
153
154 partition@f00000 {
155 label = "nvram1";
156 reg = <0xf00000 0x40000>;
157 read-only;
158 };
159
160 partition@f40000 {
161 label = "nvram2";
162 reg = <0xf40000 0x40000>;
163 read-only;
164 };
165
166 partition@f80000 {
167 label = "rsvd1";
168 reg = <0xf80000 0x40000>;
169 read-only;
170 };
171
172 partition@fc0000 {
173 label = "rsvd2";
174 reg = <0xfc0000 0x40000>;
175 read-only;
176 };
177 };
178 };
179 };