target/linux/ath79/dts/ar9344_wd_mynet-n750.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "ar9344.dtsi"
   4
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/input/input.h>
   7
   8 / {
   9         model = "Western Digital My Net N750";
  10         compatible = "wd,mynet-n750", "qca,ar9344";
  11
  12         chosen {
  13                 bootargs = "console=ttyS0,115200n8";
  14         };
  15
  16         aliases {
  17                 led-boot = &led_power;
  18                 led-failsafe = &led_power;
  19                 led-running = &led_power;
  20                 led-upgrade = &led_power;
  21         };
  22
  23         leds {
  24                 compatible = "gpio-leds";
  25
  26                 wifi {
  27                         label = "blue:wireless";
  28                         gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
  29                 };
  30
  31                 internet {
  32                         label = "blue:internet";
  33                         gpios = <&gpio 12 GPIO_ACTIVE_HIGH>;
  34                 };
  35
  36                 wps {
  37                         label = "blue:wps";
  38                         gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
  39                 };
  40
  41                 led_power: power {
  42                         label = "blue:power";
  43                         gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
  44                 };
  45         };
  46
  47         keys {
  48                 compatible = "gpio-keys";
  49
  50                 reset {
  51                         linux,code = <KEY_RESTART>;
  52                         gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
  53                 };
  54
  55                 wps {
  56                         linux,code = <KEY_WPS_BUTTON>;
  57                         gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
  58                 };
  59         };
  60 };
  61
  62 &ref {
  63         clock-frequency = <40000000>;
  64 };
  65
  66 &uart {
  67         status = "okay";
  68 };
  69
  70 &gpio {
  71         gpio_ext_lna0 {
  72                 gpio-hog;
  73                 gpios = <15 0>;
  74                 output-high;
  75                 line-name = "mynet-n750:ext:lna0";
  76         };
  77
  78         gpio_ext_lna1 {
  79                 gpio-hog;
  80                 gpios = <18 0>;
  81                 output-high;
  82                 line-name = "mynet-n750:ext:lna1";
  83         };
  84 };
  85
  86 &spi {
  87         status = "okay";
  88
  89         flash@0 {
  90                 compatible = "jedec,spi-nor";
  91                 reg = <0>;
  92                 spi-max-frequency = <25000000>;
  93
  94                 partitions {
  95                         compatible = "fixed-partitions";
  96                         #address-cells = <1>;
  97                         #size-cells = <1>;
  98
  99                         partition@0 {
 100                                 label = "bootloader";
 101                                 reg = <0x000000 0x40000>;
 102                                 read-only;
 103                         };
 104
 105                         partition@40000 {
 106                                 label = "bdcfg";
 107                                 reg = <0x040000 0x10000>;
 108                                 read-only;
 109                         };
 110
 111                         partition@50000 {
 112                                 label = "devdata";
 113                                 reg = <0x050000 0x10000>;
 114                                 read-only;
 115                         };
 116
 117                         partition@60000 {
 118                                 label = "devconf";
 119                                 reg = <0x060000 0x10000>;
 120                                 read-only;
 121                         };
 122
 123                         partition@70000 {
 124                                 compatible = "seama";
 125                                 label = "firmware";
 126                                 reg = <0x070000 0xf80000>;
 127                         };
 128
 129                         art: partition@ff0000 {
 130                                 label = "art";
 131                                 reg = <0xff0000 0x010000>;
 132                                 read-only;
 133                         };
 134                 };
 135         };
 136 };
 137
 138 &usb {
 139         #address-cells = <1>;
 140         #size-cells = <0>;
 141         status = "okay";
 142
 143         port@1 {
 144                 #address-cells = <1>;
 145                 #size-cells = <0>;
 146                 reg = <1>;
 147                 #trigger-source-cells = <0>;
 148
 149                 hub_port1: port@1 {
 150                         reg = <1>;
 151                         #trigger-source-cells = <0>;
 152                 };
 153
 154                 hub_port2: port@2 {
 155                         reg = <2>;
 156                         #trigger-source-cells = <0>;
 157                 };
 158         };
 159 };
 160
 161 &usb_phy {
 162         status = "okay";
 163 };
 164
 165 &pcie {
 166         status = "okay";
 167
 168         wifi@0,0 {
 169                 compatible = "pci168c,0033";
 170                 reg = <0x0000 0 0 0 0>;
 171                 qca,no-eeprom;
 172         };
 173 };
 174
 175 &wmac {
 176         status = "okay";
 177
 178         qca,no-eeprom;
 179 };
 180
 181 &mdio0 {
 182         status = "okay";
 183
 184         phy-mask = <0>;
 185
 186         switch0@1f {
 187                 compatible = "qca,ar8327";
 188                 reg = <0x1f>;
 189
 190                 qca,ar8327-initvals = <
 191                         0x04 0x07600000 /* PORT0 PAD MODE CTRL */
 192                         0x10 0x80000080 /* POWER_ON_STRAP */
 193                         0x50 0xc737c737 /* LED_CTRL0 */
 194                         0x54 0x00000000 /* LED_CTRL1 */
 195                         0x58 0x00000000 /* LED_CTRL2 */
 196                         0x5c 0x0030c300 /* LED_CTRL3 */
 197                         0x7c 0x0000007e /* PORT0_STATUS */
 198                         >;
 199         };
 200 };
 201
 202 &eth0 {
 203         status = "okay";
 204
 205         /* default for ar934x, except for 1000M */
 206         pll-data = <0x06000000 0x00000101 0x00001616>;
 207
 208         phy-mode = "rgmii";
 209         fixed-link {
 210                 speed = <1000>;
 211                 full-duplex;
 212         };
 213 };