target/linux/bcm53xx/patches-4.1/153-PCI-iproc-Add-iProc-PCIe-MSI-support.patch

   1 From c81922174d61127ff5baad6059ae148794c72276 Mon Sep 17 00:00:00 2001
   2 From: Ray Jui <rjui@broadcom.com>
   3 Date: Tue, 17 Nov 2015 13:14:37 -0800
   4 Subject: [PATCH 153/154] PCI: iproc: Add iProc PCIe MSI support
   5
   6 This patch adds PCIe MSI support for both PAXB and PAXC interfaces on
   7 all iProc based platforms
   8
   9 The iProc PCIe MSI support deploys an event queue based implementation.
  10 Each event queue is serviced by a GIC interrupt and can support up to 64
  11 MSI vectors. Host memory is allocated for the event queues, and each event
  12 queue consists of 64 word-sized entries. MSI data is written to the
  13 lower 16-bit of each entry, whereas the upper 16-bit of the entry is
  14 reserved for the controller for internal processing
  15
  16 Each event queue is tracked by a head pointer and tail pointer. Head
  17 pointer indicates the next entry in the event queue to be processed by
  18 the driver and is updated by the driver after processing is done.
  19 The controller uses the tail pointer as the next MSI data insertion
  20 point. The controller ensures MSI data is flushed to host memory before
  21 updating the tail pointer and then triggering the interrupt
  22
  23 MSI IRQ affinity is supported by evenly distributing the interrupts to
  24 each CPU core. MSI vector is moved from one GIC interrupt to another in
  25 order to steer to the target CPU
  26
  27 Therefore, the actual number of supported MSI vectors is:
  28
  29 M * 64 / N
  30
  31 where M denotes the number of GIC interrupts (event queues), and N
  32 denotes the number of CPU cores
  33
  34 This iProc event queue based MSI support should not be used with newer
  35 platforms with integrated MSI support in the GIC (e.g., giv2m or
  36 gicv3-its)
  37
  38 Signed-off-by: Ray Jui <rjui@broadcom.com>
  39 Reviewed-by: Anup Patel <anup.patel@broadcom.com>
  40 Reviewed-by: Vikram Prakash <vikramp@broadcom.com>
  41 Reviewed-by: Scott Branden <sbranden@broadcom.com>
  42 ---
  43  drivers/pci/host/Kconfig               |   9 +
  44  drivers/pci/host/Makefile              |   1 +
  45  drivers/pci/host/pcie-iproc-bcma.c     |   1 +
  46  drivers/pci/host/pcie-iproc-msi.c      | 675 +++++++++++++++++++++++++++++++++
  47  drivers/pci/host/pcie-iproc-platform.c |   1 +
  48  drivers/pci/host/pcie-iproc.c          |  26 ++
  49  drivers/pci/host/pcie-iproc.h          |  23 +-
  50  7 files changed, 734 insertions(+), 2 deletions(-)
  51  create mode 100644 drivers/pci/host/pcie-iproc-msi.c
  52
  53 --- a/drivers/pci/host/Kconfig
  54 +++ b/drivers/pci/host/Kconfig
  55 @@ -115,6 +115,15 @@ config PCIE_IPROC
  56           iProc family of SoCs. An appropriate bus interface driver also needs
  57           to be enabled
  58
  59 +config PCIE_IPROC_MSI
  60 +       bool "Broadcom iProc PCIe MSI support"
  61 +       depends on ARCH_BCM_IPROC && PCI_MSI
  62 +       select PCI_MSI_IRQ_DOMAIN
  63 +       default ARCH_BCM_IPROC
  64 +       help
  65 +         Say Y here if you want to enable MSI support for Broadcom's iProc
  66 +         PCIe controller
  67 +
  68  config PCIE_IPROC_PLATFORM
  69         tristate "Broadcom iProc PCIe platform bus driver"
  70         depends on ARCH_BCM_IPROC || (ARM && COMPILE_TEST)
  71 --- a/drivers/pci/host/Makefile
  72 +++ b/drivers/pci/host/Makefile
  73 @@ -14,5 +14,6 @@ obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
  74  obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
  75  obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
  76  obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
  77 +obj-$(CONFIG_PCIE_IPROC_MSI) += pcie-iproc-msi.o
  78  obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
  79  obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
  80 --- a/drivers/pci/host/pcie-iproc-bcma.c
  81 +++ b/drivers/pci/host/pcie-iproc-bcma.c
  82 @@ -55,6 +55,7 @@ static int iproc_pcie_bcma_probe(struct
  83         bcma_set_drvdata(bdev, pcie);
  84
  85         pcie->base = bdev->io_addr;
  86 +       pcie->base_addr = bdev->addr;
  87
  88         res_mem.start = bdev->addr_s[0];
  89         res_mem.end = bdev->addr_s[0] + SZ_128M - 1;
  90 --- /dev/null
  91 +++ b/drivers/pci/host/pcie-iproc-msi.c
  92 @@ -0,0 +1,675 @@
  93 +/*
  94 + * Copyright (C) 2015 Broadcom Corporation
  95 + *
  96 + * This program is free software; you can redistribute it and/or
  97 + * modify it under the terms of the GNU General Public License as
  98 + * published by the Free Software Foundation version 2.
  99 + *
 100 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 101 + * kind, whether express or implied; without even the implied warranty
 102 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 103 + * GNU General Public License for more details.
 104 + */
 105 +
 106 +#include <linux/interrupt.h>
 107 +#include <linux/irqchip/chained_irq.h>
 108 +#include <linux/irqdomain.h>
 109 +#include <linux/msi.h>
 110 +#include <linux/of_irq.h>
 111 +#include <linux/of_pci.h>
 112 +#include <linux/pci.h>
 113 +
 114 +#include "pcie-iproc.h"
 115 +
 116 +#define IPROC_MSI_INTR_EN_SHIFT        11
 117 +#define IPROC_MSI_INTR_EN              BIT(IPROC_MSI_INTR_EN_SHIFT)
 118 +#define IPROC_MSI_INT_N_EVENT_SHIFT    1
 119 +#define IPROC_MSI_INT_N_EVENT          BIT(IPROC_MSI_INT_N_EVENT_SHIFT)
 120 +#define IPROC_MSI_EQ_EN_SHIFT          0
 121 +#define IPROC_MSI_EQ_EN                BIT(IPROC_MSI_EQ_EN_SHIFT)
 122 +
 123 +#define IPROC_MSI_EQ_MASK              0x3f
 124 +
 125 +/* max number of GIC interrupts */
 126 +#define NR_HW_IRQS                     6
 127 +
 128 +/* number of entries in each event queue */
 129 +#define EQ_LEN                         64
 130 +
 131 +/* size of each event queue memory region */
 132 +#define EQ_MEM_REGION_SIZE             SZ_4K
 133 +
 134 +/* size of each MSI address region */
 135 +#define MSI_MEM_REGION_SIZE            SZ_4K
 136 +
 137 +enum iproc_msi_reg {
 138 +       IPROC_MSI_EQ_PAGE = 0,
 139 +       IPROC_MSI_EQ_PAGE_UPPER,
 140 +       IPROC_MSI_PAGE,
 141 +       IPROC_MSI_PAGE_UPPER,
 142 +       IPROC_MSI_CTRL,
 143 +       IPROC_MSI_EQ_HEAD,
 144 +       IPROC_MSI_EQ_TAIL,
 145 +       IPROC_MSI_INTS_EN,
 146 +       IPROC_MSI_REG_SIZE,
 147 +};
 148 +
 149 +struct iproc_msi;
 150 +
 151 +/**
 152 + * iProc MSI group
 153 + *
 154 + * One MSI group is allocated per GIC interrupt, serviced by one iProc MSI
 155 + * event queue
 156 + *
 157 + * @msi: pointer to iProc MSI data
 158 + * @gic_irq: GIC interrupt
 159 + * @eq: Event queue number
 160 + */
 161 +struct iproc_msi_grp {
 162 +       struct iproc_msi *msi;
 163 +       int gic_irq;
 164 +       unsigned int eq;
 165 +};
 166 +
 167 +/**
 168 + * iProc event queue based MSI
 169 + *
 170 + * Only meant to be used on platforms without MSI support integrated into the
 171 + * GIC
 172 + *
 173 + * @pcie: pointer to iProc PCIe data
 174 + * @reg_offsets: MSI register offsets
 175 + * @grps: MSI groups
 176 + * @nr_irqs: number of total interrupts connected to GIC
 177 + * @nr_cpus: number of toal CPUs
 178 + * @has_inten_reg: indicates the MSI interrupt enable register needs to be
 179 + * set explicitly (required for some legacy platforms)
 180 + * @bitmap: MSI vector bitmap
 181 + * @bitmap_lock: lock to protect access to the MSI bitmap
 182 + * @nr_msi_vecs: total number of MSI vectors
 183 + * @inner_domain: inner IRQ domain
 184 + * @msi_domain: MSI IRQ domain
 185 + * @nr_eq_region: required number of 4K aligned memory region for MSI event
 186 + * queues
 187 + * @nr_msi_region: required number of 4K aligned address region for MSI posted
 188 + * writes
 189 + * @eq_cpu: pointer to allocated memory region for MSI event queues
 190 + * @eq_dma: DMA address of MSI event queues
 191 + * @msi_addr: MSI address
 192 + */
 193 +struct iproc_msi {
 194 +       struct iproc_pcie *pcie;
 195 +       const u16 (*reg_offsets)[IPROC_MSI_REG_SIZE];
 196 +       struct iproc_msi_grp *grps;
 197 +       int nr_irqs;
 198 +       int nr_cpus;
 199 +       bool has_inten_reg;
 200 +       unsigned long *bitmap;
 201 +       struct mutex bitmap_lock;
 202 +       unsigned int nr_msi_vecs;
 203 +       struct irq_domain *inner_domain;
 204 +       struct irq_domain *msi_domain;
 205 +       unsigned int nr_eq_region;
 206 +       unsigned int nr_msi_region;
 207 +       void *eq_cpu;
 208 +       dma_addr_t eq_dma;
 209 +       phys_addr_t msi_addr;
 210 +};
 211 +
 212 +static const u16 iproc_msi_reg_paxb[NR_HW_IRQS][IPROC_MSI_REG_SIZE] = {
 213 +       { 0x200, 0x2c0, 0x204, 0x2c4, 0x210, 0x250, 0x254, 0x208 },
 214 +       { 0x200, 0x2c0, 0x204, 0x2c4, 0x214, 0x258, 0x25c, 0x208 },
 215 +       { 0x200, 0x2c0, 0x204, 0x2c4, 0x218, 0x260, 0x264, 0x208 },
 216 +       { 0x200, 0x2c0, 0x204, 0x2c4, 0x21c, 0x268, 0x26c, 0x208 },
 217 +       { 0x200, 0x2c0, 0x204, 0x2c4, 0x220, 0x270, 0x274, 0x208 },
 218 +       { 0x200, 0x2c0, 0x204, 0x2c4, 0x224, 0x278, 0x27c, 0x208 },
 219 +};
 220 +
 221 +static const u16 iproc_msi_reg_paxc[NR_HW_IRQS][IPROC_MSI_REG_SIZE] = {
 222 +       { 0xc00, 0xc04, 0xc08, 0xc0c, 0xc40, 0xc50, 0xc60 },
 223 +       { 0xc10, 0xc14, 0xc18, 0xc1c, 0xc44, 0xc54, 0xc64 },
 224 +       { 0xc20, 0xc24, 0xc28, 0xc2c, 0xc48, 0xc58, 0xc68 },
 225 +       { 0xc30, 0xc34, 0xc38, 0xc3c, 0xc4c, 0xc5c, 0xc6c },
 226 +};
 227 +
 228 +static inline u32 iproc_msi_read_reg(struct iproc_msi *msi,
 229 +                                    enum iproc_msi_reg reg,
 230 +                                    unsigned int eq)
 231 +{
 232 +       struct iproc_pcie *pcie = msi->pcie;
 233 +
 234 +       return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]);
 235 +}
 236 +
 237 +static inline void iproc_msi_write_reg(struct iproc_msi *msi,
 238 +                                      enum iproc_msi_reg reg,
 239 +                                      int eq, u32 val)
 240 +{
 241 +       struct iproc_pcie *pcie = msi->pcie;
 242 +
 243 +       writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]);
 244 +}
 245 +
 246 +static inline u32 hwirq_to_group(struct iproc_msi *msi, unsigned long hwirq)
 247 +{
 248 +       return (hwirq % msi->nr_irqs);
 249 +}
 250 +
 251 +static inline unsigned int iproc_msi_addr_offset(struct iproc_msi *msi,
 252 +                                                unsigned long hwirq)
 253 +{
 254 +       if (msi->nr_msi_region > 1)
 255 +               return hwirq_to_group(msi, hwirq) * MSI_MEM_REGION_SIZE;
 256 +       else
 257 +               return hwirq_to_group(msi, hwirq) * sizeof(u32);
 258 +}
 259 +
 260 +static inline unsigned int iproc_msi_eq_offset(struct iproc_msi *msi, u32 eq)
 261 +{
 262 +       if (msi->nr_eq_region > 1)
 263 +               return eq * EQ_MEM_REGION_SIZE;
 264 +       else
 265 +               return eq * EQ_LEN * sizeof(u32);
 266 +}
 267 +
 268 +static struct irq_chip iproc_msi_irq_chip = {
 269 +       .name = "iProc-MSI",
 270 +};
 271 +
 272 +static struct msi_domain_info iproc_msi_domain_info = {
 273 +       .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
 274 +               MSI_FLAG_PCI_MSIX,
 275 +       .chip = &iproc_msi_irq_chip,
 276 +};
 277 +
 278 +/*
 279 + * In iProc PCIe core, each MSI group is serviced by a GIC interrupt and a
 280 + * dedicated event queue. Each MSI group can support up to 64 MSI vectors
 281 + *
 282 + * The number of MSI groups varies between different iProc SoCs. The total
 283 + * number of CPU cores also varies. To support MSI IRQ affinity, we
 284 + * distribute GIC interrupts across all available CPUs. MSI vector is moved
 285 + * from one GIC interrupt to another to steer to the target CPU
 286 + *
 287 + * Assuming:
 288 + * - the number of MSI groups is M
 289 + * - the number of CPU cores is N
 290 + * - M is always a multiple of N
 291 + *
 292 + * Total number of raw MSI vectors = M * 64
 293 + * Total number of supported MSI vectors = (M * 64) / N
 294 + */
 295 +static inline int hwirq_to_cpu(struct iproc_msi *msi, unsigned long hwirq)
 296 +{
 297 +       return (hwirq % msi->nr_cpus);
 298 +}
 299 +
 300 +static inline unsigned long hwirq_to_canonical_hwirq(struct iproc_msi *msi,
 301 +                                                    unsigned long hwirq)
 302 +{
 303 +       return (hwirq - hwirq_to_cpu(msi, hwirq));
 304 +}
 305 +
 306 +static int iproc_msi_irq_set_affinity(struct irq_data *data,
 307 +                                     const struct cpumask *mask, bool force)
 308 +{
 309 +       struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
 310 +       int target_cpu = cpumask_first(mask);
 311 +       int curr_cpu;
 312 +
 313 +       curr_cpu = hwirq_to_cpu(msi, data->hwirq);
 314 +       if (curr_cpu == target_cpu)
 315 +               return IRQ_SET_MASK_OK_DONE;
 316 +
 317 +       /* steer MSI to the target CPU */
 318 +       data->hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq) + target_cpu;
 319 +
 320 +       return IRQ_SET_MASK_OK;
 321 +}
 322 +
 323 +static void iproc_msi_irq_compose_msi_msg(struct irq_data *data,
 324 +                                         struct msi_msg *msg)
 325 +{
 326 +       struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
 327 +       dma_addr_t addr;
 328 +
 329 +       addr = msi->msi_addr + iproc_msi_addr_offset(msi, data->hwirq);
 330 +       msg->address_lo = lower_32_bits(addr);
 331 +       msg->address_hi = upper_32_bits(addr);
 332 +       msg->data = data->hwirq;
 333 +}
 334 +
 335 +static struct irq_chip iproc_msi_bottom_irq_chip = {
 336 +       .name = "MSI",
 337 +       .irq_set_affinity = iproc_msi_irq_set_affinity,
 338 +       .irq_compose_msi_msg = iproc_msi_irq_compose_msi_msg,
 339 +};
 340 +
 341 +static int iproc_msi_irq_domain_alloc(struct irq_domain *domain,
 342 +                                     unsigned int virq, unsigned int nr_irqs,
 343 +                                     void *args)
 344 +{
 345 +       struct iproc_msi *msi = domain->host_data;
 346 +       int hwirq;
 347 +
 348 +       mutex_lock(&msi->bitmap_lock);
 349 +
 350 +       /* allocate 'nr_cpus' number of MSI vectors each time */
 351 +       hwirq = bitmap_find_next_zero_area(msi->bitmap, msi->nr_msi_vecs, 0,
 352 +                                          msi->nr_cpus, 0);
 353 +       if (hwirq < msi->nr_msi_vecs) {
 354 +               bitmap_set(msi->bitmap, hwirq, msi->nr_cpus);
 355 +       } else {
 356 +               mutex_unlock(&msi->bitmap_lock);
 357 +               return -ENOSPC;
 358 +       }
 359 +
 360 +       mutex_unlock(&msi->bitmap_lock);
 361 +
 362 +       irq_domain_set_info(domain, virq, hwirq, &iproc_msi_bottom_irq_chip,
 363 +                           domain->host_data, handle_simple_irq, NULL, NULL);
 364 +
 365 +       return 0;
 366 +}
 367 +
 368 +static void iproc_msi_irq_domain_free(struct irq_domain *domain,
 369 +                                     unsigned int virq, unsigned int nr_irqs)
 370 +{
 371 +       struct irq_data *data = irq_domain_get_irq_data(domain, virq);
 372 +       struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
 373 +       unsigned int hwirq;
 374 +
 375 +       mutex_lock(&msi->bitmap_lock);
 376 +
 377 +       hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq);
 378 +       bitmap_clear(msi->bitmap, hwirq, msi->nr_cpus);
 379 +
 380 +       mutex_unlock(&msi->bitmap_lock);
 381 +
 382 +       irq_domain_free_irqs_parent(domain, virq, nr_irqs);
 383 +}
 384 +
 385 +static const struct irq_domain_ops msi_domain_ops = {
 386 +       .alloc = iproc_msi_irq_domain_alloc,
 387 +       .free = iproc_msi_irq_domain_free,
 388 +};
 389 +
 390 +static inline u32 decode_msi_hwirq(struct iproc_msi *msi, u32 eq, u32 head)
 391 +{
 392 +       u32 *msg, hwirq;
 393 +       unsigned int offs;
 394 +
 395 +       offs = iproc_msi_eq_offset(msi, eq) + head * sizeof(u32);
 396 +       msg = (u32 *)(msi->eq_cpu + offs);
 397 +       hwirq = *msg & IPROC_MSI_EQ_MASK;
 398 +
 399 +       /*
 400 +        * Since we have multiple hwirq mapped to a single MSI vector,
 401 +        * now we need to derive the hwirq at CPU0. It can then be used to
 402 +        * mapped back to virq
 403 +        */
 404 +       return hwirq_to_canonical_hwirq(msi, hwirq);
 405 +}
 406 +
 407 +static void iproc_msi_handler(struct irq_desc *desc)
 408 +{
 409 +       struct irq_chip *chip = irq_desc_get_chip(desc);
 410 +       struct iproc_msi_grp *grp;
 411 +       struct iproc_msi *msi;
 412 +       struct iproc_pcie *pcie;
 413 +       u32 eq, head, tail, nr_events;
 414 +       unsigned long hwirq;
 415 +       int virq;
 416 +
 417 +       chained_irq_enter(chip, desc);
 418 +
 419 +       grp = irq_desc_get_handler_data(desc);
 420 +       msi = grp->msi;
 421 +       pcie = msi->pcie;
 422 +       eq = grp->eq;
 423 +
 424 +       /*
 425 +        * iProc MSI event queue is tracked by head and tail pointers. Head
 426 +        * pointer indicates the next entry (MSI data) to be consumed by SW in
 427 +        * the queue and needs to be updated by SW. iProc MSI core uses the
 428 +        * tail pointer as the next data insertion point
 429 +        *
 430 +        * Entries between head and tail pointers contain valid MSI data. MSI
 431 +        * data is guaranteed to be in the event queue memory before the tail
 432 +        * pointer is updated by the iProc MSI core
 433 +        */
 434 +       head = iproc_msi_read_reg(msi, IPROC_MSI_EQ_HEAD,
 435 +                                 eq) & IPROC_MSI_EQ_MASK;
 436 +       do {
 437 +               tail = iproc_msi_read_reg(msi, IPROC_MSI_EQ_TAIL,
 438 +                                         eq) & IPROC_MSI_EQ_MASK;
 439 +
 440 +               /*
 441 +                * Figure out total number of events (MSI data) to be
 442 +                * processed
 443 +                */
 444 +               nr_events = (tail < head) ?
 445 +                       (EQ_LEN - (head - tail)) : (tail - head);
 446 +               if (!nr_events)
 447 +                       break;
 448 +
 449 +               /* process all outstanding events */
 450 +               while (nr_events--) {
 451 +                       hwirq = decode_msi_hwirq(msi, eq, head);
 452 +                       virq = irq_find_mapping(msi->inner_domain, hwirq);
 453 +                       generic_handle_irq(virq);
 454 +
 455 +                       head++;
 456 +                       head %= EQ_LEN;
 457 +               }
 458 +
 459 +               /*
 460 +                * Now all outstanding events have been processed. Update the
 461 +                * head pointer
 462 +                */
 463 +               iproc_msi_write_reg(msi, IPROC_MSI_EQ_HEAD, eq, head);
 464 +
 465 +               /*
 466 +                * Now go read the tail pointer again to see if there are new
 467 +                * oustanding events that came in during the above window
 468 +                */
 469 +       } while (true);
 470 +
 471 +       chained_irq_exit(chip, desc);
 472 +}
 473 +
 474 +static void iproc_msi_enable(struct iproc_msi *msi)
 475 +{
 476 +       int i, eq;
 477 +       u32 val;
 478 +
 479 +       /* program memory region for each event queue */
 480 +       for (i = 0; i < msi->nr_eq_region; i++) {
 481 +               dma_addr_t addr = msi->eq_dma + (i * EQ_MEM_REGION_SIZE);
 482 +
 483 +               iproc_msi_write_reg(msi, IPROC_MSI_EQ_PAGE, i,
 484 +                                   lower_32_bits(addr));
 485 +               iproc_msi_write_reg(msi, IPROC_MSI_EQ_PAGE_UPPER, i,
 486 +                                   upper_32_bits(addr));
 487 +       }
 488 +
 489 +       /* program address region for MSI posted writes */
 490 +       for (i = 0; i < msi->nr_msi_region; i++) {
 491 +               phys_addr_t addr = msi->msi_addr + (i * MSI_MEM_REGION_SIZE);
 492 +
 493 +               iproc_msi_write_reg(msi, IPROC_MSI_PAGE, i,
 494 +                                   lower_32_bits(addr));
 495 +               iproc_msi_write_reg(msi, IPROC_MSI_PAGE_UPPER, i,
 496 +                                   upper_32_bits(addr));
 497 +       }
 498 +
 499 +       for (eq = 0; eq < msi->nr_irqs; eq++) {
 500 +               /* enable MSI event queue */
 501 +               val = IPROC_MSI_INTR_EN | IPROC_MSI_INT_N_EVENT |
 502 +                       IPROC_MSI_EQ_EN;
 503 +               iproc_msi_write_reg(msi, IPROC_MSI_CTRL, eq, val);
 504 +
 505 +               /*
 506 +                * Some legacy platforms require the MSI interrupt enable
 507 +                * register to be set explicitly
 508 +                */
 509 +               if (msi->has_inten_reg) {
 510 +                       val = iproc_msi_read_reg(msi, IPROC_MSI_INTS_EN, eq);
 511 +                       val |= BIT(eq);
 512 +                       iproc_msi_write_reg(msi, IPROC_MSI_INTS_EN, eq, val);
 513 +               }
 514 +       }
 515 +}
 516 +
 517 +static void iproc_msi_disable(struct iproc_msi *msi)
 518 +{
 519 +       u32 eq, val;
 520 +
 521 +       for (eq = 0; eq < msi->nr_irqs; eq++) {
 522 +               if (msi->has_inten_reg) {
 523 +                       val = iproc_msi_read_reg(msi, IPROC_MSI_INTS_EN, eq);
 524 +                       val &= ~BIT(eq);
 525 +                       iproc_msi_write_reg(msi, IPROC_MSI_INTS_EN, eq, val);
 526 +               }
 527 +
 528 +               val = iproc_msi_read_reg(msi, IPROC_MSI_CTRL, eq);
 529 +               val &= ~(IPROC_MSI_INTR_EN | IPROC_MSI_INT_N_EVENT |
 530 +                        IPROC_MSI_EQ_EN);
 531 +               iproc_msi_write_reg(msi, IPROC_MSI_CTRL, eq, val);
 532 +       }
 533 +}
 534 +
 535 +static int iproc_msi_alloc_domains(struct device_node *node,
 536 +                                  struct iproc_msi *msi)
 537 +{
 538 +       msi->inner_domain = irq_domain_add_linear(NULL, msi->nr_msi_vecs,
 539 +                                                 &msi_domain_ops, msi);
 540 +       if (!msi->inner_domain)
 541 +               return -ENOMEM;
 542 +
 543 +       msi->msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node),
 544 +                                                   &iproc_msi_domain_info,
 545 +                                                   msi->inner_domain);
 546 +       if (!msi->msi_domain) {
 547 +               irq_domain_remove(msi->inner_domain);
 548 +               return -ENOMEM;
 549 +       }
 550 +
 551 +       return 0;
 552 +}
 553 +
 554 +static void iproc_msi_free_domains(struct iproc_msi *msi)
 555 +{
 556 +       if (msi->msi_domain)
 557 +               irq_domain_remove(msi->msi_domain);
 558 +
 559 +       if (msi->inner_domain)
 560 +               irq_domain_remove(msi->inner_domain);
 561 +}
 562 +
 563 +static void iproc_msi_irq_free(struct iproc_msi *msi, unsigned int cpu)
 564 +{
 565 +       int i;
 566 +
 567 +       for (i = cpu; i < msi->nr_irqs; i += msi->nr_cpus) {
 568 +               irq_set_chained_handler_and_data(msi->grps[i].gic_irq,
 569 +                                                NULL, NULL);
 570 +       }
 571 +}
 572 +
 573 +static int iproc_msi_irq_setup(struct iproc_msi *msi, unsigned int cpu)
 574 +{
 575 +       int i, ret;
 576 +       cpumask_var_t mask;
 577 +       struct iproc_pcie *pcie = msi->pcie;
 578 +
 579 +       for (i = cpu; i < msi->nr_irqs; i += msi->nr_cpus) {
 580 +               irq_set_chained_handler_and_data(msi->grps[i].gic_irq,
 581 +                                                iproc_msi_handler,
 582 +                                                &msi->grps[i]);
 583 +               /* dedicate GIC interrupt to each CPU core */
 584 +               if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
 585 +                       cpumask_clear(mask);
 586 +                       cpumask_set_cpu(cpu, mask);
 587 +                       ret = irq_set_affinity(msi->grps[i].gic_irq, mask);
 588 +                       if (ret)
 589 +                               dev_err(pcie->dev,
 590 +                                       "failed to set affinity for IRQ%d\n",
 591 +                                       msi->grps[i].gic_irq);
 592 +                       free_cpumask_var(mask);
 593 +               } else {
 594 +                       dev_err(pcie->dev, "failed to alloc CPU mask\n");
 595 +                       ret = -EINVAL;
 596 +               }
 597 +
 598 +               if (ret) {
 599 +                       /* free all configured/unconfigured irqs */
 600 +                       iproc_msi_irq_free(msi, cpu);
 601 +                       return ret;
 602 +               }
 603 +       }
 604 +
 605 +       return 0;
 606 +}
 607 +
 608 +int iproc_msi_init(struct iproc_pcie *pcie, struct device_node *node)
 609 +{
 610 +       struct iproc_msi *msi;
 611 +       int i, ret;
 612 +       unsigned int cpu;
 613 +
 614 +       if (!of_device_is_compatible(node, "brcm,iproc-msi"))
 615 +               return -ENODEV;
 616 +
 617 +       if (!of_find_property(node, "msi-controller", NULL))
 618 +               return -ENODEV;
 619 +
 620 +       if (pcie->msi)
 621 +               return -EBUSY;
 622 +
 623 +       msi = devm_kzalloc(pcie->dev, sizeof(*msi), GFP_KERNEL);
 624 +       if (!msi)
 625 +               return -ENOMEM;
 626 +
 627 +       msi->pcie = pcie;
 628 +       pcie->msi = msi;
 629 +       msi->msi_addr = pcie->base_addr;
 630 +       mutex_init(&msi->bitmap_lock);
 631 +       msi->nr_cpus = num_possible_cpus();
 632 +
 633 +       msi->nr_irqs = of_irq_count(node);
 634 +       if (!msi->nr_irqs) {
 635 +               dev_err(pcie->dev, "found no MSI GIC interrupt\n");
 636 +               return -ENODEV;
 637 +       }
 638 +
 639 +       if (msi->nr_irqs > NR_HW_IRQS) {
 640 +               dev_warn(pcie->dev, "too many MSI GIC interrupts defined %d\n",
 641 +                        msi->nr_irqs);
 642 +               msi->nr_irqs = NR_HW_IRQS;
 643 +       }
 644 +
 645 +       if (msi->nr_irqs < msi->nr_cpus) {
 646 +               dev_err(pcie->dev,
 647 +                       "not enough GIC interrupts for MSI affinity\n");
 648 +               return -EINVAL;
 649 +       }
 650 +
 651 +       if (msi->nr_irqs % msi->nr_cpus != 0) {
 652 +               msi->nr_irqs -= msi->nr_irqs % msi->nr_cpus;
 653 +               dev_warn(pcie->dev, "Reducing number of interrupts to %d\n",
 654 +                        msi->nr_irqs);
 655 +       }
 656 +
 657 +       switch (pcie->type) {
 658 +       case IPROC_PCIE_PAXB:
 659 +               msi->reg_offsets = iproc_msi_reg_paxb;
 660 +               msi->nr_eq_region = 1;
 661 +               msi->nr_msi_region = 1;
 662 +               break;
 663 +       case IPROC_PCIE_PAXC:
 664 +               msi->reg_offsets = iproc_msi_reg_paxc;
 665 +               msi->nr_eq_region = msi->nr_irqs;
 666 +               msi->nr_msi_region = msi->nr_irqs;
 667 +               break;
 668 +       default:
 669 +               dev_err(pcie->dev, "incompatible iProc PCIe interface\n");
 670 +               return -EINVAL;
 671 +       }
 672 +
 673 +       if (of_find_property(node, "brcm,pcie-msi-inten", NULL))
 674 +               msi->has_inten_reg = true;
 675 +
 676 +       msi->nr_msi_vecs = msi->nr_irqs * EQ_LEN;
 677 +       msi->bitmap = devm_kcalloc(pcie->dev, BITS_TO_LONGS(msi->nr_msi_vecs),
 678 +                                  sizeof(*msi->bitmap), GFP_KERNEL);
 679 +       if (!msi->bitmap)
 680 +               return -ENOMEM;
 681 +
 682 +       msi->grps = devm_kcalloc(pcie->dev, msi->nr_irqs, sizeof(*msi->grps),
 683 +                                GFP_KERNEL);
 684 +       if (!msi->grps)
 685 +               return -ENOMEM;
 686 +
 687 +       for (i = 0; i < msi->nr_irqs; i++) {
 688 +               unsigned int irq = irq_of_parse_and_map(node, i);
 689 +
 690 +               if (!irq) {
 691 +                       dev_err(pcie->dev, "unable to parse/map interrupt\n");
 692 +                       ret = -ENODEV;
 693 +                       goto free_irqs;
 694 +               }
 695 +               msi->grps[i].gic_irq = irq;
 696 +               msi->grps[i].msi = msi;
 697 +               msi->grps[i].eq = i;
 698 +       }
 699 +
 700 +       /* reserve memory for event queue and make sure memories are zeroed */
 701 +       msi->eq_cpu = dma_zalloc_coherent(pcie->dev,
 702 +                                         msi->nr_eq_region * EQ_MEM_REGION_SIZE,
 703 +                                         &msi->eq_dma, GFP_KERNEL);
 704 +       if (!msi->eq_cpu) {
 705 +               ret = -ENOMEM;
 706 +               goto free_irqs;
 707 +       }
 708 +
 709 +       ret = iproc_msi_alloc_domains(node, msi);
 710 +       if (ret) {
 711 +               dev_err(pcie->dev, "failed to create MSI domains\n");
 712 +               goto free_eq_dma;
 713 +       }
 714 +
 715 +       for_each_online_cpu(cpu) {
 716 +               ret = iproc_msi_irq_setup(msi, cpu);
 717 +               if (ret)
 718 +                       goto free_msi_irq;
 719 +       }
 720 +
 721 +       iproc_msi_enable(msi);
 722 +
 723 +       return 0;
 724 +
 725 +free_msi_irq:
 726 +       for_each_online_cpu(cpu)
 727 +               iproc_msi_irq_free(msi, cpu);
 728 +       iproc_msi_free_domains(msi);
 729 +
 730 +free_eq_dma:
 731 +       dma_free_coherent(pcie->dev, msi->nr_eq_region * EQ_MEM_REGION_SIZE,
 732 +                         msi->eq_cpu, msi->eq_dma);
 733 +
 734 +free_irqs:
 735 +       for (i = 0; i < msi->nr_irqs; i++) {
 736 +               if (msi->grps[i].gic_irq)
 737 +                       irq_dispose_mapping(msi->grps[i].gic_irq);
 738 +       }
 739 +       pcie->msi = NULL;
 740 +       return ret;
 741 +}
 742 +EXPORT_SYMBOL(iproc_msi_init);
 743 +
 744 +void iproc_msi_exit(struct iproc_pcie *pcie)
 745 +{
 746 +       struct iproc_msi *msi = pcie->msi;
 747 +       unsigned int i, cpu;
 748 +
 749 +       if (!msi)
 750 +               return;
 751 +
 752 +       iproc_msi_disable(msi);
 753 +
 754 +       for_each_online_cpu(cpu)
 755 +               iproc_msi_irq_free(msi, cpu);
 756 +
 757 +       iproc_msi_free_domains(msi);
 758 +
 759 +       dma_free_coherent(pcie->dev, msi->nr_eq_region * EQ_MEM_REGION_SIZE,
 760 +                         msi->eq_cpu, msi->eq_dma);
 761 +
 762 +       for (i = 0; i < msi->nr_irqs; i++) {
 763 +               if (msi->grps[i].gic_irq)
 764 +                       irq_dispose_mapping(msi->grps[i].gic_irq);
 765 +       }
 766 +}
 767 +EXPORT_SYMBOL(iproc_msi_exit);
 768 --- a/drivers/pci/host/pcie-iproc-platform.c
 769 +++ b/drivers/pci/host/pcie-iproc-platform.c
 770 @@ -71,6 +71,7 @@ static int iproc_pcie_pltfm_probe(struct
 771                 dev_err(pcie->dev, "unable to map controller registers\n");
 772                 return -ENOMEM;
 773         }
 774 +       pcie->base_addr = reg.start;
 775
 776         if (of_property_read_bool(np, "brcm,pcie-ob")) {
 777                 u32 val;
 778 --- a/drivers/pci/host/pcie-iproc.c
 779 +++ b/drivers/pci/host/pcie-iproc.c
 780 @@ -440,6 +440,26 @@ static int iproc_pcie_map_ranges(struct
 781         return 0;
 782  }
 783
 784 +static int iproc_pcie_msi_enable(struct iproc_pcie *pcie)
 785 +{
 786 +       struct device_node *msi_node;
 787 +
 788 +       msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0);
 789 +       if (!msi_node)
 790 +               return -ENODEV;
 791 +
 792 +       /*
 793 +        * If another MSI controller is being used, the call below should fail
 794 +        * but that is okay
 795 +        */
 796 +       return iproc_msi_init(pcie, msi_node);
 797 +}
 798 +
 799 +static void iproc_pcie_msi_disable(struct iproc_pcie *pcie)
 800 +{
 801 +       iproc_msi_exit(pcie);
 802 +}
 803 +
 804  int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
 805  {
 806         int ret;
 807 @@ -506,6 +526,10 @@ int iproc_pcie_setup(struct iproc_pcie *
 808
 809         iproc_pcie_enable(pcie);
 810
 811 +       if (IS_ENABLED(CONFIG_PCI_MSI))
 812 +               if (iproc_pcie_msi_enable(pcie))
 813 +                       dev_info(pcie->dev, "not using iProc MSI\n");
 814 +
 815         pci_scan_child_bus(bus);
 816         pci_assign_unassigned_bus_resources(bus);
 817         pci_fixup_irqs(pci_common_swizzle, pcie->map_irq);
 818 @@ -530,6 +554,8 @@ int iproc_pcie_remove(struct iproc_pcie
 819         pci_stop_root_bus(pcie->root_bus);
 820         pci_remove_root_bus(pcie->root_bus);
 821
 822 +       iproc_pcie_msi_disable(pcie);
 823 +
 824         phy_power_off(pcie->phy);
 825         phy_exit(pcie->phy);
 826
 827 --- a/drivers/pci/host/pcie-iproc.h
 828 +++ b/drivers/pci/host/pcie-iproc.h
 829 @@ -41,6 +41,8 @@ struct iproc_pcie_ob {
 830         resource_size_t window_size;
 831  };
 832
 833 +struct iproc_msi;
 834 +
 835  /**
 836   * iProc PCIe device
 837   *
 838 @@ -48,19 +50,21 @@ struct iproc_pcie_ob {
 839   * @type: iProc PCIe interface type
 840   * @reg_offsets: register offsets
 841   * @base: PCIe host controller I/O register base
 842 + * @base_addr: PCIe host controller register base physical address
 843   * @sysdata: Per PCI controller data (ARM-specific)
 844   * @root_bus: pointer to root bus
 845   * @phy: optional PHY device that controls the Serdes
 846 - * @irqs: interrupt IDs
 847   * @map_irq: function callback to map interrupts
 848 - * @need_ob_cfg: indidates SW needs to configure the outbound mapping window
 849 + * @need_ob_cfg: indicates SW needs to configure the outbound mapping window
 850   * @ob: outbound mapping parameters
 851 + * @msi: MSI data
 852   */
 853  struct iproc_pcie {
 854         struct device *dev;
 855         enum iproc_pcie_type type;
 856         const u16 *reg_offsets;
 857         void __iomem *base;
 858 +       phys_addr_t base_addr;
 859  #ifdef CONFIG_ARM
 860         struct pci_sys_data sysdata;
 861  #endif
 862 @@ -69,9 +73,24 @@ struct iproc_pcie {
 863         int (*map_irq)(const struct pci_dev *, u8, u8);
 864         bool need_ob_cfg;
 865         struct iproc_pcie_ob ob;
 866 +       struct iproc_msi *msi;
 867  };
 868
 869  int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res);
 870  int iproc_pcie_remove(struct iproc_pcie *pcie);
 871
 872 +#ifdef CONFIG_PCI_MSI
 873 +int iproc_msi_init(struct iproc_pcie *pcie, struct device_node *node);
 874 +void iproc_msi_exit(struct iproc_pcie *pcie);
 875 +#else
 876 +static inline int iproc_msi_init(struct iproc_pcie *pcie,
 877 +                                struct device_node *node)
 878 +{
 879 +       return -ENODEV;
 880 +}
 881 +static void iproc_msi_exit(struct iproc_pcie *pcie)
 882 +{
 883 +}
 884 +#endif
 885 +
 886  #endif /* _PCIE_IPROC_H */