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cns3xxx: fix register for enabling MMC/SD pins
[openwrt/openwrt.git] / target / linux / cns3xxx / files / arch / arm / mach-cns3xxx / laguna.c
1 /*
2 * Gateworks Corporation Laguna Platform
3 *
4 * Copyright 2000 Deep Blue Solutions Ltd
5 * Copyright 2008 ARM Limited
6 * Copyright 2008 Cavium Networks
7 * Scott Shu
8 * Copyright 2010 MontaVista Software, LLC.
9 * Anton Vorontsov <avorontsov@mvista.com>
10 * Copyright 2011 Gateworks Corporation
11 * Chris Lang <clang@gateworks.com>
12 * Copyright 2012-2013 Gateworks Corporation
13 * Tim Harvey <tharvey@gateworks.com>
14 *
15 * This file is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License, Version 2, as
17 * published by the Free Software Foundation.
18 */
19
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/compiler.h>
23 #include <linux/io.h>
24 #include <linux/gpio.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/serial_core.h>
27 #include <linux/serial_8250.h>
28 #include <linux/platform_device.h>
29 #include <linux/mtd/mtd.h>
30 #include <linux/mtd/physmap.h>
31 #include <linux/mtd/partitions.h>
32 #include <linux/leds.h>
33 #include <linux/i2c.h>
34 #include <linux/i2c/at24.h>
35 #include <linux/i2c/pca953x.h>
36 #include <linux/spi/spi.h>
37 #include <linux/spi/flash.h>
38 #include <linux/if_ether.h>
39 #include <linux/pps-gpio.h>
40 #include <linux/usb/ehci_pdriver.h>
41 #include <linux/usb/ohci_pdriver.h>
42 #include <linux/clk-provider.h>
43 #include <linux/clkdev.h>
44 #include <linux/platform_data/cns3xxx.h>
45 #include <asm/setup.h>
46 #include <asm/mach-types.h>
47 #include <asm/mach/arch.h>
48 #include <asm/mach/map.h>
49 #include <asm/mach/time.h>
50 #include <mach/gpio.h>
51 #include "core.h"
52 #include "devices.h"
53 #include "cns3xxx.h"
54 #include "pm.h"
55
56 #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
57
58 // Config 1 Bitmap
59 #define ETH0_LOAD BIT(0)
60 #define ETH1_LOAD BIT(1)
61 #define ETH2_LOAD BIT(2)
62 #define SATA0_LOAD BIT(3)
63 #define SATA1_LOAD BIT(4)
64 #define PCM_LOAD BIT(5)
65 #define I2S_LOAD BIT(6)
66 #define SPI0_LOAD BIT(7)
67 #define SPI1_LOAD BIT(8)
68 #define PCIE0_LOAD BIT(9)
69 #define PCIE1_LOAD BIT(10)
70 #define USB0_LOAD BIT(11)
71 #define USB1_LOAD BIT(12)
72 #define USB1_ROUTE BIT(13)
73 #define SD_LOAD BIT(14)
74 #define UART0_LOAD BIT(15)
75 #define UART1_LOAD BIT(16)
76 #define UART2_LOAD BIT(17)
77 #define MPCI0_LOAD BIT(18)
78 #define MPCI1_LOAD BIT(19)
79 #define MPCI2_LOAD BIT(20)
80 #define MPCI3_LOAD BIT(21)
81 #define FP_BUT_LOAD BIT(22)
82 #define FP_BUT_HEADER_LOAD BIT(23)
83 #define FP_LED_LOAD BIT(24)
84 #define FP_LED_HEADER_LOAD BIT(25)
85 #define FP_TAMPER_LOAD BIT(26)
86 #define HEADER_33V_LOAD BIT(27)
87 #define SATA_POWER_LOAD BIT(28)
88 #define FP_POWER_LOAD BIT(29)
89 #define GPIO_HEADER_LOAD BIT(30)
90 #define GSP_BAT_LOAD BIT(31)
91
92 // Config 2 Bitmap
93 #define FAN_LOAD BIT(0)
94 #define SPI_FLASH_LOAD BIT(1)
95 #define NOR_FLASH_LOAD BIT(2)
96 #define GPS_LOAD BIT(3)
97 #define SUPPLY_5V_LOAD BIT(6)
98 #define SUPPLY_33V_LOAD BIT(7)
99
100 struct laguna_board_info {
101 char model[16];
102 u32 config_bitmap;
103 u32 config2_bitmap;
104 u8 nor_flash_size;
105 u8 spi_flash_size;
106 };
107
108 static struct laguna_board_info laguna_info __initdata;
109
110 /*
111 * NOR Flash
112 */
113 static struct mtd_partition laguna_nor_partitions[] = {
114 {
115 .name = "uboot",
116 .size = SZ_256K,
117 .offset = 0,
118 .mask_flags = MTD_WRITEABLE,
119 }, {
120 .name = "params",
121 .size = SZ_128K,
122 .offset = SZ_256K,
123 }, {
124 .name = "kernel",
125 .size = SZ_2M,
126 .offset = SZ_256K + SZ_128K,
127 }, {
128 .name = "rootfs",
129 .size = SZ_16M - SZ_256K - SZ_128K - SZ_2M,
130 .offset = SZ_256K + SZ_128K + SZ_2M,
131 },
132 };
133
134 static struct physmap_flash_data laguna_nor_pdata = {
135 .width = 2,
136 .parts = laguna_nor_partitions,
137 .nr_parts = ARRAY_SIZE(laguna_nor_partitions),
138 };
139
140 static struct resource laguna_nor_res = {
141 .start = CNS3XXX_FLASH_BASE,
142 .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
143 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
144 };
145
146 static struct platform_device laguna_nor_pdev = {
147 .name = "physmap-flash",
148 .id = 0,
149 .resource = &laguna_nor_res,
150 .num_resources = 1,
151 .dev = {
152 .platform_data = &laguna_nor_pdata,
153 },
154 };
155
156 /*
157 * SPI
158 */
159 static struct mtd_partition laguna_spi_partitions[] = {
160 {
161 .name = "uboot",
162 .size = SZ_256K,
163 .offset = 0,
164 .mask_flags = MTD_WRITEABLE,
165 }, {
166 .name = "params",
167 .size = SZ_256K,
168 .offset = SZ_256K,
169 }, {
170 .name = "kernel",
171 .size = SZ_1M + SZ_512K,
172 .offset = SZ_512K,
173 }, {
174 .name = "rootfs",
175 .size = SZ_16M - SZ_2M,
176 .offset = SZ_2M,
177 },
178 };
179
180 static struct flash_platform_data laguna_spi_pdata = {
181 .parts = laguna_spi_partitions,
182 .nr_parts = ARRAY_SIZE(laguna_spi_partitions),
183 };
184
185 static struct spi_board_info __initdata laguna_spi_devices[] = {
186 {
187 .modalias = "m25p80",
188 .platform_data = &laguna_spi_pdata,
189 .max_speed_hz = 50000000,
190 .bus_num = 1,
191 .chip_select = 0,
192 },
193 };
194
195 static struct resource laguna_spi_resource = {
196 .start = CNS3XXX_SSP_BASE + 0x40,
197 .end = CNS3XXX_SSP_BASE + 0x6f,
198 .flags = IORESOURCE_MEM,
199 };
200
201 static struct platform_device laguna_spi_controller = {
202 .name = "cns3xxx_spi",
203 .resource = &laguna_spi_resource,
204 .num_resources = 1,
205 };
206
207 /*
208 * LED's
209 */
210 static struct gpio_led laguna_gpio_leds[] = {
211 {
212 .name = "user1", /* Green Led */
213 .gpio = 115,
214 .active_low = 1,
215 },{
216 .name = "user2", /* Red Led */
217 .gpio = 114,
218 .active_low = 1,
219 },{
220 .name = "pwr1", /* Green Led */
221 .gpio = 116,
222 .active_low = 1,
223 },{
224 .name = "pwr2", /* Yellow Led */
225 .gpio = 117,
226 .active_low = 1,
227 },{
228 .name = "txd1", /* Green Led */
229 .gpio = 118,
230 .active_low = 1,
231 },{
232 .name = "txd2", /* Yellow Led */
233 .gpio = 119,
234 .active_low = 1,
235 },{
236 .name = "rxd1", /* Green Led */
237 .gpio = 120,
238 .active_low = 1,
239 },{
240 .name = "rxd2", /* Yellow Led */
241 .gpio = 121,
242 .active_low = 1,
243 },{
244 .name = "ser1", /* Green Led */
245 .gpio = 122,
246 .active_low = 1,
247 },{
248 .name = "ser2", /* Yellow Led */
249 .gpio = 123,
250 .active_low = 1,
251 },{
252 .name = "enet1", /* Green Led */
253 .gpio = 124,
254 .active_low = 1,
255 },{
256 .name = "enet2", /* Yellow Led */
257 .gpio = 125,
258 .active_low = 1,
259 },{
260 .name = "sig1_1", /* Green Led */
261 .gpio = 126,
262 .active_low = 1,
263 },{
264 .name = "sig1_2", /* Yellow Led */
265 .gpio = 127,
266 .active_low = 1,
267 },{
268 .name = "sig2_1", /* Green Led */
269 .gpio = 128,
270 .active_low = 1,
271 },{
272 .name = "sig2_2", /* Yellow Led */
273 .gpio = 129,
274 .active_low = 1,
275 },{
276 .name = "sig3_1", /* Green Led */
277 .gpio = 130,
278 .active_low = 1,
279 },{
280 .name = "sig3_2", /* Yellow Led */
281 .gpio = 131,
282 .active_low = 1,
283 },{
284 .name = "net1", /*Green Led */
285 .gpio = 109,
286 .active_low = 1,
287 },{
288 .name = "net2", /* Red Led */
289 .gpio = 110,
290 .active_low = 1,
291 },{
292 .name = "mod1", /* Green Led */
293 .gpio = 111,
294 .active_low = 1,
295 },{
296 .name = "mod2", /* Red Led */
297 .gpio = 112,
298 .active_low = 1,
299 },
300 };
301
302 static struct gpio_led_platform_data laguna_gpio_leds_data = {
303 .num_leds = 22,
304 .leds = laguna_gpio_leds,
305 };
306
307 static struct platform_device laguna_gpio_leds_device = {
308 .name = "leds-gpio",
309 .id = -1,
310 .dev.platform_data = &laguna_gpio_leds_data,
311 };
312
313 /*
314 * Ethernet
315 */
316 static struct cns3xxx_plat_info laguna_net_data = {
317 .ports = 0,
318 .phy = {
319 0,
320 1,
321 2,
322 },
323 };
324
325 static struct resource laguna_net_resource[] = {
326 {
327 .name = "eth0_mem",
328 .start = CNS3XXX_SWITCH_BASE,
329 .end = CNS3XXX_SWITCH_BASE + SZ_4K - 1,
330 .flags = IORESOURCE_MEM
331 }, {
332 .name = "eth_rx",
333 .start = IRQ_CNS3XXX_SW_R0RXC,
334 .end = IRQ_CNS3XXX_SW_R0RXC,
335 .flags = IORESOURCE_IRQ
336 }, {
337 .name = "eth_stat",
338 .start = IRQ_CNS3XXX_SW_STATUS,
339 .end = IRQ_CNS3XXX_SW_STATUS,
340 .flags = IORESOURCE_IRQ
341 }
342 };
343
344 static struct platform_device laguna_net_device = {
345 .name = "cns3xxx_eth",
346 .id = 0,
347 .resource = laguna_net_resource,
348 .num_resources = ARRAY_SIZE(laguna_net_resource),
349 .dev.platform_data = &laguna_net_data,
350 };
351
352 /*
353 * UART
354 */
355 static void __init laguna_early_serial_setup(void)
356 {
357 #ifdef CONFIG_SERIAL_8250_CONSOLE
358 static struct uart_port laguna_serial_port = {
359 .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
360 .mapbase = CNS3XXX_UART0_BASE,
361 .irq = IRQ_CNS3XXX_UART0,
362 .iotype = UPIO_MEM,
363 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
364 .regshift = 2,
365 .uartclk = 24000000,
366 .line = 0,
367 .type = PORT_16550A,
368 .fifosize = 16,
369 };
370
371 early_serial_setup(&laguna_serial_port);
372 #endif
373 }
374
375 static struct resource laguna_uart_resources[] = {
376 {
377 .start = CNS3XXX_UART0_BASE,
378 .end = CNS3XXX_UART0_BASE + SZ_4K - 1,
379 .flags = IORESOURCE_MEM
380 },{
381 .start = CNS3XXX_UART2_BASE,
382 .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
383 .flags = IORESOURCE_MEM
384 },{
385 .start = CNS3XXX_UART2_BASE,
386 .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
387 .flags = IORESOURCE_MEM
388 },
389 };
390
391 static struct plat_serial8250_port laguna_uart_data[] = {
392 {
393 .mapbase = (CNS3XXX_UART0_BASE),
394 .irq = IRQ_CNS3XXX_UART0,
395 .iotype = UPIO_MEM,
396 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP,
397 .regshift = 2,
398 .uartclk = 24000000,
399 .type = PORT_16550A,
400 },{
401 .mapbase = (CNS3XXX_UART1_BASE),
402 .irq = IRQ_CNS3XXX_UART1,
403 .iotype = UPIO_MEM,
404 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP,
405 .regshift = 2,
406 .uartclk = 24000000,
407 .type = PORT_16550A,
408 },{
409 .mapbase = (CNS3XXX_UART2_BASE),
410 .irq = IRQ_CNS3XXX_UART2,
411 .iotype = UPIO_MEM,
412 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP,
413 .regshift = 2,
414 .uartclk = 24000000,
415 .type = PORT_16550A,
416 },
417 { },
418 };
419
420 static struct platform_device laguna_uart = {
421 .name = "serial8250",
422 .id = PLAT8250_DEV_PLATFORM,
423 .dev.platform_data = laguna_uart_data,
424 .num_resources = 3,
425 .resource = laguna_uart_resources
426 };
427
428 /*
429 * USB
430 */
431 static struct resource cns3xxx_usb_ehci_resources[] = {
432 [0] = {
433 .start = CNS3XXX_USB_BASE,
434 .end = CNS3XXX_USB_BASE + SZ_16M - 1,
435 .flags = IORESOURCE_MEM,
436 },
437 [1] = {
438 .start = IRQ_CNS3XXX_USB_EHCI,
439 .flags = IORESOURCE_IRQ,
440 },
441 };
442
443 static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
444
445 static int csn3xxx_usb_power_on(struct platform_device *pdev)
446 {
447 /*
448 * EHCI and OHCI share the same clock and power,
449 * resetting twice would cause the 1st controller been reset.
450 * Therefore only do power up at the first up device, and
451 * power down at the last down device.
452 *
453 * Set USB AHB INCR length to 16
454 */
455 if (atomic_inc_return(&usb_pwr_ref) == 1) {
456 cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
457 cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
458 cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
459 __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
460 MISC_CHIP_CONFIG_REG);
461 }
462
463 return 0;
464 }
465
466 static void csn3xxx_usb_power_off(struct platform_device *pdev)
467 {
468 /*
469 * EHCI and OHCI share the same clock and power,
470 * resetting twice would cause the 1st controller been reset.
471 * Therefore only do power up at the first up device, and
472 * power down at the last down device.
473 */
474 if (atomic_dec_return(&usb_pwr_ref) == 0)
475 cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
476 }
477
478 static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
479 .power_on = csn3xxx_usb_power_on,
480 .power_off = csn3xxx_usb_power_off,
481 };
482
483 static struct platform_device cns3xxx_usb_ehci_device = {
484 .name = "ehci-platform",
485 .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
486 .resource = cns3xxx_usb_ehci_resources,
487 .dev = {
488 .dma_mask = &cns3xxx_usb_ehci_dma_mask,
489 .coherent_dma_mask = DMA_BIT_MASK(32),
490 .platform_data = &cns3xxx_usb_ehci_pdata,
491 },
492 };
493
494 static struct resource cns3xxx_usb_ohci_resources[] = {
495 [0] = {
496 .start = CNS3XXX_USB_OHCI_BASE,
497 .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
498 .flags = IORESOURCE_MEM,
499 },
500 [1] = {
501 .start = IRQ_CNS3XXX_USB_OHCI,
502 .flags = IORESOURCE_IRQ,
503 },
504 };
505
506 static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
507
508 static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
509 .num_ports = 1,
510 .power_on = csn3xxx_usb_power_on,
511 .power_off = csn3xxx_usb_power_off,
512 };
513
514 static struct platform_device cns3xxx_usb_ohci_device = {
515 .name = "ohci-platform",
516 .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
517 .resource = cns3xxx_usb_ohci_resources,
518 .dev = {
519 .dma_mask = &cns3xxx_usb_ohci_dma_mask,
520 .coherent_dma_mask = DMA_BIT_MASK(32),
521 .platform_data = &cns3xxx_usb_ohci_pdata,
522 },
523 };
524
525 static struct resource cns3xxx_usb_otg_resources[] = {
526 [0] = {
527 .start = CNS3XXX_USBOTG_BASE,
528 .end = CNS3XXX_USBOTG_BASE + SZ_16M - 1,
529 .flags = IORESOURCE_MEM,
530 },
531 [1] = {
532 .start = IRQ_CNS3XXX_USB_OTG,
533 .flags = IORESOURCE_IRQ,
534 },
535 };
536
537 static u64 cns3xxx_usb_otg_dma_mask = DMA_BIT_MASK(32);
538
539 static struct platform_device cns3xxx_usb_otg_device = {
540 .name = "dwc_otg",
541 .num_resources = ARRAY_SIZE(cns3xxx_usb_otg_resources),
542 .resource = cns3xxx_usb_otg_resources,
543 .dev = {
544 .dma_mask = &cns3xxx_usb_otg_dma_mask,
545 .coherent_dma_mask = DMA_BIT_MASK(32),
546 },
547 };
548
549 /*
550 * I2C
551 */
552 static struct resource laguna_i2c_resource[] = {
553 {
554 .start = CNS3XXX_SSP_BASE + 0x20,
555 .end = CNS3XXX_SSP_BASE + 0x3f,
556 .flags = IORESOURCE_MEM,
557 },{
558 .start = IRQ_CNS3XXX_I2C,
559 .flags = IORESOURCE_IRQ,
560 },
561 };
562
563 static struct platform_device laguna_i2c_controller = {
564 .name = "cns3xxx-i2c",
565 .num_resources = 2,
566 .resource = laguna_i2c_resource,
567 };
568
569 static struct memory_accessor *at24_mem_acc;
570
571 static void at24_setup(struct memory_accessor *mem_acc, void *context)
572 {
573 char buf[16];
574
575 at24_mem_acc = mem_acc;
576
577 /* Read MAC addresses */
578 if (at24_mem_acc->read(at24_mem_acc, buf, 0x100, 6) == 6)
579 memcpy(&laguna_net_data.hwaddr[0], buf, ETH_ALEN);
580 if (at24_mem_acc->read(at24_mem_acc, buf, 0x106, 6) == 6)
581 memcpy(&laguna_net_data.hwaddr[1], buf, ETH_ALEN);
582 if (at24_mem_acc->read(at24_mem_acc, buf, 0x10C, 6) == 6)
583 memcpy(&laguna_net_data.hwaddr[2], buf, ETH_ALEN);
584 if (at24_mem_acc->read(at24_mem_acc, buf, 0x112, 6) == 6)
585 memcpy(&laguna_net_data.hwaddr[3], buf, ETH_ALEN);
586
587 /* Read out Model Information */
588 if (at24_mem_acc->read(at24_mem_acc, buf, 0x130, 16) == 16)
589 memcpy(&laguna_info.model, buf, 16);
590 if (at24_mem_acc->read(at24_mem_acc, buf, 0x140, 1) == 1)
591 memcpy(&laguna_info.nor_flash_size, buf, 1);
592 if (at24_mem_acc->read(at24_mem_acc, buf, 0x141, 1) == 1)
593 memcpy(&laguna_info.spi_flash_size, buf, 1);
594 if (at24_mem_acc->read(at24_mem_acc, buf, 0x142, 4) == 4)
595 memcpy(&laguna_info.config_bitmap, buf, 4);
596 if (at24_mem_acc->read(at24_mem_acc, buf, 0x146, 4) == 4)
597 memcpy(&laguna_info.config2_bitmap, buf, 4);
598 };
599
600 static struct at24_platform_data laguna_eeprom_info = {
601 .byte_len = 1024,
602 .page_size = 16,
603 .flags = AT24_FLAG_READONLY,
604 .setup = at24_setup,
605 };
606
607 static struct pca953x_platform_data laguna_pca_data = {
608 .gpio_base = 100,
609 .irq_base = -1,
610 };
611
612 static struct pca953x_platform_data laguna_pca2_data = {
613 .gpio_base = 116,
614 .irq_base = -1,
615 };
616
617 static struct i2c_board_info __initdata laguna_i2c_devices[] = {
618 {
619 I2C_BOARD_INFO("pca9555", 0x23),
620 .platform_data = &laguna_pca_data,
621 },{
622 I2C_BOARD_INFO("pca9555", 0x27),
623 .platform_data = &laguna_pca2_data,
624 },{
625 I2C_BOARD_INFO("gsp", 0x29),
626 },{
627 I2C_BOARD_INFO ("24c08",0x50),
628 .platform_data = &laguna_eeprom_info,
629 },{
630 I2C_BOARD_INFO("ds1672", 0x68),
631 },
632 };
633
634 /*
635 * Watchdog
636 */
637
638 static struct resource laguna_watchdog_resources[] = {
639 [0] = {
640 .start = CNS3XXX_TC11MP_TWD_BASE + 0x100, // CPU0 watchdog
641 .end = CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1,
642 .flags = IORESOURCE_MEM,
643 },
644 };
645
646 static struct platform_device laguna_watchdog = {
647 .name = "mpcore_wdt",
648 .id = -1,
649 .num_resources = ARRAY_SIZE(laguna_watchdog_resources),
650 .resource = laguna_watchdog_resources,
651 };
652
653 /*
654 * GPS PPS
655 */
656 static struct pps_gpio_platform_data laguna_pps_data = {
657 .gpio_pin = 0,
658 .gpio_label = "GPS_PPS",
659 .assert_falling_edge = 0,
660 .capture_clear = 0,
661 };
662
663 static struct platform_device laguna_pps_device = {
664 .name = "pps-gpio",
665 .id = -1,
666 .dev.platform_data = &laguna_pps_data,
667 };
668
669 /*
670 * GPIO
671 */
672
673 static struct gpio laguna_gpio_gw2391[] = {
674 { 0, GPIOF_IN , "*GPS_PPS" },
675 { 1, GPIOF_IN , "*GSC_IRQ#" },
676 { 2, GPIOF_IN , "*USB_FAULT#" },
677 { 5, GPIOF_OUT_INIT_LOW , "*USB0_PCI_SEL" },
678 { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
679 { 7, GPIOF_OUT_INIT_LOW , "*USB1_PCI_SEL" },
680 { 8, GPIOF_OUT_INIT_HIGH, "*PERST#" },
681 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN#" },
682 { 100, GPIOF_IN , "*USER_PB#" },
683 { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
684 { 108, GPIOF_IN , "DIO0" },
685 { 109, GPIOF_IN , "DIO1" },
686 { 110, GPIOF_IN , "DIO2" },
687 { 111, GPIOF_IN , "DIO3" },
688 { 112, GPIOF_IN , "DIO4" },
689 };
690
691 static struct gpio laguna_gpio_gw2388[] = {
692 { 0, GPIOF_IN , "*GPS_PPS" },
693 { 1, GPIOF_IN , "*GSC_IRQ#" },
694 { 3, GPIOF_IN , "*USB_FAULT#" },
695 { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
696 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
697 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
698 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
699 { 100, GPIOF_OUT_INIT_HIGH, "*USER_PB#" },
700 { 108, GPIOF_IN , "DIO0" },
701 { 109, GPIOF_IN , "DIO1" },
702 { 110, GPIOF_IN , "DIO2" },
703 { 111, GPIOF_IN , "DIO3" },
704 { 112, GPIOF_IN , "DIO4" },
705 };
706
707 static struct gpio laguna_gpio_gw2387[] = {
708 { 0, GPIOF_IN , "*GPS_PPS" },
709 { 1, GPIOF_IN , "*GSC_IRQ#" },
710 { 2, GPIOF_IN , "*USB_FAULT#" },
711 { 5, GPIOF_OUT_INIT_LOW , "*USB_PCI_SEL" },
712 { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
713 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
714 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
715 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
716 { 100, GPIOF_IN , "*USER_PB#" },
717 { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
718 { 108, GPIOF_IN , "DIO0" },
719 { 109, GPIOF_IN , "DIO1" },
720 { 110, GPIOF_IN , "DIO2" },
721 { 111, GPIOF_IN , "DIO3" },
722 { 112, GPIOF_IN , "DIO4" },
723 { 113, GPIOF_IN , "DIO5" },
724 };
725
726 static struct gpio laguna_gpio_gw2385[] = {
727 { 0, GPIOF_IN , "*GSC_IRQ#" },
728 { 1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" },
729 { 2, GPIOF_IN , "*USB_HST_FAULT#" },
730 { 5, GPIOF_IN , "*USB_OTG_FAULT#" },
731 { 6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" },
732 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
733 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
734 { 9, GPIOF_OUT_INIT_LOW , "*SER_EN" },
735 { 10, GPIOF_IN, "*USER_PB#" },
736 { 11, GPIOF_OUT_INIT_HIGH, "*PERST#" },
737 { 100, GPIOF_IN , "*USER_PB#" },
738 { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" },
739 };
740
741 static struct gpio laguna_gpio_gw2384[] = {
742 { 0, GPIOF_IN , "*GSC_IRQ#" },
743 { 1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" },
744 { 2, GPIOF_IN , "*USB_HST_FAULT#" },
745 { 5, GPIOF_IN , "*USB_OTG_FAULT#" },
746 { 6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" },
747 { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
748 { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
749 { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
750 { 12, GPIOF_OUT_INIT_LOW , "J10_DIOLED0" },
751 { 13, GPIOF_OUT_INIT_HIGH, "*I2CMUX_RST#" },
752 { 14, GPIOF_OUT_INIT_LOW , "J10_DIOLED1" },
753 { 15, GPIOF_OUT_INIT_LOW , "J10_DIOLED2" },
754 { 100, GPIOF_IN , "*USER_PB#" },
755 { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" },
756 { 108, GPIOF_IN , "J9_DIOGSC0" },
757 };
758
759 static struct gpio laguna_gpio_gw2383[] = {
760 { 0, GPIOF_IN , "*GPS_PPS" },
761 { 1, GPIOF_IN , "*GSC_IRQ#" },
762 { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
763 { 3, GPIOF_IN , "GPIO0" },
764 { 8, GPIOF_IN , "GPIO1" },
765 { 100, GPIOF_IN , "DIO0" },
766 { 101, GPIOF_IN , "DIO1" },
767 { 108, GPIOF_IN , "*USER_PB#" },
768 };
769
770 static struct gpio laguna_gpio_gw2382[] = {
771 { 0, GPIOF_IN , "*GPS_PPS" },
772 { 1, GPIOF_IN , "*GSC_IRQ#" },
773 { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
774 { 3, GPIOF_IN , "GPIO0" },
775 { 4, GPIOF_IN , "GPIO1" },
776 { 9, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
777 { 10, GPIOF_OUT_INIT_HIGH, "*USB_PCI_SEL#" },
778 { 100, GPIOF_IN , "DIO0" },
779 { 101, GPIOF_IN , "DIO1" },
780 { 108, GPIOF_IN , "*USER_PB#" },
781 };
782
783 static struct gpio laguna_gpio_gw2380[] = {
784 { 0, GPIOF_IN , "*GPS_PPS" },
785 { 1, GPIOF_IN , "*GSC_IRQ#" },
786 { 3, GPIOF_IN , "GPIO0" },
787 { 8, GPIOF_IN , "GPIO1" },
788 { 100, GPIOF_IN , "DIO0" },
789 { 101, GPIOF_IN , "DIO1" },
790 { 102, GPIOF_IN , "DIO2" },
791 { 103, GPIOF_IN , "DIO3" },
792 { 108, GPIOF_IN , "*USER_PB#" },
793 };
794
795 /*
796 * Initialization
797 */
798 static void __init laguna_init(void)
799 {
800 struct clk *clk;
801 u32 __iomem *reg;
802
803 clk = clk_register_fixed_rate(NULL, "cpu", NULL,
804 CLK_IS_ROOT | CLK_IGNORE_UNUSED,
805 cns3xxx_cpu_clock() * (1000000 / 8));
806 clk_register_clkdev(clk, "cpu", NULL);
807
808 platform_device_register(&laguna_watchdog);
809
810 platform_device_register(&laguna_i2c_controller);
811
812 /* Set ext_int 0-3 drive strength to 21 mA */
813 reg = MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B;
814 *reg |= 0x300;
815
816 /* Enable SCL/SDA for I2C */
817 reg = MISC_GPIOB_PIN_ENABLE_REG;
818 *reg |= BIT(12) | BIT(13);
819
820 /* Enable MMC/SD pins */
821 *reg |= BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11);
822
823 cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
824 cns3xxx_pwr_power_up(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
825 cns3xxx_pwr_soft_rst(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C);
826
827 cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SPI_PCM_I2C));
828 cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SPI_PCM_I2C));
829
830 i2c_register_board_info(0, ARRAY_AND_SIZE(laguna_i2c_devices));
831
832 pm_power_off = cns3xxx_power_off;
833 }
834
835 static struct map_desc laguna_io_desc[] __initdata = {
836 {
837 .virtual = CNS3XXX_UART0_BASE_VIRT,
838 .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
839 .length = SZ_4K,
840 .type = MT_DEVICE,
841 },
842 };
843
844 static void __init laguna_map_io(void)
845 {
846 cns3xxx_map_io();
847 cns3xxx_pcie_iotable_init();
848 iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
849 laguna_early_serial_setup();
850 }
851
852 static int laguna_register_gpio(struct gpio *array, size_t num)
853 {
854 int i, err, ret;
855
856 ret = 0;
857 for (i = 0; i < num; i++, array++) {
858 const char *label = array->label;
859 if (label[0] == '*')
860 label++;
861 err = gpio_request_one(array->gpio, array->flags, label);
862 if (err)
863 ret = err;
864 else {
865 err = gpio_export(array->gpio, array->label[0] != '*');
866 }
867 }
868 return ret;
869 }
870
871 static int __init laguna_pcie_init(void)
872 {
873 if (!machine_is_gw2388())
874 return 0;
875
876 return cns3xxx_pcie_init();
877 }
878 subsys_initcall(laguna_pcie_init);
879
880 static int __init laguna_model_setup(void)
881 {
882 u32 __iomem *mem;
883 u32 reg;
884
885 if (!machine_is_gw2388())
886 return 0;
887
888 printk("Running on Gateworks Laguna %s\n", laguna_info.model);
889 cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
890 NR_IRQS_CNS3XXX);
891 cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
892 NR_IRQS_CNS3XXX + 32);
893
894 if (strncmp(laguna_info.model, "GW", 2) == 0) {
895 if (laguna_info.config_bitmap & ETH0_LOAD)
896 laguna_net_data.ports |= BIT(0);
897 if (laguna_info.config_bitmap & ETH1_LOAD)
898 laguna_net_data.ports |= BIT(1);
899 if (laguna_info.config_bitmap & ETH2_LOAD)
900 laguna_net_data.ports |= BIT(2);
901 if (laguna_net_data.ports)
902 platform_device_register(&laguna_net_device);
903
904 if ((laguna_info.config_bitmap & SATA0_LOAD) ||
905 (laguna_info.config_bitmap & SATA1_LOAD))
906 cns3xxx_ahci_init();
907
908 if (laguna_info.config_bitmap & (USB0_LOAD)) {
909 cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
910
911 /* DRVVBUS pins share with GPIOA */
912 mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0014);
913 reg = __raw_readl(mem);
914 reg |= 0x8;
915 __raw_writel(reg, mem);
916
917 /* Enable OTG */
918 mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0808);
919 reg = __raw_readl(mem);
920 reg &= ~(1 << 10);
921 __raw_writel(reg, mem);
922
923 platform_device_register(&cns3xxx_usb_otg_device);
924 }
925
926 if (laguna_info.config_bitmap & (USB1_LOAD)) {
927 platform_device_register(&cns3xxx_usb_ehci_device);
928 platform_device_register(&cns3xxx_usb_ohci_device);
929 }
930
931 if (laguna_info.config_bitmap & (SD_LOAD))
932 cns3xxx_sdhci_init();
933
934 if (laguna_info.config_bitmap & (UART0_LOAD))
935 laguna_uart.num_resources = 1;
936 if (laguna_info.config_bitmap & (UART1_LOAD))
937 laguna_uart.num_resources = 2;
938 if (laguna_info.config_bitmap & (UART2_LOAD))
939 laguna_uart.num_resources = 3;
940 platform_device_register(&laguna_uart);
941
942 if (laguna_info.config2_bitmap & (NOR_FLASH_LOAD)) {
943 switch (laguna_info.nor_flash_size) {
944 case 1:
945 laguna_nor_partitions[3].size = SZ_8M - SZ_256K - SZ_128K - SZ_2M;
946 laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_8M - 1;
947 break;
948 case 2:
949 laguna_nor_partitions[3].size = SZ_16M - SZ_256K - SZ_128K - SZ_2M;
950 laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_16M - 1;
951 break;
952 case 3:
953 laguna_nor_partitions[3].size = SZ_32M - SZ_256K - SZ_128K - SZ_2M;
954 laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_32M - 1;
955 break;
956 case 4:
957 laguna_nor_partitions[3].size = SZ_64M - SZ_256K - SZ_128K - SZ_2M;
958 laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_64M - 1;
959 break;
960 case 5:
961 laguna_nor_partitions[3].size = SZ_128M - SZ_256K - SZ_128K - SZ_2M;
962 laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_128M - 1;
963 break;
964 }
965 platform_device_register(&laguna_nor_pdev);
966 }
967
968 if (laguna_info.config2_bitmap & (SPI_FLASH_LOAD)) {
969 switch (laguna_info.spi_flash_size) {
970 case 1:
971 laguna_spi_partitions[3].size = SZ_4M - SZ_2M;
972 break;
973 case 2:
974 laguna_spi_partitions[3].size = SZ_8M - SZ_2M;
975 break;
976 case 3:
977 laguna_spi_partitions[3].size = SZ_16M - SZ_2M;
978 break;
979 case 4:
980 laguna_spi_partitions[3].size = SZ_32M - SZ_2M;
981 break;
982 case 5:
983 laguna_spi_partitions[3].size = SZ_64M - SZ_2M;
984 break;
985 }
986 spi_register_board_info(ARRAY_AND_SIZE(laguna_spi_devices));
987 }
988
989 if ((laguna_info.config_bitmap & SPI0_LOAD) ||
990 (laguna_info.config_bitmap & SPI1_LOAD))
991 platform_device_register(&laguna_spi_controller);
992
993 if (laguna_info.config2_bitmap & GPS_LOAD)
994 platform_device_register(&laguna_pps_device);
995
996 /*
997 * Do any model specific setup not known by the bitmap by matching
998 * the first 6 characters of the model name
999 */
1000
1001 if ( (strncmp(laguna_info.model, "GW2388", 6) == 0)
1002 || (strncmp(laguna_info.model, "GW2389", 6) == 0) )
1003 {
1004 // configure GPIO's
1005 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2388));
1006 // configure LED's
1007 laguna_gpio_leds_data.num_leds = 2;
1008 } else if (strncmp(laguna_info.model, "GW2387", 6) == 0) {
1009 // configure GPIO's
1010 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2387));
1011 // configure LED's
1012 laguna_gpio_leds_data.num_leds = 2;
1013 } else if (strncmp(laguna_info.model, "GW2385", 6) == 0) {
1014 // configure GPIO's
1015 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2385));
1016 // configure LED's
1017 laguna_gpio_leds[0].gpio = 115;
1018 laguna_gpio_leds[1].gpio = 12;
1019 laguna_gpio_leds[1].name = "red";
1020 laguna_gpio_leds[1].active_low = 0,
1021 laguna_gpio_leds[2].gpio = 14;
1022 laguna_gpio_leds[2].name = "green";
1023 laguna_gpio_leds[2].active_low = 0,
1024 laguna_gpio_leds[3].gpio = 15;
1025 laguna_gpio_leds[3].name = "blue";
1026 laguna_gpio_leds[3].active_low = 0,
1027 laguna_gpio_leds_data.num_leds = 4;
1028 } else if (strncmp(laguna_info.model, "GW2384", 6) == 0) {
1029 // configure GPIO's
1030 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2384));
1031 // configure LED's
1032 laguna_gpio_leds_data.num_leds = 1;
1033 } else if (strncmp(laguna_info.model, "GW2383", 6) == 0) {
1034 // configure GPIO's
1035 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2383));
1036 // configure LED's
1037 laguna_gpio_leds[0].gpio = 107;
1038 laguna_gpio_leds_data.num_leds = 1;
1039 } else if (strncmp(laguna_info.model, "GW2382", 6) == 0) {
1040 // configure GPIO's
1041 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2382));
1042 // configure LED's
1043 laguna_gpio_leds[0].gpio = 107;
1044 laguna_gpio_leds_data.num_leds = 1;
1045 } else if (strncmp(laguna_info.model, "GW2380", 6) == 0) {
1046 // configure GPIO's
1047 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2380));
1048 // configure LED's
1049 laguna_gpio_leds[0].gpio = 107;
1050 laguna_gpio_leds[1].gpio = 106;
1051 laguna_gpio_leds_data.num_leds = 2;
1052 } else if (strncmp(laguna_info.model, "GW2391", 6) == 0) {
1053 // configure GPIO's
1054 laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2391));
1055 // configure LED's
1056 laguna_gpio_leds_data.num_leds = 2;
1057 }
1058 platform_device_register(&laguna_gpio_leds_device);
1059 } else {
1060 // Do some defaults here, not sure what yet
1061 }
1062 return 0;
1063 }
1064 late_initcall(laguna_model_setup);
1065
1066 MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
1067 .smp = smp_ops(cns3xxx_smp_ops),
1068 .atag_offset = 0x100,
1069 .map_io = laguna_map_io,
1070 .init_irq = cns3xxx_init_irq,
1071 .init_time = cns3xxx_timer_init,
1072 .init_machine = laguna_init,
1073 .restart = cns3xxx_restart,
1074 MACHINE_END
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